T6B08

TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC

T6B08
ROW DRIVER FOR A DOT MATRIX LCD

The T6B08 is a 68-channel-output row driver for an STN dot

matrix LCD. The T6B08 features a −28-V LCD drive voltage.
The T6B08 is able to drive LCD panels with a duty ratio of up to
1/240. It is recommended for use with the T6B07.

Features
l Display duty application : to 1/240
l LCD drive signal : 68
l Data transfer : 1-bit bidirectional
(1) O68 ← O1
(2) O68 → O1
(3) O1 → O34, O68 → O35
l LCD drive voltage : −11 to −28 V (max −30 V)
l Operating voltage : 3.0 to 5.5 V
Weight: 1.45 g (typ.)
l Operating temperature : −20 to 75°C
l LCD drive output resistance : 1.2 kΩ (max) (12.8 V, 1/9 bias)
l Display-off function : When/
l DSPOF is L, all LCD drive outputs (O1 to O68) remain at the VDD level.
l LCD drive output timing : Change on falling edge of LP

Block Diagram

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Pin Assignment

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Pin Functions

Pin Name I/O Functions Level

O1 to O68 Output Output for LCD drive signal VDD to V5

DIO1, DIO2 I/O Input / output for shift data
(Shift Clock Pulse)
LP Input
Input for shift clock pulse
(Frame)
FR Input
Input for frame signal
(Dual Mode)
DUAL Input
Terminal for dual input mode or single input mode select
(Direction) VDD to VSS
DIR Input
Input for data flow direction select
(Terminal Switch)
TSW Input When tied to VSS: (O1 to O68) output on the rising edge of LP
When tied to VDD: (O1 to O68) output on the falling edge of LP
(Display Off)
/ DSPOF Input / DSPOF = L : Display−off mode, (O1 to O68) remain at the VDD level.
/ DSPOF = H : Display−on mode, (O1 to O68) are operational.
VDD ― Power supply for internal logic (5 V)
VSS ― Power supply for internal logic (0 V)
V1 ― Power supply for LCD drive circuit
―
V4 ― Power supply for LCD drive circuit
V5 ― Power supply for LCD drive circuit

Relation Between FR, Data Input and Output Level

FR Data Input (DIO1, DIO2) / DSPOF Output Level

L L H V1
L H H V5
H L H V4
H H H VDD
* * L VDD

*: Don’t Care

Data Input Format

Data Input
DUAL DIR Data Flow
DIO1 DIO2
O1 → O34
VDD VDD IN IN
O68 → O35
VSS VDD O1 → O68 IN OUT
VDD VSS
O68 → O1 OUT IN
VSS VSS

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Timing Diagram

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Absolute Maximum Ratings
(Ensure that the Following Conditions are Maintained, VDD ≥ V1 ≥ V4 ≥ V5, VSS = 0)

Item Symbol Pin Name Rating Unit

Supply Voltage 1 VDD VDD −0.3 to 7.0 V

V1 V1
Supply Voltage 2 V4 V4 VDD − 30.0 to VDD + 0.3 V
V5 V5
Input Voltage VIN (Note 1) −0.3 to VDD + 0.3 V
Operating Temperature Topr ― −20 to 75 °C
Storage Temperature Tstg ― −55 to 125 °C

Note 1: LP, FR, / DSPOF, TSW, DUAL, DIR, DIO1, DIO2

Electrical Characteristics
DC Characteristics
Test Conditions (1) Unless Otherwise Noted, VSS = 0 V, VDD = 4.5 to 5.5 V,
V5 = (VDD − 28) to (VDD − 11) V,
Ta = −20 to 75°C
Test
Item Symbol Cir- Test Condition Min Typ. Max Unit Pin Name
cuit
Supply Voltage 1 ― ― ― 4.5 5.0 5.5 V VDD
VDD VDD
Supply Voltage 2 ― ― ― ― V V5
−28 −11
VDD LP, FR,
H Level VIH ― ― VDD
−0.8 / DSPOF,
Input
― V TSW, DUAL,
voltage
L Level VIL ― 0 ― 0.8 DIR, DIO1,
DIO2
VDD
H Level VOH IOH = −0.5 mA ― VDD
Output −0.5
― V DIO1, DIO2
voltage
L Level VOL IOL = 0.5 mA 0 ― 0.5

H Level ROH VOUT = VDD − 0.5 V (Note 2) ― 0.65 1.2

Output ROM VOUT = V1 ± 0.5 V (Note 2) ― 0.65 1.2

M Level ― KΩ O1 to O68
Resistance ROM VOUT = V4 ± 0.5 V (Note 2) ― 0.65 1.2
L Level ROL VOUT = V5 + 0.5 V (Note 2) ― 0.65 1.2
VDD = 5.5 V
V5 = −22.5 V
fFR = 35.5 Hz
Current Consumption ISS ― ― 2.0 4.0 µA VSS
fLP = 7.1 kHz
fDIO = 71 Hz
VIH = 5.5 V, VIL = 0 V

Note 2: VDD = 5.0 V, V5 = −7.8 V, V1 = VDD − 1 / 9 (VDD −V5), V4 = VDD − 8 / 9 (VDD − V5)

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Test Conditions (2) Unless Otherwise Noted, VSS = 0 V, VDD = 3.0 to 5.5 V,
V5 = (VDD − 28) to (VDD − 11) V,
Ta = −20 to 75°C
Test
Item Symbol Cir- Test Condition Min Typ. Max Unit Pin Name
cuit
Supply Voltage 1 ― ― ― 3.0 3.3 5.5 V VDD
VDD VDD
Supply Voltage 2 ― ― ― ― V V5
−28 −11
VDD LP, FR,
H Level VIH ― ― VDD
−0.6 / DSPOF,
Input
― V TSW, DUAL,
voltage
L Level VIL ― 0 ― 0.6 DIR, DIO1,
DIO2
VDD
H Level VOH IOH = −0.5 mA ― VDD
Output −0.5
― V DIO1, DIO2
voltage
L Level VOL IOL = 0.5 mA 0 ― 0.5

H Level ROH VOUT = VDD − 0.5 V (Note 3) ― 0.65 1.2

Output ROM VOUT = V1 ± 0.5 V (Note 3) ― 0.65 1.2

M Level ― kΩ O1 to O68
Resistance ROM VOUT = V4 ± 0.5 V (Note 3) ― 0.65 1.2
L Level ROL VOUT = V5 + 0.5 V (Note 3) ― 0.65 1.2
VDD = 5.5 V
V5 = −22.5 V
fFR = 35.5 Hz
Current Consumption ISS ― ― 2.0 4.0 µA VSS
fLP = 7.1 kHz
fDIO = 71 Hz
VIH = 5.5 V, VIL = 0 V

Note 3: VDD = 3.0 V, V5 = −9.8 V, V1 = VDD − 1 / 9 (VDD − V5), V4 = VDD − 8 / 9 (VDD − V5)

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AC Characteristics

Test Conditions (1)

(VSS = 0 V, VDD = 4.5 to 5.5 V, V5 = (VDD − 28) to (VDD − 11) V, Ta = −20 to 75°C)

Item Symbol Test Condition Min Max Unit

SCP Pulse Width H tCWH LP 40 ― ns

SCP Pulse Width L tCWL LP 1 ― µs
Input Rise / Fall Time tr, tf LP, FR, DIO1, DIO2 ― (Note 6) ns
Data Set−up Time tDSU DIO1, DIO2 40 ― ns
Data Hold Time tDHD DIO1, DIO2 40 ― ns
Output Data Delay Time A (Note 5) tpdA DIO1, DIO2 500 ― ns
Output Data Delay Time B (Note 5) tpdB DIO1, DIO2 ― 1 µs

Test Conditions (2)

(VSS = 0 V, VDD = 3.0 to 5.5 V, V5 = (VDD − 28) to (VDD − 11) V, Ta = −20 to 75°C)

Item Symbol Test Condition Min Max Unit

SCP Pulse Width H tCWH LP 50 ― ns

SCP Pulse Width L tCWL LP 1 ― µs
Input Rise / Fall Time tr, tf LP, FR, DIO1, DIO2 ― (Note 6) ns
Data Set−up Time tDSU DIO1, DIO2 50 ― ns
Data Hold Time tDHD DIO1, DIO2 50 ― ns
Output Data Delay Time A (Note 5) tpdA DIO1, DIO2 700 ― ns
Output Data Delay Time B (Note 5) tpdB DIO1, DIO2 ― 1 µs

Note 5: CL = 10 pF
Note 6: tr, tf ≤ (tC − tCWH − tCWL) / 2 or tr, tf ≤ 50 ns

Note: Insert the bypass capacitor (0.1 µF) between VDD and VSS to decrease the power supply noise.
Place the bypass capacitor as close to the LSI as possible.

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Package Dimensions

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RESTRICTIONS ON PRODUCT USE 000707EBA

· TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical
stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of
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such TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as
set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and
conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability
Handbook” etc..

· The TOSHIBA products listed in this document are intended for usage in general electronics applications
(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances,
etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires
extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or
bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or
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· The information contained herein is presented only as a guide for the applications of our products. No
responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other
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any intellectual property or other rights of TOSHIBA CORPORATION or others.

· The information contained herein is subject to change without notice.

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