ATmega48PA/88PA/168PA/328P

Figure 23-1. Analog to Digital Converter Block Schematic Operation,

ADC CONVERSION
COMPLETE IRQ

8-BIT DATA BUS

ADIE
ADIF
15 0
ADC MULTIPLEXER ADC CTRL. & STATUS ADC DATA REGISTER
SELECT (ADMUX) REGISTER (ADCSRA) (ADCH/ADCL)

REFS1

ADLAR

MUX3

MUX2

MUX1

MUX0
REFS0

ADPS2

ADPS1

ADPS0
ADEN

ADSC

ADFR

ADIF

ADC[9:0]
MUX DECODER
PRESCALER

CHANNEL SELECTION
CONVERSION LOGIC
AVCC

INTERNAL 1.1V
REFERENCE SAMPLE & HOLD
COMPARATOR
AREF
10-BIT DAC -
+

TEMPERATURE
SENSOR

GND

BANDGAP
REFERENCE

ADC7

INPUT ADC MULTIPLEXER

ADC6
MUX OUTPUT

ADC5

ADC4

ADC3

ADC2

ADC1

ADC0

The analog input channel is selected by writing to the MUX bits in ADMUX. Any of the ADC input
pins, as well as GND and a fixed bandgap voltage reference, can be selected as single ended
inputs to the ADC. The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. Volt-
age reference and input channel selections will not go into effect until ADEN is set. The ADC
does not consume power when ADEN is cleared, so it is recommended to switch off the ADC
before entering power saving sleep modes.
The ADC generates a 10-bit result which is presented in the ADC Data Registers, ADCH and
ADCL. By default, the result is presented right adjusted, but can optionally be presented left
adjusted by setting the ADLAR bit in ADMUX.
If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read
ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the content of the Data
Registers belongs to the same conversion. Once ADCL is read, ADC access to Data Registers
is blocked. This means that if ADCL has been read, and a conversion completes before ADCH is

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read, neither register is updated and the result from the conversion is lost. When ADCH is read,
ADC access to the ADCH and ADCL Registers is re-enabled.
The ADC has its own interrupt which can be triggered when a conversion completes. When ADC
access to the Data Registers is prohibited between reading of ADCH and ADCL, the interrupt
will trigger even if the result is lost.

23.3 Starting a Conversion

A single conversion is started by disabling the Power Reduction ADC bit, PRADC, in ”Minimizing
Power Consumption” on page 42 by writing a logical zero to it and writing a logical one to the
ADC Start Conversion bit, ADSC. This bit stays high as long as the conversion is in progress
and will be cleared by hardware when the conversion is completed. If a different data channel is
selected while a conversion is in progress, the ADC will finish the current conversion before per-
forming the channel change.
Alternatively, a conversion can be triggered automatically by various sources. Auto Triggering is
enabled by setting the ADC Auto Trigger Enable bit, ADATE in ADCSRA. The trigger source is
selected by setting the ADC Trigger Select bits, ADTS in ADCSRB (See description of the ADTS
bits for a list of the trigger sources). When a positive edge occurs on the selected trigger signal,
the ADC prescaler is reset and a conversion is started. This provides a method of starting con-
versions at fixed intervals. If the trigger signal still is set when the conversion completes, a new
conversion will not be started. If another positive edge occurs on the trigger signal during con-
version, the edge will be ignored. Note that an Interrupt Flag will be set even if the specific
interrupt is disabled or the Global Interrupt Enable bit in SREG is cleared. A conversion can thus
be triggered without causing an interrupt. However, the Interrupt Flag must be cleared in order to
trigger a new conversion at the next interrupt event.

Figure 23-2. ADC Auto Trigger Logic

ADTS[2:0]
PRESCALER

START CLKADC
ADIF ADATE
SOURCE 1
. CONVERSION
. LOGIC
.
. EDGE
SOURCE n DETECTOR

ADSC

Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon
as the ongoing conversion has finished. The ADC then operates in Free Running mode, con-
stantly sampling and updating the ADC Data Register. The first conversion must be started by
writing a logical one to the ADSC bit in ADCSRA. In this mode the ADC will perform successive
conversions independently of whether the ADC Interrupt Flag, ADIF is cleared or not.

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If Auto Triggering is enabled, single conversions can be started by writing ADSC in ADCSRA to
one. ADSC can also be used to determine if a conversion is in progress. The ADSC bit will be
read as one during a conversion, independently of how the conversion was started.

23.4 Prescaling and Conversion Timing

Figure 23-3. ADC Prescaler

ADEN
START Reset
7-BIT ADC PRESCALER
CK

CK/128
CK/64
CK/32
CK/16
CK/2
CK/4
CK/8
ADPS0
ADPS1
ADPS2

ADC CLOCK SOURCE

By default, the successive approximation circuitry requires an input clock frequency between 50
kHz and 200 kHz to get maximum resolution. If a lower resolution than 10 bits is needed, the
input clock frequency to the ADC can be higher than 200 kHz to get a higher sample rate.
The ADC module contains a prescaler, which generates an acceptable ADC clock frequency
from any CPU frequency above 100 kHz. The prescaling is set by the ADPS bits in ADCSRA.
The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit
in ADCSRA. The prescaler keeps running for as long as the ADEN bit is set, and is continuously
reset when ADEN is low.
When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion
starts at the following rising edge of the ADC clock cycle.
A normal conversion takes 13 ADC clock cycles. The first conversion after the ADC is switched
on (ADEN in ADCSRA is set) takes 25 ADC clock cycles in order to initialize the analog circuitry.
When the bandgap reference voltage is used as input to the ADC, it will take a certain time for
the voltage to stabilize. If not stabilized, the first value read after the first conversion may be
wrong.
The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normal conver-
sion and 13.5 ADC clock cycles after the start of an first conversion. When a conversion is
complete, the result is written to the ADC Data Registers, and ADIF is set. In Single Conversion
mode, ADSC is cleared simultaneously. The software may then set ADSC again, and a new
conversion will be initiated on the first rising ADC clock edge.
When Auto Triggering is used, the prescaler is reset when the trigger event occurs. This assures
a fixed delay from the trigger event to the start of conversion. In this mode, the sample-and-hold
takes place two ADC clock cycles after the rising edge on the trigger source signal. Three addi-
tional CPU clock cycles are used for synchronization logic.

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In Free Running mode, a new conversion will be started immediately after the conversion com-
pletes, while ADSC remains high. For a summary of conversion times, see Table 23-1 on page
255.

Figure 23-4. ADC Timing Diagram, First Conversion (Single Conversion Mode)
Next
First Conversion Conversion

Cycle Number 1 2 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3

ADC Clock

ADEN

ADSC

ADIF

ADCH Sign and MSB of Result

ADCL LSB of Result

MUX and REFS Conversion MUX and REFS

Update Sample & Hold Complete Update

Figure 23-5. ADC Timing Diagram, Single Conversion

One Conversion Next Conversion

Cycle Number 1 2 3 4 5 6 7 8 9 10 11 12 13 1 2 3

ADC Clock

ADSC

ADIF

ADCH Sign and MSB of Result

ADCL LSB of Result

Sample & Hold

Conversion MUX and REFS
MUX and REFS Complete Update
Update

Figure 23-6. ADC Timing Diagram, Auto Triggered Conversion

One Conversion Next Conversion

Cycle Number 1 2 3 4 5 6 7 8 9 10 11 12 13 1 2

ADC Clock

Trigger
Source

ADATE

ADIF

ADCH Sign and MSB of Result

ADCL LSB of Result

Sample & Conversion Prescaler

Prescaler Hold Reset
Complete
Reset
MUX and REFS
Update

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Figure 23-7. ADC Timing Diagram, Free Running Conversion

One Conversion Next Conversion

11 12 13 1 2 3 4
Cycle Number

ADC Clock

ADSC

ADIF

ADCH Sign and MSB of Result

ADCL LSB of Result

Conversion Sample & Hold

Complete MUX and REFS
Update

Table 23-1. ADC Conversion Time

Sample & Hold Conversion Time
Condition (Cycles from Start of Conversion) (Cycles)
First conversion 13.5 25
Normal conversions, single ended 1.5 13
Auto Triggered conversions 2 13.5

23.5 Changing Channel or Reference Selection

The MUXn and REFS1:0 bits in the ADMUX Register are single buffered through a temporary
register to which the CPU has random access. This ensures that the channels and reference
selection only takes place at a safe point during the conversion. The channel and reference
selection is continuously updated until a conversion is started. Once the conversion starts, the
channel and reference selection is locked to ensure a sufficient sampling time for the ADC. Con-
tinuous updating resumes in the last ADC clock cycle before the conversion completes (ADIF in
ADCSRA is set). Note that the conversion starts on the following rising ADC clock edge after
ADSC is written. The user is thus advised not to write new channel or reference selection values
to ADMUX until one ADC clock cycle after ADSC is written.
If Auto Triggering is used, the exact time of the triggering event can be indeterministic. Special
care must be taken when updating the ADMUX Register, in order to control which conversion
will be affected by the new settings.
If both ADATE and ADEN is written to one, an interrupt event can occur at any time. If the
ADMUX Register is changed in this period, the user cannot tell if the next conversion is based
on the old or the new settings. ADMUX can be safely updated in the following ways:
a. When ADATE or ADEN is cleared.
b. During conversion, minimum one ADC clock cycle after the trigger event.
c. After a conversion, before the Interrupt Flag used as trigger source is cleared.
When updating ADMUX in one of these conditions, the new settings will affect the next ADC
conversion.

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23.5.1 ADC Input Channels

When changing channel selections, the user should observe the following guidelines to ensure
that the correct channel is selected:
In Single Conversion mode, always select the channel before starting the conversion. The chan-
nel selection may be changed one ADC clock cycle after writing one to ADSC. However, the
simplest method is to wait for the conversion to complete before changing the channel selection.
In Free Running mode, always select the channel before starting the first conversion. The chan-
nel selection may be changed one ADC clock cycle after writing one to ADSC. However, the
simplest method is to wait for the first conversion to complete, and then change the channel
selection. Since the next conversion has already started automatically, the next result will reflect
the previous channel selection. Subsequent conversions will reflect the new channel selection.

23.5.2 ADC Voltage Reference

The reference voltage for the ADC (VREF) indicates the conversion range for the ADC. Single
ended channels that exceed VREF will result in codes close to 0x3FF. VREF can be selected as
either AVCC, internal 1.1V reference, or external AREF pin.
AVCC is connected to the ADC through a passive switch. The internal 1.1V reference is gener-
ated from the internal bandgap reference (VBG) through an internal amplifier. In either case, the
external AREF pin is directly connected to the ADC, and the reference voltage can be made
more immune to noise by connecting a capacitor between the AREF pin and ground. VREF can
also be measured at the AREF pin with a high impedance voltmeter. Note that VREF is a high
impedance source, and only a capacitive load should be connected in a system.
If the user has a fixed voltage source connected to the AREF pin, the user may not use the other
reference voltage options in the application, as they will be shorted to the external voltage. If no
external voltage is applied to the AREF pin, the user may switch between AVCC and 1.1V as ref-
erence selection. The first ADC conversion result after switching reference voltage source may
be inaccurate, and the user is advised to discard this result.

23.6 ADC Noise Canceler

The ADC features a noise canceler that enables conversion during sleep mode to reduce noise
induced from the CPU core and other I/O peripherals. The noise canceler can be used with ADC
Noise Reduction and Idle mode. To make use of this feature, the following procedure should be
used:
a. Make sure that the ADC is enabled and is not busy converting. Single Conversion
mode must be selected and the ADC conversion complete interrupt must be enabled.
b. Enter ADC Noise Reduction mode (or Idle mode). The ADC will start a conversion
once the CPU has been halted.
c. If no other interrupts occur before the ADC conversion completes, the ADC interrupt
will wake up the CPU and execute the ADC Conversion Complete interrupt routine. If
another interrupt wakes up the CPU before the ADC conversion is complete, that
interrupt will be executed, and an ADC Conversion Complete interrupt request will be
generated when the ADC conversion completes. The CPU will remain in active mode
until a new sleep command is executed.
Note that the ADC will not be automatically turned off when entering other sleep modes than Idle
mode and ADC Noise Reduction mode. The user is advised to write zero to ADEN before enter-
ing such sleep modes to avoid excessive power consumption.

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23.6.1 Analog Input Circuitry

The analog input circuitry for single ended channels is illustrated in Figure 23-8. An analog
source applied to ADCn is subjected to the pin capacitance and input leakage of that pin, regard-
less of whether that channel is selected as input for the ADC. When the channel is selected, the
source must drive the S/H capacitor through the series resistance (combined resistance in the
input path).
The ADC is optimized for analog signals with an output impedance of approximately 10 kΩ or
less. If such a source is used, the sampling time will be negligible. If a source with higher imped-
ance is used, the sampling time will depend on how long time the source needs to charge the
S/H capacitor, with can vary widely. The user is recommended to only use low impedance
sources with slowly varying signals, since this minimizes the required charge transfer to the S/H
capacitor.
Signal components higher than the Nyquist frequency (fADC/2) should not be present for either
kind of channels, to avoid distortion from unpredictable signal convolution. The user is advised
to remove high frequency components with a low-pass filter before applying the signals as
inputs to the ADC.

Figure 23-8. Analog Input Circuitry

IIH

ADCn
1..100 kΩ
CS/H= 14 pF
IIL
VCC/2

23.6.2 Analog Noise Canceling Techniques

Digital circuitry inside and outside the device generates EMI which might affect the accuracy of
analog measurements. If conversion accuracy is critical, the noise level can be reduced by
applying the following techniques:
a. Keep analog signal paths as short as possible. Make sure analog tracks run over the
analog ground plane, and keep them well away from high-speed switching digital
tracks.
b. The AVCC pin on the device should be connected to the digital VCC supply voltage via
an LC network as shown in Figure 23-9.
c. Use the ADC noise canceler function to reduce induced noise from the CPU.
d. If any ADC [3..0] port pins are used as digital outputs, it is essential that these do not
switch while a conversion is in progress. However, using the 2-wire Interface (ADC4

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and ADC5) will only affect the conversion on ADC4 and ADC5 and not the other ADC
channels.

Figure 23-9. ADC Power Connections

PC4 (ADC4/SDA)
PC5 (ADC5/SCL)

Analog Ground Plane

PC3 (ADC3)

PC2 (ADC2)
GND

VCC
PC1 (ADC1)

PC0 (ADC0)

ADC7

GND

10µH
AREF

ADC6

100nF
AVCC

PB5

23.6.3 ADC Accuracy Definitions

An n-bit single-ended ADC converts a voltage linearly between GND and V REF in 2 n steps
(LSBs). The lowest code is read as 0, and the highest code is read as 2n-1.
Several parameters describe the deviation from the ideal behavior:
• Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition (at
0.5 LSB). Ideal value: 0 LSB.

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Figure 23-10. Offset Error

Output Code

Ideal ADC

Actual ADC

Offset
Error
VREF Input Voltage

• Gain error: After adjusting for offset, the gain error is found as the deviation of the last transition
(0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum). Ideal value: 0
LSB

Figure 23-11. Gain Error

Output Code Gain
Error

Ideal ADC
Actual ADC

VREF Input Voltage

• Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum
deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0
LSB.

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Figure 23-12. Integral Non-linearity (INL)

Output Code

INL
Ideal ADC

Actual ADC

VREF Input Voltage

• Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval
between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB.

Figure 23-13. Differential Non-linearity (DNL)

Output Code
0x3FF

1 LSB

DNL
0x000

0 VREF Input Voltage

• Quantization Error: Due to the quantization of the input voltage into a finite number of codes, a
range of input voltages (1 LSB wide) will code to the same value. Always ±0.5 LSB.
• Absolute accuracy: The maximum deviation of an actual (unadjusted) transition compared to
an ideal transition for any code. This is the compound effect of offset, gain error, differential
error, non-linearity, and quantization error. Ideal value: ±0.5 LSB.

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23.7 ADC Conversion Result

After the conversion is complete (ADIF is high), the conversion result can be found in the ADC
Result Registers (ADCL, ADCH).
For single ended conversion, the result is

V IN ⋅ 1024
ADC = --------------------------
V REF

where VIN is the voltage on the selected input pin and VREF the selected voltage reference (see
Table 23-3 on page 262 and Table 23-4 on page 263). 0x000 represents analog ground, and
0x3FF represents the selected reference voltage minus one LSB.

23.8 Temperature Measurement

The temperature measurement is based on an on-chip temperature sensor that is coupled to a
single ended ADC8 channel. Selecting the ADC8 channel by writing the MUX3..0 bits in ADMUX
register to "1000" enables the temperature sensor. The internal 1.1V voltage reference must
also be selected for the ADC voltage reference source in the temperature sensor measurement.
When the temperature sensor is enabled, the ADC converter can be used in single conversion
mode to measure the voltage over the temperature sensor.
The measured voltage has a linear relationship to the temperature as described in Table 23-2.
The voltage sensitivity is approximately 1 mV/°C and the accuracy of the temperature measure-
ment is +/- 10°C.

Table 23-2. Temperature vs. Sensor Output Voltage (Typical Case)

Temperature / °C -45°C +25°C +85°C
Voltage / mV 242 mV 314 mV 380 mV

The values described in Table 23-2 are typical values. However, due to the process variation the
temperature sensor output voltage varies from one chip to another. To be capable of achieving
more accurate results the temperature measurement can be calibrated in the application soft-
ware. The software calibration requires that a calibration value is measured and stored in a
register or EEPROM for each chip, as a part of the production test. The software calibration can
be done utilizing the formula:
T = { [(ADCH << 8) | ADCL] - TOS} / k
where ADCn are the ADC data registers, k is a fixed coefficient and TOS is the temperature sen-
sor offset value determined and stored into EEPROM as a part of the production test.

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23.9 Register Description

23.9.1 ADMUX – ADC Multiplexer Selection Register

Bit 7 6 5 4 3 2 1 0
(0x7C) REFS1 REFS0 ADLAR – MUX3 MUX2 MUX1 MUX0 ADMUX
Read/Write R/W R/W R/W R R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0

• Bit 7:6 – REFS1:0: Reference Selection Bits

These bits select the voltage reference for the ADC, as shown in Table 23-3. If these bits are
changed during a conversion, the change will not go in effect until this conversion is complete
(ADIF in ADCSRA is set). The internal voltage reference options may not be used if an external
reference voltage is being applied to the AREF pin.

Table 23-3. Voltage Reference Selections for ADC

REFS1 REFS0 Voltage Reference Selection
0 0 AREF, Internal Vref turned off
0 1 AVCC with external capacitor at AREF pin
1 0 Reserved
1 1 Internal 1.1V Voltage Reference with external capacitor at AREF pin

• Bit 5 – ADLAR: ADC Left Adjust Result

The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register.
Write one to ADLAR to left adjust the result. Otherwise, the result is right adjusted. Changing the
ADLAR bit will affect the ADC Data Register immediately, regardless of any ongoing conver-
sions. For a complete description of this bit, see ”ADCL and ADCH – The ADC Data Register” on
page 265.

• Bit 4 – Res: Reserved Bit

This bit is an unused bit in the ATmega48PA/88PA/168PA/328P, and will always read as zero.

• Bits 3:0 – MUX3:0: Analog Channel Selection Bits

The value of these bits selects which analog inputs are connected to the ADC. See Table 23-4
for details. If these bits are changed during a conversion, the change will not go in effect until this
conversion is complete (ADIF in ADCSRA is set).

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Table 23-4. Input Channel Selections

MUX3..0 Single Ended Input
0000 ADC0
0001 ADC1
0010 ADC2
0011 ADC3
0100 ADC4
0101 ADC5
0110 ADC6
0111 ADC7
1000 ADC8(1)
1001 (reserved)
1010 (reserved)
1011 (reserved)
1100 (reserved)
1101 (reserved)
1110 1.1V (VBG)
1111 0V (GND)

Note: 1. For Temperature Sensor.

23.9.2 ADCSRA – ADC Control and Status Register A

Bit 7 6 5 4 3 2 1 0
(0x7A) ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 ADCSRA
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0

• Bit 7 – ADEN: ADC Enable

Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the
ADC off while a conversion is in progress, will terminate this conversion.

• Bit 6 – ADSC: ADC Start Conversion

In Single Conversion mode, write this bit to one to start each conversion. In Free Running mode,
write this bit to one to start the first conversion. The first conversion after ADSC has been written
after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled,
will take 25 ADC clock cycles instead of the normal 13. This first conversion performs initializa-
tion of the ADC.
ADSC will read as one as long as a conversion is in progress. When the conversion is complete,
it returns to zero. Writing zero to this bit has no effect.

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• Bit 5 – ADATE: ADC Auto Trigger Enable

When this bit is written to one, Auto Triggering of the ADC is enabled. The ADC will start a con-
version on a positive edge of the selected trigger signal. The trigger source is selected by setting
the ADC Trigger Select bits, ADTS in ADCSRB.

• Bit 4 – ADIF: ADC Interrupt Flag

This bit is set when an ADC conversion completes and the Data Registers are updated. The
ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set.
ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alter-
natively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a Read-Modify-
Write on ADCSRA, a pending interrupt can be disabled. This also applies if the SBI and CBI
instructions are used.

• Bit 3 – ADIE: ADC Interrupt Enable

When this bit is written to one and the I-bit in SREG is set, the ADC Conversion Complete Inter-
rupt is activated.

• Bits 2:0 – ADPS2:0: ADC Prescaler Select Bits

These bits determine the division factor between the system clock frequency and the input clock
to the ADC.

Table 23-5. ADC Prescaler Selections

ADPS2 ADPS1 ADPS0 Division Factor
0 0 0 2
0 0 1 2
0 1 0 4
0 1 1 8
1 0 0 16
1 0 1 32
1 1 0 64
1 1 1 128

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23.9.3 ADCL and ADCH – The ADC Data Register

23.9.3.1 ADLAR = 0
Bit 15 14 13 12 11 10 9 8
(0x79) – – – – – – ADC9 ADC8 ADCH
(0x78) ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 ADCL
7 6 5 4 3 2 1 0
Read/Write R R R R R R R R
R R R R R R R R
Initial Value 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0

23.9.3.2 ADLAR = 1

Bit 15 14 13 12 11 10 9 8
(0x79) ADC9 ADC8 ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADCH
(0x78) ADC1 ADC0 – – – – – – ADCL
7 6 5 4 3 2 1 0
Read/Write R R R R R R R R
R R R R R R R R
Initial Value 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0

When an ADC conversion is complete, the result is found in these two registers.
When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if
the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read
ADCH. Otherwise, ADCL must be read first, then ADCH.
The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from
the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result
is right adjusted.

• ADC9:0: ADC Conversion Result

These bits represent the result from the conversion, as detailed in ”ADC Conversion Result” on
page 261.

23.9.4 ADCSRB – ADC Control and Status Register B

Bit 7 6 5 4 3 2 1 0
(0x7B) – ACME – – – ADTS2 ADTS1 ADTS0 ADCSRB
Read/Write R R/W R R R R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0

• Bit 7, 5:3 – Res: Reserved Bits

These bits are reserved for future use. To ensure compatibility with future devices, these bist
must be written to zero when ADCSRB is written.

• Bit 2:0 – ADTS2:0: ADC Auto Trigger Source

If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger
an ADC conversion. If ADATE is cleared, the ADTS2:0 settings will have no effect. A conversion
will be triggered by the rising edge of the selected Interrupt Flag. Note that switching from a trig-
ger source that is cleared to a trigger source that is set, will generate a positive edge on the

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trigger signal. If ADEN in ADCSRA is set, this will start a conversion. Switching to Free Running
mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag is set.

Table 23-6. ADC Auto Trigger Source Selections

ADTS2 ADTS1 ADTS0 Trigger Source
0 0 0 Free Running mode
0 0 1 Analog Comparator
0 1 0 External Interrupt Request 0
0 1 1 Timer/Counter0 Compare Match A
1 0 0 Timer/Counter0 Overflow
1 0 1 Timer/Counter1 Compare Match B
1 1 0 Timer/Counter1 Overflow
1 1 1 Timer/Counter1 Capture Event

23.9.5 DIDR0 – Digital Input Disable Register 0

Bit 7 6 5 4 3 2 1 0
(0x7E) – – ADC5D ADC4D ADC3D ADC2D ADC1D ADC0D DIDR0
Read/Write R R R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0

• Bits 7:6 – Res: Reserved Bits

These bits are reserved for future use. To ensure compatibility with future devices, these bits
must be written to zero when DIDR0 is written.

• Bit 5:0 – ADC5D..ADC0D: ADC5..0 Digital Input Disable

When this bit is written logic one, the digital input buffer on the corresponding ADC pin is dis-
abled. The corresponding PIN Register bit will always read as zero when this bit is set. When an
analog signal is applied to the ADC5..0 pin and the digital input from this pin is not needed, this
bit should be written logic one to reduce power consumption in the digital input buffer.
Note that ADC pins ADC7 and ADC6 do not have digital input buffers, and therefore do not
require Digital Input Disable bits.

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24. debugWIRE On-chip Debug System

24.1 Features
• Complete Program Flow Control
• Emulates All On-chip Functions, Both Digital and Analog, except RESET Pin
• Real-time Operation
• Symbolic Debugging Support (Both at C and Assembler Source Level, or for Other HLLs)
• Unlimited Number of Program Break Points (Using Software Break Points)
• Non-intrusive Operation
• Electrical Characteristics Identical to Real Device
• Automatic Configuration System
• High-Speed Operation
• Programming of Non-volatile Memories

24.2 Overview
The debugWIRE On-chip debug system uses a One-wire, bi-directional interface to control the
program flow, execute AVR instructions in the CPU and to program the different non-volatile
memories.

24.3 Physical Interface

When the debugWIRE Enable (DWEN) Fuse is programmed and Lock bits are unprogrammed,
the debugWIRE system within the target device is activated. The RESET port pin is configured
as a wire-AND (open-drain) bi-directional I/O pin with pull-up enabled and becomes the commu-
nication gateway between target and emulator.

Figure 24-1. The debugWIRE Setup

1.8 - 5.5V

VCC

dW dW(RESET)

GND

Figure 24-1 shows the schematic of a target MCU, with debugWIRE enabled, and the emulator
connector. The system clock is not affected by debugWIRE and will always be the clock source
selected by the CKSEL Fuses.

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When designing a system where debugWIRE will be used, the following observations must be
made for correct operation:
• Pull-up resistors on the dW/(RESET) line must not be smaller than 10kΩ. The pull-up resistor
is not required for debugWIRE functionality.
• Connecting the RESET pin directly to VCC will not work.
• Capacitors connected to the RESET pin must be disconnected when using debugWire.
• All external reset sources must be disconnected.

24.4 Software Break Points

debugWIRE supports Program memory Break Points by the AVR Break instruction. Setting a
Break Point in AVR Studio® will insert a BREAK instruction in the Program memory. The instruc-
tion replaced by the BREAK instruction will be stored. When program execution is continued, the
stored instruction will be executed before continuing from the Program memory. A break can be
inserted manually by putting the BREAK instruction in the program.
The Flash must be re-programmed each time a Break Point is changed. This is automatically
handled by AVR Studio through the debugWIRE interface. The use of Break Points will therefore
reduce the Flash Data retention. Devices used for debugging purposes should not be shipped to
end customers.

24.5 Limitations of debugWIRE

The debugWIRE communication pin (dW) is physically located on the same pin as External
Reset (RESET). An External Reset source is therefore not supported when the debugWIRE is
enabled.
A programmed DWEN Fuse enables some parts of the clock system to be running in all sleep
modes. This will increase the power consumption while in sleep. Thus, the DWEN Fuse should
be disabled when debugWire is not used.

24.6 Register Description

The following section describes the registers used with the debugWire.

24.6.1 DWDR – debugWire Data Register

Bit 7 6 5 4 3 2 1 0
DWDR[7:0] DWDR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0

The DWDR Register provides a communication channel from the running program in the MCU
to the debugger. This register is only accessible by the debugWIRE and can therefore not be
used as a general purpose register in the normal operations.

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25. Self-Programming the Flash, ATmega48PA

25.1 Overview
In ATmega48PA, there is no Read-While-Write support, and no separate Boot Loader Section.
The SPM instruction can be executed from the entire Flash.
The device provides a Self-Programming mechanism for downloading and uploading program
code by the MCU itself. The Self-Programming can use any available data interface and associ-
ated protocol to read code and write (program) that code into the Program memory.
The Program memory is updated in a page by page fashion. Before programming a page with
the data stored in the temporary page buffer, the page must be erased. The temporary page buf-
fer is filled one word at a time using SPM and the buffer can be filled either before the Page
Erase command or between a Page Erase and a Page Write operation:
Alternative 1, fill the buffer before a Page Erase
• Fill temporary page buffer
• Perform a Page Erase
• Perform a Page Write
Alternative 2, fill the buffer after Page Erase
• Perform a Page Erase
• Fill temporary page buffer
• Perform a Page Write
If only a part of the page needs to be changed, the rest of the page must be stored (for example
in the temporary page buffer) before the erase, and then be re-written. When using alternative 1,
the Boot Loader provides an effective Read-Modify-Write feature which allows the user software
to first read the page, do the necessary changes, and then write back the modified data. If alter-
native 2 is used, it is not possible to read the old data while loading since the page is already
erased. The temporary page buffer can be accessed in a random sequence. It is essential that
the page address used in both the Page Erase and Page Write operation is addressing the same
page.

25.1.1 Performing Page Erase by SPM

To execute Page Erase, set up the address in the Z-pointer, write “00000011” to SPMCSR and
execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored.
The page address must be written to PCPAGE in the Z-register. Other bits in the Z-pointer will
be ignored during this operation.
• The CPU is halted during the Page Erase operation.

25.1.2 Filling the Temporary Buffer (Page Loading)

To write an instruction word, set up the address in the Z-pointer and data in R1:R0, write
“00000001” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The
content of PCWORD in the Z-register is used to address the data in the temporary buffer. The
temporary buffer will auto-erase after a Page Write operation or by writing the RWWSRE bit in
SPMCSR. It is also erased after a system reset. Note that it is not possible to write more than
one time to each address without erasing the temporary buffer.

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If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded will be
lost.

25.1.3 Performing a Page Write

To execute Page Write, set up the address in the Z-pointer, write “00000101” to SPMCSR and
execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored.
The page address must be written to PCPAGE. Other bits in the Z-pointer must be written to
zero during this operation.
• The CPU is halted during the Page Write operation.

25.2 Addressing the Flash During Self-Programming

The Z-pointer is used to address the SPM commands.
Bit 15 14 13 12 11 10 9 8
ZH (R31) Z15 Z14 Z13 Z12 Z11 Z10 Z9 Z8
ZL (R30) Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0
7 6 5 4 3 2 1 0

Since the Flash is organized in pages (see Table 27-11 on page 299), the Program Counter can
be treated as having two different sections. One section, consisting of the least significant bits, is
addressing the words within a page, while the most significant bits are addressing the pages.
This is shown in Figure 26-3 on page 282. Note that the Page Erase and Page Write operations
are addressed independently. Therefore it is of major importance that the software addresses
the same page in both the Page Erase and Page Write operation.
The LPM instruction uses the Z-pointer to store the address. Since this instruction addresses the
Flash byte-by-byte, also the LSB (bit Z0) of the Z-pointer is used.

Figure 25-1. Addressing the Flash During SPM(1)

BIT 15 ZPCMSB ZPAGEMSB 1 0
Z - REGISTER 0

PCMSB PAGEMSB
PROGRAM
PCPAGE PCWORD
COUNTER

PAGE ADDRESS WORD ADDRESS

WITHIN THE FLASH WITHIN A PAGE

PROGRAM MEMORY PAGE PCWORD[PAGEMSB:0]:

PAGE 00
INSTRUCTION WORD

01

02

PAGEEND

Note: 1. The different variables used in Figure 26-3 are listed in Table 27-11 on page 299.

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25.2.1 EEPROM Write Prevents Writing to SPMCSR

Note that an EEPROM write operation will block all software programming to Flash. Reading the
Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It
is recommended that the user checks the status bit (EEPE) in the EECR Register and verifies
that the bit is cleared before writing to the SPMCSR Register.

25.2.2 Reading the Fuse and Lock Bits from Software

It is possible to read both the Fuse and Lock bits from software. To read the Lock bits, load the
Z-pointer with 0x0001 and set the BLBSET and SELFPRGEN bits in SPMCSR. When an LPM
instruction is executed within three CPU cycles after the BLBSET and SELFPRGEN bits are set
in SPMCSR, the value of the Lock bits will be loaded in the destination register. The BLBSET
and SELFPRGEN bits will auto-clear upon completion of reading the Lock bits or if no LPM
instruction is executed within three CPU cycles or no SPM instruction is executed within four
CPU cycles. When BLBSET and SELFPRGEN are cleared, LPM will work as described in the
Instruction set Manual.
Bit 7 6 5 4 3 2 1 0
Rd – – – – – – LB2 LB1

The algorithm for reading the Fuse Low byte is similar to the one described above for reading
the Lock bits. To read the Fuse Low byte, load the Z-pointer with 0x0000 and set the BLBSET
and SELFPRGEN bits in SPMCSR. When an LPM instruction is executed within three cycles
after the BLBSET and SELFPRGEN bits are set in the SPMCSR, the value of the Fuse Low byte
(FLB) will be loaded in the destination register as shown below.See Table 27-5 on page 296 for
a detailed description and mapping of the Fuse Low byte.
Bit 7 6 5 4 3 2 1 0
Rd FLB7 FLB6 FLB5 FLB4 FLB3 FLB2 FLB1 FLB0

Similarly, when reading the Fuse High byte (FHB), load 0x0003 in the Z-pointer. When an LPM
instruction is executed within three cycles after the BLBSET and SELFPRGEN bits are set in the
SPMCSR, the value of the Fuse High byte will be loaded in the destination register as shown
below. See Table 27-5 on page 296 for detailed description and mapping of the Extended Fuse
byte.
Bit 7 6 5 4 3 2 1 0
Rd FHB7 FHB6 FHB5 FHB4 FHB3 FHB2 FHB1 FHB0

Similarly, when reading the Extended Fuse byte (EFB), load 0x0002 in the Z-pointer. When an
LPM instruction is executed within three cycles after the BLBSET and SELFPRGEN bits are set
in the SPMCSR, the value of the Extended Fuse byte will be loaded in the destination register as
shown below. See Table 27-5 on page 296 for detailed description and mapping of the Extended
Fuse byte.
Bit 7 6 5 4 3 2 1 0
Rd FHB7 FHB6 FHB5 FHB4 FHB3 FHB2 FHB1 FHB0

Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are
unprogrammed, will be read as one.

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25.2.3 Preventing Flash Corruption

During periods of low VCC, the Flash program can be corrupted because the supply voltage is
too low for the CPU and the Flash to operate properly. These issues are the same as for board
level systems using the Flash, and the same design solutions should be applied.
A Flash program corruption can be caused by two situations when the voltage is too low. First, a
regular write sequence to the Flash requires a minimum voltage to operate correctly. Secondly,
the CPU itself can execute instructions incorrectly, if the supply voltage for executing instructions
is too low.
Flash corruption can easily be avoided by following these design recommendations (one is
sufficient):
1. Keep the AVR RESET active (low) during periods of insufficient power supply voltage.
This can be done by enabling the internal Brown-out Detector (BOD) if the operating volt-
age matches the detection level. If not, an external low VCC reset protection circuit can be
used. If a reset occurs while a write operation is in progress, the write operation will be
completed provided that the power supply voltage is sufficient.
2. Keep the AVR core in Power-down sleep mode during periods of low VCC. This will pre-
vent the CPU from attempting to decode and execute instructions, effectively protecting
the SPMCSR Register and thus the Flash from unintentional writes.

25.2.4 Programming Time for Flash when Using SPM

The calibrated RC Oscillator is used to time Flash accesses. Table 26-6 shows the typical pro-
gramming time for Flash accesses from the CPU.

Table 25-1. SPM Programming Time(1)

Symbol Min Programming Time Max Programming Time
Flash write (Page Erase, Page Write, and
3.7 ms 4.5 ms
write Lock bits by SPM)

Note: 1. Minimum and maximum programming time is per individual operation.

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25.2.5 Simple Assembly Code Example for a Boot Loader

Note that the RWWSB bit will always be read as zero in ATmega48PA. Nevertheless, it is rec-
ommended to check this bit as shown in the code example, to ensure compatibility with devices
supporting Read-While-Write.

;-the routine writes one page of data from RAM to Flash

; the first data location in RAM is pointed to by the Y pointer
; the first data location in Flash is pointed to by the Z-pointer
;-error handling is not included
;-the routine must be placed inside the Boot space
; (at least the Do_spm sub routine). Only code inside NRWW section can
; be read during Self-Programming (Page Erase and Page Write).
;-registers used: r0, r1, temp1 (r16), temp2 (r17), looplo (r24),
; loophi (r25), spmcrval (r20)
; storing and restoring of registers is not included in the routine
; register usage can be optimized at the expense of code size
;-It is assumed that either the interrupt table is moved to the Boot
; loader section or that the interrupts are disabled.
.equ PAGESIZEB = PAGESIZE*2 ;PAGESIZEB is page size in BYTES, not words
.org SMALLBOOTSTART
Write_page:
; Page Erase
ldi spmcrval, (1<<PGERS) | (1<<SELFPRGEN)
rcallDo_spm

; re-enable the RWW section

ldi spmcrval, (1<<RWWSRE) | (1<<SELFPRGEN)
rcallDo_spm

; transfer data from RAM to Flash page buffer

ldi looplo, low(PAGESIZEB) ;init loop variable
ldi loophi, high(PAGESIZEB) ;not required for PAGESIZEB<=256
Wrloop:
ld r0, Y+
ld r1, Y+
ldi spmcrval, (1<<SELFPRGEN)
rcallDo_spm
adiw ZH:ZL, 2
sbiw loophi:looplo, 2 ;use subi for PAGESIZEB<=256
brne Wrloop

; execute Page Write

subi ZL, low(PAGESIZEB) ;restore pointer
sbci ZH, high(PAGESIZEB) ;not required for PAGESIZEB<=256
ldi spmcrval, (1<<PGWRT) | (1<<SELFPRGEN)
rcallDo_spm

; re-enable the RWW section

ldi spmcrval, (1<<RWWSRE) | (1<<SELFPRGEN)
rcallDo_spm

; read back and check, optional

ldi looplo, low(PAGESIZEB) ;init loop variable
ldi loophi, high(PAGESIZEB) ;not required for PAGESIZEB<=256
subi YL, low(PAGESIZEB) ;restore pointer

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sbci YH, high(PAGESIZEB)

Rdloop:
lpm r0, Z+
ld r1, Y+
cpse r0, r1
rjmp Error
sbiw loophi:looplo, 1 ;use subi for PAGESIZEB<=256
brne Rdloop

; return to RWW section

; verify that RWW section is safe to read
Return:
in temp1, SPMCSR
sbrs temp1, RWWSB ; If RWWSB is set, the RWW section is not ready yet
ret
; re-enable the RWW section
ldi spmcrval, (1<<RWWSRE) | (1<<SELFPRGEN)
rcallDo_spm
rjmp Return

Do_spm:
; check for previous SPM complete
Wait_spm:
in temp1, SPMCSR
sbrc temp1, SELFPRGEN
rjmp Wait_spm
; input: spmcrval determines SPM action
; disable interrupts if enabled, store status
in temp2, SREG
cli
; check that no EEPROM write access is present
Wait_ee:
sbic EECR, EEPE
rjmp Wait_ee
; SPM timed sequence
out SPMCSR, spmcrval
spm
; restore SREG (to enable interrupts if originally enabled)
out SREG, temp2
ret

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25.3 Register Description

25.3.1 SPMCSR – Store Program Memory Control and Status Register

The Store Program Memory Control and Status Register contains the control bits needed to con-
trol the Program memory operations.
Bit 7 6 5 4 3 2 1 0
0x37 (0x57) SPMIE RWWSB – RWWSRE BLBSET PGWRT PGERS SELFPRGEN SPMCSR
Read/Write R/W R R R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0

• Bit 7 – SPMIE: SPM Interrupt Enable

When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM
ready interrupt will be enabled. The SPM ready Interrupt will be executed as long as the SELF-
PRGEN bit in the SPMCSR Register is cleared. The interrupt will not be generated during
EEPROM write or SPM.

• Bit 6 – RWWSB: Read-While-Write Section Busy

This bit is for compatibility with devices supporting Read-While-Write. It will always read as zero
in ATmega48PA.

• Bit 5 – Res: Reserved Bit

This bit is a reserved bit in the ATmega48PA/88PA/168PA/328P and will always read as zero.

• Bit 4 – RWWSRE: Read-While-Write Section Read Enable

The functionality of this bit in ATmega48PA is a subset of the functionality in
ATmega88PA/168PA. If the RWWSRE bit is written while filling the temporary page buffer, the
temporary page buffer will be cleared and the data will be lost.

• Bit 3 – BLBSET: Boot Lock Bit Set

The functionality of this bit in ATmega48PA is a subset of the functionality in
ATmega88PA/168PA. An LPM instruction within three cycles after BLBSET and SELFPRGEN
are set in the SPMCSR Register, will read either the Lock bits or the Fuse bits (depending on Z0
in the Z-pointer) into the destination register. See ”Reading the Fuse and Lock Bits from Soft-
ware” on page 271 for details.

• Bit 2 – PGWRT: Page Write

If this bit is written to one at the same time as SELFPRGEN, the next SPM instruction within four
clock cycles executes Page Write, with the data stored in the temporary buffer. The page
address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The
PGWRT bit will auto-clear upon completion of a Page Write, or if no SPM instruction is executed
within four clock cycles. The CPU is halted during the entire Page Write operation.

• Bit 1 – PGERS: Page Erase

If this bit is written to one at the same time as SELFPRGEN, the next SPM instruction within four
clock cycles executes Page Erase. The page address is taken from the high part of the Z-
pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a
Page Erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted dur-
ing the entire Page Write operation.

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• Bit 0 – SELFPRGEN: Self Programming Enable

This bit enables the SPM instruction for the next four clock cycles. If written to one together with
either RWWSRE, BLBSET, PGWRT, or PGERS, the following SPM instruction will have a spe-
cial meaning, see description above. If only SELFPRGEN is written, the following SPM
instruction will store the value in R1:R0 in the temporary page buffer addressed by the Z-pointer.
The LSB of the Z-pointer is ignored. The SELFPRGEN bit will auto-clear upon completion of an
SPM instruction, or if no SPM instruction is executed within four clock cycles. During Page Erase
and Page Write, the SELFPRGEN bit remains high until the operation is completed.
Writing any other combination than “10001”, “01001”, “00101”, “00011” or “00001” in the lower
five bits will have no effect.

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26. Boot Loader Support – Read-While-Write Self-Programming,

ATmega88PA, ATmega168PA and ATmega328P

26.1 Features
• Read-While-Write Self-Programming
• Flexible Boot Memory Size
• High Security (Separate Boot Lock Bits for a Flexible Protection)
• Separate Fuse to Select Reset Vector
• Optimized Page(1) Size
• Code Efficient Algorithm
• Efficient Read-Modify-Write Support
Note: 1. A page is a section in the Flash consisting of several bytes (see Table 27-11 on page 299)
used during programming. The page organization does not affect normal operation.

26.2 Overview
In ATmega88PA, ATmega168PA and ATmega328P, the Boot Loader Support provides a real
Read-While-Write Self-Programming mechanism for downloading and uploading program code
by the MCU itself. This feature allows flexible application software updates controlled by the
MCU using a Flash-resident Boot Loader program. The Boot Loader program can use any avail-
able data interface and associated protocol to read code and write (program) that code into the
Flash memory, or read the code from the program memory. The program code within the Boot
Loader section has the capability to write into the entire Flash, including the Boot Loader mem-
ory. The Boot Loader can thus even modify itself, and it can also erase itself from the code if the
feature is not needed anymore. The size of the Boot Loader memory is configurable with fuses
and the Boot Loader has two separate sets of Boot Lock bits which can be set independently.
This gives the user a unique flexibility to select different levels of protection.

26.3 Application and Boot Loader Flash Sections

The Flash memory is organized in two main sections, the Application section and the Boot
Loader section (see Figure 26-2). The size of the different sections is configured by the
BOOTSZ Fuses as shown in Table 26-7 on page 289 and Figure 26-2. These two sections can
have different level of protection since they have different sets of Lock bits.

26.3.1 Application Section

The Application section is the section of the Flash that is used for storing the application code.
The protection level for the Application section can be selected by the application Boot Lock bits
(Boot Lock bits 0), see Table 26-2 on page 281. The Application section can never store any
Boot Loader code since the SPM instruction is disabled when executed from the Application
section.

26.3.2 BLS – Boot Loader Section

While the Application section is used for storing the application code, the The Boot Loader soft-
ware must be located in the BLS since the SPM instruction can initiate a programming when
executing from the BLS only. The SPM instruction can access the entire Flash, including the
BLS itself. The protection level for the Boot Loader section can be selected by the Boot Loader
Lock bits (Boot Lock bits 1), see Table 26-3 on page 281.

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26.4 Read-While-Write and No Read-While-Write Flash Sections

Whether the CPU supports Read-While-Write or if the CPU is halted during a Boot Loader soft-
ware update is dependent on which address that is being programmed. In addition to the two
sections that are configurable by the BOOTSZ Fuses as described above, the Flash is also
divided into two fixed sections, the Read-While-Write (RWW) section and the No Read-While-
Write (NRWW) section. The limit between the RWW- and NRWW sections is given in Table 26-
8 on page 289 and Figure 26-2 on page 280. The main difference between the two sections is:
• When erasing or writing a page located inside the RWW section, the NRWW section can be
read during the operation.
• When erasing or writing a page located inside the NRWW section, the CPU is halted during the
entire operation.
Note that the user software can never read any code that is located inside the RWW section dur-
ing a Boot Loader software operation. The syntax “Read-While-Write section” refers to which
section that is being programmed (erased or written), not which section that actually is being
read during a Boot Loader software update.

26.4.1 RWW – Read-While-Write Section

If a Boot Loader software update is programming a page inside the RWW section, it is possible
to read code from the Flash, but only code that is located in the NRWW section. During an on-
going programming, the software must ensure that the RWW section never is being read. If the
user software is trying to read code that is located inside the RWW section (i.e., by a
call/jmp/lpm or an interrupt) during programming, the software might end up in an unknown
state. To avoid this, the interrupts should either be disabled or moved to the Boot Loader sec-
tion. The Boot Loader section is always located in the NRWW section. The RWW Section Busy
bit (RWWSB) in the Store Program Memory Control and Status Register (SPMCSR) will be read
as logical one as long as the RWW section is blocked for reading. After a programming is com-
pleted, the RWWSB must be cleared by software before reading code located in the RWW
section. See Section “26.9.1” on page 292. for details on how to clear RWWSB.

26.4.2 NRWW – No Read-While-Write Section

The code located in the NRWW section can be read when the Boot Loader software is updating
a page in the RWW section. When the Boot Loader code updates the NRWW section, the CPU
is halted during the entire Page Erase or Page Write operation.

Table 26-1. Read-While-Write Features

Which Section does the Z- Which Section can be
pointer Address during read during Read-While-Write
the Programming? Programming? CPU Halted? Supported?
RWW Section NRWW Section No Yes
NRWW Section None Yes No

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Figure 26-1. Read-While-Write vs. No Read-While-Write

Read-While-Write
(RWW) Section

Z-pointer
Addresses NRWW
Z-pointer Section
Addresses RWW No Read-While-Write
Section (NRWW) Section
CPU is Halted
During the Operation
Code Located in
NRWW Section
Can be Read During
the Operation

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Figure 26-2. Memory Sections

Program Memory Program Memory
BOOTSZ = '11' BOOTSZ = '10'
0x0000 0x0000

Read-While-Write Section

Read-While-Write Section
Application Flash Section Application Flash Section

No Read-While-Write Section

No Read-While-Write Section
End RWW End RWW
Start NRWW Start NRWW

Application Flash Section Application Flash Section

End Application
End Application Start Boot Loader
Start Boot Loader Boot Loader Flash Section
Boot Loader Flash Section
Flashend Flashend

Program Memory Program Memory

BOOTSZ = '01' BOOTSZ = '00'
0x0000 0x0000
Read-While-Write Section

Read-While-Write Section
Application Flash Section Application Flash Section

End RWW, End Application

No Read-While-Write Section

No Read-While-Write Section

End RWW
Start NRWW Start NRWW, Start Boot Loader
Application Flash Section

End Application
Boot Loader Flash Section
Start Boot Loader
Boot Loader Flash Section

Flashend Flashend

Note: 1. The parameters in the figure above are given in Table 26-7 on page 289.

26.5 Boot Loader Lock Bits

If no Boot Loader capability is needed, the entire Flash is available for application code. The
Boot Loader has two separate sets of Boot Lock bits which can be set independently. This gives
the user a unique flexibility to select different levels of protection.
The user can select:
• To protect the entire Flash from a software update by the MCU.
• To protect only the Boot Loader Flash section from a software update by the MCU.
• To protect only the Application Flash section from a software update by the MCU.
• Allow software update in the entire Flash.
See Table 26-2 and Table 26-3 for further details. The Boot Lock bits can be set in software and
in Serial or Parallel Programming mode, but they can be cleared by a Chip Erase command
only. The general Write Lock (Lock Bit mode 2) does not control the programming of the Flash
memory by SPM instruction. Similarly, the general Read/Write Lock (Lock Bit mode 1) does not
control reading nor writing by LPM/SPM, if it is attempted.

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Table 26-2. Boot Lock Bit0 Protection Modes (Application Section)(1)

BLB0 Mode BLB02 BLB01 Protection
No restrictions for SPM or LPM accessing the Application
1 1 1
section.
2 1 0 SPM is not allowed to write to the Application section.
SPM is not allowed to write to the Application section, and LPM
executing from the Boot Loader section is not allowed to read
3 0 0 from the Application section. If Interrupt Vectors are placed in
the Boot Loader section, interrupts are disabled while executing
from the Application section.
LPM executing from the Boot Loader section is not allowed to
read from the Application section. If Interrupt Vectors are placed
4 0 1
in the Boot Loader section, interrupts are disabled while
executing from the Application section.
Note: 1. “1” means unprogrammed, “0” means programmed

Table 26-3. Boot Lock Bit1 Protection Modes (Boot Loader Section)(1)
BLB1 Mode BLB12 BLB11 Protection
No restrictions for SPM or LPM accessing the Boot Loader
1 1 1
section.
2 1 0 SPM is not allowed to write to the Boot Loader section.
SPM is not allowed to write to the Boot Loader section, and LPM
executing from the Application section is not allowed to read
3 0 0 from the Boot Loader section. If Interrupt Vectors are placed in
the Application section, interrupts are disabled while executing
from the Boot Loader section.
LPM executing from the Application section is not allowed to
read from the Boot Loader section. If Interrupt Vectors are
4 0 1
placed in the Application section, interrupts are disabled while
executing from the Boot Loader section.
Note: 1. “1” means unprogrammed, “0” means programmed

26.6 Entering the Boot Loader Program

Entering the Boot Loader takes place by a jump or call from the application program. This may
be initiated by a trigger such as a command received via USART, or SPI interface. Alternatively,
the Boot Reset Fuse can be programmed so that the Reset Vector is pointing to the Boot Flash
start address after a reset. In this case, the Boot Loader is started after a reset. After the applica-
tion code is loaded, the program can start executing the application code. Note that the fuses
cannot be changed by the MCU itself. This means that once the Boot Reset Fuse is pro-
grammed, the Reset Vector will always point to the Boot Loader Reset and the fuse can only be
changed through the serial or parallel programming interface.
Table 26-4. Boot Reset Fuse(1)
BOOTRST Reset Address
1 Reset Vector = Application Reset (address 0x0000)
0 Reset Vector = Boot Loader Reset (see Table 26-7 on page 289)

Note: 1. “1” means unprogrammed, “0” means programmed

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26.7 Addressing the Flash During Self-Programming

The Z-pointer is used to address the SPM commands.
Bit 15 14 13 12 11 10 9 8
ZH (R31) Z15 Z14 Z13 Z12 Z11 Z10 Z9 Z8
ZL (R30) Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0
7 6 5 4 3 2 1 0

Since the Flash is organized in pages (see Table 27-11 on page 299), the Program Counter can
be treated as having two different sections. One section, consisting of the least significant bits, is
addressing the words within a page, while the most significant bits are addressing the pages.
This is1 shown in Figure 26-3. Note that the Page Erase and Page Write operations are
addressed independently. Therefore it is of major importance that the Boot Loader software
addresses the same page in both the Page Erase and Page Write operation. Once a program-
ming operation is initiated, the address is latched and the Z-pointer can be used for other
operations.
The only SPM operation that does not use the Z-pointer is Setting the Boot Loader Lock bits.
The content of the Z-pointer is ignored and will have no effect on the operation. The LPM
instruction does also use the Z-pointer to store the address. Since this instruction addresses the
Flash byte-by-byte, also the LSB (bit Z0) of the Z-pointer is used.

Figure 26-3. Addressing the Flash During SPM(1)

BIT 15 ZPCMSB ZPAGEMSB 1 0
Z - REGISTER 0

PCMSB PAGEMSB
PROGRAM
PCPAGE PCWORD
COUNTER

PAGE ADDRESS WORD ADDRESS

WITHIN THE FLASH WITHIN A PAGE

PROGRAM MEMORY PAGE PCWORD[PAGEMSB:0]:

PAGE 00
INSTRUCTION WORD

01

02

PAGEEND

Note: 1. The different variables used in Figure 26-3 are listed in Table 26-9 on page 289.

26.8 Self-Programming the Flash

The program memory is updated in a page by page fashion. Before programming a page with
the data stored in the temporary page buffer, the page must be erased. The temporary page buf-
fer is filled one word at a time using SPM and the buffer can be filled either before the Page
Erase command or between a Page Erase and a Page Write operation:

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Alternative 1, fill the buffer before a Page Erase

• Fill temporary page buffer
• Perform a Page Erase
• Perform a Page Write
Alternative 2, fill the buffer after Page Erase
• Perform a Page Erase
• Fill temporary page buffer
• Perform a Page Write
If only a part of the page needs to be changed, the rest of the page must be stored (for example
in the temporary page buffer) before the erase, and then be rewritten. When using alternative 1,
the Boot Loader provides an effective Read-Modify-Write feature which allows the user software
to first read the page, do the necessary changes, and then write back the modified data. If alter-
native 2 is used, it is not possible to read the old data while loading since the page is already
erased. The temporary page buffer can be accessed in a random sequence. It is essential that
the page address used in both the Page Erase and Page Write operation is addressing the same
page. See ”Simple Assembly Code Example for a Boot Loader” on page 286 for an assembly
code example.

26.8.1 Performing Page Erase by SPM

To execute Page Erase, set up the address in the Z-pointer, write “X0000011” to SPMCSR and
execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored.
The page address must be written to PCPAGE in the Z-register. Other bits in the Z-pointer will
be ignored during this operation.
• Page Erase to the RWW section: The NRWW section can be read during the Page Erase.
• Page Erase to the NRWW section: The CPU is halted during the operation.

26.8.2 Filling the Temporary Buffer (Page Loading)

To write an instruction word, set up the address in the Z-pointer and data in R1:R0, write
“00000001” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The
content of PCWORD in the Z-register is used to address the data in the temporary buffer. The
temporary buffer will auto-erase after a Page Write operation or by writing the RWWSRE bit in
SPMCSR. It is also erased after a system reset. Note that it is not possible to write more than
one time to each address without erasing the temporary buffer.
If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded will be
lost.

26.8.3 Performing a Page Write

To execute Page Write, set up the address in the Z-pointer, write “X0000101” to SPMCSR and
execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored.
The page address must be written to PCPAGE. Other bits in the Z-pointer must be written to
zero during this operation.
• Page Write to the RWW section: The NRWW section can be read during the Page Write.
• Page Write to the NRWW section: The CPU is halted during the operation.

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26.8.4 Using the SPM Interrupt

If the SPM interrupt is enabled, the SPM interrupt will generate a constant interrupt when the
SELFPRGEN bit in SPMCSR is cleared. This means that the interrupt can be used instead of
polling the SPMCSR Register in software. When using the SPM interrupt, the Interrupt Vectors
should be moved to the BLS section to avoid that an interrupt is accessing the RWW section
when it is blocked for reading. How to move the interrupts is described in ”Interrupts” on page
57.

26.8.5 Consideration While Updating BLS

Special care must be taken if the user allows the Boot Loader section to be updated by leaving
Boot Lock bit11 unprogrammed. An accidental write to the Boot Loader itself can corrupt the
entire Boot Loader, and further software updates might be impossible. If it is not necessary to
change the Boot Loader software itself, it is recommended to program the Boot Lock bit11 to
protect the Boot Loader software from any internal software changes.

26.8.6 Prevent Reading the RWW Section During Self-Programming

During Self-Programming (either Page Erase or Page Write), the RWW section is always
blocked for reading. The user software itself must prevent that this section is addressed during
the self programming operation. The RWWSB in the SPMCSR will be set as long as the RWW
section is busy. During Self-Programming the Interrupt Vector table should be moved to the BLS
as described in ”Watchdog Timer” on page 50, or the interrupts must be disabled. Before
addressing the RWW section after the programming is completed, the user software must clear
the RWWSB by writing the RWWSRE. See ”Simple Assembly Code Example for a Boot Loader”
on page 286 for an example.

26.8.7 Setting the Boot Loader Lock Bits by SPM

To set the Boot Loader Lock bits and general Lock Bits, write the desired data to R0, write
“X0001001” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR.
Bit 7 6 5 4 3 2 1 0
R0 1 1 BLB12 BLB11 BLB02 BLB01 LB2 LB1

See Table 26-2 and Table 26-3 for how the different settings of the Boot Loader bits affect the
Flash access.
If bits 5..0 in R0 are cleared (zero), the corresponding Lock bit will be programmed if an SPM
instruction is executed within four cycles after BLBSET and SELFPRGEN are set in SPMCSR.
The Z-pointer is don’t care during this operation, but for future compatibility it is recommended to
load the Z-pointer with 0x0001 (same as used for reading the lOck bits). For future compatibility it
is also recommended to set bits 7 and 6 in R0 to “1” when writing the Lock bits. When program-
ming the Lock bits the entire Flash can be read during the operation.

26.8.8 EEPROM Write Prevents Writing to SPMCSR

Note that an EEPROM write operation will block all software programming to Flash. Reading the
Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It
is recommended that the user checks the status bit (EEPE) in the EECR Register and verifies
that the bit is cleared before writing to the SPMCSR Register.

26.8.9 Reading the Fuse and Lock Bits from Software

It is possible to read both the Fuse and Lock bits from software. To read the Lock bits, load the
Z-pointer with 0x0001 and set the BLBSET and SELFPRGEN bits in SPMCSR. When an LPM

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instruction is executed within three CPU cycles after the BLBSET and SELFPRGEN bits are set
in SPMCSR, the value of the Lock bits will be loaded in the destination register. The BLBSET
and SELFPRGEN bits will auto-clear upon completion of reading the Lock bits or if no LPM
instruction is executed within three CPU cycles or no SPM instruction is executed within four
CPU cycles. When BLBSET and SELFPRGEN are cleared, LPM will work as described in the
Instruction set Manual.
Bit 7 6 5 4 3 2 1 0
Rd – – BLB12 BLB11 BLB02 BLB01 LB2 LB1

The algorithm for reading the Fuse Low byte is similar to the one described above for reading
the Lock bits. To read the Fuse Low byte, load the Z-pointer with 0x0000 and set the BLBSET
and SELFPRGEN bits in SPMCSR. When an LPM instruction is executed within three cycles
after the BLBSET and SELFPRGEN bits are set in the SPMCSR, the value of the Fuse Low byte
(FLB) will be loaded in the destination register as shown below. Refer to Table 27-5 on page 296
for a detailed description and mapping of the Fuse Low byte.
Bit 7 6 5 4 3 2 1 0
Rd FLB7 FLB6 FLB5 FLB4 FLB3 FLB2 FLB1 FLB0

Similarly, when reading the Fuse High byte, load 0x0003 in the Z-pointer. When an LPM instruc-
tion is executed within three cycles after the BLBSET and SELFPRGEN bits are set in the
SPMCSR, the value of the Fuse High byte (FHB) will be loaded in the destination register as
shown below. Refer to Table 27-7 on page 296 for detailed description and mapping of the Fuse
High byte.
Bit 7 6 5 4 3 2 1 0
Rd FHB7 FHB6 FHB5 FHB4 FHB3 FHB2 FHB1 FHB0

When reading the Extended Fuse byte, load 0x0002 in the Z-pointer. When an LPM instruction
is executed within three cycles after the BLBSET and SELFPRGEN bits are set in the SPMCSR,
the value of the Extended Fuse byte (EFB) will be loaded in the destination register as shown
below. Refer to Table 27-5 on page 296 for detailed description and mapping of the Extended
Fuse byte.
Bit 7 6 5 4 3 2 1 0
Rd – – – – EFB3 EFB2 EFB1 EFB0

Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are
unprogrammed, will be read as one.
26.8.10 Reading the Signature Row from Software

To read the Signature Row from software, load the Z-pointer with the signature byte address
given in Table 26-5 on page 286 and set the SIGRD and SPMEN bits in SPMCSR. When an
LPM instruction is executed within three CPU cycles after the SIGRD and SPMEN bits are set in
SPMCSR, the signature byte value will be loaded in the destination register. The SIGRD and
SPMEN bits will auto-clear upon completion of reading the Signature Row Lock bits or if no LPM
instruction is executed within three CPU cycles. When SIGRD and SPMEN are cleared, LPM will
work as described in the Instruction set Manual.

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Table 26-5. Signature Row Addressing

Signature Byte Z-Pointer Address
Device Signature Byte 1 0x0000
Device Signature Byte 2 0x0002
Device Signature Byte 3 0x0004
RC Oscillator Calibration Byte 0x0001

Note: All other addresses are reserved for future use.

26.8.11 Preventing Flash Corruption

During periods of low VCC, the Flash program can be corrupted because the supply voltage is
too low for the CPU and the Flash to operate properly. These issues are the same as for board
level systems using the Flash, and the same design solutions should be applied.
A Flash program corruption can be caused by two situations when the voltage is too low. First, a
regular write sequence to the Flash requires a minimum voltage to operate correctly. Secondly,
the CPU itself can execute instructions incorrectly, if the supply voltage for executing instructions
is too low.
Flash corruption can easily be avoided by following these design recommendations (one is
sufficient):
1. If there is no need for a Boot Loader update in the system, program the Boot Loader Lock
bits to prevent any Boot Loader software updates.
2. Keep the AVR RESET active (low) during periods of insufficient power supply voltage.
This can be done by enabling the internal Brown-out Detector (BOD) if the operating volt-
age matches the detection level. If not, an external low VCC reset protection circuit can be
used. If a reset occurs while a write operation is in progress, the write operation will be
completed provided that the power supply voltage is sufficient.
3. Keep the AVR core in Power-down sleep mode during periods of low VCC. This will pre-
vent the CPU from attempting to decode and execute instructions, effectively protecting
the SPMCSR Register and thus the Flash from unintentional writes.

26.8.12 Programming Time for Flash when Using SPM

The calibrated RC Oscillator is used to time Flash accesses. Table 26-6 shows the typical pro-
gramming time for Flash accesses from the CPU.

Table 26-6. SPM Programming Time(1)

Symbol Min Programming Time Max Programming Time
Flash write (Page Erase, Page Write, and
3.7 ms 4.5 ms
write Lock bits by SPM)

Note: 1. Minimum and maximum programming time is per individual operation.

26.8.13 Simple Assembly Code Example for a Boot Loader

;-the routine writes one page of data from RAM to Flash
; the first data location in RAM is pointed to by the Y pointer
; the first data location in Flash is pointed to by the Z-pointer
;-error handling is not included

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;-the routine must be placed inside the Boot space

; (at least the Do_spm sub routine). Only code inside NRWW section can
; be read during Self-Programming (Page Erase and Page Write).
;-registers used: r0, r1, temp1 (r16), temp2 (r17), looplo (r24),
; loophi (r25), spmcrval (r20)
; storing and restoring of registers is not included in the routine
; register usage can be optimized at the expense of code size
;-It is assumed that either the interrupt table is moved to the Boot
; loader section or that the interrupts are disabled.
.equ PAGESIZEB = PAGESIZE*2 ;PAGESIZEB is page size in BYTES, not words
.org SMALLBOOTSTART
Write_page:
; Page Erase
ldi spmcrval, (1<<PGERS) | (1<<SELFPRGEN)
call Do_spm

; re-enable the RWW section

ldi spmcrval, (1<<RWWSRE) | (1<<SELFPRGEN)
call Do_spm

; transfer data from RAM to Flash page buffer

ldi looplo, low(PAGESIZEB) ;init loop variable
ldi loophi, high(PAGESIZEB) ;not required for PAGESIZEB<=256
Wrloop:
ld r0, Y+
ld r1, Y+
ldi spmcrval, (1<<SELFPRGEN)
call Do_spm
adiw ZH:ZL, 2
sbiw loophi:looplo, 2 ;use subi for PAGESIZEB<=256
brne Wrloop

; execute Page Write

subi ZL, low(PAGESIZEB) ;restore pointer
sbci ZH, high(PAGESIZEB) ;not required for PAGESIZEB<=256
ldi spmcrval, (1<<PGWRT) | (1<<SELFPRGEN)
call Do_spm

; re-enable the RWW section

ldi spmcrval, (1<<RWWSRE) | (1<<SELFPRGEN)
call Do_spm

; read back and check, optional

ldi looplo, low(PAGESIZEB) ;init loop variable
ldi loophi, high(PAGESIZEB) ;not required for PAGESIZEB<=256
subi YL, low(PAGESIZEB) ;restore pointer
sbci YH, high(PAGESIZEB)
Rdloop:
lpm r0, Z+
ld r1, Y+
cpse r0, r1
jmp Error
sbiw loophi:looplo, 1 ;use subi for PAGESIZEB<=256
brne Rdloop

; return to RWW section

; verify that RWW section is safe to read
Return:
in temp1, SPMCSR

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sbrs temp1, RWWSB ; If RWWSB is set, the RWW section is not ready yet
ret
; re-enable the RWW section
ldi spmcrval, (1<<RWWSRE) | (1<<SELFPRGEN)
call Do_spm
rjmp Return

Do_spm:
; check for previous SPM complete
Wait_spm:
in temp1, SPMCSR
sbrc temp1, SELFPRGEN
rjmp Wait_spm
; input: spmcrval determines SPM action
; disable interrupts if enabled, store status
in temp2, SREG
cli
; check that no EEPROM write access is present
Wait_ee:
sbic EECR, EEPE
rjmp Wait_ee
; SPM timed sequence
out SPMCSR, spmcrval
spm
; restore SREG (to enable interrupts if originally enabled)
out SREG, temp2
ret

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26.8.14 ATmega88PA Boot Loader Parameters

In Table 26-7 through Table 26-9, the parameters used in the description of the self programming are given.

Table 26-7. Boot Size Configuration, ATmega88PA

Boot
Application Loader End
Boot Flash Flash Application Boot Reset Address (Start Boot Loader
BOOTSZ1 BOOTSZ0 Size Pages Section Section Section Section)

1 1 128 words 4 0x000 - 0xF7F 0xF80 - 0xFFF 0xF7F 0xF80

1 0 256 words 8 0x000 - 0xEFF 0xF00 - 0xFFF 0xEFF 0xF00

0 1 512 words 16 0x000 - 0xDFF 0xE00 - 0xFFF 0xDFF 0xE00

0 0 1024 words 32 0x000 - 0xBFF 0xC00 - 0xFFF 0xBFF 0xC00

Note: The different BOOTSZ Fuse configurations are shown in Figure 26-2 on page 280.

Table 26-8. Read-While-Write Limit, ATmega88PA

Section Pages Address
Read-While-Write section (RWW) 96 0x000 - 0xBFF
No Read-While-Write section (NRWW) 32 0xC00 - 0xFFF
For details about these two section, see ”NRWW – No Read-While-Write Section” on page 278 and ”RWW – Read-While-
Write Section” on page 278

Table 26-9. Explanation of Different Variables used in Figure 26-3 and the Mapping to the Z-pointer, ATmega88PA
Corresponding
Variable Z-value(1) Description
Most significant bit in the Program Counter. (The Program Counter is
PCMSB 11
12 bits PC[11:0])
Most significant bit which is used to address the words within one
PAGEMSB 4
page (32 words in a page requires 5 bits PC [4:0]).
Bit in Z-register that is mapped to PCMSB. Because Z0 is not used,
ZPCMSB Z12
the ZPCMSB equals PCMSB + 1.
Bit in Z-register that is mapped to PAGEMSB. Because Z0 is not
ZPAGEMSB Z5
used, the ZPAGEMSB equals PAGEMSB + 1.
Program counter page address: Page select, for page erase and
PCPAGE PC[11:5] Z12:Z6
page write
Program counter word address: Word select, for filling temporary
PCWORD PC[4:0] Z5:Z1
buffer (must be zero during page write operation)

Note: 1. Z15:Z13: always ignored

Z0: should be zero for all SPM commands, byte select for the LPM instruction.
See ”Addressing the Flash During Self-Programming” on page 282 for details about the use of Z-pointer during Self-
Programming.

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26.8.15 ATmega168PA Boot Loader Parameters

In Table 26-10 through Table 26-12, the parameters used in the description of the self programming are given.

Table 26-10. Boot Size Configuration, ATmega168PA

Boot
Application Loader End
Boot Flash Flash Application Boot Reset Address (Start Boot
BOOTSZ1 BOOTSZ0 Size Pages Section Section Section Loader Section)
1 1 128 words 2 0x0000 - 0x1F7F 0x1F80 - 0x1FFF 0x1F7F 0x1F80

1 0 256 words 4 0x0000 - 0x1EFF 0x1F00 - 0x1FFF 0x1EFF 0x1F00

0 1 512 words 8 0x0000 - 0x1DFF 0x1E00 - 0x1FFF 0x1DFF 0x1E00

0 0 1024 words 16 0x0000 - 0x1BFF 0x1C00 - 0x1FFF 0x1BFF 0x1C00

Note: The different BOOTSZ Fuse configurations are shown in Figure 26-2 on page 280.

Table 26-11. Read-While-Write Limit, ATmega168PA

Section Pages Address
Read-While-Write section (RWW) 112 0x0000 - 0x1BFF
No Read-While-Write section (NRWW) 16 0x1C00 - 0x1FFF
For details about these two section, see ”NRWW – No Read-While-Write Section” on page 278 and ”RWW – Read-While-
Write Section” on page 278

Table 26-12. Explanation of Different Variables used in Figure 26-3 and the Mapping to the Z-pointer, ATmega168PA
Corresponding
Variable Z-value(1) Description
Most significant bit in the Program Counter. (The Program Counter
PCMSB 12
is 13 bits PC[12:0])
Most significant bit which is used to address the words within
PAGEMSB 5
one page (64 words in a page requires 6 bits PC [5:0])
Bit in Z-register that is mapped to PCMSB. Because Z0 is not used,
ZPCMSB Z13
the ZPCMSB equals PCMSB + 1.
Bit in Z-register that is mapped to PAGEMSB. Because Z0 is not
ZPAGEMSB Z6
used, the ZPAGEMSB equals PAGEMSB + 1.
Program counter page address: Page select, for page erase and
PCPAGE PC[12:6] Z13:Z7
page write
Program counter word address: Word select, for filling temporary
PCWORD PC[5:0] Z6:Z1
buffer (must be zero during page write operation)

Note: 1. Z15:Z14: always ignored

Z0: should be zero for all SPM commands, byte select for the LPM instruction.
See ”Addressing the Flash During Self-Programming” on page 282 for details about the use of Z-pointer during Self-
Programming.

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26.8.16 ATmega328P Boot Loader Parameters

In Table 26-13 through Table 26-15, the parameters used in the description of the self programming are given.

Table 26-13. Boot Size Configuration, ATmega328P

Boot
Application Loader End
Boot Flash Flash Application Boot Reset Address (Start Boot
BOOTSZ1 BOOTSZ0 Size Pages Section Section Section Loader Section)
1 1 256 words 4 0x0000 - 0x3EFF 0x3F00 - 0x3FFF 0x3EFF 0x3F00

1 0 512 words 8 0x0000 - 0x3DFF 0x3E00 - 0x3FFF 0x3DFF 0x3E00

0 1 1024 words 16 0x0000 - 0x3BFF 0x3C00 - 0x3FFF 0x3BFF 0x3C00

0 0 2048 words 32 0x0000 - 0x37FF 0x3800 - 0x3FFF 0x37FF 0x3800

Note: The different BOOTSZ Fuse configurations are shown in Figure 26-2 on page 280.

Table 26-14. Read-While-Write Limit, ATmega328P

Section Pages Address
Read-While-Write section (RWW) 224 0x0000 - 0x37FF
No Read-While-Write section (NRWW) 32 0x3800 - 0x3FFF
For details about these two section, see ”NRWW – No Read-While-Write Section” on page 278 and ”RWW – Read-While-
Write Section” on page 278.

Table 26-15. Explanation of Different Variables used in Figure 26-3 and the Mapping to the Z-pointer, ATmega328P
Corresponding
Variable Z-value(1) Description
Most significant bit in the Program Counter. (The Program Counter
PCMSB 13
is 14 bits PC[13:0])
Most significant bit which is used to address the words within
PAGEMSB 5
one page (64 words in a page requires 6 bits PC [5:0])
Bit in Z-register that is mapped to PCMSB. Because Z0 is not used,
ZPCMSB Z14
the ZPCMSB equals PCMSB + 1.
Bit in Z-register that is mapped to PAGEMSB. Because Z0 is not
ZPAGEMSB Z6
used, the ZPAGEMSB equals PAGEMSB + 1.
Program counter page address: Page select, for page erase and
PCPAGE PC[13:6] Z14:Z7
page write
Program counter word address: Word select, for filling temporary
PCWORD PC[5:0] Z6:Z1
buffer (must be zero during page write operation)

Note: 1. Z15: always ignored

Z0: should be zero for all SPM commands, byte select for the LPM instruction.
See ”Addressing the Flash During Self-Programming” on page 282 for details about the use of Z-pointer during Self-
Programming.

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26.9 Register Description

26.9.1 SPMCSR – Store Program Memory Control and Status Register

The Store Program Memory Control and Status Register contains the control bits needed to con-
trol the Boot Loader operations.
Bit 7 6 5 4 3 2 1 0
0x37 (0x57) SPMIE RWWSB – RWWSRE BLBSET PGWRT PGERS SELFPRGEN SPMCSR
Read/Write R/W R R R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0

• Bit 7 – SPMIE: SPM Interrupt Enable

When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM
ready interrupt will be enabled. The SPM ready Interrupt will be executed as long as the SELF-
PRGEN bit in the SPMCSR Register is cleared.

• Bit 6 – RWWSB: Read-While-Write Section Busy

When a Self-Programming (Page Erase or Page Write) operation to the RWW section is initi-
ated, the RWWSB will be set (one) by hardware. When the RWWSB bit is set, the RWW section
cannot be accessed. The RWWSB bit will be cleared if the RWWSRE bit is written to one after a
Self-Programming operation is completed. Alternatively the RWWSB bit will automatically be
cleared if a page load operation is initiated.

• Bit 5 – Res: Reserved Bit

This bit is a reserved bit in the ATmega48PA/88PA/168PA/328P and always read as zero.

• Bit 4 – RWWSRE: Read-While-Write Section Read Enable

When programming (Page Erase or Page Write) to the RWW section, the RWW section is
blocked for reading (the RWWSB will be set by hardware). To re-enable the RWW section, the
user software must wait until the programming is completed (SELFPRGEN will be cleared).
Then, if the RWWSRE bit is written to one at the same time as SELFPRGEN, the next SPM
instruction within four clock cycles re-enables the RWW section. The RWW section cannot be
re-enabled while the Flash is busy with a Page Erase or a Page Write (SELFPRGEN is set). If
the RWWSRE bit is written while the Flash is being loaded, the Flash load operation will abort
and the data loaded will be lost.

• Bit 3 – BLBSET: Boot Lock Bit Set

If this bit is written to one at the same time as SELFPRGEN, the next SPM instruction within four
clock cycles sets Boot Lock bits and Memory Lock bits, according to the data in R0. The data in
R1 and the address in the Z-pointer are ignored. The BLBSET bit will automatically be cleared
upon completion of the Lock bit set, or if no SPM instruction is executed within four clock cycles.
An LPM instruction within three cycles after BLBSET and SELFPRGEN are set in the SPMCSR
Register, will read either the Lock bits or the Fuse bits (depending on Z0 in the Z-pointer) into the
destination register. See ”Reading the Fuse and Lock Bits from Software” on page 284 for
details.

• Bit 2 – PGWRT: Page Write

If this bit is written to one at the same time as SELFPRGEN, the next SPM instruction within four
clock cycles executes Page Write, with the data stored in the temporary buffer. The page
address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The

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PGWRT bit will auto-clear upon completion of a Page Write, or if no SPM instruction is executed
within four clock cycles. The CPU is halted during the entire Page Write operation if the NRWW
section is addressed.

• Bit 1 – PGERS: Page Erase

If this bit is written to one at the same time as SELFPRGEN, the next SPM instruction within four
clock cycles executes Page Erase. The page address is taken from the high part of the Z-
pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a
Page Erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted dur-
ing the entire Page Write operation if the NRWW section is addressed.

• Bit 0 – SELFPRGEN: Self Programming Enable

This bit enables the SPM instruction for the next four clock cycles. If written to one together with
either RWWSRE, BLBSET, PGWRT or PGERS, the following SPM instruction will have a spe-
cial meaning, see description above. If only SELFPRGEN is written, the following SPM
instruction will store the value in R1:R0 in the temporary page buffer addressed by the Z-pointer.
The LSB of the Z-pointer is ignored. The SELFPRGEN bit will auto-clear upon completion of an
SPM instruction, or if no SPM instruction is executed within four clock cycles. During Page Erase
and Page Write, the SELFPRGEN bit remains high until the operation is completed.
Writing any other combination than “10001”, “01001”, “00101”, “00011” or “00001” in the lower
five bits will have no effect.

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27. Memory Programming

27.1 Program And Data Memory Lock Bits

The ATmega88PA/168PA/328P provides six Lock bits which can be left unprogrammed (“1”) or
can be programmed (“0”) to obtain the additional features listed in Table 27-2. The Lock bits can
only be erased to “1” with the Chip Erase command. The ATmega48PA has no separate Boot
Loader section. The SPM instruction is enabled for the whole Flash if the SELFPRGEN fuse is
programmed (“0”), otherwise it is disabled.

Table 27-1. Lock Bit Byte(1)

Lock Bit Byte Bit No Description Default Value
7 – 1 (unprogrammed)
6 – 1 (unprogrammed)
BLB12(2) 5 Boot Lock bit 1 (unprogrammed)
(2)
BLB11 4 Boot Lock bit 1 (unprogrammed)
(2)
BLB02 3 Boot Lock bit 1 (unprogrammed)
BLB01(2) 2 Boot Lock bit 1 (unprogrammed)
LB2 1 Lock bit 1 (unprogrammed)
LB1 0 Lock bit 1 (unprogrammed)

Notes: 1. “1” means unprogrammed, “0” means programmed.

2. Only on ATmega88PA/168PA/328P.

Table 27-2. Lock Bit Protection Modes(1)(2)

Memory Lock Bits Protection Type
LB Mode LB2 LB1
1 1 1 No memory lock features enabled.
Further programming of the Flash and EEPROM is disabled in
2 1 0 Parallel and Serial Programming mode. The Fuse bits are
locked in both Serial and Parallel Programming mode.(1)
Further programming and verification of the Flash and EEPROM
is disabled in Parallel and Serial Programming mode. The Boot
3 0 0
Lock bits and Fuse bits are locked in both Serial and Parallel
Programming mode.(1)
Notes: 1. Program the Fuse bits and Boot Lock bits before programming the LB1 and LB2.
2. “1” means unprogrammed, “0” means programmed

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Table 27-3. Lock Bit Protection Modes(1)(2). Only ATmega88PA/168PA/328P.

BLB0 Mode BLB02 BLB01
No restrictions for SPM or LPM accessing the Application
1 1 1
section.
2 1 0 SPM is not allowed to write to the Application section.
SPM is not allowed to write to the Application section, and LPM
executing from the Boot Loader section is not allowed to read
3 0 0 from the Application section. If Interrupt Vectors are placed in
the Boot Loader section, interrupts are disabled while executing
from the Application section.
LPM executing from the Boot Loader section is not allowed to
read from the Application section. If Interrupt Vectors are placed
4 0 1
in the Boot Loader section, interrupts are disabled while
executing from the Application section.
BLB1 Mode BLB12 BLB11
No restrictions for SPM or LPM accessing the Boot Loader
1 1 1
section.
2 1 0 SPM is not allowed to write to the Boot Loader section.
SPM is not allowed to write to the Boot Loader section, and LPM
executing from the Application section is not allowed to read
3 0 0 from the Boot Loader section. If Interrupt Vectors are placed in
the Application section, interrupts are disabled while executing
from the Boot Loader section.
LPM executing from the Application section is not allowed to
read from the Boot Loader section. If Interrupt Vectors are
4 0 1
placed in the Application section, interrupts are disabled while
executing from the Boot Loader section.
Notes: 1. Program the Fuse bits and Boot Lock bits before programming the LB1 and LB2.
2. “1” means unprogrammed, “0” means programmed

27.2 Fuse Bits

The ATmega48PA/88PA/168PA/328P has three Fuse bytes. Table 27-5 - Table 27-9 describe
briefly the functionality of all the fuses and how they are mapped into the Fuse bytes. Note that
the fuses are read as logical zero, “0”, if they are programmed.

Table 27-4. Extended Fuse Byte for ATmega48PA

Extended Fuse Byte Bit No Description Default Value
– 7 – 1
– 6 – 1
– 5 – 1
– 4 – 1
– 3 – 1
– 2 – 1
– 1 – 1
SELFPRGEN 0 Self Programming Enable 1 (unprogrammed)

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Table 27-5. Extended Fuse Byte for ATmega88PA/168PA

Extended Fuse Byte Bit No Description Default Value
– 7 – 1
– 6 – 1
– 5 – 1
– 4 – 1
– 3 – 1
Select Boot Size
(see
BOOTSZ1 2 Table 26-7 on page 289 and 0 (programmed)(1)
Table 26-10 on page 290
for details)
Select Boot Size
(see
BOOTSZ0 1 Table 26-7 on page 289 and 0 (programmed)(1)
Table 26-10 on page 290
for details)
BOOTRST 0 Select Reset Vector 1 (unprogrammed)

Note: 1. The default value of BOOTSZ[1:0] results in maximum Boot Size. See ”Pin Name Mapping” on
page 300.

Table 27-6. Extended Fuse Byte for ATmega328P

Extended Fuse Byte Bit No Description Default Value
– 7 – 1
– 6 – 1
– 5 – 1
– 4 – 1
– 3 – 1
Brown-out Detector trigger
BODLEVEL2(1) 2 1 (unprogrammed)
level
Brown-out Detector trigger
BODLEVEL1(1) 1 1 (unprogrammed)
level
Brown-out Detector trigger
BODLEVEL0(1) 0 1 (unprogrammed)
level

Note: 1. See Table 28-4 on page 318 for BODLEVEL Fuse decoding.

Table 27-7. Fuse High Byte for ATmega48PA/88PA/168PA

High Fuse Byte Bit No Description Default Value
(1)
RSTDISBL 7 External Reset Disable 1 (unprogrammed)
DWEN 6 debugWIRE Enable 1 (unprogrammed)
Enable Serial Program and 0 (programmed, SPI
SPIEN(2) 5
Data Downloading programming enabled)

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Table 27-7. Fuse High Byte for ATmega48PA/88PA/168PA (Continued)

High Fuse Byte Bit No Description Default Value
(3)
WDTON 4 Watchdog Timer Always On 1 (unprogrammed)
EEPROM memory is
1 (unprogrammed), EEPROM
EESAVE 3 preserved through the Chip
not reserved
Erase
Brown-out Detector trigger
BODLEVEL2(4) 2 1 (unprogrammed)
level
Brown-out Detector trigger
BODLEVEL1(4) 1 1 (unprogrammed)
level
Brown-out Detector trigger
BODLEVEL0(4) 0 1 (unprogrammed)
level
Notes: 1. See ”Alternate Functions of Port C” on page 85 for description of RSTDISBL Fuse.
2. The SPIEN Fuse is not accessible in serial programming mode.
3. See ”WDTCSR – Watchdog Timer Control Register” on page 54 for details.
4. See Table 28-4 on page 318 for BODLEVEL Fuse decoding.

Table 27-8. Fuse High Byte for ATmega328P

High Fuse Byte Bit No Description Default Value
RSTDISBL(1) 7 External Reset Disable 1 (unprogrammed)
DWEN 6 debugWIRE Enable 1 (unprogrammed)
Enable Serial Program and 0 (programmed, SPI
SPIEN(2) 5
Data Downloading programming enabled)
WDTON(3) 4 Watchdog Timer Always On 1 (unprogrammed)
EEPROM memory is
1 (unprogrammed), EEPROM
EESAVE 3 preserved through the Chip
not reserved
Erase
Select Boot Size
(see
Table 26-7 on page 289,
BOOTSZ1 2 0 (programmed)(4)
Table 26-10 on page 290 and
Table 26-13 on page 291
for details)
Select Boot Size
(see
Table 26-7 on page 289,
BOOTSZ0 1 0 (programmed)(4)
Table 26-10 on page 290 and
Table 26-13 on page 291
for details)
BOOTRST 0 Select Reset Vector 1 (unprogrammed)

Notes: 1. See ”Alternate Functions of Port C” on page 85 for description of RSTDISBL Fuse.
2. The SPIEN Fuse is not accessible in serial programming mode.
3. See ”WDTCSR – Watchdog Timer Control Register” on page 54 for details.
4. The default value of BOOTSZ[1:0] results in maximum Boot Size. See ”Pin Name Mapping” on
page 300.

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Table 27-9. Fuse Low Byte

Low Fuse Byte Bit No Description Default Value
CKDIV8(4) 7 Divide clock by 8 0 (programmed)
(3)
CKOUT 6 Clock output 1 (unprogrammed)
SUT1 5 Select start-up time 1 (unprogrammed)(1)
SUT0 4 Select start-up time 0 (programmed)(1)
CKSEL3 3 Select Clock source 0 (programmed)(2)
CKSEL2 2 Select Clock source 0 (programmed)(2)
CKSEL1 1 Select Clock source 1 (unprogrammed)(2)
CKSEL0 0 Select Clock source 0 (programmed)(2)

Note: 1. The default value of SUT1..0 results in maximum start-up time for the default clock source.
See Table 8-12 on page 33 for details.
2. The default setting of CKSEL3..0 results in internal RC Oscillator @ 8 MHz. See Table 8-11 on
page 33 for details.
3. The CKOUT Fuse allows the system clock to be output on PORTB0. See ”Clock Output Buffer”
on page 35 for details.
4. See ”System Clock Prescaler” on page 35 for details.
The status of the Fuse bits is not affected by Chip Erase. Note that the Fuse bits are locked if
Lock bit1 (LB1) is programmed. Program the Fuse bits before programming the Lock bits.

27.2.1 Latching of Fuses

The fuse values are latched when the device enters programming mode and changes of the
fuse values will have no effect until the part leaves Programming mode. This does not apply to
the EESAVE Fuse which will take effect once it is programmed. The fuses are also latched on
Power-up in Normal mode.

27.3 Signature Bytes

All Atmel microcontrollers have a three-byte signature code which identifies the device. This
code can be read in both serial and parallel mode, also when the device is locked. The three
bytes reside in a separate address space. For the ATmega48PA/88PA/168PA/328P the signa-
ture bytes are given in Table 27-10.

Table 27-10. Device ID

Signature Bytes Address
Part 0x000 0x001 0x002
ATmega48PA 0x1E 0x92 0x0A
ATmega88PA 0x1E 0x93 0x0F
ATmega168PA 0x1E 0x94 0x0B
ATmega328P 0x1E 0x95 0x0F

27.4 Calibration Byte

The ATmega48PA/88PA/168PA/328P has a byte calibration value for the Internal RC Oscillator.
This byte resides in the high byte of address 0x000 in the signature address space. During reset,

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this byte is automatically written into the OSCCAL Register to ensure correct frequency of the
calibrated RC Oscillator.

27.5 Page Size

Table 27-11. No. of Words in a Page and No. of Pages in the Flash
No. of
Device Flash Size Page Size PCWORD Pages PCPAGE PCMSB
2K words
ATmega48PA 32 words PC[4:0] 64 PC[10:5] 10
(4K bytes)
4K words
ATmega88PA 32 words PC[4:0] 128 PC[11:5] 11
(8K bytes)
8K words
ATmega168PA 64 words PC[5:0] 128 PC[12:6] 12
(16K bytes)

16K words
ATmega328P 64 words PC[5:0] 256 PC[13:6] 13
(32K bytes)

Table 27-12. No. of Words in a Page and No. of Pages in the EEPROM
EEPROM Page No. of
Device Size Size PCWORD Pages PCPAGE EEAMSB
ATmega48PA 256 bytes 4 bytes EEA[1:0] 64 EEA[7:2] 7
ATmega88PA 512 bytes 4 bytes EEA[1:0] 128 EEA[8:2] 8
ATmega168PA 512 bytes 4 bytes EEA[1:0] 128 EEA[8:2] 8
ATmega328P 1K bytes 4 bytes EEA[1:0] 256 EEA[9:2] 9

27.6 Parallel Programming Parameters, Pin Mapping, and Commands

This section describes how to parallel program and verify Flash Program memory, EEPROM
Data memory, Memory Lock bits, and Fuse bits in the ATmega48PA/88PA/168PA/328P. Pulses
are assumed to be at least 250 ns unless otherwise noted.

27.6.1 Signal Names

In this section, some pins of the ATmega48PA/88PA/168PA/328P are referenced by signal
names describing their functionality during parallel programming, see Figure 27-1 and Table 27-
13. Pins not described in the following table are referenced by pin names.
The XA1/XA0 pins determine the action executed when the XTAL1 pin is given a positive pulse.
The bit coding is shown in Table 27-15.
When pulsing WR or OE, the command loaded determines the action executed. The different
Commands are shown in Table 27-16.

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Figure 27-1. Parallel Programming

+4.5 - 5.5V
RDY/BSY PD1
VCC
OE PD2 +4.5 - 5.5V

WR PD3 AVCC

BS1 PD4 PC[1:0]:PB[5:0] DATA

XA0 PD5

XA1 PD6

PAGEL PD7

+12 V RESET

BS2 PC2

XTAL1

GND

Note: VCC - 0.3V < AVCC < VCC + 0.3V, however, AVCC should always be within 4.5 - 5.5V

Table 27-13. Pin Name Mapping

Signal Name in
Programming Mode Pin Name I/O Function
0: Device is busy programming, 1: Device is
RDY/BSY PD1 O
ready for new command
OE PD2 I Output Enable (Active low)
WR PD3 I Write Pulse (Active low)
Byte Select 1 (“0” selects Low byte, “1” selects
BS1 PD4 I
High byte)
XA0 PD5 I XTAL Action Bit 0
XA1 PD6 I XTAL Action Bit 1
Program memory and EEPROM Data Page
PAGEL PD7 I
Load
Byte Select 2 (“0” selects Low byte, “1” selects
BS2 PC2 I
2’nd High byte)
DATA {PC[1:0]: PB[5:0]} I/O Bi-directional Data bus (Output when OE is low)

Table 27-14. Pin Values Used to Enter Programming Mode

Pin Symbol Value
PAGEL Prog_enable[3] 0
XA1 Prog_enable[2] 0
XA0 Prog_enable[1] 0
BS1 Prog_enable[0] 0

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Table 27-15. XA1 and XA0 Coding

XA1 XA0 Action when XTAL1 is Pulsed
0 0 Load Flash or EEPROM Address (High or low address byte determined by BS1).
0 1 Load Data (High or Low data byte for Flash determined by BS1).
1 0 Load Command
1 1 No Action, Idle

Table 27-16. Command Byte Bit Coding

Command Byte Command Executed
1000 0000 Chip Erase
0100 0000 Write Fuse bits
0010 0000 Write Lock bits
0001 0000 Write Flash
0001 0001 Write EEPROM
0000 1000 Read Signature Bytes and Calibration byte
0000 0100 Read Fuse and Lock bits
0000 0010 Read Flash
0000 0011 Read EEPROM

27.7 Parallel Programming

27.7.1 Enter Programming Mode

The following algorithm puts the device in Parallel (High-voltage) Programming mode:
1. Set Prog_enable pins listed in Table 27-14 on page 300 to “0000”, RESET pin to 0V and
VCC to 0V.
2. Apply 4.5 - 5.5V between VCC and GND.
Ensure that VCC reaches at least 1.8V within the next 20 µs.
3. Wait 20 - 60 µs, and apply 11.5 - 12.5V to RESET.
4. Keep the Prog_enable pins unchanged for at least 10µs after the High-voltage has been
applied to ensure the Prog_enable Signature has been latched.
5. Wait at least 300 µs before giving any parallel programming commands.
6. Exit Programming mode by power the device down or by bringing RESET pin to 0V.
If the rise time of the VCC is unable to fulfill the requirements listed above, the following alterna-
tive algorithm can be used.
1. Set Prog_enable pins listed in Table 27-14 on page 300 to “0000”, RESET pin to 0V and
VCC to 0V.
2. Apply 4.5 - 5.5V between VCC and GND.
3. Monitor VCC, and as soon as VCC reaches 0.9 - 1.1V, apply 11.5 - 12.5V to RESET.

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4. Keep the Prog_enable pins unchanged for at least 10µs after the High-voltage has been
applied to ensure the Prog_enable Signature has been latched.
5. Wait until VCC actually reaches 4.5 -5.5V before giving any parallel programming
commands.
6. Exit Programming mode by power the device down or by bringing RESET pin to 0V.

27.7.2 Considerations for Efficient Programming

The loaded command and address are retained in the device during programming. For efficient
programming, the following should be considered.
• The command needs only be loaded once when writing or reading multiple memory locations.
• Skip writing the data value 0xFF, that is the contents of the entire EEPROM (unless the
EESAVE Fuse is programmed) and Flash after a Chip Erase.
• Address high byte needs only be loaded before programming or reading a new 256 word
window in Flash or 256 byte EEPROM. This consideration also applies to Signature bytes
reading.

27.7.3 Chip Erase

The Chip Erase will erase the Flash and EEPROM(1) memories plus Lock bits. The Lock bits are
not reset until the program memory has been completely erased. The Fuse bits are not
changed. A Chip Erase must be performed before the Flash and/or EEPROM are
reprogrammed.
Note: 1. The EEPRPOM memory is preserved during Chip Erase if the EESAVE Fuse is programmed.
Load Command “Chip Erase”
1. Set XA1, XA0 to “10”. This enables command loading.
2. Set BS1 to “0”.
3. Set DATA to “1000 0000”. This is the command for Chip Erase.
4. Give XTAL1 a positive pulse. This loads the command.
5. Give WR a negative pulse. This starts the Chip Erase. RDY/BSY goes low.
6. Wait until RDY/BSY goes high before loading a new command.

27.7.4 Programming the Flash

The Flash is organized in pages, see Table 27-11 on page 299. When programming the Flash,
the program data is latched into a page buffer. This allows one page of program data to be pro-
grammed simultaneously. The following procedure describes how to program the entire Flash
memory:
A. Load Command “Write Flash”
1. Set XA1, XA0 to “10”. This enables command loading.
2. Set BS1 to “0”.
3. Set DATA to “0001 0000”. This is the command for Write Flash.
4. Give XTAL1 a positive pulse. This loads the command.
B. Load Address Low byte
1. Set XA1, XA0 to “00”. This enables address loading.
2. Set BS1 to “0”. This selects low address.
3. Set DATA = Address low byte (0x00 - 0xFF).

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4. Give XTAL1 a positive pulse. This loads the address low byte.
C. Load Data Low Byte
1. Set XA1, XA0 to “01”. This enables data loading.
2. Set DATA = Data low byte (0x00 - 0xFF).
3. Give XTAL1 a positive pulse. This loads the data byte.
D. Load Data High Byte
1. Set BS1 to “1”. This selects high data byte.
2. Set XA1, XA0 to “01”. This enables data loading.
3. Set DATA = Data high byte (0x00 - 0xFF).
4. Give XTAL1 a positive pulse. This loads the data byte.
E. Latch Data
1. Set BS1 to “1”. This selects high data byte.
2. Give PAGEL a positive pulse. This latches the data bytes. (See Figure 27-3 for signal
waveforms)
F. Repeat B through E until the entire buffer is filled or until all data within the page is loaded.
While the lower bits in the address are mapped to words within the page, the higher bits address
the pages within the FLASH. This is illustrated in Figure 27-2 on page 304. Note that if less than
eight bits are required to address words in the page (pagesize < 256), the most significant bit(s)
in the address low byte are used to address the page when performing a Page Write.
G. Load Address High byte
1. Set XA1, XA0 to “00”. This enables address loading.
2. Set BS1 to “1”. This selects high address.
3. Set DATA = Address high byte (0x00 - 0xFF).
4. Give XTAL1 a positive pulse. This loads the address high byte.
H. Program Page
1. Give WR a negative pulse. This starts programming of the entire page of data. RDY/BSY
goes low.
2. Wait until RDY/BSY goes high (See Figure 27-3 for signal waveforms).
I. Repeat B through H until the entire Flash is programmed or until all data has been
programmed.
J. End Page Programming
1. 1. Set XA1, XA0 to “10”. This enables command loading.
2. Set DATA to “0000 0000”. This is the command for No Operation.
3. Give XTAL1 a positive pulse. This loads the command, and the internal write signals are
reset.

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Figure 27-2. Addressing the Flash Which is Organized in Pages(1)

PCMSB PAGEMSB
PROGRAM
PCPAGE PCWORD
COUNTER

PAGE ADDRESS WORD ADDRESS

WITHIN THE FLASH WITHIN A PAGE

PROGRAM MEMORY PAGE PCWORD[PAGEMSB:0]:

PAGE 00
INSTRUCTION WORD

01

02

PAGEEND

Note: 1. PCPAGE and PCWORD are listed in Table 27-11 on page 299.

Figure 27-3. Programming the Flash Waveforms(1)

F

A B C D E B C D E G H
0x10 ADDR. LOW DATA LOW DATA HIGH XX ADDR. LOW DATA LOW DATA HIGH XX ADDR. HIGH XX
DATA

XA1

XA0

BS1

XTAL1

WR

RDY/BSY

RESET +12V

OE

PAGEL

BS2

Note: 1. “XX” is don’t care. The letters refer to the programming description above.

27.7.5 Programming the EEPROM

The EEPROM is organized in pages, see Table 27-12 on page 299. When programming the
EEPROM, the program data is latched into a page buffer. This allows one page of data to be
programmed simultaneously. The programming algorithm for the EEPROM data memory is as
follows (refer to ”Programming the Flash” on page 302 for details on Command, Address and
Data loading):
1. A: Load Command “0001 0001”.
2. G: Load Address High Byte (0x00 - 0xFF).
3. B: Load Address Low Byte (0x00 - 0xFF).
4. C: Load Data (0x00 - 0xFF).

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5. E: Latch data (give PAGEL a positive pulse).

K: Repeat 3 through 5 until the entire buffer is filled.
L: Program EEPROM page
1. Set BS1 to “0”.
2. Give WR a negative pulse. This starts programming of the EEPROM page. RDY/BSY
goes low.
3. Wait until to RDY/BSY goes high before programming the next page (See Figure 27-4 for
signal waveforms).

Figure 27-4. Programming the EEPROM Waveforms

K

A G B C E B C E L
0x11 ADDR. HIGH ADDR. LOW DATA XX ADDR. LOW DATA XX
DATA

XA1

XA0

BS1

XTAL1

WR

RDY/BSY

RESET +12V

OE

PAGEL

BS2

27.7.6 Reading the Flash

The algorithm for reading the Flash memory is as follows (refer to ”Programming the Flash” on
page 302 for details on Command and Address loading):
1. A: Load Command “0000 0010”.
2. G: Load Address High Byte (0x00 - 0xFF).
3. B: Load Address Low Byte (0x00 - 0xFF).
4. Set OE to “0”, and BS1 to “0”. The Flash word low byte can now be read at DATA.
5. Set BS1 to “1”. The Flash word high byte can now be read at DATA.
6. Set OE to “1”.

27.7.7 Reading the EEPROM

The algorithm for reading the EEPROM memory is as follows (refer to ”Programming the Flash”
on page 302 for details on Command and Address loading):
1. A: Load Command “0000 0011”.
2. G: Load Address High Byte (0x00 - 0xFF).
3. B: Load Address Low Byte (0x00 - 0xFF).
4. Set OE to “0”, and BS1 to “0”. The EEPROM Data byte can now be read at DATA.
5. Set OE to “1”.

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27.7.8 Programming the Fuse Low Bits

The algorithm for programming the Fuse Low bits is as follows (refer to ”Programming the Flash”
on page 302 for details on Command and Data loading):
1. A: Load Command “0100 0000”.
2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.
3. Give WR a negative pulse and wait for RDY/BSY to go high.

27.7.9 Programming the Fuse High Bits

The algorithm for programming the Fuse High bits is as follows (refer to ”Programming the
Flash” on page 302 for details on Command and Data loading):
1. A: Load Command “0100 0000”.
2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.
3. Set BS1 to “1” and BS2 to “0”. This selects high data byte.
4. Give WR a negative pulse and wait for RDY/BSY to go high.
5. Set BS1 to “0”. This selects low data byte.

27.7.10 Programming the Extended Fuse Bits

The algorithm for programming the Extended Fuse bits is as follows (refer to ”Programming the
Flash” on page 302 for details on Command and Data loading):
1. 1. A: Load Command “0100 0000”.
2. 2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.
3. 3. Set BS1 to “0” and BS2 to “1”. This selects extended data byte.
4. 4. Give WR a negative pulse and wait for RDY/BSY to go high.
5. 5. Set BS2 to “0”. This selects low data byte.

Figure 27-5. Programming the FUSES Waveforms

Write Fuse Low byte Write Fuse high byte Write Extended Fuse byte

A C A C A C
0x40 DATA XX 0x40 DATA XX 0x40 DATA XX
DATA

XA1

XA0

BS1

BS2

XTAL1

WR

RDY/BSY

RESET +12V

OE

PAGEL

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27.7.11 Programming the Lock Bits

The algorithm for programming the Lock bits is as follows (refer to ”Programming the Flash” on
page 302 for details on Command and Data loading):
1. A: Load Command “0010 0000”.
2. C: Load Data Low Byte. Bit n = “0” programs the Lock bit. If LB mode 3 is programmed
(LB1 and LB2 is programmed), it is not possible to program the Boot Lock bits by any
External Programming mode.
3. Give WR a negative pulse and wait for RDY/BSY to go high.
The Lock bits can only be cleared by executing Chip Erase.

27.7.12 Reading the Fuse and Lock Bits

The algorithm for reading the Fuse and Lock bits is as follows (refer to ”Programming the Flash”
on page 302 for details on Command loading):
1. A: Load Command “0000 0100”.
2. Set OE to “0”, BS2 to “0” and BS1 to “0”. The status of the Fuse Low bits can now be
read at DATA (“0” means programmed).
3. Set OE to “0”, BS2 to “1” and BS1 to “1”. The status of the Fuse High bits can now be
read at DATA (“0” means programmed).
4. Set OE to “0”, BS2 to “1”, and BS1 to “0”. The status of the Extended Fuse bits can now
be read at DATA (“0” means programmed).
5. Set OE to “0”, BS2 to “0” and BS1 to “1”. The status of the Lock bits can now be read at
DATA (“0” means programmed).
6. Set OE to “1”.

Figure 27-6. Mapping Between BS1, BS2 and the Fuse and Lock Bits During Read

Fuse Low Byte 0

0
Extended Fuse Byte 1
DATA
BS2

Lock Bits 0
1

BS1
Fuse High Byte 1

BS2

27.7.13 Reading the Signature Bytes

The algorithm for reading the Signature bytes is as follows (refer to ”Programming the Flash” on
page 302 for details on Command and Address loading):
1. A: Load Command “0000 1000”.
2. B: Load Address Low Byte (0x00 - 0x02).
3. Set OE to “0”, and BS1 to “0”. The selected Signature byte can now be read at DATA.
4. Set OE to “1”.

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27.7.14 Reading the Calibration Byte

The algorithm for reading the Calibration byte is as follows (refer to ”Programming the Flash” on
page 302 for details on Command and Address loading):
1. A: Load Command “0000 1000”.
2. B: Load Address Low Byte, 0x00.
3. Set OE to “0”, and BS1 to “1”. The Calibration byte can now be read at DATA.
4. Set OE to “1”.

27.7.15 Parallel Programming Characteristics

For chracteristics of the Parallel Programming, see ”Parallel Programming Characteristics” on
page 324.

27.8 Serial Downloading

Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while
RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (out-
put). After RESET is set low, the Programming Enable instruction needs to be executed first
before program/erase operations can be executed. NOTE, in Table 27-17 on page 309, the pin
mapping for SPI programming is listed. Not all parts use the SPI pins dedicated for the internal
SPI interface.

Figure 27-7. Serial Programming and Verify(1)

+1.8 - 5.5V

VCC

+1.8 - 5.5V(2)
MOSI
AVCC
MISO

SCK

XTAL1

RESET

GND

Notes: 1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the
XTAL1 pin.
2. VCC - 0.3V < AVCC < VCC + 0.3V, however, AVCC should always be within 1.8 - 5.5V
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming
operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase
instruction. The Chip Erase operation turns the content of every memory location in both the
Program and EEPROM arrays into 0xFF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods
for the serial clock (SCK) input are defined as follows:
Low: > 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz
High: > 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz

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27.8.1 Serial Programming Pin Mapping

Table 27-17. Pin Mapping Serial Programming

Symbol Pins I/O Description
MOSI PB3 I Serial Data in
MISO PB4 O Serial Data out
SCK PB5 I Serial Clock

27.8.2 Serial Programming Algorithm

When writing serial data to the ATmega48PA/88PA/168PA/328P, data is clocked on the rising
edge of SCK.
When reading data from the ATmega48PA/88PA/168PA/328P, data is clocked on the falling
edge of SCK. See Figure 27-9 for timing details.
To program and verify the ATmega48PA/88PA/168PA/328P in the serial programming mode,
the following sequence is recommended (See Serial Programming Instruction set in Table 27-19
on page 310):
1. Power-up sequence:
Apply power between VCC and GND while RESET and SCK are set to “0”. In some sys-
tems, the programmer can not guarantee that SCK is held low during power-up. In this
case, RESET must be given a positive pulse of at least two CPU clock cycles duration
after SCK has been set to “0”.
2. Wait for at least 20 ms and enable serial programming by sending the Programming
Enable serial instruction to pin MOSI.
3. The serial programming instructions will not work if the communication is out of synchro-
nization. When in sync. the second byte (0x53), will echo back when issuing the third
byte of the Programming Enable instruction. Whether the echo is correct or not, all four
bytes of the instruction must be transmitted. If the 0x53 did not echo back, give RESET a
positive pulse and issue a new Programming Enable command.
4. The Flash is programmed one page at a time. The memory page is loaded one byte at a
time by supplying the 6 LSB of the address and data together with the Load Program
Memory Page instruction. To ensure correct loading of the page, the data low byte must
be loaded before data high byte is applied for a given address. The Program Memory
Page is stored by loading the Write Program Memory Page instruction with the 7 MSB of
the address. If polling (RDY/BSY) is not used, the user must wait at least tWD_FLASH before
issuing the next page (See Table 27-18). Accessing the serial programming interface
before the Flash write operation completes can result in incorrect programming.
5. A: The EEPROM array is programmed one byte at a time by supplying the address and
data together with the appropriate Write instruction. An EEPROM memory location is first
automatically erased before new data is written. If polling (RDY/BSY) is not used, the
user must wait at least tWD_EEPROM before issuing the next byte (See Table 27-18). In a
chip erased device, no 0xFFs in the data file(s) need to be programmed.
B: The EEPROM array is programmed one page at a time. The Memory page is loaded
one byte at a time by supplying the 6 LSB of the address and data together with the Load
EEPROM Memory Page instruction. The EEPROM Memory Page is stored by loading
the Write EEPROM Memory Page Instruction with the 7 MSB of the address. When using
EEPROM page access only byte locations loaded with the Load EEPROM Memory Page
instruction is altered. The remaining locations remain unchanged. If polling (RDY/BSY) is

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not used, the used must wait at least tWD_EEPROM before issuing the next byte (See Table
27-18). In a chip erased device, no 0xFF in the data file(s) need to be programmed.
6. Any memory location can be verified by using the Read instruction which returns the con-
tent at the selected address at serial output MISO.
7. At the end of the programming session, RESET can be set high to commence normal
operation.
8. Power-off sequence (if needed):
Set RESET to “1”.
Turn VCC power off.

Table 27-18. Typical Wait Delay Before Writing the Next Flash or EEPROM Location
Symbol Minimum Wait Delay
tWD_FLASH 4.5 ms
tWD_EEPROM 3.6 ms
tWD_ERASE 9.0 ms

27.8.3 Serial Programming Instruction set

Table 27-19 on page 310 and Figure 27-8 on page 312 describes the Instruction set.

Table 27-19. Serial Programming Instruction Set (Hexadecimal values)

Instruction Format
Instruction/Operation Byte 1 Byte 2 Byte 3 Byte4
Programming Enable $AC $53 $00 $00
Chip Erase (Program Memory/EEPROM) $AC $80 $00 $00
Poll RDY/BSY $F0 $00 $00 data byte out
Load Instructions
Load Extended Address byte(1) $4D $00 Extended adr $00
Load Program Memory Page, High byte $48 $00 adr LSB high data byte in
Load Program Memory Page, Low byte $40 $00 adr LSB low data byte in
Load EEPROM Memory Page (page access) $C1 $00 0000 000aa data byte in
Read Instructions
Read Program Memory, High byte $28 adr MSB adr LSB high data byte out
Read Program Memory, Low byte $20 adr MSB adr LSB low data byte out
Read EEPROM Memory $A0 0000 00aa aaaa aaaa data byte out
Read Lock bits $58 $00 $00 data byte out
Read Signature Byte $30 $00 0000 000aa data byte out
Read Fuse bits $50 $00 $00 data byte out
Read Fuse High bits $58 $08 $00 data byte out
Read Extended Fuse Bits $50 $08 $00 data byte out
Read Calibration Byte $38 $00 $00 data byte out

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Table 27-19. Serial Programming Instruction Set (Hexadecimal values) (Continued)

Instruction Format
Instruction/Operation Byte 1 Byte 2 Byte 3 Byte4
(6)
Write Instructions
Write Program Memory Page $4C adr MSB adr LSB $00
Write EEPROM Memory $C0 0000 00aa aaaa aaaa data byte in
Write EEPROM Memory Page (page access) $C2 0000 00aa aaaa aa00 $00
Write Lock bits $AC $E0 $00 data byte in
Write Fuse bits $AC $A0 $00 data byte in
Write Fuse High bits $AC $A8 $00 data byte in
Write Extended Fuse Bits $AC $A4 $00 data byte in
Notes: 1. Not all instructions are applicable for all parts.
2. a = address.
3. Bits are programmed ‘0’, unprogrammed ‘1’.
4. To ensure future compatibility, unused Fuses and Lock bits should be unprogrammed (‘1’) .
5. Refer to the correspondig section for Fuse and Lock bits, Calibration and Signature bytes and Page size.
6. Instructions accessing program memory use a word address. This address may be random within the page range.
7. See htt://www.atmel.com/avr for Application Notes regarding programming and programmers.

If the LSB in RDY/BSY data byte out is ‘1’, a programming operation is still pending. Wait until
this bit returns ‘0’ before the next instruction is carried out.
Within the same page, the low data byte must be loaded prior to the high data byte.
After data is loaded to the page buffer, program the EEPROM page, see Figure 27-8 on page
312.

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Figure 27-8. Serial Programming Instruction example

Serial Programming Instruction
Load Program Memory Page (High/Low Byte)/ Write Program Memory Page/
Load EEPROM Memory Page (page access) Write EEPROM Memory Page

Byte 1 Byte 2 Byte 3 Byte 4 Byte 1 Byte 2 Byte 3 Byte 4

Adr MSB
A Adr LSB Adr MSB Adrr LSB
B
Bit 15 B 0 Bit 15 B 0

Page Buffer
Page Offset

Page 0

Page 1

Page 2
Page Number

Page N-1

Program Memory/
EEPROM Memory

27.8.4 SPI Serial Programming Characteristics

Figure 27-9. Serial Programming Waveforms

SERIAL DATA INPUT MSB LSB
(MOSI)

SERIAL DATA OUTPUT MSB LSB

(MISO)

SERIAL CLOCK INPUT

(SCK)

SAMPLE

For characteristics of the SPI module see “SPI Timing Characteristics” on page 319.

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28. Electrical Characteristics

28.1 Absolute Maximum Ratings*

Operating Temperature.................................. -55°C to +125°C *NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
Storage Temperature ..................................... -65°C to +150°C age to the device. This is a stress rating only and
functional operation of the device at these or
Voltage on any Pin except RESET other conditions beyond those indicated in the
with respect to Ground ................................-0.5V to VCC+0.5V operational sections of this specification is not
implied. Exposure to absolute maximum rating
Voltage on RESET with respect to Ground......-0.5V to +13.0V conditions for extended periods may affect
device reliability.
Maximum Operating Voltage ............................................ 6.0V

DC Current per I/O Pin ............................................... 40.0 mA

DC Current VCC and GND Pins................................ 200.0 mA

28.2 DC Characteristics

TA = -40°C to 85°C, VCC = 1.8V to 5.5V (unless otherwise noted)

Symbol Parameter Condition Min. Typ. Max. Units
Input Low Voltage, except VCC = 1.8V - 2.4V -0.5 0.2VCC(1)
VIL V
XTAL1 and RESET pin VCC = 2.4V - 5.5V -0.5 0.3VCC(1)
Input High Voltage, except VCC = 1.8V - 2.4V 0.7VCC(2) VCC + 0.5
VIH V
XTAL1 and RESET pins VCC = 2.4V - 5.5V 0.6VCC(2) VCC + 0.5
Input Low Voltage,
VIL1 VCC = 1.8V - 5.5V -0.5 0.1VCC(1) V
XTAL1 pin
Input High Voltage, VCC = 1.8V - 2.4V 0.8VCC(2) VCC + 0.5
VIH1 V
XTAL1 pin VCC = 2.4V - 5.5V 0.7VCC(2) VCC + 0.5
Input Low Voltage,
VIL2 VCC = 1.8V - 5.5V -0.5 0.1VCC(1) V
RESET pin
Input High Voltage,
VIH2 VCC = 1.8V - 5.5V 0.9VCC(2) VCC + 0.5 V
RESET pin
Input Low Voltage, VCC = 1.8V - 2.4V -0.5 0.2VCC(1)
VIL3 V
RESET pin as I/O VCC = 2.4V - 5.5V -0.5 0.3VCC(1)
Input High Voltage, VCC = 1.8V - 2.4V 0.7VCC(2) VCC + 0.5
VIH3 V
RESET pin as I/O VCC = 2.4V - 5.5V 0.6VCC(2) VCC + 0.5
Output Low Voltage(3) IOL = 20 mA, VCC = 5V 0.9
VOL V
except RESET pin IOL = 10 mA, VCC = 3V 0.6

Output High Voltage(4) IOH = -20 mA, VCC = 5V 4.2

VOH V
except Reset pin IOH = -10 mA, VCC = 3V 2.3

Input Leakage VCC = 5.5V, pin low

IIL 1 µA
Current I/O Pin (absolute value)
Input Leakage VCC = 5.5V, pin high
IIH 1 µA
Current I/O Pin (absolute value)

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TA = -40°C to 85°C, VCC = 1.8V to 5.5V (unless otherwise noted) (Continued)

Symbol Parameter Condition Min. Typ. Max. Units
RRST Reset Pull-up Resistor 30 60 kΩ
RPU I/O Pin Pull-up Resistor 20 50 kΩ

Analog Comparator VCC = 5V

VACIO <10 40 mV
Input Offset Voltage Vin = VCC/2
Analog Comparator VCC = 5V
IACLK -50 50 nA
Input Leakage Current Vin = VCC/2
Analog Comparator VCC = 2.7V 750
tACID ns
Propagation Delay VCC = 4.0V 500
Notes: 1. “Max” means the highest value where the pin is guaranteed to be read as low
2. “Min” means the lowest value where the pin is guaranteed to be read as high
3. Although each I/O port can sink more than the test conditions (20 mA at VCC = 5V, 10 mA at VCC = 3V) under steady state
conditions (non-transient), the following must be observed:
ATmega48PA/88PA/168PA/328P:
1] The sum of all IOL, for ports C0 - C5, ADC7, ADC6 should not exceed 100 mA.
2] The sum of all IOL, for ports B0 - B5, D5 - D7, XTAL1, XTAL2 should not exceed 100 mA.
3] The sum of all IOL, for ports D0 - D4, RESET should not exceed 100 mA.
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test condition.
4. Although each I/O port can source more than the test conditions (20 mA at VCC = 5V, 10 mA at VCC = 3V) under steady state
conditions (non-transient), the following must be observed:
ATmega48PA/88PA/168PA/328P:
1] The sum of all IOH, for ports C0 - C5, D0- D4, ADC7, RESET should not exceed 150 mA.
2] The sum of all IOH, for ports B0 - B5, D5 - D7, ADC6, XTAL1, XTAL2 should not exceed 150 mA.
If IIOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current
greater than the listed test condition.

28.2.1 ATmega48PA DC Characteristics

TA = -40°C to 85°C, VCC = 1.8V to 5.5V (unless otherwise noted)

Symbol Parameter Condition Min. Typ.(2) Max. Units
Active 1 MHz, VCC = 2V 0.2 0.5 mA
Active 4 MHz, VCC = 3V 1.2 2.5 mA
Active 8 MHz, VCC = 5V 4.0 9 mA
Power Supply Current(1)
Idle 1 MHz, VCC = 2V 0.03 0.15 mA
Idle 4 MHz, VCC = 3V 0.21 0.7 mA
Idle 8 MHz, VCC = 5V 0.9 2.7 mA
ICC
32 kHz TOSC enabled,
0.75 µA
VCC = 1.8V
(3)
Power-save mode
32 kHz TOSC enabled,
0.9 µA
VCC = 3V
WDT enabled, VCC = 3V 3.9 8 µA
Power-down mode(3)
WDT disabled, VCC = 3V 0.1 2 µA
Notes: 1. Values with “Minimizing Power Consumption” enabled (0xFF).
2. Typical values at 25°C. Maximum values are characterized values and not test limits in production.
3. The current consumption values include input leakage current.

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28.2.2 ATmega88PA DC Characteristics

TA = -40°C to 85°C, VCC = 1.8V to 5.5V (unless otherwise noted)

Symbol Parameter Condition Min. Typ.(2) Max. Units
Active 1 MHz, VCC = 2V 0.2 0.5 mA
Active 4 MHz, VCC = 3V 1.2 2.5 mA
Active 8 MHz, VCC = 5V 4.1 9 mA
Power Supply Current(1)
Idle 1 MHz, VCC = 2V 0.03 0.15 mA
Idle 4 MHz, VCC = 3V 0.18 0.7 mA

ICC Idle 8 MHz, VCC = 5V 0.8 2.7 mA

32 kHz TOSC enabled,
0.8 µA
VCC = 1.8V
(3)
Power-save mode
32 kHz TOSC enabled,
0.9 µA
VCC = 3V
WDT enabled, VCC = 3V 3.9 8 µA
Power-down mode(3)
WDT disabled, VCC = 3V 0.1 2 µA
Notes: 1. Values with “Minimizing Power Consumption” enabled (0xFF).
2. Typical values at 25°C. Maximum values are test limits in production.
3. The current consumption values include input leakage current.

28.2.3 ATmega168PA DC Characteristics

TA = -40°C to 85°C, VCC = 1.8V to 5.5V (unless otherwise noted)

Symbol Parameter Condition Min. Typ.(2) Max. Units
Active 1 MHz, VCC = 2V 0.2 0.5 mA
Active 4 MHz, VCC = 3V 1.2 2.5 mA
Active 8 MHz, VCC = 5V 4.2 9 mA
Power Supply Current(1)
Idle 1 MHz, VCC = 2V 0.03 0.15 mA
Idle 4 MHz, VCC = 3V 0.2 0.7 mA
Idle 8 MHz, VCC = 5V 0.9 2.7
ICC
32 kHz TOSC enabled,
0.75 µA
VCC = 1.8V
(3)
Power-save mode
32 kHz TOSC enabled,
0.83 µA
VCC = 3V
WDT enabled, VCC = 3V 4.1 8 µA
Power-down mode(3)
WDT disabled, VCC = 3V 0.1 2 µA
Notes: 1. Values with “Minimizing Power Consumption” enabled (0xFF).
2. Typical values at 25°C. Maximum values are test limits in production.
3. The current consumption values include input leakage current.

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28.2.4 ATmega328P DC Characteristics

TA = -40°C to 85°C, VCC = 1.8V to 5.5V (unless otherwise noted)

Symbol Parameter Condition Min. Typ.(2) Max. Units
Active 1 MHz, VCC = 2V 0.3 0.5 mA
Active 4 MHz, VCC = 3V 1.7 2.5 mA
Active 8 MHz, VCC = 5V 5.2 9 mA
Power Supply Current(1)
Idle 1 MHz, VCC = 2V 0.04 0.15 mA
Idle 4 MHz, VCC = 3V 0.3 0.7 mA

ICC Idle 8 MHz, VCC = 5V 1.2 2.7 mA

32 kHz TOSC enabled,
0.8 1.6 µA
VCC = 1.8V
(3)(4)
Power-save mode
32 kHz TOSC enabled,
0.9 2.6 µA
VCC = 3V
WDT enabled, VCC = 3V 4.2 8 µA
Power-down mode(3)
WDT disabled, VCC = 3V 0.1 2 µA
Notes: 1. Values with “Minimizing Power Consumption” enabled (0xFF).
2. Typical values at 25°C. Maximum values are test limits in production.
3. The current consumption values include input leakage current.
4. Maximum values are characterized values and not test limits in production.

28.3 Speed Grades

Maximum frequency is dependent on VCC. As shown in Figure 28-1, the Maximum Frequency vs.
VCC curve is linear between 1.8V < VCC < 2.7V and between 2.7V < VCC < 4.5V.

Figure 28-1. Maximum Frequency vs. VCC

20 MHz

10 MHz
Safe Operating Area

4 MHz

1.8V 2.7V 4.5V 5.5V

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28.4 Clock Characteristics

28.4.1 Calibrated Internal RC Oscillator Accuracy

Table 28-1. Calibration Accuracy of Internal RC Oscillator

Frequency VCC Temperature Calibration Accuracy
Factory
8.0 MHz 3V 25°C ±10%
Calibration
User
7.3 - 8.1 MHz 1.8V - 5.5V -40°C - 85°C ±1%
Calibration

28.4.2 External Clock Drive Waveforms

Figure 28-2. External Clock Drive Waveforms

V IH1

V IL1

28.4.3 External Clock Drive

Table 28-2. External Clock Drive

VCC= 1.8 - 5.5V VCC= 2.7 - 5.5V VCC= 4.5 - 5.5V
Symbol Parameter Min. Max. Min. Max. Min. Max. Units
1/tCLCL Oscillator Frequency 0 4 0 10 0 20 MHz
tCLCL Clock Period 250 100 50 ns
tCHCX High Time 100 40 20 ns
tCLCX Low Time 100 40 20 ns
tCLCH Rise Time 2.0 1.6 0.5 μs
tCHCL Fall Time 2.0 1.6 0.5 μs
Change in period from
ΔtCLCL one clock cycle to the 2 2 2 %
next

Note: All DC Characteristics contained in this datasheet are based on simulation and characterization of other AVR microcontrollers
manufactured in the same process technology. These values are preliminary values representing design targets, and will be
updated after characterization of actual silicon.

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28.5 System and Reset Characteristics

Table 28-3. Reset, Brown-out and Internal Voltage Characteristics(1)

Symbol Parameter Min Typ Max Units
Power-on Reset Threshold Voltage (rising) 1.1 1.4 1.6 V
VPOT
Power-on Reset Threshold Voltage (falling)(2) 0.6 1.3 1.6 V
SRON Power-on Slope Rate 0.01 10 V/ms
VRST RESET Pin Threshold Voltage 0.2 VCC 0.9 VCC V
tRST Minimum pulse width on RESET Pin 2.5 µs
VHYST Brown-out Detector Hysteresis 50 mV
tBOD Min Pulse Width on Brown-out Reset 2 µs
VCC=2.7
VBG Bandgap reference voltage 1.0 1.1 1.2 V
TA=25°C
VCC=2.7
tBG Bandgap reference start-up time 40 70 µs
TA=25°C
VCC=2.7
IBG Bandgap reference current consumption 10 µA
TA=25°C
Notes: 1. Values are guidelines only.
2. The Power-on Reset will not work unless the supply voltage has been below VPOT (falling)

Table 28-4. BODLEVEL Fuse Coding(1)

BODLEVEL 2:0 Fuses Min VBOT Typ VBOT Max VBOT Units
111 BOD Disabled
110 1.7 1.8 2.0
101 2.5 2.7 2.9 V
100 4.1 4.3 4.5
011
010
Reserved
001
000

Notes: 1. VBOT may be below nominal minimum operating voltage for some devices. For devices where this is the case, the device is
tested down to VCC = VBOT during the production test. This guarantees that a Brown-Out Reset will occur before VCC drops to
a voltage where correct operation of the microcontroller is no longer guaranteed. The test is performed using
BODLEVEL = 110, 101 and 100.

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28.6 SPI Timing Characteristics

See Figure 28-3 and Figure 28-4 for details.

Table 28-5. SPI Timing Parameters

Description Mode Min Typ Max
1 SCK period Master See Table 18-5
2 SCK high/low Master 50% duty cycle
3 Rise/Fall time Master 3.6
4 Setup Master 10
5 Hold Master 10
6 Out to SCK Master 0.5 • tsck
7 SCK to out Master 10
8 SCK to out high Master 10
9 SS low to out Slave 15
ns
10 SCK period Slave 4 • tck
11 SCK high/low(1) Slave 2 • tck
12 Rise/Fall time Slave 1600
13 Setup Slave 10
14 Hold Slave tck
15 SCK to out Slave 15
16 SCK to SS high Slave 20
17 SS high to tri-state Slave 10
18 SS low to SCK Slave 20

Note: 1. In SPI Programming mode the minimum SCK high/low period is:
- 2 tCLCL for fCK < 12 MHz
- 3 tCLCL for fCK > 12 MHz
2. All DC Characteristics contained in this datasheet are based on simulation and characteriza-
tion of other AVR microcontrollers manufactured in the same process technology. These
values are preliminary values representing design targets, and will be updated after character-
ization of actual silicon.

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Figure 28-3. SPI Interface Timing Requirements (Master Mode)

SS
6 1

SCK
(CPOL = 0)
2 2

SCK
(CPOL = 1)
4 5 3

MISO
MSB ... LSB
(Data Input)
7 8

MOSI
MSB ... LSB
(Data Output)

Figure 28-4. SPI Interface Timing Requirements (Slave Mode)

SS
10 16
9

SCK
(CPOL = 0)
11 11

SCK
(CPOL = 1)
13 14 12

MOSI
MSB ... LSB
(Data Input)
15 17

MISO
MSB ... LSB X
(Data Output)

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28.7 2-wire Serial Interface Characteristics

Table 28-6 describes the requirements for devices connected to the 2-wire Serial Bus. The
ATmega48PA/88PA/168PA/328P 2-wire Serial Interface meets or exceeds these requirements under the noted conditions.
Timing symbols refer to Figure 28-5.

Table 28-6. 2-wire Serial Bus Requirements

Symbol Parameter Condition Min Max Units

VIL Input Low-voltage -0.5 0.3 VCC V

VIH Input High-voltage 0.7 VCC VCC + 0.5 V
(1) (2)
Vhys Hysteresis of Schmitt Trigger Inputs 0.05 VCC – V
VOL(1) Output Low-voltage 3 mA sink current 0 0.4 V
tr(1) Rise Time for both SDA and SCL 20 + 0.1Cb (3)(2)
300 ns
tof(1) Output Fall Time from VIHmin to VILmax 10 pF < Cb < 400 pF (3)
20 + 0.1Cb (3)(2)
250 ns
tSP(1) Spikes Suppressed by Input Filter 0 50 (2)
ns
Ii Input Current each I/O Pin 0.1VCC < Vi < 0.9VCC -10 10 µA
Ci(1) Capacitance for each I/O Pin – 10 pF
fSCL SCL Clock Frequency fCK(4) > max(16fSCL, 250kHz) (5)
0 400 kHz
fSCL ≤ 100 kHz V CC – 0,4V 1000ns
---------------------------
- ----------------- Ω
3mA Cb
Rp Value of Pull-up resistor
fSCL > 100 kHz V CC – 0,4V 300ns
---------------------------
- -------------- Ω
3mA Cb
fSCL ≤ 100 kHz 4.0 – µs
tHD;STA Hold Time (repeated) START Condition
fSCL > 100 kHz 0.6 – µs
fSCL ≤ 100 kHz 4.7 – µs
tLOW Low Period of the SCL Clock
fSCL > 100 kHz 1.3 – µs
fSCL ≤ 100 kHz 4.0 – µs
tHIGH High period of the SCL clock
fSCL > 100 kHz 0.6 – µs
fSCL ≤ 100 kHz 4.7 – µs
tSU;STA Set-up time for a repeated START condition
fSCL > 100 kHz 0.6 – µs
fSCL ≤ 100 kHz 0 3.45 µs
tHD;DAT Data hold time
fSCL > 100 kHz 0 0.9 µs
fSCL ≤ 100 kHz 250 – ns
tSU;DAT Data setup time
fSCL > 100 kHz 100 – ns
fSCL ≤ 100 kHz 4.0 – µs
tSU;STO Setup time for STOP condition
fSCL > 100 kHz 0.6 – µs

Bus free time between a STOP and START fSCL ≤ 100 kHz 4.7 – µs
tBUF
condition fSCL > 100 kHz 1.3 – µs

Notes: 1. In ATmega48PA/88PA/168PA/328P, this parameter is characterized and not 100% tested.

2. Required only for fSCL > 100 kHz.

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3. Cb = capacitance of one bus line in pF.

4. fCK = CPU clock frequency
5. This requirement applies to all ATmega48PA/88PA/168PA/328P 2-wire Serial Interface operation. Other devices connected
to the 2-wire Serial Bus need only obey the general fSCL requirement.

Figure 28-5. 2-wire Serial Bus Timing

tof tHIGH tr

tLOW tLOW

SCL
tSU;STA tHD;STA tHD;DAT tSU;DAT
tSU;STO
SDA

tBUF

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28.8 ADC Characteristics

Table 28-7. ADC Characteristics
Symbol Parameter Condition Min Typ Max Units
Resolution 10 Bits
VREF = 4V, VCC = 4V,
2 LSB
ADC clock = 200 kHz
VREF = 4V, VCC = 4V,
4.5 LSB
ADC clock = 1 MHz
Absolute accuracy (Including
INL, DNL, quantization error, VREF = 4V, VCC = 4V,
gain and offset error) ADC clock = 200 kHz 2 LSB
Noise Reduction Mode
VREF = 4V, VCC = 4V,
ADC clock = 1 MHz 4.5 LSB
Noise Reduction Mode
VREF = 4V, VCC = 4V,
Integral Non-Linearity (INL) 0.5 LSB
ADC clock = 200 kHz
Differential Non-Linearity VREF = 4V, VCC = 4V,
0.25 LSB
(DNL) ADC clock = 200 kHz
VREF = 4V, VCC = 4V,
Gain Error 2 LSB
ADC clock = 200 kHz
VREF = 4V, VCC = 4V,
Offset Error 2 LSB
ADC clock = 200 kHz
Conversion Time Free Running Conversion 13 260 µs
Clock Frequency 50 1000 kHz
AVCC(1) Analog Supply Voltage VCC - 0.3 VCC + 0.3 V
VREF Reference Voltage 1.0 AVCC V
VIN Input Voltage GND VREF V
Input Bandwidth 38.5 kHz
VINT Internal Voltage Reference 1.0 1.1 1.2 V
RREF Reference Input Resistance 32 kΩ
RAIN Analog Input Resistance 100 MΩ
Note: 1. AVCC absolute min/max: 1.8V/5.5V

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28.9 Parallel Programming Characteristics

Table 28-8. Parallel Programming Characteristics, VCC = 5V ± 10%

Symbol Parameter Min Typ Max Units
VPP Programming Enable Voltage 11.5 12.5 V
IPP Programming Enable Current 250 μA
tDVXH Data and Control Valid before XTAL1 High 67 ns
tXLXH XTAL1 Low to XTAL1 High 200 ns
tXHXL XTAL1 Pulse Width High 150 ns
tXLDX Data and Control Hold after XTAL1 Low 67 ns
tXLWL XTAL1 Low to WR Low 0 ns
tXLPH XTAL1 Low to PAGEL high 0 ns
tPLXH PAGEL low to XTAL1 high 150 ns
tBVPH BS1 Valid before PAGEL High 67 ns
tPHPL PAGEL Pulse Width High 150 ns
tPLBX BS1 Hold after PAGEL Low 67 ns
tWLBX BS2/1 Hold after WR Low 67 ns
tPLWL PAGEL Low to WR Low 67 ns
tBVWL BS1 Valid to WR Low 67 ns
tWLWH WR Pulse Width Low 150 ns
tWLRL WR Low to RDY/BSY Low 0 1 μs
(1)
tWLRH WR Low to RDY/BSY High 3.7 4.5 ms
(2)
tWLRH_CE WR Low to RDY/BSY High for Chip Erase 7.5 9 ms
tXLOL XTAL1 Low to OE Low 0 ns
tBVDV BS1 Valid to DATA valid 0 250 ns
tOLDV OE Low to DATA Valid 250 ns
tOHDZ OE High to DATA Tri-stated 250 ns

Notes: 1. tWLRH is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock bits
commands.
2. tWLRH_CE is valid for the Chip Erase command.

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Figure 28-6. Parallel Programming Timing, Including some General Timing Requirements
tXLWL
tXHXL
XTAL1
tDVXH tXLDX
Data & Contol
(DATA, XA0/1, BS1, BS2)
tBVPH tPLBX t BVWL
tWLBX
PAGEL tPHPL
tWLWH
WR tPLWL
WLRL

RDY/BSY
tWLRH

Figure 28-7. Parallel Programming Timing, Loading Sequence with Timing Requirements(1)
LOAD ADDRESS LOAD DATA LOAD DATA LOAD DATA LOAD ADDRESS
(LOW BYTE) (LOW BYTE) (HIGH BYTE) (LOW BYTE)

t XLXH tXLPH
tPLXH
XTAL1

BS1

PAGEL

DATA ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte)

XA0

XA1

Note: 1. The timing requirements shown in Figure 28-6 (i.e., tDVXH, tXHXL, and tXLDX) also apply to load-
ing operation.

Figure 28-8. Parallel Programming Timing, Reading Sequence (within the Same Page) with
Timing Requirements(1)
LOAD ADDRESS READ DATA READ DATA LOAD ADDRESS
(LOW BYTE) (LOW BYTE) (HIGH BYTE) (LOW BYTE)

tXLOL

XTAL1
tBVDV

BS1

tOLDV

OE
tOHDZ

DATA ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte)

XA0

XA1

Note: 1. The timing requirements shown in Figure 28-6 (i.e., tDVXH, tXHXL, and tXLDX) also apply to read-
ing operation.

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29. Typical Characteristics

The following charts show typical behavior. These figures are not tested during manufacturing.
All current consumption measurements are performed with all I/O pins configured as inputs and
with internal pull-ups enabled. A square wave generator with rail-to-rail output is used as clock
source.
All Active- and Idle current consumption measurements are done with all bits in the PRR register
set and thus, the corresponding I/O modules are turned off. Also the Analog Comparator is dis-
abled during these measurements. The ”ATmega88PA: Supply Current of IO Modules” on page
356 and page 380 shows the additional current consumption compared to ICC Active and ICC Idle
for every I/O module controlled by the Power Reduction Register. See ”Power Reduction Regis-
ter” on page 42 for details.
The power consumption in Power-down mode is independent of clock selection.
The current consumption is a function of several factors such as: operating voltage, operating
frequency, loading of I/O pins, switching rate of I/O pins, code executed and ambient tempera-
ture. The dominating factors are operating voltage and frequency.
The current drawn from capacitive loaded pins may be estimated (for one pin) as CL*VCC*f where
CL = load capacitance, VCC = operating voltage and f = average switching frequency of I/O pin.
The parts are characterized at frequencies higher than test limits. Parts are not guaranteed to
function properly at frequencies higher than the ordering code indicates.
The difference between current consumption in Power-down mode with Watchdog Timer
enabled and Power-down mode with Watchdog Timer disabled represents the differential cur-
rent drawn by the Watchdog Timer.

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29.1 ATmega48PA Typical Characteristics

29.1.1 Active Supply Current

Figure 29-1. ATmega48PA: Active Supply Current vs. Low Frequency (0.1-1.0 MHz)
1
5.5 V

0.8
5.0 V

4.5 V
0.6
ICC (mA)

4.0 V

0.4 3.3 V
2.7 V
0.2 1.8 V

0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Frequency (MHz)

Figure 29-2. ATmega48PA: Active Supply Current vs. Frequency (1-20 MHz)
12

5.5 V
10
5.0 V
8
4.5 V
ICC (mA)

6
4.0 V
4
3.3 V

2
2.7 V
1.8 V
0
0 2 4 6 8 10 12 14 16 18 20
Frequency (MHz)

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Figure 29-3. ATmega48PA: Active Supply Current vs. VCC (Internal RC Oscillator, 128 kHz)
0.14

85 °C
0.12 -40 °C
25 °C
0.1

0.08

ICC (mA) 0.06

0.04

0.02

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

Figure 29-4. ATmega48PA: Active Supply Current vs. VCC (Internal RC Oscillator, 1 MHz)
1.2
85 °C
25 °C
1 -40 °C

0.8
ICC (mA)

0.6

0.4

0.2

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

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 ATmega48PA/88PA/168PA/328P

Figure 29-5. ATmega48PA: Active Supply Current vs. VCC (Internal RC Oscillator, 8 MHz)
5 85 °C
25 °C
-40 °C
4

ICC (mA) 2

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

29.1.2 Idle Supply Current

Figure 29-6. ATmega48PA: Idle Supply Current vs. Low Frequency (0.1-1.0 MHz)
0.16
5.5 V
0.14

0.12 5.0 V

0.1 4.5 V
ICC (mA)

0.08 4.0 V

0.06 3.3 V

0.04 2.7 V
1.8 V
0.02

0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Frequency (MHz)

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 ATmega48PA/88PA/168PA/328P

Figure 29-7. ATmega48PA: Idle Supply Current vs. Frequency (1-20 MHz)
3

2.5
5.5 V

5.0 V
2
4.5 V

ICC (mA)
1.5

4.0 V
1

3.3 V
0.5
2.7 V
0
1.8 V
0 2 4 6 8 10 12 14 16 18 20
Frequency (MHz)

Figure 29-8. ATmega48PA: Idle Supply Current vs. VCC (Internal RC Oscillator, 128 kHz)
0.042
85 °C

0.035

0.028
25 °C
-40 °C
ICC (mA)

0.021

0.014

0.007

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

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Figure 29-9. ATmega48PA: Idle Supply Current vs. VCC (Internal RC Oscillator, 1 MHz)
0.35

0.3
85 °C
25 °C
-40 °C
0.25

0.2

ICC (mA) 0.15

0.1

0.05

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

Figure 29-10. ATmega48PA: Idle Supply Current vs. Vcc (Internal RC Oscillator, 8 MHz)
1.2 85 °C
25 °C
-40 °C
1

0.8
ICC (mA)

0.6

0.4

0.2

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

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 ATmega48PA/88PA/168PA/328P

29.1.3 ATmega48PA: Supply Current of IO Modules

The tables and formulas below can be used to calculate the additional current consumption for
the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules
are controlled by the Power Reduction Register. See ”Power Reduction Register” on page 42 for
details.

Table 29-1. ATmega48PA: Additional Current Consumption for the different I/O modules
(absolute values)
PRR bit Typical numbers
VCC = 2V, F = 1 MHz VCC = 3V, F = 4 MHz VCC = 5V, F = 8 MHz
PRUSART0 2.9 uA 20.7 uA 97.4 uA
PRTWI 6.0 uA 44.8 uA 219.7 uA
PRTIM2 5.0 uA 34.5 uA 141.3 uA
PRTIM1 3.6 uA 24.4 uA 107.7 uA
PRTIM0 1.4 uA 9.5 uA 38.4 uA
PRSPI 5.0 uA 38.0 uA 190.4 uA
PRADC 6.1 uA 47.4 uA 244.7 uA

Table 29-2. ATmega48PA: Additional Current Consumption (percentage) in Active and Idle
mode
Additional Current consumption Additional Current consumption
compared to Active with external compared to Idle with external
clock (see Figure 29-1 on page clock (see Figure 29-6 on page
PRR bit 327 and Figure 29-2 on page 327) 329 and Figure 29-7 on page 330)
PRUSART0 1.8% 11.4%
PRTWI 3.9% 20.6%
PRTIM2 2.9% 15.7%
PRTIM1 2.1% 11.2%
PRTIM0 0.8% 4.2%
PRSPI 3.3% 17.6%
PRADC 4.2% 22.1%

It is possible to calculate the typical current consumption based on the numbers from Table 29-2
on page 332 for other VCC and frequency settings than listed in Table 29-1 on page 332.
Example Calculate the expected current consumption in idle mode with TIMER1, ADC, and SPI enabled
at VCC = 2.0V and F = 1MHz. From Table 29-2 on page 332, third column, we see that we need
to add 11.2% for the TIMER1, 22.1% for the ADC, and 17.6% for the SPI module. Reading from
Figure 29-6 on page 329, we find that the idle current consumption is ~0.028 mA at VCC = 2.0V
and F = 1MHz. The total current consumption in idle mode with TIMER1, ADC, and SPI enabled,
gives:
I CC total ≈ 0.028 mA ⋅ (1 + 0.112 + 0.221 + 0.176) ≈ 0.042 mA

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29.1.4 Power-down Supply Current

Figure 29-11. ATmega48PA: Power-Down Supply Current vs. VCC (Watchdog Timer Disabled)
1.2

85 °C
1

0.8
ICC (uA)
0.6

0.4
-40 °C
0.2 25 °C

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

Figure 29-12. ATmega48PA: Power-Down Supply Current vs. VCC (Watchdog Timer Enabled)
8
-40 °C
85 °C
25 °C
6
ICC (uA)

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

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29.1.5 Power-save Supply Current

Figure 29-13. ATmega48PA: Power-Save Supply Current vs. VCC (Watchdog Timer Disabled
and 32 kHz Crystal Oscillator Running)
2 85 °C

1.6

ICC (uA)
1.2 25 °C
-40 °C

0.8

0.4

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

29.1.6 Standby Supply Current

Figure 29-14. ATmega48PA: Standby Supply Current vs. Vcc (Watchdog Timer Disabled)
0.16
6MHz_xtal
0.14 6MHz_res

0.12
4MHz_res
0.1 4MHz_xtal
ICC (mA)

0.08
2MHz_res
2MHz_xtal
0.06
450kHz_res
0.04

0.02

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

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29.1.7 Pin Pull-Up

Figure 29-15. ATmega48PA: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8 V)
50

40

30
IOP (uA)

20

10
25 °C
85 °C
0 -40 °C
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
VOP (V)

Figure 29-16. ATmega48PA: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7 V)
70

60

50

40
IOP (uA)

30

20

25 °C
10
85 °C
-40 °C
0
0 0.5 1 1.5 2 2.5 3
VOP (V)

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Figure 29-17. ATmega48PA: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5 V)
140

120

100

80

IOP (uA) 60

40

25 °C
20
85 °C
-40 °C
0
0 1 2 3 4 5
VOP (V)

Figure 29-18. ATmega48PA: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8 V)
35

30

25
IRESET (uA)

20

15

10
25 °C
5 -40 °C
85 °C
0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
VRESET (V)

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Figure 29-19. ATmega48PA: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7 V)
60

50

40

IRESET (uA)
30

20

10 25 °C
-40 °C
0 85 °C
0 0.5 1 1.5 2 2.5 3
VRESET (V)

Figure 29-20. ATmega48PA: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5 V)

120

100

80
IRESET (uA)

60

40

20 25 °C
-40 °C
0 85 °C
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
VRESET (V)

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29.1.8 Pin Driver Strength

Figure 29-21. ATmega48PA: I/O Pin Output Voltage vs. Sink Current(VCC = 3 V)
1

85 °C
0.8

25 °C
0.6
VOL (V) -40 °C

0.4

0.2

0
0 4 8 12 16 20
IOL (mA)

Figure 29-22. ATmega48PA: I/O Pin Output Voltage vs. Sink Current(VCC = 5 V)

0.6
85 °C

0.5 25 °C

0.4 -40 °C
VOL (V)

0.3

0.2

0.1

0
0 4 8 12 16 20
IOL (mA)

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Figure 29-23. ATmega48PA: I/O Pin Output Voltage vs. Source Current(Vcc = 3 V)

3.5

2.5
-40 °C
25 °C
2 85 °C
VOH (V) 1.5

0.5

0
0 4 8 12 16 20
IOH (mA)

Figure 29-24. ATmega48PA: I/O Pin Output Voltage vs. Source Current(VCC = 5 V)

4.9

4.8

4.7
VOH (V)

4.6
-40 °C
4.5
25 °C
4.4
85 °C
4.3

4.2
0 4 8 12 16 20
IOH (mA)

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29.1.9 Pin Threshold and Hysteresis

Figure 29-25. ATmega48PA: I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin read as ‘1’)

3
-40 °C
25 °C
2.5 85 °C

2
Threshold (V)

1.5

0.5

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

Figure 29-26. ATmega48PA: I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin read as ‘0’)
2.5 85 °C
25 °C
-40 °C
2
Threshold (V)

1.5

0.5

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

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Figure 29-27. ATmega48PA: I/O Pin Input Hysteresis vs. VCC

0.6
25 °C
85 °C
0.5 -40 °C

Input Hysteresis (mV)

0.4

0.3

0.2

0.1

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

Figure 29-28. ATmega48PA: Reset Input Threshold Voltage vs. VCC (VIH, I/O Pin read as ‘1’)
2.5 -40 °C
25 °C
85 °C
2
Threshold (V)

1.5

0.5

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

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Figure 29-29. ATmega48PA: Reset Input Threshold Voltage vs. VCC (VIL, I/O Pin read as ‘0’)
2.5
85 °C
25 °C
-40 °C
2

Threshold (V)
1.5

0.5

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

Figure 29-30. ATmega48PA: Reset Pin Input Hysteresis vs. VCC

0.7

0.6

0.5
Input Hysteresis (mV)

0.4

0.3

0.2

0.1 85 °C
25 °C
-40 °C
0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

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29.1.10 BOD Threshold

Figure 29-31. ATmega48PA: BOD Thresholds vs. Temperature (BODLEVEL is 1.8 V)

1.85
Rising Vcc
1.84

1.83

Threshold (V) 1.82

Falling Vcc
1.81

1.8

1.79
-50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90
Temperature (°C)

Figure 29-32. ATmega48PA: BOD Thresholds vs. Temperature (BODLEVEL is 2.7 V)

2.76
Rising Vcc
2.74

2.72
Threshold (V)

2.7

2.68
Falling Vcc
2.66

2.64

2.62
-50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90
Temperature (°C)

343
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 ATmega48PA/88PA/168PA/328P

Figure 29-33. ATmega48PA: BOD Thresholds vs. Temperature (BODLEVEL is 4.3 V)

4.36

Rising Vcc
4.34

4.32

Threshold (V)
4.3

4.28

Falling Vcc
4.26

4.24
-50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90
Temperature (°C)

29.1.11 Internal Oscilllator Speed

Figure 29-34. ATmega48PA: Watchdog Oscillator Frequency vs. Temperature

116

114

112
FRC (kHz)

110
2.7 V
3.3 V
108
4.0 V
5.5 V
106

104
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90
Temperature (°C)

344
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 ATmega48PA/88PA/168PA/328P

Figure 29-35. ATmega48PA: Watchdog Oscillator Frequency vs. VCC

118

116

114 -40 °C

FRC (kHz) 112 25 °C

110

108

85 °C
106
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

Figure 29-36. ATmega48PA: Calibrated 8 MHz RC Oscillator Frequency vs. VCC

8.2
85 °C
8.1

8
25 °C
FRC (MHz)

7.9

7.8

7.7 -40 °C

7.6
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

345
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 ATmega48PA/88PA/168PA/328P

Figure 29-37. ATmega48PA: Calibrated 8 MHz RC Oscillator Frequency vs. Temperature

8.2
3.3 V
8.1
5.5 V
1.8 V

FRC (MHz)
7.9

7.8

7.7

7.6
-50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90
Temperature (°C)

Figure 29-38. ATmega48PA: Calibrated 8 MHz RC Oscillator Frequency vs. OSCCAL Value

16
85 °C
14 25 °C
-40 °C
12

10
FRC (MHz)

0
0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256
OSCCAL (X1)

346
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 ATmega48PA/88PA/168PA/328P

29.1.12 Current Consumption of Peripheral Units

Figure 29-39. ATmega48PA: ADC Current vs. VCC (AREF = AVCC)

350

-40 °C
300 25 °C
85 °C
250

ICC (uA) 200

150

100

50

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

Figure 29-40. ATmega48PA: Analog Comparator Current vs. VCC

90
-40 °C
80 25 °C
85 °C
70

60
ICC (uA)

50

40

30

20

10

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

347
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 ATmega48PA/88PA/168PA/328P

Figure 29-41. ATmega48PA: AREF External Reference Current vs. VCC

160
85 °C
140 25 °C
-40 °C
120

100

ICC (uA) 80

60

40

20

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

Figure 29-42. ATmega48PA: Brownout Detector Current vs. VCC

40

32

85 °C
24
25 °C
ICC (uA)

-40 °C

16

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

348
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 ATmega48PA/88PA/168PA/328P

Figure 29-43. ATmega48PA: Programming Current vs. VCC

6

-40 °C
5
25 °C
4

ICC (mA)
3
85 °C

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

29.1.13 Current Consumption in Reset and Reset Pulsewidth

Figure 29-44. ATmega48PA: Reset Supply Current vs. Low Frequency (0.1 - 1.0 MHz)
0.14

0.12 5.5 V

0.1 5.0 V

0.08 4.5 V
ICC (mA)

4.0 V
0.06
3.3 V
0.04 2.7 V

0.02 1.8 V

0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Frequency (MHz)

349
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 ATmega48PA/88PA/168PA/328P

Figure 29-45. ATmega48PA: Reset Supply Current vs. Frequency (1 - 20 MHz)

2.5
5.5 V

2 5.0 V

4.5 V
1.5

ICC (mA)
4.0 V
1

3.3 V
0.5
2.7 V

1.8 V
0
0 2 4 6 8 10 12 14 16 18 20
Frequency (MHz)

Figure 29-46. ATmega48PA: Minimum Reset Pulse width vs. VCC

1600

1400

1200
Pulsewidth (ns)

1000

800

600

400
85 °C
25 °C
200 -40 °C

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

350
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 ATmega48PA/88PA/168PA/328P

29.2 ATmega88PA Typical Characteristics

29.2.1 Active Supply Current

Figure 29-47. ATmega88PA: Active Supply Current vs. Low Frequency (0.1-1.0 MHz)
1
5.5 V

0.8 5.0 V

4.5 V
0.6
ICC (mA)

4.0 V

0.4 3.3 V
2.7 V
0.2 1.8 V

0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Frequency (MHz)

Figure 29-48. ATmega88PA: Active Supply Current vs. Frequency (1 - 20 MHz)

12

5.5 V
10
5.0 V
8
4.5 V
ICC (mA)

6
4.0 V
4
3.3 V
2.7 V
2

1.8 V
0
0 2 4 6 8 10 12 14 16 18 20
Frequency (MHz)

351
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 ATmega48PA/88PA/168PA/328P

Figure 29-49. ATmega88PA: Active Supply Current vs. VCC (Internal RC Oscillator, 128 kHz)
0.12 -40 °C
25 °C
85 °C
0.09

ICC (mA)
0.06

0.03

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

Figure 29-50. ATmega88PA: Active Supply Current vs. VCC (Internal RC Oscillator, 1 MHz)
1.2 85 °C
25 °C
1 -40 °C

0.8
ICC (mA)

0.6

0.4

0.2

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

352
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 ATmega48PA/88PA/168PA/328P

Figure 29-51. ATmega88PA: Active Supply Current vs. VCC (Internal RC Oscillator, 8 MHz)
5 85 °C
25 °C
-40 °C
4

ICC (mA) 2

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

29.2.2 Idle Supply Current

Figure 29-52. ATmega88PA: Idle Supply Current vs. Low Frequency (0.1-1.0 MHz)
0.15

5.5 V
0.12

5.0 V
0.09 4.5 V
ICC (mA)

4.0 V
0.06
3.3 V
2.7 V
0.03
1.8 V

0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Frequency (MHz)

353
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 ATmega48PA/88PA/168PA/328P

Figure 29-53. ATmega88PA: Idle Supply Current vs. Frequency (1 - 20 MHz)

2.5

5.5 V
2
5.0 V

4.5 V
1.5

ICC (mA)
4.0 V
1

3.3 V
0.5
2.7 V

1.8 V
0
0 2 4 6 8 10 12 14 16 18 20
Frequency (MHz)

Figure 29-54. ATmega88PA: Idle Supply Current vs. VCC (Internal RC Oscillator, 128 kHz)
0.04

85 °C
0.03

25 °C
ICC (mA)

-40 °C
0.02

0.01

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

354
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 ATmega48PA/88PA/168PA/328P

Figure 29-55. ATmega88PA: Idle Supply Current vs. VCC (Internal RC Oscillator, 1 MHz)
0.35
85 °C
0.3 25 °C
-40 °C
0.25

0.2

ICC (mA) 0.15

0.1

0.05

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

Figure 29-56. ATmega88PA: Idle Supply Current vs. Vcc (Internal RC Oscillator, 8 MHz)
1.2

85 °C
25 °C
0.9 -40 °C
ICC (mA)

0.6

0.3

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

355
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 ATmega48PA/88PA/168PA/328P

29.2.3 ATmega88PA: Supply Current of IO Modules

The tables and formulas below can be used to calculate the additional current consumption for
the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules
are controlled by the Power Reduction Register. See ”Power Reduction Register” on page 42 for
details.

Table 29-3. ATmega88PA: Additional Current Consumption for the different I/O modules
(absolute values)
PRR bit Typical numbers
VCC = 2V, F = 1 MHz VCC = 3V, F = 4 MHz VCC = 5V, F = 8 MHz
PRUSART0 3.0 uA 21.3 uA 97.9 uA
PRTWI 6.1 uA 45.4 uA 219.0 uA
PRTIM2 5.2 uA 35.2 uA 149.5 uA
PRTIM1 3.8 uA 25.6 uA 110.0 uA
PRTIM0 1.5 uA 9.8 uA 39.6 uA
PRSPI 5.2 uA 40.0 uA 199.6 uA
PRADC 6.3 uA 48.7 uA 247.0 uA

Table 29-4. ATmega88PA: Additional Current Consumption (percentage) in Active and Idle
mode
Additional Current consumption Additional Current consumption
compared to Active with external compared to Idle with external
clock (see Figure 29-47 on page clock (see Figure 29-52 on page
351 and Figure 29-48 on page 353 and Figure 29-53 on page
PRR bit 351) 354)
PRUSART0 1.8% 11.4%
PRTWI 3.9% 24.4%
PRTIM2 2.9% 18.6%
PRTIM1 2.1% 13.6%
PRTIM0 0.8% 5.2%
PRSPI 3.5% 21.5%
PRADC 4.2% 26.3%

It is possible to calculate the typical current consumption based on the numbers from Table 29-4
on page 356 for other VCC and frequency settings than listed in Table 29-3 on page 356.
Example Calculate the expected current consumption in idle mode with TIMER1, ADC, and SPI enabled
at VCC = 2.0V and F = 1MHz. From Table 29-4 on page 356, third column, we see that we need
to add 13.6% for the TIMER1, 26.3% for the ADC, and 21.5% for the SPI module. Reading from
Figure 29-52 on page 353, we find that the idle current consumption is ~0.027 mA at VCC = 2.0V
and F = 1MHz. The total current consumption in idle mode with TIMER1, ADC, and SPI enabled,
gives:
I CC total ≈ 0.027 mA ⋅ (1 + 0.136 + 0.263 + 0.215) ≈ 0.043 mA

356
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 ATmega48PA/88PA/168PA/328P

29.2.4 Power-down Supply Current

Figure 29-57. ATmega88PA: Power-Down Supply Current vs. VCC (Watchdog Timer Disabled)
1.6
85 °C
1.4

1.2

1
ICC (uA)
0.8

0.6

0.4
25 °C
0.2

0 -40 °C
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

Figure 29-58. ATmega88PA: Power-Down Supply Current vs. VCC (Watchdog Timer Enabled)
8 85 °C
-40 °C
25 °C
6
ICC (uA)

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

357
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 ATmega48PA/88PA/168PA/328P

29.2.5 Power-save Supply Current

Figure 29-59. ATmega88PA: Power-Save Supply Current vs. VCC (Watchdog Timer Disabled
and 32 kHzTIMER
WATCHDOG Crystal Oscillator
DISABLED andRunning)
32 kHz CRYSTAL OSCILLATOR RUNNING
3

2.5
85 °C

2 -40 °C
ICC (uA)

1.5
25 °C

0.5

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

29.2.6 Standby Supply Current

Figure 29-60. ATmega88PA: Standby Supply Current vs. Vcc (Watchdog Timer Disabled)
0.18

0.16 6MHz_res
6MHz_xtal
0.14

0.12 4MHz_res
4MHz_xtal
ICC (mA)

0.1

0.08 2MHz_res
2MHz_xtal
0.06 450kHz_res

0.04

0.02

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

358
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 ATmega48PA/88PA/168PA/328P

29.2.7 Pin Pull-Up

Figure 29-61. ATmega88PA: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8 V)
50

40

30
IOP (uA)

20

10
25 °C
-40 °C
0 85 °C
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
VOP (V)

Figure 29-62. ATmega88PA: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7 V)
80

70

60

50
IOP (uA)

40

30

20
25 °C
10 -40 °C
85 °C
0
0 0.5 1 1.5 2 2.5 3
VOP (V)

359
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 ATmega48PA/88PA/168PA/328P

Figure 29-63. ATmega88PA: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5 V)
140

120

100

80

IOP (uA) 60

40
25 °C
20
85 °C
-40 °C
0
0 1 2 3 4 5
VOP (V)

Figure 29-64. ATmega88PA: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8 V)
40

35

30

25
IRESET (uA)

20

15

10 25 °C

5 -40 °C
85 °C
0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
VRESET (V)

360
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 ATmega48PA/88PA/168PA/328P

Figure 29-65. ATmega88PA: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7 V)

60

50

40

IRESET (uA)
30

20

25 °C
10
-40 °C
85 °C
0
0 0.5 1 1.5 2 2.5 3
VRESET (V)

Figure 29-66. ATmega88PA: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5 V)
120

100

80
IRESET (uA)

60

40

20
25 °C
-40 °C
0
85 °C
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
VRESET (V)

361
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 ATmega48PA/88PA/168PA/328P

29.2.8 Pin Driver Strength

Figure 29-67. ATmega88PA: I/O Pin Output Voltage vs. Sink Current (VCC = 3 V)
1

85 °C
0.8

25 °C
0.6
VOL (V)
-40 °C

0.4

0.2

0
0 4 8 12 16 20
IOL (mA)

Figure 29-68. ATmega88PA: I/O Pin Output Voltage vs. Sink Current (VCC = 5 V)
0.6
85 °C
0.5
25 °C

0.4 -40 °C
VOL (V)

0.3

0.2

0.1

0
0 4 8 12 16 20
IOL (mA)

362
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 ATmega48PA/88PA/168PA/328P

Figure 29-69. ATmega88PA: I/O Pin Output Voltage vs. Source Current (Vcc = 3 V)
3.5

2.5
-40 °C
25 °C
2 85 °C

VOH (V) 1.5

0.5

0
0 4 8 12 16 20
IOH (mA)

Figure 29-70. ATmega88PA: I/O Pin Output Voltage vs. Source Current (VCC = 5 V)
5

4.9

4.8

4.7
VOH (V)

4.6
-40 °C
4.5
25 °C
4.4 85 °C

4.3

4.2
0 4 8 12 16 20
IOH (mA)

363
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 ATmega48PA/88PA/168PA/328P

29.2.9 Pin Threshold and Hysteresis

Figure 29-71. ATmega88PA: I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin read as ‘1’)
3 85 °C
-40 °C
2.5 25 °C

Threshold (V)
1.5

0.5

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

Figure 29-72. ATmega88PA: I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin read as ‘0’)
2.5 -40 °C
85 °C
25 °C
2
Threshold (V)

1.5

0.5

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

364
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 ATmega48PA/88PA/168PA/328P

Figure 29-73. ATmega88PA: I/O Pin Input Hysteresis vs. VCC

0.6
25 °C
85 °C
0.5
-40 °C

Input Hysteresis (mV)

0.4

0.3

0.2

0.1

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

Figure 29-74. ATmega88PA: Reset Input Threshold Voltage vs. VCC (VIH, I/O Pin read as ‘1’)

1.5
-40 °C
25 °C
85 °C
1.2
Threshold (V)

0.9

0.6

0.3

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

365
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 ATmega48PA/88PA/168PA/328P

Figure 29-75. ATmega88PA: Reset Input Threshold Voltage vs. VCC (VIL, I/O Pin read as ‘0’)
2.5 85 °C
25 °C
-40 °C
2

Threshold (V)
1.5

0.5

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

Figure 29-76. ATmega88PA: Reset Pin Input Hysteresis vs. VCC

0.6

0.5
Input Hysteresis (mV)

0.4

0.3

0.2
85 °C
0.1
25 °C
-40 °C

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

366
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 ATmega48PA/88PA/168PA/328P

29.2.10 BOD Threshold

Figure 29-77. ATmega88PA: BOD Thresholds vs. Temperature (BODLEVEL is 1.8 V)

1.83

Rising Vcc
1.82

1.81

Threshold (V)
1.8

1.79
Falling Vcc
1.78

1.77
-50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90
Temperature (°C)

Figure 29-78. ATmega88PA: BOD Thresholds vs. Temperature (BODLEVEL is 2.7 V)

2.76
Rising Vcc
2.74

2.72
Threshold (V)

2.7

Falling Vcc
2.68

2.66

2.64
-50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90
Temperature (°C)

367
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 ATmega48PA/88PA/168PA/328P

Figure 29-79. ATmega88PA: BOD Thresholds vs. Temperature (BODLEVEL is 4.3 V)

4.34
Rising Vcc

4.32

4.3

Threshold (V)
4.28

Falling Vcc
4.26

4.24

4.22
-50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90
Temperature (°C)

29.2.11 Internal Oscilllator Speed

Figure 29-80. ATmega88PA: Watchdog Oscillator Frequency vs. Temperature

114

113

112

111
FRC (kHz)

110

109

108
2.7 V
107 3.3 V
4.0 V
106
5.5 V
105
-40 -20 0 20 40 60 80 100
Temperature (°C)

368
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 ATmega48PA/88PA/168PA/328P

Figure 29-81. ATmega88PA: Watchdog Oscillator Frequency vs. VCC

116

114

-40 °C
112

FRC (kHz)
25 °C
110

108

106 85 °C

104
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

Figure 29-82. ATmega88PA: Calibrated 8 MHz RC Oscillator Frequency vs. VCC

8.3
85 °C
8.2

8.1
25 °C
FRC (MHz)

7.9
-40 °C
7.8

7.7

7.6
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

369
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 ATmega48PA/88PA/168PA/328P

Figure 29-83. ATmega88PA: Calibrated 8 MHz RC Oscillator Frequency vs. Temperature

8.3

5.5 V
8.2 4.0 V
3.0 V
8.1

FRC (MHz)
8

7.9

7.8
-40 -20 0 20 40 60 80 100
Temperature (°C)

Figure 29-84. ATmega88PA: Calibrated 8 MHz RC Oscillator Frequency vs. OSCCAL Value

14
85 °C
12 25 °C
-40 °C
10
FRC (MHz)

0
0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256
OSCCAL (X1)

370
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 ATmega48PA/88PA/168PA/328P

29.2.12 Current Consumption of Peripheral Units

Figure 29-85. ATmega88PA: ADC Current vs. VCC (AREF = AVCC)

300 -40 °C
25 °C
85 °C
250

200
ICC (uA)
150

100

50

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

Figure 29-86. ATmega88PA: Analog Comparator Current vs. VCC

90
-40 °C
80 25 °C
85 °C
70

60
ICC (uA)

50

40

30

20

10

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

371
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 ATmega48PA/88PA/168PA/328P

Figure 29-87. ATmega88PA: AREF External Reference Current vs. VCC

160 85 °C
25 °C
140 -40 °C
120

100

ICC (uA)
80

60

40

20

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

Figure 29-88. ATmega88PA: Brownout Detector Current vs. VCC

50

40

30
ICC (uA)

85 °C
25 °C
20
-40 °C

10

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

372
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 ATmega48PA/88PA/168PA/328P

Figure 29-89. ATmega88PA: Programming Current vs. VCC

8
-40 °C
7 25 °C

6
85 °C
5

ICC (mA)
4

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

29.2.13 Current Consumption in Reset and Reset Pulsewidth

Figure 29-90. ATmega88PA: Reset Supply Current vs. Low Frequency (0.1 - 1.0 MHz)
0.12

5.5 V
0.1

5.0 V
0.08
4.5 V
ICC (mA)

0.06 4.0 V

3.3 V
0.04
2.7 V
1.8 V
0.02

0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Frequency (MHz)

373
8161D–AVR–10/09
 ATmega48PA/88PA/168PA/328P

Figure 29-91. ATmega88PA: Reset Supply Current vs. Frequency (1 - 20 MHz)

2 5.5 V

5.0 V
1.6
4.5 V
1.2

ICC (mA)
4.0 V

0.8
3.3 V

0.4
2.7 V

1.8 V
0
0 2 4 6 8 10 12 14 16 18 20
Frequency (MHz)

Figure 29-92. ATmega88PA: Minimum Reset Pulse width vs. VCC

1600

1400

1200
Pulsewidth (ns)

1000

800

600

400 85 °C
25 °C
200 -40 °C
0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

374
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 ATmega48PA/88PA/168PA/328P

29.3 ATmega168PA Typical Characteristics

29.3.1 Active Supply Current

Figure 29-93. ATmega168PA: Active Supply Current vs. Low Frequency (0.1-1.0 MHz)
1
5.5 V

0.8 5.0 V

4.5 V
0.6
ICC (mA)

4.0 V

0.4 3.3 V
2.7 V
0.2 1.8 V

0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Frequency (MHz)

Figure 29-94. ATmega168PA: Active Supply Current vs. Frequency (1-20 MHz)
12

5.5 V
10
5.0 V
8
4.5 V
ICC (mA)

6
4.0 V
4
3.3 V

2
2.7 V

1.8 V
0
0 2 4 6 8 10 12 14 16 18 20
Frequency (MHz)

375
8161D–AVR–10/09
 ATmega48PA/88PA/168PA/328P

Figure 29-95. ATmega168PA: Active Supply Current vs. VCC (Internal RC Oscillator, 128 kHz)
0.15
-40 °C
85 °C
0.12 25 °C

0.09

ICC (mA)
0.06

0.03

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

Figure 29-96. ATmega168PA: Active Supply Current vs. VCC (Internal RC Oscillator, 1 MHz)
1.2
85 °C
25 °C
1
-40 °C

0.8
ICC (mA)

0.6

0.4

0.2

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

376
8161D–AVR–10/09
 ATmega48PA/88PA/168PA/328P

Figure 29-97. ATmega168PA: Active Supply Current vs. VCC (Internal RC Oscillator, 8 MHz)
5 85 °C
25 °C
-40 °C
4

ICC (mA) 2

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

29.3.2 Idle Supply Current

Figure 29-98. ATmega168PA: Idle Supply Current vs. Low Frequency (0.1-1.0 MHz)
0.15

5.5 V
0.12
5.0 V

0.09 4.5 V
ICC (mA)

4.0 V
0.06
3.3 V
2.7 V
0.03
1.8 V

0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Frequency (MHz)

377
8161D–AVR–10/09
 ATmega48PA/88PA/168PA/328P

Figure 29-99. ATmega168PA: Idle Supply Current vs. Frequency (1-20 MHz)
3

2.5 5.5 V

5.0 V
2
4.5 V

ICC (mA)
1.5
4.0 V

1
3.3 V
0.5
2.7 V

0
1.8 V
0 2 4 6 8 10 12 14 16 18 20
Frequency (MHz)

Figure 29-100.IATmega168PA: dle Supply Current vs. VCC (Internal RC Oscillator, 128 kHz)
0.04
85 °C
0.035

0.03
25 °C
0.025 -40 °C
ICC (mA)

0.02

0.015

0.01

0.005

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

378
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 ATmega48PA/88PA/168PA/328P

Figure 29-101.ATmega168PA: Idle Supply Current vs. VCC (Internal RC Oscillator, 1 MHz)
0.3
85 °C
25 °C
0.25 -40 °C

0.2

ICC (mA)
0.15

0.1

0.05

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

Figure 29-102.ATmega168PA: Idle Supply Current vs. Vcc (Internal RC Oscillator, 8 MHz)
1.2 85 °C
25 °C
-40 °C
0.9
ICC (mA)

0.6

0.3

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

379
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 ATmega48PA/88PA/168PA/328P

29.3.3 ATmega168PA Supply Current of IO Modules

The tables and formulas below can be used to calculate the additional current consumption for
the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules
are controlled by the Power Reduction Register. See ”Power Reduction Register” on page 42 for
details.

Table 29-5. ATmega168PA: Additional Current Consumption for the different I/O modules
(absolute values)
PRR bit Typical numbers
VCC = 2V, F = 1 MHz VCC = 3V, F = 4 MHz VCC = 5V, F = 8 MHz
PRUSART0 2.86 uA 20.3 uA 52.2 uA
PRTWI 6.00 uA 44.1uA 122.0 uA
PRTIM2 4.97 uA 33.2 uA 79.8 uA
PRTIM1 3.50 uA 23.0 uA 55.3 uA
PRTIM0 1.43 uA 9.2 uA 21.4 uA
PRSPI 5.01 uA 38.6 uA 111.4 uA
PRADC 6.34 uA 45.7 uA 123.6 uA

Table 29-6. ATmega168PA: Additional Current Consumption (percentage) in Active and Idle
mode
Additional Current consumption Additional Current consumption
compared to Active with external compared to Idle with external
clock (see Figure 29-93 on page clock (see Figure 29-98 on page
375 and Figure 29-94 on page 377 and Figure 29-99 on page
PRR bit 375) 378)
PRUSART0 1.5% 8.9%
PRTWI 3.2% 19.5%
PRTIM2 2.4% 14.8%
PRTIM1 1.7% 10.3%
PRTIM0 0.7% 4.1%
PRSPI 2.9% 17.1%
PRADC 3.4% 20.3%

It is possible to calculate the typical current consumption based on the numbers from Table 29-6
on page 380 for other VCC and frequency settings than listed in Table 29-5 on page 380.
Example Calculate the expected current consumption in idle mode with TIMER1, ADC, and SPI enabled
at VCC = 2.0V and F = 1MHz. From Table 29-6 on page 380, third column, we see that we need
to add 10.3% for the TIMER1, 20.3% for the ADC, and 17.1% for the SPI module. Reading from
Figure 29-98 on page 377, we find that the idle current consumption is ~0.027 mA at VCC = 2.0V
and F = 1MHz. The total current consumption in idle mode with TIMER1, ADC, and SPI enabled,
gives:
I CC total ≈ 0.027 mA ⋅ (1 + 0.103 + 0.203 + 0.171) ≈ 0.040 mA

380
8161D–AVR–10/09
 ATmega48PA/88PA/168PA/328P

29.3.4 Power-down Supply Current

Figure 29-103.ATmega168PA: Power-Down Supply Current vs. VCC (Watchdog Timer

Disabled)
1

85 °C
0.8

0.6
ICC (uA)

0.4

0.2
25 °C
-40 °C
0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

Figure 29-104.ATmega168PA: Power-Down Supply Current vs. VCC (Watchdog Timer Enabled)
8
-40 °C
85 °C
25 °C
6
ICC (uA)

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

381
8161D–AVR–10/09
 ATmega48PA/88PA/168PA/328P

29.3.5 Power-save Supply Current

Figure 29-105.ATmega168PA: Power-Save Supply Current vs. VCC (Watchdog Timer Disabled
and 32 kHz Crystal Oscillator Running)
2.5

85 °C
2

1.5
ICC (uA)

-40 °C
1
25 °C

0.5

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

29.3.6 Standby Supply Current

Figure 29-106.ATmega168PA: Standby Supply Current vs. Vcc (Watchdog Timer Disabled)
0.14 6MHz_xtal
6MHz_res
0.12
4MHz_res
0.1 4MHz_xtal

0.08
ICC(mA)

2MHz_res
2MHz_xtal
0.06 450kHz_res
1MHz_res
0.04

0.02

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (MHz)

382
8161D–AVR–10/09
 ATmega48PA/88PA/168PA/328P

29.3.7 Pin Pull-Up

Figure 29-107.ATmega168PA: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8 V)
50

40

30
IOP (uA)

20

10 25 °C
-40 °C
0 85 °C
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
VOP (V)

Figure 29-108.ATmega168PA: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7 V)
80

70

60

50
IOP (uA)

40

30

20 25 °C
10 -40 °C
85 °C
0
0 0.5 1 1.5 2 2.5 3
VOP (V)

383
8161D–AVR–10/09
 ATmega48PA/88PA/168PA/328P

Figure 29-109.ATmega168PA: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5 V)
160

140

120

100

IOP (uA)
80

60

40 25 °C
20 -40 °C
85 °C
0
0 1 2 3 4 5 6
VOP (V)

Figure 29-110.ATmega168PA: Reset Pull-up Resistor Current vs. Reset Pin Voltage
(VCC = 1.8 V)
40

35

30

25
IRESET (uA)

20

15

10
25 °C
5 -40 °C

0
85 °C
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
VRESET (V)

384
8161D–AVR–10/09
 ATmega48PA/88PA/168PA/328P

Figure 29-111.ATmega168PA: Reset Pull-up Resistor Current vs. Reset Pin Voltage
(VCC = 2.7 V)
60

50

40

IRESET (uA) 30

20

25 °C
10
-40 °C
85 °C
0
0 0.5 1 1.5 2 2.5 3
VRESET (V)

Figure 29-112.ATmega168PA: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V)
120

100

80
IRESET (uA)

60

40

20 25 °C
-40 °C
0
85 °C
0 1 2 3 4 5
VRESET (V)

385
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 ATmega48PA/88PA/168PA/328P

29.3.8 Pin Driver Strength

Figure 29-113.ATmega168PA: I/O Pin Output Voltage vs. Sink Current(VCC = 3 V)

1

85 °C
0.8

25 °C
0.6
VOL (V)
-40 °C

0.4

0.2

0
0 4 8 12 16 20
IOL (mA)

Figure 29-114.ATmega168PA: I/O Pin Output Voltage vs. Sink Current(VCC = 5 V)

0.6
85 °C
0.5
25 °C
0.4 -40 °C
VOL (V)

0.3

0.2

0.1

0
0 4 8 12 16 20
IOL (mA)

386
8161D–AVR–10/09
 ATmega48PA/88PA/168PA/328P

Figure 29-115.ATmega168PA: I/O Pin Output Voltage vs. Source Current(Vcc = 3 V)

3.5

2.5
-40 °C
25 °C
2 85 °C

VOH (V) 1.5

0.5

0
0 4 8 12 16 20
IOH (mA)

Figure 29-116.ATmega168PA: I/O Pin Output Voltage vs. Source Current(VCC = 5 V)

5

4.8

4.6
-40 °C
VOH (V)

25 °C
4.4 85 °C

4.2

4
0 4 8 12 16 20
IOH (mA)

387
8161D–AVR–10/09
 ATmega48PA/88PA/168PA/328P

29.3.9 Pin Threshold and Hysteresis

Figure 29-117.ATmega168PA: I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin read as ‘1’)
3 85 °C
25 °C
2.5 -40 °C

Threshold (V)
1.5

0.5

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

Figure 29-118.ATmega168PA: I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin read as ‘0’)
2.5 85 °C
25 °C
-40 °C
2
Threshold (V)

1.5

0.5

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

388
8161D–AVR–10/09
 ATmega48PA/88PA/168PA/328P

Figure 29-119.ATmega168PA: I/O Pin Input Hysteresis vs. VCC

0.6 85 °C
25 °C
-40 °C
0.5

Input Hysteresis (mV)

0.4

0.3

0.2

0.1

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

Figure 29-120.ATmega168PA: Reset Input Threshold Voltage vs. VCC (VIH, I/O Pin read as ‘1’)
1.5 85 °C
-40 °C
25 °C
1.2
Threshold (V)

0.9

0.6

0.3

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

389
8161D–AVR–10/09
 ATmega48PA/88PA/168PA/328P

Figure 29-121.ATmega168PA: Reset Input Threshold Voltage vs. VCC (VIL, I/O Pin read as ‘0’)
2.5 -40 °C
85 °C
25 °C
2

Threshold (V)
1.5

0.5

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

Figure 29-122.ATmega168PA: Reset Pin Input Hysteresis vs. VCC

0.7

0.6

0.5
Input Hysteresis (mV)

0.4

0.3

0.2
85 °C
0.1 25 °C
-40 °C
0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

390
8161D–AVR–10/09
 ATmega48PA/88PA/168PA/328P

29.3.10 BOD Threshold

Figure 29-123.ATmega168PA: BOD Thresholds vs. Temperature (BODLEVEL is 1.8 V)

1.86

1.84
Rising Vcc
1.82

Threshold (V)
1.8
Falling Vcc
1.78

1.76

1.74

1.72
-50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90
Temperature (°C)

Figure 29-124.ATmega168PA: BOD Thresholds vs. Temperature (BODLEVEL is 2.7 V)

2.76

Rising Vcc
2.74

2.72
Threshold (V)

2.7

2.68
Falling Vcc
2.66

2.64

2.62
-50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90
Temperature (°C)

391
8161D–AVR–10/09
 ATmega48PA/88PA/168PA/328P

Figure 29-125.ATmega168PA: BOD Thresholds vs. Temperature (BODLEVEL is 4.3 V)

4.34

4.32
Rising Vcc
4.3

Threshold (V)
4.28

4.26

Falling Vcc
4.24

4.22

4.2
-50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90
Temperature (°C)

29.3.11 Internal Oscilllator Speed

Figure 29-126.ATmega168PA: Watchdog Oscillator Frequency vs. Temperature

121

119

117
FRC (kHz)

115

2.7 V
113 3.3 V

5.5 V
111
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90
Temperature (°C)

392
8161D–AVR–10/09
 ATmega48PA/88PA/168PA/328P

Figure 29-127.ATmega168PA: Watchdog Oscillator Frequency vs. VCC

122

120

-40 °C
118

FRC (kHz)
116 25 °C

114

112
85 °C

110
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

Figure 29-128.ATmega168PA: Calibrated 8 MHz RC Oscillator Frequency vs. VCC

8,4

85 °C
8.2

25 °C
8
FRC (MHz)

7.8
-40 °C

7.6

7.4
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

393
8161D–AVR–10/09
 ATmega48PA/88PA/168PA/328P

Figure 29-129.ATmega168PA: Calibrated 8 MHz RC Oscillator Frequency vs. Temperature

8.3
5.5 V
8.2 5.0 V
2.7 V
8.1
1.8 V
8

FRC (MHz)
7.9

7.8

7.7

7.6

7.5
-50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90
Temperature (°C)

Figure 29-130.ATmega168PA: Calibrated 8 MHz RC Oscillator Frequency vs. OSCCAL Value

16
85 °C
14 25 °C
-40 °C
12

10
FRC (MHz)

0
0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256
OSCCAL (X1)

394
8161D–AVR–10/09
 ATmega48PA/88PA/168PA/328P

29.3.12 Current Consumption of Peripheral Units

Figure 29-131.ATmega168PA: ADC Current vs. VCC (AREF = AVCC)

350

-40 °C
300 25 °C
85 °C

ICC (uA) 250

200

150

100
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

Figure 29-132.ATmega168PA: Analog Comparator Current vs. VCC

90
-40 °C
80 25 °C
85 °C

70
ICC (uA)

60

50

40

30
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

395
8161D–AVR–10/09
 ATmega48PA/88PA/168PA/328P

Figure 29-133.ATmega168PA: AREF External Reference Current vs. VCC

180 25 °C
160 85 °C
-40 °C
140

120

ICC (uA)
100

80

60

40

20

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

Figure 29-134.ATmega168PA: Brownout Detector Current vs. VCC

26

85 °C
24
25 °C
22
-40 °C

20
ICC (uA)

18

16

14

12
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

396
8161D–AVR–10/09
 ATmega48PA/88PA/168PA/328P

Figure 29-135.ATmega168PA: Programming Current vs. VCC

10

-40 °C
8 25 °C

6 85 °C

ICC (mA)
4

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

29.3.13 Current Consumption in Reset and Reset Pulsewidth

Figure 29-136.ATmega168PA: Reset Supply Current vs. Low Frequency (0.1 - 1.0 MHz)
0.12

5.5 V
0.1

5.0 V
0.08
4.5 V
ICC (mA)

0.06 4.0 V

3.3 V
0.04
2.7 V
0.02 1.8 V

0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Frequency (MHz)

397
8161D–AVR–10/09
 ATmega48PA/88PA/168PA/328P

Figure 29-137.ATmega168PA: Reset Supply Current vs. Frequency (1 - 20 MHz)

2.5

5.5 V
2
5.0 V
1.5 4.5 V

ICC (mA)
4.0 V
1

3.3 V
0.5
2.7 V

0
1.8 V
0 2 4 6 8 10 12 14 16 18 20
Frequency (MHz)

Figure 29-138.ATmega168PA: Minimum Reset Pulse width vs. VCC

1750

1500

1250
Pulsewidth (ns)

1000

750

500
85 °C
250 25 °C
-40 °C
0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

398
8161D–AVR–10/09
 ATmega48PA/88PA/168PA/328P

29.4 ATmega328P Typical Characteristics

29.4.1 Active Supply Current

Figure 29-139.ATmega328P: Active Supply Current vs. Low Frequency (0.1-1.0 MHz)
1.2

5.5 V
1
5.0 V
0.8 4.5 V
ICC (mA)

4.0 V
0.6
3.3 V
0.4 2.7 V

1.8 V
0.2

0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Frequency (MHz)

Figure 29-140.ATmega328P: Active Supply Current vs. Frequency (1-20 MHz)

14
5.5 V
12 5.0 V

10 4.5 V
ICC (mA)

4.0 V
6
3.3 V
4
2.7 V
2
1.8 V
0
0 2 4 6 8 10 12 14 16 18 20
Frequency (MHz)

399
8161D–AVR–10/09
 ATmega48PA/88PA/168PA/328P

Figure 29-141.ATmega328P: Active Supply Current vs. VCC (Internal RC Oscillator, 128 kHz)
0.16
85 °C
25 °C
0.12 -40 °C

ICC (mA)

0.08

0.04

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

Figure 29-142.ATmega328P: Active Supply Current vs. VCC (Internal RC Oscillator, 1 MHz)
1.4
85 °C
1.2 25 °C
-40 °C
1

0.8
ICC (mA)

0.6

0.4

0.2

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

400
8161D–AVR–10/09
 ATmega48PA/88PA/168PA/328P

Figure 29-143.ATmega328P: Active Supply Current vs. VCC (Internal RC Oscillator, 8 MHz)
8

7
85 °C
6 25 °C
-40 °C
5
ICC (mA)
4

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

29.4.2 Idle Supply Current

Figure 29-144.ATmega328P: Idle Supply Current vs. Low Frequency (0.1-1.0 MHz)
0.2

5.5 V
0.16
5.0 V

4.5 V
0.12
ICC (mA)

4.0 V

0.08 3.3 V
2.7 V

0.04 1.8 V

0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Frequency (MHz)

401
8161D–AVR–10/09
 ATmega48PA/88PA/168PA/328P

Figure 29-145.ATmega328P: Idle Supply Current vs. Frequency (1-20 MHz)

4

3.5
5.5 V
3
5.0 V

I CC (mA)
2.5 4.5 V

4.0 V
1.5

3.3 V
1
2.7 V
0.5

1.8 V
0
0 2 4 6 8 10 12 14 16 18 20
Frequency (MHz)

, (Internal RC Oscillator, 128 kHz)

Figure 29-146.ATmega328P: Idle Supply Current vs. VCC
0.06

0.05

0.04 85 °C
ICC (mA)

25 °C
0.03
-40 °C

0.02

0.01

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

402
8161D–AVR–10/09
 ATmega48PA/88PA/168PA/328P

Figure 29-147.ATmega328P: Idle Supply Current vs. VCC (Internal RC Oscillator, 1 MHz)
0.4

0.35 85 °C
25 °C
0.3
-40 °C
ICC (mA) 0.25

0.2

0.15

0.1

0.05

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

Figure 29-148.ATmega328P: Idle Supply Current vs. Vcc (Internal RC Oscillator, 8 MHz)

85 °C
1.6
25 °C
-40 °C
1.2
ICC (mA)

0.8

0.4

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

403
8161D–AVR–10/09
 ATmega48PA/88PA/168PA/328P

29.4.3 ATmega328P Supply Current of IO Modules

The tables and formulas below can be used to calculate the additional current consumption for
the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules
are controlled by the Power Reduction Register. See ”Power Reduction Register” on page 42 for
details.

Table 29-7. ATmega328P: Additional Current Consumption for the different I/O modules
(absolute values)
PRR bit Typical numbers
VCC = 2V, F = 1MHz VCC = 3V, F = 4MHz VCC = 5V, F = 8MHz
PRUSART0 3.20 µA 22.17 µA 100.25 µA
PRTWI 7.34 µA 46.55 µA 199.25 µA
PRTIM2 7.34 µA 50.79 µA 224.25 µA
PRTIM1 6.19 µA 41.25 µA 176.25 µA
PRTIM0 1.89 µA 14.28 µA 61.13 µA
PRSPI 6.94 µA 43.84 µA 186.50 µA
PRADC 8.66 µA 61.80 µA 295.38 µA

Table 29-8. ATmega328P: Additional Current Consumption (percentage) in Active and Idle
mode
Additional Current consumption Additional Current consumption
compared to Active with external compared to Idle with external
clock (see Figure 29-139 on page clock (see Figure 29-144 on page
399 and Figure 29-140 on page 401 and Figure 29-145 on page
PRR bit 399) 402)
PRUSART0 1.4 % 7.8%
PRTWI 3.0 % 16.6 %
PRTIM2 3.3 % 17.8 %
PRTIM1 2.7 % 14.5 %
PRTIM0 0.9 % 4.8 %
PRSPI 2.9 % 15.7 %
PRADC 4.1 % 22.1 %

It is possible to calculate the typical current consumption based on the numbers from Table 29-8
on page 404 for other VCC and frequency settings than listed in Table 29-7 on page 404.
Example Calculate the expected current consumption in idle mode with TIMER1, ADC, and SPI enabled
at VCC = 2.0V and F = 1MHz. From Table 29-8 on page 404, third column, we see that we need
to add 14.5% for the TIMER1, 22.1% for the ADC, and 15.7% for the SPI module. Reading from
Figure 29-145 on page 402, we find that the idle current consumption is ~0.055 mA at VCC =
2.0V and F = 1MHz. The total current consumption in idle mode with TIMER1, ADC, and SPI
enabled, gives:
I CC total ≈ 0.045 mA ⋅ (1 + 0.145 + 0.221 + 0.157) ≈ 0.069 mA

404
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29.4.4 Power-down Supply Current

Figure 29-149.ATmega328P: Power-Down Supply Current vs. VCC (Watchdog Timer Disabled)
1.2

85 °C
1

0.8
ICC (uA)

0.6

0.4

0.2
25 °C
0 -40 °C
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

Figure 29-150.ATmega328P: Power-Down Supply Current vs. VCC (Watchdog Timer Enabled)
10

9
-40 °C
8 85 °C
25 °C
7

6
ICC (uA)

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

405
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 ATmega48PA/88PA/168PA/328P

29.4.5 Power-save Supply Current

Figure 29-151.ATmega328P: Power-Save Supply Current vs. VCC (Watchdog Timer Disabled
and 32 kHz Crystal Oscillator Running)
2

1.8

1.6

1.4 25 °C
1.2
ICC (uA)

0.8

0.6

0.4

0.2

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

29.4.6 Standby Supply Current

Figure 29-152.ATmega328P: Standby Supply Current vs. Vcc (Watchdog Timer Disabled)
0.16
6MHz_res
0.14
6MHz_xtal
0.12 4MHz_res
4MHz_xtal
0.1
2MHz_res
ICC (mA)

0.08 2MHz_xtal

0.06 1MHz_res

0.04

0.02

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

406
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29.4.7 Pin Pull-Up

Figure 29-153.ATmega328P: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8 V)
60

50

40
IOP (uA)

30

20

10 25 °C
85 °C
0 -40 °C
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
VOP (V)

Figure 29-154.ATmega328P: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7 V)
90

80

70

60

50
IOP (uA)

40

30

20 25 °C

10 85 °C
-40 °C
0
0 0.5 1 1.5 2 2.5 3
VOP (V)

407
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Figure 29-155.ATmega328P: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5 V)
160

140

120

IOP (uA) 100

80

60

40
25 °C
20 85 °C
-40 °C
0
0 1 2 3 4 5 6
VOP (V)

Figure 29-156.ATmega328P: Reset Pull-up Resistor Current vs. Reset Pin Voltage
(VCC = 1.8 V)
40

35

30

25
IRESET (uA)

20

15

10
25 °C
5 85 °C
-40 °C
0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
VRESET(V)

408
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Figure 29-157.ATmega328P: Reset Pull-up Resistor Current vs. Reset Pin Voltage
(VCC = 2.7 V)
70

60

50
IRESET (uA)

40

30

20
25 °C
10 85 °C
-40 °C
0
0 0.5 1 1.5 2 2.5 3
VRESET(V)

Figure 29-158.ATmega328P: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5 V)

120

100

80
IRESET(uA)

60

40
25 °C
20
85 °C
-40 °C
0
0 1 2 3 4 5 6
VRESET(V)

409
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29.4.8 Pin Driver Strength

Figure 29-159.ATmega328P: I/O Pin Output Voltage vs. Sink Current (VCC = 3 V)
1

85 °C
0.8

25 °C
0.6
V OL (V)

-40 °C

0.4

0.2

0
0 5 10 15 20 25
IOL (mA)

Figure 29-160.ATmega328P: I/O Pin Output Voltage vs. Sink Current (VCC = 5 V)
0.6
85 °C
0.5
25 °C

0.4
-40 °C
V OL (V)

0.3

0.2

0.1

0
0 5 10 15 20 25
IOL (mA)

410
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Figure 29-161.ATmega328P: I/O Pin Output Voltage vs. Source Current (Vcc = 3 V)
3.5

2.5
-40 °C
25 °C
2
V OH (V)
85 °C
1.5

0.5

0
0 5 10 15 20 25
IOH (mA)

Figure 29-162.ATmega328P: I/O Pin Output Voltage vs. Source Current(VCC = 5 V)

5.1

4.9

4.8
V OH (V)

4.7

4.6
-40 °C
4.5
25 °C
4.4
85 °C
4.3
0 5 10 15 20 25
IOH (mA)

411
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29.4.9 Pin Threshold and Hysteresis

Figure 29-163.ATmega328P: I/O Pin Input

, Threshold Voltage vs. VCC (VIH, I/O Pin read as ‘1’)
4

3.5

-40 °C
3
25 °C
85 °C
2.5
Threshold (V)

1.5

0.5

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

Figure 29-164.ATmega328P: I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin read as ‘0’)
2.5 85 °C
25 °C
2 -40 °C
Threshold (V)

1.5

0.5

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

412
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Figure 29-165.ATmega328P: I/O Pin Input Hysteresis vs. VCC

0.7
-40 °C
0.6 25 °C
85 °C
0.5
Input Hysteresis (mV)
0.4

0.3

0.2

0.1

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

Figure 29-166.ATmega328P: Reset Input Threshold Voltage vs. VCC (VIH, I/O Pin read as ‘1’)
2.5
-40 °C
25 °C
2 85 °C
Threshold (V)

1.5

0.5

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

413
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Figure 29-167.ATmega328P: Reset Input Threshold Voltage vs. VCC (VIL, I/O Pin read as ‘0’)
2.5 85 °C
25 °C
2 -40 °C

Threshold (V) 1.5

0.5

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

Figure 29-168.ATmega328P: Reset Pin Input Hysteresis vs. VCC

0.7

0.6

0.5
Input Hysteresis (mV)

0.4

0.3

0.2
-40 °C
0.1 25 °C
85 °C
0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

414
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29.4.10 BOD Threshold

Figure 29-169.ATmega328P: BOD Thresholds vs. Temperature (BODLEVEL is 1.8 V)

1.85

1.83
1
Threshold (V)

1.81

1.79 0

1.77

1.75
-60 -40 -20 0 20 40 60 80 100
Temperature (°C)

Figure 29-170.ATmega328P: BOD Thresholds vs. Temperature (BODLEVEL is 2.7 V)

2.78

2.76
1
2.74
Threshold (V)

2.72

2.7

2.68
0

2.66
-60 -40 -20 0 20 40 60 80 100
Temperature (°C)

415
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Figure 29-171.ATmega328P: BOD Thresholds vs. Temperature (BODLEVEL is 4.3 V)

4.4

4.35
Threshold (V)
1

4.3

0
4.25
-60 -40 -20 0 20 40 60 80 100
Temperature (°C)

29.4.11 Internal Oscilllator Speed

Figure 29-172.ATmega328P: Watchdog Oscillator Frequency vs. Temperature

119

118

117

116

115
F RC (kHz)

114

113

112
2.7 V

111
3.3 V

110
4.0 V
5.5 V
109
-60 -40 -20 0 20 40 60 80 100
Temperature (°C)

416
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Figure 29-173.ATmega328P: Watchdog Oscillator Frequency vs. VCC

120

118
-40 °C
116
F RC (kHz)

114 25 °C

112

110
85 °C

108
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

Figure 29-174.ATmega328P: Calibrated 8 MHz RC Oscillator Frequency vs. VCC

8.4
85 °C

8.2
25 °C

8
F RC (MHz)

7.8 -40 °C

7.6

7.4
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

417
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Figure 29-175.ATmega328P: Calibrated 8 MHz RC Oscillator Frequency vs. Temperature

8.4

5.0 V
8.3

3.0 V
8.2

F RC (MHz) 8.1

7.9

7.8

7.7

7.6
-50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100
Temperature (°C)

Figure 29-176.ATmega328P: Calibrated 8 MHz RC Oscillator Frequency vs. OSCCAL Value

16

14 85 °C
25 °C
12
-40 °C
10
F RC (MHz)

0
0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256
OSCCAL (X1)

418
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 ATmega48PA/88PA/168PA/328P

29.4.12 Current Consumption of Peripheral Units

Figure 29-177.ATmega328P: ADC Current vs. VCC (AREF = AVCC)

350 -40 °C
25 °C
300 85 °C

250

200
ICC (uA)

150

100

50

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

Figure 29-178.ATmega328P: Analog Comparator Current vs. VCC

120

100
-40 °C
80 25 °C
85 °C
ICC (uA)

60

40

20

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

419
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 ATmega48PA/88PA/168PA/328P

Figure 29-179.ATmega328P: AREF External Reference Current vs. VCC

180
85 °C
160
25 °C
140 -40 °C

120

100
ICC (uA)

80

60

40

20

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

Figure 29-180.ATmega328P: Brownout Detector Current vs. VCC

30

25 85 °C
25 °C
-40 °C
20
ICC (uA)

15

10

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

420
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Figure 29-181.ATmega328P: Programming Current vs. VCC

10

9
25 °C
8 85 °C
-40 °C
7

ICC (mA) 6

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

29.4.13 Current Consumption in Reset and Reset Pulsewidth

Figure 29-182.ATmega328P: Reset Supply Current vs. Low Frequency (0.1 - 1.0 MHz)
0.15
5.5 V

5.0 V

0.1 4.5 V

4.0 V
ICC (mA)

3.3 V
0.05 2.7 V

1.8 V

0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Frequency (MHz)

421
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 ATmega48PA/88PA/168PA/328P

Figure 29-183.ATmega328P: Reset Supply Current vs. Frequency (1 - 20 MHz)

3
5.5 V

2.5 5.0 V

4.5 V
2
ICC (mA)
4.0 V
1.5

1
3.3 V

0.5
2.7 V

1.8 V
0
0 2 4 6 8 10 12 14 16 18 20
Frequency (MHz)

Figure 29-184.ATmega328P: Minimum Reset Pulse width vs. VCC

1800

1600

1400

1200
Pulsewidth (ns)

1000

800

600

400
85 °C
200 25 °C
-40 °C
0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)

422
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30. Register Summary

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
(0xFF) Reserved – – – – – – – –
(0xFE) Reserved – – – – – – – –
(0xFD) Reserved – – – – – – – –
(0xFC) Reserved – – – – – – – –
(0xFB) Reserved – – – – – – – –
(0xFA) Reserved – – – – – – – –
(0xF9) Reserved – – – – – – – –
(0xF8) Reserved – – – – – – – –
(0xF7) Reserved – – – – – – – –
(0xF6) Reserved – – – – – – – –
(0xF5) Reserved – – – – – – – –
(0xF4) Reserved – – – – – – – –
(0xF3) Reserved – – – – – – – –
(0xF2) Reserved – – – – – – – –
(0xF1) Reserved – – – – – – – –
(0xF0) Reserved – – – – – – – –
(0xEF) Reserved – – – – – – – –
(0xEE) Reserved – – – – – – – –
(0xED) Reserved – – – – – – – –
(0xEC) Reserved – – – – – – – –
(0xEB) Reserved – – – – – – – –
(0xEA) Reserved – – – – – – – –
(0xE9) Reserved – – – – – – – –
(0xE8) Reserved – – – – – – – –
(0xE7) Reserved – – – – – – – –
(0xE6) Reserved – – – – – – – –
(0xE5) Reserved – – – – – – – –
(0xE4) Reserved – – – – – – – –
(0xE3) Reserved – – – – – – – –
(0xE2) Reserved – – – – – – – –
(0xE1) Reserved – – – – – – – –
(0xE0) Reserved – – – – – – – –
(0xDF) Reserved – – – – – – – –
(0xDE) Reserved – – – – – – – –
(0xDD) Reserved – – – – – – – –
(0xDC) Reserved – – – – – – – –
(0xDB) Reserved – – – – – – – –
(0xDA) Reserved – – – – – – – –
(0xD9) Reserved – – – – – – – –
(0xD8) Reserved – – – – – – – –
(0xD7) Reserved – – – – – – – –
(0xD6) Reserved – – – – – – – –
(0xD5) Reserved – – – – – – – –
(0xD4) Reserved – – – – – – – –
(0xD3) Reserved – – – – – – – –
(0xD2) Reserved – – – – – – – –
(0xD1) Reserved – – – – – – – –
(0xD0) Reserved – – – – – – – –
(0xCF) Reserved – – – – – – – –
(0xCE) Reserved – – – – – – – –
(0xCD) Reserved – – – – – – – –
(0xCC) Reserved – – – – – – – –
(0xCB) Reserved – – – – – – – –
(0xCA) Reserved – – – – – – – –
(0xC9) Reserved – – – – – – – –
(0xC8) Reserved – – – – – – – –
(0xC7) Reserved – – – – – – – –
(0xC6) UDR0 USART I/O Data Register 195
(0xC5) UBRR0H USART Baud Rate Register High 199
(0xC4) UBRR0L USART Baud Rate Register Low 199
(0xC3) Reserved – – – – – – – –
(0xC2) UCSR0C UMSEL01 UMSEL00 UPM01 UPM00 USBS0 UCSZ01 /UDORD0 UCSZ00 / UCPHA0 UCPOL0 197/212
(0xC1) UCSR0B RXCIE0 TXCIE0 UDRIE0 RXEN0 TXEN0 UCSZ02 RXB80 TXB80 196
(0xC0) UCSR0A RXC0 TXC0 UDRE0 FE0 DOR0 UPE0 U2X0 MPCM0 195

423
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Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
(0xBF) Reserved – – – – – – – –
(0xBE) Reserved – – – – – – – –
(0xBD) TWAMR TWAM6 TWAM5 TWAM4 TWAM3 TWAM2 TWAM1 TWAM0 – 244
(0xBC) TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE 241
(0xBB) TWDR 2-wire Serial Interface Data Register 243
(0xBA) TWAR TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE 244
(0xB9) TWSR TWS7 TWS6 TWS5 TWS4 TWS3 – TWPS1 TWPS0 243
(0xB8) TWBR 2-wire Serial Interface Bit Rate Register 241
(0xB7) Reserved – – – – – – –
(0xB6) ASSR – EXCLK AS2 TCN2UB OCR2AUB OCR2BUB TCR2AUB TCR2BUB 164
(0xB5) Reserved – – – – – – – –
(0xB4) OCR2B Timer/Counter2 Output Compare Register B 162
(0xB3) OCR2A Timer/Counter2 Output Compare Register A 162
(0xB2) TCNT2 Timer/Counter2 (8-bit) 162
(0xB1) TCCR2B FOC2A FOC2B – – WGM22 CS22 CS21 CS20 161
(0xB0) TCCR2A COM2A1 COM2A0 COM2B1 COM2B0 – – WGM21 WGM20 158
(0xAF) Reserved – – – – – – – –
(0xAE) Reserved – – – – – – – –
(0xAD) Reserved – – – – – – – –
(0xAC) Reserved – – – – – – – –
(0xAB) Reserved – – – – – – – –
(0xAA) Reserved – – – – – – – –
(0xA9) Reserved – – – – – – – –
(0xA8) Reserved – – – – – – – –
(0xA7) Reserved – – – – – – – –
(0xA6) Reserved – – – – – – – –
(0xA5) Reserved – – – – – – – –
(0xA4) Reserved – – – – – – – –
(0xA3) Reserved – – – – – – – –
(0xA2) Reserved – – – – – – – –
(0xA1) Reserved – – – – – – – –
(0xA0) Reserved – – – – – – – –
(0x9F) Reserved – – – – – – – –
(0x9E) Reserved – – – – – – – –
(0x9D) Reserved – – – – – – – –
(0x9C) Reserved – – – – – – – –
(0x9B) Reserved – – – – – – – –
(0x9A) Reserved – – – – – – – –
(0x99) Reserved – – – – – – – –
(0x98) Reserved – – – – – – – –
(0x97) Reserved – – – – – – – –
(0x96) Reserved – – – – – – – –
(0x95) Reserved – – – – – – – –
(0x94) Reserved – – – – – – – –
(0x93) Reserved – – – – – – – –
(0x92) Reserved – – – – – – – –
(0x91) Reserved – – – – – – – –
(0x90) Reserved – – – – – – – –
(0x8F) Reserved – – – – – – – –
(0x8E) Reserved – – – – – – – –
(0x8D) Reserved – – – – – – – –
(0x8C) Reserved – – – – – – – –
(0x8B) OCR1BH Timer/Counter1 - Output Compare Register B High Byte 138
(0x8A) OCR1BL Timer/Counter1 - Output Compare Register B Low Byte 138
(0x89) OCR1AH Timer/Counter1 - Output Compare Register A High Byte 138
(0x88) OCR1AL Timer/Counter1 - Output Compare Register A Low Byte 138
(0x87) ICR1H Timer/Counter1 - Input Capture Register High Byte 138
(0x86) ICR1L Timer/Counter1 - Input Capture Register Low Byte 138
(0x85) TCNT1H Timer/Counter1 - Counter Register High Byte 138
(0x84) TCNT1L Timer/Counter1 - Counter Register Low Byte 138
(0x83) Reserved – – – – – – – –
(0x82) TCCR1C FOC1A FOC1B – – – – – – 137
(0x81) TCCR1B ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 136
(0x80) TCCR1A COM1A1 COM1A0 COM1B1 COM1B0 – – WGM11 WGM10 134
(0x7F) DIDR1 – – – – – – AIN1D AIN0D 249
(0x7E) DIDR0 – – ADC5D ADC4D ADC3D ADC2D ADC1D ADC0D 266

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Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
(0x7D) Reserved – – – – – – – –
(0x7C) ADMUX REFS1 REFS0 ADLAR – MUX3 MUX2 MUX1 MUX0 262
(0x7B) ADCSRB – ACME – – – ADTS2 ADTS1 ADTS0 265
(0x7A) ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 263
(0x79) ADCH ADC Data Register High byte 265
(0x78) ADCL ADC Data Register Low byte 265
(0x77) Reserved – – – – – – – –
(0x76) Reserved – – – – – – – –
(0x75) Reserved – – – – – – – –
(0x74) Reserved – – – – – – – –
(0x73) Reserved – – – – – – – –
(0x72) Reserved – – – – – – – –
(0x71) Reserved – – – – – – – –
(0x70) TIMSK2 – – – – – OCIE2B OCIE2A TOIE2 163
(0x6F) TIMSK1 – – ICIE1 – – OCIE1B OCIE1A TOIE1 139
(0x6E) TIMSK0 – – – – – OCIE0B OCIE0A TOIE0 111
(0x6D) PCMSK2 PCINT23 PCINT22 PCINT21 PCINT20 PCINT19 PCINT18 PCINT17 PCINT16 74
(0x6C) PCMSK1 – PCINT14 PCINT13 PCINT12 PCINT11 PCINT10 PCINT9 PCINT8 74
(0x6B) PCMSK0 PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 74
(0x6A) Reserved – – – – – – – –
(0x69) EICRA – – – – ISC11 ISC10 ISC01 ISC00 71
(0x68) PCICR – – – – – PCIE2 PCIE1 PCIE0
(0x67) Reserved – – – – – – – –
(0x66) OSCCAL Oscillator Calibration Register 37
(0x65) Reserved – – – – – – – –
(0x64) PRR PRTWI PRTIM2 PRTIM0 – PRTIM1 PRSPI PRUSART0 PRADC 42
(0x63) Reserved – – – – – – – –
(0x62) Reserved – – – – – – – –
(0x61) CLKPR CLKPCE – – – CLKPS3 CLKPS2 CLKPS1 CLKPS0 37
(0x60) WDTCSR WDIF WDIE WDP3 WDCE WDE WDP2 WDP1 WDP0 54
0x3F (0x5F) SREG I T H S V N Z C 9
0x3E (0x5E) SPH – – – – – (SP10) 5. SP9 SP8 12
0x3D (0x5D) SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 12
0x3C (0x5C) Reserved – – – – – – – –
0x3B (0x5B) Reserved – – – – – – – –
0x3A (0x5A) Reserved – – – – – – – –
0x39 (0x59) Reserved – – – – – – – –
0x38 (0x58) Reserved – – – – – – – –
0x37 (0x57) SPMCSR SPMIE (RWWSB)5. – (RWWSRE)5. BLBSET PGWRT PGERS SELFPRGEN 292
0x36 (0x56) Reserved – – – – – – – –
0x35 (0x55) MCUCR – BODS BODSE PUD – – IVSEL IVCE 44/68/92
0x34 (0x54) MCUSR – – – – WDRF BORF EXTRF PORF 54
0x33 (0x53) SMCR – – – – SM2 SM1 SM0 SE 40
0x32 (0x52) Reserved – – – – – – – –
0x31 (0x51) Reserved – – – – – – – –
0x30 (0x50) ACSR ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 247
0x2F (0x4F) Reserved – – – – – – – –
0x2E (0x4E) SPDR SPI Data Register 175
0x2D (0x4D) SPSR SPIF WCOL – – – – – SPI2X 174
0x2C (0x4C) SPCR SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 173
0x2B (0x4B) GPIOR2 General Purpose I/O Register 2 25
0x2A (0x4A) GPIOR1 General Purpose I/O Register 1 25
0x29 (0x49) Reserved – – – – – – – –
0x28 (0x48) OCR0B Timer/Counter0 Output Compare Register B
0x27 (0x47) OCR0A Timer/Counter0 Output Compare Register A
0x26 (0x46) TCNT0 Timer/Counter0 (8-bit)
0x25 (0x45) TCCR0B FOC0A FOC0B – – WGM02 CS02 CS01 CS00
0x24 (0x44) TCCR0A COM0A1 COM0A0 COM0B1 COM0B0 – – WGM01 WGM00
0x23 (0x43) GTCCR TSM – – – – – PSRASY PSRSYNC 143/165
0x22 (0x42) EEARH (EEPROM Address Register High Byte) 5. 21
0x21 (0x41) EEARL EEPROM Address Register Low Byte 21
0x20 (0x40) EEDR EEPROM Data Register 21
0x1F (0x3F) EECR – – EEPM1 EEPM0 EERIE EEMPE EEPE EERE 21
0x1E (0x3E) GPIOR0 General Purpose I/O Register 0 25
0x1D (0x3D) EIMSK – – – – – – INT1 INT0 72
0x1C (0x3C) EIFR – – – – – – INTF1 INTF0 72

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Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
0x1B (0x3B) PCIFR – – – – – PCIF2 PCIF1 PCIF0
0x1A (0x3A) Reserved – – – – – – – –
0x19 (0x39) Reserved – – – – – – – –
0x18 (0x38) Reserved – – – – – – – –
0x17 (0x37) TIFR2 – – – – – OCF2B OCF2A TOV2 163
0x16 (0x36) TIFR1 – – ICF1 – – OCF1B OCF1A TOV1 139
0x15 (0x35) TIFR0 – – – – – OCF0B OCF0A TOV0
0x14 (0x34) Reserved – – – – – – – –
0x13 (0x33) Reserved – – – – – – – –
0x12 (0x32) Reserved – – – – – – – –
0x11 (0x31) Reserved – – – – – – – –
0x10 (0x30) Reserved – – – – – – – –
0x0F (0x2F) Reserved – – – – – – – –
0x0E (0x2E) Reserved – – – – – – – –
0x0D (0x2D) Reserved – – – – – – – –
0x0C (0x2C) Reserved – – – – – – – –
0x0B (0x2B) PORTD PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 93
0x0A (0x2A) DDRD DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 93
0x09 (0x29) PIND PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 93
0x08 (0x28) PORTC – PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 92
0x07 (0x27) DDRC – DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 92
0x06 (0x26) PINC – PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 92
0x05 (0x25) PORTB PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 92
0x04 (0x24) DDRB DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 92
0x03 (0x23) PINB PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 92
0x02 (0x22) Reserved – – – – – – – –
0x01 (0x21) Reserved – – – – – – – –
0x0 (0x20) Reserved – – – – – – – –

Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these
registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI
instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The
CBI and SBI instructions work with registers 0x00 to 0x1F only.
4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O
Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The
ATmega48PA/88PA/168PA/328P is a complex microcontroller with more peripheral units than can be supported within the 64
location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only
the ST/STS/STD and LD/LDS/LDD instructions can be used.
5. Only valid for ATmega88PA/168PA.

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31. Instruction Set Summary

Mnemonics Operands Description Operation Flags #Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD Rd, Rr Add two Registers Rd ← Rd + Rr Z,C,N,V,H 1
ADC Rd, Rr Add with Carry two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1
ADIW Rdl,K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S 2
SUB Rd, Rr Subtract two Registers Rd ← Rd - Rr Z,C,N,V,H 1
SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1
SBC Rd, Rr Subtract with Carry two Registers Rd ← Rd - Rr - C Z,C,N,V,H 1
SBCI Rd, K Subtract with Carry Constant from Reg. Rd ← Rd - K - C Z,C,N,V,H 1
SBIW Rdl,K Subtract Immediate from Word Rdh:Rdl ← Rdh:Rdl - K Z,C,N,V,S 2
AND Rd, Rr Logical AND Registers Rd ← Rd • Rr Z,N,V 1
ANDI Rd, K Logical AND Register and Constant Rd ← Rd • K Z,N,V 1
OR Rd, Rr Logical OR Registers Rd ← Rd v Rr Z,N,V 1
ORI Rd, K Logical OR Register and Constant Rd ← Rd v K Z,N,V 1
EOR Rd, Rr Exclusive OR Registers Rd ← Rd ⊕ Rr Z,N,V 1
COM Rd One’s Complement Rd ← 0xFF − Rd Z,C,N,V 1
NEG Rd Two’s Complement Rd ← 0x00 − Rd Z,C,N,V,H 1
SBR Rd,K Set Bit(s) in Register Rd ← Rd v K Z,N,V 1
CBR Rd,K Clear Bit(s) in Register Rd ← Rd • (0xFF - K) Z,N,V 1
INC Rd Increment Rd ← Rd + 1 Z,N,V 1
DEC Rd Decrement Rd ← Rd − 1 Z,N,V 1
TST Rd Test for Zero or Minus Rd ← Rd • Rd Z,N,V 1
CLR Rd Clear Register Rd ← Rd ⊕ Rd Z,N,V 1
SER Rd Set Register Rd ← 0xFF None 1
MUL Rd, Rr Multiply Unsigned R1:R0 ← Rd x Rr Z,C 2
MULS Rd, Rr Multiply Signed R1:R0 ← Rd x Rr Z,C 2
MULSU Rd, Rr Multiply Signed with Unsigned R1:R0 ← Rd x Rr Z,C 2
FMUL Rd, Rr Fractional Multiply Unsigned R1:R0 ← (Rd x Rr) << 1 Z,C 2
FMULS Rd, Rr Fractional Multiply Signed R1:R0 ← (Rd x Rr) << 1 Z,C 2
FMULSU Rd, Rr Fractional Multiply Signed with Unsigned R1:R0 ← (Rd x Rr) << 1 Z,C 2
BRANCH INSTRUCTIONS
RJMP k Relative Jump PC ← PC + k + 1 None 2
IJMP Indirect Jump to (Z) PC ← Z None 2
JMP(1) k Direct Jump PC ← k None 3
RCALL k Relative Subroutine Call PC ← PC + k + 1 None 3
ICALL Indirect Call to (Z) PC ← Z None 3
CALL(1) k Direct Subroutine Call PC ← k None 4
RET Subroutine Return PC ← STACK None 4
RETI Interrupt Return PC ← STACK I 4
CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC ← PC + 2 or 3 None 1/2/3
CP Rd,Rr Compare Rd − Rr Z, N,V,C,H 1
CPC Rd,Rr Compare with Carry Rd − Rr − C Z, N,V,C,H 1
CPI Rd,K Compare Register with Immediate Rd − K Z, N,V,C,H 1
SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC ← PC + 2 or 3 None 1/2/3
SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC ← PC + 2 or 3 None 1/2/3
SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC ← PC + 2 or 3 None 1/2/3
SBIS P, b Skip if Bit in I/O Register is Set if (P(b)=1) PC ← PC + 2 or 3 None 1/2/3
BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC←PC+k + 1 None 1/2
BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC←PC+k + 1 None 1/2
BREQ k Branch if Equal if (Z = 1) then PC ← PC + k + 1 None 1/2
BRNE k Branch if Not Equal if (Z = 0) then PC ← PC + k + 1 None 1/2
BRCS k Branch if Carry Set if (C = 1) then PC ← PC + k + 1 None 1/2
BRCC k Branch if Carry Cleared if (C = 0) then PC ← PC + k + 1 None 1/2
BRSH k Branch if Same or Higher if (C = 0) then PC ← PC + k + 1 None 1/2
BRLO k Branch if Lower if (C = 1) then PC ← PC + k + 1 None 1/2
BRMI k Branch if Minus if (N = 1) then PC ← PC + k + 1 None 1/2
BRPL k Branch if Plus if (N = 0) then PC ← PC + k + 1 None 1/2
BRGE k Branch if Greater or Equal, Signed if (N ⊕ V= 0) then PC ← PC + k + 1 None 1/2
BRLT k Branch if Less Than Zero, Signed if (N ⊕ V= 1) then PC ← PC + k + 1 None 1/2
BRHS k Branch if Half Carry Flag Set if (H = 1) then PC ← PC + k + 1 None 1/2
BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC ← PC + k + 1 None 1/2
BRTS k Branch if T Flag Set if (T = 1) then PC ← PC + k + 1 None 1/2
BRTC k Branch if T Flag Cleared if (T = 0) then PC ← PC + k + 1 None 1/2
BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ← PC + k + 1 None 1/2
BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1 None 1/2

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Mnemonics Operands Description Operation Flags #Clocks

BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None 1/2
BRID k Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1 None 1/2
BIT AND BIT-TEST INSTRUCTIONS
SBI P,b Set Bit in I/O Register I/O(P,b) ← 1 None 2
CBI P,b Clear Bit in I/O Register I/O(P,b) ← 0 None 2
LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), Rd(0) ← 0 Z,C,N,V 1
LSR Rd Logical Shift Right Rd(n) ← Rd(n+1), Rd(7) ← 0 Z,C,N,V 1
ROL Rd Rotate Left Through Carry Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7) Z,C,N,V 1
ROR Rd Rotate Right Through Carry Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0) Z,C,N,V 1
ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n=0..6 Z,C,N,V 1
SWAP Rd Swap Nibbles Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0) None 1
BSET s Flag Set SREG(s) ← 1 SREG(s) 1
BCLR s Flag Clear SREG(s) ← 0 SREG(s) 1
BST Rr, b Bit Store from Register to T T ← Rr(b) T 1
BLD Rd, b Bit load from T to Register Rd(b) ← T None 1
SEC Set Carry C←1 C 1
CLC Clear Carry C←0 C 1
SEN Set Negative Flag N←1 N 1
CLN Clear Negative Flag N←0 N 1
SEZ Set Zero Flag Z←1 Z 1
CLZ Clear Zero Flag Z←0 Z 1
SEI Global Interrupt Enable I←1 I 1
CLI Global Interrupt Disable I←0 I 1
SES Set Signed Test Flag S←1 S 1
CLS Clear Signed Test Flag S←0 S 1
SEV Set Twos Complement Overflow. V←1 V 1
CLV Clear Twos Complement Overflow V←0 V 1
SET Set T in SREG T←1 T 1
CLT Clear T in SREG T←0 T 1
SEH Set Half Carry Flag in SREG H←1 H 1
CLH Clear Half Carry Flag in SREG H←0 H 1
DATA TRANSFER INSTRUCTIONS
MOV Rd, Rr Move Between Registers Rd ← Rr None 1
MOVW Rd, Rr Copy Register Word Rd+1:Rd ← Rr+1:Rr None 1
LDI Rd, K Load Immediate Rd ← K None 1
LD Rd, X Load Indirect Rd ← (X) None 2
LD Rd, X+ Load Indirect and Post-Inc. Rd ← (X), X ← X + 1 None 2
LD Rd, - X Load Indirect and Pre-Dec. X ← X - 1, Rd ← (X) None 2
LD Rd, Y Load Indirect Rd ← (Y) None 2
LD Rd, Y+ Load Indirect and Post-Inc. Rd ← (Y), Y ← Y + 1 None 2
LD Rd, - Y Load Indirect and Pre-Dec. Y ← Y - 1, Rd ← (Y) None 2
LDD Rd,Y+q Load Indirect with Displacement Rd ← (Y + q) None 2
LD Rd, Z Load Indirect Rd ← (Z) None 2
LD Rd, Z+ Load Indirect and Post-Inc. Rd ← (Z), Z ← Z+1 None 2
LD Rd, -Z Load Indirect and Pre-Dec. Z ← Z - 1, Rd ← (Z) None 2
LDD Rd, Z+q Load Indirect with Displacement Rd ← (Z + q) None 2
LDS Rd, k Load Direct from SRAM Rd ← (k) None 2
ST X, Rr Store Indirect (X) ← Rr None 2
ST X+, Rr Store Indirect and Post-Inc. (X) ← Rr, X ← X + 1 None 2
ST - X, Rr Store Indirect and Pre-Dec. X ← X - 1, (X) ← Rr None 2
ST Y, Rr Store Indirect (Y) ← Rr None 2
ST Y+, Rr Store Indirect and Post-Inc. (Y) ← Rr, Y ← Y + 1 None 2
ST - Y, Rr Store Indirect and Pre-Dec. Y ← Y - 1, (Y) ← Rr None 2
STD Y+q,Rr Store Indirect with Displacement (Y + q) ← Rr None 2
ST Z, Rr Store Indirect (Z) ← Rr None 2
ST Z+, Rr Store Indirect and Post-Inc. (Z) ← Rr, Z ← Z + 1 None 2
ST -Z, Rr Store Indirect and Pre-Dec. Z ← Z - 1, (Z) ← Rr None 2
STD Z+q,Rr Store Indirect with Displacement (Z + q) ← Rr None 2
STS k, Rr Store Direct to SRAM (k) ← Rr None 2
LPM Load Program Memory R0 ← (Z) None 3
LPM Rd, Z Load Program Memory Rd ← (Z) None 3
LPM Rd, Z+ Load Program Memory and Post-Inc Rd ← (Z), Z ← Z+1 None 3
SPM Store Program Memory (Z) ← R1:R0 None -
IN Rd, P In Port Rd ← P None 1
OUT P, Rr Out Port P ← Rr None 1
PUSH Rr Push Register on Stack STACK ← Rr None 2

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Mnemonics Operands Description Operation Flags #Clocks

POP Rd Pop Register from Stack Rd ← STACK None 2
MCU CONTROL INSTRUCTIONS
NOP No Operation None 1
SLEEP Sleep (see specific descr. for Sleep function) None 1
WDR Watchdog Reset (see specific descr. for WDR/timer) None 1
BREAK Break For On-chip Debug Only None N/A

Note: 1. These instructions are only available in ATmega168PA and ATmega328P.

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32. Ordering Information

32.1 ATmega48PA

Speed (MHz) Power Supply Ordering Code(2) Package(1) Operational Range

ATmega48PA-AU 32A
ATmega48PA-MMH(4) 28M1 Industrial
20(3) 1.8 - 5.5
ATmega48PA-MU 32M1-A (-40°C to 85°C)
ATmega48PA-PU 28P3
Note: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive).Also
Halide free and fully Green.
3. See ”Speed Grades” on page 316.
4. NiPdAu Lead Finish.

Package Type
32A 32-lead, Thin (1.0 mm) Plastic Quad Flat Package (TQFP)
28M1 28-pad, 4 x 4 x 1.0 body, Lead Pitch 0.45 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
32M1-A 32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
28P3 28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)

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32.2 ATmega88PA

Speed (MHz) Power Supply Ordering Code(2) Package(1) Operational Range

ATmega88PA-AU 32A
ATmega88PA-MMH(4) 28M1 Industrial
20(3) 1.8 - 5.5
ATmega88PA-MU 32M1-A (-40°C to 85°C)
ATmega88PA-PU 28P3
Note: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive).Also
Halide free and fully Green.
3. See ”Speed Grades” on page 316.
4. NiPdAu Lead Finish.

Package Type
32A 32-lead, Thin (1.0 mm) Plastic Quad Flat Package (TQFP)
28M1 28-pad, 4 x 4 x 1.0 body, Lead Pitch 0.45 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
32M1-A 32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
28P3 28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)

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32.3 ATmega168PA

Speed (MHz)(3) Power Supply Ordering Code(2) Package(1) Operational Range

ATmega168PA-AU 32A
ATmega168PA-MMH(4) 28M1 Industrial
20 1.8 - 5.5
ATmega168PA-MU 32M1-A (-40°C to 85°C)
ATmega168PA-PU 28P3
Note: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive).Also
Halide free and fully Green.
3. See ”Speed Grades” on page 316.
4. NiPdAu Lead Finish.

Package Type
32A 32-lead, Thin (1.0 mm) Plastic Quad Flat Package (TQFP)
28M1 28-pad, 4 x 4 x 1.0 body, Lead Pitch 0.45 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
32M1-A 32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
28P3 28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)

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 ATmega48PA/88PA/168PA/328P

32.4 ATmega328P

Speed (MHz) Power Supply Ordering Code(2) Package(1) Operational Range

ATmega328P- AU 32A
Industrial
20(3) 1.8 - 5.5 ATmega328P- MU 32M1-A
(-40°C to 85°C)
ATmega328P- PU 28P3
Note: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive).Also
Halide free and fully Green.
3. See Figure 28-1 on page 316.

Package Type
32A 32-lead, Thin (1.0 mm) Plastic Quad Flat Package (TQFP)
28P3 28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)
32M1-A 32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

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 ATmega48PA/88PA/168PA/328P

33. Packaging Information

33.1 32A

PIN 1
B
PIN 1 IDENTIFIER

e E1 E

D1
D

C 0˚~7˚

A1 A2 A
L
COMMON DIMENSIONS
(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

A – – 1.20
A1 0.05 – 0.15
A2 0.95 1.00 1.05
D 8.75 9.00 9.25
D1 6.90 7.00 7.10 Note 2
E 8.75 9.00 9.25
Notes: 1. This package conforms to JEDEC reference MS-026, Variation ABA.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable E1 6.90 7.00 7.10 Note 2
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum B 0.30 – 0.45
plastic body size dimensions including mold mismatch.
C 0.09 – 0.20
3. Lead coplanarity is 0.10 mm maximum.
L 0.45 – 0.75
e 0.80 TYP

10/5/2001
TITLE DRAWING NO. REV.
2325 Orchard Parkway
32A, 32-lead, 7 x 7 mm Body Size, 1.0 mm Body Thickness,
R San Jose, CA 95131 32A B
0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)

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33.2 28M1

1
Pin 1 ID
2

3 E SIDE VIEW

TOP VIEW
A2

D2
A1

1 0.08 C

Pin #1 2
Notch COMMON DIMENSIONS
(0.20 R) 3 E2 (Unit of Measure = mm)

b SYMBOL MIN NOM MAX NOTE

A 0.70 0.75 0.80
A1 – 0.01 0.05
L A2 0.20 REF
b 0.18 0.23 0.30
e
D 4.00 BSC

BOTTOM VIEW D2 2.45 2.60 2.75

E 4.00 BSC
E2 2.45 2.60 2.75
e 0.50 BSC
Note: Reference JEDEC Standard MO-220, Fig. 1 (SAW Singulation) WGGD-5. L 0.35 0.40 0.55

10/27/04
TITLE DRAWING NO. REV.
2325 Orchard Parkway 20M1, 20-pad, 4 x 4 x 0.8 mm Body, Lead Pitch 0.50 mm,
S J CA 9 131 26 E d P d Mi L dF P k (MLF) 20M1 A

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33.3 32M1-A

D1

1
0
2
3 Pin 1 ID

E1 E SIDE VIEW

TOP VIEW A3
A2
A1
A
K
0.08 C COMMON DIMENSIONS
P (Unit of Measure = mm)
D2
SYMBOL MIN NOM MAX NOTE
A 0.80 0.90 1.00

1 A1 – 0.02 0.05
P
2 A2 – 0.65 1.00
Pin #1 Notch
(0.20 R) 3
A3 0.20 REF
E2
b 0.18 0.23 0.30

K D 4.90 5.00 5.10

D1 4.70 4.75 4.80
D2 2.95 3.10 3.25
E 4.90 5.00 5.10
b e L
E1 4.70 4.75 4.80

BOTTOM VIEW E2 2.95 3.10 3.25

e 0.50 BSC
L 0.30 0.40 0.50
P – – 0.60
0 – – 12o
Note: JEDEC Standard MO-220, Fig. 2 (Anvil Singulation), VHHD-2. K 0.20 – –

5/25/06
TITLE DRAWING NO. REV.
2325 Orchard Parkway
32M1-A, 32-pad, 5 x 5 x 1.0 mm Body, Lead Pitch 0.50 mm, 32M1-A E
R San Jose, CA 95131 3.10 mm Exposed Pad, Micro Lead Frame Package (MLF)

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33.4 28P3

D
PIN
1

E1

SEATING PLANE

A1
L B2
B (4 PLACES)
B1
e

COMMON DIMENSIONS
0º ~ 15º REF (Unit of Measure = mm)
C
SYMBOL MIN NOM MAX NOTE

eB A – – 4.5724
A1 0.508 – –
D 34.544 – 34.798 Note 1
E 7.620 – 8.255
E1 7.112 – 7.493 Note 1
B 0.381 – 0.533

Note: 1. Dimensions D and E1 do not include mold Flash or Protrusion. B1 1.143 – 1.397
Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). B2 0.762 – 1.143
L 3.175 – 3.429
C 0.203 – 0.356
eB – – 10.160
e 2.540 TYP

09/28/01
TITLE DRAWING NO. REV.
2325 Orchard Parkway
28P3, 28-lead (0.300"/7.62 mm Wide) Plastic Dual 28P3 B
R San Jose, CA 95131 Inline Package (PDIP)

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 ATmega48PA/88PA/168PA/328P

34. Errata

34.1 Errata ATmega48PA

The revision letter in this section refers to the revision of the ATmega48PA device.

34.1.1 Rev. D
No known errata.

34.2 Errata ATmega88PA

The revision letter in this section refers to the revision of the ATmega88PA device.

34.2.1 Rev. F
No known errata.

34.3 Errata ATmega168PA

The revision letter in this section refers to the revision of the ATmega168PA device.

34.3.1 Rev E
No known errata.

34.4 Errata ATmega328P

The revision letter in this section refers to the revision of the ATmega328P device.

34.4.1 Rev D
No known errata.

34.4.2 Rev C
Not sampled.

34.4.3 Rev B
• Unstable 32 kHz Oscillator

1. Unstable 32 kHz Oscillator

The 32 kHz oscillator does not work as system clock.
The 32 kHz oscillator used as asynchronous timer is inaccurate.
Problem Fix/ Workaround
None

34.4.4 Rev A
• Unstable 32 kHz Oscillator

1. Unstable 32 kHz Oscillator

The 32 kHz oscillator does not work as system clock.
The 32 kHz oscillator used as asynchronous timer is inaccurate.
Problem Fix/ Workaround
None

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 ATmega48PA/88PA/168PA/328P

35. Datasheet Revision History

Please note that the referring page numbers in this section are referred to this document. The
referring revision in this section are referring to the document revision.

35.1 Rev. 8161D – 10/09

1. Inserted Table on page 32, Capacitance for Low-frequency Oscillator.

35.2 Rev. 8161C – 05/09

1. Updated ”Features” on page 1 for ATmega48PA/88PA/168PA/328P.

2. Updated ”Overview” on page 5 included the Table 2-1 on page 6.
3. Updated ”AVR Memories” on page 16 included ”Register Description” on page 21 and inserted
Figure 7-1 on page 17.
4. Updated ”Register Description” on page 44.
5. Updated ”System Control and Reset” on page 46.
6. Updated ”Interrupts” on page 57.
7. Updated ”External Interrupts” on page 70.
8. Updated ”Boot Loader Support – Read-While-Write Self-Programming, ATmega88PA,
ATmega168PA and ATmega328P” on page 277.
9. Inserted ”ATmega168PA DC Characteristics” on page 315.
10. Inserted ”ATmega328P DC Characteristics” on page 316.
11. Inserted ”ATmega168PA Typical Characteristics” on page 375.
12. Inserted ”ATmega328P Typical Characteristics” on page 399.
13. Inserted Ordering Information for ”ATmega168PA” on page 432.
14. Inserted Ordering Information for ”ATmega328P” on page 433.
15. Inserted ”Errata ATmega328P” on page 438.
16. Editing updates.

35.3 Rev. 8161B – 01/09

1. Updated ”Features” on page 1 for ATmega48PA and updated the book accordingly.
2. Updated ”Overview” on page 5 included the Table 2-1 on page 6.
3. Updated ”AVR Memories” on page 16 included ”Register Description” on page 21 and inserted
Figure 7-1 on page 17.
4. Updated ”Register Description” on page 44.
5. Updated ”System Control and Reset” on page 46.

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6. Updated ”Interrupts” on page 57.

7. Updated ”External Interrupts” on page 70.
8. Inserted Typical characteristics for ”ATmega48PA Typical Characteristics” on page 327.
9. Updated figure names in Typical characteristics for ”ATmega88PA Typical Character-
istics” on page 351.
10. Inserted ”ATmega48PA DC Characteristics” on page 314.
11. Updated Table 28-1 on page 317 by removing the footnote from Vcc/User calibration
12. Updated Table 28-7 on page 323 by removing Max value (2.5 LSB) from Absolute
accuracy, VREF = 4V, VCC = 4V, ADC clock = 200 kHz.
13. Inserted Ordering Information for ”ATmega48PA” on page 430.

35.4 Rev. 8161A – 11/08

1. Initial revision (Based on the ATmega48P/88P/168P/328P datasheet 8025F-AVR-08/08).

2. Changes done compared to ATmega48P/88P/168P/328P datasheet 8025F-AVR-08/08:
– Updated ”DC Characteristics” on page 313 with new typical values for ICC.
– Updated ”Speed Grades” on page 316.
– New graphics in ”Typical Characteristics” on page 326.
– New ”Ordering Information” on page 430.

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 ATmega48PA/88PA/168PA/328P

Table of Contents
Features ..................................................................................................... 1

1 Pin Configurations ................................................................................... 2

1.1Pin Descriptions ........................................................................................................3

2 Overview ................................................................................................... 5
2.1Block Diagram ...........................................................................................................5
2.2Comparison Between ATmega48PA, ATmega88PA, ATmega168PA and
ATmega328P 6

3 Resources ................................................................................................. 7

4 Data Retention .......................................................................................... 7

5 About Code Examples ............................................................................. 7

6 AVR CPU Core .......................................................................................... 8

6.1Overview ...................................................................................................................8
6.2ALU – Arithmetic Logic Unit ......................................................................................9
6.3Status Register ..........................................................................................................9
6.4General Purpose Register File ................................................................................11
6.5Stack Pointer ...........................................................................................................12
6.6Instruction Execution Timing ...................................................................................13
6.7Reset and Interrupt Handling ..................................................................................14

7 AVR Memories ........................................................................................ 16

7.1Overview .................................................................................................................16
7.2In-System Reprogrammable Flash Program Memory .............................................16
7.3SRAM Data Memory ...............................................................................................18
7.4EEPROM Data Memory ..........................................................................................19
7.5I/O Memory ..............................................................................................................20
7.6Register Description ................................................................................................21

8 System Clock and Clock Options ......................................................... 26

8.1Clock Systems and their Distribution .......................................................................26
8.2Clock Sources .........................................................................................................27
8.3Low Power Crystal Oscillator ...................................................................................28
8.4Full Swing Crystal Oscillator ....................................................................................30
8.5Low Frequency Crystal Oscillator ............................................................................32
8.6Calibrated Internal RC Oscillator .............................................................................33

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 ATmega48PA/88PA/168PA/328P

8.7128 kHz Internal Oscillator ......................................................................................34

8.8External Clock .........................................................................................................34
8.9Clock Output Buffer .................................................................................................35
8.10Timer/Counter Oscillator .......................................................................................35
8.11System Clock Prescaler ........................................................................................35
8.12Register Description ..............................................................................................37

9 Power Management and Sleep Modes ................................................. 39

9.1Sleep Modes ...........................................................................................................39
9.2BOD Disable ............................................................................................................40
9.3Idle Mode .................................................................................................................40
9.4ADC Noise Reduction Mode ...................................................................................40
9.5Power-down Mode ..................................................................................................41
9.6Power-save Mode ...................................................................................................41
9.7Standby Mode .........................................................................................................41
9.8Extended Standby Mode .........................................................................................41
9.9Power Reduction Register .......................................................................................42
9.10Minimizing Power Consumption ............................................................................42
9.11Register Description ..............................................................................................44

10 System Control and Reset .................................................................... 46

10.1Resetting the AVR .................................................................................................46
10.2Reset Sources .......................................................................................................46
10.3Power-on Reset .....................................................................................................47
10.4External Reset .......................................................................................................48
10.5Brown-out Detection ..............................................................................................48
10.6Watchdog System Reset .......................................................................................49
10.7Internal Voltage Reference ....................................................................................49
10.8Watchdog Timer ....................................................................................................50
10.9Register Description ..............................................................................................54

11 Interrupts ................................................................................................ 57
11.1Interrupt Vectors in ATmega48PA .........................................................................57
11.2Interrupt Vectors in ATmega88PA .........................................................................59
11.3Interrupt Vectors in ATmega168PA .......................................................................62
11.4Interrupt Vectors in ATmega328P .........................................................................65
11.5Register Description ..............................................................................................68

12 External Interrupts ................................................................................. 70

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 ATmega48PA/88PA/168PA/328P

12.1Pin Change Interrupt Timing .................................................................................70

12.2Register Description ..............................................................................................71

13 I/O-Ports .................................................................................................. 75
13.1Overview ...............................................................................................................75
13.2Ports as General Digital I/O ...................................................................................76
13.3Alternate Port Functions ........................................................................................80
13.4Register Description ..............................................................................................92

14 8-bit Timer/Counter0 with PWM ............................................................ 94

14.1Features ................................................................................................................94
14.2Overview ...............................................................................................................94
14.3Timer/Counter Clock Sources ...............................................................................96
14.4Counter Unit ..........................................................................................................96
14.5Output Compare Unit ............................................................................................97
14.6Compare Match Output Unit ..................................................................................98
14.7Modes of Operation ...............................................................................................99
14.8Timer/Counter Timing Diagrams .........................................................................104
14.9Register Description ............................................................................................106

15 16-bit Timer/Counter1 with PWM ........................................................ 113

15.1Features ..............................................................................................................113
15.2Overview .............................................................................................................113
15.3Accessing 16-bit Registers ..................................................................................115
15.4Timer/Counter Clock Sources .............................................................................118
15.5Counter Unit ........................................................................................................119
15.6Input Capture Unit ...............................................................................................120
15.7Output Compare Units .........................................................................................122
15.8Compare Match Output Unit ................................................................................124
15.9Modes of Operation .............................................................................................125
15.10Timer/Counter Timing Diagrams .......................................................................132
15.11Register Description ..........................................................................................134

16 Timer/Counter0 and Timer/Counter1 Prescalers .............................. 141

16.1Internal Clock Source ..........................................................................................141
16.2Prescaler Reset ...................................................................................................141
16.3External Clock Source .........................................................................................141
16.4Register Description ............................................................................................143

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 ATmega48PA/88PA/168PA/328P

17 8-bit Timer/Counter2 with PWM and Asynchronous Operation ...... 144

17.1Features ..............................................................................................................144
17.2Overview .............................................................................................................144
17.3Timer/Counter Clock Sources .............................................................................145
17.4Counter Unit ........................................................................................................145
17.5Output Compare Unit ..........................................................................................146
17.6Compare Match Output Unit ................................................................................148
17.7Modes of Operation .............................................................................................149
17.8Timer/Counter Timing Diagrams .........................................................................153
17.9Asynchronous Operation of Timer/Counter2 .......................................................155
17.10Timer/Counter Prescaler ...................................................................................156
17.11Register Description ..........................................................................................158

18 SPI – Serial Peripheral Interface ......................................................... 166

18.1Features ..............................................................................................................166
18.2Overview .............................................................................................................166
18.3SS Pin Functionality ............................................................................................171
18.4Data Modes .........................................................................................................171
18.5Register Description ............................................................................................173

19 USART0 ................................................................................................. 176

19.1Features ..............................................................................................................176
19.2Overview .............................................................................................................176
19.3Clock Generation .................................................................................................177
19.4Frame Formats ....................................................................................................180
19.5USART Initialization ............................................................................................182
19.6Data Transmission – The USART Transmitter ....................................................183
19.7Data Reception – The USART Receiver .............................................................186
19.8Asynchronous Data Reception ............................................................................190
19.9Multi-processor Communication Mode ................................................................193
19.10Register Description ..........................................................................................195
19.11Examples of Baud Rate Setting ........................................................................199

20 USART in SPI Mode ............................................................................. 204

20.1Features ..............................................................................................................204
20.2Overview .............................................................................................................204
20.3Clock Generation .................................................................................................204
20.4SPI Data Modes and Timing ...............................................................................205

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20.5Frame Formats ....................................................................................................206

20.6Data Transfer ......................................................................................................208
20.7AVR USART MSPIM vs. AVR SPI ......................................................................210
20.8Register Description ............................................................................................211

21 2-wire Serial Interface .......................................................................... 214

21.1Features ..............................................................................................................214
21.22-wire Serial Interface Bus Definition ..................................................................214
21.3Data Transfer and Frame Format ........................................................................216
21.4Multi-master Bus Systems, Arbitration and Synchronization ...............................218
21.5Overview of the TWI Module ...............................................................................221
21.6Using the TWI ......................................................................................................223
21.7Transmission Modes ...........................................................................................227
21.8Multi-master Systems and Arbitration ..................................................................240
21.9Register Description ............................................................................................241

22 Analog Comparator ............................................................................. 246

22.1Overview .............................................................................................................246
22.2Analog Comparator Multiplexed Input .................................................................246
22.3Register Description ............................................................................................247

23 Analog-to-Digital Converter ................................................................ 250

23.1Features ..............................................................................................................250
23.2Overview .............................................................................................................250
23.3Starting a Conversion ..........................................................................................252
23.4Prescaling and Conversion Timing ......................................................................253
23.5Changing Channel or Reference Selection .........................................................255
23.6ADC Noise Canceler ...........................................................................................256
23.7ADC Conversion Result ......................................................................................261
23.8Temperature Measurement .................................................................................261
23.9Register Description ............................................................................................262

24 debugWIRE On-chip Debug System .................................................. 267

24.1Features ..............................................................................................................267
24.2Overview .............................................................................................................267
24.3Physical Interface ................................................................................................267
24.4Software Break Points .........................................................................................268
24.5Limitations of debugWIRE ...................................................................................268
24.6Register Description ............................................................................................268

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 ATmega48PA/88PA/168PA/328P

25 Self-Programming the Flash, ATmega48PA ...................................... 269

25.1Overview .............................................................................................................269
25.2Addressing the Flash During Self-Programming .................................................270
25.3Register Description ............................................................................................275

26 Boot Loader Support – Read-While-Write Self-Programming,

ATmega88PA, ATmega168PA and ATmega328P 277
26.1Features ..............................................................................................................277
26.2Overview .............................................................................................................277
26.3Application and Boot Loader Flash Sections .......................................................277
26.4Read-While-Write and No Read-While-Write Flash Sections ..............................278
26.5Boot Loader Lock Bits .........................................................................................280
26.6Entering the Boot Loader Program ......................................................................281
26.7Addressing the Flash During Self-Programming .................................................282
26.8Self-Programming the Flash ................................................................................282
26.9Register Description ............................................................................................292

27 Memory Programming ......................................................................... 294

27.1Program And Data Memory Lock Bits .................................................................294
27.2Fuse Bits .............................................................................................................295
27.3Signature Bytes ...................................................................................................298
27.4Calibration Byte ...................................................................................................298
27.5Page Size ............................................................................................................299
27.6Parallel Programming Parameters, Pin Mapping, and Commands .....................299
27.7Parallel Programming ..........................................................................................301
27.8Serial Downloading .............................................................................................308

28 Electrical Characteristics .................................................................... 313

28.1Absolute Maximum Ratings* ...............................................................................313
28.2DC Characteristics ..............................................................................................313
28.3Speed Grades .....................................................................................................316
28.4Clock Characteristics ...........................................................................................317
28.5System and Reset Characteristics ......................................................................318
28.6SPI Timing Characteristics ..................................................................................319
28.72-wire Serial Interface Characteristics .................................................................321
28.8ADC Characteristics ............................................................................................323
28.9Parallel Programming Characteristics .................................................................324

29 Typical Characteristics ........................................................................ 326

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 ATmega48PA/88PA/168PA/328P

29.1ATmega48PA Typical Characteristics .................................................................327

29.2ATmega88PA Typical Characteristics .................................................................351
29.3ATmega168PA Typical Characteristics ...............................................................375
29.4ATmega328P Typical Characteristics .................................................................399

30 Register Summary ............................................................................... 423

31 Instruction Set Summary .................................................................... 427

32 Ordering Information ........................................................................... 430

32.1ATmega48PA ......................................................................................................430
32.2ATmega88PA ......................................................................................................431
32.3ATmega168PA ....................................................................................................432
32.4ATmega328P ......................................................................................................433

33 Packaging Information ........................................................................ 434

33.132A ......................................................................................................................434
33.228M1 ...................................................................................................................435
33.332M1-A ................................................................................................................436
33.428P3 ....................................................................................................................437

34 Errata ..................................................................................................... 438

34.1Errata ATmega48PA ...........................................................................................438
34.2Errata ATmega88PA ...........................................................................................438
34.3Errata ATmega168PA .........................................................................................438
34.4Errata ATmega328P ............................................................................................438

35 Datasheet Revision History ................................................................ 439

35.1Rev. 8161D – 10/09 ............................................................................................439
35.2Rev. 8161C – 05/09 ............................................................................................439
35.3Rev. 8161B – 01/09 .............................................................................................439
35.4Rev. 8161A – 11/08 .............................................................................................440

Table of Contents....................................................................................... i

vii
8161D–AVR–10/09
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8161D–AVR–10/09