IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 54, NO.

2, FEBRUARY 2019 441

A 78.5-dB SNDR Radiation- and Metastability-

Tolerant Two-Step Split SAR ADC Operating
Up to 75 MS/s With 24.9-mW Power
Consumption in 65-nm CMOS
Hongda Xu , Student Member, IEEE, Hai Huang , Yongda Cai, Ling Du, Yuan Zhou, Student Member, IEEE,
Benwei Xu , Student Member, IEEE, Datao Gong, Jingbo Ye, and Yun Chiu, Senior Member, IEEE

Abstract— This paper presents a 14-bit radiation- and

metastability-tolerant two-step split successive-approximation
register (SAR) analog-to-digital converter (ADC) that achieves
a 78.5-dB peak signal-to-noise-and-distortion ratio (SNDR) and
a 103-dB peak spurious-free dynamic range (SFDR) at 35 MS/s.
The prototype operates up to 75 MS/s with less than 25-mW
power consumption. To tolerate errors originating from radia-
tions and/or metastability, multiple redundancy techniques are
implemented hierarchically from the system level to the circuit
level. At the system level, the deployment of the split architecture
plus a few additional error detection techniques not only identify
but also correct the errors, leading to a p to p2 error rate
reduction. These detection techniques include a residue over- and
under (OU)-flow detection using the second-stage digital codes,
an extra bit (EB)-cycle error detection with LSB repeating using a
larger digital-to-analog converter (DAC) capacitor, and a parity
bit (PB) error detection for on-the-fly SAR data latch protec-
tion. Sub-radix-2 DAC and reference voltage scaling also create
circuit-level intra- and inter-stage redundancy, further improving
the robustness of the conversion process. Preamplifier sharing
and offset digital calibration alleviate the offset problem between
the residue amplifier (RA) and the first-stage comparator. Two
reference buffers are implemented on chip with a 1.8-V supply.
Fabricated in a 65-nm CMOS process, the ADC core occupies
an active area of 0.342 mm2 . Fig. 1. Schematic of the ATLAS detector at CERN (top) and its frontend
Index Terms— Analog-to-digital converter (ADC), metastabil- readout module and ADC requirement (bottom).
ity, metastability tolerant, radiation, radiation tolerant, split
successive-approximation register (SAR), two step.

I. I NTRODUCTION
high-energy physics experiments [1]–[3]. As an example,

R ADIATION-TOLERANT electronics are in great

demand in the field of medical, aerospace, and
the evolving ATLAS experiment [4] at the CERN large hadron
collider (LHC) [5] continuously requires a large number
of radiation-tolerant analog-to-digital converters (ADCs) of
Manuscript received May 29, 2018; revised August 10, 2018 and
September 30, 2018; accepted October 25, 2018. Date of publication 12–14 bits, and 40–160 MS/s to be deployed in its data
December 7, 2018; date of current version January 25, 2019. This work was acquisition system for current and future upgrade needs [6].
supported in part by the U.S. ATLAS and in part by the U.S. Department of The upper [7] and lower diagrams in Fig. 1 illustrate
Energy under Grant 258086. This paper was approved by Associate Editor
Piero Malcovati. (Corresponding author: Hai Huang.) the ATLAS detector and its readout frontend architecture
H. Xu, H. Huang, and Y. Chiu are with the Texas Analog Center of for the operation phase starting in mid-2020s with a high-
Excellence, The University of Texas at Dallas, Richardson, TX 75080 USA luminosity upgrade of the LHC. The frontend electronics
(e-mail: [email protected]).
Y. Cai is with Analog Device, Milpitas, CA 95035 USA. will be embedded in the center of the detector surrounding
L. Du is with Chengdu MECS Microelectronics Technology Co., Ltd., the collision point. Due to the large energy range of the
Chengdu 610051, China. incident particles to the detector, the analog frontend needs
Y. Zhou is with Broadcom Inc., Irvine, CA 92618 USA.
B. Xu is with Apple Inc., Cupertino, CA 95014 USA. to accommodate a 17 bit + dynamic range (DR), which
D. Gong and J. Ye are with the Physics Department, Southern Methodist translates into a 12- to 14-bit resolution requirement for the
University, Dallas, TX 75205 USA. ADC [8]. On the speed aspect, the LHC runs at a 40-MHz
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org. frequency (i.e., a particle collision takes place every 25 ns).
Digital Object Identifier 10.1109/JSSC.2018.2879942 To capture the potential valuable physics events during each
0018-9200 © 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

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442 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 54, NO. 2, FEBRUARY 2019

collision, the ADC is required to operate at a minimum

of 40 MS/s to guarantee at least one sample per collision/bunch
crossing (BC) for the backend digital processing. In addition,
the proximity of the front-end board to the collision point
requires the on-board electronics to be resistant to the radiation
effects in this harsh radioactive environment, adding another
level of a design challenge.
Radiation effects can be broadly divided into two cate-
gories [9]–[13]. The “short-term” single-event effect (SEE)
is caused by the ionization effect of the incident particle,
mostly leading to soft errors, such as bit flips or memory Fig. 2. (a) Illustration of the TMR technique in digital designs. (b) Possible
TMR architecture applied to the ADC.
errors [called the single-event upset (SEU)]. While SEUs only
corrupt data, some SEE may lead to system malfunction
and need to be corrected by a system refresh, other SEE
where p is the error rate of a conventional ADC operating in
may even produce fatal circuit failures. The total ionizing
the same irradiation or normal condition.
dose (TID) is a “long-term” cumulative effect, often caused
The rest of this paper is organized as follows. In Section II,
by charges trapped in the oxide and accumulated to a certain
methods and techniques for radiation and metastability error
amount, resulting in device threshold shifts and eventually
detection and correction will be first discussed, followed by
functionality loss. Fortunately, the TID effect is alleviated by
the circuit design details to realize a 14-bit accuracy up to
process scaling [14], [15] and layout practice. In general, as the
75 MS/s in Section III. Experimental results are summarized in
gate oxide shrinks in a finer technology node, the probability
Section IV, including the SEE and TID test results obtained in
of the charge-trapping event reduces. In contrast, the SEE does
a radiation environment. Finally, a brief conclusion is drawn in
not vary significantly with the process. For the successive-
Section V.
approximation register (SAR) ADC, the SEE may cause
large burst conversion errors due to the state flip in data
registers or charge loss/leakage on high-impedance nodes (e.g., II. R ADIATION -/M ETASTABILITY-T OLERANT
the summing node) during the conversion process. Mean- T ECHNIQUES FOR SAR ADC
while, the TID effect may increase the power consumption A radiation- and metastability-tolerant design can be imple-
dramatically after a long time exposure of the device to mented at the architecture level, the circuit level, the device
radiation. level, and/or the layout level. In this paper, methods and
In the rapidly advancing CMOS technology, the low power techniques are mainly devised at the architecture and circuit
supply voltage limits the development of high-gain amplifier- levels for a CMOS SAR ADC.
based ADC architectures, such as the pipelined ADC. On the The triple modular redundancy (TMR) is a widely used
other hand, as the cutoff frequency of the transistor improves, technique in digital designs for radiation-tolerant applica-
SAR ADC becomes a more suitable candidate for high resolu- tions [25]. As depicted in Fig. 2(a), three identical digital
tion (14–20 bits) [16]–[20] and moderate speed (1–100 MHz) blocks process one single input and produce the final output by
designs with high power efficiency. In addition, the nearly majority voting. Similarly, TMR can also be applied to include
all-digital structure of the SAR ADC is also more amenable analog circuitry for protections [26]. As shown in Fig. 2(b),
to existing radiation-tolerant design techniques for digital one ADC is replicated three times to convert the same analog
circuits [9], which are often easier to protect than conventional input signal. The associated error probability can be largely
analog circuits. reduced. However, the chip area and power consumption are
In SAR ADCs, the comparator metastability often produces also tripled, and the area and power overhead are of concern
SEE-like soft errors that greatly degrade its conversion error in lower power and/or multi-channel applications, such as
rate. Benefiting from Moore’s law, the operation speed of SAR the ATLAS frontend readout module, which includes hundred
ADC has improved 5–6 orders of magnitude over the past two thousand channels in a limited region and the stringent require-
decades [21]–[24]; the mean bit-cycle time has dropped to the ment for cooling is of stern concern. Also, the complexity
sub-nanosecond range, which, unfortunately, greatly increases and associated overhead of TMR may degrade the ADC
the metastability rate. Reducing the speed is one obvious solu- input bandwidth. The matching accuracy between the three
tion to mitigate the metastability problem; however, it hurts the sub-ADCs and the skews in clock and signal distributions are
ADC sample rate and bandwidth performance. In this paper, also difficult challenges.
the treatment for SEE errors will also be applied to treating To preserve the architecture-level redundancy while
the metastability errors. mitigating the area and power penalty of the TMR technique,
This paper describes a 14-bit two-step SAR ADC that can the double modular redundancy (DMR) is exploited in this
operate up to 75 MS/s. By adopting a split structure, system- paper, resulting in a split ADC architecture [27] sketched
level redundancy is introduced. At the meantime, incorporating in Fig. 3. The two sub-ADCs, labeled as ADC-A and
a few specifically designed error detection circuits, the split ADC-B process the same analog input simultaneously and
SAR structure can not only identify but also correct errors, independently. In the ideal condition, the two digital outcomes
leading to a substantial error rate reduction from p to p2 , are nearly identical (less the circuit and quantization noises).

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XU et al.: 78.5-dB SNDR RADIATION- AND METASTABILITY-TOLERANT TWO-STEP SPLIT SAR ADC 443

Fig. 3. Prototype radiation-tolerant SAR ADC architecture.

Fig. 5. Illustration of the out-of-range residue detection.

Fig. 4. Illustrations of the embedded error detectors in the two-step SAR

sub-ADC.
Fig. 6. EB cycle in the second SAR stage.

When any one of the two ADCs is subject to a large

conversion error, their results will notably differ. Therefore,
the difference between the two digital codes, denoted as DO
in Fig. 3, can be taken as an indicator of conversion errors.
When this happens, the erroneous result is discarded, and the
correct one is retained; otherwise, if both are correct, the two
results will be averaged, and a 3-dB SNR improvement can be
obtained for that sample. If the error is rare, one can reduce Fig. 7. Principle of the EB-cycle detection for the second stage.
the size of each sub-ADC by half relative to a single-channel
counterpart of the same SNR, thus minimizing the area/power
overhead of the approach. SAR will resolve to an all-1 or all-0 code. By observing
To identify the erroneous sub-ADC when DO is large, this OU-flow digital code, the erroneous sub-ADC can be
several detection circuits are designed to monitor the internal identified.
nodes of each sub-ADC and to control the MUX to output
the correct digital codes via some simple digital logics. B. Extra Bit-Cycle Error Detection
In addition, with the injection of a pseudorandom binary For the second SAR stage, an EB-cycle detection method
sequence (PRBS) in the digital-to-analog converter (DAC), is devised to monitor its residue. Fig. 6 depicts a simplified
the transfer curves of the two sub-ADCs slightly differ from DAC of the second stage. One extra capacitor Cdet is attached
each other in the split structure to enable a digital bit-weight to the summing node for an EB cycle [28]–[30], similar to a
calibration [22]. one-step LSB repeating. Note that the value of Cdet is several
In each sub-ADC, a two-step pipelined SAR structure is times larger than that of the LSB capacitor.
employed as shown in Fig. 4. Three types of detection circuits Fig. 7 illustrates the principle of this technique. Toward
are deployed for the first- and second-stage error detections, the LSB cycle, the summing-node differential voltage should
including the residue over- and under (OU)-flow detection, approach zero in the normal condition. Given this nature,
the extra bit (EB)-cycle detection, and the parity bit (PB) the LSB repeating cycle with the switching of the large
detection for SAR data latches. The details are given as capacitor Cdet should always produce an opposite bit decision
follows. relative to the LSB decision, as displayed in Fig. 7 (left).
In practice, even when electronic noise is considered, this is
A. Over- and Under-Flow Error Detection always the case. As shown in the middle of Fig. 7, suppose
In this circuit, we simply monitor the second-stage SAR that the ideal LSB decision is 1. However, due to noise, the
output digital codes. Because of the 2-bit redundancy allocated actual decision is 0. Then, according to the actual decision,
between the first and second stages, the residue voltage will the summing-node voltage will switch to a much more positive
be bounded within one-fourth of the second-stage full range in value, resulting in a “1” decision, which is still opposite to
the normal condition as indicated by the lower curve in Fig. 5. the LSB decision. The opposite case can be argued similarly.
If the residue voltage exceeds the full range due to SEE or any In any case, as long as the summing-node residue voltage is
other reason as shown by the upper curve, the second-stage close to 0 after the LSB decision, the extra DAC capacitor Cdet

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444 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 54, NO. 2, FEBRUARY 2019

Fig. 9. Data latch error detection.

Fig. 8. Potential error in data latches and its consequence.

will always drive the summing-node voltage to depart the zero

value in the opposite direction relative to the LSB decision,
thus producing an opposite bit decision than the LSB. This is
true when Cdet is sufficiently large.
Now, suppose that a striking particle disturbs the conversion
process somewhere before the LSB cycle, and the summing-
node voltage is far away from zero; then, the EB cycle tends to
yield an identical decision as the LSB, provided that the error
charge resulting from the disturbance is larger than that due to
the switching of Cdet . In contrast, when the radiation-induced
error is small and within the detection range set by Cdet ,
the error will be simply treated as noise.
The above-mentioned argument leads to the question of how Fig. 10. (a) Schematic and (b) timing of the two-stage pipelined SAR.
to choose the right value for Cdet . If a small Cdet is selected, for
example, of 1 or 2 LSBs, circuit noise may produce many false To treat this case, a PB is added as depicted in Fig. 9. The
alarms. On the contrary, if a large Cdet (e.g., of 10–20 LSBs) is PB circuit trailing the comparator counts the number of 1’s
selected, small radiation-induced errors will be missed. Thus, when the comparator gives a decision. The logic expression
a sensible strategy is to choose a small capacitor right above for this operation is
the noise level with some margin. In this paper, we choose a Di = Di−1 ⊕ bi (1)
capacitor six times of the LSB capacitor for this task.
where Di is the parity of the leading i bits and bi is the i th bit
of the comparator output. D0 is always 0, and i ranges from
C. Parity Bit Error Detection 1 to 10 for the first stage and from 1 to 8 for the second stage.
In this paper, TMR is used to protect most digital circuits By the end of all bit cycles, a final PB is produced and
except the data latches in the SAR loop due to the speed stored. By comparing the stored PB and the actual output data
consideration as all data latches present loading to the com- parity, one can verify whether there is a bit flip after the digital
parator. If the number of latches is tripled, the SAR loop will bits are stored in the data latches (or during the transmission
be significantly impeded as illustrated in Fig. 8 (left). to off chip). It is worth to mention that in case the PB itself is
However, left untreated, SEE may randomly flip the bit flipped by the radiation effect, the final data output may still
values stored in these latches and potentially produce gross be intact as the detection logic will always examine DO first.
conversion errors. In practice, if the summing-node voltage is When DO is close to 0, the two sub-ADCs’ results are simply
upset by a bit flip in these latches, the residue voltage will averaged and sent to off chip.
likely saturate the second stage as shown by the uppermost
III. P ROTOTYPE SAR ADC D ESIGN
curve in Fig. 8 (right). Then, by observing the second-stage
digital code (i.e., via the OU-flow detectors), such an error The various error detection techniques described in
can still be detected. However, depending on the extent of the Section II place the critical internal nodes of the sub-ADCs
upset, the following case can also occur. When one data latch under surveillance. The error rate of the ADC can, thus,
is disturbed toward the end of the residue amplification (RA) be greatly reduced. In this section, the circuit details of the
phase, as shown by the red curve in Fig. 8, the residue may SAR ADC design will be discussed.
still be within the redundancy range when the second-stage
DAC samples and the second-stage resolving process may still A. Architecture
converge. However, the final digital output is far away from Fig. 10(a) draws the block diagram of the two-step pipelined
its correct value. SAR sub-ADC [31]–[33]. It is known that the speed bottleneck

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XU et al.: 78.5-dB SNDR RADIATION- AND METASTABILITY-TOLERANT TWO-STEP SPLIT SAR ADC 445

Fig. 11. Inter- and intra-stage redundancies.

Fig. 13. Effect of an offset between the comparator and RA.

achieving an over 60-dB open-loop gain. The first two stages

utilize a simple five-transistor structure, and the third stage
adopts a cascode PMOS load to boost the gain. Compared to
the conventional design of a multi-stage amplifier in which the
Fig. 12. Schematic of the three-stage RA. dominant pole is in the first stage, in this design, the dominant
pole resides in the last stage. With a large second-stage
of a two-step SAR is usually in the first stage, because it needs capacitive DAC to drive and a small feedback factor of 1/16,
to complete three operations of sampling, bit cycles, and RA, the closed-loop response of the amplifier is stable, obviating
whereas the second stage only needs to finish the first two any frequency compensation. In the simulation, the RA’s
operations within the same time as sketched in Fig. 10(b). phase margin is 61° in the TT corner. The low-gain, high-
Therefore, in a balanced timing scheme, more bits should bandwidth first gain stage is also reused as the preamplifier
be allocated to the second stage. However, a low-resolution for the first-stage comparator. Although this choice results in
first stage implies that the RA needs to maintain a relatively somewhat larger noise from the wideband first stage, it much
high linearity, i.e., an amplifier with high open-loop gain alleviates the offset problem between the RA and the first-
is required. In this paper, considering the tradeoffs between stage comparator (see Section III-C).
speed, linearity, design complexity, and power consumption, The comparator in the first stage consists of a preamplifier
a 9b + 5b architecture is chosen and implemented. More bits and a dynamic latch. The preamplifier (reused from the
are allocated to the first stage to relax the design requirements first-stage RA) is a single-stage amplifier providing a gain of
of the RA, whose 16× closed-loop gain also alleviates the around 18 dB to relax the noise and offset requirements of
noise requirement for the second stage considerably. the trailing latch. The strong-arm dynamic latch [35] is used
In the actual design, the first stage resolves 10 bits, and in this comparator for its fast regeneration speed.
the second resolves 8 bits. The total 18-bit raw code includes
4-bit redundancy. Out of which, one-bit redundancy is C. RA-Comparator Offset Removal
embedded in each stage for dynamic error tolerance, realized
by a sub-binary weighted [34] capacitor array in the DAC The offset between the first-stage comparator and the RA
as illustrated in Fig. 11 (left); 2-bit inter-stage redundancy is is an issue in the pipelined structure and needs to be carefully
allocated to the residue transfer process, realized by scaling the considered. For example, with a 1.2-V reference voltage and
second-stage reference voltage as depicted in Fig. 11 (right). the 9b + 7b configuration, the full-scale range of the second
As shown in Fig. 11 (right), after nine effective bits are stage is 150 mV and, with 2-bit inter-stage redundancy, the
resolved in the first stage, a residue gain of 512 is ideally residue should be bounded within ±VFS /4 in the ideal case,
required for the second stage to resolve the remaining 5 bits as shown by the lower curve in Fig. 13. If the residue goes
using the same reference voltage. Such a high closed-loop beyond 3VFS /4 as shown by the upper curve, the second stage
gain usually translates into high design complexity, high will be saturated. Since the inter-stage gain is 16×, it can be
power, and/or area consumptions. To alleviate this problem, calculated that the max allowable offset between the first-stage
a three-stage RA with a 16× closed-loop gain is employed in comparator and the RA is 7 mV, which is too small to only
this paper. Accordingly, the second-stage reference needs to be rely on a careful layout to achieve.
downscaled by 32× to maintain an overall 14-bit resolution. Therefore, a preamp sharing scheme is devised and imple-
In the actual design, the second-stage reference is downscaled mented as sketched in Fig. 10(a). The RA is a three-stage
by 8×, leaving 7 bits for the second stage to resolve, fully differential amplifier with its first stage reused as the
incorporating 2-bit redundancy for inter-stage error tolerance. preamplifier for the comparator. As a result, the dominant part
of the offset is removed. Any residual offset from the second
and third stages of the RA relative to the comparator will be
B. Residue Amplifier and First-Stage Comparator divided by the first-stage gain when input referred.
With a 1.2-V supply voltage, an amplifier with three To treat the residual offset, a small unit-element DAC is
cascaded gain stages is implemented as shown in Fig. 12, attached to the first-stage summing nodes. As discussed earlier,

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446 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 54, NO. 2, FEBRUARY 2019

Fig. 14. Residual RA-comparator offset calibration.

the residue voltage should be confined within ±VFS /4 in

Fig. 15. Schematic of the on-chip reference buffer.
the ideal case and if it goes beyond ±3VFS /4, an over-
flow or underflow signal is triggered. Thus, by monitoring the
first two bits of the second stage, namely, D11 and D12, externally, the parasitic inductance from the bonding wire
these two cases can be identified. When this occurs, some and printed circuit board (PCB) trace can introduce reference
charge will be injected onto the summing nodes through the ringing that impedes the DAC settling.
calibration DAC to compensate the offset as shown in Fig. 14. One common solution to this is to use on-chip bypass
Once the process converges, an offset-free residue transfer capacitors to stabilize the reference voltage, leading to large
process results. area consumptions [37]. To improve the area efficiency,
an on-chip reference buffer is included in this design,
D. Calibration for DAC Mismatch and RA Gain Errors as shown in Fig. 15, to deliver the reference voltage with a
The split ADC not only provides architectural redundancy fast response. It adopts a master–slave structure. The output
for SEE tolerance but also enables the digital calibration reference voltage is 1.2 V, so a 1.8-V power supply is
for DAC capacitor mismatch [36]. As shown in Fig. 3, employed to ensure a non-zero VDS of the output transistor
the difference between the two digital outcomes DO can (all transistors in this block are 1.8-V devices). The error
be used as an error signal to direct the adaptation of bit amplifier uses a two-stage structure. The first stage employs a
weights [22], [37]. A least mean square (LMS) algorithm used diode load, and the second stage uses a cascode current mirror
to update the bit weights are given as as a load. As the second stage also drives multiple large output
stages plus a bypass capacitor, the dominant pole of this
WA,i (n + 1) = WA,i (n) − μ × DO × DA,i amplifier is in the second stage, and the closed-loop response
WB,i (n + 1) = WB,i (n) + μ × DO × DB,i (2) is stable. The output stage is actually the third stage, but the
“master” output is not connected to the DAC. The two replica
where WA,i /WB,i and DA,i /DB,i are the bit weight and the “slave” outputs are connected to the first-stage and the second-
bit value of the i th bit for ADC-A and ADC-B, respectively, stage DACs, respectively. As they are out of the feedback loop
μ is a constant that sets the convergence speed, and n is the of the reference buffer, they do not affect the loop stability.
iteration number. Once the weights are correctly identified for
both sub-ADCs, the two calibrated outcomes dA and dB must IV. E XPERIMENTAL R ESULTS
be identical, leading to a zero DO (in the statistical sense), The prototype was fabricated in a 65-nm CMOS process.
and the update halts.
The core size is 600 μm × 570 μm (0.342 mm2 ). As shown
The transfer curves of the two conversion paths must be
in Fig. 16, the clock generation circuits and reference buffers
different from each other to rule out the scenario wherein the are placed in the center, and the two sub-ADCs are laid out
two ADCs commit errors in the same way and D O is still 0.
symmetrically on the two sides. The experimental results are
This is realized by injecting a dynamic offset to the summing organized and presented in two parts for the normal electronic
node through a small capacitor CCAL . The two transfer curves measurement and the irradiation test as follows.
are offset in opposite directions near the bit transition points.
A. Electronic Measurement Results
E. Reference Buffer Fig. 17 shows the differential nonlinearity (DNL) and inte-
During each bit cycle, the capacitive DAC draws dynamic gral nonlinearity (INL) plots at 35 MS/s with a low-frequency
current from the reference voltage to proceed with its charge sine-wave input. The DNL is within ±0.42 LSBs, and the
redistribution process. With a non-zero source impedance, the INL is within ±0.56 LSBs at the 14-bit level, indicating
on-chip reference voltage received by the DAC will first droop an excellent static linearity of the prototype after bit-weight
and then settle back. If the reference voltage is supplied calibration.

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XU et al.: 78.5-dB SNDR RADIATION- AND METASTABILITY-TOLERANT TWO-STEP SPLIT SAR ADC 447

Fig. 16. Die photograph. Fig. 19. Measured sub-ADC output spectra ( f s = 35 MHz and f in =
5 MHz).

Fig. 17. Measured DNL and INL.

Fig. 20. Measured ADC output spectrum near Nyquist ( f s = 75 MHz and
f in = 40 MHz).

Fig. 18. Measured ADC output Spectra (left: f s = 35 MHz, right:

f s = 40 MHz, f in = 5 MHz in both).
Fig. 21. Measured ADC dynamic performance.

Fig. 18 sketches the measured fast Fourier transform (FFT)

spectra at 35 and 40 MS/s for a 5-MHz sine-wave input. the prototype measures a >75-dB SNDR and a >90-dB
It demonstrates a 78.5-dB peak signal-to-noise-and-distortion SFDR up to the Nyquist frequency. At 75 MS/s, it measures
ratio (SNDR) and a 103-dB peak spurious-free dynamic range a >70-dB SNDR and a >88-dB SFDR up to the Nyquist.
(SFDR) after calibration at 35 MS/s. The results are obtained The power consumption of the ADC is displayed in Fig. 22.
by averaging the two sub-ADC outputs, and the same proce- It varies linearly from 22.2 to 24.9 mW from 40 to 75 MS/s.
dure is followed for the remaining results in this section if not As the power breakdown (at 40 MS/s) chart shows, most of
otherwise stated. At 40 MS/s, the prototype achieves a 78-dB the power is consumed by the RAs and the reference buffers,
peak SNDR and a 95-dB peak SFDR after calibration (this while the digital circuits only consume 14% of the total power
sample rate is used in the ATLAS experiment). Fig. 19 shows in spite of the TMR technique applied. This explains the
the two sub-ADC output spectra at 35 MS/s for a 5-MHz input. merely 2.7-mW (∼12%) power increase when the sample rate
Compared to Fig. 18 (left), there is a ∼3-dB SNR gain for the is nearly doubled from 40 to 75 MS/s.
averaged output. Fig. 20 displays the spectrum at 75 MS/s
with a near-Nyquist input. B. Irradiation Test Results
Fig. 21 summarizes the ADC’s dynamic performance at The irradiation tests were performed separately in two parts.
35, 40, and 75 MS/s. The amplitude of the input signal One is the SEE test with a high-energy proton beam, and the
varies between −0.5 and −2.0 dBFS. At 35 and 40 MS/s, other is the TID test with an X-ray source.

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448 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 54, NO. 2, FEBRUARY 2019

Fig. 22. Power consumption and breakdown.

Fig. 24. Mapping of the ADC error rate to the “time domain.”

TABLE I
R ADIATION D OSE

Fig. 25. ADC error rate versus the error threshold.

probability of both sub-ADCs being erroneous ( p2 ) is signifi-

cantly lower than either one being wrong (2 p). Fig. 23 (right)
shows the final results after the EB cycle, and the PB detec-
tions are applied. To plot the results in Fig. 23 (right) using
the same scale, the erroneous results are identified and set to
Fig. 23. Error plot of ADC-A and ADC-B (left) before and (right) after
equal to the correct one. Therefore, the blue squares all lie on
correction. the diagonal line. It can be concluded that all conversion errors
are successfully detected and after correction the error spread
is within ±4 LSBs, yielding a 100% large error correction rate
1) SEE Test Results: In the SEE test, a high-energy proton in this experiment.
beam is aligned to the center of the chip. The beam has Another test was conducted with the same setup but without
a spread of a normal distribution with a σ of ∼5.0 mm. radiation. Under this condition, most of the errors are produced
As the die size is only 1.5 mm × 1.0 mm, it is completely by metastability. The ADC was set to run for about 9 h
covered by the beam. Table I lists the radiation plan, the actual at 50 MS/s with a phase-locked 10-MHz sine-wave input,
dose, and the dose rate of the experiment. The goal is to and the experiment was repeated at 25 MS/s with a 5-MHz
reach a total fluence of 3.8 × 1012 protons/cm2, which is the sine-wave input. All errors were recorded and counted. After
ATLAS liquid argon (LAr) calorimeter specification [38]. The performing the error detection and correction, all errors are
experiment was divided into three separate runs to start with again successfully corrected for both sample rates, leading to
a low dose rate, which is the flux shown in the third column a <10−12 error rate in both cases (limited by the observation
of Table I. After the three runs, the chip received a total of time).
5.05 × 1012 protons/cm2 fluence. The proton energy is Theoretically, the error rate after the correction is lowered
120 MeV. to p 2 if the raw error rate of each sub-ADC is p. Fig. 24 plots
Fig. 23 shows the error records before and after correction this p– p 2 relationship and interprets it in “time,” which is the
when the beam is ON. The x- and y-axes, labeled with mean time to observe one error. The upper and lower lines
DOA and DOB , represent the error of the ADC-A and correspond to the error rate–time relationship for the 25- and
ADC-B, respectively. It can be observed from Fig. 23 (left) 50-MS/s sample rates, respectively. The two stars represent
that all large errors are located along the x- or y-axes, indi- the raw error rates before correction, which is p, and the
cating that the large conversion errors of the two sub-ADCs two squares represent the error rates after correction, which
are uncorrelated, i.e., one conversion output is always correct is p2 . From Fig. 24, it is clear that due to the observation time
when the other is erroneous. This behavior is as expected—the limit (∼9 h), we did not see one single error after correction.

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XU et al.: 78.5-dB SNDR RADIATION- AND METASTABILITY-TOLERANT TWO-STEP SPLIT SAR ADC 449

TABLE II
S UMMARY AND C OMPARISONS

two on-chip reference buffers. It also achieves the highest

Schreier figure of merit (FoM) and the best Walden FoM
among these works.
V. C ONCLUSION
A low-power 14-bit radiation-tolerant ADC is reported.
Measurement results demonstrate that the split SAR structure
with built-in SEE detection circuits not only provides
architecture- and circuit-level redundancy for radiation
tolerance but also reduces the ADC metastability errors.
The prototype measures a 78.5-dB peak SNDR and an over
Fig. 26. SNDR, SFDR (left), and power consumption (right) variations versus 100-dB peak SFDR with less than 25-mW power. It also
the dose. reports a 100% correction rate for SEE and metastability
errors in our experiments.
The mean time to observe one error is 7 years at 50 MS/s and
35 million years at 25 MS/s, indicating a very high reliability ACKNOWLEDGMENT
of the prototype incorporating all radiation-tolerant design The authors would like to thank SRC for the TxACE
techniques. silicon fabrication program, Mentor Graphics for providing
Fig. 25 shows the raw error rate versus the error threshold the AFS simulator, and Dr. M. Newcomer from the University
of DO . It can be seen that the curve is nearly flat, revealing of Pennsylvania, Philadelphia, PA, USA, for his kind help in
a weak dependence of the error rate on the threshold. irradiation testing.
2) TID Test Results: In the TID test, the prototype was
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SNDR over 1 kHz BW in 55 nm CMOS,” in IEEE ISSCC Dig. Tech.
Papers, Feb. 2016, pp. 458–459. Hongda Xu (S’14) received the B.E. degree
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MS/s SAR ADC with 100.2 dB dynamic range,” in Symp. VLSI Circuits sity, Nanjing, China, in 2010, and the M.S. and
Dig. Tech. Papers, Jun. 2014, pp. 1–2. Ph.D. degrees from The University of Texas at
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ple/s A/D converter capable of 12 b untrimmed linearity,” in IEEE ISSCC respectively.
Dig. Tech. Papers, Feb. 1997, pp. 132–133. His research interests included high resolution,
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CMOS SAR ADC achieving over 90 dB SFDR,” in IEEE ISSCC Dig. (SAR) analog-to-digital converter (ADC) design,
Tech. Papers, Feb. 2010, pp. 380–381. and digital signal processing for high-precision data
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pipelined-SAR ADC with PVT-stabilized dynamic amplifier achieving Dr. Xu was a recipient of the Louis Beecherl, Jr. Graduate Fellowship
<1 dB SNDR variation,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2017, in 2015 and the Analog Devices Outstanding Student Designer Award in 2017.
pp. 472–473.
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ground second-stage common-mode regulation and offset calibration in Hai Huang received the B.S. and M.Sc. degrees in
14 nm CMOS FinFET,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2017, electrical engineering from the University of Elec-
pp. 474–475. tronic Science and Technology of China, Chengdu,
[25] S. Niranjan and J. F. Frenzel, “A comparison of fault-tolerant state China, in 2010 and 2013, respectively, and the Ph.D.
machine architectures for space-borne electronics,” IEEE Trans. Rel., degree from The University of Texas at Dallas,
vol. 45, no. 1, pp. 109–113, Mar. 1996. Richardson, TX, USA, in 2017.
His main research interests include data converters
[26] H. Venkatram, J. Guerber, M. Gande, and U.-K. Moon, “Detection
and emerging low-power amplifiers.
and correction methods for single event effects in analog to digital
Dr. Huang was a recipient of the First Prize of the
converters,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 60, no. 12, National Undergraduate Electronic Design Contest
pp. 3163–3172, Dec. 2013.
in Sichuan section in 2009 and the Analog Devices
[27] J. McNeill, M. Coln, and B. Larivee, “A split-ADC architecture for Outstanding Student Designer Award in 2014.
deterministic digital background calibration of a 16 b 1 MS/s ADC,” in
IEEE ISSCC Dig. Tech. Papers, Feb. 2005, pp. 276–277.
[28] H. Xu et al., “A 78.5 dB-SNDR radiation- and metastability-tolerant Yongda Cai received the B.S. degree from the
two-step split SAR ADC operating up to 75 MS/s with 24.9 mW power Huazhong University of Science and Technology,
consumption in 65 nm CMOS,” in IEEE ISSCC Dig. Tech. Papers, Wuhan, China, in 2013, and the M.S.E.E. degree
Feb. 2017, pp. 476–477. from The University of Texas at Dallas, Richardson,
[29] T. Miki et al., “A 4.2 mW 50 MS/s 13 bit CMOS SAR ADC with TX, USA, in 2017.
SNR and SFDR enhancement techniques,” IEEE J. Solid-State Circuits, From 2014 to 2016, he was a Research Assistant
vol. 50, no. 6, pp. 1372–1381, Jun. 2015. with the TxACE Analog Center of Excellence, The
[30] J. Shen et al., “A 16-bit 16-MS/s SAR ADC with on-chip calibration in University of Texas at Dallas. He is currently a
55-nm CMOS,” in Symp. VLSI Circuits Dig. Tech. Papers, 2017, pp. 1–2. Power IC Design Engineer with Analog Devices,
[31] W. Yang, D. Kelly, L. Mehr, M. T. Sayuk, and L. Singer, “A 3-V Milpitas, CA, USA.
340-mW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR at Nyquist Mr. Cai was a recipient of the China National
input,” IEEE J. Solid-State Circuits, vol. 36, no. 12, pp. 1931–1936, Scholarship in 2012 and the ADI Outstanding Student Designer Award
Dec. 2001. in 2014.

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XU et al.: 78.5-dB SNDR RADIATION- AND METASTABILITY-TOLERANT TWO-STEP SPLIT SAR ADC 451

Ling Du received the Ph.D. degree in microelectron- Jingbo Ye received the B.Sc. degree in physics
ics and solid-state electronics from the University from the University of Science and Technology of
of Electronic Science and Technology of China, China (USTC), Hefei, China, and the Ph.D. degree
Chengdu, China, in 2016. in physics from USTC in conjunction with the Swiss
From 2014 to 2015, he was a Visiting Student Federal Institute of Technology, Zurich, Switzerland,
with The University of Texas at Dallas, Richardson, and the Institute of High Energy Physics, Beijing,
TX, USA. He is currently with Chengdu MECS China.
Microelectronics Technology Co., Ltd, Chengdu. From 1989 to 1995, he mainly worked at CERN,
His current research interests include the design Geneva, Switzerland, and in the L3 collaboration on
of high-speed high-resolution analog-to-digital con- detector simulation, physics data analyses, software
verters (ADCs), especially successive-approximation development, and maintenance. From 1995 to 1998,
register (SAR) ADC, pipelined ADC, and hybrid ADC. he worked in the CLEO Collaboration at the Cornell Electron-Positron Storage
Ring (CESR) on detector development for the CLEO III Upgrade. Since 1998,
he has been a member of the ATLAS collaboration on the Large Hadron
Collider at CERN. He is currently a Physicist in experimental particle physics,
and also a Professor with Southern Methodist University (SMU), Dallas, TX,
Yuan Zhou (S’12) received the B.S. degree in elec- USA. He coordinated the design and construction of the optical link system for
trical engineering from Tsinghua University, Beijing, ATLAS’ Liquid Argon Calorimeter detector front-end readout. He currently
China, in 2009, the M.S. degree from Columbia leads the R&D and Construction Programs at SMU for upgrades in ATLAS
University, New York, NY, USA, in 2011, and the and for next-generation detector data transmission in HEP experiments.
Ph.D. degree from The University of Texas at Dallas,
Richardson, TX, USA, in 2016.
He is currently with Broadcom Ltd, Irvine, CA,
USA. His current research interests include high-
resolution analog-to-digital converters (ADCs) and Yun Chiu (S’97–M’04–SM’10) received the B.S.
digital calibration techniques for data converters. degree in physics from the University of Science and
Technology of China, Hefei, China, the M.S. degree
in electrical engineering from the University of
California at Los Angeles, Los Angeles, CA, USA,
and the Ph.D. degree in electrical engineering and
Benwei Xu (S’13) received the B.S. degree in micro- computer sciences from the University of California
electronics from Shanghai Jiao Tong University, at Berkeley, Berkeley, CA, USA.
Shanghai, China, in 2011, and the Ph.D. degree in From 1997 to 1999, he was a Senior Staff Mem-
electrical engineering with The University of Texas ber with CondorVision Technology Inc., Fremont,
at Dallas, Richardson, TX, USA, in 2017. CA, USA, where he was in charge of develop-
Since 2017, he has been with Apple Inc., ing analog and mixed-mode circuits for CMOS digital imaging products.
Cupertino, CA, USA. His research interests include From 1999 to 2004, he was with the Berkeley Wireless Research Center,
high-speed data converter design and digital calibra- University of California at Berkeley, where he involved in low-power and
tion techniques for data converter. low-voltage CMOS data converters. In 2004, he joined the Department
Dr. Xu was a recipient of the ADI Outstanding of Electrical and Computer Engineering, University of Illinois at Urbana–
Student Designer Award in 2013 and TxACE Out- Champaign, Champaign, IL, USA, as an Assistant Professor, where he
standing Student Supplement in 2011. received the tenure offer in 2010. He is currently a Full Professor and
the Erik Jonsson Distinguished Professor with the Department of Electrical
and Computer Engineering, The University of Texas at Dallas, Richardson,
TX, USA, where he is also the Director of the Analog and Mixed-Signal
Laboratory, Texas Analog Center of Excellence, The University of Texas at
Datao Gong received the B.S., M.S., and Ph.D. Dallas.
degrees in physics from the University of Science Dr. Chiu was a co-recipient of the Jack Kilby Outstanding Student
and Technology of China, Hefei, China, in 1993, Paper Award from the 2004 International Solid-State Circuits Confer-
1996, and 1999, respectively. ence (ISSCC), the Outstanding Evening Session Award from the 2017 ISSCC,
From 2001 to 2007, he was a Research Asso- the 46th ISSCC/DAC Student Design Contest Award in 2009, and the Best
ciate with the Physics Department, University of Regular Paper Award from the 2012 Custom Integrated Circuits Confer-
Minnesota, Minneapolis, MN, USA. He is currently ence (CICC). He was an Associate Editor of the IEEE T RANSACTIONS ON
a Research Professor with the Physics Department, C IRCUITS AND S YSTEMS II: E XPRESS B RIEFS from 2007 to 2009. He served
Southern Methodist University, Dallas, TX, USA. on the Technical Program Committees for several IEEE solid-state circuits
His main research interest is the data acquisition conferences including the Symposium on VLSI Circuits, the CICC, and
system and integrated circuits design in the the Asian Solid-State Circuits Conference. He currently serves on the data
high-energy physics experiment. converter committee of the ISSCC.

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