Data Communication File
Data Communication File
OBJECTIVE:
To study Basics of serial communication ports and protocols.
EQUIPMENTS:
DCT-03 Kit
9 Pin D connector Cables – 2 Nos.
Computers – 2 nos.
Connecting Chords.
Power Supply.
THEORY:
Need for Serial Communication:
Within a system data is transferred in parallel because it is the fastest
way to do so. For transferring data over long distances, however,
parallel data transfer requires too many wires. Therefore, data to be
send long distances is usually converted to serial form from parallel
form so that it can be sent on a single wire or a pair of wires. Serial
data received from a distance source is converted to parallel form so
that it can be easily transferred to system bus. Three terms often
encountered in serial communication are simplex, half-duplex and full
duplex. A simplex data line can transmit data only in one direction.
Amouse sending data to CPU is an example of simplex communication.
Half-Duplex transmission means that the communication can take
place in either direction between two systems but only one at a time.
An example of Half-Duplex communication is the walky-talky system.
The term full duplex means that each system can send and receive
data at the same time. A normal phone conversation is an example of
a full duplex operation
Protocol
RS-232 communication is asynchronous. That is a clock signal is not
sent with the data. Each word is synchronized using it’s start bit, and
an internal clock on each side, keeps tabs on the timing.
The diagram above shows the expected waveform from the UART
(Universal Asynchronous Transmitter Receiver) when using the
common 8N1 format. 8N1 signify 8 Data bits, No Parity and 1 Stop Bit.
The RS-232 line, when idle is in the Mark State (Logic 1). A
transmission starts with a start bit, which is (Logic 0). Then each bit is
sent down the line, one at a time. The LSB (Least Significant Bit)
is sent first. A Stop Bit (Logic 1) is then appended to the signal to
make up the transmission. The diagram shows the next bit after the
Stop Bit to be Logic 0. This must mean another word is following, and
this is its Start Bit. If there is no more data coming then the receive
line will stay in its idle state (logic 1). We have encountered something
called a "Break" Signal. This is when the data line is held in Logic 0
state for a time long enough to send an entire word. Therefore if you
don’t put the line back into an idle state, the receiving end will
interpret this as a break signal.
The data sent using this method, is said to be framed. That is the data
is framed between a Start and Stop Bit. Should the Stop Bit be
received as Logic 0, then a framing error will occur. This is common,
when both sides are communicating at different speeds.
The above diagram is only relevant for the signal immediately at the
UART. RS-232 logic levels uses +3 to +15 volts to signify a "Space"
The above waveform applies to the Transmit and Receive lines on the
RS-232 port. These lines carry serial data, hence the name Serial Port.
There are other lines on the RS-232 port, which, in essence are
Parallel lines. These lines (RTS, CTS, DCD, DSR, DTR, RTS and RI) are
also at RS-232 Logic Levels.
Simple Error Detection
There are many approaches to overcoming the problems of noise and
distortion. The simplest method is to add a parity bit to be transmitted
with each character. There are two types of parity, odd parity and
even parity. In the following discussion we shall assume that even
parity is in use.
In even parity the total number of 1’s in a transmitted character and
parity bit together is always an even number. If, for example, there
were 3 1’s in a 7 bit character the parity bit would be set to 1 If, on
the other hand there were 4 1’s the parity bit would be set to 0. This is
illustrated in the figure below.
Type Description
Bits/Sec Refers to the Actual information Transfer rate that Can be
achieved on A given channel. It is the result of different coding
Level and signaling rate.
Baud Refers to the fundamental signaling rate used on the circuit.
Rate
For example, the V22 modem as listed above; the carrier frequency is
600 Hertz. The fundamental signaling rate again is 600 baud and an
information transfer rate is 1200 bits/sec. Note that it carries 2 bits for
each operating cycle.
Baud rate refers to the symbol per unit time of which a symbol might
consist of two levels (one bit), four levels (two bits) or even more.
Bit/s refers to the actual measurement of data transmission.
2) Asynchronous Communication
In Asynchronous communication the sender and receiver
decide a data rate before communication. They decide upon
signaling used for start and stop of data transmission.
Both sender and receiver use a precise timing reference
internally to divide serial received data into bits.
Start bit and Stop bit differentiates two different adjacent data words
being transmitted and will also let receiver know when data word
starts and ends.
The sender and receiver decide upon no of bits in one data word
such as 8 bits (1byte). More over they decide that:
A first bit before transmission of data word will always be 0 (or
1) after which data bits will follow. It is called start bit.
The last bit followed by data bits will always be 1(or 0) after
which it requires start bit for transmission of next word. This bit
is called stop bit.
START 1 2 3 4 5 6 7 8 P STOP
Odd Parity:
Odd parity is added to keep the no. of 1’s odd in transmission. For
example for above case of data being
10011101
The odd parity will be added as 0 as no of 1’s are already 5 (an odd no.)
PROCEDURE:
1) Connect the power supply with proper polarity to the Kit DCT-
03 and while connecting, ensure that it is off.
2) Keep all switch faults in off position.
3) Connect 9 Pin D connector Cable between one computer COM
port and CN3 connector and second 9 Pin D connector Cable
between another computer COM port and CN4 connector.
4) Connect the TD1 post to RD2 post.
5) Connect the RD1 post to TD2 post.
6) Keep the switch setting of SW4 towards ON position.
7) Switch ON the power supply and both the computers.
8) Run DCT-03 software on both computers.
9) Select Serial Communication Software link on both computers.
This will provide link to hyper terminal software. A new Window
will Open, where in you Double Click on HYPERTERM,
EQUIPMENTS:
DCT-03 Kit
25 Pin D connector Cables – 2 Nos.
Power Supply.
Printer
Computers – PC, Intel Celeron and above
- 2 nos. (Minimum Configuration).
THEORY:
Windows software is provided to access parallel port of computer, for
Hand shaking of signals and for data transfer between two computers.
Software enables user to communicate between two computers with
three different types of protocols namely, stop and wait, go back to N
and selective repeat. Transfer request, request acknowledgement,
packets transfer, packets receipt, packet verification, error report,
satisfied data report, are indications of this process.
Go back N Protocol
This is the simpler of the two selective repeat protocols as the receiver
rejects every frame except the one it is supposed to receive. There are
several identifying features to this protocol, which are:
Frame numbers lie between 0 and N - 1 if there are more than N
frames,frame numbers are duplicated. So frames are numbered
consecutively modulo N;
The receiving station always expects to receive frames in order
of frame number. If a frame is received out of order it sends a
negative acknowledgement (nak) for the one it wanted and waits
for the correct one to arrive;
If a frame arrives damaged, it is ignored and a nak is sent for it;
However there are also several differences with the Selective Repeat
protocol:
It defines a second sliding window to buffer incoming frames. So
should a frame arrive out of order, it is buffered until its
predecessors arrive - frames must be delivered to the patron in
the correct order;
If a frame arrives whose frame number is in the window it is
accepted and passed on to the patron only once all of its
predecessors have arrived;
If a frame arrives whose frame number is in the window but
whose predecessors have not yet arrived, it is still accepted but
a nak is sent for the one it expected;
Go back N Protocol
This protocol can handle most problems that arise, however its
weakness is its sliding window. If the sliding window size is set to be
the same as the value entered under ’frames to be numbered
consecutively modulo...’ then the protocol may fail - especially when
running under any of the scenarios concerning acknowledgements. For
example if frames are numbered consecutively modulo 6 and the
sliding window size is set to 6 so frames 0 to 5 are sent. Now if the
only acknowledgement returned is that for 5 and this
acknowledgement becomes lost or damaged, the frame timer at the
sender’s end should expire as none of the frames have been
acknowledged. Therefore all the frames in the window are resent. The
receiver not realising that the frames are duplicates accepts the
frames (as they have the correct numbering - again 0 to 5) and
delivers them.Thus this protocol has failed.
GO BACK N PROTOCOL:
2.1) The Receiver’s window size is 1.
2.2) The Transmitter’s window size can be anything from 1 to 7.
2.3) ACK (n):- If a ACK (n) is received it is assumed that all packets
up to the number (including n) have been received correctly.
2.4) NACK (n):- If a NACK (n) is received it is assumed that all
packets prior to the number have been received correctly. The
packet number n is corrupted or discarded by the receiver.
2.5) The Transmitter transmits the packets if the packets are
available in the window for transmission.
2.6) The Transmitter slides its window depending upon the ACK
received and grows up to the MAX_WINDOW_SIZE.
2.7) The Transmitter maintains timers for each packet within its
window which it resets or starts after transmitting the packet.
2.8) The transmitter starts retransmitting all the packets once again
from the packets of which NACK is received or the timer times out.
2.9) The Transmitter stores all the packets until its ACK is received.
2.10) The Receiver sends ACK of the packet if received correctly and
advances its window to receive the next packet.
2.11) The Receiver DISCARDS and sends NACK of the packet if
received corrupt or out of sequence.
PROCEDURE:
1 Refer to the fig. and connect the power supply with proper polarity to the
2 kit DCT-03 and while connecting, ensure that it is off.
3 Keep all switch faults in off position.
4 Keep switches SW6 in PC mode.
5 Connect LPT/parallel port of one PC to connector CN1 using 25-25 D
cable. Similarly connect printer port cable from printer to connector CN2.
6 Keep the switch settings for SW1, SW2 & SW3 in ON position.
7 Switch ON the power supply and both the computers.
8 Run DCT-03 software on computer and Select parallel Communication
Software link both the computers.]
25 At the receiver a selection window will popup to indicate location for the
received file to be saved.
26 Verify the received file with transmitted file, this shows end of file transfer
with success.
27 Click on Protocols menu and select Go Back to N Protocol on both PCs.
28 Select one PC in transmit mode and another PC in receive mode.
29 Select the file to be sent on transmitter side.
30 After the user has selected the file. The PC shows the No of Packets and
31 Size of the file in the boxes on the top. The Packets with their packet
sequence is also shown.
32 You can change delay duration between two adjacent packets as per
requirement.
33 You can change window size of the packet frame as per requirement.
34 Click on Transmit file button.
EQUIPMENTS:
DCT-03 Kit.
9 Pin D connector Cables – 2 Nos,
Modem interface cable.
Power Supply.
Telephone Link.
Computers – PC, Intel Celeron and above
- 2 nos. (Minimum Configuration).
THEORY:
FSK MODEM:
The name modem is a contraction of the term Modulator and demodulator. When
used in the transmitting mode, the modem accepts digital data and converts it to
analog signals for use in modulating a carrier signal. At the receiver end of the
systems, the carrier is demodulated to recover the data.
FSK DEMODULATION:
The most common circuit for demodulating FSK signals is the PLL. The FSK
signal at the PLL input has two values of frequency. The error voltage at the
output of the phase comparator follows these frequency shifts, thus providing a
two-level signal corresponding to the original binary data stream. The PLL
demodulator is followed by a low pass filter, which removes the residual carrier
components, and by a pulse forming circuit which restores the correct shape of
the data signal.
The main aspects of FSK are:
Less error rate than ASK.
if FB is the bit transmission speed, the minimum spectrum Bw of the
modulated signal is higher than Fb
the transmission efficiency, defined as the ratio of Fb and Bw, is less
than1
the “Baud” or “Baud rate”, defined as the “modulation speed” or “symbol
speed”
All of the above modems can operate within a single 300- to 3400-Hz (4-kHz)
telephone channel. As speed increases beyond approximately 19,000 bps, a
wideband modem is needed, as is a wideband channel.
Modem Interfacing:
RS-232 interface is a standard interconnection between business machine and
modem. The RS-232 interface has been defined by the Electronic Industries
Association (EIA) to ensure compatibility between data sets and terminal
equipment.
The RS-232 interface specifications limit the interconnecting cable to a length of
50 ft (15 m)
The interface also specifies the voltage levels with which data and control signals
are exchanged between data sets and business machines. Each pin in the 25-pin
connector will carry either a binary 0 or a I to indicate activation or deactivation
control functions or data values. A binary 1 is used for making and signifies OFF
while the 0 is used for spacing and signifies ON.
Modem interconnection:
The majority of data circuits utilize telephone channels provided by public
carriers. These channels generally pass through switching facilities and are
provided with equipment designed to enhance the use of the channel for voice
application. This type of equipment is not designed specifically for data
transmission, so that the modem must be designed to compensate for any
inadequate of the voice-grade channel. The two broad types of modems are
available for this type of service, the hard-wired modem and the acoustically
coupled data set.
The one limitation of the hard-wired modem is that it precludes mobility since,
being hard-wired; the equipment must remain connected to the circuit terminals.
The acoustically coupled modem solves the mobility problem. Using this device,
a person is able to interconnect with any computer system which has dial-up
interconnect capability.
OBJECTIVE:
The objective of this experiment is to connect the RS-232 ports of two
computers using IR transmitter and IR receiver, transmit data from one
computer and receive the same data on the other computer.
EQUIPMENTS:
DCT-03 Kit
9 Pin D connector Cables – 2 Nos.
Power Supply.
Computers – PC, Intel Celeron and above
- 2 nos. (Minimum Configuration).
THEORY:
Infrared wireless communication is achieved using transmitters/receivers
(transceivers) that modulate noncoherent infrared light. Transceivers must be
within the line of sight of each other either directly or via reflection from a light
colored surface such as the ceiling of a room.
In wireless communication, the serial data is modulated at a carrier frequency of
38 KHz. The RS-232 serial data is simply controls the carrier frequency by
turning the carrier ON/OFF according to the DC level of the serial data.
A 38 KHz carrier frequency is available during the ON time or high level of i/p
where as no carrier during OFF time or low level of i/p. This modulated signal is
fed to IR LED using a transistorized driver circuit.
The receiver is a IR detector module, which filters out the 38 KHz carrier from the
IR signal waves. Thus at the TTL OUT post of IR receiver section, the actual
serial data is being re-constructed with no carrier present. Using this
experimental set up a baud rate of 110 bps to 2400 bps can be achieved on RS-
232 serial port.
The free air IR data transmission, IR remote control as well as the most opto
electronic sensors and light barrier systems work with a wavelength between
870nm and 950nm. The emitter and detector components are highly efficient in
this near IR wavelength band and can be manufactured at low cost. Data
transmission in free space places a high demand for interference immunity on
the IR receiving modules. The receiver unit (waiting to receive signals) is loaded
with different optical and electromagnetic disturbances, omni–present in the
ambient environment or generated by the electrical appliance itself. All optical
sources with an emission spectrum in the receiving bandwidth (830nm –1100nm)
of the detector can be considered as disturbing sources. These are mainly
fluorescent lamps, incandescent lamps and sunlight. Sometimes also plasma
displays emit significantly in the optical band of the IR transmission. As emitter
for the IR signal there are various IR emitting diodes with high brightness and
OBJECTIVE:
The objective of this experiment is to connect the RS-232 ports of two
computers using Optical Fiber Digital Link, transmit data from one
computer over this link and receive the same data on the other computer.
EQUIPMENTS:
DCT-03 Kit
9 Pin D connector Cables – 2 Nos.
Power Supply.
1 Meter Fiber cable.
Computers – PC, Intel Celeron and above - 2 nos. (Minimum
Configuration).
THEORY:
Fiber Optic Links can be used for transmission of digital as well as analog
signals.
Basically a fiber optic link contains three main elements, a transmitter, an optical
fiber and a receiver. The transmitter module takes the input signal in electrical
form and then transforms it into optical (light) energy containing the same
information. The optical fiber is the medium which carries this energy to the
receiver. At the receiver, light is converted back into electrical form with the same
pattern as originally fed to the transmitter.
RECEIVER:
The function of the receiver is to convert the optical energy into electrical form
which is then conditioned to reproduce the transmitted electrical signal in its
original form. We have used a photo detector SFH551V having TTL type output.
Usually it consists of PIN photodiode, transimpedance amplifier and level shifter.
BLOCK DIAGRAM FOR STUDY OF FIBER OPTIC COMMUNICATION.
PROCEDURE:
1 Refer to the fig. and connect the power supply with proper polarity to the
kit DCT-03 and while connecting, ensure that it is off.
2 Keep all switch faults in off position.
3 Connect 9 Pin D connector Cable between one computer COM port and
CN3 connector and second 9 Pin D connector Cable between another
computer COM port and CN4 connector.
4Connect the TD1 post to TX post of Fiber Optic transmitter.
5Slightly unscrew the cap of LED SFH 756(660nm) on kit. Do not remove
the cap from connector. Once the cap is loosened, insert the fiber into
cap, now tight the cap by screwing it back.
6 Connect the other end of fiber cable to detector SFH551V.
7 Connect the TTL OUT post of Fiber Optic receiver to RD2 post.
8Connect the RD1 post to TD2 post.
9 Keep the switch setting of SW4 towards ON position.
10 Switch ON the power supply and both the computers.
11 Run DCT-03 software on both computers.
12 Select Serial Communication Software link on both computers.
13 This will provide link to hyper terminal software.
14 Open the previously stored connection (e.g. pc1 or pc2)
15 To start communicating between the two PCs Click on the TRANSFER
Menu and again click on Send File. A window will be prompted having title
Send File with File Name and Protocol.
16 Select Browse for the file, which you would like to send to the PC
connected, select the file and Click on Open, the file name and address
will be displayed in the small window. Then select the Protocol, (optional
use protocols are X modem, Y modem and 1K Xmodem, etc.)
EQUIPMENT:
Experimentor Kits ADCL-05
Connecting Chords.
Power supply.
e-Lab.
CONCLUSION:
The data are coded in Tribit, which generates, A data signal I (in
phase) consisting in voltage levels corresponding to the value of the
first bit of the considered data, for a period equal to 3 bit intervals. A
data signal Q (in quadrature) consisting in voltage levels
corresponding to the value of the second bit of the data, for duration
equal to 3 bit intervals. A data signal C consisting in voltage levels
corresponding to the value of the third bit of the data, for duration
equal to 3 bit intervals.
OBJECTIVE:
Study of Carrier Modulation Techniques by Quadrature amplitude
method.
EQUIPMENT:
Experimentor Kits ADCL-05
Connecting Chords.
Power supply.
e-Lab.
QAM MODULATOR
Department of ECE Data Communication Lab (EC - 605) 41
The block diagram of the modulator used on the module is shown in
the diagram four 500KHz sine carriers, shifted between them of 90
deg, are applied to modulator. The data (signal I, Q AND C) reach the
modulator from the Tribit coder. The instantaneous value of I, Q and C
data bit generates a symbol. Since I, Q and C can take either 0 or 1
value, maximum 8 possible symbols can begenerated as shown in the
above table. According to the symbol generated one of the four-sine
carriers will be selected. The relation between the symbol generated
and sine carrier is shown in fig.2. A receiver for the QAM signal is
shown in diagram Synchronous detection is required and hence it is
necessary to locally regenerate the carriers. The scheme for carrier
regeneration is similar to BPSK. In that earlier case we squared the
incoming signal, extracted the waveform at twice the carrier frequency
by filtering, and recovered the carrier by frequency dividing by two. In
the present case, it is required that the incoming signal be raised to
the fourth power after which filtering recovers a waveforms at four
times the carrier.
The incoming signal also applied to the sampler followed by an adder
and envelope detectors. Two adders add the sampled QAM signal,
sampled by the Clock having different phases. At the output of adder
the signals consisting the envelope corresponds to the I and Q bit.
Envelope detector then filters the high Frequency components and
PROCEDURE:
1 Refer to Block Diagram & Carry out the following connections and
switch settings.
2 Connect power supply in proper polarity to the kit ADCL-05 and
ADCL-06 switch it on.
3 Select Data pattern of simulated data using switch SW1, SW2, SW3.
4 Connect SDATA generated to DATA IN of NRZ-L CODER.
5 Connect the NRZ-L coded data at DATA OUT to the DATA IN of the
TRIBIT CODER.
6 Connect the clock generated SCLOCK to CLK IN of TRIBIT CODER.
7 Connect the tribit data I BIT, Q BIT & C BIT to control input C1, C2
and C3 of CARRIER MODULATOR respectively.
8 Connect sine carrier to input of CARRIER MODULATOR as follows:
SIN 1 to IN 1.
SIN 2 to IN 2.
SIN 3 to IN 3.
SIN 4 to IN 4.
9 Connect QAM modulated signal MOD OUT on ADCL-05 to the MOD IN
Of the QAM DEMODULATOR on ADCL-06.
10 Connect I BIT, Q BIT & C BIT outputs of QAM Demodulator to I BIT
IN, Q BIT IN & C BIT IN posts of Data Decoder.
11 Put switch SW1 on QAM mode.
12 Observe the decoded data at DATA OUT post of data decoder.
Compare the decoded data with SDATA on ADCL-05.
OBSERVATIONS:
Input NRZ-L coded Data at DATA OUT of NRZ-L coder.
Tribit coded data I BIT, Q BIT & C BIT at the output of tribit coder.
Carrier signal SIN 1 to SIN 4.
QAM modulated signal at MOD OUT of carrier modulator.
ON KIT ADCL-06.
Output of first squarer at SQUARER 1.
Output of second squarer at SQUARER 2.
Recovered carrier of 2MHz at PLL.
CONCLUSION:
In BPSK we deal individually with each bit of duration Tb. In QAM we
lump three bits together to form a SYMBOL. The symbol can have any
one of eight possible values corresponding to three-bit sequence. We
therefore arrange to make available for transmission eight distinct
signals. At the receiver each signal represents one symbol and,
correspondingly, three bits. When bits are transmitted, as in BPSK, the
signal changes occur at the bit rate. When symbols are transmitted the
changes occur at the symbol rate, which is one-third the bit rate. Thus
the symbol time is Ts = 3Tb.
EQUIPMENT:
Experimentor Kits ADCL-02
Connecting Chords.
Power supply.
20 MHZ Dual Trace Oscilloscope.
E-lab.
NON - RETURN TO ZERO signal are the easiest formats that can be
generated. These signals do not return to zero with the clock. The
frequency component associated with these signals are half that of the
clock frequency. Non-return to zero encoding is commonly used in
slow speed communications interfaces for both synchronous and
asynchronous transmission. Using NRZ, logic 1 bit is sent as a high
value and logic 0 bit is sent as a low value.
The mechanism by which a bit stream b (t) generates a QPSK signal
for transmission is shown in fig. 1.2 and relevant waveforms are
shown in fig. In these waveforms we have arbitrarily assumed that in
every case the active edge of the is the upward edge. The toggle flip-
flop generates an odd clock waveform and an even waveform. These
clocks have period 2Tb. The active edge of one of the clocks and the
active edge of the other are separated by the bit time Tb. The bit
stream b(t) is applied as the data input to type-D flip-flops, one driven
by the odd and one, driven by the even clock waveform. The flip-flop
register alternate bits in the stream b (t) and hold each such
registered bit for two bit intervals that is for the time 2Tb. in fig.1.4.
We have numbered the bits in the stream b (t). Note that the bit
stream Bo(t) (which is the output of the flip-flop driven by the odd
clock) registers bit 1 and holds that bit for time 2Tb, then register bit 3
for time 2Tb, then bit 5 for 2Tb, etc. The even bit stream be (t) holds,
for times 2Tb each, the alternates bits numbered 2, 4, 6, etc.
Dibit Conversion
OBSERVATIONS:
Transmitter clock SCLOCK.
Simulated data SDATA.
NRZ-L coded data NRZ-L DATA.
Coded data I BIT.
Coded data Q BIT.
EQUIPMENT:
Experimentor Kit ADCL-02-03.
Connecting Chords.
Power supply.
e-Lab
PROCEDURE:
1 Refer to Block Diagram & Carry out the following connections and
switch settings.
2 Connect power supply in proper polarity to the kit ADCL-02 &
switch it on.
3 Select Data pattern of simulated data using switch SW1.
4 Connect SDATA generated to DATA IN of NRZ-L CODER.
5 Connect the coded data NRZ-L DATA to the DATA IN of the DIBIT
CONVERSION.
6 Connect the SCLOCK to CLK IN of DIBIT CONVERSION.
7 Connect the dibit data I bit to control input C1 of CARRIER MODULATOR
8 Connect the dibit data Q bit to control input C2 of CARRIER MODULATOR.
9 Connect carrier components to input of CARRIER MODULATOR as
follows:
SIN 1 to IN 1
SIN 2 to IN 2
SIN 3 to IN 3
SIN 4 to IN 4
10 Connect QPSK modulated signal MOD OUT on ADCL-02 to the MOD
IN of the QPSK DEMODULATOR on ADCL-03.
11 Observe the output of first squarer at SQUARER 1.
12 Observe the output of second squarer at SQUARER 2.
13 Observe four sampling clocks at the output of SAMPLING CLOCK
GENERATOR.
14 Observe the output of ADDER 1.
15 Observe the output of ADDER 2.
16 Observe the recovered data bit I at the output of ENVELOPE DETECTOR1.
17 Observe the recovered data bit Q at the output of ENVELOPE DETECTOR2.
18 Connect I BIT, Q BIT & CLK OUT outputs of QPSK Demodulator to I
BIT IN, Q BIT IN & CLK IN posts of Data Decoder respectively.
19 Observe the recovered NRZ-L data from I & Q bits at the output of
DATA DECODER.
20 Use RESET switch if delay occurs at data out post and use PHASE
SYNC switch if there is mismatch in the pattern of data at output
with respect to the transmitter data.
CONCLUSION :
In BPSK we deal individually with each bit of duration Tb. In QPSK we
lump two bits together to form a SYMBOL. The symbol can have any
one of four possible values corresponding to two-bit sequence 00, 01,
10, and 11. We therefore arrange to make available for transmission
four distinct signals. At the receiver each signal represents one symbol
and, correspondingly, two bits. When bits are transmitted, as in BPSK,
the signal changes occur at the bit rate. When symbols are transmitted
the changes occur at the symbol rate which is one-half the bit rate.
Thus the symbol time is Ts = 2Tb.