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EXP4 - Report Task

This document contains summaries of 4 code snippets: 1. The first code snippet shows non-blocking and blocking assignments in Verilog. Non-blocking assignments model register updates over multiple clock cycles, while blocking assignments update registers instantly. 2. The second code snippet implements an end-around shift register that shifts the data left on each clock cycle and loads new data when a select signal is asserted. 3. The third code snippet is a Johnson counter that shifts and inverts the bits in a register on each clock cycle. 4. The fourth code snippet is a clock divider that divides the input clock by 16 using a 4-bit counter and toggles the output divided clock each time the counter reaches

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Shamsul Haque
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27 views

EXP4 - Report Task

This document contains summaries of 4 code snippets: 1. The first code snippet shows non-blocking and blocking assignments in Verilog. Non-blocking assignments model register updates over multiple clock cycles, while blocking assignments update registers instantly. 2. The second code snippet implements an end-around shift register that shifts the data left on each clock cycle and loads new data when a select signal is asserted. 3. The third code snippet is a Johnson counter that shifts and inverts the bits in a register on each clock cycle. 4. The fourth code snippet is a clock divider that divides the input clock by 16 using a 4-bit counter and toggles the output divided clock each time the counter reaches

Uploaded by

Shamsul Haque
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Report Task - 1

For Code Snippet -1: Non-blocking assignment, denoted by the symbol "<=", is a type of assignment
used in Verilog. Non-blocking assignments are used in procedural blocks, such as always blocks, to model
synchronous behavior or register updates in a hardware design. Here q1 gets the value from in after the
first clock cycle. After the second clock cycle, q2 gets the value that was assigned to q1 in first clock cycle.
Then on the third clock cycle, out gets the value from q2.

For Code Snippet -2: Blocking assignment, denoted by the symbol "=", is present here in this code. For
having blocking assignment, as soon as in has a value, q1, q2 and out has the value instantly.
Report Task - 2
Verilog Code:
module EndAroundShiftRegister(
input clk, // Clock input
input rst, // Reset input
input [n-1:0] data_in, // Input data (n bits)
input sel, // Load control signal
output [n-1:0] data_out // Output data (n bits)
);
parameter n = 4; // Define the number of bits for the shift register
reg [n-1:0] shift_reg; // n-bit shift register
always @(posedge clk or posedge rst) begin
if (rst) begin
shift_reg <= 0; // Reset the shift register to all zeros
end else begin
if (sel) begin
shift_reg <= data_in; // Load data into the shift register when sel is asserted
end else begin
// Shift the data in the shift register to the left, and the last bit becomes the first bit
shift_reg <= {shift_reg[n-2:0], shift_reg[n-1]};
end
end
end
assign data_out = shift_reg;
endmodule

Timing Diagram:
Report Task -3
Verilog Code:
module johnson(Resetn, Clock, Q);
input Resetn, Clock;
output[7:0] Q;
reg [7:0] Q;
always @(negedge Resetn or posedge Clock)
if(!Resetn)
Q <= 0;
else
Q <= {{Q[6:0]},{~Q[7]}};
endmodule

Timing Diagram:
Report Task - 4
Verilog Code:
module ClockDividerBy16 (clk, divided_clk);
input clk; // Input clock
output reg divided_clk; // Divided clock output
reg [3:0] count; // 4-bit counter to count 16 clock cycles

always @(posedge clk)


begin
if (count == 4'b1111)
begin
divided_clk <= ~divided_clk; // Toggle the divided clock output every 16 cycles
count <= 0; // Reset the counter
end
else
begin
count <= count + 1; // Increment the counter
end
end
endmodule

Timing Diagram:

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