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Lab 2

This document outlines 5 assignments for a laboratory on digital logic circuits. Assignment 1 involves implementing a 2-bit comparator circuit using truth tables, Boolean expressions, logic diagrams, and Verilog. It provides details on each part including constructing the truth table and testbench. The other assignments involve designing logic diagrams from Boolean expressions, writing Verilog models, and verifying the expressions using truth tables and simulations.

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27 views

Lab 2

This document outlines 5 assignments for a laboratory on digital logic circuits. Assignment 1 involves implementing a 2-bit comparator circuit using truth tables, Boolean expressions, logic diagrams, and Verilog. It provides details on each part including constructing the truth table and testbench. The other assignments involve designing logic diagrams from Boolean expressions, writing Verilog models, and verifying the expressions using truth tables and simulations.

Uploaded by

Từ Thị Hồng Điệp
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Laboratory 2 (100 Points)

Assignment 1 (20 Points)


Implement a logic circuit for the two-bit comparator. This comparator has two two-bit inputs A (A =
A1A0) and B (B = B1B0) and produces one output. The output should be 1 if A is greater than B, otherwise
the output should be 0.

a. Construct the truth table for the two-bit comparator


b. Write the sum of product form of the function from the truth table.
c. Simplify the function as much as possible
d. Design a logic diagram for the simplified function
e. Run the simulation of the logic diagram using Simulation Waveform Editor tool.
f. Write a Verilog structural description (gate-entry modeling) for the simplified function
g. Run the simulation of the Verilog code using Simulation Waveform Editor tool.
h. Write a Verilog testbench for the Verilog code to test the model.

a. Construct the truth table for the two-bit comparator

A1 A0 B1 B0 A_greater_than_B
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 1 A > B (A = 1, B = 0)
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 1 A > B (A = 2, B = 0)
1 0 0 1 1 A > B (A = 2, B = 1)
1 0 1 0 0
1 0 1 1 0
1 1 0 0 1 A > B (A = 3, B = 0)
1 1 0 1 1 A > B (A = 3, B = 1)
1 1 1 0 1 A > B (A = 3, B = 2)
1 1 1 1 0

b. Write the sum of product form of the function from the truth table.

A_greater_than_B = A1’A0B1’B0’ + A1A0’B1’B0’ + A1A0’B1’B0 + A1A0B1’B0’ + A1A0B1’B0 + A1A0B1B0’


c. Simplify the function as much as possible

B1B0
00 01 11 10
00
01 1
A1A0
11 1 1 1
10 1 1

A_greater_than_B = A0B1’B0’ + A1A0B0’+A1B1’

d. Design a logic diagram for the simplified function

e. Run the simulation of the logic diagram using Simulation Waveform Editor tool

f. Write a Verilog structural description (gate-entry modeling) for the simplified function
- Set the Verilog file as Top-Level Entity

g. Run the simulation of the Verilog code using Simulation Waveform Editor tool

The same order of A1, A0,


B1, B0 in the truth table
g. Write a Verilog testbench for the Verilog code to test the model

- When you installed the Quartus Prime Lite software, ModelSim - Intel FPGA Starter edition was
installed. We need to configure the Quartus Prime Lite to use ModelSim.

- Go to Tools\Options:
- Write the Verilog testbench to test the module comparator_greater_than_structural:
- Configure EDA Tool Settings for simulation
- Compile and run simulation using ModelSim
Assignment 2 (20 Points)
Design a logic diagram for the following Boolean expressions and write a Verilog program using gate-
level modeling and verify the waveform with its simplified Boolean expression (as much as possible)
truth table.

a) AB(C + D) + AB(C + D)’

b) AB’C + B + BD’ + ABD’ + A’C

Assignment 3 (20 Points)


Write the Boolean expressions for the following a logic diagram and write a Verilog program using gate-
level modeling for the expression. Then verify the waveform with its simplified Boolean expression (as
much as possible) truth table.

(a)

(b)
Assignment 4 (20 Points)
Reduce the following expression in both SOP and POS forms using 3 variable K-map and design the logic
diagram. Now write a Verilog program using gate-level modeling for these simplified Boolean
expressions and verify them with their truth tables and waveforms.

a) Σ m(0, 2, 3, 4, 5, 6)

b) Π M(0, 1, 2, 3 , 4, 7)

Assignment 5 (20 Points)


Reduce the following expression in both SOP and POS forms using 4 variable K-map and design the logic
diagram. Now write a Verilog program using gate-level modeling for these simplified Boolean
expressions and verify them with their truth tables and waveforms.

a) Σ m(0, 1, 2, 3, 5, 7, 8, 9, 10, 12, 13)

b) Π M(2, 8, 9, 10, 11, 12, 14)

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