4282 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 61, NO.

12, DECEMBER 2014

A Compact Current–Voltage Model for 2D

Semiconductor Based Field-Effect Transistors
Considering Interface Traps, Mobility
Degradation, and Inefficient
Doping Effect
Wei Cao, Student Member, IEEE, Jiahao Kang, Student Member, IEEE,
Wei Liu, Member, IEEE, and Kaustav Banerjee, Fellow, IEEE

Abstract— This paper presents an analytical current–voltage

model specifically formulated for 2-dimensional (2D) transition
metal dichalcogenide (TMD) semiconductor based field-effect
transistors (FETs). The model is derived from the fundamentals
considering the physics of 2D TMD crystals, and covers
all regions of the FET operation (linear, saturation, and
subthreshold) under a continuous function. Moreover, three
issues of great importance in the emerging 2D FET arena:
interface traps, mobility degradation, and inefficient doping have
been carefully considered. The compact models are verified
against 2-D device simulations as well as experimental results
for state-of-the-art top-gated monolayer TMD FETs, and can
be easily employed for efficient exploration of circuits based
on 2D FETs as well as for evaluation and optimization of
2D TMD-channel FET design and performance.
Index Terms— 2D field-effect transistor (FET), 2D semi-
conductors, compact modeling, interface trap, molybdenum
disulphide (MoS2 ), transition metal dichalcogenide (TMD),
tungsten diselenide (WSe2 ).
Fig. 1. (a) Top view and side view of monolayer TMD materials. M and X
I. I NTRODUCTION represent metal and chalcogen atoms, respectively. (b) Typical band struc-
ECENTLY, 2D semiconductors,1 primarily the mono-
R
ture of monolayer TMDs. (c) List of practical issues of 2D TMD FETs.
(d) Schematic of a typical top-gated 2D FET. The inset is the zoomed-in-
layer TMDs schematically shown in Fig. 1(a), such view of an infinitely small enclosure along the channel in which Gauss’s law
as molybdenum disulphide (MoS2 ) and tungsten dise- is applied to establish a differential system governing the operation of
lenide (WSe2 ), have gained broad interest as transistor channel 2D FETs. The black arrows in the inset represent electric displacement vector
D. TOX/BOX represent top-oxide/bottom-oxide. A highly doped substrate can
materials [1]–[3] in digital applications due to their atomic also be used as a bottom gate. T2D denotes the thickness of the 2D TMD
scale thicknesses and suitable bandgaps [Fig. 1(b)] that are channel.
highly desirable properties for low-power field-effect tran-
sistors (FETs) in the future sub-10 nm technology nodes. flexibility, transparency, nonzero bandgaps, and dangling-
They are also inherently suitable for display electron- bond-free interfaces. To date, significant progress in this
ics [4] and FET-based bio/gas sensors [5], [6], due to their field has been achieved, such as large-scale chemical-vapor-
Manuscript received March 2, 2014; revised September 24, 2014; accepted
deposition growth of monolayer/multilayer MoS2 [7], n-type
October 20, 2014. Date of current version December 9, 2014. This work multilayer MoS2 FETs with ultralow contact resistance [8],
was supported by the Air Force Office of Scientific Research, Arlington, VA, n-type monolayer WSe2 FETs with record ON-current [9], and
USA, under Grant A9550-14-1-0268 (R18641). The review of this paper was
arranged by Editor N. Bhat.
p-type monolayer WSe2 FETs with subthreshold swing (SS)
The authors are with the Department of Electrical and Computer reaching the theoretical lower limit of 60 mV/dec [10]
Engineering, University of California at Santa Barbara, Santa Barbara, (although only achieved once so far in experimental works
CA 93106 USA (e-mail: [email protected]; [email protected];
[email protected]; [email protected]).
with conventional gate dielectric materials, most reported
Color versions of one or more of the figures in this paper are available values are much larger). Moreover, a tremendous amount of
online at http://ieeexplore.ieee.org. efforts are being expended to address remaining practical
Digital Object Identifier 10.1109/TED.2014.2365028
1 2D semiconductor in this paper specifically refers to 2D transition metal issues, such as high contact resistances [8], [9], [11] to
dichalcogenide (TMD) materials with nonzero bandgaps, and parabolic energy monolayer TMD FETs, low carrier mobility, high trap density,
dispersions (E − k), thus excludes graphene. and lack of efficient doping method, as listed in Fig. 1(c).

0018-9383 © 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

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CAO et al.: COMPACT CURRENT–VOLTAGE MODEL 4283

In parallel with experimental and physical modeling efforts, carrier transport in monolayer TMDs can be described by the
compact modeling work is necessary to pave the way for effective mass based transport equations. It has been found
circuit explorations and wide-scale applications of these that the carrier effective masses in monolayer TMDs are
2D FETs. The only available work [12] on this topic to date, generally larger than commonly used semiconductors, such
simply modeled the intrinsic device characteristics based on as Si, Ge, and III-V, thus a large density of states (DOS)
a lumped capacitance network, which implies that the model that is proportional to the effective mass can be expected.
is not scalable. In addition, the concepts of drift and diffusion Dangling-bond-free monolayer TMDs can potentially achieve
current, chemical or Fermi potential (or voltage), and elec- superior interface properties and high mobilities, but a
trostatic potential are not correctly defined and differentiated, perfect 2D crystal and layered gate dielectric material,
which can be misleading.2 In general, from an application such as hexagonal boron nitride (h-BN) that is also free of
point of view, any 2D FET model that only considers the dangling bonds, are the two prerequisites [15]. However, such
intrinsic characteristics is overidealistic, and hence rarely perfect 2D crystals are not achievable at present. In fact, traps
consistent with real device performance. Extrinsic effects that in 2D FETs arising from the imperfection/contamination of the
are critical for 2D materials should be considered, to make 2D crystals and the dangling bonds at the gate dielectric side
the models useful and relevant to integrated circuit designers. in FETs have been recently reported [16], [17]. These traps
At present, a 2D FET compact model, which is rigorous and remain a performance limiter for 2D TMD based electronic
standardized in terms of the mathematical procedure, compati- devices at the current technology stage of 2D TMD materials.
ble with industry convention (based on surface potential),
self-consistent in terms of the physics, comprehensive in III. D IFFERENTIAL S YSTEM E STABLISHMENT
terms of including practical concerns, and calibrated with For all electronic devices, there always exists a differential
experimental results, is still lacking. This paper is aimed at system that is responsible for their physics and operation,
providing such a model. and also serves as the starting point for compact modeling.
This paper is organized as follows. First, a brief introduction No such system has, so far, been explicitly established for
to the unique physics of 2D TMD semiconductors is provided 2D semiconductor FETs. Therefore, this naturally becomes
in Section II. Then, a differential system for modeling the the first step in this paper.
2D FET operation is established in Section III. Based on this Fig. 1(d) shows a schematic diagram of a typical top-gated
differential system, intrinsic current–voltage (I –V ) model as n-type 2D FET. Note that the model developed in this paper is
well as I –V models that include the key effects of interface transferable to p-type devices by replacing parameters for elec-
traps, mobility degradation, and inefficient source/drain (S/D) trons with that for holes. Since the 2D semiconductor channel
doping are derived in Sections IV–VII, respectively. Next, has an atomic-scale thickness T2D (∼0.65 nm for TMDs), it is
a discussion on modeling of short channel effect (SCE) in reasonable to consider that the electrostatic potential ϕ(x, y)
2D FETs is provided in Section VIII. Finally, the conclusions inside it does not change in the direction vertical to the channel
are drawn in Section IX. plane. An arbitrary enclosure along the channel, with a height
of T2D and an infinitely small length x, is selected for the
II. F UNDAMENTALS OF 2D TMD S EMICONDUCTORS analysis, as shown by the zoomed-in-view inset in Fig. 1(d).
As schematically shown in Fig. 1(a), the in-plane lattice of By applying Gauss’s law to this enclosure, the relationship
TMDs has two types of atoms, M and X, which are arranged between the charge density inside the enclosure and electric
in a 2D honeycomb array within the TMD plane, and in an field outside the enclosure can be obtained
X-M-X sandwich form normal to the TMD plane. M stands for
Q = (εTOX ξTOX + εBOX ξBOX )x
transition metal, such as Mo and W. X stands for chalcogen,
including O, S, Se, and Te. As in graphite, atomically thin + (ε2Dξx (x) + ε2D ξx (x + x))T2D (1)
layers in bulk TMDs are held together by weak van der Waals where εTOX/BOX/2D are the dielectric permittivities of
bonds. Each TMD layer has a fixed and uniform thickness TOX/BOX/2D semiconductor, ΔQ = qΔx(Nimp − n 2D ). q is
of ∼0.65 nm. Fig. 1(b) shows the typical band structure of the elementary charge. Nimp and n 2D are the area densities of
monolayer TMD semiconductors, in which the conduction impurity (net density = donor density − acceptor density) and
band minima and valence band maxima separate, and are electron, respectively. The four electric fields can be written as
both at the high-symmetry K point in the first Brillouin zone,
i.e., monolayer TMDs have direct bandgaps (obtained by Vgt − Δψt − ϕ(x) Vgb − Δψb −ϕ(x)
ξTOX = − , ξBOX = −
first-principle calculation) [13], in contrast with bulk TMDs TTOX TBOX
that have indirect bandgaps. The indirect-to-direct bandgap dϕ(x) dϕ(x + x)
ξx (x) = , ξx (x + x) = −
transition from bulk TMDs to monolayer TMDs is due to dx dx
valley transition induced by the spatial confinement along where Vgt/b are top/bottom gate biases and ψt /b are
the thickness direction [14]. The energy dispersions near flat-band voltages (= the work function difference (divided
the band edges have classic parabolic shapes, indicating that by q) between the top/bottom gate electrodes and the TMD
channel). Note that positive directions of these electric fields
2 The “drift-diffusion” drain current equation in [12] only includes the
are assumed to point outward from the Gaussian enclosure.
drift component and the electric field is incorrectly defined in that work as
the derivative of the Fermi potential or voltage (instead of the electrostatic By substituting the expressions for the above four electric
potential). fields in (1) followed by some reorganization, a differential

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4284 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 61, NO. 12, DECEMBER 2014

equation that determines the channel electrostatic potential Substituting (3) into (5), the Fermi potential can be explicitly
can be obtained as expressed as a function of the electrostatic potential
 
d 2ϕ ϕ
− 2 +ς =
q(n 2D − Nimp )
(2) kT ε2D T2D  ϕ Nimp
dx 2 λ ε2D T2D V =ϕ− ln ς− 2 + (6)
q q NDOS λ NDOS
where
which is very useful in the following I –V model derivation.
Vgt − ψt Vgb − ψb
1/λ2 = 1/λ2T + 1/λ2B , ς = + Since current remains constant along the channel, it is
λ2T λ2B
εTOX εBOX convenient to convert (4) into an integral form as
1/λT =
2
, 1/λ B =
2
. 
ε2D TTOX T2D ε2D TBOX T2D q W μ0 V D
This equation is essentially a modified Poisson’s equation Ids = n 2D d V
L V
specific for 2D FETs. The physical meaning of λ will be  ϕS D 
q W μ0 ε2D T2D  ϕ dV
made evident in Section VIII. The mobile electron density = ς − 2 + Nimp dϕ. (7)
L ϕS q λ dϕ
can be written as
∞ The explicit form of (6) makes possible the variable change
q(ϕ−V )
n 2D = DOS2D (E) f (E − E F )d E ≈ NDOS e kT (3) from V to ϕ. μ0 here is an effective mobility that is inde-
Ec pendent of biasing condition. L is the channel length. With
the known source voltage VS and drain voltage V D , the lower
where
gs g1 m ∗1 kT gs g2 m ∗2 kT − E c limit ϕ S and upper limit ϕ D of the integral can be obtained by
NDOS = + e kT applying Newton–Raphson’s approximation to (6). The final
(2π2 ) (2π2 )
expression for the drain current has a closed form under a
which is the effective electron  DOS for 2D semiconductors, continuous function covering all regions of the FET operation
and the 2D DOS, DOS2D = i=1,2 gs gi m ∗i /(2π2 ), conduc-
(linear, saturation, and subthreshold)
tion band minima E c = −qϕ(x), Fermi level E F = −q V ,
⎛   ⎞
T is temperature, k is Boltzmann’s constant,  is the reduced ε2D T2D kT
ς + 2 + Nimp (ϕ D − ϕ S )⎟
Planck’s constant, gs is spin degeneracy, g1,2 are valley degen- q W μ0 ⎜⎜ q qλ ⎟
eracy, m 1,2 are effective masses, ΔE c is the energy difference Ids = ⎝ ⎠
2D 2D D − ϕ S
ε ϕ 2 2
L T
between the two lowest valleys, and V is the Fermi potential. − 2
qλ 2
Due to the relatively large DOS (∼1014 eV−1 cm−2 ) of TMDs, (8)
the primary 2D semiconductors, FETs based on them generally
work in the nondegenerate condition (E F < E c ) as verified which essentially avoids any nonphysical error when higher-
in Appendix I, thus Boltzmann distribution has been used to order derivatives are applied to the derived current expression.
simplify the Fermi–Dirac distribution function f (E − E F ) Although differences exist between the 2D and 3D physics,
in (3). Note that the second lowest valley [Fig. 1(b)] for such as the DOS, and in terms of the methodologies
TMD materials is nonnegligible, since ΔE c is only around employed in treating the channel potential for 2D FETs
2kT, and its valley degeneracy is as large as 6 (there are 6 and Si semiconductor-on-insulator (SOI)/double-gate (DG)
such valleys inside the first Brillouin zone), compared with FETs [20], it can be observed that the final expres-
2 for the lowest valley. Other valleys are too high [13] to sions have similar form. However, Si SOI/DG FET model
contribute to electrical conduction, and hence neglected. cannot be arbitrarily used for 2D FETs, from both the
Carrier transport is governed by drift–diffusion (DD) mathematical and device physics perspectives. Specifically,
equation [18] equations for obtaining the unknown terms, ϕ S/D , in the
d V (x) final expressions are very different. On the other hand,
Ids (x) = q W n 2D (x)μ(x) (4) DOS in Si SOI/DG FETs is 3D, while it is 2D in 2D
dx
where μ is electron mobility, and W is device width. Both drift FETs, which is physically not interchangeable. Therefore, a
and diffusion components have been included in this equation. physics-based derivation starting from the fundamentals is
Due to the low mean free path (∼15 nm) [19] of carriers in desirable to provide a convincing result specifically for
2D TMD devices, DD equations remain valid even for 2D FETs. To verify the model, transfer characteristics
sub-100 nm channel lengths. and output characteristics are calculated using the model
and compared with self-consistent 2-D numerical simulation
IV. I NTRINSIC I –V M ODEL (Appendix II) in both DG and SOI modes. In the calcula-
The channel electrostatics is determined by (2) in which tion/simulation throughout this paper, 2-nm SiO2 is used as
the first and the rest of the terms on the left of the equality both TOX and BOX, and top and bottom gates are connected
sign are responsible for lateral (along the channel) and vertical together for DG mode; 2-nm SiO2 and 90-nm Al2 O3 are used
(toward the gate) electric fields, respectively. In the limit of as TOX and BOX, respectively, and bottom gate is always
long-channel condition, the lateral field is weak compared with grounded or at a fixed voltage for SOI mode. Some constants
the vertical, thus can be neglected, which is essentially the used in the calculation are μ0 = 50 cm2 V−1 s−1 , L = 10 μm,
gradual channel approximation [18]. Hence, (2) is reduced to
  Nimp = 3.5×1011 cm−2 , ε2D = 4.8ε0 , where ε0 is the vacuum
ε2D T2D ϕ permittivity. As shown in Fig. 2, the analytical model is in
n 2D = ς − 2 + Nimp . (5)
q λ good agreement with numerical simulation in all regimes for

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CAO et al.: COMPACT CURRENT–VOLTAGE MODEL 4285

Fig. 2. (a) Transfer characteristics (logarithmic scale at the left, linear scale
at the right) and (b) output characteristics of an ideal 2D FET in DG and SOI
modes. Fig. 3. (a) Transfer characteristics of a 2D FET in SOI mode considering the
effect of interface traps. E it1 (= −5kT ) and E it2 (= −10kT ) are considered
as two trap energy levels. (b) Model verification with experimental data for a
both DG and SOI modes. The large S/D contact resistance high-performance p-type top-gated monolayer WSe2 FET [10], during which
in the top-gated devices is basically a constant and can be the developed model for an n-type device is modified to that for a p-type
fed into the developed model in the form of a constant series device by replacing parameters for electrons with that for holes, as shown in
Appendix III. Nit and E it are the only two fitting parameters. Other parameters
resistance extracted from experiments. Note that this approach (marked with red color) in the figure are directly adapted from [10].
is applicable for back-gated devices only when the Schottky
barriers at the S/D contacts are low and gate dependence of of electrons that occupy the trap states) can be written as
contact resistance is negligible [8], [9]. Due to the limited  Nit, j
−
space and the similarity between the I –V curves for SOI and N2D,it = qV −qϕ+E it, j
(9)
j 1+ g e
1 kT
DG modes, subsequent analysis and results are shown for the it, j
SOI mode only, unless specified otherwise.
where Nit, j , git, j , and E it, j are the trap density, degeneracy,
and energy level with respect to the conduction band minima,
V. I NTERFACE T RAP M ODEL respectively. By tuning Nit, j , E it, j , and the number of trap
Interface traps that degrade device performance are levels, j , the real trap distribution in energy can be mimicked.
inevitable in FETs, even for those made by state-of-the-art To include the contribution from the interface traps, Nimp
−
CMOS technology. The emerging 2D FETs suffer from this in (2), (5), and (7) should be revised to be Nimp − N2D,it .
issue even more, since the SS of fabricated 2D FETs so far Then, an explicit expression of V similar to that in (6) can
is mostly found to be much larger than the expected value. be obtained. Subsequently, the change of variable procedure
Therefore, it is necessary to include this effect into the compact can be accomplished in the same manner as introduced
model. in Section IV. The closed form of the last-step integral is
For n-type devices, acceptor-type traps, which are nega- achievable, but too complex and long winded. A numerical
tively charged when occupied by electrons and are in the integration is recommended in this step. As shown in Fig. 3(a),
upper half of the bandgap in energy, contribute most to I –V a good agreement is achieved between the results obtained
characteristics.3 The charged trap density (equal to the density from the compact model and simulation in the cases of free-
of-trap, one trap level (at E it1 = −5kT ) and two trap level
3 Note that acceptor-type traps will not be occupied in the deep- OFF-state.
(at both E it1 = −5kT and E it2 = −10kT ). The trap density
However, when Vg pulls down E c during turn-ON, electrons that should have
gone to E c will now charge these traps, thereby degrading the gate efficiency for each level is set as 1 × 1012 cm−2 . It can be observed
and the SS. that the interface traps not only degrade SS but also shift the

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4286 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 61, NO. 12, DECEMBER 2014

threshold voltage. A recent experimental work [10] is used to

verify the validity of the developed model in Fig. 3(b) in which
relevant parameters are listed. It can be found that the intrinsic
I –V model slightly deviates from the experimental values
around the threshold point. By introducing a single trap level
with appropriately tuned density and energy level [values
shown in Fig. 3(b)], the experimental data can be well captured
by the interface trap model.

VI. M OBILITY D EGRADATION

Carrier mobility is not only dependent on the material
but also affected by the biasing (or electric field) condition
of the device, in which the material is integrated. In long-
channel devices, lateral electric field is generally weak, thus its
effects on the carrier mobility, such as velocity saturation, are
negligible. Interestingly, MoS2 was reported to exhibit a very
high critical electric field (∼1.15 × 105 V/cm) [21], which
further enhances the immunity of long-channel MoS2 FETs to
velocity saturation. In contrast, the strong vertical electric field
that shifts the charge centroid in the 2D channel toward the
dangling bonds of the gate dielectric is expected to increase the
scattering rate for carriers and thus degrade carrier mobility.
Due to the lack of a rigorous mobility model for 2D FETs at
this stage, we employ an empirical mobility model that has
been widely used for Si MOSFETs [22]
μ0
μ= (10)
1 + [(|ξ⊥t | + |ξ⊥b |)/ξ⊥c ]α
where ξ⊥c is the critical vertical electric field, α is a fitting Fig. 4. (a) Mobility model calibration with experimental data. Square
symbols are for devices from [1] and [23], circle symbols represent our own
factor, and fabricated top-gated monolayer MoS2 FET (see [8] for experimental details).
εTOX Vgt −ψt −ϕ(x) εBOX Vgb −ψb −ϕ(x) Both devices have a similar device topology, as shown in the inset. ξ⊥c is
ξ⊥t = , ξ⊥b = critical electric field in the denominator of (10). (b) Transfer characteristics
ε2D TTOX ε2D TBOX and transconductance (gm ) of a 2D FET in SOI mode considering the effect of
vertical gate electric field on the carrier mobility. The numerical gm values are
are the effective vertical top/bottom dielectric electric fields obtained by performing small-signal simulation around the dc sweep points.
acting on the carriers. To justify this model for 2D FETs, it
is fitted with experimental data extracted from [1] and [23]
of the Ids –Vg curves (linear scale in red) and decrease of
and our own fabricated top-gated monolayer MoS2 FETs with
transconductance (gm ) after turn-ON. It is worth mentioning
device topology schematically shown in Fig. 4(a). It can be
that any other vertical-field-dependent mobility model for
observed that a good agreement is achieved when ξ⊥c and
2D FETs that may be established by systematic study in the
α are set to be the values listed in the figure, which to
future can be integrated into our I –V model in the same
some extent reflects the similarity of mobility degradation
manner, as shown in this section.
mechanisms in Si MOSFETs and 2D TMD FETs (for typical
Si MOSFETs, ξ⊥c is ∼9 × 107 V/m and α is ∼1.86 [22]).
Note that the values of ξ⊥c and α would typically vary a little VII. I NEFFICIENT S OURCE /D RAIN D OPING
bit under different processing conditions or with different gate Similar to other low-dimensional materials, such as
dielectric materials. 1D nanotubes and nanowires, 2D semiconductors currently
To include this mobility model, only (7) needs to be lack efficient doping method (a recently developed doping
revised as method can achieve high doping level, but it is not practical
 
q W ϕ D ε2D T2D  ϕ dV due to the instability of the gas-phase dopants [10]), which
Ids = μ ς − 2 + Nimp dϕ. (11) makes the access resistance of the 2D FETs significantly
L ϕS q λ dϕ
high. Although the contact resistance, one component of the
Following the procedure introduced in Section IV, the current access resistance of FETs, has been effectively reduced (to
can be calculated. Similar to the case of the interface 0.8 k · μm for few-layer MoS2 FETs [8]) by effectively
traps, the last-step integral can be achieved using numerical metalizing the TMD underneath with selected metals that can
integration due to its complex closed form. As shown in form overlapped d-orbitals with TMD, so that the Schottky
Fig. 4(b), the accuracy of including the mobility model into and tunnel barriers vanish [11], [24], the resistances in the S/D
the I –V model is well verified by simulations. It can be extensions between gate and contact remain high. Purely using
observed that mobility degradation results in the nonlinearity a series resistance to model the function of S/D extension is

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CAO et al.: COMPACT CURRENT–VOLTAGE MODEL 4287

tively. ϕ S (x S ) and ϕ D (x D ) can be solved by substituting

VS and V D into the function VS/D (ϕ). The remaining four
variables are solved from (12) and (13). Fig. 5(a) and (b)
show the transfer characteristics and output characteristics for
different chemical doping density N S/D in S/D extensions
(Vgb = 0 V) and using electrostatic doping (Vgb = 2 V)
that is usually considered a supplementary method to
chemical doping in the 2D FET arena [25]. Doping density
in the channel region NCh is fixed at 3.5 × 1011 cm−2 .
It can be observed that lower N S/D significantly reduces
ON -current, and degrades saturation performance. Electrostatic
doping through bottom gate, although reduces S/D resistance
and improves ON-current, shifts the threshold voltage (due
to electrostatic doping of the channel) and further degrades
saturation (since overdrive voltage is increased by the bottom
gate). A good agreement is achieved between the model and
simulation. It is worthwhile to mention that a similar three-
region approach [26] was applied, very recently, to model the
effects of S/D series resistance in GaN-based high-electron
mobility transistors (HEMTs). However, due to the difference
in device structure and specification between 2D FETs and
HEMTs, the detailed modeling methodology and eventual
form are inevitably different.

VIII. S HORT-C HANNEL E FFECT

In short-channel FETs, the lateral electric field is responsible
for the well-known SCE. Therefore, the first term in (2) that
introduces lateral field in the channel cannot be neglected
Fig. 5. (a) Transfer characteristics and (b) output characteristics of a when analyzing the SCE of 2D FETs. SS is usually considered
2D FET in SOI mode with different S/D extension chemical doping (N S/D )
and electrostatic doping (Vgb ). as an effective indicator of SCE for FET scaling. In the
subthreshold regime, mobile carrier density is negligible,
hence (2) has an explicit solution as
inappropriate. The reason is that the resistance in this region
is bias dependent. More specifically, it is dependent on the φ(0) sinh[(L − x)/λ] + φ(L) sinh(x/λ)
φ= (14)
drain bias in the saturation regime due to the appearance of sinh(L/λ)
a depletion region at the drain side, and dependent on the
where φ = ϕ − λ2 (ς + q Nimp /ε2D), φ(0), and φ(L)
bottom gate bias in SOI mode due to the full coverage of
are determined by the boundary conditions (BCs) at S/D:
the bottom gate to the S/D extensions, as shown in Fig. 1(d).
φ(0) = Vbi , φ(L) = Vbi + V D − VS , where Vbi is the built-in
A more reasonable approach is to divide the device into three
potential at S/D junctions. Subthreshold current can be
regions along the channel: x S to o (source extension), o to x L
obtained by converting (4) to
(channel), and x L to x D (drain extension). Each region is seen  q(V D −V S ) 
as a separate device with different structures. For the device μ0 W kT NDOS 1 − e− kT
operated in SOI mode shown in Fig. 1(d), the channel region Ids =  L − qϕ(x) . (15)
0 e
remains an SOI device, while S/D extensions act as bottom- kT d x

gated FETs. The Fermi potentials are only fixed at x S and x D , Substituting (15) into the definition of SS, we get
and continuous at o and x L . The other useful condition is that
   L − qϕ(x)
current is continuous at o and x L . These four equations can d lg(IDS ) −1 2.3kT 0 e
kT d x
be written as SS = =   (16)
d Vgt q  L − qϕ(x) dϕ(x)
 e kT d x
V (o) = VS/D (ϕ S (o)) = VCh (ϕCh (o)) 0 d Vg
(12)
V (x L ) = VS/D (ϕ D (x L )) = VCh (ϕCh (x L ))
⎧ where
⎨ Ids = Ids,S/D (ϕ S (x S ), ϕ S (o)) ⎧  
= Ids,Ch (ϕCh (o), ϕCh (x L )) ⎪
⎪ λ2 sinh [(L − x)/λ] + sinh(x/λ)
(13) ⎪
⎨ 2 1− , SOI
⎩ dϕ λT
= Ids,S/D (ϕ D (x L ), ϕ D (x D )) =
sinh(L/λ)
d Vg ⎪
⎪ sinh [(L − x)/λ] + sinh(x/λ)
where VS/D (ϕ) and Ids,S/D (ϕ) are modified functions ⎪
⎩1− , DG.
from (6) and (8), respectively, in which λ is replaced sinh(L/λ)
by λ B and ς is replaced by ς S/D = (Vgb − ψb )/λ2B . It can be observed from the above expressions that the con-
VCh (ϕ) and Ids,Ch (ϕ) are the same as in (6) and (8), respec- trollability of gate (dϕ/dV g ) (relevant to the vertical electric

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4288 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 61, NO. 12, DECEMBER 2014

Fig. A1. Surface potential versus gate voltage in an n-type DG MoS2 FET.
Fig. 6. SS versus gate length for a double-gated 2D FET. The inset shows
the channel potential profile of 2D FET with gate length of 20 nm.
TMDs, and thus are specific to them. This eradicates the
field in the gate dielectric) is independent of the permittivity
necessity of any tentative effort in modifying the models for
of the 2D semiconductor channel, which is due to the fact
Si MOSFETs to that for 2D FETs, which may introduce
that the 2D channel is so thin that it contributes little to the
unphysical issues. From an utility point of view, these models
potential or electric field distribution in the vertical direction.
not only provide a useful platform for circuit explorations and
It can also be found that dϕ/dV g is degraded when gate
benchmarking (with respect to Si) with such emerging 2D
length L becomes small. SS is calculated using (16) for the
FETs but also offer the growing 2D TMD FET device com-
DG-mode case in Fig. 6. SS increases rapidly when
munity a user-friendly tool to gain straightforward insight into
L decreases to sub-20 nm regime. It is observed that the
these devices and also to examine their device characterization
compact model deviates from simulation results when L
results, thereby facilitating device design and performance
decreases to sub-30 nm. The inset shows the potential profile
optimization.
along the channel in the case of L = 20 nm, which also
deviates from simulation at the S/D sides. Results in the SOI A PPENDIX I
mode deviate even more, which is not shown here due to V ERIFYING B OLTZMANN S TATISTICS
space limitation. This stems from an assumption during the
establishment of the differential system in the beginning that To verify the validity of using Boltzmann statistics,
the electric field in the oxides is along the vertical direction. we calculate the channel potential versus gate voltage
In fact, electric field in the top and bottom oxides also has for monolayer MoS2 (a typical material among TMDs)
lateral component similar to that considered in the channel. DG FETs considering Fermi–Dirac and Boltzmann distribution
The preassumption that electric field in the gate dielectric is respectively, as shown in Fig. A1. It can be observed that
vertical to the channel, is only valid when the channel is much only for the condition of aggressively scaled gate oxide (both
thicker than the gate dielectric as in ultra-thin body (UTB) TOX and BOX in Fig. 1(d) = 1 nm SiO2 ), and only in
SOI/DG MOSFETs. For 2D FETs, the gate dielectric is much the very strong inversion regime, does the channel potential
thicker than the channel. Under this condition, the electric go beyond the Fermi potential, i.e., degenerate condition.
field distribution cannot simply be considered vertical to the However, the essence of using ultrathin 2D TMDs as channel
channel. 2D Poisson’s equation should be rigorously solved materials in FETs is to help improve the device electrostatics,
in the gate dielectric to obtain the channel potential. This which in turn avoids the aggressive scaling of gate dielec-
effect therefore needs careful consideration for 2D FETs with tric and prevents gate leakage. In fact, the TMD FETs are
L < 30 nm. even further away from degenerate condition compared with
Si DG FETs, which can be shown by comparing Fig. A1
IX. C ONCLUSION
with Fig. 3 in [27]. This is due to the large DOS and
In summary, a compact I –V model for 2D TMD semi- hence large quantum capacitance (Cq in S1) that leads to
conductor channel FETs that not only considers intrin- the weak dependence of the channel potential, beyond the
sic device performance but also includes the effects of threshold voltage, on the gate voltage (most of it drops across
interface traps, mobility degradation, and inefficient S/D the gate dielectric), and thus prevents the gate from moving
extension doping effect, is introduced and verified by E F above E c
2-D numerical simulations as well as experimental results
∂n 2D q 2 NDOS q(ϕ−V )
for state-of-the-art top-gated monolayer TMD FETs. The Cq = q ≈ e kT . (S1)
scalability of the model for ultra-short channel 2D FETs ∂ϕ kT
up to sub-30 nm channel lengths is discussed as well. Therefore, using Boltzmann distribution in this paper is
The compact models developed in this paper are found justified. It is worthwhile to mention that the large DOS can
to pass the Gummel symmetry test, as demonstrated in also help prevent source starvation [28] in 2D TMD FETs that
Appendix IV. Moreover, they are derived from the funda- degrades device performance in the ballistic transport regime
mentals considering the unique physical properties of the 2D in the ultrashort channel case.

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CAO et al.: COMPACT CURRENT–VOLTAGE MODEL 4289

A PPENDIX III
M ODEL FOR P-T YPE D EVICE
In order for the developed model to be applicable to p-type
devices, some parameters for electrons should be modified
to that for holes. Detailed derivation procedure is similar to
that in Sections III-V, and we only provide the key results as
follows.
First, electron density n 2D should be changed to hole density
p2D , and (3) should be modified as
Fig. A2. Numerical simulation domain and BCs employed.
Ev
p2D = DO S 2D (E)[1 − f (E − E F )]dE
−∞
q(V −ϕ−E g /q)
≈ PD O S e kT (S4)
where DO S2D = gs m ∗h /(2π2 ), PD O S = gs m ∗h kT /(2π2 ),
and m ∗h is the hole effective mass. Here, we only consider the
first hole valley at K point in the first Brillouin zone. Second,
(6) should be modified as
 
Eg kT ε2D T2D  ϕ  Nimp
V =ϕ+ + ln −ς − (S5)
q q q N D O S λ2 ND O S
and finally, (8) should be modified as
⎛   ⎞
ε2D T2D kT
− ς − Nimp (ϕ S − ϕ D ) ⎟
q W μ0 ⎜⎜ q qλ2 ⎟
Ids = ⎜ ⎟.
Fig. A3. Ids and its first, second, and third derivatives in the vicinity of L ⎝ T2D ε2D ϕ S2 − ϕ 2D ⎠
Vds = 0 V. The humps (aligned with the break point) on the third derivative +
curve are due to the abrupt scale change around the breaks in the vertical qλ2 2
axes. The inset shows the device schematic and biasing condition for Gummel (S6)
symmetry test.
A PPENDIX IV
A PPENDIX II G UMMEL S YMMETRY T EST
N UMERICAL S IMULATION Gummel symmetry test [30] is usually used as a bench-
In our numerical simulation, the 2-D Poisson’s equation mark test for developed compact models, to quantify their
S/D symmetry. It can be found that during the mathematical
 
∂ ∂ϕ derivation in this paper, source and drain are not specifically
ε(x, y) labeled, which indicates the inherent S/D symmetry of the
∂x ∂x
   −  developed models. As plotted in Fig. A3, Ids and its second
∂ ∂ϕ q n 2D + N2D,it − Nimp
+ ε(x, y) = (S2) derivatives are odd functions of S/D stimulus voltage V X ,
∂y ∂y T2D and continuous in the vicinity of Vds = 0, which meets the
and the 1-D transport equation along the channel requirements of Gummel symmetry test.
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