CoAsia SEMI

Design Compiler – Syntheis

Jumpstart Training
2022 June
Nguyen Van Thang

CONFIDENTIAL
1. Basic reg2reg timing
2. Design setup
3. Design constraint
4. Synthesis optimization
5. Output and report
6. Q&A
1. Basic reg2reg timing
2. Design setup
3. Design constraint
4. Synthesis optimization
5. Output and report
6. Q&A
 Basic timing – Combinational logic charactersitics

80% 80%

20% 50%
50% 20%

50% 50%

• Rise delay (Tr): Measure from 50% voltage level of input to 50% voltage level of rise output
• Fall delay (Tf): Measure from 50% voltage level of input to 50% voltage level of fall output
• Rise transition time: Measure from 20% to 80% of voltage level of rise waveform signal (input or output)
• Fall transition time: Measure from 80% to 20% of voltage level of fall waveform signal (input or output)

CONFIDENTIAL
 Basic timing – Flip-Flop charactersitics
tsetup
thold

D DataX DataY
D Q

tsetup/hold tck2q
CK
tck2q
CK

Q DataX DataY

• Setup time (tsetup): The minimum time data need to be stable before clock trigger edge.
• Hold time (thold): The minimum time data need to be stable after clock trigger edge.
• Delay time (tck2q): The time data propagate from clock trigger edge to data output pin.

CONFIDENTIAL
 Basic timing – Reg2Reg path with ideal clock
T
tX

D1 DataX IN D1 Q1 X D2 Q2 OUT
tck2q tsetup/hold

CK1 CLK CK1 CK2

tck2q DFF1 DFF2
tX

Q1 DataX
tr • Set in ideal clock condition, single cycle design, and assum
data sampled success at DFF1
D2 DataX
• To ensure no setup violation when capture current data at
thold tsetup DFF2:
tr = T – (tck2q + tX) ≥ tsetup
CK2 tck2q + tX ≤ T- tsetup
tck2q + tX ≤ tck2q + tX_max ≤ T- tsetup
• To ensure no hold violation when capture previous data at
DFF2:
• DFF1: launch data
• DFF2: capture data
tck2q + tX ≥ thold
tck2q + tX ≥ tck2q + tX_min ≥ thold
CONFIDENTIAL
 Basic timing – Reg2Reg path with real clock
T
tck2
CLK IN D1 Q1 X D2 Q2 OUT
tX
tck2q tsetup/hold
tck1
D1 DataX CLK CK1 CK2
tck1
DFF1 tck2 DFF2

CK1
tck2q • To ensure no setup violation when capture current data at
tX
DFF2:
Q1 DataX tr = T + tck2 – (tck1 + tck2q + tX) ≥ tsetup
tck2 tr tck2q + tX ≤ T + tck2 - tck1 - tsetup
D2 DataX tck2q + tX ≤ tck2q + tX_max ≤ T + (tck2 - tck1) - tsetup
tsetup
 If tck2>tck1: Good for setup time
thold
 If tck2<tck1: Bad for setup time
• To ensure no hold violation when capture previous data at
CK2 DFF2:
tck1+ tck2q + tX ≥ tck2+ thold
• DFF1: launch data tck2q + tX ≥ tck2q + tX_min ≥ thold + tck2 - tck1
• DFF2: capture data  If tck2>tck1: Bad for hold time
CONFIDENTIAL  If tck2<tck1: Good for hold time
1. Basic reg2reg timing
2. Design setup
3. Design constraint
4. Synthesis optimization
5. Output and report
6. Q&A
 ASIC design flow - Recall

We’re here

Image Source: Synopsys

CONFIDENTIAL
 Logic Synthesis

Image Source: Synopsys

CONFIDENTIAL
 Logic Synthesis

Logic Synthesis = Translation + Mapping + Optimization

residue = 16’h0000;
if (high_bits == 2’b10)
residue = state_table[index];
Translation
else (read_verilog
state_table[index] =
16’h0000; read_vhdl )
Hardware Description
Language (HDL)
Mapping/Optimization
(compile, compile_ultra)
Timing constraints
create_clock …
set_input_delay …
set_output_delay …
… Generic Boolean (GTECH)

Target Technology Gate

(standard cells)
Save Outputs
write_file –format dđc …
write_file –format verilog …
…
CONFIDENTIAL
 Logic optimization – Constraint driven

create_clock …
set_input_delay …
set_output_delay …
Large …

•
Area
•
•
Small • • •

Short Delay Long

Image Source: Synopsys

Design goals (constraints) drive optimization

CONFIDENTIAL
 Design setup - Libraries

• Technology specific for logic synthesis

• Design Compiler requires technology specific logic libraries for synthesis
• Standard cell library
• Hard macro or IP libraries
• Physical library for physical aware synthesis (Optional)
• From the ASIC vender
• Physical cell library: Frame view of standard cell and IP
• Technology data
• Technology file
• TLUPlus file
• Layer mapping file
CONFIDENTIAL
 Design setup - Technology specific libraries

• Technology specific libraries: Provide timing and functionality information for

all standard cells (and, or, inv, buffer, flipflops,…)
• IP/Macro libraries : Provide timing information for hard macros (IP, RAM,
ROM,…)
• Define Logic Design Rule Check (LDRC):
• Min/max transition
• Min/max capacitance
• Min/max fanout

CONFIDENTIAL
 Technology specific libraries – Liberty format example

Cell name

Pin name

DRC rules

Timing delay information

CONFIDENTIAL
 Technology specific libraries – Wire load model

• If not using Physical Aware Synthesis flow, how do you estimate the parasitics of
a net before placement and routing?
• Answer: Using Wire Load Model (WLM), estimate the parasitics base on the
fanout of a net

CONFIDENTIAL
 Design setup – Setting for library

• Target library: using during compile to create technology specify gate level
netlist
• DC optimization selects the smallest gates that meet the required timing and
logic function
• Default setting (non-existent default lib), querry using printvar
target_library:
target_library = your_library.db

• User must specify the actual synthesis libray as target technology

set_app_var target_library “sc_max.db”

CONFIDENTIAL
 Design setup – Setting for library

• Link library: using for resolve instantiated references in a netlist

• First look in DC memory for matching design name.
• Next look in the technology list in the link_library variable for a matching
library cell name.
• Default value
link_library = “* your_library.db”
• User must specify the actual link libray
set_app_var link_library “* $ip_libraries $target_library”

CONFIDENTIAL
 Design setup – Reading RTL files
• Using command
• Verilog file format: read_verilog
• Systemverilog: read_sverilog
• VHDL format: read_vhdl

• The read command:

• Load default and specified libraries
• Read RTL files and translates into GTECH
• Load the unmapdesign in DC memory
• Set the current design

CONFIDENTIAL
 Design setup – Complete scripts for reference

#optional, set folder to find data

set_app_var search_path "$search_path $ADDITIONAL_SEARCH_PATH"
#required, target_library need to set as spec
set_app_var target_library $TARGET_LIBRARY_FILES
#required, link_library need to set as spec
set_app_var link_library "* $target_library"
#optional, set synbol library
set_app_var symbol_library $SYMBOL_LIBRARY_FILE

#optional, load physical library

#start read RTL design

read_verilog ./rtl/TOP.v
current_design TOP
link
#finish loading design step

CONFIDENTIAL
1. Basic reg2reg timing
2. Design setup
3. Design constraint
4. Synthesis optimization
5. Output and report
6. Q&A
 Specifing setup timing constraints

• Goals: Define setup timing constraints for all paths within a sequential design
• All input logic paths (starting from input ports)
• All internal reg2reg path
• All output paths (ending at output ports)
• Under following conditions:
• Follow the design’s spec
• Block or Chip-level design
• Single clock, single cycle or environment synthesis

CONFIDENTIAL
 Default design scenarios

• Design Compiler assumes a synchronously-clock environment. By default:

• Input data arrives from a pos-edge clocked device
• Output data goes to a pos-edge clocked device

CONFIDENTIAL
 Timing analysis during synthesis

• Design Compiler optimization design throught STA engine.

• After read design into memory, during compile process, STA engine break
design into set of timing paths.
• Each timing path is defined by Startpoint and Endpoint.
• Startpoint:
• All input ports, except clock ports
• Clock input pin of sequential elements (FFs,
memory, etc …)

• Endpoint:
• Data input pin of sequential elements (FFs,
memory, etc …)
• Output ports
Image Source: Synopsys

CONFIDENTIAL
 Constraining Register-to-Register path

• How to constraint Register-to-Register paths in MY_DESIGN?

• What’s information must provide?
• ???

CONFIDENTIAL
 Constraining Register-to-Register path

CONFIDENTIAL
 Constraining Register-to-Register path

CONFIDENTIAL
 Constraining Register-to-Register path

• What’s the maximum delay requirement Tmax for Register-to-Register path

through X logic path?

CONFIDENTIAL
 Default clock behavior

• Defining the clock in a single-clock design constraints all timing paths between
registers for single-cycle, setup time.
• By default the clock rises at 0ns and has a 50% duty cycle
• By default, DC will not buffer the clock network, even when connected to many
clock/enable pins of FFs/Latches. The other way, the clock network is treated as
ideal – infinite drive capability
• Zero rise/fall transition time
• Zero skew
• Zero insertion delay or latency
• Estimated skew, latency and transition times can (should be) modeled for more
accurate representation of clock behavior.

CONFIDENTIAL
 Modeling Clock Trees

• Design Compiler is NOT used to synthesize clock buffer trees

• Clock tree synthesis is done by a physical layout tool (ICC2/FC) based on actual
cell placement

• Design Compiler should be model clock tree behavior for correlation QoR
results with PnR step.

CONFIDENTIAL
 Modeling Clock Skew

• Uncertainty models the maximum delay difference berween the clock network
sink pins, knows as clock skew, and can also include clock jitter and timing
margin
set_clock_uncertainty –setup Tu [get_clocks CLK]
* Pre layout, uncertainty Tu=skew+jitter+margin

CONFIDENTIAL
 Modeling Latency or Insertion Delay

• Network latency models the average internal delay from the create_clock port
or pin to the register clock pins
• Source latency models the delay from the actual clock origin to the create_clock
port or pin
• Used for either pre and post layout analysis (ideal vs propagated clock)
set_clock_latency –source –max 3 [get_clock CLK]
set_clock_latency –network –max 1 [get_clocks CLK] ;#only for pre-layout analysis

CONFIDENTIAL
 Modeling Clock Transition Time

• Clock transition time modeling clock rise/fall transition time at register clock
pin at pre-layout step
set_clock_transition TT [get_clock CLK]
• At post layout step, tool wil propagated clock to calculated clock transition time

CONFIDENTIAL
 Constraining Inputs Path

• Spec: Latest data arrival time at port A after Jane’s launch clock edge = 0.6ns
create_clock –period 2 [get_ports Clk]
set_clock_uncertainty –setup 0.3 [get_clocks Clk]
set_input_delay –max 0.6 –clock [get_clocks Clk] [get_ports A]

• What the maximum delay of Tmax?

CONFIDENTIAL
 Constraining Outputs Path

• Spec: Latest data arrival time at port B before JOE’s capture clock edge = 0.8ns
create_clock –period 2 [get_ports Clk]
set_clock_uncertainty –setup 0.3 [get_clocks Clk]
set_input_delay –max 0.6 –clock [get_clocks Clk] [get_ports A]
set_output_delay –max 0.8 –clock [get_clocks Clk] [get_ports B]

• What the maximum delay of Tmax?

CONFIDENTIAL
 Modeling Output Capacitance Load

• Spec: At chip level, maximum capacitive load on output port B = 30fF

create_clock –period 2 [get_ports Clk]
set_clock_uncertainty –setup 0.3 [get_clocks Clk]
set_output_delay –max 0.8 –clock [get_clocks Clk] [get_ports B]
set_load [expr 30.0/1000] [get_ports B]

Cause unit in library is 1pF, define

in technology library

CONFIDENTIAL
 Modeling Input Transition

• Spec: At chip level, maximum rise/fall input transition on input port A=0.12ns
create_clock –period 2 [get_ports Clk]
set_clock_uncertainty –setup 0.3 [get_clocks Clk]
set_output_delay –max 0.8 –clock [get_clocks Clk] [get_ports B]
set_load [expr 30.0/1000] [get_ports B]
set_input_transition 0.12 [get_ports A]

CONFIDENTIAL
 Thank you!

CONFIDENTIAL