8-Channel, 12-Bit, Configurable ADC/DAC

with On-Chip Reference, SPI Interface

Data Sheet AD5592R
FEATURES When an I/Ox pin is configured as an analog input, it is
8-channel, configurable ADC/DAC/GPIO connected to a 12-bit ADC via an analog multiplexer. The input
Configurable as any combination of range of the ADC is 0 V to VREF or 0 V to 2 × VREF. The ADC
8 × 12-bit DAC channels has a total throughput rate of 400 kSPS. The I/Ox pins can also
8 × 12-bit ADC channels be configured as digital, general-purpose input or output
8 × general-purpose digital input/output pins (GPIO) pins. The state of the GPIO pins can be set or read back
Integrated temperature sensor by accessing the GPIO write data register or the GPIO read
SPI interface configuration register, respectively, via a serial peripheral
Available in interface (SPI) write or read operation.
16-ball, 2 mm × 2 mm WLCSP The AD5592R/AD5592R-1 have an integrated 2.5 V, 25 ppm/°C
16-lead, 3 mm × 3 mm LFCSP reference, which is turned off by default, and an integrated
16-lead TSSOP temperature indicator, which gives an indication of the die
temperature. The temperature value is read back as part of an
APPLICATIONS
ADC read sequence.
Control and monitoring
General-purpose analog and digital inputs/outputs The AD5592R/AD5592R-1 are available in 16-ball, 2 mm ×
2 mm WLCSP, 16-lead, 3 mm × 3 mm LFCSP, and 16-lead
GENERAL DESCRIPTION TSSOP. The AD5592R/AD5592R-1 operate over a temperature
The AD5592R/AD5592R-1 have eight I/Ox pins (I/O0 to I/O7) range of −40°C to +105°C.
that can be independently configured as digital-to-analog
Table 1. Related Products
converter (DAC) outputs, analog-to-digital converter (ADC)
Part No. Description
inputs, digital outputs, or digital inputs. When an I/Ox pin is
configured as an analog output, it is driven by a 12-bit DAC. AD5593R AD5592R equivalent with VLOGIC and RESET pins and
an I2C interface
The output range of the DAC is 0 V to VREF or 0 V to 2 × VREF.

FUNCTIONAL BLOCK DIAGRAM

VDD VREF

AD5592R
POWER-ON 2.5V
RESET REFERENCE

GPIO0
INPUT DAC
SYNC REGISTER REGISTER DAC 0 I/O0
SCLK
SDI
GPIO7
SDO SPI INPUT DAC I/O7
REGISTER REGISTER DAC 7
INTERFACE
LOGIC

RESET MUX
SEQUENCER

12-BIT
SUCCESSIVE T/H
APPROXIMATION
ADC

TEMPERATURE
INDICATOR
12506-001

GND

Figure 1. AD5592R Functional Block Diagram

Rev. D Document Feedback

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Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
AD5592R Data Sheet

TABLE OF CONTENTS
Features .............................................................................................. 1  Serial Interface ................................................................................ 26 
Applications ....................................................................................... 1  Power-Up Time .......................................................................... 26 
General Description ......................................................................... 1  Write Mode ................................................................................. 26 
Functional Block Diagram .............................................................. 1  Read Mode .................................................................................. 26 
Revision History ............................................................................... 2  Configuring the AD5592R/AD5592R-1 ................................. 27 
Functional Block Diagram (AD5592R-1) ...................................... 3  General-Purpose Control Register .......................................... 28 
Specifications..................................................................................... 4  DAC Write Operation................................................................ 29 
Timing Characteristics ................................................................ 7  DAC Readback............................................................................ 30 
Absolute Maximum Ratings............................................................ 9  ADC Operation .......................................................................... 31 
Thermal Resistance ...................................................................... 9  GPIO Operation ......................................................................... 35 
ESD Caution .................................................................................. 9  Three-State Pins.......................................................................... 37 
Pin Configurations and Function Descriptions ......................... 10  85 kΩ Pull-Down Resistor Pins................................................ 37 
Typical Performance Characteristics ........................................... 15  Power-Down Mode .................................................................... 38 
Terminology .................................................................................... 20  Reset Function ............................................................................ 39 
ADC Terminology ...................................................................... 20  Readback and LDAC Mode Register ....................................... 39 
DAC Terminology ...................................................................... 21  Applications Information .............................................................. 40 
Theory of Operation ...................................................................... 23  Microprocessor Interfacing ....................................................... 40 
DAC Section ................................................................................ 23  AD5592R/AD5592R-1 to SPI Interface .................................. 40 
ADC Section ............................................................................... 24  AD5592R/AD5592R-1 to SPORT Interface ........................... 40 
GPIO Section .............................................................................. 25  Layout Guidelines....................................................................... 40 
Internal Reference ...................................................................... 25  Outline Dimensions ....................................................................... 41 
RESET Function ......................................................................... 25  Ordering Guide .......................................................................... 42 
Temperature Indicator ............................................................... 25 

REVISION HISTORY
8/2017—Rev. C to Rev. D Changes to Table 18 ....................................................................... 28
Changed VLOGIC Parameter, Table 2 ................................................ 7 Changes to Table 33 ....................................................................... 36
Changes to Table 4 ............................................................................ 8 Changes to Table 39 and Table 41 ................................................ 37
Changed VLOGIC Pin Description, Table 10 .................................. 13 Changes to Ordering Guide .......................................................... 42
Changed VLOGIC Pin Description, Table 11 .................................. 14
10/2014—Rev. 0 to Rev. A
2/2017—Rev. B to Rev. C Added 16-Lead TSSOP ...................................................... Universal
Changes to Figure 9 Caption and Table 11 Title ........................ 14 Changes to Gain Error; Table 2 .......................................................4
Change to D15 Bit Description, Table 22 .................................... 19 Changes to Table 6.......................................................................... 10
Added Figure 6 and Table 8 .......................................................... 12
2/2016—Rev. A to Rev. B Added Figure 8 and Table 10 ........................................................ 14
Changes to Table 2 and Table 3 ....................................................... 7 Changes to Table 12 ....................................................................... 25
Added Figure 7 and Table 9; Renumbered Sequentially ........... 12 Added Figure 48; Outline Dimensions ........................................ 40
Changes to ADC Section ............................................................... 24 Changes to Ordering Guide .......................................................... 41
Added Calculating ADC Input Current Section, Table 12, and
Figure 39 .......................................................................................... 24 8/2014—Revision 0: Initial Version
Changes to Temperature Indicator Section................................. 25

Rev. D | Page 2 of 42
Data Sheet AD5592R

FUNCTIONAL BLOCK DIAGRAM (AD5592R-1)

VLOGIC VDD VREF

AD5592R-1
POWER-ON 2.5V
RESET REFERENCE

GPIO0
INPUT DAC
SYNC REGISTER REGISTER DAC 0 I/O0
SCLK
SDI
GPIO7
SDO SPI INPUT DAC I/O7
REGISTER REGISTER DAC 7
INTERFACE
LOGIC

MUX
SEQUENCER

12-BIT
SUCCESSIVE T/H
APPROXIMATION
ADC

TEMPERATURE
INDICATOR

12506-202
GND

Figure 2. AD5592R-1 Functional Block Diagram

Rev. D | Page 3 of 42
AD5592R Data Sheet

SPECIFICATIONS
VDD = 2.7 V to 5.5 V, VREF = 2.5 V (external), RL = 2 kΩ to GND, CL = 200 pF to GND, TA = TMIN to TMAX, temperature range = −40°C to +105°C,
unless otherwise noted.

Table 2.
Parameter Min Typ Max Unit 1 Test Conditions/Comments
ADC PERFORMANCE fIN = 10 kHz sine wave
Resolution 12 Bits
Input Range 0 VREF V When using the internal ADC buffer, there is
a dead band of 0 V to 5 mV
0 2 × VREF V
Integral Nonlinearity (INL) −2 +2 LSB
Differential Nonlinearity (DNL) −1 +1 LSB
Offset Error ±5 mV
Gain Error 0.3 % FSR
Throughput Rate2 400 kSPS
Track Time (tTRACK)2 500 ns
Conversion Time (tCONV)2 2 µs
Signal-to-Noise Ratio (SNR) 69 dB VDD = 2.7 V, input range = 0 V to VREF
67 dB VDD = 5.5 V, input range = 0 V to VREF
61 dB VDD = 5.5 V, input range = 0 V to 2 × VREF
Signal-to-Noise-and-Distortion (SINAD) Ratio 69 dB VDD = 2.7 V, input range = 0 V to VREF
67 dB VDD = 3.3 V, input range = 0 V to VREF
60 dB VDD = 5.5 V, input range = 0 V to 2 × VREF
Total Harmonic Distortion (THD) −91 dB VDD = 2.7 V, input range = 0 V to VREF
−89 dB VDD = 3.3 V, input range = 0 V to VREF
−72 dB VDD = 5.5 V, input range = 0 V to 2 × VREF
Peak Harmonic or Spurious Noise (SFDR) 91 dB VDD = 2.7 V, input range = 0 V to VREF
91 dB VDD = 3.3 V, input range = 0 V to VREF
72 dB VDD = 5.5 V, input range = 0 V to 2 × VREF
Aperture Delay 2 15 ns VDD = 3 V
12 ns VDD = 5 V
Aperture Jitter2 50 ps
Channel-to-Channel Isolation −95 dB fIN = 5 kHz
Input Capacitance 45 pF
Full Power Bandwidth 8.2 MHz At 3 dB
1.6 MHz At 0.1 dB
DAC PERFORMANCE 3
Resolution 12 Bits
Output Range 0 VREF V
0 2 × VREF V
Integral Nonlinearity (INL) −1 +1 LSB
Differential Nonlinearity (DNL) −1 +1 LSB
Offset Error −3 +3 mV
Offset Error Drift2 8 µV/°C
Gain Error ±0.2 % FSR Output range = 0 V to VREF
±0.1 % FSR Output range = 0 V to 2 × VREF
Zero Code Error 0.65 2 mV
Total Unadjusted Error ±0.03 ±0.25 % FSR Output range = 0 V to VREF
±0.015 ±0.1 Output range = 0 V to 2 × VREF
Capacitive Load Stability2 2 nF RLOAD = ∞
10 nF RLOAD = 1 kΩ
Resistive Load 1 kΩ
Short-Circuit Current 25 mA
Rev. D | Page 4 of 42
Data Sheet AD5592R
Parameter Min Typ Max Unit 1 Test Conditions/Comments
DC Crosstalk2 −4 +4 µV Due to single channel, full-scale output change
DC Output Impedance 0.2 Ω
DC Power Supply Rejection Ratio (PSRR)2 0.15 mV/V DAC code = midscale, VDD = 3 V ± 10% or
5 V ± 10%
Load Impedance at Rails 4 25 Ω
Load Regulation 200 µV/mA VDD = 5 V ± 10%, DAC code = midscale,
−10 mA ≤ IOUT ≤ +10 mA
200 µV/mA VDD = 3 V ± 10%, DAC code = midscale,
−10 mA ≤ IOUT ≤ +10 mA
Power-Up Time 7 µs Coming out of power-down mode, VDD = 5 V
AC SPECIFICATIONS
Slew Rate 1.25 V/µs Measured from 10% to 90% of full scale
Settling Time 6 µs ¼ scale to ¾ scale settling to 1 LSB
DAC Glitch Impulse 2 nV-sec
DAC to DAC Crosstalk 1 nV-sec
Digital Crosstalk 0.1 nV-sec
Analog Crosstalk 1 nV-sec
Digital Feedthrough 0.1 nV-sec
Multiplying Bandwidth 240 kHz DAC code = full scale, output range = 0 V to VREF
Output Voltage Noise Spectral Density 200 nV/√Hz DAC code = midscale, output range = 0 V to
2 × VREF, measured at 10 kHz
Signal-to-Noise Ratio (SNR) 81 dB
Peak Harmonic or Spurious Noise (SFDR) 77 dB
Signal-to-Noise-and-Distortion (SINAD) Ratio 74 dB
Total Harmonic Distortion (THD) −76 dB
REFERENCE INPUT
VREF Input Voltage 1 VDD V
DC Leakage Current −1 +1 µA No I/Ox pins configured as DACs
Reference Input Impedance 12 kΩ DAC output range = 0 V to 2 × VREF
24 kΩ DAC output range = 0 V to VREF
REFERENCE OUTPUT
VREF Output Voltage 2.495 2.5 2.505 V At ambient
VREF Temperature Coefficient 20 ppm/°C
Capacitive Load Stability 5 μF RL = 2 kΩ
Output Impedance2 0.15 Ω VDD = 2.7 V
0.7 Ω VDD = 5 V
Output Voltage Noise 10 µV p-p 0.1 Hz to 10 Hz
Output Voltage Noise Density 240 nV/√Hz At ambient, f = 10 kHz, CL = 10 nF
Line Regulation 20 µV/V At ambient, sweeping VDD from 2.7 V to 5.5 V
10 µV/V At ambient, sweeping VDD from 2.7 V to 3.3 V
Load Regulation
Sourcing 210 µV/mA At ambient, −5 mA ≤ load current ≤ +5 mA
Sinking 120 µV/mA At ambient, −5 mA ≤ load current ≤ +5 mA
Output Current Load Capability ±5 mA VDD ≥ 3 V
GPIO OUTPUT
ISOURCE, ISINK 1.6 mA
Output Voltage
High (VOH) VDD − 0.2 V ISOURCE = 1 mA
Low (VOL) 0.4 V ISOURCE = 1 mA

Rev. D | Page 5 of 42
AD5592R Data Sheet
Parameter Min Typ Max Unit 1 Test Conditions/Comments
GPIO INPUT
Input Voltage
High (VIH) 0.7 × VDD V
Low (VIL) 0.3 × VDD V
Input Capacitance 20 pF
Hysteresis 0.2 V
Input Current ±1 µA
LOGIC INPUTS
AD5592R Input Voltage
High (VINH) 0.7 × VDD V
Low (VINL) 0.3 × VDD V
AD5592R-1 Input Voltage
High (VINH) 0.7 × VLOGIC V
Low (VINL) 0.3 × VLOGIC V
Input Current (IIN) −1 +1 µA Typically 10 nA, RESET = 1 µA typical
Input Capacitance (CIN) 10 pF
LOGIC OUTPUT (SDO)
Output High Voltage (VOH)
AD5592R VDD − 0.2 V ISOURCE = 200 µA, VDD = 2.7 V to 5. 5 V
AD5592R-1 VLOGIC − 0.2 V ISOURCE = 200 µA, VDD = 2.7 V to 5. 5 V
Output Low Voltage (VOL) 0.4 V ISINK = 200 µA
Floating-State Output Capacitance 10 pF
TEMPERATURE SENSOR2
Resolution 12 Bits
Operating Range −40 +105 °C
Accuracy ±3 °C 5 sample averaging
Track Time 5 µs ADC buffer enabled
20 µs ADC buffer disabled
POWER REQUIREMENTS
VDD 2.7 5.5 V
IDD 2.7 mA Digital inputs = 0 V or VDD, I/O0 to I/O7
configured as DACs and ADCs, internal
reference on, ADC buffer on, DAC code = 0xFFF,
range is 0 V to 2 × VREF for DACs and ADCs
Power-Down Mode 3.5 µA
VDD = 5 V (Normal Mode) 1.6 mA I/O0 to I/O7 are DACs, internal reference,
gain = 2
1 mA I/O0 to I/O7 are DACs, external reference,
gain = 2
2.4 mA I/O0 to I/O7 are DACs and sampled by the
ADC, internal reference, gain = 2
1.1 mA I/O0 to I/O7 are DACs and sampled by the
ADC, external reference, gain = 2
1 mA I/O0 to I/O7 are ADCs, internal reference,
gain = 2
0.75 mA I/O0 to I/O7 are ADCs, external reference,
gain = 2
0.5 mA I/O0 to I/O7 are general-purpose outputs
0.5 mA I/O0 to I/O7 are general-purpose inputs
0.5 mA I/O0 to I/O3 are general-purpose outputs,
I/O4 to I/O7 are general-purpose inputs

Rev. D | Page 6 of 42
Data Sheet AD5592R
Parameter Min Typ Max Unit 1 Test Conditions/Comments
VDD = 3 V (Normal Mode) 1.1 mA I/O0 to I/O7 are DACs, internal reference,
gain = 1
1 mA I/O0 to I/O7 are DACs, external reference,
gain = 1
1.1 mA I/O0 to I/O7 are DACs and sampled by the
ADC, internal reference, gain = 1
0.78 mA I/O0 to I/O7 are DACs and sampled by the
ADC, external reference, gain = 1
0.75 mA I/O0 to I/O7 are ADCs, internal reference,
gain = 1
0.5 mA I/O0 to I/O7 are ADCs, external reference,
gain = 1
0.45 mA I/O0 to I/O7 are general-purpose outputs
0.45 mA I/O0 to I/O7 are general-purpose inputs
VLOGIC 1.62 VDD V AD5592R-1 only
ILOGIC 3 µA AD5592R-1 only
1
All specifications expressed in decibels are referred to full-scale input (FSR) and tested with an input signal at 0.5 dB below full scale, unless otherwise noted.
2
Guaranteed by design and characterization; not production tested.
3
DC specifications tested with the outputs unloaded, unless otherwise noted. Linearity calculated using a code range of 8 to 4095. There is an upper dead band of
10 mV when VREF = VDD.
4
When drawing a load current at either rail, the output voltage headroom with respect to that rail is limited by the 25 Ω typical channel resistance of the output
devices. For example, when sinking 1 mA, the minimum output voltage = 25 Ω × 1 mA = 25 mV (see Figure 33).

TIMING CHARACTERISTICS
Guaranteed by design and characterization, not production tested; all input signals are specified with tR = tF = 5 ns (10% to 90% of VDD)
and timed from a voltage level of (VIL + VIH)/2; TA = TMIN to TMAX, unless otherwise noted.

Table 3. AD5592R Timing Characteristics

Parameter 2.7 V ≤ VDD < 3 V 3 V ≤ VDD ≤ 5.5 V Unit Test Conditions/Comments
t1 33 20 ns min SCLK cycle time, write operation
50 50 ns min SCLK cycle time, read operation
t2 16 10 ns min SCLK high time
t3 16 10 ns min SCLK low time
t4 15 10 ns min SYNC falling edge to SCLK falling edge setup time
2 2 µs max SYNC falling edge to SCLK falling edge setup time 1
t5 7 7 ns min Data setup time
t6 5 5 ns min Data hold time
t7 15 10 ns min SCLK falling edge to SYNC rising edge
t8 30 30 ns min Minimum SYNC high time for register write operations
60 60 ns min Minimum SYNC high time for register read operations
t9 0 0 ns min SYNC rising edge to next SCLK falling edge
t10 25 25 ns max SCLK rising edge to SDO valid
t11 250 250 ns min RESET low pulse width (not shown in Figure 4)
1
When reading an ADC conversion.

Rev. D | Page 7 of 42
AD5592R Data Sheet
Table 4. AD5592R-1 Timing Characteristics
Parameter 1.62 V ≤ VLOGIC < 3 V 3 V ≤ VLOGIC ≤ 5.5 V Unit Test Conditions/Comments
t1 33 20 ns min SCLK cycle time, write operation
65 50 ns min SCLK cycle time, read operation
t2 16 10 ns min SCLK high time
t3 16 10 ns min SCLK low time
t4 15 10 ns min SYNC to SCLK falling edge setup time
2 2 µs max SYNC to SCLK falling edge setup time
t5 7 7 ns min Data setup time
t6 5 5 ns min Data hold time
t7 15 10 ns min SCLK falling edge to SYNC rising edge
t8 30 30 ns min Minimum SYNC high time for write operations
60 60 ns min Minimum SYNC high time for register read operations
t9 0 0 ns min SYNC rising edge to next SCLK falling edge
t10 56 25 ns max SCLK rising edge to SDO valid

200µA IOL

TO OUTPUT 1.6V
PIN
CL
25pF

12506-203
200µA IOH

Figure 3. Load Circuit for Logic Output (SDO) Timing Specifications

t1
t9

SCLK
t2
t8 t4 t3 t7

SYNC

t6
t5
SDI DB15 DB0

t10
12506-002

SDO DB15 DB0

Figure 4. Timing Diagram

Rev. D | Page 8 of 42
Data Sheet AD5592R

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted. Transient currents of up to THERMAL RESISTANCE
100 mA do not cause SCR latch-up. θJA is specified for the worst-case conditions, that is, a device
Table 5. soldered in a circuit board for surface-mount packages.
Parameter Rating Table 6. Thermal Resistance
VDD to GND −0.3 V to + 7 V Package Type θJA Unit
VLOGIC to GND −0.3 V to + 7 V 16-Ball WLCSP 60 °C/W
Analog Input Voltage to GND −0.3 V to VDD + 0.3 V 16-Lead LFCSP 137 °C/W
AD5592R 16-Lead TSSOP 112 °C/W
Digital Input Voltage to GND −0.3 V to VDD + 0.3 V
Digital Output Voltage to GND −0.3 V to VDD + 0.3 V
AD5592R-1 ESD CAUTION
Digital Input Voltage to GND −0.3 V to VLOGIC + 0.3 V
Digital Output Voltage to GND −0.3 V to VLOGIC + 0.3 V
VREF to GND −0.3 V to VDD + 0.3 V
Operating Temperature Range −40°C to +105°C
Storage Temperature Range −65°C to +150°C
Junction Temperature (TJ max) 150°C
Lead Temperature JEDEC industry standard
Soldering J-STD-020
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.

Rev. D | Page 9 of 42
AD5592R Data Sheet

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS BALL A1

INDICATOR
1 2 3 4
SDI SCLK RESET SYNC
A

GND I/O7 I/O0 VDD

B

I/O6 I/O3 I/O2 I/O1

C

I/O4 SDO VREF I/O5

D

AD5592R
TOP VIEW

12506-003
(BALL SIDE DOWN)
Not to Scale

Figure 5. AD5592R 16-Ball WLCSP Pin Configuration

Table 7. AD5592R 16-Ball WLCSP Pin Function Descriptions

Pin No. Mnemonic Description
A1 SDI Data In. Logic input. Data that is to be written to the DACs and control registers is provided on this input and
is clocked into the register on the falling edge of SCLK.
A2 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input.
Data can be transferred at rates of up to 50 MHz when writing to the DACs. SCLK has a maximum speed of
20 MHz when performing a conversion or clocking data from the AD5592R.
A3 RESET Asynchronous Reset Pin. Tie this pin high for normal operation. When this pin is brought low, the AD5592R is
reset to its default configuration.
A4 SYNC Synchronization. Active low control input. SYNC is the frame synchronization signal for the input data.
When SYNC goes low, data is transferred in on the falling edges of the next 16 clocks.
B1 GND Ground Reference Point for All Circuitry on the AD5592R.
B2 I/O7 Input/Output 7. This pin can be configured as a DAC, ADC, or general-purpose digital input or output. The
function of this pin is determined by programming the I/Ox pin configuration registers (see Table 15 and
Table 16). I/O7 can also be configured as a BUSY signal to indicate when an ADC conversion is taking place
(see Table 30 and Table 31).
B3, C4, C3, C2, I/O0 to I/O6 Input/Output 0 Through Input/Output 6. These pins can be independently configured as DACs, ADCs, or
D1, D4, C1 general-purpose digital inputs or outputs. The function of each pin is determined by programming the I/Ox
pin configuration registers (see Table 15 and Table 16).
B4 VDD Power Supply Input. The AD5592R operates from 2.7 V to 5.5 V, and this pin must be decoupled with a 0.1 µF
capacitor to GND.
D2 SDO Data Out. Logic output. The conversion results from the ADC, register reads, and temperature sensor
information are provided on this output as a serial data stream. The bits are clocked out on the rising edge
of the SCLK input. The MSB is placed on the SDO pin on the falling edge of SYNC. Because the SCLK can idle
high or low, the next bit is clocked out on the first rising edge of SCLK that follows a falling edge SCLK
while SYNC is low (see Figure 4).
D3 VREF Reference Input/Output. When the internal reference is enabled, the 2.5 V reference voltage is available on
this pin. A 0.1 µF capacitor connected from the VREF pin to GND is recommended to achieve the specified
performance from the AD5592R. When the internal reference is disabled, an external reference must be
applied to this pin. The voltage range for the external reference is 1 V to VDD.

Rev. D | Page 10 of 42
Data Sheet AD5592R

RESET 1 16 SCLK

SYNC 2 15 SDI

VDD 3 14 GND

I/O0 4 AD5592R 13 I/O7

TOP VIEW
I/O1 5 (Not to Scale) 12 I/O6
I/O2 6 11 I/O5

I/O3 7 10 I/O4

12506-303
VREF 8 9 SDO

Figure 6. AD5592R 16-Lead TSSOP Pin Configuration

Table 8. AD5592R 16-Lead TSSOP Pin Function Descriptions

Pin No. Mnemonic Description
15 SDI Data In. Logic input. Data that is to be written to the DACs and control registers is provided on this input and
is clocked into the register on the falling edge of SCLK.
16 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input.
Data can be transferred at rates of up to 50 MHz when writing to the DACs. SCLK has a maximum speed of
20 MHz when performing a conversion or clocking data from the AD5592R.
1 RESET Asynchronous Reset Pin. Tie this pin high for normal operation. When this pin is brought low, the AD5592R is
reset to its default configuration.
2 SYNC Synchronization. Active low control input. SYNC is the frame synchronization signal for the input data. When
SYNC goes low, data is transferred in on the falling edges of the next 16 clocks.
14 GND Ground Reference Point for All Circuitry on the AD5592R.
13 I/O7 Input/Output 7. This pin can be configured as a DAC, ADC, or general-purpose digital input or output. The
function of this pin is determined by programming the I/Ox pin configuration registers (see Table 15 and
Table 16). I/O7 can also be configured as a BUSY signal to indicate when an ADC conversion is taking place
(see Table 30 and Table 31).
4, 5, 6, 7, 10, I/O0 to I/O6 Input/Output 0 Through Input/Output 6. These pins can be independently configured as DACs, ADCs, or
11, 12 general-purpose digital inputs or outputs. The function of each pin is determined by programming the I/Ox
pin configuration registers (see Table 15 and Table 16).
3 VDD Power Supply Input. The AD5592R operates from 2.7 V to 5.5 V, and this pin must be decoupled with a 0.1 μF
capacitor to GND.
9 SDO Data Out. Logic output. The conversion results from the ADC, register reads, and temperature sensor
information are provided on this output as a serial data stream. The bits are clocked out on the rising edge
of the SCLK input. The MSB is placed on the SDO pin on the falling edge of SYNC. Because the SCLK can idle
high or low, the next bit is clocked out on the first rising edge of SCLK that follows a falling edge SCLK while
SYNC is low (see Figure 4).
8 VREF Reference Input/Output. When the internal reference is enabled, the 2.5 V reference voltage is available on
this pin. A 0.1 μF capacitor connected from the VREF pin to GND is recommended to achieve the specified
performance from the AD5592R. When the internal reference is disabled, an external reference must be
applied to this pin. The voltage range for the external reference is 1 V to VDD.

Rev. D | Page 11 of 42
AD5592R Data Sheet

15 RESET
16 SYNC

14 SCLK
13 SDI
V DD 1 12 GND

I/O0 2 AD5592R 11 I/O7

TOP VIEW
I/O1 3 (Not to Scale) 10 I/O6
I/O2 4 9 I/O5

I/O4 8
SDO 7
I/O3 5
VREF 6

12506-007
Figure 7. AD5592R 16-Lead LFCSP Pin Configuration

Table 9. AD5592R 16-Lead LFCSP Pin Function Descriptions

Pin No. Mnemonic Description
1 VDD Power Supply Input. The AD5592R operates from 2.7 V to 5.5 V, and this pin must be decoupled with a 0.1 µF
capacitor to GND.
2, 3, 4, 5, I/O0 to Input/Output 0 Through Input/Output 6. These pins can be independently configured as DACs, ADCs, or general-
8, 9, 10 I/O6 purpose digital inputs or outputs. The function of each pin is determined by programming the I/Ox pin
configuration registers (see Table 15 and Table 16).
6 VREF Reference Input/Output. When the internal reference is enabled, the 2.5 V reference voltage is available on this
pin. A 0.1 µF capacitor connected from the VREF pin to GND is recommended to achieve the specified performance
from the AD5592R. When the internal reference is disabled, an external reference must be applied to this pin. The
voltage range for the external reference is 1 V to VDD.
7 SDO Data Out. Logic output. The conversion results from the ADC, register reads, and temperature sensor information
are provided on this output as a serial data stream. The bits are clocked out on the rising edge of the SCLK input.
The MSB is placed on the SDO pin on the falling edge of SYNC. Because the SCLK can idle high or low, the next bit
is clocked out on the first rising edge of SCLK that follows a falling edge SCLK while SYNC is low (see Figure 4).
11 I/O7 Input/Output 7. This pin can be configured as a DAC, ADC, or general-purpose digital input or output. The function of
this pin is determined by programming the I/Ox pin configuration registers (see Table 15 and Table 16). I/O7 can also
be configured as a BUSY signal to indicate when an ADC conversion is taking place (see Table 30 and Table 31).
12 GND Ground Reference Point for All Circuitry on the AD5592R.
13 SDI Data In. Logic input. Data that is to be written to the DACs and control registers is provided on this input and is
clocked into the register on the falling edge of SCLK.
14 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data
can be transferred at rates of up to 50 MHz when writing to the DACs. SCLK has a maximum speed of 20 MHz
when performing a conversion or clocking data from the AD5592R.
15 RESET Asynchronous Reset Pin. Tie this pin high for normal operation. When this pin is brought low, the AD5592R is reset
to its default configuration.
16 SYNC Synchronization. Active low control input. SYNC is the frame synchronization signal for the input data.
When SYNC goes low, data is transferred in on the falling edges of the next 16 clocks.

Rev. D | Page 12 of 42
Data Sheet AD5592R

15 V LOGIC
16 SYNC

14 SCLK
13 SDI
V DD 1 12 GND

I/O0 2 AD5592R-1 11 I/O7

TOP VIEW
I/O1 3 (Not to Scale) 10 I/O6
I/O2 4 9 I/O5

I/O4 8
SDO 7
I/O3 5
VREF 6

12506-004
Figure 8. AD5592R-1 16-Lead LFCSP Pin Configuration

Table 10. AD5592R-1 16-Lead LFCSP Pin Function Descriptions

Pin No. Mnemonic Description
1 VDD Power Supply Input. The AD5592R-1 operates from 2.7 V to 5.5 V, and this pin must be decoupled with a
0.1 µF capacitor to GND.
2 to 5, 8 to 10 I/O0 to I/O6 Input/Output 0 Through Input/Output 6. These pins can be independently configured as DACs, ADCs,
or general-purpose digital inputs or outputs. The function of each pin is determined by programming
the I/Ox pin configuration registers (see Table 15 and Table 16).
6 VREF Reference Input/Output. When the internal reference is enabled, the 2.5 V reference voltage is available
on this pin. A 0.1 µF capacitor connected from the VREF pin to GND is recommended to achieve the
specified performance from the AD5592R-1. When the internal reference is disabled, an external
reference must be applied to this pin. The voltage range for the external reference is 1 V to VDD.
7 SDO Data Out. Logic output. The conversion results from the ADC, register reads, and temperature sensor
information are provided on this output as a serial data stream. The bits are clocked out on the rising
edge of the SCLK input. The MSB is placed on the SDO pin on the falling edge of SYNC. Because the
SCLK can idle high or low, the next bit is clocked out on the first rising edge of SCLK that follows a
falling edge SCLK while SYNC is low (see Figure 4).
11 I/O7 Input/Output 7. This pin can be configured as a DAC, ADC, or general-purpose digital input or output.
The function of this pin is determined by programming the I/Ox pin configuration registers (see Table 15 and
Table 16). I/O7 can also be configured as a BUSY signal to indicate when an ADC conversion is taking
place (see Table 30 and Table 31).
12 GND Ground Reference Point for All Circuitry on the AD5592R-1.
13 SDI Data In. Logic input. Data to be written to the DACs and control registers is provided on this input and is
clocked into the register on the falling edge of SCLK.
14 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock
input. Data can be transferred at rates of up to 50 MHz when writing to the DACs. SCLK has a maximum
speed of 20 MHz when performing a conversion or clocking data from the AD5592R-1.
15 VLOGIC Interface Power Supply. The voltage of this pin ranges from 1.62 V to 5.5 V.
16 SYNC Synchronization. Active low control input. SYNC is the frame synchronization signal for the input data.
When SYNC goes low, data is transferred in on the falling edges of the next 16 clocks.

Rev. D | Page 13 of 42
AD5592R Data Sheet
BALL A1
INDICATOR
1 2 3 4
SDI SCLK VLOGIC SYNC
A

GND I/O7 I/O0 VDD

B

I/O6 I/O3 I/O2 I/O1

C

I/O4 SDO VREF I/O5

D

AD5592R-1

12506-308
TOP VIEW
(BALL SIDE DOWN)
Not to Scale
Figure 9. AD5592R-1 16-Ball WLCSP Pin Configuration

Table 11. AD5592R-1 16-Lead WLCSP Pin Function Descriptions

Pin No. Mnemonic Description
B4 VDD Power Supply Input. The AD5592R-1 operates from 2.7 V to 5.5 V, and this pin must be decoupled with a
0.1 µF capacitor to GND.
B3, C4, C3, C2, I/O0 to I/O6 Input/Output 0 Through Input/Output 6. These pins can be independently configured as DACs, ADCs,
D1, D4, C1 or general-purpose digital inputs or outputs. The function of each pin is determined by programming
the I/Ox pin configuration registers (see Table 15 and Table 16).
D3 VREF Reference Input/Output. When the internal reference is enabled, the 2.5 V reference voltage is available
on this pin. A 0.1 µF capacitor connected from the VREF pin to GND is recommended to achieve the
specified performance from the AD5592R-1. When the internal reference is disabled, an external
reference must be applied to this pin. The voltage range for the external reference is 1 V to VDD.
D2 SDO Data Out. Logic output. The conversion results from the ADC, register reads, and temperature sensor
information are provided on this output as a serial data stream. The bits are clocked out on the rising
edge of the SCLK input. The MSB is placed on the SDO pin on the falling edge of SYNC. Because the
SCLK can idle high or low, the next bit is clocked out on the first rising edge of SCLK that follows a
falling edge SCLK while SYNC is low (see Figure 4).
B2 I/O7 Input/Output 7. This pin can be configured as a DAC, ADC, or general-purpose digital input or output.
The function of this pin is determined by programming the I/Ox pin configuration registers (see Table 15 and
Table 16). I/O7 can also be configured as a BUSY signal to indicate when an ADC conversion is taking
place (see Table 30 and Table 31).
B1 GND Ground Reference Point for All Circuitry on the AD5592R-1.
A1 SDI Data In. Logic input. Data to be written to the DACs and control registers is provided on this input and is
clocked into the register on the falling edge of SCLK.
A2 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock
input. Data can be transferred at rates of up to 50 MHz when writing to the DACs. SCLK has a maximum
speed of 20 MHz when performing a conversion or clocking data from the AD5592R-1.
A3 VLOGIC Interface Power Supply. The voltage of this pin ranges from 1.62 V to 5.5 V.
A4 SYNC Synchronization. Active low control input. SYNC is the frame synchronization signal for the input data.
When SYNC goes low, data is transferred in on the falling edges of the next 16 clocks.

Rev. D | Page 14 of 42
Data Sheet AD5592R

TYPICAL PERFORMANCE CHARACTERISTICS

1.0 0.5

0.4
0.8
0.3

0.2
0.6
0.1

DNL (LSB)
INL (LSB)

0.4 0

–0.1
0.2
–0.2

–0.3
0
–0.4

–0.2 –0.5

12506-102

12506-105
0 1000 2000 3000 4000 0 1000 2000 3000 4000
ADC CODE ADC CODE

Figure 10. ADC INL, VDD = 5.5 V Figure 13. ADC DNL, VDD = 2.7 V

0.5 35000
VDD = 2.7V
0.4 SAMPLES = 60000
30000 VIN = 1.5V
0.3 GAIN = 1

NUMBER OF OCCURRENCES
EXTERNAL
0.2 25000 REFERENCE = 2.5V

0.1
DNL (LSB)

20000
0
15000
–0.1

–0.2 10000

–0.3
5000
–0.4

–0.5 0

12506-100
12506-103

0 1000 2000 3000 4000 2528 2529 2530

ADC CODE ADC CODE

Figure 11. ADC DNL, VDD = 5.5 V Figure 14. Histogram of ADC Codes, VDD = 2.7 V

0.5 35000
VDD = 5.5V
0.4 SAMPLES = 60000
30000 VIN = 1.5V
0.3 GAIN = 1
NUMBER OF OCCURRENCES

EXTERNALREFERENCE = 2.5V
0.2 25000

0.1
INL (LSB)

20000
0
15000
–0.1

–0.2 10000

–0.3
5000
–0.4

–0.5 0
12506-101
12506-104

0 1000 2000 3000 4000 2520 2521 2522 2523 2524 2525 2526
ADC CODE ADC CODE

Figure 12. ADC INL, VDD = 2.7 V Figure 15. Histogram of ADC Codes, VDD = 5.5 V

Rev. D | Page 15 of 42
AD5592R Data Sheet
1 4
VDD = 3V, 5V
ADC MULTIPLYING BANDWIDTH (dB)

2
–1

GLITCH (nV-sec)
–2
0
–3

–4
–2

–5

–6 –4

12506-126
12506-124
1k 10k 100k 1M 10M 100M 0 1024 2048 3072 4095
FREQUENCY (Hz) DAC CODE

Figure 16. ADC Multiplying Bandwidth Figure 19. DAC Adjacent Code Glitch

1.0 2.510

0.5 2.505
INL (LSB)

VOUT (V)

0 2.500

–0.5 2.495

–1.0 2.490
12506-130

12506-115
0 1024 2048 3072 4095 –10 0 10 20
DAC CODE TIME (µs)

Figure 17. DAC INL Figure 20. DAC Digital-to-Analog Glitch (Rising)

1.0 2.510

0.5 2.505
DNL (LSB)

VOUT (V)

0 2.500

–0.5 2.495

–1.0 2.490
12506-127

12506-116

0 1024 2048 3072 4095 –10 0 10 20

DAC CODE TIME (µs)

Figure 18. DAC DNL Figure 21. DAC Digital-to-Analog Glitch (Falling)

Rev. D | Page 16 of 42
Data Sheet AD5592R
2.58 4.0
1/4 SCALE TO 3/4 SCALE
2.56
3.5
RL = 2kΩ
2.54 CL = 200pF
3.0
2.52
VOUT (V)

VOUT (V)
2.50 2.5

2.48
2.0
2.46

1.5
2.44 3/4 SCALE TO 1/4 SCALE

2.42 1.0

12506-132
12506-119
–10 –5 0 5 10 0 1 2 3 4 5
TIME (µs) TIME (µs)

Figure 22. DAC Settling Time (100 Code Change, Rising Edge) Figure 25. DAC Settling Time, Output Range = 0 V to 2 × VREF

2.58 4.0

2.56 3.5

2.54 3.0

2.52 2.5
VOUT (V)

VOUT (V)
2.50 2.0

2.48 1.5

2.46 1.0
0nF LOAD
10nF LOAD
2.44 0.5 22nF LOAD
47nF LOAD
2.42 0
12506-120

12506-121
–10 –5 0 5 10 –5 0 5 10 15
TIME (µs) TIME (µs)

Figure 23. DAC Settling Time (100 Code Change, Falling Edge) Figure 26. DAC Settling Time for Various Capacitive Loads

2.00 0
1/4 SCALE TO 3/4 SCALE fS = 250kHz
fOUT = 999.45Hz
–20 SNR = 81dB
1.75
THD = –77dB
RL = 2kΩ
SFDR = 77dB
CL = 200pF
–40 SINAD = 74dB
1.50
VOUT (dBV)

–60
VOUT (V)

1.25
–80

1.00
–100

0.75
3/4 SCALE TO 1/4 SCALE –120

0.50 –140
12506-106
12506-131

0 1 2 3 4 5 0 5000 10000 15000 20000

TIME (µs) FREQUENCY (Hz)

Figure 24. DAC Settling Time, Output Range = 0 V to VREF Figure 27. DAC Sine Wave Output, Output Range = 0 V to 2 × VREF,
Bandwidth = 0 Hz to 20 kHz

Rev. D | Page 17 of 42
AD5592R Data Sheet
0 2500
fS = 250kHz FULL SCALE
fOUT = 999.45Hz 3/4 SCALE
–20 SNR = 80dB MIDSCALE
THD = –67dB 2000 1/4 SCALE
SFDR = 67dB ZERO SCALE
–40 SINAD = 65dB

NSD (nV/√Hz)
1500
VOUT (dBV)

–60

–80
1000

–100

500
–120

–140 0

12506-107

12506-112
0 5000 10000 15000 20000 10 100 1k 10k 100k 1M
FREQUENCY (Hz) FREQUENCY (Hz)

Figure 28. DAC Sine Wave Output, Output Range = 0 V to VREF, Figure 31. DAC Output Noise Spectral Density (NSD)
Bandwidth = 0 Hz to 20 kHz
200 5

150
4
100
OUTPUT VOLTAGE (V)
50
VOUT (µV p-p)

0 FULL SCALE

2
–50 3/4 SCALE

1/2 SCALE
–100
1
1/4 SCALE
–150

ZERO SCALE
–200 0
12506-109

12506-133
0 2 4 6 8 10 –30 –20 –10 0 10 20 30
TIME (Seconds) LOAD CURRENT (mA)

Figure 29. DAC 1/f Noise with External Reference Figure 32. DAC Output Sink and Source Capability,
Output Range = 0 V to VREF
200 6

FULL SCALE
150 5

100
3/4 SCALE
OUTPUT VOLTAGE (V)

50
VOUT (µV p-p)

3
1/2 SCALE
0
2
–50 1/4 SCALE
1
–100
ZERO SCALE

–150 0

–200 –1
12506-134
12506-110

0 2 4 6 8 10 –30 –20 –10 0 10 20 30

TIME (Seconds) LOAD CURRENT (mA)

Figure 30. DAC 1/f Noise with Internal Reference Figure 33. DAC Output Sink and Source Capability,
Output Range = 0 V to 2 × VREF

Rev. D | Page 18 of 42
Data Sheet AD5592R
20 2.5005

15
2.5003
10

5
VOUT (µV p-p)

2.5001

VREF (V)
0

–5 2.4999

–10
2.4997
–15

–20 2.4995

12506-111

12506-204
0 2 4 6 8 10 2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4
TIME (Seconds) VDD (V)

Figure 34. Internal Reference 1/f Noise Figure 36. Reference Line Regulation

1200

1000

800
NSD (nV/√Hz)

600

400

200

0
12506-113

10 100 1k 10k 100k 1M

FREQUENCY (Hz)

Figure 35. Reference Noise Spectral Density (NSD)

Rev. D | Page 19 of 42
AD5592R Data Sheet

TERMINOLOGY
ADC TERMINOLOGY Signal-to-Noise-and-Distortion (SINAD) Ratio
Integral Nonlinearity (INL) SINAD is the measured ratio of signal-to-noise-and-distortion
INL is the maximum deviation from a straight line passing through at the output of the ADC. The signal is the rms amplitude of the
the endpoints of the ADC transfer function. The end-points of fundamental. Noise is the sum of all nonfundamental signals up
the transfer function are zero scale, a point that is 1 LSB below to half the sampling frequency (fS/2), excluding dc. The ratio is
the first code transition, and full scale, a point that is 1 LSB dependent on the number of quantization levels in the digitization
above the last code transition. process; the more levels, the smaller the quantization noise. The
theoretical SINAD ratio for an ideal N-bit converter with a sine
Differential Nonlinearity (DNL) wave input is given by
DNL is the difference between the measured and the ideal
1 LSB change between any two adjacent codes in the ADC. SINAD (dB) = 6.02N + 1.76

Offset Error Thus, for a 12-bit converter, SINAD is 74 dB.

Offset error is the deviation of the first code transition (00 … 000) Total Harmonic Distortion (THD)
to (00 … 001) from the ideal, that is, AGND + 1 LSB. THD is the ratio of the rms sum of harmonics to the fundamental.
Offset Error Match For the AD5592R/AD5592R-1, it is defined as
Offset error match is the difference in offset error between any V2 2 + V3 2 + V4 2 + V5 2 + V6 2
two channels. THD (dB ) = 20 × log
V1
Gain Error where:
Gain error is the deviation of the last code transition (111 … 110) V1 is the rms amplitude of the fundamental.
to (111 … 111) from the ideal (that is, VREF − 1 LSB) after the V2, V3, V4, V5, and V6 are the rms amplitudes of the second
offset error has been adjusted out. through the sixth harmonics.
Channel-to-Channel Isolation Peak Harmonic or Spurious Noise (SFDR)
Channel-to-channel isolation is a measure of the level of crosstalk Peak harmonic or spurious noise is defined as the ratio of the
between channels. It is measured by applying a full-scale, 5 kHz rms value of the next largest component in the ADC output
sine wave signal to all nonselected ADC input channels and spectrum (up to fS/2 and excluding dc) to the rms value of the
determining how much that signal is attenuated in the selected fundamental. Normally, the value of this specification is
channel. This specification is the worst case across all ADC determined by the largest harmonic in the spectrum, but for
channels for the AD5592R/AD5592R-1. ADCs where the harmonics are buried in the noise floor, it is a
Track-and-Hold Acquisition Time noise peak.
The track-and-hold amplifier enters hold mode on the falling
edge of SYNC and returns to track mode when the conversion
is complete. The track-and-hold acquisition time is the
minimum time required for the track-and-hold amplifier to
remain in track mode for its output to reach and settle to within
±1 LSB of the applied input signal, given a step change to the
input signal.

Rev. D | Page 20 of 42
Data Sheet AD5592R
DAC TERMINOLOGY Digital Feedthrough
Relative Accuracy or Integral Nonlinearity (INL) Digital feedthrough is a measure of the impulse injected into the
For the DAC, relative accuracy or integral nonlinearity is a analog output of the DAC from the digital inputs of the DAC,
measurement of the maximum deviation, in LSBs, from a but is measured when the DAC output is not updated. It is
straight line passing through the endpoints of the DAC transfer specified in nV-sec, and measured with a full-scale code change
function. A typical INL vs. code plot is shown in Figure 17. on the data bus, that is, from all 0s to all 1s and vice versa.

Differential Nonlinearity (DNL) Reference Feedthrough

Differential nonlinearity is the difference between the measured Reference feedthrough is the ratio of the amplitude of the signal
change and the ideal 1 LSB change between any two adjacent at the DAC output to the reference input when the DAC output
codes. A specified differential nonlinearity of ±1 LSB maximum is not being updated. It is expressed in dB.
ensures monotonicity. This DAC is guaranteed monotonic by Noise Spectral Density
design. A typical DNL vs. code plot can be seen in Figure 18. Noise spectral density is a measurement of the internally generated
Zero Code Error random noise. Random noise is characterized as a spectral
Zero code error is a measurement of the output error when zero density (nV/√Hz). It is measured by loading the DAC to midscale
code (0x000) is loaded to the DAC register. Ideally, the output is and measuring noise at the output. It is measured in nV/√Hz.
0 V. The zero code error is always positive in the AD5592R/ DC Crosstalk
AD5592R-1 because the output of the DAC cannot go below DC crosstalk is the dc change in the output level of one DAC in
0 V due to a combination of the offset errors in the DAC and response to a change in the output of another DAC. It is
the output amplifier. Zero code error is expressed in mV. measured with a full-scale output change on one DAC (or soft
Gain Error power-down and power-up) while monitoring another DAC
Gain error is a measure of the span error of the DAC. It is the maintained at midscale. It is expressed in μV.
deviation in slope of the DAC transfer characteristic from the DC crosstalk due to load current change is a measure of the
ideal expressed as % FSR. impact that a change in load current on one DAC has to
Offset Error Drift another DAC kept at midscale. It is expressed in μV/mA.
Offset error drift is a measurement of the change in offset error Digital Crosstalk
with a change in temperature. It is expressed in µV/°C. Digital crosstalk is the glitch impulse transferred to the output
Gain Temperature Coefficient of one DAC at midscale in response to a full-scale code change
Gain temperature coefficient is a measurement of the change in (all 0s to all 1s and vice versa) in the input register of another DAC.
gain error with changes in temperature. It is expressed in ppm It is measured in standalone mode and is expressed in nV-sec.
of FSR/°C. Analog Crosstalk
Offset Error Analog crosstalk is the glitch impulse transferred to the output
Offset error is a measurement of the difference between VOUT of one DAC due to a change in the output of another DAC. It is
(actual) and VOUT (ideal), expressed in mV, in the linear region measured by loading one of the input registers with a full-scale
of the transfer function. Offset error can be negative or positive. code change (all 0s to all 1s and vice versa), then executing a
software LDAC (see Table 45 and Table 46), and monitoring the
DC Power Supply Rejection Ratio (PSRR) output of the DAC whose digital code was not changed. The
PSRR indicates how the output of the DAC is affected by changes area of the glitch is expressed in nV-sec.
in the supply voltage. PSRR is the ratio of the change in VOUT to
a change in VDD for a full-scale output of the DAC. It is measured DAC-to-DAC Crosstalk
in mV/V. VREF is held at 2 V, and VDD is varied by ±10%. DAC-to-DAC crosstalk is the glitch impulse transferred to the
output of one DAC due to a digital code change and subsequent
Output Voltage Settling Time analog output change of another DAC. It is measured by loading
Output voltage settling time is the amount of time it takes for the the attack channel with a full-scale code change (all 0s to all 1s
output of a DAC to settle to a specified level for a ¼ to ¾ full-scale and vice versa), using the write to and update commands while
input change and is measured from the rising edge of SYNC. monitoring the output of the victim channel that is at midscale.
Digital-to-Analog Glitch Impulse The energy of the glitch is expressed in nV-sec.
Digital-to-analog glitch impulse is the impulse injected into the Multiplying Bandwidth
analog output when the input code in the DAC register changes The amplifiers within the DAC have a finite bandwidth; the
state. It is normally specified as the area of the glitch in nV-sec, multiplying bandwidth is a measure of this. A sine wave on the
and is measured when the digital input code is changed by 1 LSB reference (with full-scale code loaded to the DAC) appears on
at the major carry transition (0x7FF to 0x800). the output. The multiplying bandwidth is the frequency at which
the output amplitude falls to 3 dB below the input.

Rev. D | Page 21 of 42
AD5592R Data Sheet
Voltage Reference Temperature Coefficient (TC) where:
Voltage reference TC is a measure of the change in the reference VREF(MAX) is the maximum reference output measured over the
output voltage with a change in temperature. The voltage total temperature range.
reference TC is calculated using the box method, which defines VREF(MIN) is the minimum reference output measured over the
the TC as the maximum change in the reference output over a total temperature range.
given temperature range expressed in ppm/°C, as follows: VREF(NOM) is the nominal reference output voltage, 2.5 V.
Temp Range is the specified temperature range of −40°C to
 VREF ( MAX ) − VREF ( MIN )  6 +105°C.
TC =   × 10
V
 REF ( NOM ) × Temp Range 

Rev. D | Page 22 of 42
Data Sheet AD5592R

THEORY OF OPERATION
The AD5592R/AD5592R-1 are 8-channel configurable analog Resistor String
and digital input/output ports. The AD5592R/AD5592R-1 have The simplified segmented resistor string DAC structure is
eight pins that can be independently configured as a 12-bit shown in Figure 38. The code loaded to the DAC register
DAC output channel, a 12-bit ADC input channel, a digital determines the switch on the string that is connected to the
input pin, or a digital output pin. output buffer.
The function of each pin is determined by programming the ADC, Because each resistance in the string has the same value, R, the
DAC, or GPIO configuration registers as appropriate. See the string DAC is guaranteed monotonic.
Configuring the AD5592R/AD5592R-1 section and Table 16 for
more information. R

DAC SECTION
The AD5592R/AD5592R-1 contain eight 12-bit DACs and R
implement a segmented string DAC architecture with an
internal output buffer. Figure 37 shows the internal block
TO OUTPUT
diagram of the DAC architecture. R
BUFFER
VREF

REF (+)
RESISTOR
DAC REGISTER STRING I/Ox

REF (–) OUTPUT R

12506-011

AMPLIFIER

GND
R
Figure 37. Internal Block Diagram of the DAC Architecture

12506-012
The DAC channels have a shared gain bit that sets the output
range as 0 V to VREF or 0 V to 2 × VREF. Because the gain bit is Figure 38. Simplified Resistor String Structure
shared by all channels, it is not possible to set different output
ranges on a per channel basis. The input coding to the DAC is Output Buffer
straight binary. The ideal output voltage is given by The output buffer is designed as an input/output rail-to-rail
buffer. The output buffer can drive 2 nF capacitance with a 1 kΩ
 D  resistor in parallel. The slew rate is 1.25 V/µs with a ¼ to ¾
VOUT = G × VREF ×  

 2N  scale settling time of 6 µs. By default, the DAC outputs update
directly after data has been written to the input register. The
where:
LDAC register is used to delay the updates until additional
D is the decimal equivalent of the binary code (0 to 4095) that is
channels have been written to, if required. See the Readback
loaded to the DAC register.
and LDAC Mode Register section for more information.
G = 1 for an output range of 0 V to VREF, or G = 2 for an output
range of 0 V to 2 × VREF.
N = 12.

Rev. D | Page 23 of 42
AD5592R Data Sheet
ADC SECTION Calculating ADC Input Current
The 12-bit, single-supply ADC is capable of throughput rates of The current flowing into the I/Ox pins configured as ADC
400 kSPS. The ADC is preceded by a multiplexer that switches inputs vary with the sampling rate (fS), the voltage difference
selected I/Ox pins to the ADC. A sequencer is included to between successive channels (VDIFF), and whether buffered or
automatically switch the multiplexer to the next selected unbuffered mode is used. Figure 39 shows a simplified version
channel. Channels are selected for conversion by writing to the of the ADC input structure. When a new channel is selected for
ADC sequence register. When the write to the ADC sequence conversion, the 5.8 pF capacitor must be charged or discharged
register has completed, the first channel in the conversion of the voltage that was on the previously selected channel. The
sequence is put into track mode. Allow each channel to track time required by the charge or discharge depends on the voltage
the input signal for a minimum of 500 ns. The first SYNC difference between the two channels. This affects the input
falling edge following the write to the ADC sequence register impedance of the multiplexer and therefore the input current
begins the conversion of the first channel in the sequence. The flowing into the I/Ox pins. In buffered mode, Switch S1 is open
next SYNC falling edge starts a conversion on the second and Switch S2 is closed, in which case the U1 buffer is directly
channel in the sequence and also begins to clock the first ADC driving the 23.1 pF capacitor, and its charging time is negligible.
result onto the serial interface. ADC data is clocked out of the In unbuffered mode, Switch S1 is closed and Switch S2 is closed.
AD5592R in a 16-bit frame. D15 is 0 to indicate that the data In unbuffered mode, the 23.1 pF capacitor must be charged
contains ADC data, D14 to D12 is the binary representation of from the I/Ox pins, which contributes to the input current.
the ADC address, and D11 to D0 is the ADC result (see Table 12). For applications where the ADC input current is too high, an
external input buffer may be required. The choice of buffer is a
Each conversion takes 2 µs, and the conversion must be
function of the particular application.
completed before another conversion is initiated. Only write to
the AD5592R/AD5592R-1 when no conversion is taking place. Calculate the input current for buffered mode as follows:
I/O7 can be configured as a BUSY signal to indicate when a fS × C × VDIFF + 1 nA
conversion is taking place. BUSY goes low while a conversion is where:
in progress, and high when an ADC result is available. The fS is the ADC sample rate in Hertz.
ADC has an input range selection bit (Bit D5 in the general- C is the sampling capacitance in Farads.
purpose control register), which sets the input range as 0 V to VDIFF is the voltage change between successive channels.
VREF or 0 V to 2 × VREF. All input channels share the same range. 1 nA is the dc leakage current associated with buffered mode.
The output coding of the ADC is straight binary. It is possible to
Calculate the input current for unbuffered mode as follows:
set each I/Ox pin as both a DAC and an ADC. When an I/Ox
pin is set as both a DAC and an ADC, the primary function is fS × C × VDIFF
that of the DAC. If the pin is selected for inclusion in an ADC An example solution is as follows: for the ADC input current in
conversion sequence, the voltage on the pin is converted and buffered mode, where I/O0 = 0.5 V, I/O1 = 2 V, and fS = 10 kHz,
made available via the serial interface, allowing the DAC voltage
(10,000 × 5.8 × 10−12 × 1.5) + 1 nA = 88 nA
to be monitored.
Under the same conditions, the ADC input current in unbuffered
mode is as follows:
(10,000 × 28.9 × 10−12 × 1.5) = 433.5 nA
Table 12. ADC Conversion Format
MSB LSB
D15 D14 D13 D12 D11 to D0
0 ADC address 12-bit ADC data

S1
I/O0
MUX

S2

I/O7 5.8pF U1
300Ω
S3
23.1pF CONTROL
S4 LOGIC

COMPARATOR
12506-039

Figure 39. ADC Input Structure

Rev. D | Page 24 of 42
Data Sheet AD5592R
GPIO SECTION RESET FUNCTION
Each of the eight I/Ox pins can be configured as a general- The AD5592R/AD5592R-1 have an asynchronous RESET pin.
purpose digital input pin by programming the GPIO read For normal operation, RESET is tied high. A falling edge
configuration register or as a digital output pin by programming on RESET resets all registers to their default values and
the GPIO write configuration register. When an I/Ox pin is reconfigures the I/Ox pins to their default values (85 kΩ pull-
configured as an output, the pin can be set high or low by down to GND). The reset function takes 250 µs maximum; do
programming the GPIO write data register. Logic levels for not write new data to the AD5592R/AD5592R-1 during this
general-purpose outputs are relative to VDD and GND. When an time. The AD5592R/AD5592R-1 have a software reset that
I/Ox pin is configured as an input, its status can be determined performs the same function as the RESET pin. The reset
by setting Bit D10 in the GPIO read configuration register (see
function is activated by writing 0x5AC to the reset register
Table 37). The next SPI operation clocks out the state of the
(see Table 44).
GPIO pins. When an I/Ox pin is set as an output, it is possible
to read its status by also setting it as an input pin. When reading TEMPERATURE INDICATOR
the status of the I/Ox pins set as inputs, the status of an I/Ox pin The AD5592R/AD5592R-1 contain an integrated temperature
set as both an input and output pin is also returned. indicator, which can be read to provide an estimation of the die
INTERNAL REFERENCE temperature. The temperature reading can be used in fault
detection where a sudden rise in die temperature may indicate a
The AD5592R/AD5592R-1 contain an on-chip 2.5 V reference.
fault condition such as a shorted output. Temperature readback
The reference is powered down by default and is enabled by
is enabled by setting Bit D8 in the ADC sequence register to 1
setting Bit D9 in the power-down register to 1 (see Table 43).
(see Table 28). The temperature result is then added to the ADC
When the on-chip reference is powered up, the reference voltage
sequence. The temperature result has an address of 0b1000; take
appears on the VREF pin and may be used as a reference source
care that this result is not confused with the readback from
for other components. When the internal reference is used, it is
DAC0. The temperature conversion takes 5 µs with the ADC
recommended to decouple the internal reference to GND using
buffer enabled and 20 µs when the buffer is disabled. Calculate
a 100 nF capacitor. It is recommended that the internal
the temperature by using the following formulae:
reference be buffered before using it elsewhere in the system.
When the reference is powered down, an external reference For ADC gain = 1,
must be connected to the VREF pin. Suitable external reference ADC Code – 820
sources for the AD5592R/AD5592R-1 include the AD780, Temperature(° C) = 25 +
2.654
AD1582, ADR431, REF193, and ADR391.
For ADC gain = 2,
ADC Code – 410
Temperature(° C) = 25 +
2.654
The range of codes returned by the ADC when reading from
the temperature indicator is approximately 645 to 1035,
corresponding to a temperature between −40°C to +105°C.
The accuracy of the temperature indicator, averaged over five
samples, is typically 3°C.

Rev. D | Page 25 of 42
AD5592R Data Sheet

SERIAL INTERFACE
The AD5592R/AD5592R-1 have a serial interface (SYNC, SCLK, WRITE MODE
SDI, and SDO), which is compatible with SPI standards, as well Figure 4 shows the read and write timing for the AD5592R/
as with most DSPs. The input shift register is 16 bits wide (see AD5592R-1. A write sequence begins by bringing the SYNC
Table 13). The MSB (D15) determines what type of write function line low. Data on SDI is clocked into the 16-bit shift register on
is required. When D15 is 0, a write to the control register is the falling edge of SCLK. After the 16th falling clock edge, the last
selected. The control register address is selected by D14 to D11.
data bit is clocked in. SYNC is brought high, and the programmed
D10 and D9 are reserved and are 0s. D8 to D0 set the data that is
function is executed (that is, a change in a DAC input register
written to the selected control register. When D15 is 1, data is
or a change in a control register). SYNC must be brought high
written to a DAC channel (assuming that channel has been set to
for a minimum of 20 ns before the next write. All interface pins
be a DAC). D14 to D12 select which DAC is addressed. D11 to D0
must be operated close to the VDD or VLOGIC rails to minimize
is the 12-bit data loaded to the selected DAC, with D11 being the
power consumption in the digital input buffers.
MSB of the DAC data. Table 14 shows the control register map for
the AD5592R/AD5592R-1. The register map allows the operation READ MODE
of each of the I/Ox pins to be configured. ADCs can be selected The AD5592R/AD5592R-1 allow data readback from the ADCs
for inclusion in sampling sequences. DACs can be updated and control registers via the serial interface. ADC conversions
individually or simultaneously (see the LDAC Mode Operation are automatically clocked out on the serial interface as part of a
section). GPIO settings are also controlled via the register map. sequence or as a single ADC conversion. Reading from a register
POWER-UP TIME first requires a write to the readback and LDAC mode register
to select the register to read back. The contents of the selected
When power is applied to the AD5592R/AD5592R-1, the
register are clocked out on the next 16 SCLKs following a falling
power-on reset block begins to configure the device and to load
edge of SYNC. Note that due to timing requirements of t10 (25 ns),
the registers with their default values. The configuration process
takes 250 µs; do not write to any of the registers during this time. the maximum speed of the SPI interface during a read operation
must not exceed 20 MHz.
Table 13. Input Shift Register Format
MSB LSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0 Control register address 0 0 Control register data
1 DAC address 12-bit DAC data

Table 14. Control Register Map

MSB Address Default
(D15) (D14 to D11) Name Description Value
0 0000 NOP No operation 0x000
0 0001 DAC readback Selects and enables DAC readback 0x000
0 0010 ADC sequence register Selects ADCs for conversion 0x000
0 0011 General-purpose control register DAC and ADC control register 0x000
0 0100 ADC pin configuration Selects which pins are ADC inputs 0x000
0 0101 DAC pin configuration Selects which pins are DAC outputs 0x000
0 0110 Pull-down configuration Selects which pins have a 85 kΩ pull-down resistor to GND 0x0FF
0 0111 Readback and LDAC mode Selects the operation of the Load DAC (LDAC) function and/or 0x000
which configuration register is read back
0 1000 GPIO write configuration 1 Selects which pins are general-purpose outputs 0x000
0 1001 GPIO write data Writes data to the general-purpose outputs 0x000
0 1010 GPIO read configuration Selects which pins are general-purpose inputs 0x000
0 1011 Power-down/reference control Powers down DACs and enables/disables the reference 0x000
0 1100 GPIO open-drain configuration Selects open-drain or push/pull for general-purpose outputs 0x000
0 1101 Three-state configuration Selects which pins are three-state 0x000
0 1110 Reserved Reserved
0 1111 Software reset Resets the AD5592R/AD5592R-1 0x000
1 XXX 2 DAC write Writes to addressed DAC register 0x000
1
This register is also used to set I/O7 as a BUSY output.
2
D14 to D11 is the DAC register address (see Table 13).

Rev. D | Page 26 of 42
Data Sheet AD5592R
CONFIGURING THE AD5592R/AD5592R-1 to this rule are that an I/Ox pin can be set as both a DAC and an
ADC or as a digital input and output. When an I/Ox pin is
The AD5592R/AD5592R-1 I/Ox pins are configured by writing configured as a DAC and ADC, its primary function is as a
to a series of configuration registers. The control registers are DAC, and the ADC can measure the voltage being provided by
accessed when the MSB of a serial write is 0, as shown in the DAC. This feature can monitor the output voltage to detect
Table 13. The control register map for the AD5592R/AD5592R-1 short circuits or overload conditions.
is shown in Table 14. At power-up, the I/Ox pins are configured
as 85 kΩ pull-down resistors connected to GND. When a pin is configured as both a general-purpose input and
output, the primary function is as an output pin. This configuration
The input/output channels of the AD5592R/AD5592R-1 can be allows the status of the output pin to be determined by reading the
configured to operate as DAC outputs, ADC inputs, digital outputs, GPIO register. Figure 40 shows a typical configuration example
digital inputs, three-state, or connected to GND with 85 kΩ where I/O0 and I/O1 are configured as ADCs, I/O2 and I/O3 are
pull-down resistors. When configured as digital outputs, the configured as DACs, I/O4 is a general-purpose output pin, I/O5
I/Ox pins have the additional option of being configured as is a general-purpose input pin, and I/O6 and I/O7 are three-state.
push/pull or open-drain. The input/output channels are configured
by writing to the appropriate configuration registers, as shown in The general-purpose control register also contains other
Table 15 and Table 16. To assign a particular function to an functions associated with the DAC and ADC, such as the lock
input/output channel, the user writes to the appropriate register configuration bit. When the lock configuration bit is set to 1,
and sets the corresponding bit to 1. For example, setting Bit D0 any writes to the pin configuration registers are ignored, thus
in the DAC configuration register to 1 configures I/O0 as a preventing the function of the I/Ox pins from being changed.
DAC (see Table 20). The I/Ox pins can be reconfigured at any time when the AD5592R/
In the event that the bit for an input/output channel is set in AD5592R-1 is in an idle state, that is, no ADC conversions are
multiple configuration registers, the input/output channel takes taking place and no registers are being read back. The lock
the function dictated by the last write operation. The exceptions configuration bit must also be 0.

Table 15. I/Ox Pin Configuration Registers

MSB LSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0 Register address Reserved IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0

Table 16. Bit Descriptions for the I/Ox Pin Configuration Registers
Bit(s) Bit Name Description
D15 MSB Set this bit to 0.
D14 to D11 Register address Selects which pin configuration register is addressed.
0100: ADC pin configuration.
0101: DAC pin configuration.
0110: pull-down configuration. (Default condition at power-up.)
1000: GPIO write configuration.
1010: GPIO read configuration.
1100: GPIO open-drain configuration.
1101: three-state configuration.
D10 to D8 Reserved Reserved. Set these bits to 0.
D7 to D0 IO7 to IO0 Enable register function on selected I/Ox pin.
0: no function selected.
1: set the selected I/Ox pin to the register function.
CONFIGURE CONFIGURE
SYNC I/O0 AND I/O1 AS ADCS I/O2 AND I/O3 AS DACS

SDI 0b0010 0000 0000 00 11 0b0010 1000 0000 1100

CONFIGURE CONFIGURE
SYNC I/O4 AS GPO I/O5 AS GPI

SDI 0b0100 0000 0001 0000 0b0101 0100 0010 0000

CONFIGURE I/O6 AND I/O7

SYNC AS THREE-STATE PINS
12506-205

SDI 0b0110 1000 1100 0000

Figure 40. Typical Configuration Example

Rev. D | Page 27 of 42
AD5592R Data Sheet
GENERAL-PURPOSE CONTROL REGISTER The general-purpose control register also enables/disables the
ADC buffer and precharge function (see the ADC Section for
The general-purpose control register enables or disables certain more details). The register can also be used to lock the I/Ox pin
functions associated with the DAC, ADC, and I/Ox pin configuration to prevent accidental change. When Bit D7 is set
configuration (see Table 17 and Table 18). The general-purpose to 1, writes to the configuration registers are ignored.
control register sets the gain of the DAC and ADC. Bit D5 sets
the input range for the ADC, and Bit D4 sets the output range
of the DAC.

Table 17. General-Purpose Control Register

MSB LSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0 Register address Reserved ADC buffer ADC buffer Lock All ADC DAC Reserved
precharge enable DACs range range

Table 18. Bit Descriptions for the General-Purpose Control Register

Bit(s) Bit Name Description
D15 MSB Set this bit to 0.
D14 to D11 Register address Set these bits to 0b0011.
D10 Reserved Reserved. Set this bit to 0.
D9 ADC buffer precharge ADC buffer precharge.
0: ADC buffer is not used to precharge the ADC. If the ADC buffer is enabled, it is always powered
up (default).
1: ADC buffer is used to precharge the ADC. If the ADC buffer is enabled, it is powered up while the
conversion takes place and then powered down until the next conversion takes place.
D8 ADC buffer enable ADC buffer enable.
0: ADC buffer is disabled (default).
1: ADC buffer is enabled.
D7 Lock Lock configuration.
0: the contents of the I/Ox pin configuration registers can be changed (default).
1: the contents of the I/Ox pin configuration registers cannot be changed.
D6 All DACs Write all DACs.
0: for future DAC writes, the DAC address bits determine which DAC is written to (default).
1: for future DAC writes, the DAC address bits are ignored, and all channels configured as DACs are
updated with the same data.
D5 ADC range ADC input range select.
0: ADC gain is 0 V to VREF (default).
1: ADC gain is 0 V to 2 × VREF.
D4 DAC range DAC output range select.
0: DAC output range is 0 V to VREF (default).
1: DAC output range is 0 V to 2 × VREF.
D3 to D0 Reserved Reserved. Set these bits to 0.

Rev. D | Page 28 of 42
Data Sheet AD5592R
DAC WRITE OPERATION LDAC Mode Operation
To set a pin as a DAC, set the appropriate bit in the DAC pin When the LDAC mode bits (D1 and D0) are 00 respectively,
configuration register to 1 (see Table 19 and Table 20). For new data is automatically transferred from the input register to
example, setting Bit 0 to Bit 1 enables I/O0 as a DAC output. the DAC register, and the analog output updates. When the
Data is written to a DAC when the MSB (D15) of the serial LDAC mode bits are 01, data remains in the input register. This
write is 1. D14, D13, and D12 determine which DAC is LDAC mode allows writes to input registers without affecting
addressed, and D11 to D0 contain the 12-bit data to be written the analog outputs. When the input registers have been loaded
to the DAC, as shown in Table 21 and Table 22. Data is written with the desired values, setting the LDAC mode bits to 10 transfers
to the selected DAC input register. Data written to the input the values in the input registers to the DAC registers, and the
register can be automatically copied to the DAC register, if analog outputs update simultaneously. The LDAC mode bits
required. Data is transferred to the DAC register based on the then revert back to 01, assuming their previous setting was 01.
setting of the LDAC mode register (see Table 45 and Table 46). See Table 45 and Table 46.

Table 19. DAC Pin Configuration Register

MSB LSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0 Register address Reserved DAC7 DAC6 DAC5 DAC4 DAC3 DAC2 DAC1 DAC0

Table 20. Bit Descriptions for the DAC Pin Configuration Register
Bit(s) Bit Name Description
D15 MSB Set this bit to 0.
D14 to D11 Register address Set these bits to 0b0101.
D10 to D8 Reserved Reserved. Set these bits to 0.
D7 to D0 DAC7 to DAC0 Select I/Ox pins as DAC outputs.
1: I/Ox is a DAC output.
0: I/Ox function is determined by the pin configuration registers (default).

Table 21. DAC Write Register

MSB LSB
D15 D14 D13 D12 D11 (MSB) D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
1 DAC address 12-bit DAC data

Table 22. Bit Descriptions for the DAC Data Register

Bit(s) Bit Name Description
D15 MSB Set this bit to 1.
D14 to D12 DAC address Bit D14 to Bit D12 select the DAC register to which the data in D11 to D0 is loaded.
000: DAC0
001: DAC1
010: DAC2
011: DAC3
100: DAC4
101: DAC5
110: DAC6
111: DAC7
D11 to D0 12-bit DAC data 12-bit DAC data.

Rev. D | Page 29 of 42
AD5592R Data Sheet
DAC READBACK This is achieved by writing to the DAC read back register (shown
The input register of each DAC can be read back via the SPI in Table 23 and Table 24). Set the D4 and D3 bits to 1 to enable
interface. Reading back the DAC register value can be used to the readback function. The D2 to D0 bits select which DAC
confirm that the data was received correctly before writing to data is required. The DAC data is clocked out of the AD5592R/
the LDAC register, or to check what value was last loaded to a AD5592R-1 on the subsequent SPI operation. Figure 41 shows
DAC. Data can only be read back from a DAC when there is no an example of setting I/O3, configured as a DAC, to midscale.
ADC conversion sequence taking place. The input data is then read back. D14 to D12 contain the
address of the DAC register being read back, and D15 is 1.
To read back a DAC input register, it is first necessary to enable
the readback function and select which DAC register is required.

Table 23. DAC Readback Register

MSB LSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0 Register address Reserved Enable DAC readback DAC channel

Table 24. Bit Descriptions for the DAC Readback Register

Bit(s) Bit Name Description
D15 MSB Set this bit to 0.
D14 to D11 Register address Set these bits to 0b0001.
D10 to D5 Reserved Reserved. Set these bits to 0.
D4 and D3 Enable DAC readback Enable readback of the DAC input register.
11: readback enabled.
00: readback disabled (default).
D2 to D0 DAC channel Select DAC channel.
000: DAC0
001: DAC1
…
110: DAC6
111: DAC7

SET I/O3 (DAC) TO SELECT I/O3 (DAC)

SYNC MIDSCALE FOR READBACK

SDI 0b1011 1000 0000 0000 0b0000 1000 0001 10 11

SYNC NOP

SDI 0b0000 0000 0000 0000

I/O3 (DAC) DATA

D15 = 1
12506-206

D14 TO D12 = DAC ADDRESS

D11 TO D0 = DAC DATA

Figure 41. DAC Readback Operation

Rev. D | Page 30 of 42
Data Sheet AD5592R
ADC OPERATION order on successive SYNC falling edges. Once all the selected
To set a pin as an ADC, set the appropriate bit in the ADC pin channels in the control register are converted, the ADC repeats
configuration register to 1 (see Table 25 and Table 26). For example, the sequence if the REP bit is set. If the REP bit is clear, the ADC
setting Bit 0 to Bit 1 enables I/O0 as an ADC input. The ADC goes three-state. Figure 42 to Figure 45 show typical ADC modes of
channels of the AD5592R/AD5592R-1 operate as a traditional operation. I/O7 can be configured as a BUSY output pin to indicate
multichannel ADC, where each serial transfer selects the next when a conversion result is available. BUSY goes low while a
channel for conversion. Writing to the ADC sequence register conversion takes place and goes high when the conversion result is
(see Table 27 and Table 28) selects the ADC channels to be available. The conversion result is clocked out on the SDO pin
included in the sequence, and the REP bit determines if the on the following read/write operation. For an ADC conversion,
sequence is repeated. The SYNC signal is used to frame the D15 is 0, D14 to D12 contain the ADC address, and D11 to D0
write to the converter on the SDI pin. The data that appears on contain the 12-bit conversion result, as shown in Table 29.
the SDO pin during the initial write to the ADC sequence register Changing an ADC Sequence
is invalid. When the sequence register is written to, the ADC The channels included in an ADC sequence can be changed by first
begins to track the first channel in the sequence. Tracking takes
stopping an existing conversion sequence (see Figure 46). The
500 ns; do not initiate a conversion until this time has passed.
ADC conversion sequence is stopped by clearing the REP, TEMP,
The next SYNC falling edge initiates a conversion on the selected and ADC7 to ADC0 bits in the ADC sequence register to 0.
channel. The subsequent SYNC falling edge begins clocking out
As the command to stop the sequence is written, an ADC
the ADC result and also initiates the next conversion. The ADC
conversion is also taking place. This conversion must finish
operates with one cycle latency, thus the conversion result
before a new sequence can be written to the ADC sequence
corresponding to each conversion is available one serial read
register. Allow a minimum of 2 µs between starting the write to
cycle after the cycle in which the conversion was initiated.
end the current sequence and starting the write to select a new
If more than one channel is selected in the ADC sequence register, sequence. After selecting the new sequence, allow an ADC track
the ADC converts all selected channels sequentially in ascending time of 500 ns before initiating the next conversion.

Table 25. ADC Pin Configuration Register

MSB LSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0 Register address Reserved ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0

Table 26. Bit Descriptions for the ADC Pin Configuration Register
Bit(s) Bit Name Description
D15 MSB Set this bit to 0.
D14 to D11 Register address Set these bits to 0b0100.
D10 to D8 Reserved Reserved. Set these bits to 0.
D7 to D0 ADC7 to ADC0 Select I/Ox pins as ADC inputs.
1: I/Ox is an ADC input.
0: I/Ox function is determined by the pin configuration registers (default).

Rev. D | Page 31 of 42
AD5592R Data Sheet
Table 27. ADC Sequence Register
MSB LSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0 Register address Reserved REP TEMP ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0

Table 28. Bit Descriptions for the ADC Sequence Register

Bit(s) Bit Name Description
D15 MSB Set this bit to 0.
D14 to D11 Register address Set these bits to 0b0010.
D10 Reserved Reserved. Set these bits to 0.
D9 REP ADC sequence repetition.
0: sequence repetition disabled (default).
1: sequence repetition enabled.
D8 TEMP Include temperature indicator in ADC sequence.
0: disable temperature indicator readback (default).
1: enable temperature indicator readback.
D7 to D0 ADC7 to ADC0 Include ADC channels in conversion sequence.
0: the selected ADC channel is not included in the conversion sequence.
1: include the selected ADC channel in the conversion sequence.

Table 29. ADC Conversion Result

MSB LSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0 ADC address1 12-bit ADC result
1
The ADC addresses are as follows: 000 = ADC0 … 111 = ADC7.

CONVERSION
STARTS ON
CHANNEL 1

SYNC
1 12 16 1 16 1 16 1 16
SCLK

DATA WRITTEN TO SEQUENCE NOP, DAC, OR CONTROL NOP, DAC, OR CONTROL NOP, DAC, OR CONTROL
SDI REGISTER CHANNEL 1 SELECTED REGISTER WRITE REGISTER WRITE REGISTER WRITE

12506-207
INVALID DATA INVALID DATA CONVERSION RESULT
SDO FOR CHANNEL 1

Figure 42. Single-Channel ADC Conversion Sequence, No Repeat

CONVERSION NEW CONVERSION

STARTS ON STARTS ON
CHANNEL 1 CHANNEL 1

SYNC
1 12 16 1 16 1 16 1 16
SCLK

DATA WRITTEN TO SEQUENCE NOP, DAC, OR CONTROL NOP, DAC, OR CONTROL NOP, DAC, OR CONTROL
SDI REGISTER CHANNEL 1 SELECTED REGISTER WRITE REGISTER WRITE REGISTER WRITE
12506-208

INVALID DATA INVALID DATA CONVERSION RESULT NEW CONVERSION RESULT

SDO FOR CHANNEL 1 FOR CHANNEL 1

Figure 43. Single-Channel, Repeating, ADC Conversion Sequence

Rev. D | Page 32 of 42
Data Sheet AD5592R
CONVERSION CONVERSION
STARTS ON STARTS ON CHANNEL 2
CHANNEL 1

SYNC
1 12 16 1 16 1 16
SCLK

WRITE TO SEQUENCE NOP, DAC, OR CONTROL NOP, DAC, OR CONTROL

SDI REGISTER CH 1 AND CH 2 SELECTED REGISTER WRITE REGISTER WRITE

SDO INVALID DATA INVALID DATA CONVERSION RESULT

FOR CHANNEL 1

SYNC
1 16 1 16
SCLK

NOP, DAC, OR CONTROL NOP, DAC, OR CONTROL

SDI REGISTER WRITE REGISTER WRITE

12506-209
CONVERSION RESULT
SDO FOR CHANNEL 2

Figure 44. Multichannel ADC Conversion Sequence, No Repeat

CONVERSION CONVERSION
STARTS ON STARTS ON CHANNEL 2
CHANNEL 1

SYNC
1 12 16 1 16 1 16
SCLK

WRITE TO SEQUENCE NOP, DAC, OR CONTROL NOP, DAC, OR CONTROL

SDI REGISTER CH 1 AND CH 2 SELECTED REGISTER WRITE REGISTER WRITE

SDO INVALID DATA INVALID DATA CONVERSION RESULT

FOR CHANNEL 1

NEW CONVERSION
STARTS ON
CHANNEL 1

SYNC
1 16 1 16
SCLK

NOP, DAC, OR CONTROL NOP, DAC, OR CONTROL

SDI REGISTER WRITE REGISTER WRITE

12506-210
CONVERSION RESULT NEW CONVERSION RESULT
SDO FOR CHANNEL 2 FOR CHANNEL 1

Figure 45. Multichannel, Repeating, ADC Conversion Sequence

Rev. D | Page 33 of 42
AD5592R Data Sheet
CONVERSION CONVERSION
STARTS ON STARTS ON CHANNE L 2
CHANNE L 1

SYNC
1 12 16 1 16 1 16
SCLK

WRITE TO SEQUENCE NOP, DAC, OR CONTROL NOP, DAC, OR CONTROL

SDI REGISTER CH 1 AND CH 2 SELECTED REGISTER WRITE REGISTER WRITE

SDO INVALID DATA INVALID DATA CONVERSION RESULT

FOR CHANNEL 1

CONVERSION CONVERSION CONVERSION

STARTS ON STARTS ON STARTS ON
CHANNEL 1 CHANNEL 2 CHANNEL 1

SYNC
1 12 16 1 16 1 16
SCLK

NOP, DAC, OR CONTROL NOP, DAC, OR CONTROL WRITE TO SEQUENCE

SDI REGISTER WRITE REGISTER WRITE REGISTER TO END SEQUENCE

CONVERSION RESULT CONVERSION RESULT CONVERSION RESULT

SDO FOR CHANNEL 2 FOR CHANNEL 1 FOR CHANNEL 2

CONVERSION CONVERSION
STARTS ON STARTS ON
CHANNEL 4 CHANNEL 5

SYNC
1 12 16 1 16 1 16
SCLK

WRITE TO SEQUENCE NOP, DAC OR CONTROL NOP, DAC, OR CONTROL

SDI REGISTER CH 4 AND CH 5 SELECTED REGISTER WRITE REGISTER WRITE

CONVERSION RESULT
SDO INVALID DATA INVALID DATA
FOR CHANNEL 4

CONVERSION CONVERSION
STARTS ON STARTS ON
CHANNEL 4 CHANNEL 5

SYNC
1 16 1 16 1 16
SCLK

NOP, DAC, OR CONTROL NOP, DAC, OR CONTROL NOP, DAC, OR CONTROL

SDI REGISTER WRITE REGISTER WRITE REGISTER WRITE

12506-211
SDO CONVERSION RESULT CONVERSION RESULT CONVERSION RESULT
FOR CHANNEL 5 FOR CHANNEL 4 FOR CHANNEL 5

Figure 46. Changing a Multichannel, Repeating, ADC Conversion Sequence

SET I/O4 TO I/O7 SELECT THE GPIO INPUT SELECT THE GPIO INPUT
SYNC AS INPUTS REGISTER FOR READBACK REGISTER FOR READBACK

SDI 0b0101 0000 1111 0000 0b0101 0100 1111 0000 0b0101 0100 0011 0000

SDO I/O7 to I/O4 PINS STATES

DAC WRITE
SYNC SET I/O3 TO MIDSCALE

SDI 0b1011 1000 0000 0000

12506-212

SDO I/O5 AND I/04 PINS STATES

Figure 47. Configuring and Reading General-Purpose Input Pins

Rev. D | Page 34 of 42
Data Sheet AD5592R
GPIO OPERATION the open-drain configuration allows for one pin to pull down
Each of the I/Ox pins of the AD5592R/AD5592R-1 can operate the others pins. This method is commonly used where multiple
as a general-purpose, digital input or output pin. The function pins are used to trigger an alarm or an interrupt pin.
of the pins is determined by writing to the appropriate bit in the To change the state of the I/Ox pins, a write to the GPIO write data
GPIO read configuration and GPIO write configuration registers. register is required. Setting a bit to 1 gives a Logic 1 on the selected
Setting Pins as Outputs output. Clearing a bit to 0 gives a Logic 0 on the selected output.

To set a pin as a general-purpose output, set the appropriate bit Setting Pins as Inputs
in the GPIO write configuration register to 1 (see Table 30 and To set a pin as a general-purpose input, set the appropriate bit
Table 31). For example, setting Bit 0 to Bit 1 enables I/O0 as a in the GPIO read configuration register to 1 (see Table 36 and
general-purpose output. The state of the output pin is controlled by Table 37). For example, setting Bit 0 to Bit 1 enables I/O0 as a
setting or clearing the bits in the GPIO write data register (see general-purpose input. To read the state of the general-purpose
Table 34). A data bit is ignored if it is written to a location that inputs, write to the GPIO read and configuration register to set
is not configured as an output. Bit D10 to 1 and also any of Bit D7 to Bit D0 that correspond to
The outputs can be independently configured as push/pull or a general-purpose input pin. The following SPI operation clocks
open-drain outputs. When in a push/pull configuration, the out the state of any pins set as general-purpose inputs. Figure 47
output is driven to VDD or GND, as determined by the data in shows an example where I/O4 to I/O7 are set as general-purpose
the GPIO write data register. To set a pin as an open-drain output, inputs. I/O3 is assumed to be a DAC. To read the status of I/O7
set the appropriate bit in the GPIO open-drain configuration to I/O4, Bit D10 and Bit D7 to Bit D4 are set to 1. To read the
register to 1 (see Table 32 and Table 33). When in an open-drain status of I/O5 and I/O4, only Bit D10, Bit D5, and Bit D4 need
configuration, the output is driven to GND when a data bit in to be set to 1. The status of I/O7 and I/O6 are not read, and Bit D7
the GPIO write data register sets the pin low. When the pin is and Bit D6 are read as 0. Figure 47 also has a write to a DAC to
set high, the output is not driven and must be pulled high by an show that other operations can be included when reading the
external resistor. Open-drain configuration allows for multiple status of the general-purpose pins.
output pins to be tied together. If all the pins are normally high,

Table 30. GPIO Write Configuration Register

MSB LSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0 Register address Reserved Enable BUSY GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0

Table 31. Bit Descriptions for the GPIO Write Configuration Register
Bit(s) Bit Name Description
D15 MSB Set this bit to 0.
D14 to D11 Register address Set these bits to 0b1000.
D10 to D9 Reserved Reserved. Set this bit to 0.
D8 Enable BUSY Enable the I/O7 pin as BUSY.
0: Pin I/O7 is not configured as BUSY.
1: Pin I/O7 is configured as BUSY. D7 must also be set to 1 to enable the I/O7 pin as an output.
D7 to D0 GPIO7 to GPIO0 Select I/Ox pins as GPIO outputs.
1: I/Ox is a general-purpose output pin.
0: I/Ox function is determined by the pin configuration registers (default).

Rev. D | Page 35 of 42
AD5592R Data Sheet
Table 32.GPIO Open-Drain Configuration Register
MSB LSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0 Register address Reserved Open Open Open Open Open Open Open Open
Drain 7 Drain 6 Drain 5 Drain 4 Drain 3 Drain 2 Drain 1 Drain 0

Table 33. Bit Descriptions for the GPIO Open-Drain Configuration Register
Bit(s) Bit Name Description
D15 MSB Set this bit to 0.
D14 to D11 Register address Set these bits to 0b1100.
D10 to D8 Reserved Reserved. Set these bits to 0.
D7 to D0 Open Drain 7 to Open Drain 0 Set output pins as open-drain. The pins must also be set as digital output pins. See Table 31.
1: I/Ox is an open-drain output pin.
0: I/Ox is a push/pull output pin (default).

Table 34. GPIO Write Data Register

MSB LSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0 Register address Reserved GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0

Table 35. Bit Descriptions for the GPIO Write Data Register
Bit(s) Bit Name Description
D15 MSB Set this bit to 0.
D14 to D11 Register address Set these bits to 0b1001.
D10 to D8 Reserved Reserved. Set these bits to 0.
D7 to D0 GPIO7 to GPIO0 Set state of output pins.
1: I/Ox is a Logic 1.
0: I/Ox is a Logic 0.

Table 36. GPIO Read Configuration Register

MSB LSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0 Register address Enable readback Reserved GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0

Table 37. Bit Descriptions for the GPIO Read Configuration Register
Bit(s) Bit Name Description
D15 MSB Set this bit to 0.
D14 to D11 Register address Set these bits to 0b1010.
D10 Enable readback Enable GPIO readback.
1: the next SPI operation clocks out the state of the GPIO pins.
0: Bit D7 to Bit D0 determine which pins are set as general-purpose inputs.
D9 to D8 Reserved Reserved. Set these bits to 0.
D7 to D0 GPIO7 to GPIO0 Set I/Ox pins as GPIO inputs.
1: I/Ox is a general-purpose input pin.
0: I/Ox function is determined by the pin configuration registers (default).

Rev. D | Page 36 of 42
Data Sheet AD5592R
THREE-STATE PINS 85 kΩ PULL-DOWN RESISTOR PINS
The I/Ox pins can be set to three-state by writing to the three- The I/Ox pins can be connected to GND via a pull-down
state configuration register, as shown in Table 38 and Table 39. resistor (85 kΩ) by setting the appropriate bits in the pull-down
configuration register, as shown in Table 40 and Table 41.

Table 38. Three-State Configuration Register

MSB LSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0 Register address Reserved TSO7 TSO6 TSO5 TSO4 TSO3 TSO2 TSO1 TSO

Table 39. Bit Descriptions for the Three-State Configuration Register

Bit(s) Bit Name Description
D15 MSB Set this bit to 0.
D14 to D11 Register address Set these bits to 0b1101.
D10 to D8 Reserved Reserved. Set these bits to 0.
D7 to D0 TSO7 to TSO0 Set I/Ox pins as three-state outputs.
1: I/Ox is a three-state output pin.
0: I/Ox function is determined by the pin configuration registers (default).

Table 40. Pull-Down Configuration Register

MSB LSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0 Register address Reserved Pull Pull Pull Pull Pull Pull Pull Pull
Down 7 Down 6 Down 5 Down 4 Down 3 Down 2 Down 1 Down 0

Table 41. Bit Descriptions for the Pull-Down Configuration Register

Bit(s) Bit Name Description
D15 MSB Set this bit to 0.
D14 to D11 Register address Set these bits to 0b0110.
D10 to D8 Reserved Reserved. Set these bits to 0.
D7 to D0 Pull Down 7 to Pull Down 0 Set I/Ox pins as weak pull-down outputs.
1: I/Ox is connected to GND via an 85 kΩ pull-down resistor.
0: I/Ox function is determined by the pin configuration registers (default).

Rev. D | Page 37 of 42
AD5592R Data Sheet
POWER-DOWN MODE buffer are powered down by default and are enabled by setting
The AD5592R/AD5592R-1 have a power configuration register the EN_REF bit in the power-down register. The internal
to reduce the power consumption when certain functions are reference voltage then appears at the VREF pin.
not needed. The power-down register allows any channels set as There is no dedicated power-down function for the ADC, but
DACs to be individually placed in a power-down state. When in the ADC is automatically powered down if none of the I/Ox
a power-down state, the DAC outputs are three-state. When a pins are selected as ADCs. The PD_ALL bit powers down all the
DAC channel is put back into normal mode, the DAC output DACs, the reference and its buffer, and the ADC simultaneously.
returns to its previous value. The internal reference and its Table 42 and Table 43 show the power-down register.

Table 42. Power-Down/Reference Control Register

MSB LSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0 Register address PD_ALL EN_REF Reserved PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

Table 43. Bit Descriptions for the Power-Down/Reference Control Register

Bit(s) Bit Name Description
D15 MSB Set this bit to 0.
D14 to D11 Register address Set these bits to 0b1011.
D10 PD_ALL Power down DACs and internal reference.
0: the reference and DACs power-down states are determined by D9 and D7 to D0 (default).
1: the reference, DACs and ADC are powered down.
D9 EN_REF Enable internal reference.
0: the reference and its buffer are powered down (default). Set this bit if an external reference is used.
1: the reference and its buffer are powered up. The reference is available on the VREF pin.
D8 Reserved Reserved. Set this bit to 0.
D7 to D0 PD7 to PD0 Power down DACs.
0: the channel is in normal operating mode (default).
1: the channel is powered down if it is configured as a DAC.

Rev. D | Page 38 of 42
Data Sheet AD5592R
RESET FUNCTION READBACK AND LDAC MODE REGISTER
The AD5592R/AD5592R-1 can be reset to their default conditions The values contained in the AD5592R/AD5592R-1 registers can
by writing to the reset register, as shown in Table 44. This write be read back to ensure that the registers are correctly set up. The
resets all registers to their default values and reconfigures the register readback is initiated by writing to the readback and
I/Ox pins to their default values (85 kΩ pull-down resistor to LDAC mode register with Bit D6 set to 1. Bit D5 to Bit D2 select
GND). The reset function takes 250 µs maximum; do not write which register is to be read back. The register data is clocked
new data to the AD5592R/AD5592R-1 during this time. The out of the AD5592R/AD5592R-1 on the next SPI transfer.
AD5592R has a RESET pin that performs the same function. Bit D1 to Bit D0 of the readback and LDAC mode register select
For normal operation, RESET is tied high. A falling edge the LDAC mode. The LDAC mode determines if data written to
on RESET triggers the reset function. a DAC input register is also transferred to the DAC register. See
the LDAC Mode Operation section for details of the LDAC
mode function.
Table 44. Software Reset
MSB LSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0 1 1 1 1 1 0 1 1 0 1 0 1 1 0 0
Control register write Write to reset register Reset the AD5592R/AD5592R-1

Table 45. Readback and LDAC Mode Register

MSB LSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0 Register address Reserved EN REG_READBACK LDAC mode

Table 46. Bit Descriptions for the Readback and LDAC Mode Register
Bit(s) Bit Name Description
D15 MSB Set this bit to 0.
D14 to D11 Register address Set these bits to 0b0111.
D10 to D7 Reserved Reserved. Set these bits to 0.
D6 EN Enable readback. Note that the LDAC mode bits are always used regardless of the EN bit.
1: Bit D5 to Bit D2 select which register is read back. Bit D6 automatically clears when the read is complete.
0: no readback is initiated.
D5 to D2 REG_READBACK If Bit D6 is 1, Bits D5 to Bit D2 determine which register is to be read back.
0000: NOP.
0001: DAC readback.
0010: ADC sequence.
0011: general-purpose configuration.
0100: ADC pin configuration.
0101: DAC pin configuration.
0110: pull-down configuration.
0111: LDAC configuration.
1000: GPIO write configuration.
1001: GPIO write data.
1010: GPIO read configuration.
1011: power-down and reference control.
1100: open-drain configuration.
1101: three-state pin configuration.
1110: reserved.
1111: software reset.
D1 to D0 LDAC mode Determines how data written to an input register of a DAC is handled.
00: data written to an input register is immediately copied to a DAC register, and the DAC output updates (default).
01: data written to an input register is not copied to a DAC register. The DAC output is not updated.
10: data in the input registers is copied to the corresponding DAC registers. When the data has been
transferred, the DAC outputs are updated simultaneously.
11: reserved.
Rev. D | Page 39 of 42
AD5592R Data Sheet
AD5592R/AD5592R-1 TO SPORT INTERFACE
APPLICATIONS INFORMATION
The Analog Devices ADSP-BF527 has two serial ports (SPORT).
MICROPROCESSOR INTERFACING Figure 49 shows how a SPORT interface can be used to control
Microprocessor interfacing to the AD5592R/AD5592R-1 is via a the AD5592R/AD5592R-1. The ADSP-BF527 has an SPI port
serial bus that uses a standard protocol compatible with DSPs and that can also be used. This method is the same as when using
microcontrollers. The communications channel requires a 4-wire the ADSP-BF531.
interface consisting of a clock signal, a data input signal, a data
output signal, and a synchronization signal. The devices require AD5592R/
AD5592R-1
a 16-bit data-word with data valid on the falling edge of SCLK.
AD5592R/AD5592R-1 TO SPI INTERFACE ADSP-BF527
SPORT_TFS SYNC
The SPI interface of the AD5592R/AD5592R-1 is designed to be
SPORT_RFS
easily connected to industry-standard DSPs and microcontrollers. SPORT_TSCK SCLK
Figure 48 shows the AD5592R/AD5592R-1 connected to the SPORT_RSCK
Analog Devices, Inc., ADSP-BF531 Blackfin® DSP. The Blackfin SPORT_DR SDO
SPORT_DT SDI
has an integrated SPI port that can be connected directly to the

12506-165
GPIO1 RESET
SPI pins of the AD5592R/AD5592R-1.
Figure 49. ADSP-BF527 SPORT Interface
AD5592R/
AD5592R-1 LAYOUT GUIDELINES
ADSP-BF531
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
SPISELx SYNC
SCK SCLK
the rated performance. The printed circuit board (PCB) on which
MOSI SDI the AD5592R or the AD5592R-1 is mounted must be designed
MISO SD0 so that the AD5592R/AD5592R-1 lie on the analog plane.
12506-164

PF8 RESET
The AD5592R/AD5592R-1 must have ample supply bypassing of
Figure 48. ADSP-BF531 SPI Interface 10 μF in parallel with 0.1 μF on each supply, located as close to
the package as possible, ideally right up against the device. The
10 μF capacitors are the tantalum bead type. The 0.1 μF capacitor
must have low effective series resistance (ESR) and low effective
series inductance (ESI). Ceramic capacitors, for example, provide
a low impedance path to ground at high frequencies to handle
transient currents due to internal logic switching.

Rev. D | Page 40 of 42
Data Sheet AD5592R

OUTLINE DIMENSIONS
5.10
5.00
4.90

16 9

4.50
6.40
4.40 BSC
4.30
1 8

PIN 1
1.20
MAX
0.15 0.20
0.05 0.09 0.75
0.30 8° 0.60
0.65 0.19 0° 0.45
BSC SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB

Figure 50. 16-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-16)
Dimensions shown in millimeters

3.10 0.30
3.00 SQ 0.25
PIN 1 2.90 0.20
INDICATOR
13 16
0.50
12 1
BSC

9 4

0.50 8 5
TOP VIEW BOTTOM VIEW
0.40
0.30
0.80
0.75
0.05 MAX
0.70
0.02 NOM
COPLANARITY
SEATING 0.08
PLANE 0.152 REF
09-03-2013-A
PKG-004132

COMPLIANT TO JEDEC STANDARDS MO-220-WEED.

Figure 51. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

3 mm × 3 mm Body, Very Very Thin Quad
(CP-16-32)
Dimensions shown in millimeters

Rev. D | Page 41 of 42
AD5592R Data Sheet
2.000
1.960 SQ
1.920
4 3 2 1

A
BALL A1
IDENTIFIER
1.50 B
REF
C

D
0.50
BSC
TOP VIEW BOTTOM VIEW
(BALL SIDE DOWN) (BALL SIDE UP)

0.640
0.595 SIDE VIEW
0.540
COPLANARITY
0.05

SEATING 0.340 0.270

PLANE 0.320 0.240

10-17-2012-B
0.300 0.210

Figure 52. 16-Ball Wafer Level Chip Scale Package [WLCSP]

(CB-16-3)
Dimensions shown in millimeters

ORDERING GUIDE
Model 1 Temperature Range Package Description Package Option Branding
AD5592RBCBZ-1-RL7 −40°C to +105°C 16-Ball Wafer Level Chip Scale Package [WLCSP] CB-16-3
AD5592RBCPZ-1-RL7 −40°C to +105°C 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-16-32 DMD
AD5592RBRUZ −40°C to +105°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
AD5592RBRUZ-RL7 −40°C to +105°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
AD5592RBCBZ-RL7 −40°C to +105°C 16-Ball Wafer Level Chip Scale Package [WLCSP] CB-16-3
AD5592RBCPZ-RL7 −40°C to +105°C 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-16-32 DMG
EVAL-AD5592R-1SDZ Evaluation Board
1
Z = RoHS Compliant Part.

©2014–2017 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D12506-0-8/17(D)

Rev. D | Page 42 of 42