IJISET - International Journal of Innovative Science, Engineering & Technology, Vol. 2 Issue 4, April 2015.

www.ijiset.com
ISSN 2348 – 7968

A Review on Challenges for MOSFET Scaling

Shivani Chopra1 and Subha Subramaniam2

1
Department of Electronics Engineering, Shah & Anchor Kutchhi Engineering College,
Mumbai, Maharashtra, India

Abstract performance is achieved by reducing the MOS transistor’s

This paper provides an overview of the issues faced by the dimensions. MOSFETs dimensions are going down from
downscaling of MOS devices. For retaining growth in device submicron to nanometer scale. However, the drastic
density, the scaling issues like the power supply and threshold dimension reduction will not always comply with device
voltage scaling, hot carrier degradation, gate oxide tunneling, performances and poses problems that are yet to be solved.
random doping fluctuation, high electric field, parasitic
resistance and capacitance, source to drain tunneling, short-
channel effect should be well understood. A possible way for the
2.1 Power supply and Threshold Voltage
microelectronics industry to keep up the high-density pace is to
shift from the traditional MOSFET based standards to one based The MOSFET channel down-scaling tends to involve
on nanostructures at the molecular level. proportional reduction in supply voltage to keep electric
Keywords: Scaling, Nanoelectronics, Short channel effect, field and active power within limits. However, the
Tunneling, Threshold Voltage threshold voltage cannot be scaled down much. This is
because the passive power (due to transistor off-state
leakage) constitutes a significant portion of the total power
1. Introduction dissipation in high performance CMOS products. The
major power consumed in this state is due to leakage
CMOS technology scaling has been a basic key for current through the device. Therefore, VT scaling has
continuous progress in silicon-based semiconductor slowed down to avoid dramatic increase in IOFF. To achieve
industry. Scaling is followed by Moore’s Law since few large drive current, the gate overdrive (VDD – VT) needs to
decades which provided simple rules for transistor design be significant and therefore VDD scaling also has to slow
to increase circuit density and speed. The improved circuit down, which results in increase active power density [3].
performance and density enable more complicated
functionality, since more transistors can be integrated on 2.2 High electric fields
one single chip. However, as device scaling continues for
the 21st century, it turns out that the historical growth, As mentioned above, the supply voltage cannot be reduced
doubled circuit density and increased performance in proportion to channel length, hence the scaling will
followed by Moore’s Law cannot be maintained only by increase the electric field strength across the gate oxide.
the conventional scaling theory. Increasing leakage current Carrier mobilities are degraded due to higher vertical
does not allow further reduction of threshold voltage, electric fields in MOSFET channel which in worst cases
which in turn prevents further supply voltage scaling for can cause breakdown of the barrier and hence higher
the speed improvement. Higher electric fields generated leakage currents which can cause damage to the device.
inside of the transistor worsen device reliability and
increase leakage currents. Moreover, the required high 2.3 Gate oxide tunneling
channel doping causes significant challenges such as
mobility degradation and random dopants induced Since the electron thermal voltage, kT/q, is a constant at
threshold voltage fluctuations [1]. room temperature, the ratio between operating voltage and
the thermal voltage shrinks with scaling down of
2. Significant problems in downscaling of MOS MOSFET. This leads to higher leakage currents stemming
devices from the thermal diffusion of electrons. With reduction in
channel lengths, an appropriate reduction in oxide
The development of MOSFET-based CMOS technology is thickness is also needed. The thin oxide films subject to
facing challenges in the further development aiming quantum mechanical tunneling, giving rise to gate leakage
higher device performances mainly low power current that increases exponentially as the oxide thickness
consumption and high ON-state current. The improved is scaled down. Further scaling can be realized by

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 IJISET - International Journal of Innovative Science, Engineering & Technology, Vol. 2 Issue 4, April 2015.
www.ijiset.com
ISSN 2348 – 7968
replacing the oxide gate dielectric with a high-permittivity Reduction of the wire width increases the resistance and
(high-k) gate dielectric. hence increases the delay. This reduces the speed and
hence device may not function much faster due to large
2.4 Parasitic resistances and capacitances interconnect delays. The purpose of scaling is not only to
increase the device density on chip but also to increase its
As transistor dimensions are reduced, parasitic resistances speed [6].
and capacitances both scale unfavorably with reduced
pitch. Therefore, influence of parasitic elements on on- 2.10 Short-channel effect
current increases significantly. These parasitic elements
will diminish the performance gain by transistor scaling. As the channel length becomes comparable to the source-
substrate or drain-substrate depletion depth, the total
2.5 Hot-carrier amount of depletion charge in the substrate decreases.
This results in reduction of threshold voltage [4].
When carriers possess high energies having effective
temperature greater than the lattice temperature, they are
said to be hot. These carriers are not in thermal 3. Conclusions
equilibrium with the lattice because they cannot transfer
their energies to the lattice atoms fast enough. They are As the device scaling is approaching its physical size
generated in inverted channel region when MOSFET is limitations, various researches have been actively carried
operating in linear or saturation mode. The main problems out to find an alternative way to continue Moore’s law.
which arise due to hot carriers are parasitic gate currents, The technology cycle is getting slow down due to
drain current degradation, decrease in transconductance, increasing power consumption, process variation, and
shift of threshold voltage with time. Using graded drain fabrication cost. Nowadays device scaling tradeoffs
profile reduces generation of hot carriers [4]. between performance and power consumption, therefore
technological innovations which can achieve high
2.6 Randomness of dopant distribution performance through very low power are required. If some
efforts are being made to maintain the advanced CMOS
The affect of randomness of dopant distribution on the technology, it cannot go beyond few decades. Hence
MOSFET characteristics becomes more extreme in small emerging devices should be considered in order to comply
devices, because precise position of the individual dopant with technology developments in the near and far future.
atoms cannot be managed. So, as the device dimensions
are reduced it becomes difficult to place the dopant atoms References
at exact and required positions. [1] Yong-Bin Kim, “Challenges for Nanoscale MOSFETs and
Emerging Nanoelectronics”, Trans. Electr. Electron. Mater.
10(1)21(2009): G.-D. Hong et al.
2.7 Source to drain tunneling [2] ITRS Roadmap 2010; www.itrs.net.
[3] Xin Sun, “Nanoscale Bulk MOSFET Design and Process
If the MOSFETs channel length between source and drain Technology for Reduced Variability”, Ph.D. thesis,
becomes small enough for electrons to tunnel through the Electrical Engineering and Computer Sciences, University
barrier without the gate bias, it can no longer be operated of California, Berkeley, 2010.
as a switch. Device scaling should be carried out with [4] V K Khanna, “Emerging trends in ultra-miniaturized
appropriate limits on dimensions for proper behavior [7]. CMOS (Complementary metal-oxide-semiconductor)
transistors, single-electron and molecular-scale devices: A
comparative analysis of high-performance computational
2.8 Heat dissipation nanoelectronics”, Journal of Scientific &Industrial
Research, Vol. 63, October 2004, pp 795-806.
MOSFETs release their energy in the form of heat in the [5] G. E. Moore, Electronics, Vol. 38, No. 8, April 19, 1965.
resistive parts. If this heat is not dissipated properly, hot [6] Tezaswi Raja, Vishwani D. Agarwal and Michael
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[7] Subha Subramaniam, R.N Awale and Sangeeta M. Joshi,

2.9 Interconnect delays “Drain Current Models for Single-Gate MOSFETs &
Undoped Symmetric & Assynetric Dopuble-Gate SOI
MOSFETs and Quantum Mechanical Effects”,

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 IJISET - International Journal of Innovative Science, Engineering & Technology, Vol. 2 Issue 4, April 2015.
www.ijiset.com
ISSN 2348 – 7968
International Journal of Engineering Science &
Technology, Vol. 5, No. 1, January 2013.

Shivani Chopra was born in Jammu district,

Jammu & Kashmir, India.She received her B.E.
degree in Electronics and Telecommunication
from Marathwada Mitra Mandal College of
Engineering affiliated to University of Pune in May
2013. She is currently pursuing M.E. degree in the
Department of Electronics, University of Mumbai,
India, duration 2013-2015.

Subha Subramaniam was born in Nagercoil,

Kanyakumari district, TamilNadu, India. She
received B.E degree in Electronics and
Communication Engineering from Govt. College of
Engineering (GCE), Tirunelveli affiliated to Anna
University in July 1998 and M.E degree in
Electronics Engineering from Thadomal Shahani
Engineering College (TSEC), Mumbai affiliated to
Mumbai University in Nov 2003. She is currently pursuing Ph.D in
Electronics Engineering from Veeramata Jijabai Technological Institute
(VJTI), Mumbai. Presently she is working as Associate professor,
Department of Electronics at Shah & Anchor Kutchhi Engineering
College (SAKEC), Mumbai. Her research interest is in the area of
Nanoelctronics.

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