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Addressing Modes

• Immediate
• Direct
• Indirect
• Register
Addressing Modes and
• Register Indirect
Formats
• Displacement (Indexed)
• Stack

Immediate Addressing Immediate Addressing Diagram

• Operand is part of instruction

• Operand = address field Instruction

• e.g. ADD 5 Opcode Operand

– Add 5 to contents of accumulator

– 5 is operand
• No memory reference to fetch data
• Fast
• Limited range

Direct Addressing Direct Addressing Diagram

• Address field contains address of operand Instruction

• Effective address (EA) = address field (A) Opcode Address A

Memory
• e.g. ADD A
– Add contents of cell A to accumulator
– Look in memory at address A for operand
• Single memory reference to access data
• No additional calculations to work out effective Operand

address
• Limited address space

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Indirect Addressing (1) Indirect Addressing (2)

• Memory cell pointed to by address field • Large address space

contains the address of (pointer to) the • 2n where n = word length
operand • May be nested, multilevel, cascaded
• EA = (A) – e.g. EA = (((A)))
– Look in A, find address (A) and look there for • Draw the diagram yourself
operand
• Multiple memory accesses to find operand
• e.g. ADD (A)
– Add contents of cell pointed to by contents of A to • Hence slower
accumulator

Indirect Addressing Diagram Register Addressing (1)

Instruction

Opcode Address A • Operand is held in register named in address

Memory filed
Pointer to operand • EA = R
• Limited number of registers
• Very small address field needed
Operand
– Shorter instructions
– Faster instruction fetch

Register Addressing (2) Register Addressing Diagram

• No memory access Instruction

• Very fast execution Opcode Register Address R
• Very limited address space Registers

• Multiple registers helps performance

– Requires good assembly programming or compiler
writing
– N.B. C programming Operand
• register int a;
• c.f. Direct addressing

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Register Indirect Addressing Register Indirect Addressing Diagram

• C.f. indirect addressing Instruction

• EA = (R) Opcode Register Address R

Memory
• Operand is in memory cell pointed to by
contents of register R Registers

• Large address space (2n)

• One fewer memory access than indirect Pointer to Operand Operand

addressing

Displacement Addressing Displacement Addressing Diagram

• EA = A + (R) Instruction

• Address field hold two values Opcode Register R Address A

Memory
– A = base value
– R = register that holds displacement Registers

– or vice versa

Pointer to Operand + Operand

Relative Addressing Base-Register Addressing

• A version of displacement addressing • A holds displacement

• R = Program counter, PC • R holds pointer to base address
• EA = A + (PC) • R may be explicit or implicit
• i.e. get operand from A cells from current • e.g. segment registers in 80x86
location pointed to by PC
• c.f locality of reference & cache usage

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Indexed Addressing Combinations

• A = base • Postindex
• R = displacement • EA = (A) + (R)
• EA = A + R
• Good for accessing arrays • Preindex
– EA = A + R • EA = (A+(R))
– R++

• (Draw the diagrams)

Stack Addressing x86 Addressing Modes

• Virtual or effective address is offset into segment

• Operand is (implicitly) on top of stack – Starting address plus offset gives linear address
• e.g. – This goes through page translation if paging enabled
• 12 addressing modes available
– ADD Pop top two items from stack – Immediate
and add – Register operand
– Displacement
– Base
– Base with displacement
– Scaled index with displacement
– Base with index and displacement
– Base scaled index with displacement
– Relative

ARM Addressing Modes

x86 Addressing Mode Calculation Load/Store

• Only instructions that reference memory

• Indirectly through base register plus offset
• Offset
– Offset added to or subtracted from base register contents to form the memory
address
• Preindex
– Memory address is formed as for offset addressing
– Memory address also written back to base register
– So base register value incremented or decremented by offset value
• Postindex
– Memory address is base register value
– Offset added or subtracted
Result written back to base register
• Base register acts as index register for preindex and postindex addressing
• Offset either immediate value in instruction or another register
• If register scaled register addressing available
– Offset register value scaled by shift operator
– Instruction specifies shift size

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ARM Data Processing Instruction Addressing

ARM
& Branch Instructions
Indexing
Methods
• Data Processing
– Register addressing
• Value in register operands may be scaled using a shift
operator
– Or mixture of register and immediate addressing
• Branch
– Immediate
– Instruction contains 24 bit value
– Shifted 2 bits left
• On word boundary
• Effective range +/-32MB from PC.

ARM Load/Store Multiple Addressing ARM Load/Store Multiple Addressing Diagram

• Load/store subset of general-purpose

registers
• 16-bit instruction field specifies list of
registers
• Sequential range of memory addresses
• Increment after, increment before, decrement
after, and decrement before
• Base register specifies main memory address
• Incrementing or decrementing starts before
or after first memory access

Instruction Formats Instruction Length

• Layout of bits in an instruction • Affected by and affects:

• Includes opcode – Memory size
• Includes (implicit or explicit) operand(s) – Memory organization
– Bus structure
• Usually more than one instruction format in
– CPU complexity
an instruction set
– CPU speed
• Trade off between powerful instruction
repertoire and saving space

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Allocation of Bits PDP-8 Instruction Format

• Number of addressing modes

• Number of operands
• Register versus memory
• Number of register sets
• Address range
• Address granularity

PDP-10 Instruction Format PDP-11 Instruction Format

VAX Instruction Examples x86 Instruction Format

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ARM Instruction Formats ARM Immediate Constants Fig 11.11

• S = For data processing instructions, updates condition codes

• S = For load/store multiple instructions, execution restricted to supervisor mode
• P, U, W = distinguish between different types of addressing_mode
• B = Unsigned byte (B==1) or word (B==0) access
• L = For load/store instructions, Load (L==1) or Store (L==0)
• L = For branch instructions, is return address stored in link register

Thumb Instruction Set Expanding Thumb ADD Instruction to ARM Equivalent Fig 11.12

• Re-encoded subset of ARM instruction set

• Increases performance in 16-bit or less data bus
• Unconditional (4 bits saved)
• Always update conditional flags
– Update flag not used (1 bit saved)
• Subset of instructions
– 2 bit opcode, 3 bit type field (1 bit saved)
– Reduced operand specifications (9 bits saved)

Assembler Improvements

• Machines store and understand binary instructions • Use hexadecimal rather than binary
• E.g. N= I + J + K initialize I=2, J=3, K=4 – Code as series of lines
• Program starts in location 101 • Hex address and memory address
• Data starting 201 – Need to translate automatically using program
• Code: • Add symbolic names or mnemonics for instructions
• Load contents of 201 into AC • Three fields per line
• Add contents of 202 to AC – Location address
• Add contents of 203 to AC – Three letter opcode
• Store contents of AC to 204 – If memory reference: address
• Tedious and error prone • Need more complex translation program

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Program in:
Binary Hexadecimal Symbolic Addresses
Address Contents Address Contents

101 0010 0010 101 2201 101 2201

• First field (address) now symbolic
102 0001 0010 102 1202 102 1202
• Memory references in third field now
103 0001 0010 103 1203 103 1203
symbolic
104 0011 0010 104 3204 104 3204
• Now have assembly language and need an
assembler to translate
201 0000 0000 201 0002 201 0002
• Assembler used for some systems
202 0000 0000 202 0003 202 0003 programming
203 0000 0000 203 0004 203 0004 – Compliers
204 0000 0000 204 0000 204 0000 – I/O routines

Symbolic Program Assembler Program

Address Instruction Label Operation Operand

101 LDA 201 FORMUL LDA I
102 ADD 202 ADD J
103 ADD 203
ADD K
104 STA 204
STA N

201 DAT 2
202 DAT 3
I DATA 2
203 DAT 4
J DATA 3
204 DAT 0
K DATA 4
N DATA 0