A B C D E

1 1

LCFC Confidential
EYG10/ES430/ES530 MB Schematics Document
2 KBL-U22/U42 with DDR4 + Nvidia N16S-GTR/N17S-G1 2

2018-01
REV:1.0

3 3

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 Cover Page
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EYG10_ES430_ES530
Date: Tuesday, January 09, 2018 Sheet 1 of 60
A B C D E
 A B C D E

LCFC confidential

NV: N17S-G1
Package: GB2C-64 Memory Bus DDR4 SO-DIMM x1
PCI-Express 1.2V DDR4
Page 18

4x Gen3
1
VRAM: 256*32 1

GDDR5*2: 2GB x1 Charger

TI SN1702001
USB3.0 USB3.0 Conn
HDMI (DDI 1) x1
HDMI Conn. Repeater
Parade PS8203
x1 Redriver Type-C
eDP x2
PS8713 Realtek RTS5448 Type-C Conn
eDP Conn x1

Touch Screen
I2C x1 Intel MCP
Redriver
x1
PS8713
NGFF PCI-Express KBL-U22 /U42 15W USB2.0 x1 USB3.0 Conn
SSD 4x Gen3
2 IO Board 2

x1 C/R
NGFF PCIe x1 SD Conn.
RTS5146
USB2.0 x1
WLAN&BT BGA-1356
42mm*24mm
x1
SPK Conn. Finger Print (Optional)
Page 30

Realtek
HP&Mic ALC3240 HD Audio
Combo Conn.
Page 30 Page 43

SPI SPI ROM (8MB)

DMIC W25Q64JVSIQ
Page 07

3 3
I2C x1 I2C x1 Redriver I2C
G-Sensor Redriver ISH I2C x1 Touch Pad
NTSX2102 NTSX2102
Page 45
Page 3~16

G-Sensor Board G-Sensor

EC GPIO x2 HALL Sensor x2

I2C x1
ITE IT8586E-VFBGA IO Board
Page 44
AH9247

Int.KBD Thermal Sensor

Page 45
NCT7718W Page 39

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 Block Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EYG10_ES430_ES530
Date: Tuesday, January 09, 2018 Sheet 2 of 60
A B C D E
 A B C D E

Voltage Rails ( O --> Means ON , X --> Means OFF )

SIGNAL
STATE SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

Full ON HIGH HIGH HIGH ON ON ON ON

Power Plane
S3 (Suspend to RAM) LOW HIGH HIGH ON ON OFF OFF
+3VALW +5VS

+5VALW +1.2V +3VS S4 (Suspend to Disk) LOW LOW LOW ON OFF OFF OFF
1 +VCCIO 1
S5 (Soft OFF) LOW LOW LOW ON OFF OFF OFF
V20B+ +3VALW_PCH +2.5V_DDR +VCCSTG
+VCCSA
+1.8VALW +VCCST +VCC_GT
+1.0VALW +CPU_CORE
State +0.6VS
HSIO PORT Function BOM Structure BTO Item
1 USB3.0 Conn Right @ Un-stuff
2 USB3.0 Conn Left 14@ For 14" part
3 USB Type-C 15@ For 15" part
USB3.0 4 NC YOGA@ For YOGA530 part
S0 O O O O 5 NC 530@ For 530S part
6 NC
1 USB3.0 Conn Left
S3 O O O X 2 USB Type-C
3 USB3.0 Conn Right CD@ For C cost down
4 Finger Print
S3
2
Battery only O O O X USB2.0 5 Card reader EMC@ For EMC part 2

6 Touch Panel EMC_15@ For EMC 15" part

7 EMC_NS@
S5 S4 Bluetooth For EMC un-stuff part
AC Only O O X X 8 Camera EMC_PX@ For EMC PX part
9 NC EMC_PXNS@ For EMC PX nu-stuff part
10 NC
S5 S4
Battery only O X X X 1~4 DGPU
X4
S5 S4 ME@ For ME part
5 WLAN
AC & Battery X X X X PCIE 6 NC
don't exist
7~8
X2 SSD-2
OPT@ For NV GPU part
SMBUS Control Table 9~12 OPTN16@ For NV N16S-GTR GPU part
SSD-1
X4 OPTN17@ For NV N17S-G1 GPU part
SOURCE BATT Charger DGPU IT8586E Memory PCH PMIC SODIMM Thermal WLAN
Down Sensor WiMAX

3 3
EC_SMB_CK1 IT8586E
V V X V X X X X X X
EC_SMB_DA1 +3VL_EC +3VL_EC

EC_SMB_CK2 IT8586E
X X V V X V X X V X
EC_SMB_DA2 +3VS +3VG_AON +3VS +3VALW_PCH TS@ For touch screen part
TP@ For TOuch Pad Part
EC_SMB_CK3 IT8586E UMA@
X X X V X X V X X X For UMA part
EC_SMB_DA3 +3VL_EC +3VL_EC

PCH_SMB_CLK PCH
X X X X X V X V X V
PCH_SMB_DATA +3VALW_PCH +3VALW_PCH +3VS +3VS

EC SMBus1 address EC SMBus2 address EC SMBus3 address PCH SM Bus address

Device Address Device Address Device Address Device Address
Smart Battery need to update Thermal Sensor(NCT7718W) 1001_100xb PMIC need to update DDR4 SODIMM need to update
4 4
Charger 0001 0010 b PCH need to update W lan Reserved
DGPU need to update

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 Notes List

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom EYG10_ES430_ES530 1.0

Date: Tuesday, January 09, 2018 Sheet 3 of 60

A B C D E
 5 4 3 2 1

SKL_ULT ?
UC1A
CPU_HDMI_TXN2 E55 C47 CPU_EDP_TX0-
34 CPU_HDMI_TXN2 CPU_HDMI_TXP2 DDI1_TXN[0] EDP_TXN[0] CPU_EDP_TX0+ CPU_EDP_TX0- 33
HDMI D2 F55 C46
34 CPU_HDMI_TXP2 CPU_HDMI_TXN1 E58 DDI1_TXP[0] EDP_TXP[0] D46 CPU_EDP_TX1- CPU_EDP_TX0+ 33
34 CPU_HDMI_TXN1 CPU_HDMI_TXP1 DDI1_TXN[1] EDP_TXN[1] CPU_EDP_TX1+ CPU_EDP_TX1- 33
HDMI D1 F58 C45
34 CPU_HDMI_TXP1 CPU_HDMI_TXN0 DDI1_TXP[1] EDP_TXP[1] CPU_EDP_TX2- CPU_EDP_TX1+ 33
F53 A45
34 CPU_HDMI_TXN0 CPU_HDMI_TXP0 G53 DDI1_TXN[2] EDP_TXN[2] B45 CPU_EDP_TX2+ CPU_EDP_TX2- 33
HDMI D0 34 CPU_HDMI_TXP0 CPU_HDMI_CLKN DDI1_TXP[2] EDP_TXP[2] CPU_EDP_TX3- CPU_EDP_TX2+ 33
F56 A47
34 CPU_HDMI_CLKN CPU_HDMI_CLKP G56 DDI1_TXN[3] EDP_TXN[3] B47 CPU_EDP_TX3+ CPU_EDP_TX3- 33
HDMI CLK 34 CPU_HDMI_CLKP DDI1_TXP[3] EDP_TXP[3] CPU_EDP_TX3+ 33
D CPU_EDP_AUX# D
C50 E45
D50 DDI2_TXN[0] DDI EDP EDP_AUXN F45 CPU_EDP_AUX CPU_EDP_AUX# 33
C52 DDI2_TXP[0] EDP_AUXP CPU_EDP_AUX 33
D52 DDI2_TXN[1] B52
A50 DDI2_TXP[1] EDP_DISP_UTIL
B50 DDI2_TXN[2] G50
D51 DDI2_TXP[2] DDI1_AUXN F50
C51 DDI2_TXN[3] DDI1_AUXP E48
DDI2_TXP[3] DDI2_AUXN F48
DDI2_AUXP G46
DISPLAY SIDEBANDS DDI3_AUXN +3VS
F46
PCH_HDMI_DDC_CLK L13 DDI3_AUXP
34 PCH_HDMI_DDC_CLK PCH_HDMI_DDC_DATA L12 GPP_E18/DDPB_CTRLCLK L9 CPU_HDMI_HPD
34 PCH_HDMI_DDC_DATA GPP_E19/DDPB_CTRLDATA GPP_E13/DDPB_HPD0 L7 CPU_HDMI_HPD 34
GPP_E14/DDPC_HPD1 GPP_E15 RC1601 1 @ 2 10K_0201_5%
N7 L6 GPP_E15 RC181 1 2 0_0201_5% @
GPP_E20/DDPC_CTRLCLK GPP_E15/DDPD_HPD2 EC_SCI# 44
N8 N9
GPP_E21/DDPC_CTRLDATA GPP_E16/DDPE_HPD3 L10 CPU_EDP_HPD
GPP_E17/EDP_HPD CPU_EDP_HPD 33
N11
+VCCIO N12 GPP_E22/DDPD_CTRLCLK R12 PCH_ENBKL
GPP_E23/DDPD_CTRLDATA EDP_BKLTEN PCH_ENBKL 33,44
R11 PCH_EDP_PWM
EDP_COMP EDP_BKLTCTL PCH_EDP_PWM 33
RC4 2 1 24.9_0402_1% E52 U13 PCH_ENVDD CPU_EDP_HPD RC13 1 2 100K_0402_5%
EDP_RCOMP EDP_VDDEN PCH_ENVDD 33
1 OF 20
SKYLAKE-U_BGA1356
+VCCIO&EDP_COMP : REV = 1 ?
Trace Width: 20mil @
Isolation Spacing: 25mil
Max length: 100mil

+3VS
DDP*_CTRLDATA strapping sampled on the rising edge of PWROK
RPC27
1 4 PCH_HDMI_DDC_CLK
2 3 PCH_HDMI_DDC_DATA Port Strap Enable Disable
2.2K_0404_4P2R_5% Pull up to 3.3 V
C Port 1 DDPB_CTRLDATA with 2.2Kohm NC C

Pull up to 3.3 V
Port 2 DDPC_CTRLDATA with 2.2Kohm NC

+VCCST_CPU
+VCCSTG
1

RC1625
1

49.9_0402_1% SKL_ULT ?
UC1D
RC19 @
1K_0402_5% D63
CATERR#
2

H_PECI A54 CATERR#

44 H_PECI
2

RC20 1 2 499 +-1% 0402 H_PROCHOT#_R C65 PECI

44,55 H_PROCHOT# PROCHOT# JTA G
H_THRMTRIP# C63
A65 THERMTRIP# B61 XDP_TCK
SKTOCC# PROC_TCK D60 XDP_TDI
CPU MISC PROC_TDI
1

PAD @ TC11 1 XDP_BPM0# C55 A61 XDP_TDO

RC143 PAD @ TC12 1 XDP_BPM1# D55 BPM#[0] PROC_TDO C60 XDP_TMS
PAD @ TC13 1 XDP_BPM2# B54 BPM#[1] PROC_TMS B59 XDP_TRST#
1K_0402_5% BPM#[2] PROC_TRST#
PAD @ TC14 1 XDP_BPM3# C56
BPM#[3] B56 PCH_JTAG_TCK 1
TC29 PAD @
2

PAD @ TC162 1 GPP_E3 A6 PCH_JTAG_TCK D59 PCH_JTAG_TDI

B
A7 GPP_E3/CPU_GP0 PCH_JTAG_TDI A56 PCH_JTAG_TDO B

+VCCST_CPU BA5 GPP_E7/CPU_GP1 PCH_JTAG_TDO C59 PCH_JTAG_TMS

AY5 GPP_B3/CPU_GP2 PCH_JTAG_TMS C61 PCH_JTAG_TRST#
GPP_B4/CPU_GP3 PCH_TRST# A59 JTAGX
RC155 1 2 49.9_0402_1% PROC_OPI_RCOMP AT16 JTAGX
RC156 1 2 49.9_0402_1% PCH_OPI_RCOMP AU16 PROC_POPIRCOMP
U23E@ RC157 1 2 49.9_0402_1% EDRAM_OPIO_RCOMP H66 PCH_OPIRCOMP
U23E@ RC170 1 2 49.9_0402_1% EOPIO_RCOMP H65 OPCE_RCOMP
OPC_RCOMP

SKYLAKE-U_BGA1356 1 OF 20
REV = 1 ?
@

XDP_TCK RC1546 1 2 0_0402_5% @ JTAGX RC1551 1 2 51_0402_5%

XDP_TDO RC1547 1 2 0_0402_5% @ PCH_JTAG_TDO RC1543 1 2 51_0402_5% +VCCSTG

XDP_TDI RC1548 1 2 0_0402_5% @ PCH_JTAG_TDI

XDP_TMS RC1549 1 2 0_0402_5% @ PCH_JTAG_TMS
XDP_TRST# RC1550 1 2 0_0402_5% @ PCH_JTAG_TRST#

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (DDI,EDP)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EYG10_ES430_ES530
Date: Tuesday, January 09, 2018 Sheet 4 of 60
5 4 3 2 1
 5 4 3 2 1

?
SKL_ULT
UC1B

AU53
18 DDRA_DQ[0..63] DDRA_DQ0 AL71 DDR0_CKN[0] AT53 DDRA_CLK0# 18
DDRA_DQ1 AL68 DDR0_DQ[0] DDR0_CKP[0] AU55 DDRA_CLK0 18
DDRA_DQ2 DDR0_DQ[1] DDR0_CKN[1] DDRA_CLK1# 18
AN68 AT55
DDRA_DQ3 DDR0_DQ[2] DDR0_CKP[1] DDRA_CLK1 18
AN69
DDRA_DQ4 AL70 DDR0_DQ[3] BA56
DDRA_DQ5 DDR0_DQ[4] DDR0_CKE[0] DDRA_CKE0 18
AL69 BB56
D DDRA_DQ6 AN70 DDR0_DQ[5] DDR0_CKE[1] AW56 DDRA_CKE1 18 D
DDRA_DQ7 AN71 DDR0_DQ[6] DDR0_CKE[2] AY56
DDRA_DQ8 AR70 DDR0_DQ[7] DDR0_CKE[3]
DDRA_DQ9 AR68 DDR0_DQ[8] AU45
DDRA_DQ10 AU71 DDR0_DQ[9] DDR0_CS#[0] AU43 DDRA_CS0# 18
DDRA_DQ11 AU68 DDR0_DQ[10] DDR0_CS#[1] AT45 DDRA_CS1# 18
DDRA_DQ12 DDR0_DQ[11] DDR0_ODT[0] DDRA_ODT0 18
AR71 AT43
DDRA_DQ13 AR69 DDR0_DQ[12] DDR0_ODT[1] DDRA_ODT1 18
DDRA_DQ14 AU70 DDR0_DQ[13] BA51
DDRA_DQ15 AU69 DDR0_DQ[14] DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] BB54 DDRA_MA5 18
DDRA_DQ16 DDR0_DQ[15] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] DDRA_MA9 18
BB65 BA52
DDRA_DQ17 DDR0_DQ[16]/DDR0_DQ[32] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] DDRA_MA6 18
AW65 AY52
DDRA_DQ18 AW63 DDR0_DQ[17]/DDR0_DQ[33] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] AW52 DDRA_MA8 18
DDRA_DQ19 DDR0_DQ[18]/DDR0_DQ[34] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] DDRA_MA7 18
AY63 AY55
DDRA_DQ20 BA65 DDR0_DQ[19]/DDR0_DQ[35] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] AW54 DDRA_BG0 18
DDRA_DQ21 DDR0_DQ[20]/DDR0_DQ[36] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] DDRA_MA12 18
AY65 BA54
DDRA_DQ22 DDR0_DQ[21]/DDR0_DQ[37] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] DDRA_MA11 18
BA63 BA55
DDRA_DQ23 DDR0_DQ[22]/DDR0_DQ[38] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# DDRA_ACT# 18
BB63 AY54
DDRA_DQ24 DDR0_DQ[23]/DDR0_DQ[39] DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] DDRA_BG1 18
BA61
DDRA_DQ25 AW61 DDR0_DQ[24]/DDR0_DQ[40] AU46
DDRA_DQ26 DDR0_DQ[25]/DDR0_DQ[41] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] DDRA_MA13 18
BB59 AU48
DDRA_DQ27 DDR0_DQ[26]/DDR0_DQ[42] DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] DDRA_MA15_CAS# 18
AW59 AT46
DDRA_DQ28 DDR0_DQ[27]/DDR0_DQ[43] DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] DDRA_MA14_WE# 18
BB61 AU50
DDRA_DQ29 AY61 DDR0_DQ[28]/DDR0_DQ[44] DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] AU52 DDRA_MA16_RAS# 18
DDRA_DQ30 BA59 DDR0_DQ[29]/DDR0_DQ[45] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] AY51 DDRA_BS0# 18
DDRA_DQ31 DDR0_DQ[30]/DDR0_DQ[46] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] DDRA_MA2 18
AY59 AT48
DDRA_DQ32 DDR0_DQ[31]/DDR0_DQ[47] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] DDRA_BS1# 18
AY39 AT50
DDRA_DQ33 DDR0_DQ[32]/DDR1_DQ[0] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] DDRA_MA10 18
AW39 BB50
DDRA_DQ34 DDR0_DQ[33]/DDR1_DQ[1] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] DDRA_MA1 18
AY37 AY50
DDRA_DQ35 AW37 DDR0_DQ[34]/DDR1_DQ[2] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] BA50 DDRA_MA0 18
DDRA_DQ36 BB39 DDR0_DQ[35]/DDR1_DQ[3] DDR0_MA[3] BB52 DDRA_MA3 18
DDRA_DQ37 DDR0_DQ[36]/DDR1_DQ[4] DDR0_MA[4] DDRA_MA4 18
BA39
C DDRA_DQ38 BA37 DDR0_DQ[37]/DDR1_DQ[5] AM70 DDRA_DQS#0 C
DDRA_DQ39 BB37 DDR0_DQ[38]/DDR1_DQ[6] DDR0_DQSN[0] AM69 DDRA_DQS0
DDRA_DQ40 AY35 DDR0_DQ[39]/DDR1_DQ[7] DDR0_DQSP[0] AT69 DDRA_DQS#1
DDRA_DQ41 AW35 DDR0_DQ[40]/DDR1_DQ[8] DDR0_DQSN[1] AT70 DDRA_DQS1
DDRA_DQ42 AY33 DDR0_DQ[41]/DDR1_DQ[9] DDR0_DQSP[1] BA64 DDRA_DQS#2
DDRA_DQ43 AW33 DDR0_DQ[42]/DDR1_DQ[10] DDR0_DQSN[2]/DDR0_DQSN[4] AY64 DDRA_DQS2 DDRA_DQS#[0..7]
DDRA_DQ44 DDR0_DQ[43]/DDR1_DQ[11] DDR0_DQSP[2]/DDR0_DQSP[4] DDRA_DQS#3 DDRA_DQS#[0..7] 18
BB35 AY60
DDRA_DQ45 BA35 DDR0_DQ[44]/DDR1_DQ[12] DDR0_DQSN[3]/DDR0_DQSN[5] BA60 DDRA_DQS3 DDRA_DQS[0..7]
DDRA_DQ46 BA33 DDR0_DQ[45]/DDR1_DQ[13] DDR0_DQSP[3]/DDR0_DQSP[5] BA38 DDRA_DQS#4 DDRA_DQS[0..7] 18
DDRA_DQ47 BB33 DDR0_DQ[46]/DDR1_DQ[14] DDR0_DQSN[4]/DDR1_DQSN[0] AY38 DDRA_DQS4
DDRA_DQ48 AY31 DDR0_DQ[47]/DDR1_DQ[15] DDR0_DQSP[4]/DDR1_DQSP[0] AY34 DDRA_DQS#5
DDRA_DQ49 AW31 DDR0_DQ[48]/DDR1_DQ[32] DDR0_DQSN[5]/DDR1_DQSN[1] BA34 DDRA_DQS5
DDRA_DQ50 AY29 DDR0_DQ[49]/DDR1_DQ[33] DDR0_DQSP[5]/DDR1_DQSP[1] BA30 DDRA_DQS#6
DDRA_DQ51 AW29 DDR0_DQ[50]/DDR1_DQ[34] DDR0_DQSN[6]/DDR1_DQSN[4] AY30 DDRA_DQS6
DDRA_DQ52 BB31 DDR0_DQ[51]/DDR1_DQ[35] DDR0_DQSP[6]/DDR1_DQSP[4] AY26 DDRA_DQS#7
DDRA_DQ53 BA31 DDR0_DQ[52]/DDR1_DQ[36] DDR0_DQSN[7]/DDR1_DQSN[5] BA26 DDRA_DQS7
DDRA_DQ54 BA29 DDR0_DQ[53]/DDR1_DQ[37] DDR0_DQSP[7]/DDR1_DQSP[5]
DDRA_DQ55 BB29 DDR0_DQ[54]/DDR1_DQ[38] AW50
DDRA_DQ56 DDR0_DQ[55]/DDR1_DQ[39] DDR0_ALERT# DDRA_ALERT# 18
AY27 AT52
DDRA_DQ57 DDR0_DQ[56]/DDR1_DQ[40] DDR0_PAR DDRA_PAR 18
AW27 SMVREF
DDRA_DQ58 AY25 DDR0_DQ[57]/DDR1_DQ[41] AY67
DDR0_DQ[58]/DDR1_DQ[42] DDR_VREF_CA DDR_SA_VREFCA 18 WIDTH:20MIL
DDRA_DQ59 AW25 AY68
DDRA_DQ60 DDR0_DQ[59]/DDR1_DQ[43] DDR0_VREF_DQ DDR_SB_VREFCA
SPACING: 20MIL
BB27 DDR CH - A BA67 1
DDRA_DQ61 DDR0_DQ[60]/DDR1_DQ[44] DDR1_VREF_DQ TC213 @
BA27
DDRA_DQ62 BA25 DDR0_DQ[61]/DDR1_DQ[45] AW67 DDR_VTT_CNTL
DDRA_DQ63 BB25 DDR0_DQ[62]/DDR1_DQ[46] DDR_VTT_CNTL
DDR0_DQ[63]/DDR1_DQ[47]
1 OF 20
SKYLAKE-U_BGA1356
REV = 1 ?
@
B B

+3VALW

RC30
100K_0402_5%
2

CPU_DRAMPG_CNTL 55
+1.2V
RC3
1K_0402_5%
1

C
1 2 2 QC18
B
E
3

MMBT3904WH_SOT323-3

DDR_VTT_CNTL
2

RC29
10K_0402_5%
@
1

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (DDR4)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EYG10_ES430_ES530
Date: Tuesday, January 09, 2018 Sheet 5 of 60
5 4 3 2 1
 5 4 3 2 1

?
SKL_ULT
UC1C

AF65 AN45
AF64 DDR1_DQ[0]/DDR0_DQ[16] DDR1_CKN[0] AN46
AK65 DDR1_DQ[1]/DDR0_DQ[17] DDR1_CKN[1] AP45
AK64 DDR1_DQ[2]/DDR0_DQ[18] DDR1_CKP[0] AP46
AF66 DDR1_DQ[3]/DDR0_DQ[19] DDR1_CKP[1]
D AF67 DDR1_DQ[4]/DDR0_DQ[20] AN56 D
AK67 DDR1_DQ[5]/DDR0_DQ[21] DDR1_CKE[0] AP55
AK66 DDR1_DQ[6]/DDR0_DQ[22] DDR1_CKE[1] AN55
AF70 DDR1_DQ[7]/DDR0_DQ[23] DDR1_CKE[2] AP53
AF68 DDR1_DQ[8]/DDR0_DQ[24] DDR1_CKE[3]
AH71 DDR1_DQ[9]/DDR0_DQ[25] BB42
AH68 DDR1_DQ[10]/DDR0_DQ[26] DDR1_CS#[0] AY42
AF71 DDR1_DQ[11]/DDR0_DQ[27] DDR1_CS#[1] BA42
AF69 DDR1_DQ[12]/DDR0_DQ[28] DDR1_ODT[0] AW42
AH70 DDR1_DQ[13]/DDR0_DQ[29] DDR1_ODT[1]
AH69 DDR1_DQ[14]/DDR0_DQ[30] AY48
AT66 DDR1_DQ[15]/DDR0_DQ[31] DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] AP50
AU66 DDR1_DQ[16]/DDR0_DQ[48] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] BA48
AP65 DDR1_DQ[17]/DDR0_DQ[49] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] BB48
AN65 DDR1_DQ[18]/DDR0_DQ[50] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] AP48
AN66 DDR1_DQ[19]/DDR0_DQ[51] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] AP52
AP66 DDR1_DQ[20]/DDR0_DQ[52] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] AN50
AT65 DDR1_DQ[21]/DDR0_DQ[53] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] AN48
AU65 DDR1_DQ[22]/DDR0_DQ[54] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] AN53
AT61 DDR1_DQ[23]/DDR0_DQ[55] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# AN52
AU61 DDR1_DQ[24]/DDR0_DQ[56] DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]
AP60 DDR1_DQ[25]/DDR0_DQ[57] BA43
AN60 DDR1_DQ[26]/DDR0_DQ[58] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] AY43
AN61 DDR1_DQ[27]/DDR0_DQ[59] DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] AY44
AP61 DDR1_DQ[28]/DDR0_DQ[60] DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14] AW44
AT60 DDR1_DQ[29]/DDR0_DQ[61] DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16] BB44
AU60 DDR1_DQ[30]/DDR0_DQ[62] DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] AY47
AU40 DDR1_DQ[31]/DDR0_DQ[63] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2] BA44
AT40 DDR1_DQ[32]/DDR1_DQ[16] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] AW46
AT37 DDR1_DQ[33]/DDR1_DQ[17] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] AY46
AU37 DDR1_DQ[34]/DDR1_DQ[18] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] BA46
AR40 DDR1_DQ[35]/DDR1_DQ[19] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0] BB46
C AP40 DDR1_DQ[36]/DDR1_DQ[20] DDR1_MA[3] BA47 C
AP37 DDR1_DQ[37]/DDR1_DQ[21] DDR1_MA[4]
AR37 DDR1_DQ[38]/DDR1_DQ[22] AH66
AT33 DDR1_DQ[39]/DDR1_DQ[23] DDR1_DQSN[0]/DDR0_DQSN[2] AH65
AU33 DDR1_DQ[40]/DDR1_DQ[24] DDR1_DQSP[0]/DDR0_DQSP[2] AG69
AU30 DDR1_DQ[41]/DDR1_DQ[25] DDR1_DQSN[1]/DDR0_DQSN[3] AG70
AT30 DDR1_DQ[42]/DDR1_DQ[26] DDR1_DQSP[1]/DDR0_DQSP[3] AR66
AR33 DDR1_DQ[43]/DDR1_DQ[27] DDR1_DQSN[2]/DDR0_DQSN[6] AR65
AP33 DDR1_DQ[44]/DDR1_DQ[28] DDR1_DQSP[2]/DDR0_DQSP[6] AR61
AR30 DDR1_DQ[45]/DDR1_DQ[29] DDR1_DQSN[3]/DDR0_DQSN[7] AR60
AP30 DDR1_DQ[46]/DDR1_DQ[30] DDR1_DQSP[3]/DDR0_DQSP[7] AT38
AU27 DDR1_DQ[47]/DDR1_DQ[31] DDR1_DQSN[4]/DDR1_DQSN[2] AR38
AT27 DDR1_DQ[48] DDR1_DQSP[4]/DDR1_DQSP[2] AT32
AT25 DDR1_DQ[49] DDR1_DQSN[5]/DDR1_DQSN[3] AR32
AU25 DDR1_DQ[50] DDR1_DQSP[5]/DDR1_DQSP[3] AR25
AP27 DDR1_DQ[51] DDR1_DQSN[6] AR27
AN27 DDR1_DQ[52] DDR1_DQSP[6] AR22
AN25 DDR1_DQ[53] DDR1_DQSN[7] AR21
AP25 DDR1_DQ[54] DDR1_DQSP[7]
AT22 DDR1_DQ[55] AN43
AU22 DDR1_DQ[56] DDR1_ALERT# AP43
AU21 DDR1_DQ[57] DDR1_PAR AT13 CPU_DRAMRST#_R
AT21 DDR1_DQ[58] DRAM_RESET# AR18 SM_RCOMP_0 RC24 1 2 121_0402_1%
AN22 DDR1_DQ[59] DDR_RCOMP[0] AT18 SM_RCOMP_1 RC25 1 2 80.6_0402_1%
AP22 DDR1_DQ[60] DDR_RCOMP[1] AU18 SM_RCOMP_2 RC26 1 2 100_0402_1%
AP21 DDR1_DQ[61] DDR_RCOMP[2]
AN21 DDR1_DQ[62] DDR CH - B
DDR1_DQ[63]

SKYLAKE-U_BGA1356 1 OF 20
REV = 1 ?
B @ B

+1.2V
1

RC22
470_0402_5%
2

RC23 1 2 0_0402_5% @ CPU_DRAMRST#_R

18 CPU_DRAMRST#
1
CC1
0.01U_0201_25V6-K
EMC_NS@
2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (DDR4)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EYG10_ES430_ES530
Date: Tuesday, January 09, 2018 Sheet 6 of 60
5 4 3 2 1
 5 4 3 2 1

+3VALW_PCH +3VS +3VS

?
SKL_ULT
UC1E

4
3

4
3
SPI - FLASH
SMBUS, SMLINK
SPI_CLK_R AV2 R7 PCH_SMB_CLK RPC24
SPI0_CLK GPP_C0/SMBCLK RPC1

2
D SPI_CLK SPI_CLK_R SPI_SO_R PCH_SMB_DATA D
RC1539 1 2 15_0402_5% AW3 R8 DIMM, NGFF 2.2K_0404_4P2R_5%

G
44 SPI_CLK SPI_SI_R AV3 SPI0_MISO GPP_C1/SMBDATA R10 SMB_ALERT# 2.2K_0404_4P2R_5%
SPI_WP#_R AW2 SPI0_MOSI GPP_C2/SMBALERT#

1
2

1
2
SPI_SO RC53 1 2 15_0402_5% SPI_SO_R SPI_HOLD#_R AU4 SPI0_IO2 R9 SML0_CLK
44 SPI_SO SPI_CS0#_R SPI0_IO3 GPP_C3/SML0CLK SML0_DATA PCH_SMB_CLK
AU3 W2 QC2A 6 1

S
SPI0_CS0# GPP_C4/SML0DATA SML0_ALERT# SMB_CLK_S3 18,40
AU2 W1

D
SPI_SI RC52 1 2 15_0402_5% SPI_SI_R AU1 SPI0_CS1# GPP_C5/SML0ALERT# 2N7002KDWH_SOT363-6
44 SPI_SI SPI0_CS2#

5
W3 PCH_SML1_CLK

G
GPP_C6/SML1CLK V3 PCH_SML1_DAT
SPI_CS0# GPP_C7/SML1DATA GPU, EC, Thermal Sensor
RC51 1 2 0_0201_5% @ SPI_CS0#_R SPI - TOUCH
AM7 SML1_ALERT#
44 SPI_CS0# GPP_B23/SML1ALERT#/PCHHOT#
M2
M3 GPP_D1/SPI1_CLK PCH_SMB_DATA QC2B 3 4

S
GPP_D2/SPI1_MISO SMB_DATA_S3 18,40
J4

D
V1 GPP_D3/SPI1_MOSI 2N7002KDWH_SOT363-6
V2 GPP_D21/SPI1_IO2
BOARD_ID4 M1 GPP_D22/SPI1_IO3 AY13
LPC
8 BOARD_ID4 GPP_D0/SPI1_CS# GPP_A1/LAD0/ESPI_IO0 BA13 LPC_AD0 44
GPP_A2/LAD1/ESPI_IO1 LPC_AD1 44
BB13
C LINK GPP_A3/LAD2/ESPI_IO2 AY12 LPC_AD2 44
GPP_A4/LAD3/ESPI_IO3 LPC_AD3 44
G3 BA12
CL_CLK GPP_A5/LFRAME#/ESPI_CS# LPC_FRAME# 44
G2 BA11
G1 CL_DATA GPP_A14/SUS_STAT#/ESPI_RESET#
CL_RST#
AW9 CLK_PCI_EC_R RC173 2 1 22_0402_5%
GPP_A9/CLKOUT_LPC0/ESPI_CLK CLK_PCI_EC 44
KBRST# AW13 AY9
44 KBRST# GPP_A0/RCIN# GPP_A10/CLKOUT_LPC1 PM_CLKRUN#
AW11
SERIRQ AY11 GPP_A8/CLKRUN#
44 SERIRQ GPP_A6/SERIRQ

SKYLAKE-U_BGA1356 1 OF 20
REV = 1
?
@

C +3V_SPI C
+3VALW
check CLKRUN# / SUS_STAT# signal if need to connect +3VS
@
RC171 1 2 0_0402_5%

PM_CLKRUN# RC11 1 2 8.2K_0402_5%

+3V_SPI
1. If support DS3, connect to +3VS and don't support EC mirror code; SERIRQ RC12 1 2 10K_0402_5%
2. If don't support DS3, connect to +3VALW_PCH and support EC mirror code.
*
KBRST# RC10 1 2 10K_0402_5% +3VALW_PCH

SMB_ALERT# 2.2K_0402_5% 2 1 RC1562

KBRST# CC1255 1 2 1000P_0201_50V7-K
SML0_CLK 2.2K_0402_5% 2 1 RC3042
EMC_NS@
+3V_SPI
SML0_DATA 2.2K_0402_5% 2 1 RC3043
1

RC60 RC61
1K_0402_5% 1K_0402_5% SML0_ALERT# RC1564 2 @ 1 2.2K_0402_5%
2

SPI_WP#_R SPI_WP#
This signal has a weak internal pull-down.
RC54 1 2 15_0402_5% +3VALW_PCH +3VS 0 = LPC Is selected for EC. (Default)
1 = eSPI Is selected for EC.
SPI_HOLD#_R RC55 1 2 15_0402_5% SPI_HOLD# Notes:
1. The internal pull-down is disabled after RSMRST#
de-asserts.
1

Check with BIOS, SPI is Dual mode or quad mode

RC3045
2. This signal is in the primary wel
RC3044

2
B B
Rising edge of RSMRST#

G
2.2K_0402_5% 2.2K_0402_5% +3VALW_PCH
2

+3V_SPI PCH_SML1_CLK QC10A 6 1 SML1_ALERT# RC1569 1 @ 2 150K_0402_5% +3VS

S
EC_SMB_CK2 26,36,39,44
D

UC3
2N7002KDWH_SOT363-6 RC1655 1 2 150K_0402_5%

5
SPI_CS0# 1 8

G
/CS VCC @
SPI_SO 2 7 SPI_HOLD#
DO (IO1) IO3 1 To enable Direct Connect Interface (DCI), a 150K pull up resistor will need to be
CC8
SPI_WP# 3 6 SPI_CLK 0.1u_0201_10V6K PCH_SML1_DAT QC10B 3 4 added to PCHHOT# pin. This pin must be low during the rising edge of RSMRST#.
S
IO2 CLK EC_SMB_DA2 26,36,39,44 (Refer to WW52_MOW)
D

4 5 SPI_SI 2 2N7002KDWH_SOT363-6
GND DI (IO0)
@

W25Q64JVSSIQ_SO8

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (MISC,JTAG,SPI,LPC,SMB)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EYG10_ES430_ES530
Date: Tuesday, January 09, 2018 Sheet 7 of 60
5 4 3 2 1
 5 4 3 2 1

+3VS

+3VS
@OPT&GC6 Only for NV GPU SKU
+3VS

2
RC1559 2 OPT@ 1 10K_0402_5% PXS_PWREN_R 1K_0201_5% 2 OPT@ 1 RC7

1
10K_0201_5%

10K_0201_5%

10K_0201_5%

10K_0201_5%

10K_0201_5%
PXS_PWREN 23,55 @

OPTN17@
FB_GC6_EN_R

10K_0201_5%

10K_0201_5%

10K_0201_5%
OPT@
RC1629 1 2 10K_0402_5%

1 RC1615

RC1613

RC1611

RC1609

1 RC1606
NTS@
FB_GC6_EN_R 23,26

NFP@

FHD@
RC1608

2 RC1631

RC1639
RC1641 1 2 10K_0402_5% PXS_RST#_R @ 0_0201_5% 2 1RC8

530S@
@

15@
PXS_RST# 26 GPU_EVENT#
RC1630 1 GC6@ 2 10K_0201_5%
Reserve for GPU sequence GPU_EVENT# 26

1
RC1557 1 OPT@ 2 10K_0402_5% PXS_RST#_R RC1637 1 @ 2 10K_0402_5% FB_GC6_EN_R

2
BOARD_ID0
BOARD_ID1
CC1259 1 2 0.01U_0201_10V6K PXS_RST# RC1638 1 @ 2 10K_0201_5% GPU_EVENT#
BOARD_ID2
BOARD_ID3
OPT@ BOARD_ID4
D D
7 BOARD_ID4 BOARD_ID5
DGPU_PWROK
DGPU_PWROK 23,57 BOARD_ID6
BOARD_ID7

2
2

1
10K_0201_5%
@UMA SKU

2
10K_0201_5%

10K_0201_5%

10K_0201_5%

10K_0201_5%

10K_0201_5%

10K_0201_5%
UMAorN16@

10K_0201_5%

YOGA@
1 RC1616

RC1614

RC1612

RC1610

RC1607

2 RC1634

RC1640
@

TS@

14@
UMA@

FP@
?

UHD@
1 RC123
SKL_ULT
2 10K_0201_5% DGPU_PWROK UC1F
RC1558 1 UMA@
LPSS ISH

1
1

2
AN8 P2 BOARD_ID0
AP7 GPP_B15/GSPI0_CS# GPP_D9 P3 BOARD_ID1
AP8 GPP_B16/GSPI0_CLK GPP_D10 P4 BOARD_ID2
RC1561 1 @ 2 2.2K_0402_5% GPP_B18 AR7 GPP_B17/GSPI0_MISO GPP_D11 P1 BOARD_ID3
+3VS +3VS GPP_B18/GSPI0_MOSI GPP_D12
AM5 M4 ISH_I2C0_SDA
AN7 GPP_B19/GSPI1_CS# GPP_D5/ISH_I2C0_SDA N3 ISH_I2C0_SCL ISH_I2C0_SDA 36,43
RPC28
PCH_I2C_SDA0 GPP_B20/GSPI1_CLK GPP_D6/ISH_I2C0_SCL ISH_I2C0_SCL 36,43
1 4 AP5
2 3 PCH_I2C_SCL0 RC1563 1 @ 2 2.2K_0402_5% GPP_B22 AN5 GPP_B21/GSPI1_MISO N1 ISH_I2C1_SDA Board ID Description Stuff R
GPP_B22/GSPI1_MOSI GPP_D7/ISH_I2C1_SDA N2 ISH_I2C1_SCL ISH_I2C1_SDA 43
UART_RX_DEBUG GPP_D8/ISH_I2C1_SCL ISH_I2C1_SCL 43 00 UMA RC1614 RC1616
2.2K_0404_4P2R_5% AB1
40 UART_RX_DEBUG UART_TX_DEBUG AB2 GPP_C8/UART0_RXD AD11
RPC30 40 UART_TX_DEBUG GPP_C9/UART0_TXD GPP_F10/I2C5_SDA/ISH_I2C2_SDA 01 Reserved RC1613 RC1616
PCH_I2C_SDA1 W4 AD12 Board_ID[1:0]
1 4 GPP_C10/UART0_RTS# GPP_F11/I2C5_SCL/ISH_I2C2_SCL
PCH_I2C_SCL1 AB3
2 3 GPP_C11/UART0_CTS# 10 N16S-GTR RC1613 RC1616
PXS_PWREN_R AD1 U1
2.2K_0404_4P2R_5% PXS_RST#_R AD2 GPP_C20/UART2_RXD GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA U2 11 N17S_G1 RC1613 RC1615
TS@ DGPU_PWROK GPP_C21/UART2_TXD GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL PCH_WLAN_OFF#
AD3 U3
FB_GC6_EN_R AD4 GPP_C22/UART2_RTS# GPP_D15/ISH_UART0_RTS# U4 PCH_BT_OFF# PCH_WLAN_OFF# 40 0 others CPU RC1612
Board_ID2
2 RC1658 1 PCH_TP_INT# GPP_C23/UART2_CTS# GPP_D16/ISH_UART0_CTS#/SML0BALERT# PCH_BT_OFF# 40
AC1 PCH_TS_IRQ
1 4415U RC1611
10K_0402_5% 2 0_0402_5% @ PCH_I2C_SDA0 U7 GPP_C12/UART1_RXD/ISH_UART1_RXD AC2 PCH_TS_RST# PCH_TS_IRQ 33
RC1656 1 PCH_TS_RST# 33
Touch PAD 45 TP_I2C_SDA0
RC1657 1 2 0_0402_5% @ PCH_I2C_SCL0 U6 GPP_C16/I2C0_SDA GPP_C13/UART1_TXD/ISH_UART1_TXD AC3 GPU_EVENT# 0 FP RC1610
45 TP_I2C_SCL0 GPP_C17/I2C0_SCL GPP_C14/UART1_RTS#/ISH_UART1_RTS#
Board_ID3
AB4 PCH_TP_INT#
PCH_I2C_SDA1 U8 GPP_C15/UART1_CTS#/ISH_UART1_CTS# PCH_TP_INT# 45 1 NON-FP RC1609
+3VS 33 PCH_I2C_SDA1 PCH_I2C_SCL1 U9 GPP_C18/I2C1_SDA ISH_GP0
C Touch Screen AY8 C
33 PCH_I2C_SCL1 GPP_C19/I2C1_SCL GPP_A18/ISH_GP0 BA8 BOARD_ID6 ISH_GP0 43 0 TS RC1607
GPP_A19/ISH_GP1
Board_ID4
PCH_I2C_SDA2 AH9 BB7 BOARD_ID5
PCH_I2C_SCL2 AH10 GPP_F4/I2C2_SDA GPP_A20/ISH_GP2 BA7 AOAC_ON# 1 NON_TS RC1608
PCH_WLAN_OFF# GPP_F5/I2C2_SCL GPP_A21/ISH_GP3 AOAC_ON# 40
RC1596 2 1 10K_0402_5% AY7
RC1597 2 1 10K_0402_5% PCH_BT_OFF# AH11 GPP_A22/ISH_GP4 AW7 0 UHD RC123
GPP_F6/I2C3_SDA GPP_A23/ISH_GP5
Board_ID5
AH12 AP13 ISH_GP6
GPP_F7/I2C3_SCL GPP_A12/BM_BUSY#/ISH_GP6 ISH_GP6 43 1 FHD RC1606
AF11
AF12 GPP_F8/I2C4_SDA
Board_ID6 0 14" RC1634
GPP_F9/I2C4_SCL
+3VALW +3VS 1 15" RC1631
SKYLAKE-U_BGA1356 1 OF 20
RC1600 1 @ 2 1K_0402_5% REV = 1 ? @ 0 YOGA RC1640
PCH_TS_RST# RC513 1 2 10K_0402_5% Board_ID7
@
RC47 1 @ 2 1K_0402_5% HDA_SDOUT 1 530S RC1639

*
HDA_SDO This signal has a weak internal pull-down.
0 = Enable security measures defined in the Flash Descriptor.
1 = Disable Flash Descriptor Security(override). This strap
should only be asserted high during external pull-up in
manufacturing/debug environments ONLY. UC1G SKL_ULT ?

AUDIO

RC43 1 2 33_0402_5% HDA_SYNC BA22

30 HDA_SYNC_AUDIO HDA_BCLK HDA_SYNC/I2S0_SFRM
RC42 1 2 33_0402_5% AY22
30 HDA_BITCLK_AUDIO HDA_SDOUT BB22 HDA_BLK/I2S0_SCLK
SDIO/SDXC
HDA_SDIN0 BA21 HDA_SDO/I2S0_TXD
30 HDA_SDIN0 AY21 HDA_SDI0/I2S0_RXD AB11
AW22 HDA_SDI1/I2S1_RXD GPP_G0/SD_CMD AB13
For EMI HDA_SDIN0 HDA_RST#/I2S1_SCLK GPP_G1/SD_DATA0
J5 AB12
1 AY20 GPP_D23/I2S_MCLK GPP_G2/SD_DATA1 W12
CC7 AW20 I2S1_SFRM GPP_G3/SD_DATA2 W11
10P_0201_50V8F I2S1_TXD GPP_G4/SD_DATA3 W10
EMC_NS@ AK7 GPP_G5/SD_CD# W8
B 2 GPP_F1/I2S2_SFRM GPP_G6/SD_CLK B
AK6 W7
AK9 GPP_F0/I2S2_SCLK GPP_G7/SD_WP
AK10 GPP_F2/I2S2_TXD BA9
GPP_F3/I2S2_RXD GPP_A17/SD_PWR_EN#/ISH_GP7 BB9
GPP_A16/SD_1P8_SEL
H5 AB7 SD_RCOMP
RC45 1 2 33_0402_5% HDA_SDOUT BOARD_ID7 D7 GPP_D19/DMIC_CLK0 SD_RCOMP
30 HDA_SDOUT_AUDIO GPP_D20/DMIC_DATA0
RC46 1 2 0_0402_5% @
44 ME_FLASH

1
D8 AF13
C8 GPP_D17/DMIC_CLK1 GPP_F23 RC49
GPP_D18/DMIC_DATA1 200_0402_1%
PCH_BEEP AW5
30 PCH_BEEP GPP_B14/SPKR

2
+3VS
SKYLAKE-U_BGA1356 1 OF 20
REV = 1 ?
RC14 1 @ 2 2.2K_0402_5% PCH_BEEP @

RC514 1 TS@ 2 10K_0402_5% PCH_TS_IRQ

+1.8VS
Default When
Pin Name Strap Description Configuration Value Sampled +1.8VS

Internal PD
2
1

0 = Disable “ Top Swap” RPC29

SPKR / Top Swap 0 Rising edge
GPP_B14 Override
mode. (Default)
1 = Enable “ Top Swap” * of PCH_PWROK 2.2K_0404_4P2R_5%
G1

mode. 8396@
3
4

Internal PD PCH_I2C_SCL2 S1 EC_SMB_CK4

GSPI0_MOSI 0 = Disable “ No Reboot” Rising edge EC_SMB_CK4 44
D1S
D

/GPP_B18 No Reboot 0 of PCH_PWROK

mode. (Default)
*
G2

1 = Enable “ No Reboot” QV37A

mode DMN5L06DWK-7_SOT363-6
8396@
G

A A
PCH_I2C_SDA2 S2 D2 EC_SMB_DA4
EC_SMB_DA4 44
S

GSPI1_MOSIBoot BIOS Internal PD Rising edge

/GPP_B22 Strap Bit 0 = SPI (Default) 0 of PCH_PWROK
BBS 1 = LPC * QV37B
DMN5L06DWK-7_SOT363-6
8396@

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (LPSS,ISH,AUDIO,SDIO)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EYG10_ES430_ES530
Date: Tuesday, January 09, 2018 Sheet 8 of 60
5 4 3 2 1
 5 4 3 2 1

20 PCIE_CRX_GTX_N[0..3]

20 PCIE_CRX_GTX_P[0..3]

20 PCIE_CTX_C_GRX_N[0..3]

20 PCIE_CTX_C_GRX_P[0..3]

SKL_ULT
?
UC1H
D D

SSIC / USB3
PCIE/USB3/SATA
H8 USB30_RX_N1
USB3_1_RXN USB30_RX_P1 USB30_RX_N1 43
G8
PCIE_CRX_GTX_N0 H13
PCIE1_RXN/USB3_5_RXN
USB3_1_RXP
USB3_1_TXN
C13 USB30_TX_N1 USB30_RX_P1
USB30_TX_N1
43
43
RIGHT USB3.0
PCIE_CRX_GTX_P0 G13 D13 USB30_TX_P1
PCIE_CTX_C_GRX_N0 PCIE_CTX_GRX_N0 PCIE1_RXP/USB3_5_RXP USB3_1_TXP USB30_TX_P1 43
0.22U_0201_6.3V6-K OPT@ 1 2 CC16 B17
PCIE_CTX_C_GRX_P0 0.22U_0201_6.3V6-K OPT@ 1 2 CC14 PCIE_CTX_GRX_P0 A17 PCIE1_TXN/USB3_5_TXN J6 USB30_RX_N2
PCIE1_TXP/USB3_5_TXP USB3_2_RXN/SSIC_1_RXN USB30_RX_P2 USB30_RX_N2 41
H6
PCIE_CRX_GTX_N1 USB3_2_RXP/SSIC_1_RXP USB30_TX_N2 USB30_RX_P2 41
G11 B13
PCIE_CRX_GTX_P1 F11 PCIE2_RXN/USB3_6_RXN
PCIE2_RXP/USB3_6_RXP
USB3_2_TXN/SSIC_1_TXN
USB3_2_TXP/SSIC_1_TXP
A13 USB30_TX_P2 USB30_TX_N2
USB30_TX_P2
41
41
LEFT USB3.0
PCIE_CTX_C_GRX_N1 0.22U_0201_6.3V6-K OPT@ 1 2 CC15 PCIE_CTX_GRX_N1 D16
PCIE_CTX_C_GRX_P1 0.22U_0201_6.3V6-K OPT@ 1 2 CC17 PCIE_CTX_GRX_P1 C16 PCIE2_TXN/USB3_6_TXN J10 USB30_RX_N3
DGPU PCIE2_TXP/USB3_6_TXP USB3_3_RXN/SSIC_2_RXN
USB3_3_RXP/SSIC_2_RXP
H10 USB30_RX_P3 USB30_RX_N3
USB30_RX_P3
42
42
PCIE_CRX_GTX_N2 H16 B15 USB30_TX_N3
PCIE_CRX_GTX_P2 G16 PCIE3_RXN
PCIE3_RXP
USB3_3_TXN/SSIC_2_TXN
USB3_3_TXP/SSIC_2_TXP
A15 USB30_TX_P3 USB30_TX_N3
USB30_TX_P3
42
42
Type-C
PCIE_CTX_C_GRX_N2 0.22U_0201_6.3V6-K OPT@ 1 2 CC18 PCIE_CTX_GRX_N2 D17
PCIE_CTX_C_GRX_P2 0.22U_0201_6.3V6-K OPT@ 1 2 CC19 PCIE_CTX_GRX_P2 C17 PCIE3_TXN E10
PCIE3_TXP USB3_4_RXN F10
PCIE_CRX_GTX_N3 G15 USB3_4_RXP C15
PCIE_CRX_GTX_P3 F15 PCIE4_RXN USB3_4_TXN D15
PCIE_CTX_C_GRX_N3 0.22U_0201_6.3V6-K OPT@ 1 2 CC20 PCIE_CTX_GRX_N3 B19 PCIE4_RXP USB3_4_TXP
PCIE_CTX_C_GRX_P3 0.22U_0201_6.3V6-K OPT@ 1 2 CC21 PCIE_CTX_GRX_P3 A19 PCIE4_TXN AB9 USB20_N1
PCIE4_TXP USB2N_1 USB20_N1 41
PCIE_PRX_DTX_N5 F16 USB2P_1
AB10 USB20_P1
USB20_P1 41 LEFT USB3.0
40 PCIE_PRX_DTX_N5 PCIE_PRX_DTX_P5 PCIE5_RXN USB20_N2
E16 AD6
40 PCIE_PRX_DTX_P5 PCIE5_RXP USB2N_2 USB20_N2 42
40 PCIE_PTX_C_DRX_N5
CC1264 1 2 0.1u_0201_10V6K PCIE_PTX_DRX_N5 C19
PCIE5_TXN USB2P_2
AD7 USB20_P2
USB20_P2 42 Type-C
WLAN 40 PCIE_PTX_C_DRX_P5
CC1263 1 2 0.1u_0201_10V6K PCIE_PTX_DRX_P5 D19
PCIE5_TXP AH3 USB20_N3
USB2N_3 USB20_N3 43
G18
F18 PCIE6_RXN USB2P_3
AJ3 USB20_P3
USB20_P3 43 RIGHT USB3.0
D20 PCIE6_RXP AD9 USB20_N4
PCIE6_TXN USB2N_4 USB20_N4 45
C20
PCIE6_TXP USB2P_4
AD10 USB20_P4
USB20_P4 45 Finger Print
PCIE_PRX_DTX_N7 F20 AJ1 USB20_N5
38 PCIE_PRX_DTX_N7 PCIE7_RXN/SATA0_RXN USB2N_5 USB20_N5 43
C
38 PCIE_PRX_DTX_P7
PCIE_PRX_DTX_P7
PCIE_PTX_DRX_N7
E20
B21 PCIE7_RXP/SATA0_RXP USB2P_5
AJ2 USB20_P5
USB20_P5 43 Card reader C
USB2
38 PCIE_PTX_DRX_N7 PCIE_PTX_DRX_P7 A21 PCIE7_TXN/SATA0_TXN AF6 USB20_N6
38 PCIE_PTX_DRX_P7 PCIE7_TXP/SATA0_TXP USB2N_6 USB20_N6 33
SSD 1 PCIE_PRX_DTX_N8 G21 USB2P_6
AF7 USB20_P6
USB20_P6 33 Touch Screen
38 PCIE_PRX_DTX_N8 PCIE_PRX_DTX_P8 PCIE8_RXN/SATA1A_RXN USB20_N7
F21 AH1
38 PCIE_PRX_DTX_P8 PCIE8_RXP/SATA1A_RXP USB2N_7 USB20_N7 40
38 PCIE_PTX_DRX_N8
PCIE_PTX_DRX_N8
PCIE_PTX_DRX_P8
D21
C21 PCIE8_TXN/SATA1A_TXN USB2P_7
AH2 USB20_P7
USB20_P7 40 BT
38 PCIE_PTX_DRX_P8 PCIE8_TXP/SATA1A_TXP USB20_N8
AF8
USB2N_8 USB20_N8 33
37 PCIE_PRX_DTX_N9
PCIE_PRX_DTX_N9
PCIE_PRX_DTX_P9
E22
E23 PCIE9_RXN USB2P_8
AF9 USB20_P8
USB20_P8 33 Camera
37 PCIE_PRX_DTX_P9 PCIE_PTX_DRX_N9 B23 PCIE9_RXP AG1
37 PCIE_PTX_DRX_N9 PCIE_PTX_DRX_P9 A23 PCIE9_TXN USB2N_9 AG2
37 PCIE_PTX_DRX_P9 PCIE9_TXP USB2P_9
PCIE_PRX_DTX_N10 F25 AH7
37 PCIE_PRX_DTX_N10 PCIE_PRX_DTX_P10 E25 PCIE10_RXN USB2N_10 AH8
37 PCIE_PRX_DTX_P10 PCIE_PTX_DRX_N10 D23 PCIE10_RXP USB2P_10
37 PCIE_PTX_DRX_N10 PCIE_PTX_DRX_P10 C23 PCIE10_TXN AB6 USB2_COMP RC118 2 1 113_0402_1% USBRBIAS
37 PCIE_PTX_DRX_P10 PCIE10_TXP USB2_COMP AG3 USB2_ID RC1626 1 2 0_0402_5% @ Width 20Mil
RC119 1 2 100_0402_1% PCIE_RCOMPN F5 USB2_ID AG4 USB2_VBUSSENSE RC1627 1 2 1K_0402_5% Space 15Mil
PCIE_RCOMPP E5 PCIE_RCOMPN USB2_VBUSSENSE Length 500Mil
PCIE_RCOMPP A9 USB_OC0#
GPP_E9/USB2_OC0# USB_OC0# 43
SSD 2 PCIE_RCOMPN and PCIE_RCOMPP
Trace Width: 12-15mil
PAD @
PAD @
TC20
TC19
1
1
XDP_PRDY#
XDP_PREQ#
D56
D61 PROC_PRDY# GPP_E10/USB2_OC1#
C9
D9
USB_OC1#
USB_OC2# USB_OC1# 41
Differential between RCOMPP/RCOMPN
PIRQA# BB11 PROC_PREQ# GPP_E11/USB2_OC2# B9 USB_OC3#
GPP_A7/PIRQA# GPP_E12/USB2_OC3#
PCIE_PRX_DTX_N11 E28 J1 GPP_E4 RC1628 1 2 0_0201_5% @
37 PCIE_PRX_DTX_N11 PCIE_PRX_DTX_P11 E27 PCIE11_RXN/SATA1B_RXN GPP_E4/DEVSLP0 J2 EC_SMI# 44 2016/05/03: Implement as Power Button
37 PCIE_PRX_DTX_P11 PCIE_PTX_DRX_N11 PCIE11_RXP/SATA1B_RXP GPP_E5/DEVSLP1 PCH_SATA_1_DEVSLP 37 function for Windows RedStone support
D24 J3
37 PCIE_PTX_DRX_N11 PCIE_PTX_DRX_P11 PCIE11_TXN/SATA1B_TXN GPP_E6/DEVSLP2
C24
37 PCIE_PTX_DRX_P11 PCIE_PRX_DTX_N12 E30 PCIE11_TXP/SATA1B_TXP H2
37 PCIE_PRX_DTX_N12 SATA0GP
PCIE_PRX_DTX_P12 F30 PCIE12_RXN/SATA2_RXN GPP_E0/SATAXPCIE0/SATAGP0 H3 SSD_1_PCIE_DET#
37 PCIE_PRX_DTX_P12 PCIE_PTX_DRX_N12 PCIE12_RXP/SATA2_RXP GPP_E1/SATAXPCIE1/SATAGP1 SSD_2_PCIE_DET# SSD_1_PCIE_DET# 38
A25 G4
37 PCIE_PTX_DRX_N12 PCIE_PTX_DRX_P12 PCIE12_TXN/SATA2_TXN GPP_E2/SATAXPCIE2/SATAGP2 SSD_2_PCIE_DET# 37
B25
37 PCIE_PTX_DRX_P12 PCIE12_TXP/SATA2_TXP H1
GPP_E8/SATALED#

SKYLAKE-U_BGA1356 1 OF 20
REV = 1 ?
B B
@

+3VS

+3VALW_PCH
GPP_E4 RC1617 2 @ 1 10K_0201_5%
RPC17
+3VS 1 8 USB_OC0#
RPC2 2 7 USB_OC1#
1 8 SSD_2_PCIE_DET# 3 6 USB_OC3#
USB_OC2# USB_OC2# @
2 7 PIRQA# 4 5 RC1654 1 2 0_0402_5%
3 6 SSD_1_PCIE_DET# TYPE_C_OCP# 42
4 5 SATA0GP 10K_0804_8P4R_5%

10K_0804_8P4R_5%

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (PCIE,SATA,USB3,USB2)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EYG10_ES430_ES530
Date: Tuesday, January 09, 2018 Sheet 9 of 60
5 4 3 2 1
 5 4 3 2 1

UC1I
SKL_ULT ?

CSI-2

A36 C37
B36 CSI2_DN0 CSI2_CLKN0 D37
C38 CSI2_DP0 CSI2_CLKP0 C32
D38 CSI2_DN1 CSI2_CLKN1 D32
C36 CSI2_DP1 CSI2_CLKP1 C29
D36 CSI2_DN2 CSI2_CLKN2 D29
A38 CSI2_DP2 CSI2_CLKP2 B26
B38 CSI2_DN3 CSI2_CLKN3 A26
D CSI2_DP3 CSI2_CLKP3 D

C31 E13 CSI2_COMP RC73 1 2 100_0402_1%

D31 CSI2_DN4 CSI2_COMP B7
C33 CSI2_DP4 GPP_D4/FLASHTRIG
D33 CSI2_DN5
A31 CSI2_DP5 EMMC

B31 CSI2_DN6 AP2

A33 CSI2_DP6 GPP_F13/EMMC_DATA0 AP1
B33 CSI2_DN7 GPP_F14/EMMC_DATA1 AP3
CSI2_DP7 GPP_F15/EMMC_DATA2 AN3
A29 GPP_F16/EMMC_DATA3 AN1
B29 CSI2_DN8 GPP_F17/EMMC_DATA4 AN2
C28 CSI2_DP8 GPP_F18/EMMC_DATA5 AM4
D28 CSI2_DN9 GPP_F19/EMMC_DATA6 AM1
A27 CSI2_DP9 GPP_F20/EMMC_DATA7
B27 CSI2_DN10 AM2
C27 CSI2_DP10 GPP_F21/EMMC_RCLK AM3
D27 CSI2_DN11 GPP_F22/EMMC_CLK AP4
CSI2_DP11 GPP_F12/EMMC_CMD
AT1 EMMC_RCOMP RC50 1 2 200_0402_1%
EMMC_RCOMP
SKYLAKE-U_BGA1356 1 OF 20
REV = 1 ?
@

@DIS For NV GPU SKU UC1J SKL_ULT ?

C CLOCK SIGNALS C

CLK_PCIE_GPU# D42
20 CLK_PCIE_GPU# CLK_PCIE_GPU C42 CLKOUT_PCIE_N0
PCIE CLK0 DGPU 20 CLK_PCIE_GPU GPU_CLKREQ# CLKOUT_PCIE_P0
AR10
20 GPU_CLKREQ# GPP_B5/SRCCLKREQ0#
B42
A42 CLKOUT_PCIE_N1 F43 CLK_PCIE_XDP# 1 TC85 @ SUSCLK RC95 1 @ 2 1K_0402_5%
AT7 CLKOUT_PCIE_P1 CLKOUT_ITPXDP_N E43 CLK_PCIE_XDP 1 TC87 @
GPP_B6/SRCCLKREQ1# CLKOUT_ITPXDP_P
CLK_PCIE_WLAN# D41 BA17 SUSCLK
40 CLK_PCIE_WLAN# CLK_PCIE_WLAN C41 CLKOUT_PCIE_N2 GPD8/SUSCLK SUSCLK 40
+3VS WLAN 40 CLK_PCIE_WLAN WLAN_CLKREQ# AT8 CLKOUT_PCIE_P2 E37 XTAL24_U22_IN
40 WLAN_CLKREQ# GPP_B7/SRCCLKREQ2# XTAL24_IN E35 XTAL24_U22_OUT +VCCCLK5
RPC4 CLK_PCIE_SSD_1# D40 XTAL24_OUT
1 8 GPU_CLKREQ# 37 CLK_PCIE_SSD_1# CLKOUT_PCIE_N3
CLK_PCIE_SSD_1 C40 E42 DIFFCLK_BIASREF RC72 1 2 2.7K_0402_1%
2 7 WLAN_CLKREQ# 37 CLK_PCIE_SSD_1 CLKOUT_PCIE_P3 XCLK_BIASREF
SSD_1_CLKREQ# AT10
3 6 SSD_2_CLKREQ# SSD-2 37 SSD_1_CLKREQ# GPP_B8/SRCCLKREQ3# RTC_X1
SSD_1_CLKREQ# AM18
4 5 CLK_PCIE_SSD_2# RTCX1 RTC_X2
B40 AM20
38 CLK_PCIE_SSD_2# CLK_PCIE_SSD_2 A40 CLKOUT_PCIE_N4 RTCX2
10K_0804_8P4R_5% SSD-1 38 CLK_PCIE_SSD_2 SSD_2_CLKREQ# AU8 CLKOUT_PCIE_P4 AN18 SRTC_RST#
38 SSD_2_CLKREQ# GPP_B9/SRCCLKREQ4# SRTCRST# AM16 RTC_RST#
E40 RTCRST#
E38 CLKOUT_PCIE_N5
AU7 CLKOUT_PCIE_P5
GPP_B10/SRCCLKREQ5#

1U_0402_6.3V6K
1 OF 20 1
SKYLAKE-U_BGA1356

CC3
REV = 1 ? VCCRTC
@
B U22@ 2 B
RC3035 2 1 0_0402_5% SRTC_RST#
RC33 1 2 20K_0402_1%
RC34 1 2 20K_0402_1% RTC_RST# RC1624 1 @ 2 0_0402_5%
EC_RTC_RST# 44
L1 U22_EMC_NS@

1U_0402_6.3V6K
XTAL24_U22_IN_R 1 2 XTAL24_U22_IN 1

1
1 2

CC6
XTAL24_U22_OUT_R 4 3 XTAL24_U22_OUT JCMOS2
4 3 2
@
EXC24CH900U_4P RTC_X1 Place Bottom
SM070004400
U22@ RTC_X2
RC3034 1 2 0_0402_5% RC32 2 1 10M_0402_5%

YC1
1 2
U22@
RC3030 2 1 1M_0402_5% 2 32.768KHZ_9PF_X1A0001410002 2
YC3 CC4 CC5
6P_0402_50V8D 6P_0402_50V8D
2 3 XTAL24_U22_OUT_R 1 1
GND1 OSC2
XTAL24_U22_IN_R 1 4
OSC1 GND2
1
CC1324 24MHZ_6PF_7V24000032 1
CC1325
2.7P_0402_50V9-B
U22@ 2.7P_0402_50V9-B
U22@
2 U22@
2
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (CSI2,EMMC,CLOCK)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EYG10_ES430_ES530
Date: Tuesday, January 09, 2018 Sheet 10 of 60
5 4 3 2 1
 5 4 3 2 1

2
CC1322 ?
SKL_ULT
0.1U_0402_25V6 UC1K
EMC_NS@
1 SYSTEM POWER MANAGEMENT
AT11
GPP_B12/SLP_S0# AP15 PM_SLP_S3#_R RC96 1 2 0_0402_5% @
1 @ 2 0_0402_5% PLT_RST#_R AN10 GPD4/SLP_S3# BA16 PM_SLP_S4#_R 1 2 0_0402_5% @ PM_SLP_S3# 44
RC84 RC97
26,37,38,40,44 PLT_RST# SYS_RESET# B5 GPP_B13/PLTRST# GPD5/SLP_S4# AY16 PM_SLP_S4# 44
D 1 @ 2 0_0402_5% PCH_RSMRST#_R AY17 SYS_RESET# GPD10/SLP_S5# D
RC85
44 EC_RSMRST# RSMRST# AN15 PM_SLP_SUS#_R 1
1 CPU_PROCPWRGD A68 SLP_SUS# AW15 TC211 @ PAD
@ PAD TC21
VCCST_PWRGD_R RC93 1 2 60.4_0402_1% VCCST_PWRGD B65 PROCPWRGD SLP_LAN# BB17
VCCST_PWRGD GPD9/SLP_WLAN# AN16
RC139 1 2 0_0402_5% @ SYS_PWROK_R B6 GPD6/SLP_A#
44 SYS_PWROK 2 0_0402_5% @ PCH_PWROK_R SYS_PWROK PBTN_OUT#_R
RC126 1 BA20 BA15 RC87 1 2 0_0402_5% @
44 PCH_PWROK PCH_DPWROK_R BB20 PCH_PWROK GPD3/PWRBTN# AY15 AC_PRESENT_R PBTN_OUT# 44
DSW_PWROK GPD1/ACPRESENT AU13 BATLOW#
SUSWARN#_R AR13 GPD0/BATLOW#
AP11 GPP_A13/SUSWARN#/SUSPWRDNACK VCCRTC
GPP_A15/SUSACK# AU11
PCIE_WAKE# BB15 GPP_A11/PME# AP16 INTVRMEN RC41 2 1 330K_0402_5%
40 PCIE_WAKE# PCH_LAN_WAKE# AM15 WAKE# INTRUDER#
AW17 GPD2/LAN_WAKE# AM10
AT15 GPD11/LANPHYPC GPP_B11/EXT_PWR_GATE# AM11
GPD7/RSVD GPP_B2/VRALERT#

SKYLAKE-U_BGA1356 1 OF 20
REV = 1 ?
@

RC88 1 2 0_0402_5% @ AC_PRESENT_R

44 AC_PRESENT
+3VALW

RC74 1 2 10K_0402_5% AC_PRESENT_R

RC75 1 2 8.2K_0402_5% BATLOW#

C +VCCST_CPU C
RC76 2 1 1K_0402_5% PCIE_WAKE# Follow CRB change to 1kohm

RC90 1 2 10K_0402_5% PCH_LAN_WAKE#

2
RC137
1K_0402_5%
+3VALW_PCH

1
RC15991 2 0_0402_5% @ VCCST_PWRGD_R
RC78 1 @ 2 10K_0402_5% SUSWARN#_R 44 EC_VCCST_PWRGD
2
CC140
+3VS 1000P_0201_50V7-K
EMC_NS@
1

RC80 1 2 10K_0402_5% SYS_RESET#

PCH_DPWROK_R RC182 1 2 0_0402_5% @ EC_RSMRST#

EMC_NS@
1000P_0201_50V7-K 1 2 CC1254 PCH_RSMRST#_R

0.01U_0201_10V6K 1 2 CC104 @ PCH_PWROK

1000P_0201_50V7-K 1 2 CC103 PCH_DPWROK_R

B EMC_NS@ B

47P_0201_25V8-J 1 2 CC101 @ SYS_PWROK

+3VL
0.01U_0201_10V6K 1 2 CC1260 @ EC_RSMRST#
@
RC17 1 2 0_0402_5% EC_RSMRST#

2
Add to fix Reset&PWRGD test fail issue RC5
100K_0402_5%
@

3
D

1
5 Q3B
G
2N7002KDWH_SOT363-6
RPC21

6
1 8 PCH_RSMRST#_R D S @
1 2 0_0402_5% 2

4
2 7 PCH_PWROK 54 +3V_PWRGD RC15 @ Q3A
SYS_PWROK G
3 6 2N7002KDWH_SOT363-6
RC16 1 @ 2 0_0402_5%
4 5 54,55 ALW_PWRGD S @

1
10K_0804_8P4R_5%

330P_0402_50V7K 1 2 CC1294

100K_0402_5% 2 1 RC92 PLT_RST#_R

100K_0402_1% 2 @ 1 RC94 PCH_DPWROK_R

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (SYSTEM PWR MANAGEMENT)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EYG10_ES430_ES530
Date: Tuesday, January 09, 2018 Sheet 11 of 60
5 4 3 2 1
 5 4 3 2 1

+CPU_CORE ? +CPU_CORE +CPU_CORE +VCC_GT +VCC_GT

SKL_ULT SKL_ULT ?
UC1L +VCCCORE_GT2 +VCC_GT UC1M
CPU POWER 1 OF 4 VCORE_VCC_SEN VCCGT_VCC_SEN
RC77 1 2 100_0402_1% RC83 1 2 100_0402_1% CPU POWER 2 OF 4
A30 G32 N70
A34 VCC_A30 VCC_G32 G33 A48 VCCGT_N70 N71
A39 VCC_A34 VCC_G33 G35 VCORE_VSS_SEN RC82 1 2 100_0402_1% VCCGT_VSS_SEN RC98 1 2 100_0402_1% A53 VCCGT_A48 VCCGT_N71 R63
A44 VCC_A39 VCC_G35 G37 A58 VCCGT_A53 VCCGT_R63 R64
AK33 VCC_A44 VCC_G37 G38 A62 VCCGT_A58 VCCGT_R64 R65
AK35 VCC_AK33 VCC_G38 G40 A66 VCCGT_A62 VCCGT_R65 R66
AK37 VCC_AK35 VCC_G40 G42 AA63 VCCGT_A66 VCCGT_R66 R67
AK38 VCC_AK37 VCC_G42 J30 AA64 VCCGT_AA63 VCCGT_R67 R68
AK40 VCC_AK38 VCC_J30 J33 AA66 VCCGT_AA64 VCCGT_R68 R69
AL33 VCC_AK40 VCC_J33 J37 AA67 VCCGT_AA66 VCCGT_R69 R70
AL37 VCC_AL33 VCC_J37 J40 AA69 VCCGT_AA67 VCCGT_R70 R71
AL40 VCC_AL37 VCC_J40 K33 AA70 VCCGT_AA69 VCCGT_R71 T62
AM32 VCC_AL40 VCC_K33 K35 +VCCST_CPU AA71 VCCGT_AA70 VCCGT_T62 U65
D
VCC_AM32 VCC_K35
SVID VCCGT_AA71 VCCGT_U65
D
AM33 K37 AC64 U68
AM35 VCC_AM33 VCC_K37 K38 AC65 VCCGT_AC64 VCCGT_U68 U71
AM37 VCC_AM35 VCC_K38 K40 AC66 VCCGT_AC65 VCCGT_U71 W63
AM38 VCC_AM37 VCC_K40 K42 AC67 VCCGT_AC66 VCCGT_W63 W64
G30 VCC_AM38 VCC_K42 K43 AC68 VCCGT_AC67 VCCGT_W64 W65
VCC_G30 VCC_K43 AC69 VCCGT_AC68 VCCGT_W65 W66
VCORE_VCC_SEN 1 VCCGT_AC69 VCCGT_W66
1 K32 E32 CC42 AC70 W67
@ TC90 RSVD_K32 VCC_SENSE E33 VCORE_VSS_SEN VCORE_VCC_SEN 58 0.1u_0201_10V6K AC71 VCCGT_AC70 VCCGT_W67 W68
VSS_SENSE VCORE_VSS_SEN 58 VCCGT_AC71 VCCGT_W68

1
56_0402_5%
AK32 J43 W69

100_0402_1%

100_0402_1%
@
RSVD_AK32 B63 CPU_SVID_ALERT#_R 2 J45 VCCGT_J43 VCCGT_W69 W70

RC131

RC132
RC1544
AB62 VIDALERT# A63 CPU_SVID_CLK_R J46 VCCGT_J45 VCCGT_W70 W71
P62 VCCOPC_AB62 VIDSCK D64 CPU_SVID_DAT_R J48 VCCGT_J46 VCCGT_W71 Y62
V62 VCCOPC_P62 VIDSOUT J50 VCCGT_J48 VCCGT_Y62 +VCCCORE_GT1

2
VCCOPC_V62 G20 J52 VCCGT_J50
VCCSTG_G20 +VCCSTG VCCGT_J52
H63 @ J53 AK42
VCC_OPC_1P8_H63 J55 VCCGT_J53 VCCGTX_AK42 AK43
G61 J56 VCCGT_J55 VCCGTX_AK43 AK45
VCC_OPC_1P8_G61 RC133 1 2 220_0402_1% CPU_SVID_ALERT#_R J58 VCCGT_J56 VCCGTX_AK45 AK46
58 VR_SVID_ALRT# VCCGT_J58 VCCGTX_AK46
AC63 J60 AK48
AE63 VCCOPC_SENSE +VCCCOREG2_GT K48 VCCGT_J60 VCCGTX_AK48 AK50
VSSOPC_SENSE RC134 1 2 0_0402_5% @ CPU_SVID_CLK_R K50 VCCGT_K48 VCCGTX_AK50 AK52
AE62 58 VR_SVID_CLK K52 VCCGT_K50 VCCGTX_AK52 AK53
AG62 VCCEOPIO_AE62 K53 VCCGT_K52 VCCGTX_AK53 AK55
VCCEOPIO_AG62 RC1545 1 2 0_0402_5% @ CPU_SVID_DAT_R K55 VCCGT_K53 VCCGTX_AK55 AK56
AL63 58 VR_SVID_DAT K56 VCCGT_K55 VCCGTX_AK56 AK58
AJ62 VCCEOPIO_SENSE K58 VCCGT_K56 VCCGTX_AK58 AK60
VSSEOPIO_SENSE K60 VCCGT_K58 VCCGTX_AK60 AK70
1, Alert# Route Between CLK and Data L62 VCCGT_K60 VCCGTX_AK70 AL43
SKYLAKE-U_BGA1356 1 OF 20 L63 VCCGT_L62 VCCGTX_AL43 AL46
REV = 1 ? L64 VCCGT_L63 VCCGTX_AL46 AL50
@ L65 VCCGT_L64 VCCGTX_AL50 AL53
L66 VCCGT_L65 VCCGTX_AL53 AL56
L67 VCCGT_L66 VCCGTX_AL56 AL60
L68 VCCGT_L67 VCCGTX_AL60 AM48
09/09 delete CC1097 22uf_0402 change to Power side PC4089 L69 VCCGT_L68 VCCGTX_AM48 AM50
+CPU_CORE
Backside Cap 8x10uF 0402, SIT update L70 VCCGT_L69 VCCGTX_AM50 AM52
13x10uF 0402, SIT update to 0603 package +VCC_GT L71 VCCGT_L70 VCCGTX_AM52 AM53
M62 VCCGT_L71 VCCGTX_AM53 AM56
N63 VCCGT_M62 VCCGTX_AM56 AM58
C
N64 VCCGT_N63 VCCGTX_AM58 AU58 C
10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
N66 VCCGT_N64 VCCGTX_AU58 AU63

10U_0402_6.3V6M

10U_0402_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1

10U_0402_6.3V6M
1 1 1 1 1 1 1 1 1 1 1 1 1 N67 VCCGT_N66 VCCGTX_AU63 BB57
CC1086

CC1085

CC1080

CC1236

CC1237

CC1093

CC1092

CC1091

CC1089

CC1238

CC1098

CC1109

CC1318

CC1317

CC1122

CC1123

CC1124

CC1125

CC1127

CC1128

CC1129
CC1095 N69 VCCGT_N67 VCCGTX_BB57 BB66

CC1096
VCCGT_N69 VCCGTX_BB66
2 2 2 2 2 2 2 2 2 2 VCCGT_VCC_SEN J70 AK62
2 2 2 2 2 2 2 2 2 2 2 2 2 58 VCCGT_VCC_SEN VCCGT_SENSE VCCGTX_SENSE
VCCGT_VSS_SEN J69 AL61
@ @ @ @ 58 VCCGT_VSS_SEN VSSGT_SENSE VSSGTX_SENSE
@
@ @ @ @ @ @
SKYLAKE-U_BGA1356 1 OF 20
REV = 1 ?
@
09/09 NC CC1317 ,CC1096,CC1080,CC1238,CC1085 09/09-1 CC1108 change from U42@ to all
09/09-2 delete CC1108 and add PC4091 on power side 09/09 NC PC4087,,mount CC1317 09/15 NC CC1128

+CPU_CORE
+VCC_GT
Backside Cap 12x1uF 0201, SIT update

1U_0402_6.3V6K
1

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K
CC1119
1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1 1 1 1 1 1

CC1240
1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1 1 1

CC1111

CC1114

CC1115

CC1116

CC1118
1 1 1 1 1 1
CC1101
CC1099

CC1100

CC1296

CC1306
CC1102

CC1104

CC1304

CC1305

2
2 2 2 2 2 2
2 2 2 @
2 2 2 2 2 2 @
@

B B
+VCCCORE_GT2
+VCCCORE_GT2
+CPU_CORE

RC1068 1 U42@ 2 0.0002_0805

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

1 1 1 1
CC1326

CC1327

CC1328

CC1329

+VCC_GT
2 2 2 2
RC1068,RC1069,RC1070
RC1069 1 U22@ 2 0.0002_0805 @ @ @
SDV: SD00002040T
SIV: SD000020400

07/04 add location based on Layout condition

+VCCCORE_GT1
+CPU_CORE

+VCCCORE_GT1
RC1070 1 U42@ 2 0.0002_0805

+VCC_GT +VCCCOREG2_GT
10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

1 1 1
RC3029 1 U22@ 2 0_0402_5%
CC1330

CC1331

CC1332

2 2 2

U42@ U42@ U42@

07/04 add location based on Layout condition

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2016/12/14 Deciphered Date 2017/12/13 MCP (CPU PWR1)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EYG10_ES430_ES530
Date: Tuesday, January 09, 2018 Sheet 12 of 60
5 4 3 2 1
 5 4 3 2 1

+VCCIO
3.1A 2x10uF, 4x1uF

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M
10U_0402_6.3V6M

10U_0402_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1
+VCCIO

CC1152

CC1153

CC1158

CC1159

CC1160

CC1161

CC1218

CC1230

CC1231

CC1232
?
+1.2V UC1N SKL_ULT

CPU POWER 3 OF 4 2 2 2 2 2 2 2 2 2 2
2800mA AU23 AK28 3100mA
AU28 VDDQ_AU23 VCCIO_AK28 AK30
AU35 VDDQ_AU28 VCCIO_AK30 AL30 @ @ @ @ @
AU42 VDDQ_AU35 VCCIO_AL30 AL42
+1.2V BB23 VDDQ_AU42 VCCIO_AL42 AM28
2A , 3x22uF, 6x10uF, 4x1uF, SIT update VDDQ_BB23 VCCIO_AM28
BB32 AM30 +VCCSA
BB41 VDDQ_BB32 VCCIO_AM30 AM42
BB47 VDDQ_BB41 VCCIO_AM42
D VDDQ_BB47 D
BB51 AK23 5100mA +VCCSA

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M
10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
VDDQ_BB51 VCCSA_AK23 AK25
1 1 1 1 1 1 1 1 1 1 1 1 1 1 VCCSA_AK25
4.5A 10x10uF, 7x1uF, SIT update
G23
CC1256

CC1257

CC1258

CC1168

CC1169

CC1171

CC1222

CC1223

CC1243

CC1244

CC1224

CC1225

CC1226

CC1227
AM40 VCCSA_G23 G25
+VDDQ_CPU_CLK VDDQC VCCSA_G25 G27
2 2 2 2 2 2 2 2 2 2 2 2 2 2 A18 VCCSA_G27 G28

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
+VCCST_CPU VCCST VCCSA_G28 J22 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CD@ @ CD@ @ CD@ @ A22 VCCSA_J22 J23

CC1133

CC1134

CC1135

CC1136

CC1137

CC1251

CC1252

CC1253

CC1139

CC1140

CC1142

CC1145

CC1141

CC1143

CC1144
+VCCSTG VCCSTG_A22 VCCSA_J23 J27

CC1132
AL23 VCCSA_J27 K23
+VCCSFR_OC VCCPLL_OC VCCSA_K23 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
K25
K20 VCCSA_K25 K27
130mA K21 VCCPLL_K20 VCCSA_K27 K28 @
CC1168,CC1223,CC1243,CC1244 change to 0402 Bourne 20170501 +VCCPLL_CPU VCCPLL_K21 VCCSA_K28 K30 CD@ CD@ CD@ CD@ @ CD@ CD@
CC1256,CC1257,CC1258 change 22uF/0603 to 10uf/0402 by high limit VCCSA_K30
Stuff CC1256,CC1257,CC1258,CC1243 AM23 VCCIO_SENSE 1 TC136 @
Bourne 20170713 VCCIO_SENSE VSSIO_SENSE
AM22 1 TC137 @
VSSIO_SENSE 10uF change to 0402 Bourne 20170501 0909 NC1253,CC1137
H21 VCCSA_VSS_SEN
VSSSA_SENSE H20 VCCSA_VCC_SEN VCCSA_VSS_SEN 58
VCCSA_SENSE VCCSA_VCC_SEN 58

SKYLAKE-U_BGA1356 1 OF 20
REV = 1 ?
@

+VCCSTG +VCCST_CPU
+VDDQ_CPU_CLK
120mA
+1.2V RC1497 1 2 0_0402_5% @ +VCCIO RC103 1 2 0_0402_5% @
1U_0201_6.3V6-M

1U_0402_6.3V6K
1
10U_0402_6.3V6M

1U_0402_6.3V6K
1 1 RC1604 1 @ 2 0_0402_5%
CC1229

+VCCST_CPU
CC1228

CC86
1 +VCCSA

CC87
C @ +1.0VALW +VCCST_CPU C
2
2 2 Reserved for VCCST/VCCSTG/VCCPLL
power optimized 2
RC1605 1 @ 2 0_0402_5%
VCCSA_VCC_SEN RC101 1 2 100_0402_1%
Reserved for VCCST/VCCSTG/VCCPLL power optimized
+VCCSFR_OC VCCSA_VSS_SEN RC102 1 2 100_0402_1%

+VCCPLL_CPU
RC104 1 2 0_0402_5% @
1U_0201_6.3V6-M

1 120mA
CC85

+VCCST_CPU RC105 1 2 0_0402_5% @

0.1u_0201_10V6K

1U_0402_6.3V6K
2 1 1

CC1249

CC84
2 2

+VCCIO
+1.0VALW

10U_0402_6.3V6M
10U_0402_6.3V6M

22U_0402_4V6-M
VCCIO_EN

22U_0402_4V6-M
RC128 1 2 0_0402_5% @ 1 1
44 EC_VCCIO_EN 1 1

CC1250

C1102
B B

CC71

CC72
@
@
1 2 2
CC77 2 2
0.01U_0201_6.3V7-K UC4
@ 1 14
2 2 IN1_1 OUT1_2 13
IN1_2 OUT1_1
VCCIO_EN 3 12 CC1293 1 2 1000P_0201_50V7-K
EN1 CT1
+5VALW
4 11
VBIAS GND
VCCST_EN 5 10 CC1292 1 2 1000P_0201_50V7-K
EN2 CT2 +VCCST_CPU
+1.0VALW
6 9
IN2_1 OUT2_2

10U_0402_6.3V6M
7 8
IN2_2 OUT2_1
VCCST_EN 1

10U_0402_6.3V6M
RC142 1 2 0_0402_5% @ 15

CC80
44 EC_VCCST_EN GPAD
1 @

CC79
1 AP22966DC8-7 V-DFN3020 14P
CC81 2
0.01U_0201_6.3V7-K
@ 2
2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (CPU PWR2)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EYG10_ES430_ES530
Date: Tuesday, January 09, 2018 Sheet 13 of 60
5 4 3 2 1
 5 4 3 2 1

+1.0VALW RC1503 1 2 0_0603_SM @ +VCCAMPHY

+1.0VALW RC1504 1 2 0_0402_5% @

+VCCAPLL_1P0

+VCCHDA

D D

+3VALW_PCH RC1586 1 2 0_0402_5% @

RC1620 1 @ 2 0_0402_5% VCCMPHYON_1P0_L1

+1.0VALW

1U_0402_6.3V6K
1

CC144
2

+3VALW_PCH

0.696A
+1.0VALW

1U_0402_6.3V6K
Near AB19
1

1U_0402_6.3V6K

1U_0402_6.3V6K
CC141
1 1

CC156

CC174
22mA 2.574A @ +3VALW_PCH
+1.0VALW +1.0VALW ?

1U_0402_6.3V6K
1 1 @

22U_0603_6.3V6-M
SKL_ULT
2 UC1O

CC158
2 2

CC153
+1.0VALW
1.5A @
CPU POWER 4 OF 4

1U_0402_6.3V6K
+VCCDSW_1P0 2 2 AB19 1

1U_0201_6.3V6-M
VCCPRIM_1P0_AB19
1U_0201_6.3V6-M

CC175
1 AB20 AK15 20mA Near Y15
22U_0402_4V6-M

VCCPRIM_1P0_AB20 VCCPGPPA +3VALW_PCH

CC145
1 1 P18 AG15 4mA @

1U_0402_6.3V6K
VCCPRIM_1P0_P18 VCCPGPPB
CC148

CC147

Near AF18 Y16 6mA 1

VCCPGPPC 2

CC176
@ AF18 Y15 8mA
2 AF19 VCCPRIM_CORE_AF18 VCCPGPPD T16 6mA @
2 2 VCCPRIM_CORE_AF19 VCCPGPPE +1.8VALW
C V20 AF16 161mA C

1U_0402_6.3V6K
VCCPRIM_CORE_V20 VCCPGPPF +1.8VALW 2
V21 AD15 61mA 1
VCCPRIM_CORE_V21 VCCPGPPG

CC142
PCH Internal VRM +3VALW_PCH
AL1 V19

0.1u_0201_10V6K

1U_0402_6.3V6K
DCPDSW_1P0 VCCPRIM_3P3_V19
Near N15 1 1

CC143
2

CC149
K17 T1
VCCMPHYON_1P0_L1 VCCMPHYAON_1P0_K17 VCCPRIM_1P0_T1 +1.0VALW
+VCCAMPHY
88mA L1
VCCMPHYAON_1P0_L1 AA1 6mA
22U_0402_4V6-M

1U_0402_6.3V6K

N15 VCCATS_1P8 2 2
1 1 VCCMPHYGT_1P0_N15
CC151

N16 AK17 1mA

C1096

@ N17 VCCMPHYGT_1P0_N16 VCCRTCPRIM_3P3

P15 VCCMPHYGT_1P0_N17 AK19 1mA
2 2 VCCMPHYGT_1P0_P15 VCCRTC_AK19 VCCRTC
Near K15 P16 BB14

0.1u_0201_10V6K

1U_0402_6.3V6K
VCCMPHYGT_1P0_P16 VCCRTC_BB14
1 1

CC146

CC1242
K15 BB10 VCCRTCEXT
L15 VCCAMPHYPLL_1P0_K15 DCPRTC
VCCAMPHYPLL_1P0_L15

0.1u_0201_10V6K
A14 35mA
VCCCLK1 +1.0VALW 2 2
22mA V15 1
+VCCAPLL_1P0 VCCAPLL_1P0 K19 29mA @ 0_0402_5% 1 2 RC1587

CC55
VCCCLK2 +1.0VALW
0.1u_0201_10V6K

1U_0402_6.3V6K

1 1 AB17

1U_0402_6.3V6K

22U_0402_4V6-M
+1.0VALW VCCPRIM_1P0_AB17
CC154

Y18 L21 24mA

1 1
C1097

VCCPRIM_1P0_Y18 VCCCLK3 +1.0VALW 2

CC56

C1098
+VCCHDA
0.118A AD17 N20 33mA @
2 2 +3VALW VCCDSW_3P3_AD17 VCCCLK4 +VCCCLK4
0.1u_0201_10V6K

1 AD18
AJ17 VCCDSW_3P3_AD18 L19 4mA 2 2
CC165

VCCDSW_3P3_AJ17 VCCCLK5 +VCCCLK5

68mA AJ19 A10 10mA
+1.0VALW
2 VCCHDA VCCCLK6

1U_0402_6.3V6K
11mA AJ16 AN11 1
+3VALW_PCH VCCSPI GPP_B0/CORE_VID0 AN13

CC57
0.642A AF20 GPP_B1/CORE_VID1
+1.0VALW VCCSRAM_1P0_AF20
AF21
VCCSRAM_1P0_AF21 2
1U_0402_6.3V6K

1 Near AF20 T19

VCCSRAM_1P0_T19
CC159

T20
CD@

VCCSRAM_1P0_T20
75mA AJ21 RC1587,RC1588,RC1589 Change to 0402 for placement Bourne 20170630
2 +3VALW_PCH VCCPRIM_3P3_AJ21
1U_0402_6.3V6K

1 AK20
+1.0VALW VCCPRIM_1P0_AK20
CC171
CD@

33mA N18 @ 0_0402_5% 1 2 RC1588

B +1.0VALW VCCAPLLEBB +VCCCLK4 +1.0VALW B
2

22U_0603_6.3V6-M
1
1U_0402_6.3V6K

SKYLAKE-U_BGA1356 1 OF 20
1

C1099
REV = 1 @
CC169

?
@
2
2

Near A18
+VCCCLK5 RC1589 1 2 0_0402_5% @
+1.0VALW

22U_0402_4V6-M
1

C1100
@
2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (PCH PWR)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EYG10_ES430_ES530
Date: Tuesday, January 09, 2018 Sheet 14 of 60
5 4 3 2 1
 5 4 3 2 1

SKL_ULT
UC1Q ?
SKL_ULT
UC1P ?
D GND 2 OF 3 D
GND 1 OF 3
AT63 BA49
A5 AL65 AT68 VSS_AT63 VSS_BA49 BA53
A67 VSS_A5 VSS_AL65 AL66 AT71 VSS_AT68 VSS_BA53 BA57
A70 VSS_A67 VSS_AL66 AM13 AU10 VSS_AT71 VSS_BA57 BA6
AA2 VSS_A70 VSS_AM13 AM21 AU15 VSS_AU10 VSS_BA6 BA62
AA4 VSS_AA2 VSS_AM21 AM25 AU20 VSS_AU15 VSS_BA62 BA66
AA65 VSS_AA4 VSS_AM25 AM27 AU32 VSS_AU20 VSS_BA66 BA71
AA68 VSS_AA65 VSS_AM27 AM43 AU38 VSS_AU32 VSS_BA71 BB18
AB15 VSS_AA68 VSS_AM43 AM45 AV1 VSS_AU38 VSS_BB18 BB26
AB16 VSS_AB15 VSS_AM45 AM46 AV68 VSS_AV1 VSS_BB26 BB30
AB18 VSS_AB16 VSS_AM46 AM55 AV69 VSS_AV68 VSS_BB30 BB34
AB21 VSS_AB18 VSS_AM55 AM60 AV70 VSS_AV69 VSS_BB34 BB38
VSS_AB21 VSS_AM60 VSS_AV70 VSS_BB38 SKL_ULT ?
AB8 AM61 AV71 BB43 UC1R
AD13 VSS_AB8 VSS_AM61 AM68 AW10 VSS_AV71 VSS_BB43 BB55
AD16 VSS_AD13 VSS_AM68 AM71 AW12 VSS_AW10 VSS_BB55 BB6 GND 3 OF 3
AD19 VSS_AD16 VSS_AM71 AM8 AW14 VSS_AW12 VSS_BB6 BB60 F8 L18
AD20 VSS_AD19 VSS_AM8 AN20 AW16 VSS_AW14 VSS_BB60 BB64 G10 VSS_F8 VSS_L18 L2
AD21 VSS_AD20 VSS_AN20 AN23 AW18 VSS_AW16 VSS_BB64 BB67 G22 VSS_G10 VSS_L2 L20
AD62 VSS_AD21 VSS_AN23 AN28 AW21 VSS_AW18 VSS_BB67 BB70 G43 VSS_G22 VSS_L20 L4
AD8 VSS_AD62 VSS_AN28 AN30 AW23 VSS_AW21 VSS_BB70 C1 G45 VSS_G43 VSS_L4 L8
AE64 VSS_AD8 VSS_AN30 AN32 AW26 VSS_AW23 VSS_C1 C25 G48 VSS_G45 VSS_L8 N10
AE65 VSS_AE64 VSS_AN32 AN33 AW28 VSS_AW26 VSS_C25 C5 G5 VSS_G48 VSS_N10 N13
AE66 VSS_AE65 VSS_AN33 AN35 AW30 VSS_AW28 VSS_C5 D10 G52 VSS_G5 VSS_N13 N19
AE67 VSS_AE66 VSS_AN35 AN37 AW32 VSS_AW30 VSS_D10 D11 G55 VSS_G52 VSS_N19 N21
AE68 VSS_AE67 VSS_AN37 AN38 AW34 VSS_AW32 VSS_D11 D14 G58 VSS_G55 VSS_N21 N6
AE69 VSS_AE68 VSS_AN38 AN40 AW36 VSS_AW34 VSS_D14 D18 G6 VSS_G58 VSS_N6 N65
AF1 VSS_AE69 VSS_AN40 AN42 AW38 VSS_AW36 VSS_D18 D22 G60 VSS_G6 VSS_N65 N68
AF10 VSS_AF1 VSS_AN42 AN58 AW41 VSS_AW38 VSS_D22 D25 G63 VSS_G60 VSS_N68 P17
AF15 VSS_AF10 VSS_AN58 AN63 AW43 VSS_AW41 VSS_D25 D26 G66 VSS_G63 VSS_P17 P19
AF17 VSS_AF15 VSS_AN63 AP10 AW45 VSS_AW43 VSS_D26 D30 H15 VSS_G66 VSS_P19 P20
C AF2 VSS_AF17 VSS_AP10 AP18 AW47 VSS_AW45 VSS_D30 D34 H18 VSS_H15 VSS_P20 P21 C
AF4 VSS_AF2 VSS_AP18 AP20 AW49 VSS_AW47 VSS_D34 D39 H71 VSS_H18 VSS_P21 R13
AF63 VSS_AF4 VSS_AP20 AP23 AW51 VSS_AW49 VSS_D39 D44 J11 VSS_H71 VSS_R13 R6
AG16 VSS_AF63 VSS_AP23 AP28 AW53 VSS_AW51 VSS_D44 D45 J13 VSS_J11 VSS_R6 T15
AG17 VSS_AG16 VSS_AP28 AP32 AW55 VSS_AW53 VSS_D45 D47 J25 VSS_J13 VSS_T15 T17
AG18 VSS_AG17 VSS_AP32 AP35 AW57 VSS_AW55 VSS_D47 D48 J28 VSS_J25 VSS_T17 T18
AG19 VSS_AG18 VSS_AP35 AP38 AW6 VSS_AW57 VSS_D48 D53 J32 VSS_J28 VSS_T18 T2
AG20 VSS_AG19 VSS_AP38 AP42 AW60 VSS_AW6 VSS_D53 D58 J35 VSS_J32 VSS_T2 T21
AG21 VSS_AG20 VSS_AP42 AP58 AW62 VSS_AW60 VSS_D58 D6 J38 VSS_J35 VSS_T21 T4
AG71 VSS_AG21 VSS_AP58 AP63 AW64 VSS_AW62 VSS_D6 D62 J42 VSS_J38 VSS_T4 U10
AH13 VSS_AG71 VSS_AP63 AP68 AW66 VSS_AW64 VSS_D62 D66 J8 VSS_J42 VSS_U10 U63
AH6 VSS_AH13 VSS_AP68 AP70 AW8 VSS_AW66 VSS_D66 D69 K16 VSS_J8 VSS_U63 U64
AH63 VSS_AH6 VSS_AP70 AR11 AY66 VSS_AW8 VSS_D69 E11 K18 VSS_K16 VSS_U64 U66
AH64 VSS_AH63 VSS_AR11 AR15 B10 VSS_AY66 VSS_E11 E15 K22 VSS_K18 VSS_U66 U67
AH67 VSS_AH64 VSS_AR15 AR16 B14 VSS_B10 VSS_E15 E18 K61 VSS_K22 VSS_U67 U69
AJ15 VSS_AH67 VSS_AR16 AR20 B18 VSS_B14 VSS_E18 E21 K63 VSS_K61 VSS_U69 U70
AJ18 VSS_AJ15 VSS_AR20 AR23 B22 VSS_B18 VSS_E21 E46 K64 VSS_K63 VSS_U70 V16
AJ20 VSS_AJ18 VSS_AR23 AR28 B30 VSS_B22 VSS_E46 E50 K65 VSS_K64 VSS_V16 V17
AJ4 VSS_AJ20 VSS_AR28 AR35 B34 VSS_B30 VSS_E50 E53 K66 VSS_K65 VSS_V17 V18
AK11 VSS_AJ4 VSS_AR35 AR42 B39 VSS_B34 VSS_E53 E56 K67 VSS_K66 VSS_V18 W13
AK16 VSS_AK11 VSS_AR42 AR43 B44 VSS_B39 VSS_E56 E6 K68 VSS_K67 VSS_W13 W6
AK18 VSS_AK16 VSS_AR43 AR45 B48 VSS_B44 VSS_E6 E65 K70 VSS_K68 VSS_W6 W9
AK21 VSS_AK18 VSS_AR45 AR46 B53 VSS_B48 VSS_E65 E71 K71 VSS_K70 VSS_W9 Y17
AK22 VSS_AK21 VSS_AR46 AR48 B58 VSS_B53 VSS_E71 F1 L11 VSS_K71 VSS_Y17 Y19
AK27 VSS_AK22 VSS_AR48 AR5 B62 VSS_B58 VSS_F1 F13 L16 VSS_L11 VSS_Y19 Y20
AK63 VSS_AK27 VSS_AR5 AR50 B66 VSS_B62 VSS_F13 F2 L17 VSS_L16 VSS_Y20 Y21
AK68 VSS_AK63 VSS_AR50 AR52 B71 VSS_B66 VSS_F2 F22 VSS_L17 VSS_Y21
AK69 VSS_AK68 VSS_AR52 AR53 BA1 VSS_B71 VSS_F22 F23
AK8 VSS_AK69 VSS_AR53 AR55 BA10 VSS_BA1 VSS_F23 F27
AL2 VSS_AK8 VSS_AR55 AR58 BA14 VSS_BA10 VSS_F27 F28
AL28 VSS_AL2 VSS_AR58 AR63 BA18 VSS_BA14 VSS_F28 F32 1 OF 20
SKYLAKE-U_BGA1356
AL32 VSS_AL28 VSS_AR63 AR8 BA2 VSS_BA18 VSS_F32 F33 REV = 1
B VSS_AL32 VSS_AR8 VSS_BA2 VSS_F33 ? B
AL35 AT2 BA23 F35 @
AL38 VSS_AL35 VSS_AT2 AT20 BA28 VSS_BA23 VSS_F35 F37
AL4 VSS_AL38 VSS_AT20 AT23 BA32 VSS_BA28 VSS_F37 F38
AL45 VSS_AL4 VSS_AT23 AT28 BA36 VSS_BA32 VSS_F38 F4
AL48 VSS_AL45 VSS_AT28 AT35 F68 VSS_BA36 VSS_F4 F40
AL52 VSS_AL48 VSS_AT35 AT4 BA45 VSS_F68 VSS_F40 F42
AL55 VSS_AL52 VSS_AT4 AT42 VSS_BA45 VSS_F42 BA41
AL58 VSS_AL55 VSS_AT42 AT56 VSS_BA41
AL64 VSS_AL58 VSS_AT56 AT58
VSS_AL64 VSS_AT58
1 OF 20
SKYLAKE-U_BGA1356
1 OF 20
SKYLAKE-U_BGA1356 REV = 1 ?
REV = 1 ? @
@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (VSS)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EYG10_ES430_ES530
Date: Tuesday, January 09, 2018 Sheet 15 of 60
5 4 3 2 1
 5 4 3 2 1

?
SKL_ULT
UC1S

RESERVED SIGNALS-1
UC1T SKL_ULT ?
CPU_CFG0 E68 BB68
D PAD @ TC142 1 CPU_CFG1 B67 CFG[0] RSVD_TP_BB68 BB69 SPARE D
PAD @ TC143 1 CPU_CFG2 D65 CFG[1] RSVD_TP_BB69
XDP_CPU_CFG3 CFG[2] AW 69 F6
PAD @ TC144 1 D67 AK13 RSVD_AW 69 RSVD_F6
CPU_CFG4 CFG[3] RSVD_TP_AK13 AW 68 E3 XTAL24_U42_IN
E70 AK12 RSVD_AW 68 RSVD_E3
CPU_CFG5 CFG[4] RSVD_TP_AK12 AU56 C11
PAD @ TC146 1 C68 RSVD_AU56 RSVD_C11
CFG[5] AW 48 B11
2
PAD @ TC147 1 CPU_CFG6 D68 BB2 RSVD_AW 48 RSVD_B11
CFG[6] RSVD_BB2 XTAL24_U42_OUT C7 A11

2
RC1618 PAD @ TC148 1 CPU_CFG7 C67 BA3 RSVD_C7 RSVD_A11
CFG[7] RSVD_BA3 U12 D12
1K_0402_5% RC106 F71 RSVD_U12 RSVD_D12
CFG[8] U11 C12
@ 1K_0402_5% G69 RSVD_U11 RSVD_C12
CFG[9] H11 F52
F70 AU5 RSVD_H11 RSVD_F52
1

G68 CFG[10] TP5 AT5

1 CFG[11] TP6
H70
G71 CFG[12] 1 OF 20
CFG[13] SKYLAKE-U_BGA1356
H69 D5
G70 CFG[14] RSVD_D5 D4 REV = 1 ?
CFG[15] RSVD_D4 @
B2
E63 RSVD_B2 C2
F63 CFG[16] RSVD_C2
CFG[17] B3
E66 RSVD_B3 A3
F66 CFG[18] RSVD_A3
CFG[19] AW 1 RC71 2 U42@ 1 1M_0402_5%
C CFG_RCOMP E60 RSVD_AW 1 C
CFG_RCOMP E1 YC2
1 XDP_ITP_PMODE E8 RSVD_E1 E2
PAD @ TC166 ITP_PMODE RSVD_E2 2 3 XTAL24_U42_OUT_R
AY2 BA4 GND1 OSC2
2

AY1 RSVD_AY2 RSVD_BA4 BB4 XTAL24_U42_IN_R 1 4

RC162 RSVD_AY1 RSVD_BB4 OSC1 GND2
49.9_0402_1% D1 A4
D3 RSVD_D1 RSVD_A4 C4 24MHZ_6PF_7V24000032
RSVD_D3 RSVD_C4 1 1
CC12 CC11
1

U42@
K46 BB5 2.2P_0402_50V8-C 2.2P_0402_50V8-C
K45 RSVD_K46 TP4 U42@ U42@
RSVD_K45 A69 2 KBL R U42 Use 2
AL25 RSVD_A69 B69
RSVD_AL25 RSVD_B69 need to check with Intel
AL27
RSVD_AL27 AY3 RSVD_AY3
RSVD_AY3 need to use 38.4MHz (30ohm) for Cannonlake-u
C71
RSVD_C71

2
B70 D71
RSVD_B70 RSVD_D71 C70 RC107
F60 RSVD_C70
RSVD_F60 0_0402_5%
C54 U42@
A52 RSVD_C54 D54 @ RC241 2 1 0_0402_5%

1
B RSVD_A52 RSVD_D54 B
BA70 AY4 L36
BA68 RSVD_TP_BA70 TP1 BB3
RSVD_TP_BA68 TP2 need to check with Intel XTAL24_U42_IN_R 4 3 XTAL24_U42_IN
4 3
J71 AY71 VSS_AY71 @ 0_0402_5% 2 1 RC108
J68 RSVD_J71 VSS_AY71 AR56
RSVD_J68 ZVM# XTAL24_U42_OUT_R 1 2 XTAL24_U42_OUT
1 2
1 F65 AW 71
PAD @ TC169 VSS_F65 RSVD_TP_AW 71 EXC24CH900U_4P
1 G65 AW 70
PAD @ TC170 VSS_G65 RSVD_TP_AW 70 U42_EMC_NS@
F61 AP56 SM070004400
E61 RSVD_F61 MSM# C64 PROC_SELECT# 1 U42@
RSVD_E61 PROC_SELECT# TC214 @ PAD RC240 1 2 0_0402_5%

1 OF 20
SKYLAKE-U_BGA1356 L36 Co-layer w/ RC241,RC240
REV = 1 ?
@

Default
A Pin Name Strap Description Configuration A
Value

Security Classification LC Future Center Secret Data Title

CFG[4] Display Port — 1 = eDP Disabled 1 Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (CFG,RESERVED)
Presence strap — 0 = eDP Enabled
* THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EYG10_ES430_ES530
Date: Tuesday, January 09, 2018 Sheet 16 of 60
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2016/12/14 Deciphered Date 2017/12/13 Blank
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EYG10_ES430_ES530
Date: Tuesday, January 09, 2018 Sheet 17 of 60
5 4 3 2 1
 5 4 3 2 1

+1.2V

DDR4 SO-DIMM DDRA_DQ[0..63]

DDRA_DQ[0..63] 5

1
DDRA_DQS#[0..7]
RD91
DDRA_DQS#[0..7] 5
+1.2V +1.2V +1.2V 240_0402_1%
JDDR1A DDRA_DQS[0..7] +1.2V JDDR1B
@
DDRA_DQS[0..7] 5

2
1 2 DDRA_MA3 131 132 DDRA_MA2
DDRA_DQ5 3 VSS_1 VSS_2 4 DDRA_DQ0 5 DDRA_MA3 DDRA_MA1 133 A3 A2 134 DDRA_EVENT# DDRA_MA2 5
5 DQ5 DQ4 6 5 DDRA_MA1 135 A1 EVENT_n 136
DDRA_DQ1 7 VSS_3 VSS_4 8 DDRA_DQ4 DDRA_CLK0 137 VDD_9 VDD_10 138 DDRA_CLK1
9 DQ1 DQ0 10 5 DDRA_CLK0 DDRA_CLK0# 139 CK0_t CK1_t 140 DDRA_CLK1# DDRA_CLK1 5
DDRA_DQS#0 11 VSS_5 VSS_6 12 5 DDRA_CLK0# 141 CK0_c CK1_c 142 DDRA_CLK1# 5
DDRA_DQS0 13 DQS0_C DM0_n/DBIO_n/NC 14 DDRA_PAR 143 VDD_11 VDD_12 144 DDRA_MA0
15 DQS0_t VSS_7 16 DDRA_DQ6 5 DDRA_PAR Parity A0 DDRA_MA0 5
D
DDRA_DQ2 17 VSS_8 DQ6 18 D
19 DQ7 VSS_9 20 DDRA_DQ3 DDRA_BS1# 145 146 DDRA_MA10
DDRA_DQ7 21 VSS_10 DQ2 22 5 DDRA_BS1# 147 BA1 A10/AP 148 DDRA_MA10 5
23 DQ3 VSS_11 24 DDRA_DQ8 DDRA_CS0# 149 VDD_13 VDD_14 150 DDRA_BS0#
DDRA_DQ9 25 VSS_12 DQ12 26 5 DDRA_CS0# DDRA_MA14_WE# 151 CS0_n BA0 152 DDA_MA16_RAS# DDRA_BS0# 5
27 DQ13 VSS_13 28 DDRA_DQ13 5 DDRA_MA14_WE# 153 WE_n/A14 RAS_n/A16 154 DDRA_MA16_RAS# 5
DDRA_DQ12 29 VSS_14 DQ8 30 DDRA_ODT0 155 VDD_15 VDD_16 156 DDRA_MA15_CAS#
31 DQ9 VSS_15 32 DDRA_DQS#1 5 DDRA_ODT0 DDRA_CS1# 157 ODT0 CAS_n/A15 158 DDRA_MA13 DDRA_MA15_CAS# 5
33 VSS_16 DQS1_c 34 DDRA_DQS1 5 DDRA_CS1# 159 CS1_n A13 160 DDRA_MA13 5
35 DM1_n/DBl1_n/NC DQS1_t 36 DDRA_ODT1 161 VDD_17 VDD_18 162
DDRA_DQ10 37 VSS_17 VSS_18 38 DDRA_DQ11 5 DDRA_ODT1 163 ODT1 C0/CS2_n/NC 164 +VREF_CA_DIMM
39 DQ15 DQ14 40 165 VDD_19 VREFCA 166 DDRA_SA2

0.1u_0201_10V6K

2.2U_0402_6.3V6M
DDRA_DQ15 41 VSS_19 VSS_20 42 DDRA_DQ14 167 C1/CS3_n/NC SA2 168
43 DQ10 DQ11 44 DDRA_DQ37 169 VSS_53 VSS_54 170 DDRA_DQ33 1 1
DDRA_DQ16 VSS_21 VSS_22 DDRA_DQ17 DQ37 DQ36

CD1

CD2
45 46 171 172
47 DQ21 DQ20 48 DDRA_DQ32 173 VSS_55 VSS_56 174 DDRA_DQ36 @
DDRA_DQ20 49 VSS_23 VSS_24 50 DDRA_DQ21 175 DQ33 DQ32 176
DQ17 DQ16 DDRA_DQS#4 VSS_57 VSS_58 2 2
51 52 177 178
DDRA_DQS#2 53 VSS_25 VSS_26 54 DDRA_DQS4 179 DQS4_c DM4_n/DBl4_n/NC 180
DDRA_DQS2 55 DQS2_c DM2_n/DBl2_n/NC 56 181 DQS4_t VSS_59 182 DDRA_DQ35
57 DQS2_t VSS_27 58 DDRA_DQ22 DDRA_DQ38 183 VSS_60 DQ39 184
DDRA_DQ23 59 VSS_28 DQ22 60 185 DQ38 VSS_61 186 DDRA_DQ34
61 DQ23 VSS_29 62 DDRA_DQ19 DDRA_DQ39 187 VSS_62 DQ35 188
DDRA_DQ18 63 VSS_30 DQ18 64 189 DQ34 VSS_63 190 DDRA_DQ41
65 DQ19 VSS_31 66 DDRA_DQ29 DDRA_DQ40 191 VSS_64 DQ45 192
DDRA_DQ25 67 VSS_32 DQ28 68 193 DQ44 VSS_65 194 DDRA_DQ45
69 DQ29 VSS_33 70 DDRA_DQ28 DDRA_DQ44 195 VSS_66 DQ41 196
DDRA_DQ24 71 VSS_34 DQ24 72 197 DQ40 VSS_67 198 DDRA_DQS#5
73 DQ25 VSS_35 74 DDRA_DQS#3 199 VSS_68 DQS5_c 200 DDRA_DQS5
+1.2V 75 VSS_36 DQS3_c 76 DDRA_DQS3 201 DM5_n/DBl5_n/NC DQS5_t 202
77 DM3_n/DBl3_n/NC DQS3_t 78 DDRA_DQ43 203 VSS_69 VSS_70 204 DDRA_DQ42
DDRA_DQ30 79 VSS_37 VSS_38 80 DDRA_DQ31 205 DQ46 DQ47 206
81 DQ30 DQ31 82 DDRA_DQ46 207 VSS_71 VSS_72 208 DDRA_DQ47
DDRA_DQ26 83 VSS_39 VSS_40 84 DDRA_DQ27 209 DQ42 DQ43 210
DQ26 DQ27 VSS_73 VSS_74
1

85 86 DDRA_DQ49 211 212 DDRA_DQ48

87 VSS_41 VSS_42 88 213 DQ52 DQ53 214
RD92 RD93 89 CB5/NC CB4/NC 90 DDRA_DQ52 215 VSS_75 VSS_76 216 DDRA_DQ53
240_0402_1% 240_0402_1% 91 VSS_43 VSS_44 92 217 DQ49 DQ48 218
93 CB1/NC CB0/NC 94 DDRA_DQS#6 219 VSS_77 VSS_78 220
2

DDRB_DQS#8 95 VSS_45 VSS_46 96 DDRA_DQS6 221 DQS6_c DM6_n/DBl6_n/NC 222

DDRB_DQS8 97 DQS8_c DM8_n/DBI8_n/NC 98 223 DQS6_t VSS_79 224 DDRA_DQ54
C
99 DQS8_t VSS_47 100 DDRA_DQ50 225 VSS_80 DQ54 226 C
101 VSS_48 CB6/NC 102 227 DQ55 VSS_81 228 DDRA_DQ51
103 CB2/NC VSS_49 104 DDRA_DQ55 229 VSS_82 DQ50 230
105 VSS_50 CB7/NC 106 231 DQ51 VSS_83 232 DDRA_DQ57
107 CB3/NC VSS_51 108 CPU_DRAMRST# DDRA_DQ56 233 VSS_84 DQ60 234
DDRA_CKE0 109 VSS_52 RESET_n 110 DDRA_CKE1 CPU_DRAMRST# 6 235 DQ61 VSS_85 236 DDRA_DQ61
5 DDRA_CKE0 111 CKE0 CKE1 112 DDRA_CKE1 5 1 DDRA_DQ60 237 VSS_86 DQ57 238
DDRA_BG1 113 VDD_1 VDD_2 114 DDRA_ACT# CD3 239 DQ56 VSS_87 240 DDRA_DQS#7
5 DDRA_BG1 DDRA_BG0 115 BG1 ACT_n 116 DDRA_ALERT# DDRA_ACT# 5 0.1u_0201_10V6K 241 VSS_88 DQS7_c 242 DDRA_DQS7
5 DDRA_BG0 117 BG0 ALERT_n 118 DDRA_ALERT# 5 @ 243 DM7_n/DBl7_n/NC DQS7_t 244
DDRA_MA12 VDD_3 VDD_4 DDRA_MA11 2 DDRA_DQ59 VSS_89 VSS_90 DDRA_DQ63
119 120 245 246
5 DDRA_MA12 DDRA_MA9 121 A12 A11 122 DDRA_MA7 DDRA_MA11 5 247 DQ62 DQ63 248
5 DDRA_MA9 123 A9 A7 124 DDRA_MA7 5 DDRA_DQ58 249 VSS_91 VSS_92 250 DDRA_DQ62
DDRA_MA8 125 VDD_5 VDD_6 126 DDRA_MA5 251 DQ58 DQ59 252
5 DDRA_MA8 DDRA_MA6 127 A8 A5 128 DDRA_MA4 DDRA_MA5 5 SMB_CLK_S3 253 VSS_93 VSS_94 254 SMB_DATA_S3
5 DDRA_MA6 129 A6 A4 130 DDRA_MA4 5 7,40 SMB_CLK_S3 +VDD_SPD SCL SDA DDRA_SA0 SMB_DATA_S3 7,40
+3VS RD1 1 2 0_0603_SM @ 255 256
VDD_7 VDD_8 257 VDDSPD SA0 258

2.2U_0402_6.3V6M
VPP_1 VTT DDRA_SA1 +0.6VS

0.1u_0201_10V6K
1 1 259 260
VPP_2 SA1

CD4

CD5
261 262
ARGOS_D4AR0-26001-1P40 GND_1 GND_2
ME@ 2 2
ARGOS_D4AR0-26001-1P40
ME@

+2.5V_DDR RD2 1 2 0_0603_SM @ +VPP

+1.2V

1
CD117 Note:
1

0.1u_0201_10V6K +0.6VS +2.5V_DDR

2 VREF trace width:20 mils at least Layout Note:
RD3
1K_0402_1% Spacing:20mils to other signal/planes Place near DIMM
Place near DIMM scoket
2

1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K
B B

+VREF_CA_DIMM 1 1 1 1 1 1 1 1

CD118

CD11
RD4 1 2 2_0402_5%

CD6

CD7

CD8

CD@

CD9

CD10

CD@

CD12
5 DDR_SA_VREFCA
@
1
2 2 2 2 2 2 2 2
CD13 1
1

0.022U_0201_6.3V6-K
RD5 CD14
2 1K_0402_1% 0.1u_0201_10V6K CD@
2
1

RD6 10uF change to 0402 Bourne 20170501

24.9_0402_1%

+1.2V
2

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CD20

CD28

CD29

CD30

CD31
CD@

CD19

CD21

CD22

CD23

CD24

CD25

CD26

CD27

CD@

CD32

CD@

CD33

CD34
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

CD@
+3VS +3VS +3VS
10uF change to 0402 Bourne 20170501
+1.2V
1

RD7 RD8 RD9

0_0402_5% 0_0402_5% 0_0402_5%
@ @
@
4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

0.1u_0201_10V6K

33P_0402_50V8J

33P_0402_50V8J
0.1u_0201_10V6K
2

EMC_NS@

EMC_NS@

EMC_NS@

1 1 1 1 1 1
EMC_NS@

CD17

CD18

CD37
CD15

CD16

RF@

CD36

RF@

A DDRA_SA0 DDRA_SA1 DDRA_SA2 A

2 2 2 2 2 2
1

RD10 RD11 RD12

0_0402_5% 0_0402_5% 0_0402_5%
@ @ @
For EMC Near JDDRL1
2

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 DDR4 SO-DIMM
SPD Address = A0 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EYG10_ES430_ES530
Date: Tuesday, January 09, 2018 Sheet 18 of 60
5 4 3 2 1
 5 4 3 2 1

N16x GPIO

GPIO I/O ACTIVE Function Description Performance Mode P0 TDP and EDP-Continuous current (GDDR5)
GPIO0 OUT - GPU Core VDD PWM control signal
FBVDDQ Other
Min FBVDD (GPU+Mem) (1.05V)
GPIO1 OUT N/A FB Enable for GC6 2.0 GPU Mem Core Clk NVVDD (1.35V) (1.35V) (6) (3.3V)
Products (W) (W) (MHz) (V) (A) (W) (A) (W) (A) (W) (mA) (W) (mA) (W)
D GPIO2 OUT N/A D

N16S-GMR 16 1.6 849 TBD 19 TBD 2 TBD 4.2 TBD 800 TBD 60 TBD
GPIO3 OUT N/A
N16S-GTR 18 1.7 967 26.5 2 4.2 800 60
GPIO4 OUT N/A

GPIO5 OUT N/A GPU power sequencing---3V3_MAIN_EN

GPIO6 IN - GPU wake signal for GC6 2.0

GPIO7 OUT N/A

GPIO8 I/O - System side PCIe reset Monitor

GPIO9 I/O N/A 2.2K Pull-up

GPIO10 OUT FBVREF_ALTV for GDDR5

GPIO11 OUT - N16x Multi-level Straps

GPIO12 IN AC Power Detect Input (10K pull High)
Physical Logical Logical Logical Logical
GPIO13 OUT - Phase Shedding Strapping pin Power Rail Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0
ROM_SCLK +3VGS SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED
GPIO14 IN N/A
ROM_SI +3VGS RAM_CFG[3] RAM_CFG[2] RAM_CFG[1] RAM_CFG[0]
C C
GPIO15 IN N/A ROM_SO +3VGS DEVID_SEL PCIE_CFG SMB_ALT_ADDR VGA_DEVICE
STRAP0 +3VGS Reserved(keep pull-up and pull-down footprint and stuff 50Kohm pull-up)
GPIO16 N/A
STRAP1 +3VGS

GPIO17 IN N/A STRAP2 +3VGS

Reserved(keep pull-up and pull-down footprint and not stuff by default)
STRAP3 +3VGS
GPIO18 IN N/A
STRAP4 +3VGS

GPIO19 IN N/A

GPIO20 N/A

GPIO21 OUT GPU PCIe self-reset control

OVERT OUT Active Low Thermal Catastrophic Over Temperature

N15V-GM Power Sequence

B B

+3VG_AON

+VGA_CORE

tNVVDD >0
+1.05VS_VGA

+1.35VGS
tPEX_VDD >0

1. all power rail ramp up time should be larger than 40us~4ms

Other Power rail

+3VG_AON
A A

Tpower-off <10ms

Security Classification LC Future Center Secret Data Title

1.all GPU power rails should be turned off within 10ms
2. Optimus system VDD33 avoids drop down earlier than NVDD and FBVDDQ
Issued Date 2015/08/20 Deciphered Date 2016/08/20 VGA Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EYG10_ES430_ES530
Date: Tuesday, January 09, 2018 Sheet 19 of 60
5 4 3 2 1
 5 4 3 2 1

PEX_DVDD/Q Decouling
+1.0VGS
UV1A ? COMMON INS34146449
1/14 PCI_EXPRESS
MLCC N16 N17 location
Under Near GPU and PS
1.0uF 1 1

4.7U_0402_6.3V6M
Under

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

22U_0402_4V6-M
4.7uF 0 1

1U_0402_6.3V6K
D AA22 PEX_DVDD D

OPTN17@

OPTN17@

OPTN17@

OPTN17@

OPTN17@
PLT_RST_VGA# PEX_DVDD_1 1 1 1 1 2 2 1 N16:+1.05VGS(recommend)

CV668
AC7 AB23

OPT@

CV48

CV49

OPT@

CV669

CV670

CV671

CV43
26 PLT_RST_VGA# PEX_DVDD_2 Near
CLK_REQ_GPU# PEX_RST_N PEX_DVDD_3
AC24 +1.0VGS(Used) 4.7uF 1 2
AC6 AD25 N17:+1.0VGS
PEX_CLKREQ_N PEX_DVDD_4 AE26
CLK_PCIE_GPU AE8 PEX_DVDD_5 AE27
2 2 2 2 1 1 2 10uF 0 2 Midway
10 CLK_PCIE_GPU CLK_PCIE_GPU# AD8 PEX_REFCLK PEX_DVDD_6
10 CLK_PCIE_GPU# PEX_REFCLK_N
PCIE_CRX_GTX_P0 PCIE_CRX_C_GTX_P0
22uF 0 1
OPT@ CV10 1 2 0.22U_0201_6.3V6-K AC9
PCIE_CRX_GTX_N0 OPT@ CV13 1 2 0.22U_0201_6.3V6-K PCIE_CRX_C_GTX_N0 AB9 PEX_TX0 PEX_HVDD
PEX_TX0_N +3V_1.8VGS
PCIE_CTX_C_GRX_P0 AG6 Under GPU OPTN17@
PCIE_CTX_C_GRX_N0 PEX_RX0 (below 150mils) Near GPU GPU and PS PEX_HVDD/Q Decouling
AG7 AA10 PEX_HVDD RV42 2 1 0_0805_5%
PEX_RX0_N PEX_HVDD_1

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
AA12

22U_0402_4V6-M
PCIE_CRX_GTX_P1 PCIE_CRX_C_GTX_P1 PEX_HVDD_2 +1.0VGS

1U_0402_6.3V6K

33P_0402_50V8J
OPT@ CV8 1 2 0.22U_0201_6.3V6-K AB10 AA13

OPTN17@

OPTN17@
PCIE_CRX_GTX_N1 PCIE_CRX_C_GTX_N1 PEX_TX1 PEX_HVDD_3 1 1 1 1 1 1 2 2 1 1 MLCC N16 N17 location

CV672

OPTN17@

OPT_RF@
OPT@ CV9 1 2 0.22U_0201_6.3V6-K AC10 AA16 OPTN16@

OPT@

CV33

CV673

CV763

OPT@

CV675

OPT@

CV676

CV39

OPT@

CV677

CV215
PEX_TX1_N PEX_HVDD_4

CV37
AA18 RV43 2 1 0_0805_5%

@
PCIE_CTX_C_GRX_P1 AF7 PEX_HVDD_5 AA19
PCIE_CTX_C_GRX_N1 AE7 PEX_RX1 PEX_HVDD_6 AA20 2 2 2 2 2 2 1 1 2 2
1.0uF 1 4 Under
PEX_RX1_N PEX_HVDD_7 AA21
PCIE_CRX_GTX_P2 OPT@ CV6 1 2 0.22U_0201_6.3V6-K PCIE_CRX_C_GTX_P2 AD11 PEX_HVDD_8 AB22 PEX_HVDD 4.7uF 1 2 Near
PCIE_CRX_GTX_N2 OPT@ CV7 1 2 0.22U_0201_6.3V6-K PCIE_CRX_C_GTX_N2 AC11 PEX_TX2 PEX_HVDD_9 AC23 N16:+1.05VGS(recommend)
PEX_TX2_N PEX_HVDD_10 AD24 +1.0VGS(Used)
PCIE_CTX_C_GRX_P2 AE9 PEX_HVDD_11 AE25 Change by Bourne 20170412 N17:+1.8VGS 10uF 1 2 Midway
PCIE_CTX_C_GRX_N2 AF9 PEX_RX2 PEX_HVDD_12 AF26
PEX_RX2_N PEX_HVDD_13 AF27 22uF 1 1
PCIE_CRX_GTX_P3 PCIE_CRX_C_GTX_P3 PEX_HVDD_14 For RF
OPT@ CV4 1 2 0.22U_0201_6.3V6-K AC12
PCIE_CRX_GTX_N3 OPT@ CV5 1 2 0.22U_0201_6.3V6-K PCIE_CRX_C_GTX_N3 AB12 PEX_TX3
PEX_TX3_N
PCIE_CTX_C_GRX_P3 AG9
PCIE_CTX_C_GRX_N3 AG10 PEX_RX3
PEX_RX3_N
AB13
AC13 PEX_TX4
PEX_TX4_N
9 PCIE_CRX_GTX_N[0..3] AF10
AE10 PEX_RX4
PEX_RX4_N +3.3V_1.8V_AON
C 9 PCIE_CRX_GTX_P[0..3]
AD14 OPTN16@
PEX_PLL_HVDD/Q Decouling C
AC14 PEX_TX5 AA8 PEX_PLL_HVDD RV227 1 2 0_0402_5%
9 PCIE_CTX_C_GRX_N[0..3] PEX_TX5_N PEX_PLL_HVDD_1 AA9
PEX_PLL_HVDD
PEX_PLL_HVDD_2 N16:+3.3V_AON MLCC N16 N17 location

0.1u_0201_10V6K
AE12 +3V_1.8VGS
9 PCIE_CTX_C_GRX_P[0..3] PEX_RX5
AF12
PEX_RX5_N 1 OPTN17@ N17:+1.8VGS 0.1uF 1 1

OPT@
Near

CV55
RV246 1 2 0_0402_5%
AC15
AB15 PEX_TX6
PEX_TX6_N 2 Change by Bourne 20170412
AG12
AG13 PEX_RX6
PEX_RX6_N
AB16 Under GPU
PEX_TX7
AC16
PEX_TX7_N
(below 150mils)
AF13
AE13 PEX_RX7
PEX_RX7_N
AD17
AC17 PEX_TX8
PEX_TX8_N
AE15
AF15 PEX_RX8
PEX_RX8_N
AC18
AB18 PEX_TX9
PEX_TX9_N
AG15
AG16 PEX_RX9
PEX LANES 15 - 4 ARE DEFEATURED

PEX_RX9_N
AB19
AC19 PEX_TX10
PEX_TX10_N
AF16
AE16 PEX_RX10
PEX_RX10_N
AD20
AC20 PEX_TX11 +3.3V_1.8V_AON +3V_1.8VGS
B B
PEX_TX11_N
AE18
PEX_RX11

2
AF18
PEX_RX11_N RV4 RV40
AC21 0_0402_5% 0_0402_5%
AB21 PEX_TX12 @ @
PEX_TX12_N
+3.3V_1.8V_AON

1
AG18
AG19 PEX_RX12
PEX_RX12_N 1
CV23

2
AD23 0.1u_0201_10V6K
PEX_TX13 RV44
AE23 @
PEX_TX13_N 2 10K_0402_5%

2
AF19 OPT@
AE19 PEX_RX13

1
PEX_RX13_N
1 3 CLK_REQ_GPU#
AF24 10 GPU_CLKREQ#
AE24 PEX_TX14 QV5
PEX_TX14_N

2
LSI1012XT1G_SC-89-3
AE21
AF21 PEX_RX14 OPT@ RV46
PEX_RX14_N 10K_0402_5%
@
AG24 @
AG25 PEX_TX15 RV48 1 2 0_0402_5%

1
PEX_TX15_N
AG21
AG22 PEX_RX15
PEX_RX15_N

AF25 PEX_TERMP 2.49K_0402_1% 2 OPT@ 1 RV35

PEX_TERMP

N17S-G1-A1_GB2C-64-595 @

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 GPU_PCIE Interface

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EYG10_ES430_ES530
Date: Tuesday, January 09, 2018 Sheet 20 of 60
5 4 3 2 1
 5 4 3 2 1

27,28 FBA_D[0..63]

27,28 FBA_CMD[31..0]

27,28 FBA_EDC[7..0]

27,28 FBA_DBI[7..0]

UV1B ? COMMON INS34147394

2/14 FBA
FBA_D0 E18
FBA_D1 F18 FBA_D0
D D
FBA_D2 E16 FBA_D1
FBA_D3 F17 FBA_D2
FBA_D4 D20 FBA_D3
FBA_D5 D21 FBA_D4
FBA_D6 F20 FBA_D5
FBA_D7 E21 FBA_D6
FBA_D8 E15 FBA_D7
FBA_D9 D15 FBA_D8
FBA_D10 F15 FBA_D9
FBA_D11 F13 FBA_D10
FBA_D12 C13 FBA_D11
FBA_D13 B13 FBA_D12
FBA_D14 E13 FBA_D13
FBA_D15 FBA_D14 +1.35VGS
D13
FBA_D16 B15 FBA_D15
FBA_D17 C16 FBA_D16
FBA_D18 A13 FBA_D17
FBA_D19 A15 FBA_D18
FBA_D20 B18 FBA_D19

1
FBA_D21 A18 FBA_D20
FBA_D22 A19 FBA_D21 RV210 RV209
FBA_D23 FBA_D22 10K_0402_1% 10K_0402_1%
C19
FBA_D24 FBA_D23 OPT@ OPT@
B24
FBA_D25 C23 FBA_D24

2
FBA_D26 A25 FBA_D25
FBA_D26 FBA_CMD14
FBA_D27 A24
FBA_D28 A21 FBA_D27
FBA_D28 FBA_CMD30
FBA_D29 B21
FBA_D30 C20 FBA_D29
FBA_D31 C21 FBA_D30
FBA_D32 R22 FBA_D31
FBA_D32 FBA_CMD13
FBA_D33 R24 C27 FBA_CMD0
FBA_D34 T22 FBA_D33 FBA_CMD0 C26 FBA_CMD1
FBA_D34 FBA_CMD1 FBA_CMD29
FBA_D35 R23 E24 FBA_CMD2
FBA_D36 N25 FBA_D35 FBA_CMD2 F24 FBA_CMD3
FBA_D37 N26 FBA_D36 FBA_CMD3 D27 FBA_CMD4

1
FBA_D38 N23 FBA_D37 FBA_CMD4 D26 FBA_CMD5
C FBA_D39 FBA_D38 FBA_CMD5 FBA_CMD6 RV212 RV211 C
N24 F25
FBA_D40 V23 FBA_D39 FBA_CMD6 F26 FBA_CMD7 10K_0402_1% 10K_0402_1%
FBA_D41 FBA_D40 FBA_CMD7 FBA_CMD8 OPT@ OPT@
V22 F23
FBA_D42 T23 FBA_D41 FBA_CMD8 G22 FBA_CMD9

2
FBA_D43 U22 FBA_D42 FBA_CMD9 G23 FBA_CMD10
FBA_D44 Y24 FBA_D43 FBA_CMD10 G24 FBA_CMD11
FBA_D45 AA24 FBA_D44 FBA_CMD11 F27 FBA_CMD12
FBA_D46 Y22 FBA_D45 FBA_CMD12 G25 FBA_CMD13
FBA_D47 AA23 FBA_D46 FBA_CMD13 G27 FBA_CMD14
FBA_D48 AD27 FBA_D47 FBA_CMD14 G26 FBA_CMD15
FBA_D49 AB25 FBA_D48 FBA_CMD15 M24 FBA_CMD16
FBA_D50 AD26 FBA_D49 FBA_CMD16 M23 FBA_CMD17
FBA_D51 AC25 FBA_D50 FBA_CMD17 K24 FBA_CMD18
FBA_D52 AA27 FBA_D51 FBA_CMD18 K23 FBA_CMD19
FBA_D53 AA26 FBA_D52 FBA_CMD19 M27 FBA_CMD20
FBA_D54 W26 FBA_D53 FBA_CMD20 M26 FBA_CMD21
FBA_D55 Y25 FBA_D54 FBA_CMD21 M25 FBA_CMD22
FBA_D56 R26 FBA_D55 FBA_CMD22 K26 FBA_CMD23
FBA_D57 T25 FBA_D56 FBA_CMD23 K22 FBA_CMD24
FBA_D58 N27 FBA_D57 FBA_CMD24 J23 FBA_CMD25
FBA_D59 R27 FBA_D58 FBA_CMD25 J25 FBA_CMD26
FBA_D60 V26 FBA_D59 FBA_CMD26 J24 FBA_CMD27
FBA_D61 V27 FBA_D60 FBA_CMD27 K27 FBA_CMD28
FBA_D62 W27 FBA_D61 FBA_CMD28 K25 FBA_CMD29
FBA_D63 W25 FBA_D62 FBA_CMD29 J27 FBA_CMD30
FBA_D63 FBA_CMD30 J26 FBA_CMD31 +1.35VGS
FBA_CMD31 B19
FBA_DBI0 D19 FBA_CMD32 F22 RV121 2 @ 1 60.4_0402_1%
FBA_DBI1 D14 FBA_DQM0 FBA_CMD34 J22 RV122 2 @ 1 60.4_0402_1%
FBA_DBI2 C17 FBA_DQM1 FBA_CMD35
FBA_DBI3 C22 FBA_DQM2
FBA_DBI4 P24 FBA_DQM3
FBA_DBI5 W24 FBA_DQM4
FBA_DBI6 AA25 FBA_DQM5
FBA_DBI7 U25 FBA_DQM6
FBA_DQM7

B
FBA_EDC0 E19 B
FBA_EDC1 C15 FBA_DQS_WP0
FBA_EDC2 B16 FBA_DQS_WP1 D24 FBA_CLK0
FBA_EDC3 B22 FBA_DQS_WP2 FBA_CLK0 FBA_CLK0# FBA_CLK0 27
D25
FBA_EDC4 R25 FBA_DQS_WP3 FBA_CLK0_N N22 FBA_CLK1 FBA_CLK0# 27
FBA_EDC5 W23 FBA_DQS_WP4 FBA_CLK1 FBA_CLK1# FBA_CLK1 28
M22
FBA_EDC6 AB26 FBA_DQS_WP5 FBA_CLK1_N FBA_CLK1# 28
FBA_EDC7 T26 FBA_DQS_WP6
FBA_DQS_WP7

F19 D18 FBA_WCLK01

C14 FBA_DQS_RN0 FBA_WCK01 C18 FBA_WCLK01# FBA_WCLK01 27
FBA_DQS_RN1 FBA_WCK01_N FBA_WCLK23 FBA_WCLK01# 27
A16 D17
FBA_DQS_RN2 FBA_WCK23 FBA_WCLK23# FBA_WCLK23 27
A22 D16
P25 FBA_DQS_RN3 FBA_WCK23_N T24 FBA_WCLK45 FBA_WCLK23# 27
FBA_DQS_RN4 FBA_WCK45 FBA_WCLK45# FBA_WCLK45 28
W22 U24
AB27 FBA_DQS_RN5 FBA_WCK45_N V24 FBA_WCLK67 FBA_WCLK45# 28
FBA_DQS_RN6 FBA_WCK67 FBA_WCLK67# FBA_WCLK67 28 Place close to BGA
T27 V25
FBA_DQS_RN7 FBA_WCK67_N FBA_WCLK67# 28 +FB_PLLAVDD FB_PLL/Q Decouling
200mA PEX_HVDD
LV10 PEX_HVDD
F16 Under GPU Near GPU 2 1 N16:+1.05VGS(recommend) MLCC N16 N17 location
FB_PLL_AVDD_1 SBK160808T-300Y-N +1.0VGS(Used)
+FB_PLLAVDD
0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

22U_0402_4V6-M

P22 OPT@ N17:+1.8VGS 0.1uF 2 4

FB_PLL_AVDD_2 Under
OPTN17@

1 1 1 1 1
OPTN17@

Place close to ball

CV710

OPT@

CV711

CV113

OPT@

CV111

H22
OPT@

CV112

FB_REFPLL_AVDD 30ohms (ESR=0.01) 0603 Bead

22uF 1 1 Near
0.1u_0201_10V6K

0.1u_0201_10V6K

2 2 2 2 2
0.1u_0201_10V6K

OPTN17@

OPTN17@

2 1 1
OPT@

CV115

CV58

CV59

1 2 2
D23
FB_VREF

N17S-G1-A1_GB2C-64-595 @
A A

N17S Add 2x0.1u

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 GPU_MEM Interface

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EYG10_ES430_ES530
Date: Tuesday, January 09, 2018 Sheet 21 of 60
5 4 3 2 1
 5 4 3 2 1

+VGA_CORE
Under GPU 12x4.7uF 5x1uF For RF
CV89 CV90 CV91 CV92 CV688 CV76 CV77 CV78 CV79 CV80 CV81 CV82 CV83 CV84 CV85 CV86 CV87 CV213
+VGA_CORE

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

33P_0402_50V8J
OPTN17@
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

OPTNS@

OPTN17@

OPTNS@

OPTNS@

OPTN17@

OPT_RF@
OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
OPT@
+VGA_CORE
UV1C ? COMMON INS34149135 UV1G ? COMMON INS34149676 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
11/14 NVVDD 6/14 XVDD
K10
K12 VDD_001
K14 VDD_002 G1 N4
K16 VDD_003 G2 XVDD_1 XVDD_36 N5
K18 VDD_004 G3 XVDD_2 XVDD_37 N7
D D
L13 VDD_005 G4 XVDD_3 XVDD_38 P3
L15 VDD_006 G5 XVDD_4 XVDD_39 P4
M10 VDD_007 G6 XVDD_5 XVDD_40 P6
M12 VDD_008 G7 XVDD_6 XVDD_41 R1
Near GPU 4x4.7uF 11x10uF 4x22uF Near VRAM
M16 VDD_009 H3 XVDD_7 XVDD_42 R2 CV93 CV94 CV95 CV96 CV88 CV98 CV99 CV100 CV101 CV102 CV693 CV694 CV695 CV696 CV697 CV103 CV104 CV105 CV704 CV214 CV705 CV706
M18 VDD_010 H4 XVDD_8 XVDD_43 R3
N11 VDD_011 H6 XVDD_9 XVDD_44 R4

10U_0603_6.3V6M

10U_0603_6.3V6M
VDD_012 XVDD_10 XVDD_45

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

33P_0402_50V8J
N13 J1 R5

OPTN17_NS@

OPTN17_NS@

OPTN17_NS@
VDD_013 XVDD_11 XVDD_46

OPTN17@

OPTN17@

OPTN17_NS@

OPTN17@

OPTN17@

RF_NS@
N15 J2 R6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2

OPTNS@

OPTNS@

OPTN17@

OPTN17@

OPTN17@

OPTN17@

OPTNS@

OPTN17@

OPTNS@

OPTNS@
VDD_014 XVDD_12 XVDD_47

OPT@

OPT@

OPT@
N17 J3 R7
P14 VDD_015 J4 XVDD_13 XVDD_48 T1
R11 VDD_016 J5 XVDD_14 XVDD_49 T2
R13 VDD_017 J6 XVDD_15 XVDD_50 T3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1
R15 VDD_018 J7 XVDD_16 XVDD_51 T4
R17 VDD_019 K1 XVDD_17 XVDD_52 T5
T10 VDD_020 K2 XVDD_18 XVDD_53 T6
T12 VDD_021 K3 XVDD_19 XVDD_54 T7
VDD_022 XVDD_20 XVDD_55 CV88 Use virtual Symbol for diff value For RF
T16 K4 U3
T18 VDD_023 K5 XVDD_21 XVDD_56 U4
U13 VDD_024 K6 XVDD_22 XVDD_57 U6
U15 VDD_025 K7 XVDD_23 XVDD_58 V1 NVVDD/Q Decouling
V10 VDD_026 L3 XVDD_24 XVDD_59 V2 +VGA_CORE
V12 VDD_027 L4 XVDD_25 XVDD_60 V3
V14 VDD_028 M1 XVDD_26 XVDD_61 V4 MLCC N16 N17 location
V16 VDD_029 M2 XVDD_27 XVDD_62 V5 RV6 1 @ 2 0_0402_5%
V18 VDD_030 M3 XVDD_28 XVDD_63 V6 RV21 1 2 0_0402_5%
VDD_031 XVDD_29 XVDD_64 @
M4
XVDD_30 XVDD_65
V7 4.7uF 10 12
M5 W1
M7 XVDD_31 XVDD_66 W2 Under
F2 NVVDD_VCC_SENSE N1 XVDD_32 XVDD_67 W3 1.0uF 4 5
VDD_SENSE F1 NVVDD_VSS_SENSE N2 XVDD_33 XVDD_68 W4
GND_SENSE N3 XVDD_34 XVDD_69
XVDD_35 47uF 1 0
NVVDD_VCC_SENSE
NVVDD_VSS_SENSE NVVDD_VCC_SENSE 57
NVVDD_VSS_SENSE 57
10uF 0 11
C trace width: 16mils Near C

N17S-G1-A1_GB2C-64-595 N17S-G1-A1_GB2C-64-595 differential voltage sensing. 22uF 1 4

differential signal routing.
@

4.7uF 5 4
330uF 1 2

+1.35VGS UV1D ? COMMON INS34149225

12/14 FBVDDQ

B26
C25 FBVDDQ_01
E23 FBVDDQ_02 +1.35VGS
FBVDDQ_03 1x10uF 3x22uF +VGA_CORE UV1F ? COMMON INS34149408
E26
F14 FBVDDQ_04 Under GPU(below 150mils) 8x10uF 2x10uF Near GPU 7/14 VDDS
F21 FBVDDQ_05 CV32 CV686 CV29 CV30 CV683 CV682 CV681 CV680 CV679 CV678 CV687 CV25 CV684 CV685
G13 FBVDDQ_06
FBVDDQ_07 L11

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

10U_0603_6.3V6M
G14 VDDS_1
FBVDDQ_08 L17
0.1U_0402_25V6

10U_0402_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

OPTN17_NS@
G15 VDDS_2

OPTN17@
FBVDDQ_09 1 1 1 2 M14
OPTN17@

OPTN17@

OPTN17@
G16 1 2 1 1 1 1 1 1 1 1 VDDS_3
OPTNS@

OPTN17@

OPTN17@

OPTN17@

OPT@

OPT@
FBVDDQ_10 P10
OPTNS@

OPT@

G18 VDDS_4
OPT@

FBVDDQ_11 P12
G19 VDDS_5
FBVDDQ_12 P16
G20 2 2 2 1 VDDS_6
FBVDDQ_13 2 1 2 2 2 2 2 2 2 2 P18
G21 VDDS_7
FBVDDQ_14 T14
L22 VDDS_8
FBVDDQ_19 U11
L24 VDDS_9
FBVDDQ_20 U17
L26 VDDS_10
M21 FBVDDQ_21
N21 FBVDDQ_22
B
R21 FBVDDQ_23 B
FBVDDQ_24 CV32 CV686 Use virtual Symbol for diff value
T21
V21 FBVDDQ_25
W21 FBVDDQ_26
H24 FBVDDQ_27
FBVDDQ_15 F4 TV6 @ 1 OPTN16@
H26 VDDS_SENSE
FBVDDQ_16 F3 FB_CLAMP RV1399 1 2 10K_0402_5%
J21 GNDS_SENSE
K21 FBVDDQ_17
FBVDDQ_18
N17S-G1-A1_GB2C-64-595

@
FBVDD/Q Decouling

CALIBRATION PIN GDDR5 MLCC N16 N17 location

FB_CAL_x_PD_VDDQ 40.2Ohm 0.1uF 2 0

FB_CAL_x_PU_GND 40.2Ohm 1.0uF 2 8

Under
FB_CAL_xTERM_GND 60.4Ohm 4.7uF 2 0
10uF 0 2
10uF 1 1
Near
+1.35VGS
22uF 1 3
D22 RV55 1 OPT@ 2 40.2_0402_1%
FB_CAL_PD_VDDQ

C24 RV56 1 OPT@ 2 40.2_0402_1%

FB_CAL_PU_GND
A A

B25 RV57 1 OPT@ 2 60.4_0402_1%

FB_CAL_TERM_GND
Place near balls

Security Classification LC Future Center Secret Data Title

N17S-G1-A1_GB2C-64-595
Issued Date 2015/08/20 Deciphered Date 2016/08/20 GPU_+VGA_CORE,FBVDDQ
@

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EYG10_ES430_ES530
Date: Tuesday, January 09, 2018 Sheet 22 of 60
5 4 3 2 1
 5 4 3 2 1

+3V_1.8VGS
Under GPU Near GPU N16 3V3_MAIN(N17 VDD_18) Decouling Discharge
@
UV1E ? COMMON INS34151253 +VDD18 RV54 1 2 0_0402_5%
14/14 VDD18
+1.35VGS
MLCC N16 N17 location

0.1u_0201_10V6K

0.1u_0201_10V6K

1U_0402_6.3V6K

4.7U_0402_6.3V6M
Change by Bourne 20170412
G8 +5VALW
VDD18_1 1 1 1
1

OPT@

OPT@

OPT@
G9

1
CV50

OPT@

CV52

CV53
VDD18_2 0.1uF 2 2

CV51
G10 Under
1V8_AON_1 G12 RV67

1
1V8_AON_2 2 2 2 470_0603_5%
2 RV69
1.0uF 1 1 OPTNS@
47K_0402_5%

3 2
Near OPTNS@ D
4.7uF 1 1

2
FBVDDQ_PWR_EN# 5 QV27B
G
LBSS138DW1T1G_SOT363-6

6
D
S

4
+3.3V_1.8V_AON FBVDDQ_PWR_EN 2
D
QV27A OPTNS@ D
Under GPU Near GPU G
VDD_AON @ S LBSS138DW1T1G_SOT363-6
RV220 1 2 0_0402_5%

1
N16 3V3_AON(N17 1V8_AON) Decouling OPTNS@

0.1u_0201_10V6K

0.1u_0201_10V6K

1U_0402_6.3V6K

4.7U_0402_6.3V6M
N17S-G1-A1_GB2C-64-595
MLCC N16 N17 location

OPTN17@
1 1 1 1
@

OPT@

CV716

OPT@

CV717

OPT@
CV714

CV715
2 2 2 2
0.1uF 1 2 Under +3.3V_1.8V_AON

+5VALW

1
1.0uF 1 1
Near RV7

2
470_0603_5%
4.7uF 1 1 RV9 OPTNS@
47K_0402_5%

3 2
OPTNS@
D

1
PXS_PWREN# 5 QV35B
G
2N7002KDWH_SOT363-6

6
D
PXS_PWREN 2 QV35A S OPTNS@
PXE_VDD & 1V8_AON

4
G +3V_1.8VGS
2N7002KDWH_SOT363-6
S OPTNS@

1
PXS_PWREN RV214 1 OPT@ 2 0_0402_5% PXS_PWR_EN_R
8,55 PXS_PWREN PXS_PWR_EN_R 56 1
RV72 CV74
470_0603_5% 10U_0603_6.3V6M
1 OPTNS@
2
GC6@
RV213

2
100K_0402_5%
@

1
D
2

2 QV20
G 2N7002KW_SOT323-3
C C
OPTNS@
S
+3VS +3.3V_1.8V_AON

3
1.8VGS_PWR_EN 1 2
2

DV3
LRB751V-40T1G_SOD323-2 RV62 RV49
OPT@ 10K_0402_5% 10K_0402_5%
OPT@ @
DV7
1

PXS_PWREN 2 +1.0VGS
PXE_VDD_EN RV63 PXE_VDD_EN_R
1 2 1
DGPU_PWROK 2 RV27 1 3 PXE_VDD_EN_R 55,56 RV109 change to 470ohm 0805 for N16 GPU
8,23,57 DGPU_PWROK 10K_0402_5%
0.22U_0201_6.3V6-K
1

0_0402_5% OPT@ 1
LBAT54AWT1G_SOT323-3
OPT@

CV726
RV64
@ OPT@
10K_0402_5%

1
@ RV109
2 RV102
5.11_0805_1%
5.11_0805_1%
2

+5VALW @
OPTN17@

2
1
RV100
47K_0402_5%
+1.8VG_AON TO +1.8VGS

1
OPT@

D
+1.0VGS_PWR_EN# 2 QV15
G AO3402_SOT-23-3
OPTN17@

S
+3VS +3VALW +3VS

3
1
D
PXE_VDD_EN_R 2
1

1
+1.0VGS
B G QV17 B
RV114 RV236 RV237

1
2N7002KW_SOT323-3 D
82K_0402_1% 10K_0402_5% 10K_0402_5% @ S 2
@ @

3
1

DV8 G QV34
PXS_PWREN RV51 1 @ 2 0_0402_5% 2 RV238 OPT@ 2N7002KW_SOT323-3
2

2
PEX_PWROK
1 1K_0402_5% S
@ NVVDD_EN 57

3
1.8VGS_PWR_EN RV117 1 2 0_0402_5% 3 @ OPTN16@

1
D
26,56 1.8VGS_PWR_EN
1

C 2 QV31
2

LBAT54AWT1G_SOT323-3 2
@ QV32 LBSS139WT1G_SC70-3
1

1 G
+3V_1.8VGS RV116 1 2 0_0402_5% @ B CV756 S
RV115 @ @

3
1 E 0.1u_0201_10V6K
@ 100K_0402_1% CV755
3

RV235 1 2 0_0402_5%
0.1u_0201_10V6K
@ 2 @
@
2

2 MMBT3904WH_SOT323-3

+VGA_CORE

+5VALW

1
RV240

2
10_0603_5%
RV239
OPTNS@
47K_0402_5%

3 2
OPTNS@
D
NVVDD_EN# QV36B
5

1
DV4 GC6@
FB_GC6_EN_R @ GC6_EN G LBSS138DW1T1G_SOT363-6
RV123 1 2 0_0402_5% 2

6
8,26 FB_GC6_EN_R D
FBVDDQ_PWR_EN S OPTNS@
1

4
NVVDD_EN 2
DGPU_PWROK RV233 1 OPT@ 2 10K_0402_5% 3 FBVDDQ_PWR_EN 56 QV36A
8,23,57 DGPU_PWROK G
LBSS138DW1T1G_SOT363-6
1

A S A
@ BAV70W-7-F_SOT323-3

1
PEX_PWROK RV234 1 2 0_0402_5% OPTNS@
RV125
200K_0402_5%
1 2
GC6@
RV126
2

0_0402_5%
1 NGC6@
CV754
0.1u_0201_10V6K
OPT@
2
Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 GPU_AON/MAIN PWR/SEQUENCE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EYG10_ES430_ES530
Date: Tuesday, January 09, 2018 Sheet 23 of 60
5 4 3 2 1
 5 4 3 2 1

UV1H ? COMMON INS34152041

13/14 GND

D D
A2 K11
AB17 GND_001 GND_057 K13
AB20 GND_005 GND_058 K15
AB24 GND_006 GND_059 K17
AC2 GND_007 GND_060 L10
AC22 GND_008 GND_061 L12
AC26 GND_009 GND_062 L14
AC5 GND_010 GND_063 L16
AC8 GND_011 GND_064 L18
AD12 GND_012 GND_065 L5
AD13 GND_013 GND_069 M11
A26 GND_014 GND_070 M13
AD15 GND_002 GND_071 M15
AD16 GND_015 GND_072 M17
AD18 GND_016 GND_073 N10
AD19 GND_017 GND_074 N12
AD21 GND_018 GND_075 N14
AD22 GND_019 GND_076 N16
AE11 GND_020 GND_077 N18
AE14 GND_021 GND_078 P11
AE17 GND_022 GND_079 P13
AE20 GND_023 GND_080 P15
AB11 GND_024 GND_081 P17
AF1 GND_003 GND_082 P23
AF11 GND_025 GND_084 P26
AF14 GND_026 GND_085 R10
AF17 GND_027 GND_087 R12
AF20 GND_028 GND_088 R14
AF23 GND_029 GND_089 R16
AF5 GND_030 GND_090 R18
AF8 GND_031 GND_091 T11
AG2 GND_032 GND_092 T13
AG26 GND_033 GND_093 T15
AB14 GND_034 GND_094 T17
B1 GND_004 GND_095 U10
B11 GND_035 GND_096 U12
B14 GND_036 GND_097 U14
B17 GND_037 GND_098 U16
C C
B20 GND_038 GND_099 U18
B23 GND_039 GND_100 U23
B27 GND_040 GND_102 U26
B5 GND_041 GND_103 V11
B8 GND_042 GND_105 V13
E11 GND_043 GND_106 V15
E14 GND_044 GND_107 V17
E17 GND_045 GND_108 Y2
E2 GND_046 GND_109 Y23
E20 GND_047 GND_110 Y26
E22 GND_048 GND_111 Y5
E25 GND_049 GND_112 AA7
E5 GND_050 GND_F AB7
E8 GND_051 GND_H
GND_052

H2 P2
H5 GND_053 GND_083 P5
L2 GND_056 GND_086 U2
GND_066 GND_101 U5
GND_104

H23 L23
H25 GND_054 GND_067 L25
GND_055 GND_068

N17S-G1-A1_GB2C-64-595
@

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 GPU_GND

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EYG10_ES430_ES530
Date: Tuesday, January 09, 2018 Sheet 24 of 60
5 4 3 2 1
 5 4 3 2 1

+1.0VGS UV1J ? COMMON INS34153007

PEX_PLLVDD/Q Decouling 4/14 IFPAB
UV1I ? COMMON INS34152647
OPTN16@ Under GPU Near GPU +PEX_PLLVDD 5/14 NC
RV10 2 1 0_0402_5%
MLCC N16 N17 location DVI HDMI
SL/DL
DP

0.1u_0201_10V6K

4.7U_0402_6.3V6M
1U_0402_6.3V6K
+PEX_PLLVDD AA14

OPTN16@
Under NC_1 AC4
1.0uF 1 NA 1 1 1

OPTN16@

OPTN16@
AA15 IFPA_L3_N

CV758
NC_2 TXC/TXC AC3

CV757

CV60
AB6 IFPA_L3
PEX_SVDD_3V3 AB8 NC_3
1uF 1 NA PEX_PLLVDD NC_4 AA6
N16:+1.0VGS(recommend) 2 2 2 AD10 IFPAB_RSET
Near NC_5 TXD0/0 Y3
N17:NC AD7 IFPA_L2_N
NC_6 Y4
4.7uF 1 NA 1 2 PEX_TSTCLK_OUT AE22
NC_7
IFPA_L2
RV32 AE3
200_0402_1% AE4 NC_8
NC_9 TXD1/1 AA2
@ AF2 IFPA_L1_N
D PEX_TSTCLK_OUT# NC_10 W7 AA3 D
AF22 IFPAB_PLLVDD IFPA_L1
AF3 NC_11
Differential signal AF4 NC_12
NC_13 TXD2/2 AA1
AG3 IFPA_L0_N
NC_14 AB1
PEX_SVDD/Q Decouling +3.3V_1.8V_AON D10
NC_15
IFPA_L0
E10
OPTN16@ F10 NC_16
RV11 2 1 0_0402_5% PEX_SVDD_3V3 NC_17 AA5
MLCC N16 N17 location F5 IFPA_AUX_SDA_N

4.7U_0402_6.3V6M
MULTI_STRAP_REF0_GND NC_18 AA4
F6 IFPA_AUX_SCL

4.7U_0402_6.3V6M
W5 NC_19

OPTN16@

OPTN16@
4.7uF 2 NA Near 1 1 NC_20

CV57

CV759
AB4
IFPB_L3_N AB5
TXC
PEX_SVDD_3V3 IFPB_L3
N16:+3.3V_AON(recommend) 2 2
N17:NC W6 TXD0/3 AB2
N17S-G1-A1_GB2C-64-595 IFP_IOVDD_1 IFPB_L2_N AB3
IFPB_L2

@
Y6
Change by Bourne 20170412 IFP_IOVDD_2
Near GPU
TXD1/4 AD2
IFPB_L1_N AD3
IFPB_L1

+3.3V_1.8V_AON
TXD2/5 AD1
IFPB_L0_N AE1
IFPB_L0

1
RV181
AD5
10K_0402_5% IFPB_AUX_SDA_N AD4
@ IFPB_AUX_SCL

2
MULTI_STRAP_REF0_GND
1
IFPAB (DEFEATURED 0N GM108)

N17S-G1-A1_GB2C-64-595
RV243

@
40.2K_0402_1%
C OPTN16@ C
UV1K ? COMMON INS34152829
2

10/14 MISC2

Change by Bourne 20170412

D12 @ 1
ROM_CS_N TV5
B12 ROM_SI
ROM_SI ROM_SO ROM_SI 29
A12
D1 ROM_SO C12 ROM_SCLK ROM_SO 29
STRAP0
29 STRAP0 STRAP0 ROM_SCLK ROM_SCLK 29
STRAP1 D2
29 STRAP1 STRAP1
STRAP2 E4
29 STRAP2 E3 STRAP2
STRAP3
29 STRAP3 STRAP3
STRAP4 D3
29 STRAP4 C1 STRAP4
STRAP5
29 STRAP5 STRAP5

D11 RV50 2 @ 1 10K_0402_5%

BUFRST_N
PEX_HVDD
N16:+1.05VGS(recommend)
+1.0VGS(Used)
N17:+1.8VGS
PEX_HVDD
XS_PLLVDD/Q Decouling
@ Under GPU XS_PLLVDD
1 2 LV5 1 2 0_0402_5%
MLCC N16 N17 location
0.1u_0201_10V6K

0.1u_0201_10V6K

LV2
4.7U_0402_6.3V6M

22U_0603_6.3V6-M

SBK160808T-300Y-N 1 1
1 1
OPT@

CV667

OPT@ Under
0.1uF 1 1
OPT@

CV728

OPT@

CV727

CV21
@

30ohms (ESR=0.05) Bead N17S-G1-A1_GB2C-64-595

Near

@
2 2
2 2 22uF 1 0 +3.3V_1.8V_AON

B XTALOUT 1 @ 2 RV33 10K_0402_5% B

SP_PLLVDD & VID_PLLVDD/Q Decouling XTALSSIN 1 OPT@ 2 RV34 10K_0402_5%

Under GPU(below 150mils)
SP_PLLVDD XTALOUT 1 OPT@ 2 RV36 10K_0402_5%
1 2
MLCC N16 N17 location
0.1u_0201_10V6K

0.1u_0201_10V6K

LV1
1 1
OPT@

OPT@

0_0402_5% Under UV1L ? COMMON INS34152886

0.1uF 2 2
CV15

CV762

VID_PLLVDD 9/14 XTAL_PLL

@ 1 2
RV38 1 OPT@ 2 10M_0402_5%
2 2 RV24 10uF 1 0 XS_PLLVDD
SP_PLLVDD
L6
XS_PLLVDD
0_0402_5% Near M6
OPTN17@ GPCPLL_AVDD F11 SP_PLLVDD YV1
47uF 1 0 VID_PLLVDD N6 GPCPLL_AVDD
VID_PLLVDD XTAL_IN 1 4
150mA OSC1 GND2
2 3 XTAL_OUT
GND1 OSC2

GPCPLL_AVDD/Q Decouling XTALSSIN A10 C10 XTALOUT

1
27MHZ_10PF_7V27000050
1
CV20
GPCPLL_AVDD XTAL_SSIN XTAL_OUTBUFF CV19
1 2 OPT@ 12P_0201_25V8-J
12P_0201_25V8-J
OPT@
0.1u_0201_10V6K

LV21
MLCC N16 N17 location XTAL_IN C11 B10 XTAL_OUT 2 OPT@ 2
OPTN17@

0_0402_5% 1 XTAL_IN XTAL_OUT

CV16

OPTN17@
N17S-G1-A1_GB2C-64-595
0.1uF NA 1 Under
@

2
4.7uF NA 1
Near
Change by Bourne 20170412 22uF NA 1

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 GPU_STRAP/DP/HDMI

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EYG10_ES430_ES530
Date: Tuesday, January 09, 2018 Sheet 25 of 60
5 4 3 2 1
 5 4 3 2 1

+3.3V_1.8V_AON
GPU Address 0x9E
+3.3V_1.8V_AON
UV1M ? COMMON INS34153763

2
8/14 MISC1
RV3 RV5

G1
2.2K_0402_5% 2.2K_0402_5%
OPTN17@ OPTN17@
QV1A

G
DMN5L06DWK-7_SOT363-6

1
VGA_SMB_CK2 S1
EC_SMB_CK2 7,36,39,44

D1S
D
OPTN17@
D9 VGA_SMB_CK2
I2CS_SCL D8 VGA_SMB_DA2 Internal Thermal Sensor
OVERT# A6 I2CS_SDA OPTN16@
AE2 OVERT A9 I2CC_SCL RV1 2 1 0_0402_5%
TS_VREF I2CC_SCL B9 I2CC_SDA

G2
D 1 I2CC_SDA D
CV707
QV1B
0.1u_0201_10V6K

G
VGA_SMB_DA2 DMN5L06DWK-7_SOT363-6
@ E12 S2 D2
2 THERMDN C9 I2CB_SCL EC_SMB_DA2 7,36,39,44

D
OPTN17@
F12 I2CB_SCL C8 I2CB_SDA
THERMDP I2CB_SDA
OPTN16@
RV2 2 1 0_0402_5%

PU AT EC SIDE, +3VS AND 4.7K

C6 NVVDD_PWM_VID
GPIO0 FB_GC6_EN NVVDD_PWM_VID 57
B2
GPIO1 D6 GPU_EVENT#_R
GPIO2 NVVDDS_PWM PLT_RST_VGA# @
C7 1 RV174 1 2 56_0402_5%
GPIO3 1.8VGS_PWR_EN TV8 @
F9 1
GPIO4 A3 1.8VGS_PWR_EN 23,56
CV218
GPIO5 A4 PSI_VGA 220P_0201_25V7-K
GPIO6 B6 PSI_VGA 57
@
GPIO7

2
E9 MEM_VDD_CTL 2
GPIO8 F8 VGA_ALERT#
GPIO9 C5 GPIO10_FBVREF_ALTV
GPIO10 GPIO10_FBVREF_ALTV 27
E7 OVERT# 3 1
GPIO11 D7 VGA_AC_DET_R 2 1 OPT@ WRST# 44
GPIO12 VGA_AC_DET 44
B4 DV1 RB751V-40_SOD323-2 1
GPIO13 B3 CV221
GPIO14 C3 QV24
OPTN16@ 0.01U_0201_10V6K
GPIO15 D5 RV244 1 2 0_0402_5% SYS_PEX_RST_MON# @ LSI1012XT1G_SC-89-3
GPIO16 D4 2 @
GPIO17 C2
GPIO18 F7
GPIO19 E6 OPTN16@
GPIO20 C4 RV245 1 2 0_0402_5% GPU_PEX_RST_HOLD#
GPIO21 A7 VGA_CRT_DATA
GPIO22 B7 VGA_CRT_CLK
GPIO23

@
C N17S-G1-A1_GB2C-64-595 MEM_VDD_CTL SYS_PEX_RST_MON# C
RV1397 1 2 0_0402_5% +3VS
@

UV1N ? COMMON INS34153738 +3VALW

2
3/14 JTAG RV41
10K_0402_5%
GC6N17@

2
1 @ AE5 RV45
TV1 1 AE6 JTAG_TCK +3.3V_1.8V_AON
@ 10K_0402_5%
TV2

1
1 @ AF6 JTAG_TDI GC6N17@
TV3 1 AD6 JTAG_TDO FB_GC6_EN_R
@
TV4 JTAG_TMS FB_GC6_EN_R 8,23
10K_0402_5% 2 OPT@ 1 RV53 AG4

1
2 OPT@ 1 RV52 AD9 JTAG_TRST_N

D2
10K_0402_5% TESTMODE
NVJTAG_SEL RV249
10K_0402_5%
G2
D
G QV33B
@ S DMN5L06DWK-7_SOT363-6
GC6N17@

S2
D1
FB_GC6_EN G1 G
D

S
QV33A
DMN5L06DWK-7_SOT363-6

2
GC6N17@

S1
RV47
10K_0402_5%
GC6@

1
N17S-G1-A1_GB2C-64-595 GC6N16@
RV250 1 2 0_0402_5%
@

+3.3V_1.8V_AON +3.3V_1.8V_AON

+3VS
1

2
CV12
B 0.1u_0201_10V6K B
RV13
2

10K_0402_5% @
RV12 2
GC6@

2
0_0402_5%
+3.3V_1.8V_AON

1
@
+3.3V_1.8V_AON
+1.8VGARST 1

GPU_EVENT#_R 3 1 GPU_EVENT#
GPU_EVENT# 8
2

1
CV11
0.1u_0201_10V6K RV1398 2 GC6@
QV25
10K_0402_5%
OPT@ RV37 LSI1012XT1G_SC-89-3
2 OPTN16@
10K_0402_5%
OPT@
1

DV6
5

UV2 GPU_PEX_RST_HOLD# RV15 1 @ 2 0_0402_5%

2
1

PLT_RST# 1
P

11,37,38,40,44 PLT_RST# B SYS_PEX_RST_MON# 1

4 SYS_PEX_RST_MON# PLT_RST_VGA# 20
Y 3
2
8 PXS_RST# A
1
G

BAT54AW_SOT323-3
RV14
OPTN16@
3

100K_0402_5%
1

OPT@
RV16
RV39 1 2 0_0402_5% +3.3V_1.8V_AON
2

100K_0402_5% MC74VHC1G09DFT2G_SC70-5
+3.3V_1.8V_AON
OPT@ OPTN17@
OPT@
VGA_CRT_DATA RV17 1 @ 2 2.2K_0402_5%
2

VGA_CRT_CLK RV19 1 @ 2 2.2K_0402_5% 1.8VGS_PWR_EN RV18 2 OPT@ 1 1K_0402_1%

I2CB_SCL RV22 1 @ 2 2.2K_0402_5% OVERT# RV20 1 OPT@ 2 10K_0402_5%
I2CB_SDA RV25 1 @ 2 2.2K_0402_5% VGA_ALERT# RV23 1 OPT@ 2 10K_0402_5%
I2CC_SCL RV28 1 @ 2 2.2K_0402_5% VGA_AC_DET_R RV26 1 OPT@ 2 100K_0402_5%
I2CC_SDA RV30 1 @ 2 2.2K_0402_5% PSI_VGA RV29 1 @ 2 10K_0402_5%
MEM_VDD_CTL RV224 1 @ 2 10K_0402_5% GPU_PEX_RST_HOLD# RV31 1 OPT@ 2 10K_0402_5%
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 GPU_GPIO/JTAG

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EYG10_ES430_ES530
Date: Tuesday, January 09, 2018 Sheet 26 of 60
5 4 3 2 1
 5 4 3 2 1

Lower 32 bits

21,28 FBA_D[0..63]
MF=0 No Mirror
21,28 FBA_CMD[31..0]
UV5
21,28 FBA_EDC[7..0]
MF=0 MF=1 MF=1 MF=0
21,28 FBA_DBI[7..0]
A4 FBA_D0
FBA_EDC0 C2 DQ24 DQ0 A2 FBA_D1
D FBA_EDC1 C13 EDC0 EDC3 DQ25 DQ1 B4 FBA_D2 D
FBA_EDC2 R13 EDC1 EDC2 DQ26 DQ2 B2 FBA_D3
FBA_EDC3 EDC2 EDC1 DQ27 DQ3 FBA_D4 BYTE0
R2 E4
EDC3 EDC0 DQ28 DQ4 E2 FBA_D5
DQ29 DQ5 F4 FBA_D6
FBA_DBI0 D2 DQ30 DQ6 F2 FBA_D7
FBA_DBI1 D13 DBI0# DBI3# DQ31 DQ7 A11 FBA_D8
FBA_DBI2 P13 DBI1# DBI2# DQ16 DQ8 A13 FBA_D9
FBA_CLK0 OPT@ FBA_DBI3 DBI2# DBI1# DQ17 DQ9 FBA_D10
RV193 1 2 40.2_0402_1% P2 B11
21 FBA_CLK0 DBI3# DBI0# DQ18 DQ10 FBA_D11
B13 BYTE1
FBA_CLK0# RV194 1 OPT@ 2 40.2_0402_1% FBA_CLK0 J12 DQ19 DQ11 E11 FBA_D12
21 FBA_CLK0# FBA_CLK0# J11 CK DQ20 DQ12 E13 FBA_D13
FBA_CMD14 J3 CK# DQ21 DQ13 F11 FBA_D14
1 CKE# DQ22 DQ14 FBA_D15
CV228 F13
0.01U_0201_10V6K DQ23 DQ15 U11 FBA_D16
OPT@ FBA_CMD2 H11 DQ8 DQ16 U13 FBA_D17
2 FBA_CMD4 K10 BA0/A2 BA2/A4 DQ9 DQ17 T11 FBA_D18
FBA_CMD3 K11 BA1/A5 BA3/A3 DQ10 DQ18 T13 FBA_D19
FBA_CMD1 BA2/A4 BA0/A2 DQ11 DQ19 FBA_D20 BYTE2
H10 N11
BA3/A3 BA1/A5 DQ12 DQ20 N13 FBA_D21
DQ13 DQ21 M11 FBA_D22
FBA_CMD6 K4 DQ14 DQ22 M13 FBA_D23
FBA_CMD11 H5 A8/A7 A10/A0 DQ15 DQ23 U4 FBA_D24
FBA_CMD10 H4 A9/A1 A11/A6 DQ0 DQ24 U2 FBA_D25
FBA_CMD7 K5 A10/A0 A8/A7 DQ1 DQ25 T4 FBA_D26
FBA_CMD9 J5 A11/A6 A9/A1 DQ2 DQ26 T2 FBA_D27
A12/RFU/NC DQ3 DQ27 N4 FBA_D28
DQ4 DQ28 FBA_D29 BYTE3
A5 N2 +1.35VGS
U5 VPP/NC1 DQ5 DQ29 M4 FBA_D30
VPP/NC2 DQ6 DQ30 M2 FBA_D31
DQ7 DQ31
RV182 1 2 1K_0402_1% OPT@ J1 +1.35VGS Close to DRAM
RV183 1 2 1K_0402_1% OPT@ FBA_SEN0 J10 MF
RV185 1 2 121_0402_1% OPT@ J13 SEN B1 CV741 CV743 CV742 CV623 CV621 CV622 CV625
ZQ VDDQ1 D1

10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
VDDQ2 F1
FBA_CMD8 VDDQ3 1 1 1 1 1 1 1

OPT_NS@
J4 M1

OPT_NS@

OPT@

OPT@

OPT@

OPT@
FBA_CMD12 ABI# VDDQ4

OPT@
C G3 P1 C
FBA_CMD0 G12 RAS# CAS# VDDQ5 T1
FBA_CMD15 L3 CS# WE# VDDQ6 G2
CAS# RAS# VDDQ7 2 2 2 2 2 2 2
FBA_CMD5 L12 L2
WE# CS# VDDQ8 B3
VDDQ9 D3
VDDQ10 F3
FBA_WCLK01# D5 VDDQ11 H3
21 FBA_WCLK01# FBA_WCLK01 WCK01# WCK23# VDDQ12
D4 K3
21 FBA_WCLK01 WCK01 WCK23 VDDQ13 M3
FBA_WCLK23# P5 VDDQ14 P3 CV744 CV745 CV746 CV627 CV628 CV630 CV629
21 FBA_WCLK23# FBA_WCLK23 P4 WCK23# WCK01# VDDQ15 T3

10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
21 FBA_WCLK23 WCK23 WCK01 VDDQ16

1U_0402_6.3V6K
E5
VDDQ17 N5 1 1 1 1 1 1 1

OPT_NS@

OPT@

OPT_NS@

OPT_NS@

OPT@

OPT@
VDDQ18

OPT@
A10 E10
FBA_VREFC VREFD1 VDDQ19
U10 N10
+1.35VGS FBA_VREFC J14 VREFD2 VDDQ20 B12
VREFC VDDQ21 2 2 2 2 2 2 2
1 D12
CV224 VDDQ22 F12
820P_0402_25V7 VDDQ23 H12
1

RV192 FBA_CMD13 J2 VDDQ24 K12

OPT@ 2 RESET# VDDQ25 M12
549_0402_1%
OPT@ VDDQ26 P12
VDDQ27 T12
VDDQ28 G13 Around DRAM
1 2

FBA_VREFC VDDQ29
H1 L13
K1 VSS1 VDDQ30 B14
RV191 B5 VSS2 VDDQ31 D14 CV747 CV748 CV750 CV749 CV751 CV752 CV753
1.33K_0402_1% G5 VSS3 VDDQ32 F14
VSS4 VDDQ33

10U_0603_6.3V6M

10U_0603_6.3V6M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
OPT@ L5 M14
T5 VSS5 VDDQ34 P14 1 1
2

VSS6 VDDQ35 1 1 1 1 1

OPT@

OPT@

OPT@

OPT@

OPT@
B10 T14
VSS7 VDDQ36

@
D10
G10 VSS8
VSS9 2 2
L10 A1 2 2 2 2 2
P10 VSS10 VSSQ1 C1
T10 VSS11 VSSQ2 E1
H14 VSS12 VSSQ3 N1
B
K14 VSS13 VSSQ4 R1 B
VSS14 VSSQ5 U1
VSSQ6 H2
+1.35VGS G1 VSSQ7 K2
L1 VDD1 VSSQ8 A3
G4 VDD2 VSSQ9 C3
FBA_VREFC L4 VDD3 VSSQ10 E3
RV190 C5 VDD4 VSSQ11 N3
2 1 R5 VDD5 VSSQ12 R3
C10 VDD6 VSSQ13 U3
931_0402_1% VDD7 VSSQ14
R10 C4
OPT@ D11 VDD8 VSSQ15 R4
G11 VDD9 VSSQ16 F5
L11 VDD10 VSSQ17 M5
VDD11 VSSQ18
1

D P11 F10
QV26
2 G14 VDD12 VSSQ19 M10
26 GPIO10_FBVREF_ALTV LBSS139WT1G_SC70-3 L14 VDD13 VSSQ20 C11
G
OPT@ VDD14 VSSQ21 R11
1

S
3

RV208 VSSQ22 A12

VSSQ23 C12
100K_0402_5% VSSQ24 E12
OPT@ VSSQ25 N12
VSSQ26 R12
2

170-BALL VSSQ27 U12

VSSQ28 H13
SGRAM GDDR5 VSSQ29 K13
VSSQ30 A14
VSSQ31 C14
VSSQ32 E14
VSSQ33 N14
VSSQ34 R14
VSSQ35 U14
VSSQ36
@ H5GQ1H24AFR-T2L_BGA170

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 GPU_GDDR5_Rank0_[31:0]

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EYG10_ES430_ES530
Date: Tuesday, January 09, 2018 Sheet 27 of 60
5 4 3 2 1
 5 4 3 2 1

upper 32 bits

21,27 FBA_D[0..63] MF=0 No Mirror

21,27 FBA_CMD[31..0]
UV14
21,27 FBA_EDC[7..0]
MF=0 MF=1 MF=1 MF=0
D 21,27 FBA_DBI[7..0] D
A4 FBA_D32
FBA_EDC4 C2 DQ24 DQ0 A2 FBA_D33
FBA_EDC5 C13 EDC0 EDC3 DQ25 DQ1 B4 FBA_D34
FBA_EDC6 R13 EDC1 EDC2 DQ26 DQ2 B2 FBA_D35
FBA_EDC7 EDC2 EDC1 DQ27 DQ3 FBA_D36 BYTE4
R2 E4
EDC3 EDC0 DQ28 DQ4 E2 FBA_D37
DQ29 DQ5 F4 FBA_D38
FBA_DBI4 D2 DQ30 DQ6 F2 FBA_D39
FBA_DBI5 D13 DBI0# DBI3# DQ31 DQ7 A11 FBA_D40
FBA_DBI6 P13 DBI1# DBI2# DQ16 DQ8 A13 FBA_D41
FBA_DBI7 P2 DBI2# DBI1# DQ17 DQ9 B11 FBA_D42
DBI3# DBI0# DQ18 DQ10 B13 FBA_D43
FBA_CLK1 DQ19 DQ11 FBA_D44 BYTE5
J12 E11
FBA_CLK1# J11 CK DQ20 DQ12 E13 FBA_D45
FBA_CMD30 J3 CK# DQ21 DQ13 F11 FBA_D46
FBA_CLK1 OPT@ CKE# DQ22 DQ14 FBA_D47
RV195 1 2 40.2_0402_1% F13
21 FBA_CLK1 DQ23 DQ15 FBA_D48
U11
FBA_CLK1# RV196 1 OPT@ 2 40.2_0402_1% FBA_CMD18 H11 DQ8 DQ16 U13 FBA_D49
21 FBA_CLK1# FBA_CMD20 K10 BA0/A2 BA2/A4 DQ9 DQ17 T11 FBA_D50
1 FBA_CMD19 K11 BA1/A5 BA3/A3 DQ10 DQ18 T13 FBA_D51
CV649 FBA_CMD17 H10 BA2/A4 BA0/A2 DQ11 DQ19 N11 FBA_D52
0.01U_0201_10V6K BA3/A3 BA1/A5 DQ12 DQ20 FBA_D53 BYTE6
N13
OPT@ DQ13 DQ21 M11 FBA_D54
2 DQ14 DQ22
FBA_CMD22 K4 M13 FBA_D55
FBA_CMD27 H5 A8/A7 A10/A0 DQ15 DQ23 U4 FBA_D56
FBA_CMD26 H4 A9/A1 A11/A6 DQ0 DQ24 U2 FBA_D57
FBA_CMD23 K5 A10/A0 A8/A7 DQ1 DQ25 T4 FBA_D58
FBA_CMD25 J5 A11/A6 A9/A1 DQ2 DQ26 T2 FBA_D59
A12/RFU/NC DQ3 DQ27 N4 FBA_D60
DQ4 DQ28 FBA_D61 BYTE7
A5 N2
U5 VPP/NC1 DQ5 DQ29 M4 FBA_D62
VPP/NC2 DQ6 DQ30 M2 FBA_D63
DQ7 DQ31
RV197 1 2 1K_0402_1% OPT@ J1 +1.35VGS
RV198 1 2 1K_0402_1% OPT@ FBA_SEN1 J10 MF
RV201 1 2 121_0402_1% OPT@ J13 SEN B1
ZQ VDDQ1 D1
C VDDQ2 F1 C
FBA_CMD24 J4 VDDQ3 M1
FBA_CMD28 G3 ABI# VDDQ4 P1
FBA_CMD16 G12 RAS# CAS# VDDQ5 T1
FBA_CMD31 L3 CS# WE# VDDQ6 G2
FBA_CMD21 L12 CAS# RAS# VDDQ7 L2
WE# CS# VDDQ8 B3
VDDQ9 D3
VDDQ10 F3
FBA_WCLK45# D5 VDDQ11 H3
21 FBA_WCLK45# FBA_WCLK45 WCK01# WCK23# VDDQ12 +1.35VGS
D4 K3
21 FBA_WCLK45 WCK01 WCK23 VDDQ13 M3 Close to DRAM
FBA_WCLK67# P5 VDDQ14 P3
21 FBA_WCLK67# FBA_WCLK67 P4 WCK23# WCK01# VDDQ15 T3 CV654 CV729 CV650 CV651 CV653 CV652 CV730
21 FBA_WCLK67 WCK23 WCK01 VDDQ16 E5
VDDQ17 N5

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
FBA_VREFC VDDQ18

10U_0603_6.3V6M
A10 E10
VREFD1 VDDQ19 1 1 1 1 1 1 1

OPT_NS@

OPT_NS@
U10 N10

OPT@

OPT@

OPT@

OPT_NS@

OPT@
FBA_VREFC J14 VREFD2 VDDQ20 B12
VREFC VDDQ21 D12
1 VDDQ22
CV665 F12 2 2 2 2 2 2 2
820P_0402_25V7 VDDQ23 H12
FBA_CMD29 J2 VDDQ24 K12
OPT@ 2 RESET# VDDQ25 M12
VDDQ26 P12
VDDQ27 T12
VDDQ28 G13
H1 VDDQ29 L13 CV731 CV732 CV733 CV638 CV639 CV641 CV640
K1 VSS1 VDDQ30 B14
VSS2 VDDQ31

10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
B5 D14
G5 VSS3 VDDQ32 F14 1 1 1 1 1 1 1

OPT_NS@
VSS4 VDDQ33

OPT_NS@

OPT_NS@

OPT@

OPT@

OPT_NS@
L5 M14

OPT@
T5 VSS5 VDDQ34 P14
B10 VSS6 VDDQ35 T14
D10 VSS7 VDDQ36 2 2 2 2 2 2 2
G10 VSS8
L10 VSS9 A1
P10 VSS10 VSSQ1 C1
B B
T10 VSS11 VSSQ2 E1
H14 VSS12 VSSQ3 N1
K14 VSS13 VSSQ4 R1
VSS14 VSSQ5 U1
VSSQ6 H2 Around DRAM
+1.35VGS G1 VSSQ7 K2
L1 VDD1 VSSQ8 A3 CV734 CV735 CV736 CV737 CV738 CV739 CV740
G4 VDD2 VSSQ9 C3
VDD3 VSSQ10

10U_0603_6.3V6M

10U_0603_6.3V6M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
L4 E3
C5 VDD4 VSSQ11 N3 1 1 1 1 1 1 1

OPT@

OPT@

OPT@

OPT@
R5 VDD5 VSSQ12 R3

@
C10 VDD6 VSSQ13 U3
R10 VDD7 VSSQ14 C4
VDD8 VSSQ15 2 2 2 2 2 2 2
D11 R4
G11 VDD9 VSSQ16 F5
L11 VDD10 VSSQ17 M5
P11 VDD11 VSSQ18 F10
G14 VDD12 VSSQ19 M10
L14 VDD13 VSSQ20 C11
VDD14 VSSQ21 R11
VSSQ22 A12
VSSQ23 C12
VSSQ24 E12
VSSQ25 N12
VSSQ26 R12
170-BALL VSSQ27 U12
VSSQ28 H13
SGRAM GDDR5 VSSQ29 K13
VSSQ30 A14
VSSQ31 C14
VSSQ32 E14
VSSQ33 N14
VSSQ34 R14
VSSQ35 U14
VSSQ36
@
H5GQ1H24AFR-T2L_BGA170
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 GPU_GDDR5_Rank0_[64:32]

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EYG10_ES430_ES530
Date: Tuesday, January 09, 2018 Sheet 28 of 60
5 4 3 2 1
 5 4 3 2 1

+3.3V_1.8V_AON
X76

2
RV146 RV147 RV148
100K_0402_5% 100K_0402_5% 100K_0402_5%
@ @ @

1
D D

25 STRAP0 STRAP0
25 STRAP1 STRAP1
25 STRAP2 STRAP2

2
RV151 RV152 RV153
100K_0402_5% 100K_0402_5% 100K_0402_5%
@ @ @
1

1
+3.3V_1.8V_AON
2

2
RV149 RV150 RV219
100K_0402_5% 100K_0402_5% 100K_0402_5%
@ @ @
C C
1

25 STRAP3 STRAP3
25 STRAP4 STRAP4
25 STRAP5 STRAP5
2

RV154 RV155 RV218

100K_0402_5% 100K_0402_5% 100K_0402_5%
@ @ @
1

Strap5 is NC pin on N16

B B

+3V_1.8VGS +3.3V_1.8V_AON
2
2

RV247
RV248
0_0402_5%
0_0402_5%
OPTN17@
OPTN16@
1
1
2

RV156 RV157 RV158

100K_0402_5% 100K_0402_5% 100K_0402_5%
@ @ @
1

ROM_SI
25 ROM_SI ROM_SO
25 ROM_SO ROM_SCLK
25 ROM_SCLK
2

RV159 RV160 RV161

100K_0402_5% 100K_0402_5% 100K_0402_5%
@ @ @
1

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 GPU_MISC

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EYG10_ES430_ES530
Date: Tuesday, January 09, 2018 Sheet 29 of 60
5 4 3 2 1
 5 4 3 2 1

UA1

10 20 +5VA
DC_DET AVDD1 +1.8V_SYSA

4.7U_0402_6.3V6M
33
5 AVDD2
8 HDA_BITCLK_AUDIO BCLK +1.8V_SYS

4.7U_0402_6.3V6M
29 1

CA325
9 CPVDD
8 HDA_SYNC_AUDIO SYNC ALC3240-VA3-CG +3V_AUD 1

CA326
1
RA3 1 2 33_0402_5% HDA_SDIN0_AUDIO 7 DVDD

0.1u_0201_10V6K
8 HDA_SDIN0 SDATA-IN +3V_AUD_IO 2
8 4 8
HDA_SDOUT_AUDIO SDATA-OUT DVDD-IO 2 +5VS
1
+5V_AUD 1200mA

CA318
34 GNDA +5V_AUD
DMIC_DATA_R PVDD1 2 1
33 DMIC_DATA RA1 1 2 0_0402_5% @ 2 39
RA11 1 2 22_0402_5% DMIC_CLK_R 3 GPIO0/DMIC-DATA12 PVDD2 RA20
33 DMIC_CLK GPIO1/DMIC-CLK 2

10U_0603_6.3V6M

10U_0402_6.3V6M

0.1u_0201_10V6K

0.1u_0201_10V6K
D 0_0603_SM D

1U_0201_6.3V6-K
SPKR_MUTE# 40 22 @ 1 1 1 1

CA383

CA384

CA327
HPOUT-JD_R PDB VREF 1

CA320
HPOUT-JD RA684 1 2 200K_0402_1% 12
HP/LINE1-JD(JD1) @

CA382
23 MIC2-VREFO
BEEP 11 MIC2-VREFO
PCBEEP 2 2 2 2
MIC1L_RING2 13 24
MIC2-L(PORT-F-L)/RING2 LINE1-VREFO-L 2
MIC1R_SLEEVE 14
RA683 1 2 2.2K_0402_5% MIC2-R(PORT-F-R)/SLEEVE
GNDA
MIC2-VREFO RA724 1 2 2.2K_0402_5% 27
15 CPVEE 28

1U_0201_6.3V6-K
MIC2-CAP CBN

1U_0201_6.3V6-K
17 30 1
1 LINE1-R(PORT-C-R) CBP

CA388
18 1 +3VS

4.7U_0402_6.3V6M
LINE1-L(PORT-C-L)

CA385
CA324 21 1
LDO1-CAP 5mA

CA328
4.7U_0402_6.3V6M 32 +3V_AUD
SPK_L+ LDO2-CAP 2 2 1

4.7U_0402_6.3V6M
2 35 6
SPK_L- 36 SPK-OUT-LP LDO3-CAP 2 RA18
1

4.7U_0402_6.3V6M

1U_0201_6.3V6-K

0.1u_0201_10V6K
+3V_AUD SPK_R- SPK-OUT-LN 2 1 1

CA329
37 16 RA5 1 2 0_0402_5% @ 0_0603_SM

CA330
CA380
GNDA SPK_R+ 38 SPK-OUT-RN VD33STB @
SPK-OUT-RP 1

CA331
GNDA
1

19 2
AVSS1 2 2
HP_L_CON 60.4_0402_1% 2 1 RA57 HPOUT-L 25 31 +3VL
R4 HP_R_CON HPOUT-L(PORT-I-L) AVSS2 2
60.4_0402_1% 1 2 RA59 HPOUT-R 26 GNDA
100K_0402_1% HPOUT-R(PORT-I-R) 41
GND(Thermal_Pad)
2

HPOUT-JD_R
RA57 & RA59 HW BOM request from 47Ω change to GNDA
ALC3240-CG_MQFN40_5X5
120Ω /SD00000FU8J,solution for HP noise issue
CPU HDA BUS power
+3VALW

RA27 2 1 0_0603_SM @
RA2 1 2 0_0402_5% @
RA15 1 2 0_0402_5% @ SPKR_MUTE#
44 EC_MUTE# +3V_AUD +3V_AUD_IO
RA8 1 2 0_0402_5% @ RA19 1 2 0_0402_5% @
VD33STB:Power for combo jack depop circuit at system shutdown mode.
2

RA12 1 2 0_0402_5% @ 1mA

RA23
C 10K_0402_5% RA13 1 2 0_0402_5% @
AVDD1:Analog power for mixers ,IO ports C
+5VS
1

RA4 1 @ 2 0_0402_5% DVDD-IO:Digital power for HDA link 2 1 +5VA

RA6 1 @ 2 0_0402_5% RA21

2.2U_0402_6.3V6M

0.1u_0201_10V6K
DVDD:Digital power for digital I/0 circuit 0_0603_SM 1 1 19mA

CA317
CA381
RA7 1 @ 2 0_0402_5% @
AVDD2:Analog power for DACS ,ADCS
RA9 1 @ 2 0_0402_5% 2 2
DA1
3 PVDD1,PVDD2:Power supply for full-bridge left and right channel
44 EC_BEEP
GNDA
1 1 2 1 2 BEEP
RA16
8 PCH_BEEP 2 CA323
1K_0402_5%
2

0.1u_0201_10V6K
GNDA
BAT54CW_SOT323-3
RA24
10K_0402_5% +1.8VS
131mA
1

RA722 2 1 0_0603_SM @ +1.8V_SYS

MIC1R_SLEEVE

MIC1L_RING2

HP_L_CON 26mA
JHP1 +1.8V_SYS RA723 2 1 0_0603_SM @ +1.8V_SYSA
HP_R_CON
MIC1L_RING2 3
HP_L_CON G/M HPOUT-JD
1 2 2 1 1

AZ5123-01F.R7GR_DFN1006P2X2
L

AZ5123-01F.R7GR_DFN1006P2X2

AZ5123-01F.R7GR_DFN1006P2X2
AZ5123-01F.R7GR_DFN1006P2X2
RA719

AZ5123-01F.R7GR_DFN1006P2X2
C2643 HPOUT-JD 5
0_0402_5% 5
1000P_0201_50V7-K
EMC_NS@
EMC_NS@ 6

1
6
EMC_NS@

EMC_NS@
HP_R_CON

1
1 2 2 1 2

EMC_NS@

EMC_NS@

EMC@

DA11
B R B
DA5

DA7

DA8
DA6
RA718 MIC1R_SLEEVE 4
C2642
0_0402_5% M/G
1000P_0201_50V7-K
EMC_NS@
100P_0201_25V8J

100P_0201_25V8J

EMC_NS@ 7 2

2
GNDA 1 1
MS
CA421

EMC@

2
EMC@

CA422

SINGA_2SJ3095-140111F
ME@
2 2
GNDA Close to Connector
Change Symbol to DC021608101 Bourne 0706
FOR ESD
GNDA Inner->out:HP_L->HP_R->Ring2->Sleeve

RA29,RA30,RA31,RA32 will to be changed from 15ohm to 0ohm,

for HW SO---->S3 play muisc hang up issue solut i on
SPK_L+ RA17 1 2 0_0402_5% @ SPK_L+_CON
HDA_BITCLK_AUDIO DMIC_CLK DMIC_DATA_R
SPK_L+ 1 2 CD@ 1 2 CD@
SPK_L- RA28 1 2 0_0402_5% @ SPK_L-_CON
RA29 0_0402_5% CA1 2200P_0201_25V7-K

22P_0201_25V8

33P_0201_50V8-J

33P_0201_50V8-J
1 1 1

EMC_NS@

EMC_NS@
EMC@

CA104

CA105
SPK_L- 1
1000P_0402_50V7K

1000P_0402_50V7K

CA16
2 CD@ 1 2 CD@
1 1
4 ohm ,0.7W RA30 0_0402_5% CA2 2200P_0201_25V7-K
EMC@

CA152

EMC@

CA153

2 2 2
0.418A RMS SPK_R+ 1 2 CD@ 1 2 CD@
RA31 0_0402_5% CA3 2200P_0201_25V7-K
2 2 JSPK1
SPK_R- 1 2 CD@ 1 2 CD@
1 RA32 0_0402_5% CA4 2200P_0201_25V7-K
2 1
A SPK_R- RA720 1 2 0_0402_5% @ SPK_R-_CON 3 2 5 A
SPK_R+ RA721 1 2 0_0402_5% @ SPK_R+_CON 4 3 GND1 6
4 GND2 Place Close To Codec
1000P_0402_50V7K

1000P_0402_50V7K

1 1 HIGHS_WS33041-S0191-HF
CA155
EMC@

CA154

EMC@

ME@

2 2 Change Symbol to SP011509163 Bourne 0706

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 CODEC_ALC3240

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EYG10_ES430_ES530
Date: Tuesday, January 09, 2018 Sheet 30 of 61
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 Blank

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EYG10_ES430_ES530
Date: Tuesday, January 09, 2018 Sheet 31 of 60
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 Blank
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EYG10_ES430_ES530
Date: Tuesday, January 09, 2018 Sheet 32 of 60
5 4 3 2 1
 5 4 3 2 1

LCD POWER CIRCUIT CMOS Camera

+3VS_DMIC +3VS +3VS_CMOS
+LCDVDD +LCDVDD_CON +3VS
+3VS
W=60mils
U5 R3 1 2 0_0603_SM @

0.1u_0201_10V6K

.047U_0201_6.3V6K
R1025 1 2 0_0402_5% @
5 1 R263 1 2 0_0805_5% @ 1 1

0.1u_0201_10V6K

10U_0603_6.3V6M

EMC_NS@
IN OUT 1
1

0.1u_0201_10V6K

C24
C206

C4
1 2 @

CD@

C3
GND @

4.7U_0402_6.3V6M

0.1u_0201_10V6K

33P_0402_50V8J
PCH_ENVDD 2 2

C1
4 3 1 1 1 2

RF_NS@
EN OCB 2

C121

C122

C123
2 SY6288C20AAC_SOT23-5 @
D D
2 2 2

U5 EN PIN VIH MIN 1.5V Touch

PCH_ENVDD
4 PCH_ENVDD For RF +3VS +3VS_GSEN2 +3VS_Touch
+3VS
1
R1 TS@
V20B+ R26 1 2 0_0402_5%
100K_0402_5% R5 1 2 0_0402_5% @

2
0.1u_0201_10V6K

0.1u_0201_10V6K

0_0402_5%
1 1

UHD@
R17 1 2 0_0805_5%
2

TS@

C25

R80
C2
+LEDVDD @
U28 2 2

1
@
1 10 R98 1 2 0_0805_5%
VIN1 VOUT2
+5VS

4.7U_0805_25V6-K

0.1U_0201_25V6-K
C43 2 9
VIN2 VOUT1
PCH_ENVDD 1 1

EMC@
1 2 3 8

CD@

C15
VDD EN

C14
JEDP1
4.7U_0402_6.3V6M 4 7 +3VALW
SDA ADDR R97 2 2
@
5 6 1 2 +LEDVDD 1 37
SCL INT# 2 1 GND1 38
44,52,53 100K_0201_5% 2 GND2
EC_SMB_DA1 11 3
GPAD @ 3
4
44,52,53 EC_SMB_CK1 CPU_EDP_TX0+ C19 1 2 0.1U_0402_25V6 EDP_TX0+ 5 4
OZ7520_DFN10_3X3 EMI Request 4 CPU_EDP_TX0+ CPU_EDP_TX0- EDP_TX0- 5
C16 1 2 0.1U_0402_25V6 6
4 CPU_EDP_TX0- 6
@ 7
CPU_EDP_TX1+ C17 1 2 0.1U_0402_25V6 EDP_TX1+ 8 7
4 CPU_EDP_TX1+ CPU_EDP_TX1- EDP_TX1- 8
C18 1 2 0.1U_0402_25V6 9
C 4 CPU_EDP_TX1- 9 C
10
CPU_EDP_AUX C20 1 2 0.1U_0402_25V6 EDP_AUX 11 10
4 CPU_EDP_AUX CPU_EDP_AUX# EDP_AUX# 11
C21 1 2 0.1U_0402_25V6 12
4 CPU_EDP_AUX# 12
13
DISPOFF# 14 13
INVT_PWM 15 14
+3VS 16 15
4 CPU_EDP_HPD 16
+LCDVDD_CON 17
17
Camera R183 1 2 0_0402_5%
W=60mils
18
18
2

+3VS_GSEN2 19
R10 MCU_I2C0_RE_SCL 20 19
PCH_ENBKL R11 1 L12 36 MCU_I2C0_RE_SCL MCU_I2C0_RE_SDA 20
@ 2 0_0402_5% 4.7K_0402_5% USB20_N8 USB20_N8_R 21
4,44 PCH_ENBKL 1 2 36 MCU_I2C0_RE_SDA 21
@ 9 USB20_N8 1 2 22
23 22
+3VS_DMIC
1

DMIC_CLK 24 23
USB20_P8 4 3 USB20_P8_R 30 DMIC_CLK 24
BKOFF# R12 1 2 0_0402_5% @ DISPOFF# 9 USB20_P8 4 3 DMIC_DATA 25
44 BKOFF# 30 DMIC_DATA 25
26
EXC24CH900U_4P 26
+3VS_CMOS 27
EMC_NS@ USB20_P8_R 27
28
USB20_N8_R 29 28
R182 1 2 0_0402_5% 29
+3VS 30
EDP_TX2+ 31 30
EDP_TX2- 32 31
@ PCH_TS_RST#_R 32
R127 1 2 0_0402_5% 33
2

8 PCH_TS_RST# EDP_TX3+ 33
34
R18 EDP_TX3- 34
35
1K_0402_5% 35
+3VS_Touch 36
@ 36
TS
1

R19 1 2 0_0402_5% @ INVT_PWM

4 PCH_EDP_PWM TS_I@ USB20_N6_R
RC3055 2 1 0_0402_5% PCH_TS_RST#_R HIGHS_FC5AF361-1151H
8 PCH_I2C_SDA1
1

ME@
TS_I@ USB20_P6_R
R20 RC3056 2 1 0_0402_5%

2
8 PCH_I2C_SCL1 W Touch panel
100K_0402_5% R77
B 0_0402_5% B
TS_U@
2

RC1 2 1 0_0402_5% UHD@

+3VS JEDP2

1
L6 EMC_NS@ +LEDVDD 1
USB20_N6 1 2 USB20_N6_R 2 1
9 USB20_N6 1 2 2
3
4 3
4
2

USB20_P6 4 3 USB20_P6_R EDP_TX0+ 5

R8 9 USB20_P6 4 3 EDP_TX0- 5
R9 6
100K_0402_1% 100K_0402_1% EXC24CH900U_4P 7 6
@ @ EDP_TX1+ 8 7
TS_U@ EDP_TX1- 9 8
RC2 2 1 0_0402_5%
1

10 9
EDP_AUX 10
EDP_AUX 11
EDP_AUX# 11
EDP_AUX# 12
TS@ 13 12
USB20_N6_R RC9 2 1 0_0402_5% 13
2

DISPOFF# 14
R15 R13 INVT_PWM 15 14
100K_0402_1% 100K_0402_1% CPU_EDP_HPD 16 15
CPU_EDP_TX2+ C6 1 2 0.1U_0402_25V6 UHD@ EDP_TX2+ 16
4 CPU_EDP_TX2+ +LCDVDD_CON 17
@ @ CPU_EDP_TX2- EDP_TX2- 17
C5 1 2 0.1U_0402_25V6 UHD@ 18
4 CPU_EDP_TX2-
1

19 18
+3VS_GSEN2 MCU_I2C0_RE_SCL 19
20
USB20_P6_R TS@ MCU_I2C0_RE_SDA 20
RC6 2 1 0_0402_5% 21
22 21
23 22
+3VS_DMIC DMIC_CLK 23
R28 2 1 0_0402_5% TS@ 24
44 EC_TS_ON DMIC_DATA 24
25
26 25
CPU_EDP_TX3+ C9 1 2 0.1U_0402_25V6 UHD@ EDP_TX3+ 27 26
EMI request 4 CPU_EDP_TX3+ +3VS_CMOS USB20_P8_R 28 27
CPU_EDP_TX3- C8 1 2 0.1U_0402_25V6 UHD@ EDP_TX3- USB20_N8_R 29 28 31
DMIC_CLK DISPOFF# INVT_PWM PCH_TS_RST#_R 4 CPU_EDP_TX3- 29 GND1
30 32
30 GND2
470P_0201_50V7-K

0.01U_0402_25V7K

A A
470P_0201_50V7-K
100P_0201_25V8J

2 R23 2 1 0_0402_5% TS_I@

EMC_NS@

1 1 8 PCH_TS_IRQ HIGHS_FC5AF301-3181H
EMC_NS@

C8799

EMC@

1
EMC@

ME@
C11

C13
C12

1 W/O Touch panel

2 2
2

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 eDP/CAMERA/TS_CONN.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EYG10_ES430_ES530
Date: Tuesday, January 09, 2018 Sheet 33 of 60
5 4 3 2 1
 5 4 3 2 1

+3VS

2
G
CPU_HDMI_TXP2 C42 2 1 0.1u_0201_10V6K HDMI_TX2_DP_C
4 CPU_HDMI_TXP2 CPU_HDMI_TXN2 HDMI_TX2_DN_C
C41 2 1 0.1u_0201_10V6K
4 CPU_HDMI_TXN2
PCH_HDMI_DDC_DATA 1 6 DDPB_DATA_U
CPU_HDMI_TXP1 HDMI_TX1_DP_C

S
C40 2 1 0.1u_0201_10V6K 4 PCH_HDMI_DDC_DATA

D
4 CPU_HDMI_TXP1 CPU_HDMI_TXN1 2 1 HDMI_TX1_DN_C
C39 0.1u_0201_10V6K Q4A
4 CPU_HDMI_TXN1 CPU_HDMI_TXP0 HDMI_TX0_DP_C
C38 2 1 0.1u_0201_10V6K
4 CPU_HDMI_TXP0 CPU_HDMI_TXN0 HDMI_TX0_DN_C 2N7002KDWH_SOT363-6
C37 2 1 0.1u_0201_10V6K
4 CPU_HDMI_TXN0
D CPU_HDMI_CLKP C36 2 1 0.1u_0201_10V6K HDMI_CLK_DP_C D
4 CPU_HDMI_CLKP

5
CPU_HDMI_CLKN C35 2 1 0.1u_0201_10V6K HDMI_CLK_DN_C

G
4 CPU_HDMI_CLKN

PCH_HDMI_DDC_CLK 4 3 DDPB_CLK_U

S
4 PCH_HDMI_DDC_CLK

D
Q4B
2N7002KDWH_SOT363-6
HDMI_TX0_DP_C R90 1 2 470_0402_5%
HDMI_TX0_DN_C R92 1 2 470_0402_5% +3VS
HDMI_TX1_DP_C R93 1 2 470_0402_5%
HDMI_TX1_DN_C R94 1 2 470_0402_5%
HDMI_TX2_DP_C R81 1 2 470_0402_5%

2
HDMI_TX2_DN_C R87
R83 1 2 470_0402_5%

2
Q12

G
1M_0402_5%
HDMI_CLK_DP_C R85 1 2 470_0402_5%

1
HDMI_CLK_DN_C R86 1 2 470_0402_5% CPU_HDMI_HPD 3 1 HDMI_DET
4 CPU_HDMI_HPD

D
2N7002KW_SOT323-3

2
D
2 R35
+3VS Q13
G 20K_0402_5%
2N7002KW_SOT323-3
S
3

1
1 2
R41
100K_0402_5%
@
C C

+5VS_HDMI

2
1
RP1
2.2K_0404_4P2R_5%
+5VS_HDMI
JHDMI1

3
4
18 15 DDPB_CLK_U
+5V_Power SCL 16 DDPB_DATA_U
SDA
+5VS_HDMI_F
F1 use 1A HDMI_TX0_DP_C R46 2 @ 1 0_0402_5% HDMI_TX0_DP_CON 7
+5VS_HDMI HDMI_TX0_DN_C R45 2 @ 1 0_0402_5% HDMI_TX0_DN_CON 9 TMDS_Data0+ 13
+5VS F1 HDMI_TX1_DP_C HDMI_TX1_DP_CON TMDS_Data0- CEC
R48 2 @ 1 0_0402_5% 4 17
1A_6V_TLC-NSMD100 HDMI_TX1_DN_C HDMI_TX1_DN_CON TMDS_Data1+ DDC/CEC_Ground HDMI_DET
R47 2 @ 1 0_0402_5% 6 19
1 3 1 2 HDMI_TX2_DP_C R50 2 @ 1 0_0402_5% HDMI_TX2_DP_CON 1 TMDS_Data1- Hot_Plug_Detect
D

HDMI_TX2_DN_C R49 2 @ 1 0_0402_5% HDMI_TX2_DN_CON 3 TMDS_Data2+

Q22 1 TMDS_Data2-
C34 8 14
LP2301ALT1G_SOT23-3
G
2

0.1u_0201_10V6K 5 TMDS_Data0_Shield Utility

2 TMDS_Data1_Shield
2 TMDS_Data2_Shield
46 SUSP
20
11 GND1 21
HDMI_CLK_DP_C R44 2 @ 1 0_0402_5% HDMI_CLK_DP_CON 10 TMDS_Clock_Shield GND2 22
HDMI_CLK_DN_C R43 2 @ 1 0_0402_5% HDMI_CLK_DN_CON 12 TMDS_Clock+ GND3 23
TMDS_Clock- GND4

ALLTO_C128S9-K1935-L
ME@

B B

L2
HDMI_TX0_DP_C 1 2 HDMI_TX0_DP_CON
1 2
D6
HDMI_CLK_DN_CON 1 1 10 9
HDMI_CLK_DN_CON
HDMI_TX0_DN_C 4 3 HDMI_TX0_DN_CON
4 3
HDMI_CLK_DP_CON 2 2 9 8
HDMI_CLK_DP_CON
EXC24CH900U_4P
HDMI_TX0_DN_CON 4 4 HDMI_TX0_DN_CON EMC@
7 7
HDMI_TX0_DP_CON 5 5 6 6
HDMI_TX0_DP_CON L3
HDMI_TX1_DP_C 1 2 HDMI_TX1_DP_CON
3 3 1 2
D3
HDMI_DET 1 1 10 9
HDMI_DET 8 HDMI_TX1_DN_C 4 3 HDMI_TX1_DN_CON
4 3
DDPB_DATA_U 2 2 9 8
DDPB_DATA_U EXC24CH900U_4P
AZ1045-04F_DFN2510P10E-10-9 For EMC EMC@
DDPB_CLK_U 4 4 7 7
DDPB_CLK_U
EMC_NS@
L4
+5VS_HDMI 5 5 6 6
+5VS_HDMI HDMI_TX2_DP_C 1 2 HDMI_TX2_DP_CON
1 2
D7
3 3 HDMI_TX1_DN_CON HDMI_TX1_DN_CON
1 1 10 9 HDMI_TX2_DN_C HDMI_TX2_DN_CON
4 3
8 4 3
HDMI_TX1_DP_CON 2 2 9 8 HDMI_TX1_DP_CON
EXC24CH900U_4P
HDMI_TX2_DN_CON HDMI_TX2_DN_CON EMC@
4 4 7 7
AZ1045-04F_DFN2510P10E-10-9
EMC_NS@ HDMI_TX2_DP_CON 5 5 6 6
HDMI_TX2_DP_CON L5
HDMI_CLK_DP_C 1 2 HDMI_CLK_DP_CON
3 3 1 2

A 8 HDMI_CLK_DN_C 4 3 HDMI_CLK_DN_CON A
4 3
EXC24CH900U_4P
AZ1045-04F_DFN2510P10E-10-9 EMC@ For EMC
EMC_NS@

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 HDMI_CONN

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EYG10_ES430_ES530
Date: Tuesday, January 09, 2018 Sheet 34 of 60
5 4 3 2 1
 A B C D E F G H

1 1

2 2

3 3

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 Blank
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EYG10_ES430_ES530
Date: Tuesday, January 09, 2018 Sheet 35 of 60
A B C D E F G H
 5 4 3 2 1

G-SENSOR
+3VS +3VS_GSEN1

@
R21 1 2 0_0603_5%
1
CG1
+3VS_GSEN1
+3VS 0.1u_0201_10V6K
@
2

2
1
+3VS_GSEN1
RG2

2
1
D RG1 D
1K_0404_4P2R_5%
1K_0404_4P2R_5%
@ YOGA@

3
4
UG1

3
4
1 8
VCCA VCCB
ISH_I2C0_SCL RC159 1 2 0_0402_5% @ MCU_I2C0_SCL 2 7 RC27 1 2 0_0402_5% @ MCU_I2C0_RE_SCL
8,43 ISH_I2C0_SCL A1 B1 MCU_I2C0_RE_SCL 33
ISH_I2C0_SDA RC160 1 2 0_0402_5% @ MCU_I2C0_SDA 3 6 RC28 1 2 0_0402_5% @ MCU_I2C0_RE_SDA
8,43 ISH_I2C0_SDA A2 B2 MCU_I2C0_RE_SDA 33
4 5
GND OE +3VS_GSEN1

2
NTSX2102GU8_XQFN8_1P2X1P4 RG3
When use ISH change RPG2/RPG1 to 1K 100K_0402_5%
@
@
When use ECSH change RPG2/RPG1 to 2.2K

1
EC_SMB_CK2 RC3049 1 2 0_0402_5% @ MCU_I2C0_SCL ISH_I2C0_SCL RG4 1 2 0_0402_5% @ MCU_I2C0_RE_SCL
7,26,39,44 EC_SMB_CK2 EC_SMB_DA2 RC3050 1 2 0_0402_5% @ MCU_I2C0_SDA
7,26,39,44 EC_SMB_DA2
ISH_I2C0_SDA RG5 1 2 0_0402_5% @ MCU_I2C0_RE_SDA

C C

+3VS
UG2
1 12 MCU_I2C0_RE_SCL
MCU_I2C0_RE_SDA 2 SDO SCx 11
SDx PS 10
+3VS 5 CSB
6 INT1 9
3 INT2 GND 8
7 VDDIO GNDIO 4
VDD NC
0.1u_0201_10V6K

1 1 0.1u_0201_10V6K
YOGA@
BMA253_LGA12P_2X2
CD@

CG2

CG3 YOGA@

2 2

B B

LID switch

+3VL
U14
R264 1 2 0_0402_5% @ +VCC_LID 2
VCC
2
C1105
3 R22 1 2 0_0402_5% @ LID_SW#
0.01U_0201_10V6K OUTPUT LID_SW# 43,44
530S@ 1 1
GND 2
C1104
AH9247-W-7_SC59-3 100P_0201_25V8J
530S@ 530S@
1

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 HALL/G Sensor

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EYG10_ES430_ES530
Date: Tuesday, January 09, 2018 Sheet 36 of 60
5 4 3 2 1
 5 4 3 2 1

+3VS
+3VS_SSD1

R4682 1 2 0_0805_5% @ Min 3A

10U_0402_6.3V6-M

10U_0402_6.3V6M

4.7U_0402_6.3V6M

0.1u_0201_10V6K
1 1 1 1

C2093

C2094

C2095
C2037
@
D 2 2 2 2 D

+3VS_SSD1

JSSD2
76
GND15
1 2
3 GND1 3.3V_1 4
5 GND2 3.3V_2 6
9 PCIE_PRX_DTX_N9 PERn3 N/C_2
7 8
9 PCIE_PRX_DTX_P9 PERp3 N/C_3
9 10
0.22U_0201_6.3V6-K 1 2 C2039 PCIE_PTX_C_DRX_N9 11 GND3 DAS/DSS#(I/O)/LED1#(I)(0/3.3V) 12
9 PCIE_PTX_DRX_N9 PCIE_PTX_C_DRX_P9 PETn3 3.3V_3
0.22U_0201_6.3V6-K 1 2 C2038 13 14
9 PCIE_PTX_DRX_P9 15 PETp3 3.3V_4 16
17 GND4 3.3V_5 18
9 PCIE_PRX_DTX_N10 PERn2 3.3V_6
19 20
9 PCIE_PRX_DTX_P10 21 PERp2 N/C_4 22
0.22U_0201_6.3V6-K 1 2 C2040 PCIE_PTX_C_DRX_N10 23 GND5 N/C_5 24
9 PCIE_PTX_DRX_N10 PCIE_PTX_C_DRX_P10 PETn2 N/C_6
0.22U_0201_6.3V6-K 1 2 C2041 25 26

1
9 PCIE_PTX_DRX_P10 PETp2 N/C_7
27 28
GND6 N/C_8 R4678
29 30
9 PCIE_PRX_DTX_N11 31 PERn1 N/C_9 32 10K_0402_5%
9 PCIE_PRX_DTX_P11 PERp1 N/C_10 @
33 34
0.22U_0201_6.3V6-K 1 2 C2042 PCIE_PTX_C_DRX_N11 35 GND7 N/C_11 36

2
9 PCIE_PTX_DRX_N11 PCIE_PTX_C_DRX_P11 PETn1 N/C_12 @
9 PCIE_PTX_DRX_P11 0.22U_0201_6.3V6-K 1 2 C2043 37 38 R70 1 2 0_0402_5%
PETp1 DEVSLP(O) PCH_SATA_1_DEVSLP 9
39 40
41 GND8 N/C_13 42
9 PCIE_PRX_DTX_P12 PERn0/SATA-B+ N/C_14
43 44
9 PCIE_PRX_DTX_N12 45 PERp0/SATA-B- N/C_15 46
0.22U_0201_6.3V6-K 1 2 C2044 PCIE_PTX_C_DRX_N12 47 GND9 N/C_16 48
C 9 PCIE_PTX_DRX_N12 PCIE_PTX_C_DRX_P12 PETn0/SATA-A- N/C_17 PLT_RST# C
9 PCIE_PTX_DRX_P12 0.22U_0201_6.3V6-K 1 2 C2045 49 50
51 PETp0/SATA-A+ PERST#(O)(0/3.3V) or N/C 52 SSD_1_CLKREQ_Q# PLT_RST# 11,26,38,40,44
R4679 1 2 0_0402_5% @
SSD_1_CLKREQ# 10
53 GND10 CLKREQ#(I/O)(0/3.3V) or N/C 54 TP265 1
10 CLK_PCIE_SSD_1# 55 REFCLKn PEWAKE#(I/O)(0/3.3V) or N/C 56
10 CLK_PCIE_SSD_1 REFCLKp N/C_18
57 58
GND11 N/C_19

+3VS_SSD1

67 68
SSD_2_DET 69 N/C_1 SUSCLK(32kHz)(O)(0/3.3) 70
71 PEDET(NC-PCIe/GND-SATA) 3.3V_7 72
73 GND12 3.3V_8 74
75 GND13 3.3V_9
GND14 77
GND16

ARGOS_NASM0-S6705-TSH4
ME@

Change Symbol to SP011511122 Bourne 0705

B B

+3VS_SSD1
1

R4680
R79 1 2 0_0402_5% @
9 SSD_2_PCIE_DET# 10K_0402_5%
@
2
1

D
2 SSD_2_DET
Q1 G
2N7002KW_SOT323-3
S
@
3

SSD_DET#
0--SATA
1--PCIE

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 NGFF_SSD_1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EYG10_ES430_ES530
Date: Tuesday, January 09, 2018 Sheet 37 of 60
5 4 3 2 1
 5 4 3 2 1

+3VS +3VS_SSD2

R42 1 2 0_0805_5% @ Min 3A

10U_0402_6.3V6-M

10U_0402_6.3V6M

4.7U_0402_6.3V6M

0.1u_0201_10V6K
1 1 1 1

C8785

530S@

C8786

530S@

C8788

530S@

C8787
@
D D

2 2 2 2

+3VS_SSD2
JSSD3
76
GND15
1 2
3 GND1 3.3V_1 4
5 GND2 3.3V_2 6
1 7 PERn3 N/C_2 8
@ TP1 PERp3 N/C_3
9 10
11 GND3 DAS/DSS#(I/O)/LED1#(I)(0/3.3V) 12
13 PETn3 3.3V_3 14
15 PETp3 3.3V_4 16
17 GND4 3.3V_5 18
19 PERn2 3.3V_6 20
21 PERp2 N/C_4 22
23 GND5 N/C_5 24
PETn2 N/C_6

1
1 25 26
@ TP2 PETp2 N/C_7
27 28 R40
29 GND6 N/C_8 30
9 PCIE_PRX_DTX_N7 PERn1 N/C_9 10K_0402_5%
31 32
9 PCIE_PRX_DTX_P7 PERp1 N/C_10 @
C 33 34 C

2
0.22U_0201_6.3V6-K 1 2 C8783 530S@ PCIE_PTX_C_DRX_N7 35 GND7 N/C_11 36
9 PCIE_PTX_DRX_N7 PETn1 N/C_12
9 PCIE_PTX_DRX_P7 0.22U_0201_6.3V6-K 1 2 C8784 530S@ PCIE_PTX_C_DRX_P7 37 38
39 PETp1 DEVSLP(O) 40
41 GND8 N/C_13 42
9 PCIE_PRX_DTX_P8 PERn0/SATA-B+ N/C_14
43 44
9 PCIE_PRX_DTX_N8 45 PERp0/SATA-B- N/C_15 46
0.22U_0201_6.3V6-K 1 2 C8781 530S@ PCIE_PTX_C_DRX_N8 47 GND9 N/C_16 48
9 PCIE_PTX_DRX_N8 PETn0/SATA-A- N/C_17
0.22U_0201_6.3V6-K 1 2 C8782 530S@ PCIE_PTX_C_DRX_P8 49 50 PLT_RST#
9 PCIE_PTX_DRX_P8 PETp0/SATA-A+ PERST#(O)(0/3.3V) or N/C SSD_2_CLKREQ_Q# PLT_RST# 11,26,37,40,44
51 52 R34 1 2 0_0402_5% @
GND10 CLKREQ#(I/O)(0/3.3V) or N/C SSD_2_CLKREQ# 10
10 CLK_PCIE_SSD_2# 53 54 1
55 REFCLKn PEWAKE#(I/O)(0/3.3V) or N/C 56 TP314@
10 CLK_PCIE_SSD_2 REFCLKp N/C_18
57 58
GND11 N/C_19

+3VS_SSD2

67 68
SSD_1_DET 69 N/C_1 SUSCLK(32kHz)(O)(0/3.3) 70
71 PEDET(NC-PCIe/GND-SATA) 3.3V_7 72
73 GND12 3.3V_8 74
75 GND13 3.3V_9
GND14 77
GND16

ARGOS_NASM0-S6705-TSH4
ME@

Change Symbol to SP011511122 Bourne 0705

+3VS_SSD2

B B
1

R32
1 2 0_0402_5% @ 10K_0402_5%
R78
9 SSD_1_PCIE_DET# @
2
1

D
2 SSD_1_DET
Q2 G
2N7002KW_SOT323-3
@ S
SSD_DET#
3

0--SATA
1--PCIE

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 NGFF_SSD_2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EYG10_ES430_ES530
Date: Tuesday, January 09, 2018 Sheet 38 of 60
5 4 3 2 1
 5 4 3 2 1

REMOTE2+
Close to U1 REMOTE+_R R176 1 2 0_0402_5% @ REMOTE2+
Near CPU core
1

1
REMOTE+_R C46 C
1 100P_0201_25V8J 2 Q16
C44 REMOTE-_R R177 1 2 0_0402_5% @ REMOTE2- B MMBT3904WH_SOT323-3
2200P_0201_25V7-K 2 E
Near GPU&VRAM

3
REMOTE2-
2 REMOTE-_R
REMOTE+/-_R, REMOTE1+/-, REMOTE2+/-:
Trace width/space:10/10 mil +3VALW
D Trace length:<8" +3VALW D
Near CPU

1
R36
13.7K_0402_1% R25
13.7K_0402_1%

2
NTC_V1

2
NTC_V2
SMSC thermal sensor

1
R287
placed near DIMM 100K_0402_1%_NCP15WF104F03RC
OPT@
R288
100K_0402_1%_NCP15WF104F03RC
+3VS

2
U1

2
1 8 EC_SMB_CK2
VDD SCL EC_SMB_CK2 7,26,36,44
REMOTE+_R 2 7 EC_SMB_DA2
1 D+ SDA EC_SMB_DA2 7,26,36,44
C47
0.1u_0201_10V6K REMOTE-_R 3 6
D- ALERT#
2 2 1 4 5
+3VS T_CRIT# GND
R51
NCT7718W_MSOP8
10K_0402_5%

Address 1001_101xb
C C

+5VS_FAN
+5VS

+5VLP +5VLP
+5VLP
R57 1 2 0_0603_SM @

HW thermal sensor

0.1u_0201_10V6K
10U_0805_10V6K
2

2 1 1
0.1u_0201_10V6K

C8798

C8797
1 R252 R253
21.5K_0402_1% @
21.5K_0402_1%
C7

@ @
@ 2 2
FAN Conn
1

2
U4 +5VS_FAN
1 8 TMSNS1 R196 1 @ 2 0_0402_5% NTC_V1 JFAN2
VCC TMSNS1 NTC_V1 44
+5VS_FAN 1
2 7 PHYST1 R6 1 @ 2 10K_0402_5% 1
GND RHYST1 44 EC_FAN_PWM
2 5
3 2 GND1 6
3 6 TMSNS2 R197 1 @ 2 0_0402_5%NTC_V2 44 EC_FAN_SPEED 3 GND2
44,54,55 EC_ON OT1 TMSNS2 NTC_V2 44 4
4
4 5 PHYST2 R7 1 @ 2 10K_0402_5%
OT2 RHYST2
CVILU_CI1804M2HR0-NH
G718TM1U_SOT23-8
@ ME@

B B
+5VS +5VS_FAN1 Change Symbol to SP01001JO00 Bourne 0629
over temperature threshold:
R52 1 2 0_0603_SM @
RSET=3*RTMH

0.1u_0201_10V6K
10U_0805_10V6K
92+/-30C 1
1

C49

C50
Hysteresis temperature threshold. @
RHYST=(RSET*RTML)/(3*RTML-RSET) 2
+5VS_FAN1
FAN Conn
2
56+/-30C JFAN1
+5VS_FAN1 1
2 1 5
44 EC_FAN_PWM1 2 GND1
44 EC_FAN_SPEED1
3 6
4 3 GND2
4

CVILU_CI1804M2HR0-NH
ME@
Change Symbol to SP01001JO00 Bourne 0629

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2016/08/16 Deciphered Date 2017/08/15 Thermal sensor/FAN CONN.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EYG10_ES430_ES530
Date: Tuesday, January 09, 2018 Sheet 39 of 60
5 4 3 2 1
 A B C D E

1 1

Mini-Express Card(WLAN/WiMAX)

+3VS_WLAN +3VS
+3VS Need short +3VS_WLAN
1
JWLAN1
2
J2 @ 3 GND1 3.3V-2 4
9 USB20_P7 USB_D+ 3.3V-4
1 2 5 6 1

1
1 2 9 USB20_N7 USB_D- LED1# T2 @

1
7 8
JUMP_43X79 9 GND2 PCM_CLK/12S SCK 10 R258 R259
1 SDIO_CLK PCM_SYNC/12S WS
C53 11 12 49.9K_0402_1% 49.9K_0402_1%
0.1u_0201_10V6K 13 SDIO_CMD PCM_OUT/12S SD_OUT 14
@ 15 SDIO_DAT0 PCM_IN/12S SD_IN 16 1

2
T3 @

2
2 17 SDIO_DAT1 LED2# 18
19 SDIO_DAT2 GND11 20
+3VALW 21 SDIO_DAT3 UART WAKE# 22 UART_RX_DEBUG_R R256 1 2 0_0402_5% @
Q36 SDIO_WAKE# UART TXD UART_RX_DEBUG 8
23
LP2301ALT1G_SOT23-3 SDIO_RESET#
AOAC@
S

3 1
0.1u_0201_10V6K

1 1 25 KEY E 24
C2083 27 PIN24~PIN31 NC PIN 26
G

C2082
2

0.1u_0201_10V6K @ 29 28
@ 31 30
2 2
R4677 33 32 UART_TX_DEBUG_R R257 1 2 0_0402_5% @
AOAC_ON# GND3 UART RXD UART_TX_DEBUG 8
1 2 35 34
8 AOAC_ON# 9 PCIE_PTX_C_DRX_P5 37 PERP0 UART RTS 36
100K_0402_5% 9 PCIE_PTX_C_DRX_N5 PERN0 UART CTS EC_TX_RSVD
2 1 39 38 R62 1 @ 2 0_0402_5% 2
AOAC@ 41 GND4 RSRVD4 40 EC_RX_RSVD 1 2 0_0402_5%
R63 @
C2081 9 PCIE_PRX_DTX_P5 PETP0 RSRVD3
43 42
0.1u_0201_10V6K 9 PCIE_PRX_DTX_N5 PETN0 RSRVD2
45 44 R88 1 2 0_0402_5% @
AOAC_ON# 1 R1266 2 2 AOAC@ 47 GND5 COEX3 46 EC_RX 44
10 CLK_PCIE_WLAN REFCLKP0 COEX2
49 48
100K_0402_5% 10 CLK_PCIE_WLAN# 51 REFCLKN0 COEX1 50 SUSCLK_R 1 2 0_0402_5% @
R55
AOAC@ WLAN_CLKREQ_Q# GND6 SUSCLK PLT_RST# SUSCLK 10
10 WLAN_CLKREQ# R61 1 2 0_0402_5% @ 53 52
PCIE_WAKE#_WLAN CLKREQ0# PERSTO# BT_OFF# PLT_RST# 11,26,37,38,44
R262 1 2 0_0402_5% @ 55 54 R53 1 2 1K_0402_5%
11 PCIE_WAKE# 57 PEWAKE0# W_DISABLE2# 56 WLAN_OFF# 1 2 0_0402_5% @ PCH_BT_OFF# 8
R56
GND7 W_DISABLE1# PCH_WLAN_OFF# 8

59 58 WLAN_SMB_DATA R58 1 @ 2 0_0402_5%

RESERVED/PERP1 I2C_DATA WLAN_SMB_CLK SMB_DATA_S3 7,18
61 60 R59 1 @ 2 0_0402_5%
63 RESERVED/PERN1 I2C_CLK 62 SMB_CLK_S3 7,18
65 GND8 ALERT# 64 EC_TX_R R89 1 2 0_0402_5% @
67 RESERVED/PETP1 RSRVD1 66 EC_TX 44
69 RESERVED/PETN1 UIM_SWP/PERST1# 68 +3VS_WLAN
GND9 UIM_POWER_SNK/CLKREQ1#

1
71 70
73 RESERVED/REFCLKP1 UIM_POWER_SRC/GPIO1/PEWAKE1# 72 R186
75 RESERVED/REFCLKN1 3.3V-72 74 100K_0402_5%
GND10 3.3V-74
77 76

2
GND13 GND12

ARGOS_NASE0-S6701-TSH4
ME@

3 3

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2016/12/14 Deciphered Date 2017/12/13 NGFF_WLAN

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EYG10_ES430_ES530
Date: Tuesday, January 09, 2018 Sheet 40 of 60
A B C D E
 5 4 3 2 1

RIGHT SIDE USB3.0 PORT x1

USB charger CLT1 CLT2 CLT3 ILIM_SEL MOD

2.2A 0 0 0 X DCH OUT held low

+5VALW U8
SN1702001RTER_WQFN16_3X3 1 1 1 1 CDP Data Connected and Port Power Mgt. Function Active

1 16 ILIM_HI R2047 1 2 20K_0402_1%

*
D USB20_N1 2
IN ILIM_HI
15 ILIM_LO R2048 1 @ 2 20K_0402_1%
* 1 1 1 0 SDP2 Data Connected
D
9 USB20_N1 DM_OUT ILIM_LO

9 USB20_P1
USB20_P1 3
DP_OUT GND
14 * 1 1 0 X SDP1 Data Connected
ILIM_SEL 4 13 USB_OC1#

USB_CHG_EN 5
ILIM_SEL FAULT
12
USB_OC1#

+USB_VCCA
9
* 0 1 0 X SDP1 Data Connected
44 USB_CHG_EN EN OUT
CHG_MOD1 R37 1 2 0_0402_5% @ 6 11 USB20_N1_C 1 0 0 X DCP_Short Device Forced to stay in DCP BC 1.2 charging mode
44 CHG_MOD1 CLT1 DM_IN
7 10 USB20_P1_C
CLT2 DP_IN 1 0 1 X Device Forced to stay in DCP Divider 1 Charging Mode
DCP_Divider

E_PAD
CHG_MOD3 R39 1 2 0_0402_5% @ 8 9 AOU_DET#_R @ 0_0402_5% 2 1 R38 AOU_DET#
44 CHG_MOD3 CLT3 STATUS AOU_DET# 44
0 1 1 X DCP_Auto Data Disconnected and Port Power Mgt. Function Active
2 *

17
C197
0 0 1 X DCP_Auto Data Disconnected and Power Wake Function Active
0.1u_0201_10V6K
@ 1
+5VALW

R2051 2 1 10K_0402_5% AOU_DET#_R

+5VALW

R2064 1 2 0_0402_5% @ ILIM_SEL

+USB_VCCA

R2052 1 @ 2 10K_0402_5% USB_CHG_EN

100U_1206_6.3V6M

100U_1206_6.3V6M
0.1u_0201_10V6K
R68 1 @ 2 0_0402_5% 1 1 1

C2630
C C

C187

C2631
1 @ 2 10K_0402_5% ILIM_SEL
R2065 @
L4210
USB20_N1_C 1 2 USB20_N1_R 2 2 2
1 2

USB20_P1_C 4 3 USB20_P1_R
4 3
EXC24CH900U_4P
EMC@

R67 1 @ 2 0_0402_5%

R65 1 @ 2 0_0402_5%

+USB_VCCA
L4208
USB30_TX_P2 JUSB5
C8790 1 2 0.1u_0201_10V6K USB30_TX_C_P2 1 2 USB30_TX_R_P2
9 USB30_TX_P2 1 2
USB30_TX_R_P2 9
USB30_TX_N2 C8789 1 2 0.1u_0201_10V6K USB30_TX_C_N2 4 3 USB30_TX_R_N2 1 StdA_SSTX+
9 USB30_TX_N2 4 3 USB30_TX_R_N2 VBUS
8
EXC24CH900U_4P USB20_P1_R 3 StdA_SSTX-
EMC@ 7 D+
USB20_N1_R 2 GND_DRAIN 10
R66 1 @ 2 0_0402_5% USB30_RX_R_P2 6 D- GND_2 11
4 StdA_SSRX+ GND_3 12
USB30_RX_R_N2 5 GND_1 GND_4 13
R69 1 @ 2 0_0402_5% StdA_SSRX- GND_5

ALLTO_C190AG-10939-L
L4209
USB30_RX_P2 USB30_RX_R_P2 ME@
1 2
9 USB30_RX_P2 1 2

USB30_RX_N2 4 3 USB30_RX_R_N2
9 USB30_RX_N2 4 3
B EXC24CH900U_4P B
EMC@

R71 1 @ 2 0_0402_5%

USB20_P1_R
+USB_VCCA
USB20_N1_R
D4313 EMC@
USB30_RX_R_N2 9 1USB30_RX_R_N2
10 1
1

USB30_RX_R_P2 8 2 USB30_RX_R_P2
AZ5725-01F.R7GR_DFN1006P2X2

9 2
1

AZ5425-01F_DFN1006P2E2

AZ5425-01F_DFN1006P2E2
2

2
EMC@

D4314

EMC@

USB30_TX_R_N2 7 4USB30_TX_R_N2
EMC@

7 4
D10

D9

USB30_TX_R_P2 6 6 5 USB30_TX_R_P2
5
2

3 3
2

8
EMC
AZ1045-04F_DFN2510P10E-10-9

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 USB3 PORT_LEFT

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EYG10_ES430_ES530
Date: Tuesday, January 09, 2018 Sheet 41 of 60
5 4 3 2 1
 5 4 3 2 1

R943 1 @ 2 0_0402_5%

L23 VBUS_P0
C_DM

GND6
GND5
USB30_TX_P3 USB30_TX_P3_M 1 2 VBUS_P0
CW45 1 2 0.1U_0201_6.3V6-K 9 USB20_N2 1 2
9 USB30_TX_P3 USB30_TX_N3 CW44 1 2 0.1U_0201_6.3V6-K USB30_TX_N3_M JUSB4
9 USB30_TX_N3
4 3 C_DP

GND9
GND10
9 USB20_P2 4 3
USB30_RX_P3 CW46 2 1 0.1U_0201_6.3V6-K USB30_RX_P3_M EXC24CH900U_4P A12 B1
9 USB30_RX_P3 USB30_RX_N3 USB30_RX_N3_M GND2 GND3
CW47 2 1 0.1U_0201_6.3V6-K EMC@
D 9 USB30_RX_N3 C_RX2_P_C C_TX2_P_C D
A11 B2
R91 1 @ 2 0_0402_5% SSRXp2 SSTXp2
C_RX2_N_C A10 B3 C_TX2_N_C
+3V_MUX +3V_MUX
Rp configuration SSRXn2 SSTXn2
A9 B4
Vbus2 Vbus3
A8 B5 CC2
2

Rp:1.5A (now) SBU1 CC2

R3139 R3142 C_DM C_DP
A7 B6
10K_0402_5% 10K_0402_5% Dn1 Dp2
M1 M0 Note C_DP C_DM
A6 B7
Rp:900mA 0 1 +3VALW +3V_MUX +5VALW Dp1 Dn2
R3144/R3142 mount
1

+5V_MUX
TYPE_C_M1_R TYPE_C_M0_R CC1 A5 B8
Rp:1.5A 1 0 R133 1 2 0_0402_5% CC1 SBU2
R3139/R3143 mount R173 1 2 0_0402_5% @
A4 B9
2

Rp:3.0A 1 1 +3VS Vbus1 Vbus4

R3144 R4674 R3139/R3142 mount +5VS C_TX1_N_C C_RX1_N_C
A3 B10
@ 10K_0402_5% 10K_0402_5% SSTXn1 SSRXn1
R134 1 @ 2 0_0402_5%
R174 1 @ 2 0_0402_5% C_TX1_P_C C_RX1_P_C
@ A2 B11
SSTXp1 SSRXp1
1

0.1u_0201_10V6K

GND5
GND6
GND7
GND8
4.7U_0402_6.3V6M
A1 B12
2 GND1 GND4
1

C2064
CC1273
ATOB_066-12A1-3211

GND1
GND2
GND3
GND4
1 ME@
2
+3V_MUX
For C_VBUS
2

power switch enable pin Close Pin20

R3146
10K_0402_5%
@
Power switch enable pin Note @
R3135 1 2 0_0402_5%
1

VBUS_EN
Low Active R3146 mount 2 2
2

CC1271 CC1272 L31

High Active R3141 mount U26 220P_0201_25V7-K 220P_0201_25V7-K C_RX1_N C_RX1_N_C
R3141 4 3
C
10K_0402_5% 1 1 4 3 C
@
10K_0402_5% 2 1 R76 23 12 CC1 A5
NC CC1 14 CC2 C_RX1_P 1 2 C_RX1_P_C
B5
1

CC2 1 2
USB30_RX_N3_M 5 8 MUX_TX1_P C2073 1 2 0.1U_0201_6.3V6-K C_TX1_P EXC24CH900U_4P
USB30_RX_P3_M 4 SSRX_1N/2P C_TX1_1P/2N 9 MUX_TX1_N C2074 1 2 0.1U_0201_6.3V6-K C_TX1_N A2 EMC@
SSRX_1P/2N C_TX1_1N/2P A3
R3137 1 @ 2 0_0402_5%
USB30_TX_N3_M 7 2 C_RX1_P
USB30_TX_P3_M 6 SSTX_1N/2P C_RX1_1P/2N 3 C_RX1_N B11
+3V_MUX
For C_VBUS SSTX_1P/2N C_RX1_1N/2P B10
power switch OCP pin 11 MUX_TX2_P C2076 1 2 0.1U_0201_6.3V6-K C_TX2_P
C_TX2_1P/2N 10 MUX_TX2_N C2075 1 2 0.1U_0201_6.3V6-K C_TX2_N B2 R3136 1 @ 2 0_0402_5%
TYPE_C_M1 R72 2 TYPE_C_M1_R C_TX2_1N/2P B3
2

1 0_0402_5% @ 21
R3147 44 TYPE_C_M1 RP_SEL_M1 24 C_RX2_P A10
10K_0402_5% TYPE_C_M0 R74 2 1 0_0402_5% @ TYPE_C_M0_R 22 C_RX2_1P/2N 1 C_RX2_N L32
44 TYPE_C_M0 A11
RP_SEL_M0 C_RX2_1N/2P C_TX1_N 1 2 C_TX1_N_C
Power switch OCP pin +3V_MUX
Note TYPE_C_OCP# 16 1 2
1

TYPE_C_OCP# OCP_DET 20
Low Active +5V_MUX
R3147 mount VBUS_EN 15 LDO_3V3 R33 1 2 0_0402_5% C_TX1_P 4 3 C_TX1_P_C
VBUS_EN 4 3
2

19 R75 1 @ 2 0_0402_5%
R3140 High Active R3140 mount 6.2K_0402_1% 1 2 R3150 TYPE_C_REXT 18 5V_IN 13 EXC24CH900U_4P
10K_0402_5% REXT VCON_IN EMC@
VMON 17 25 @
@ VMON E-PAD Use LDO:Stuff R75,un-stuff R33,R133 R3138 1 2 0_0402_5%

0.1u_0201_10V6K
Close LDO:Stuff R33,R133,Un-stuff R75
1

2 2

C2063
RTS5448-GR_QFN24_4X4 C2077 @
R944 2 1 0_0402_5%
10U_0603_10V6K
1 1
L24
C_TX2_P 2 1 C_TX2_P_C
2 1

Close Pin19 C_TX2_N 3 4 C_TX2_N_C

VBUS_P0 3 4
EXC24CH900U_4P
EMC@
1

B B
R3107 2 @ 1 0_0402_5%
3.4A
R3155
200K_0402_1% +5VALW VBUS_P0 CC1 C_DM
U27 VBUS_P0 C_DP
CC2
2

5 1
VMON IN OUT

AZ5425-01F.R7GR DFN1006P2E

AZ5425-01F.R7GR DFN1006P2E

AZ5425-01F.R7GR DFN1006P2E
2

AZ5725-01F.R7GR_DFN1006P2X2

AZ5425-01F.R7GR DFN1006P2E
GND

1
2

1
VBUS_EN 4 3 TYPE_C_OCP#
@

1
R3149 EN FLAG TYPE_C_OCP# 9 R100 2 1 0_0402_5%

EMC_NS@
1

1
EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@
10K_0402_1%

D12
G517G1TO1U_TSOT-23-5

D38

D11

D13

D14
L25
C_RX2_P 3 4 C_RX2_P_C
1

3 4
+5VALW

2
2

2
VBUS_P0

2
C_RX2_N 2 1 C_RX2_N_C

2
2 1
EXC24CH900U_4P
1
150U_B2_6.3VM_R35M

47U_0805_6.3V6-M

EMC@
10U_0805_25V6K

4.7U_0805_25V6-K

0.47U_0402_25V6K

0.47U_0402_25V6K

0.47U_0402_25V6K

0.47U_0402_25V6K

+ 1 @
C1333

1 1 1 1 1 1 R101 2 1 0_0402_5%
C213

@
C1334
C918

C919

C922

C921

C920

2 @
2
2 2 2 2 2 2
D36 D20
C_TX2_P_C 9 10 1 C_TX2_P_C C_TX1_P_C 9 10 1 C_TX1_P_C
1 1
C_TX2_N_C 8 2 C_TX2_N_C C_TX1_N_C 8 2 C_TX1_N_C
9 2 9 2
C_RX1_N_C 7 4 C_RX1_N_C C_RX2_N_C 7 4 C_RX2_N_C
7 4 7 4
C_RX1_P_C 6 5 C_RX1_P_C C_RX2_P_C 6 5 C_RX2_P_C
6 5 6 5

3 3 3 3
A 8 8 A

AZ1045-04F_DFN2510P10E-10-9 AZ1045-04F_DFN2510P10E-10-9
EMC_NS@ For ESD EMC_NS@

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 TYPE-C_RTS5448

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EYG10_ES430_ES530
Date: Tuesday, January 09, 2018 Sheet 42 of 60
5 4 3 2 1
 A B C D E

Right SIDE USB3.0 PORT

1 +USB_VCCB 1

+5VALW +USB_VCCB J3
U2 1
5 1 1
IN OUT 2
1 3 2
C128 2 3
GND 4
1U_0402_6.3V6K 4
USB_OC0# 5
4 3 5
2 44 USB_ON# ENB OCB USB_OC0# 9 6
USB30_TX_P1 7 6
SY6288D20AAC_SOT23-5 1 9 USB30_TX_P1 USB30_TX_N1 7
8
C140 9 USB30_TX_N1 9 8
1000P_0201_50V7-K USB30_RX_P1 9
10
Low Active 2A EMC_NS@ 9 USB30_RX_P1 USB30_RX_N1 11 10
2 9 USB30_RX_N1 11
12
USB20_P3 13 12
9 USB20_P3 USB20_N3 14 13
9 USB20_N3 14
15
USB20_N5 16 15
9 USB20_N5 USB20_P5 16
17
9 USB20_P5 17
18
19 18
+3VL +3VS 19
20
ON/OFFBTN# 21 20
NOVO_BTN# 22 21
2

PWR_LED_WIT#_R 23 22
R82 24 23
PWR_LED_ABR# +3VALW 24
25
100K_0402_5% 44,45 PWR_LED_ABR# LID_SW#_1 26 25
LID_SW#_2 27 26
1

28 27
NOVO_BTN# +3VL 28
NOVO# R261 1 2 0_0402_5% @ 29
44 NOVO# 30 GND1
GND2
ACES_88194-2841
ME@
2 2
+3VL LID_SW# R29 2 1 0_0402_5% @ LID_SW#_1
36,44 LID_SW#
2

TAB_SW# R30 2 1 0_0402_5% @ LID_SW#_2

44 TAB_SW#
R114
100K_0402_5% PWR_LED_WIT# R73 2 1 0_0402_5% @ PWR_LED_WIT#_R
44,45 PWR_LED_WIT#
1

ON/OFF 2 1 ON/OFFBTN#
44 ON/OFF
R119
2

2
SHORT PADS

SHORT PADS

0_0402_5%
J5

@ @
J6

@
1

3 3

JDEBUG
ISH_I2C0_SCL 1
8,36 ISH_I2C0_SCL ISH_I2C0_SDA 1
2
8,36 ISH_I2C0_SDA ISH_I2C1_SCL 2
3
8 ISH_I2C1_SCL ISH_I2C1_SDA 4 3
8 ISH_I2C1_SDA 4
5
ISH_GP0 6 5
8 ISH_GP0 ISH_GP6 6
7
8 ISH_GP6 7
8
9 8
10 9
11 10
12 11
13 12
14 13
+3VS 15 14
16 15
17 16
18 17
18

19
GND1
20
GND2
ELCO_04-6809-618-210-846+
ME@

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 I/O_DB_CONN

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EYG10_ES430_ES530
Date: Tuesday, January 09, 2018 Sheet 43 of 60
A B C D E
 5 4 3 2 1

+3VL_EC +3VL_EC
RE1 1 2 0_0603_SM @ +3VL

1
RE12 RE16 1 2 0_0603_5% +3VL_EC
RE3 @ +3VALW +3VL_EC
100K_0402_5% 100K_0402_5% +3VL_EC_R
OPTN16@ YOGA@
All capacitors close to EC LE1 1 2 0_0603_SM @
2

2
EC_ID0 EC_ID1
Close EC +3VL_EC

1000P_0201_50V7-K
0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K
1

1
1 1
CE3 1 1 1 1 1 1

CE4

CE5
RE13 RE17 +3VS

CD@

CE7

CE9

CE10

CE11
1 2 VCOREVCC +3VL_EC_R

CE6

CE8
100K_0402_5% 100K_0402_5% +3VS +3VS @ @
D UMAorN17@ 530S@ 0.1u_0201_10V6K 2 2 8396@ D
2 2 2 2 2 2 EC_SMB_DA4 RE721 2 1 4.7K_0402_5%
2

2
1 EC_SMB_CK4
CE19 RE6 1 2 0_0402_5% @ RE722 2 8396@ 1 4.7K_0402_5%
0.1u_0201_10V6K LE2 1 2 0_0603_5% EC_AGND
EC_FAN_SPEED RE10 1 2 10K_0402_5%
2
EC_FAN_SPEED1 RE35 2 1 10K_0402_5%
Close J5 minimum trace width 12 mil

D10
K10
D4
D5
K5

K4
E4

E9
EC_AGND

J4

J5
UE1 EC_FAN_PWM RE11 1 @ 2 10K_0402_5%
EC_FAN_PWM1

VSTBY1
VSTBY2
VSTBY3
VSTBY4
VSTBY5
VCC

VSTBY(PLL)

AVCC
VBAT

VCORE
RE4 1 @ 2 10K_0402_5%
LPC_FRAME# RE7 1 @ 2 10K_0402_5%
26 WRST# CPU_VR_READY RE270 1 2 10K_0402_5%
RE56 2 1 0_0402_5% @ H4 M5 PWR_LED_WIT#
7 KBRST# KBRST#/GPB6 PWM0/GPA0 PWR_LED_WIT# 43,45 EC_TP_ON RE277 1 @ 2 10K_0402_5%
RE59 2 1 0_0402_5% @ G2 N5 PWR_LED_ABR#
DE1 7 SERIRQ LPC_FRAME#_EC H1 SERIRQ/GPM6 PWM1/GPA1 BATT_LOW_LED# PWR_LED_ABR# 43,45
RE60 1 2 0_0402_5% @ M6
7 LPC_FRAME# LPC_AD3_EC LFRAME#/GPM5 PWM2/GPA2 EC_KB_BKL_EN BATT_LOW_LED# 45 ENBKL RE9 1 @ 2 100K_0402_5%
1 2 RE61 1 2 0_0402_5% @ H2 N6
7 LPC_AD3 LPC_AD2_EC LAD3/GPM3 PWM3/GPA3 EC_FAN_PWM1 EC_KB_BKL_EN 45
RE62 1 2 0_0402_5% @ J1 PWM K6 EC_FAN_PWM1 39
+3VL_EC 7 LPC_AD2 LPC_AD1_EC LAD2/GPM2 PWM4/GPA4 EC_FAN_PWM
RB751V-40_SOD323-2 RE63 1 2 0_0402_5% @ J2 J6
7 LPC_AD1 1 2 LPC_AD0_EC K1 LAD1/GPM1 PWM5/GPA5 M7 EC_BEEP EC_FAN_PWM 39
@ RE64 0_0402_5% @
7 LPC_AD0 CLK_PCI_EC LAD0/GPM0 PWM6/SSCK/GPA6 EC_VCCST_EN EC_BEEP 30
K2 LPC K7
1 2 7 CLK_PCI_EC L1 LPCCLK/GPM4 PWM7/RIG1#/GPA7 C2 EC_ON_5V EC_VCCST_EN 13
WRST#
EC_SMI# WRST# TMRI0/GPC4 EC_ON_5V 54
1 L2 E1 SUSP#
RE8 9 EC_SMI# EC_RX ECSMI#/GPD4 TMRI1/GPC6 SUSP# 46
M2
100K_0402_5% CE12 40 EC_RX EC_TX M1 PWUREQ#/BBO/SMCLK2ALT/GPC7 G10
40 EC_TX PLT_RST# LPCPD#/GPE6 ADC0/GPI0 NTC_V1 39
1U_0402_6.3V6K M4 G13 NTC_V2 NTC_V2 39 For PMIC
2 11,26,37,38,40 PLT_RST# EC_SCI# N4 LPCRST#/GPD2 ADC1/GPI1 G12 BATT_TEMP
4 EC_SCI# EC_RTCRST#_ON F1 ECSCI#/GPD3 ADC2/GPI2 TYPE_C_M1 BATT_TEMP 52,53 +3VALW +3VL_EC
ADC F9
GA20/GPB5 ADC3/GPI3 F13 CPU_VR_READY TYPE_C_M1 42
IT8586VG/AX ADC4/GPI4 F10 ADP_I CPU_VR_READY 58

1
ADC5/DCD1#/GPI5 ADP_I 53
F12 RE276 1 2 0_0402_5% @ RE274
PSYS 53,58 RE273

45 KSI[0..7]
KSI[0..7] KSI0 J12
VFBGA128 ADC6/DSR1#/GPI6
ADC7/CTS1#/GPI7
E13 SYS_PWROK
SYS_PWROK 11 0_0402_5%
@
0_0402_5%
KSI1 J13 KSI0/STB# D12 EC_TS_ON @
KSI1/AFD# DAC2/TACH0B/GPJ2 EC_TP_ON EC_TS_ON 33
KSO[0..15] KSI2 J9 C13 RPE4

2
45 KSO[0..15] KSI2/INIT# DAC3/TACH1B/GPJ3 H_PROCHOT#_EC EC_TP_ON 45 EC_SMB_DA3
C KSI3 H12 DAC B13 1 4 C
KSI4 H9 KSI3/SLIN# DAC4/DCD0#/GPJ4 C12 ENBKL R14 2 1 0_0402_5% @ EC_SMB_CK3 2 3
KSI4 DAC5/RIG0#/GPJ5 PCH_ENBKL 4,33
KSI5 H10
KSI6 H13 KSI5 A11 EC_ON_GPIO RE57 1 2 0_0402_5% @ 2.2K_0404_4P2R_5%
G9 KSI6 PS2CLK0/TMB0/CEC/GPF0 B11 PBTN_OUT# EC_ON 39,54,55
KSI7
+3VL_EC KSI7 PS2DAT0/TMB1/GPF1 EC_SMB_CK3 PBTN_OUT# 11
KSO0 M8 A10
EC_SMB_CK1 1 J7 KSO0/PD0 GPF2 B10 EC_SMB_DA3 EC_SMB_CK3 55
RPE2 PAD @ KSO1 Int. K/B PS2
EC_SMB_DA1 EC_SMB_DA1 IT1 KSO1/PD1 GPF3 TAB_SW# EC_SMB_DA3 55
2 3 PAD 1 @ KSO2 N9 Matrix D9
EC_SMB_CK1 IT2 KSO2/PD2 PS2CLK2/GPF4 CHG_MOD1 TAB_SW# 43
1 4 PAD 1 @ KSO3 M9 B9
1 IT3 K8 KSO3/PD3 PS2DAT2/GPF5 CHG_MOD1 41 +3VL_EC
PAD @ KSO4
IT4 KSO4/PD4 CAPS_LED#
2.2K_0404_4P2R_5% PAD 1 @ KSO5 J8 EXTERNAL SERIAL FLASH A9 CAPS_LED# 45
IT5 N10 KSO5/PD5 GPH3/ID3 B8 PCH_PWR_EN
KSO6 PCH_PWR_EN 55
KSO7 M10 KSO6/PD6 GPH4/ID4 A8 EC_VCCST_PWRGD EC_ON RE65 2 1 100K_0402_5%
KSO7/PD7 GPH5/ID5 PCH_PWROK EC_VCCST_PWRGD 11 EC_VCCST_PWRGD OD output
KSO8 N11 B7
KSO8/ACK# GPH6/ID6 PCH_PWROK 11
KSI7 PAD 1 @ KSO9 K9 SUSP# RE18 1 @ 2 100K_0402_5%
IT6 KSO9/BUSY EC_SPI_CS0#
+3VS KSI6 PAD 1 @ KSO10 N12 A7
1 IT7 N13 KSO10/PE NC1 B6 EC_SPI_SI
RPE3 WRST# PAD @ KSO11 SUSP# RE19 1 2 100K_0402_5%
EC_SMB_CK2 IT8 KSO11/ERR# NC2 EC_SPI_SO
1 4 KSO12 M13 SPI Flash ROM A6
2 3 EC_SMB_DA2 KSO13 L12 KSO12/SLCT NC3 B5 EC_SPI_CLK SYSON RE21 1 2 100K_0402_5%
KSO14 L13 KSO13 NC4
For factory EC flash KSO14 EC_VCCST_EN
2.2K_0404_4P2R_5% KSO15 K12 RE269 1 @ 2 100K_0402_5%
EC_ID0 K13 KSO15 A4 ACIN#
EC_ID1 J10 KSO16/SMOSI/GPC3 AC_IN# A3 LID_SW# EC_VCCIO_EN RE268 1 @ 2 100K_0402_5%
KSO17/SMISO/GPC5 UART LID_SW# LID_SW# 36,43
ENBKL R16 1 2 100K_0402_5%
ON/OFF B4 A13 AOU_DET#
43 ON/OFF EC_ON PWRSW# EGAD/GPE1 VDDQ_PGOOD AOU_DET# 41
RE58 2 @ 1 0_0402_5% A2 SM Bus A12
VDDQ_PGOOD 55
EC_SMB_CK1 B3 XLP_OUT EGCS#/GPE2 B12 EC_VPP_PWREN
52,53 EC_SMB_CK1 EC_SMB_DA1 SMCLK1/GPC1 EGCLK/GPE3 EC_VPP_PWREN 55 Add to fix Reset&PWRGD test fail issue
Charger Battery B2
52,53 EC_SMB_DA1 H_PECI 2 43_0402_5% PECI_EC SMDAT1/GPC2 EC_MUTE#
4 H_PECI RE24 1 B1 GPIO D13
EC_MUTE# 30 VDDQ_PGOOD CE51 1
CHG_MOD3 SMCLK2/PECI/GPF6 GPJ1 2 0.01U_0201_10V6K
C1 E7 GPG2
41 CHG_MOD3 EC_SMB_CK2 E8 SMDAT2/PECIRQT#/GPF7 SSCE0#/GPG2 E6 BKOFF#
7,26,36,39 EC_SMB_CK2 EC_SMB_DA2 CRX1/SIN1/SMCLK3/GPH1/ID1 SSCE1#/GPG0 ME_FLASH BKOFF# 33 PM_SLP_S4#
GPU SENSOR Thermal D7 D6 CE50 1 2 EMC_NS@ 1000P_0201_50V7-K
7,26,36,39 EC_SMB_DA2 CTX1/SOUT1/SMDAT3/GPH2/ID2 DSR0#/GPG6 ME_FLASH 8
A5 SYSON
DTR1#/SBUSY/GPG1/ID7 D1 EC_RSMRST# SYSON 55
+3VL CRX0/GPC0 EC_RSMRST# 11 PM_SLP_S3# CE21 1 2 EMC_NS@ 1000P_0201_50V7-K
D2 EC_VCCIO_EN
CTX0/TMA0/GPB2 PM_SLP_S3# EC_VCCIO_EN 13
RE27 1 2 0_0402_5% @ A1 N1
VSTBY0 RI1#/GPD0 PM_SLP_S4# PM_SLP_S3# 11
RE272 1 2 0_0402_5% @ E2 N3 PM_SLP_S4# 11 SYSON CE13 1 2 EMC_NS@ 1000P_0201_50V7-K
B 58 EC_VR_ON GPE4 RI2#/GPD1 B
WAKE UP E12 NOVO# NOVO# 43
+5VALW TACH2/GPJ0 M12 EC_FAN_SPEED1
TACH1A/TMA1/GPD7 EC_FAN_SPEED EC_FAN_SPEED1 39 NOVO# CE48 1 2 EMC_NS@ 0.01U_0201_10V6K
M11 EC_FAN_SPEED 39
USB_ON# N7 TACH0A/GPD6 M3 EC_SMB_DA4
RE15 2 1 100K_0402_5% USB_ON# 43 USB_ON# GINT/CTS0#/GPD5 L80LLAT/GPE7 EC_SMB_DA4 8
USB_CHG_EN N8 N2 EC_SMB_CK4 PECI_EC CE15 1 2 EMC_NS@ 47P_0201_25V8-J
41 USB_CHG_EN TYPE_C_M0 RTS1#/GPE5 GPIO L80HLAT/BAO/GPE0 EC_SMB_CK4 8
D8
+3VL 42 TYPE_C_M0 CLKRUN#/GPH0/ID0
BATT_TEMP CE16 1 2 EMC_NS@ 100P_0201_25V8J
RE5 2 1 0_0402_5% @ BATT_CHG_LED# 45
RE36 1 @ 2 10K_0402_5% BKOFF# VGA_AC_DET G1
26 VGA_AC_DET AC_PRESENT CK32KE/GPJ7
F2 Clock ACIN# CE17 1 2 EMC_NS@ 100P_0201_25V8J
11 AC_PRESENT CK32K/GPJ6
RE38 2 1 100K_0402_5% LID_SW#
YOGA@ ON/OFF CE18 1 2 @ 1U_0402_6.3V6K
RE278 2 1 100K_0402_5% TAB_SW#
PLT_RST# CE1 1 2 EMC@ 220P_0201_25V7-K
RE40 1 2 10K_0402_5% BKOFF#
AVSS
VSS1

VSS2
VSS3
VSS4
VSS5
VSS6

For ESD
IT8586VG-FX_VFBGA128 EMC Request
E10
E5

H5
F4
F5
G4
G5

EC_SPI_CS0# RE45 2 1 0_0402_5% @ SPI_CS0#

SPI_CS0# 7 For EMI
EC_AGND
EC_SPI_SI RE47 2 1 0_0402_5% @ SPI_SI CLK_PCI_EC RE2 1 EMC@ 2 33_0402_5%
SPI_SI 7 RE34 1 2 0_0402_5% @ H_PROCHOT# 4,55
53,58 VR_HOT#
1

1
EC_SPI_SO RE48 2 1 0_0402_5% @ SPI_SO CE2
SPI_SO 7 1 22P_0402_50V8-J
RE267
CE14
+3VL EMC@
EC_SPI_CLK 100_0402_5% 47P_0201_25V8-J
RE49 2 1 0_0402_5% @ SPI_CLK 2
SPI_CLK 7 EMC_NS@
2

2
2

EC_RTC_RST# 10

1
QE1 D
1

RE42 QE3 D H_PROCHOT#_EC

EC_RTCRST#_ON 2
A 100K_0402_5% 2 A
2N7002KW_SOT323-3 G
G 2N7002KW_SOT323-3
1

+3VL_EC @
1

ACIN# RE262 1 2 0_0402_5% @ S

RE50

3
S
3

RE44 1 2 10K_0402_5% GPG2 100K_0402_5%

@
1

D QE2
RE46 1 @ 2 10K_0402_5% GPG2
2
2

G ACIN 53

S 2N7002KW_SOT323-3
3

@ Security Classification LC Future Center Secret Data Title

when mirror, GPG2 pull high
when no mirror, GPG2 pull low Issued Date 2015/08/20 Deciphered Date 2016/08/20 EC_ITE8586VFBGA
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EYG10_ES430_ES530
Date: Tuesday, January 09, 2018 Sheet 44 of 60
5 4 3 2 1
 5 4 3 2 1

D D

K/B Connector KSI[0..7]

KSI[0..7] 44 ME@
KB Backlight Connector +5VS +5VALW
KSO[0..15] HIGHS_FC8AF321-3201H
KSO[0..15] 44 Q31
+5VS +VCC_KB_LED
KSO12 1

1
2 1 LP2301ALT1G_SOT23-3
KSI2
3 2 R24 R265 3 1 BL@

D
4 3 10K_0402_5% 10K_0402_5%
5 4 @ BL@

10U_0603_6.3V6M

0.1u_0201_10V6K
6 5 1 1

C1106

C1107
6 R266

BL@
KSI1 7 R31

2
7 1 2 1 2
KSI7 8

0.01U_0201_10V6K
KSI6 9 8 0_0402_5% 30K_0402_1%
9 2 2
KSO9 10 @ 1
BL@

C1108
10

BL@
PWR_CAPS_LED KSI4 11
EMC_NS@ 100P_0201_25V8J 2 1 C133 11

1
KSI5 12 D
13 12 EC_KB_BKL_EN 1 R60 2 2
KSO0 2
14 13 44 EC_KB_BKL_EN
CAPS_LED# KSI2 G
EMC@ 100P_0201_25V8J 2 1 C117 14 0_0402_5%
KSI3 15 Q32
16 15 @
KSO5 1 S 2N7002KW_SOT323-3

3
C
KSO1 17 16 C1109 BL@
C

KSI0 18 17 0.1u_0201_10V6K
CAPS_LED# KSO2 19 18 BL@
KSO4 20 19 2
KSO7 21 20
21
1

KSO8 22
D22 KSO6 23 22
1

AZ5123-01F.R7GR_DFN1006P2X2 KSO3 24 23 +VCC_KB_LED

EMC@ KSO12 25 24
26 25 JKBL1 JKBL2
KSO13
KSO14 27 26 +VCC_KB_LED 6 6
27 GND2 GND2
2

KSO11 28 5 5
KSO10 29 28 GND1 GND1
2

KSO15 30 29 4 4
For EMC CAPS_LED# CAPS_LED#_R 30 4 4
R275 1 2 0_0402_5% @ 31 34 3 3
44 CAPS_LED# PWR_CAPS_LED 31 GND2 3 3
R84 1 2 200_0402_1% 32 33 1 2 2
+3VALW 32 GND1 C1110 1 2 1 2
0.1u_0201_10V6K 1 1
JKB1 @
2 HIGHS_FC1AF041-1201H HIGHS_FC1AF041-1201H
Change Symbol to SP01001YC00 Bourne 0629 ME@ ME@

FP_PWR
Finger Print Connector
+3VS TP/B Connector
+3VS TP_PWR
R3120 1 2 0_0402_5% @
1 C2061 R141 1 2 0_0402_5% @ ME@
FP_PWR
0.1u_0201_10V6K HIGHS_FC5AF081-2931H

0.1u_0201_10V6K
FP@ 2 0_0402_5% @ EC_TP_ON_R
2 JFP1 1 R4675 1 1
44 EC_TP_ON 2 0_0402_5% @ TP_INT# 1

C114
1 R4676 1 2
R3122 1 2 0_0402_5% @ USB20_N4_CONN 1 8 PCH_TP_INT# 2
2 3
USB20_P4_CONN 3 2 4 3
L4211 4 3 2 5 4
USB20_N4 4 3 USB20_N4_CONN
5 4 TP_I2C_SDA0 6 5
9 USB20_N4 4 3
5 8 TP_I2C_SDA0 TP_I2C_SCL0 6
6 7
7 6 8 TP_I2C_SCL0 8 7
USB20_P4 USB20_P4_CONN

100P_0201_25V8J
1 2 7 TP_PWR 8

100P_0201_25V8J
9 USB20_P4 1 2 8
8 1 1

EMC_NS@

EMC_NS@
9
EXC24CH900U_4P GND1

C115

C116
9 10
EMC_NS@ 10 GND1 TP_I2C_SCL0 GND2
USB20_N4_CONN
GND2 TP_I2C_SDA0
B R3121 1 2 0_0402_5% @ 2 2 JTP1 B
HIGHS_FC5AF081-2931H

2
USB20_P4_CONN ME@
DT1
Change Symbol to SP01001WX00 Bourne 0629
AZ5425-01F.R7GR DFN1006P2E

EMC_NS@
1

1
AZ5425-01F.R7GR DFN1006P2E

EMC_FP@
1

1
EMC_FP@

D4316
D4315

AZC199-02S.R7G_SOT23-3
2

1
For EMC

PWM PWM
LED2 LED4
R4672
BATT_LOW_LED# 1 2 R143 1 2 150_0402_5% PWR_LED_WIT# 1 2 1 2
44 BATT_LOW_LED# +3VALW 43,44 PWR_LED_WIT# +3VALW
470_0402_5%
L-C192JFCT-LCFC_SUPER_AMBER
1

L-C192WDT-LCFC_WHITE
1

530S@
530S@
1

LED Stute LED Behavior

1

D1
D18
AZ5123-01F.R7GR_DFN1006P2X2 White_on(battery：21%~100%)
AZ5123-01F.R7GR_DFN1006P2X2
EMC_NS@ System on
EMC_NS@ Amber_on(battery：0%~20%)
2

White_on(battery：21%~100%)
2

Power Button Standby

LID closed
2

Amber_Blink_3S(battery：0%~20%)
2

System off OFF

GPIO PWM Battery only OFF

LED3 Charging Amber_on(battery：1%~90%)
LED1
BATT_CHG_LED# 1 2 R4683 Charging
44 BATT_CHG_LED# R144 1 2 1.5K_0402_5% +5VALW PWR_LED_ABR# 1 2 1 2 White_on(battery：91%~100%)
43,44 PWR_LED_ABR# +3VALW
A L-C192WDT-LCFC_WHITE 470_0402_5% A
L-C192JFCT-LCFC_SUPER_AMBER
1

530S@
1

530S@
1
1

D19
D2
AZ5725-01F.R7GR_DFN1006P2X2
AZ5123-01F.R7GR_DFN1006P2X2
EMC_NS@
EMC_NS@
2
2

2
2

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 KB/FP/TP_CONN.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Re v
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EYG10_ES430_ES530
Date: Tuesday, January 09, 2018 Sheet 45 of 60
5 4 3 2 1
 A B C D E

Load Switch +3VS, C173 --> 2.74ms

+5VALW To +5VS +5VS, C176 --> 2.03ms
+3VALW To +3VS VIN 5V and 3.3V (VBIAS=5V), IMAX(per channel)=6A, Rds=16mohm
+5VALW U13
R64 1 2 0_0402_5% @ 3VSON 15 Need Short
GPAD +5VS
1 7 8 J12 @ 1
IN2_2 OUT2_1 +5VS_LS

1U_0402_6.3V6K
6 9 1 2
1 IN2_1 OUT2_2 1 2

C177
5VSON 5 10 C176 1 2 1000P_0201_50V7-K JUMP_43X79 1
SUSP# R27 1 2 0_0402_5% @ 5VSON EN2 CT2 C174
2 4 11 0.1u_0201_10V6K
+5VALW VBIAS GND @
+3VALW 3VSON 3 12 C173 1 2 2200P_0402_25V7-K 2 +3VS
1 1 EN1 CT1 J11 @
C180 C179 2 13 +3VS_LS 1 2
1U_0402_6.3V6K 1U_0402_6.3V6K 1 IN1_2 OUT1_1 14 1 2

1U_0402_6.3V6K
2 2 IN1_1 OUT1_2 JUMP_43X79
1 1
AP22966DC8-7 V-DFN3020 14P C175

C178
@ Need Short 0.1u_0201_10V6K
@
2 2

+3VALW Need short +3VALW_PCH

2 +1.8VALW Q35 2
+1.8VS
J7 @ LP2301ALT1G_SOT23-3
1 2 Id=3.2A 0.6A
1 2

D
3 1

0.1u_0201_10V6K
JUMP_43X79

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K
1 1 1 1

C203
2
C201

C204

C205
2 2 2 2
SUSP R201 1 2 0_0402_5% @

0.1u_0201_10V6K
1

470K_0402_5%
1

R202

C202
@

2
3 3

+5VLP +5VALW
For DisCharge
1

R156 R157 +0.6VS +2.5V_DDR

100K_0402_5% 100K_0402_5%
@ 1

1
2

R159 R278
SUSP 47_0603_5% 200_0402_5%
34 SUSP
@ @
2

2
1

1
Q10 D D Q11 D Q33
2 2 SUSP 2 SUSP
44 SUSP# G G G

S 2N7002KW_SOT323-3 S 2N7002KW_SOT323-3 S 2N7002KW_SOT323-3

3

3
@ @

4 4
08/29: Need double check enable signal and the resistance

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20
DC V TO VS INTERFACE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EYG10_ES430_ES530
Date: Tuesday, January 09, 2018 Sheet 46 of 60
A B C D E
 5 4 3 2 1

B2 A2
D
+3VLP PCH_PWR_EN# 2 D

Q25,+3V_PCH

V
V
AC A1
MODE VIN

V V
A2 A4 B5
3 +3V_PCH

V
PU301 PU904

V
B+
+3VALW
BATT BATT V 1
DPWROK_EC
V
MODE

V V V
B1
4
PCH_RSMRST#
EC 14
PM_DRAM_PWRGD
5 PBTN_OUT#

V
EC_ON PM_SLP_S3# PCH 15
PM_SLP_S4# H_CPUPWRGD CPU

V V
A3 B4 PM_SLP_S5#
PM_SLP_SUS# 6

V
CPU_PLTRST# 16
12
PCH_PWROK

V V
C C

B3 13
SYS_PWROK

V
ON/OFF V
NOVO

NVDD_PWR_EN
(DIS)
Vb
+VGA_CORE

V
11 VR_REDY SYSON 7 +1.35V
PU801
PU501

V
DGPU_PWROK
DGPU_PWR_EN
10 Va (DIS)

V
PU901 VR_ON +1.5VS_VGA

V
Q31
V

PU601

V
+CPU_CORE
+5VS

B B

V
Q32 +1.05VSP_VGA

V
SUSP#,SUSP 9 +3VS PU702

V
VGA

V
PU602
+1.5VS +3VS_VGA

V
Q27

V
PU502
+0.675V
8
SUS_VCCP PU701
V
+1.05VS

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 Power sequence block
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EYG10_ES430_ES530
Date: Tuesday, January 09, 2018 Sheet 47 of 60
5 4 3 2 1
 5 4 3 2 1

SH1 SH2 SH3

Hole
PCB Fedical Mark PAD 1 1 1
1 1 1
H1 H2 H4
HOLEA HOLEA HOLEA
FD1 FD2 FD3 FD4 FD5 FD6
SHIELDING_SUL-15A3M_6X1P2_1P SHIELDING_SUL-15A3M_6X1P2_1P SHIELDING_SUL-15A3M_6X1P2_1P
D D
ME@ ME@ ME@
1

1
SH5 SH6
SH4
PAD_D2P5 pad_c3p5d2p5 pad_c5p0d4p0
1 1
1 1 1
1
H5 H6 H7 H8
HOLEA HOLEA HOLEA HOLEA
SHIELDING_SUL-15A3M_6X1P2_1P SHIELDING_SUL-15A3M_6X1P2_1P
SHIELDING_SUL-15A3M_6X1P2_1P
ME@ ME@
ME@
1

1
SH7
PAD_O2P5X2P8D2P5X2P8N
PAD_CT7P0B6P0D3P4 pad_ct6p0b5p0d2p5 pad_c2p5d2p5n
1
1
H9 H10 H11 H12
HOLEA HOLEA HOLEA HOLEA
SHIELDING_SUL-15A3M_6X1P2_1P
ME@ SSD1 Shielding
1

C C

pad_c2p5d2p5n pad_ct6p0d3p5 pad_ct6p0d3p5 pad_ct6p0d3p5

H13 H14 H15 H16

HOLEA HOLEA HOLEA HOLEA
SH9 SH10 SH12

1 1 1
1

1 1 1

pad_ct6p0d3p5 PAD_C7P0D3P3 PAD_C7P0D3P3 PAD_C7P0D3P3

SHIELDING_SUL-15A3M_6X1P2_1P SHIELDING_SUL-15A3M_6X1P2_1P SHIELDING_SUL-15A3M_6X1P2_1P
H18 H19 H20 H21 ME@ ME@ ME@
HOLEA HOLEA HOLEA HOLEA
SH11 SH13 SH14
1

1 1 1
1 1 1
B B
PAD_C7P0D3P3 PAD_C7P0D3P3 PAD_C7P0D3P3 PAD_C7P0D3P3

SHIELDING_SUL-15A3M_6X1P2_1P SHIELDING_SUL-15A3M_6X1P2_1P SHIELDING_SUL-15A3M_6X1P2_1P

H23 H25 ME@ ME@ ME@
H22
HOLEA HOLEA
HOLEA
SH15
SH8

1
1

1
1

1
pad_o6p0x8p5d6p0x8p5n PAD_O6P5X3P5D6P5X3P5N 1
pad_o2p2x2p5d2p2x2p5n

SHIELDING_SUL-15A3M_6X1P2_1P
SHIELDING_SUL-15A3M_6X1P2_1P
ME@
ME@

DDR Shielding

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 Hole
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EYG10_ES430_ES530
Date: Tuesday, January 09, 2018 Sheet 49 of 60
5 4 3 2 1
 5 4 3 2 1

D D

V20B+ Silergy +5VLP/ 100mA

SY8180C
+5VALW/8A
Converter
Adaptor 65W EN
FOR SYSTEM PGOOD
+1.05VGS/2.1A

+3VLP/ 100mA
Silergy
SY8286B +1.0VALW/6A
+3VALW/ 5.5A
Converter
EN
FOR SYSTEM PGOOD

+1.8VALW/1A

C C

TI Richtek +1.35V/8A Silergy +2.5V/1A

BQ24780SRUYR LV5095A LV5028AGQV

Battery Charger EN Switch Mode SYS PMIC
Switch Mode FOR VRAM PGOOD
+1.2V/6A

Richtek +0.6VS/2A

SMBus RT8812AGQW For N16 +VGA_CORE/30A

RT8816AGQW For N17
EN Switch Mode
PGOOD
FOR GPU VDDC

B B
Battery IA Core/42A
Onsemi
polymer NCP81218MNTXG VCCGT/18A

3S1P/2S2P Switch Mode VCCSA/4A

EN FOR CPU Core
PGOOD

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 PWR-Power Diagram

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EYG10_ES430_ES530
Date: Tuesday, January 09, 2018 Sheet 50 of 60
5 4 3 2 1
 5 4 3 2 1

VIN
3.25A HCB2012KF-121T50_0805
JDCIN1 PF101 PL101
1 ADPIN 1 2 APDIN_F 1 2
1 2
GND1 EMC@
3 7A_24VDC_F1206HI7000V024TM
GND2

1000P_0201_50V7-K
470P_0201_50V7-K
4
GND3

1000P_0201_50V7-K

470P_0201_50V7-K
5 HCB2012KF-121T50_0805
GND4

EMC@

EMC@
PC101

PC102
6 PL102
GND5

2
EMC@

EMC@
PC103

PC104
D 7 1 2 D
GND6
EMC_NS@
HIGHS_PJSS0026-8B01H

1
ME@

+3VL

1
PR102
1.5K_0402_1%

VCCRTC 2
1

PR103
C C
45.3K_0402_1%
RTC_VCC
2

3 2 PR101 1

PD101 1K_0603_5%
2

BAT54CW_SOT323-3
PC105
1U_0402_6.3V6K
1

RTC_VCC 20MIL
+3VL 20MIL
VCCRTC 20MIL

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 PWR-DCIN / RTC charger
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EYG10
Date: Tuesday, January 09, 2018 Sheet 51 of 60
5 4 3 2 1
 5 4 3 2 1

VBAT EMC@
D JBATT1
10A HCB2012KF-121T50_0805
BATT+ D
1 PL201
1 2 1 2
9 2 3 EC_SMCA PR202 1 2 100_0402_1%
10 GND1 3 4 EC_SMDA 1 2
EC_SMB_CK1
EC_SMB_DA1
44,53
44,53
1 2 2S1P polymer battery
GND2 4 5
5 6
PR201 100_0402_1%
PL202
voltage level: +5.5V ~
6
7
7 HCB2012KF-121T50_0805 8.8 V

2
8 EMC@
8

SUYIN_125022HB008M202ZL

1
PC201 PC202
ME@ RTC_VCC 1000P_0201_50V7-K 0.01U_0201_25V6-K
EMC@ EMC@

2
PD201
AZC199-02S.R7G_SOT23-3

1
EMC_NS@

PR209
1 2
+3VALW
100K_0402_1%

PR213
C 1 2 C
BATT_TEMP 44,53
10K_0402_5%
1
1

PD202
AZ5215-01F_DFN1006P2E2
EMC_NS@
2
2

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 PWR-BATTERY CONN/OTP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EYG10
Date: Tuesday, January 09, 2018 Sheet 52 of 60
5 4 3 2 1
 5 4 3 2 1

VIN PQ311
AON6414AL_DFN8-5 PQ312
AON7408L_DFN8-5 N2
N1 PR301
1 1 PJ301 @ 0.01_1206_1%
2 2 JUMP_43X118 V20B+
5 3 3 5 1 2 1 4
1 2
2 3
D D

10U_0603_25V6-M

10U_0603_25V6-M

220P_0402_50V7K

470P_0402_50V7K

680P_0402_50V7K
470P_0201_50V7-K

4700P_0402_50V7-K

6800P_0402_25V7-K
0.022U_0402_25V7K

0.01U_0201_25V6-K
4

EMC_NS@

EMC_NS@
PC301

1
EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@
PC303

PC304

PC329

PC330

PC331

PC332

PC333

PC334
1

PC302
PR302

2
4.7_0603_5%

5
0.1U_0201_25V6-K

2
PQ314
PC305
AON6324_DFN8-5
1 2
BQ24780_BATDRV PR345
1 2BQ24780_BATDRV_R 4

2
09/09 NC MEC part
0_0603_5%
PC037 PC306
0.1U_0201_25V6-K 0.1U_0201_25V6-K

3
2
1
2
PR303
499K_0402_1% PC308
0.01U_0201_25V6-K

1
VIN BATT+

2
BAT54CW_SOT323-3
PD301
2

3
V20B+

4.02K_0603_1%
VIN

1
1

1
4.02K_0603_1%

0.1U_0201_25V6-K
ACN

EMC_NS@
ACP
PR310

PR311

10U_0805_25V6-K

10U_0805_25V6-K
1

1
PC310
2

PC313

PC314
PR314

1
10_0805_5% BQ24780_VDD
2

2
2

5
C PR313 PU301 C
0.47U_0603_25V6-K
7.15K_0402_1% 44.2K_0402_1%

ACN

D
ACP
PC315

AON7506_DFN8-5
1 2

1
PR315 2 1 780_VCC 28 24 1 2

2
VCC REGN 2.2U_0603_10V6-K PC316

PQ316
1 2 ACDET 6 4
PC309 ACDET PR316 PC318 G
0.01U_0402_25V7K 25 BST_CHG 1 2 2 1

S3
S2
S1
BTST PR317
2.2_0603_5% 0.047U_0603_16V7K PL302 0.01_1206_1% 6A

3
2
1
3
CMSRC HIDRV
26 DH_CHG 2.2UH_PCME063T-2R2MS_10A_20% BATT+
@ 1 2 CHG 1 4

5
PR339 2 1 20K_0402_1% 4
ACDRV

1
@ 2 3

AON7506_DFN8-5
PR324 2 1100K_0402_1% 27 LX_CHG PR321
BQ24780_VDD PHASE
@ 2.2_0805_5%

10U_0805_25V6-K

10U_0805_25V6-K

10U_0805_25V6-K

10U_0805_25V6-K
1

1
PR325 1 2 0_0402_5% ACIN_R 5

PQ317

PC340

PC342
44 ACIN ACOK EMC_NS@
@ 4

PC319

PC320
2
PR320 1 2 0_0402_5% EC_SMB_DA1_R 11 G

2
44,52 EC_SMB_DA1 SDA 23 DL_CHG

S3
S2
S1
470P_0201_25V7K
LODRV

1
@

2
PR322 1 2 0_0402_5% EC_SMB_CK1_R 12 22 PC321

PC345

3
2
1
44,52 EC_SMB_CK1 SCL GND 1000P_0402_50V7K

2
@ BQ24780SRUYR_QFN28_4X4 EMC_NS@

1
PR323 1 2 0_0402_5% ADP_I_R 7 29 @

0.1U_0201_25V6-K

0.1U_0201_25V6-K
44 ADP_I IADP PAD

2
IDCHG 8 18 BQ24780_BATDRV

PC322

PC323
IDCHG BATDRV
9 PR338 10_0603_5%

1
44,58 Psys PMON 17 2 1
BATSRC
100P_0201_25V8J

100P_0201_25V8J
2

20 SRP_R 2 1 SRP
20K_0402_1%

100P_0201_25V8J

0.1U_0201_25V6-K
SRP
2

10 PR328 10_0603_5%
44,58 VR_HOT#
PC324

PROCHOT#

2
PC325

PR340

PC341

PC327
1

13
CMPIN
1

1
BATPRES#
TB_STAT#
@ 14
1

CMPOUT 19 SRN_R 2 1 SRN

B
ILIM 21 SRN PR329 10_0603_5% B
ILIM
2

16

15
PR330
@ 0_0402_5%
09/19 PR331 change from 147K to 133K
PR331 PR332
1

1 2 ILIM_R 1 2 TB_STAT#
+3VALW BATT_TEMP 44,52
30K_0402_1%
133K_0402_1%
0.01U_0201_25V6-K

1
2

PC328

PR333
100K_0402_1%
1

ACDECT setting 17.2V

Charge current limit HW=7A
DC discharge limit =26A
Discharge current limit HW=9A during Turbo boost

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 PWR-CHARGER

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EYG10
Date: Tuesday, January 09, 2018 Sheet 53 of 60
5 4 3 2 1
 5 4 3 2 1

+3VALW

2
PR407
100K_0402_5%
@
V20B+ Pull high by +3VL Use for EE Bourne.gong

1
PJ401 @ PU401
2 1 +3V_VIN 5 9 +3V_PWRGD
2 1 4 IN1 PG 1 1 2 +3V_PWRGD 11
+3VBS

10U_0805_25V6-K

10U_0805_25V6-K
0.01U_0201_25V6-K
3 IN2 BS

1
PC403
2 IN3 +3VALW

SY8286BRAC_QFN20_3X3
JUMP_43X79

PC401

PC402

PC452
0.1U_0603_25V7-M
IN4 6 2.2UH_PCMB063T-2R2MS_8A_20% @

2
7 LX1 19 PL401 PJ402
8 GND1 LX2 20 +3VLX 1 2 +3VALW_P 2 1
6A
GND2 LX3 2 1

EMC@
18

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
D
21 GND3 D
GND4

1
JUMP_43X79
EC_ON PR415 2 1 0_0402_5% 12 14 +3VALW_P PR403

PC434

PC432

PC431

PC435
39,44,55 EC_ON +3V_VIN 11 EN1 OUT 2.2_0805_5%
Vout=3.3V± 5%

2
@ EN2 13 +3VALW_FB
FF
EMC_NS@
10
Vset=3.37V± 1.5%

2
1
15 NC1

1M_0402_5%
NC2 100mA +3VLP

1
16 17

PR416

1M_0402_5%
OCP=12A

0.1U_0201_25V6-K
NC3 LDO

1
PR401
1
PC410

PC408
OVP=(1.15~1.25)*Vout

4.7U_0603_6.3V6K
1
1000P_0402_50V7K

2
EMC_NS@

PC409
UVP=(0.55~0.65)*Vout

2
@ Fsw=600Khz

PC411
PR405
1 2 1 2

1K_0402_1%
1000P_0201_25V7K
+3VLP +3VL
PJ404 @
2 1
2 1

JUMP_43X39

C C

+3VALW

2
PR406
100K_0402_5%
@
Pull high by +3VL Use for EE Bourne.gong
V20B+

1
@
PJ405 PU402
2 1 +5V_VIN 5 9 ALW_PWRGD PC415
2 1 4 IN1 PG 1 +5VBS 1 2
ALW_PWRGD 11,55 8A
+5VALW
10U_0805_25V6-K

10U_0805_25V6-K
0.01U_0201_25V6-K
1

3 IN2 BS PL402
JUMP_43X79 2 IN3 0.1U_0603_25V7-M 2.2UH +-20% PCMB064T-2R2MS 9A PJ406 @
EMC@ PC412

PC413

PC414

IN4 6 +5VLX 1 2 +5VALW_P 2 1

2

7 LX1 19 2 1

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
8 GND1 LX2 20

150U_B2_6.3VM_R35M
JUMP_43X118
GND2 LX3

1
18

PC4092
21 GND3 PR410 @ 0_0402_5% 1

PC419

PC420

PC425

PC426
GND4

1
14 +5VALW_OUT 1 2 +5VALW_P
+ Vout=5V± 3%

2
EC_ON_5V 1 2 +5VALW_EN 12 OUT PR411
44 EC_ON_5V +5V_VIN EN1 2.2_0805_5%
11 13
PR414 @ 0_0402_5% EN2 FF
EMC_NS@ 2
@ @ @ @ Vset=5.1V± 1.5%
15
+5VLP OCP=12A

2
10 LDO
16 NC1 17 +5VVCC
100mA OVP=(1.15~1.25)*Vout

4.7U_0603_6.3V6K
NC2 VCC 11/06 NC to add, debug EE noise issue.

1
1M_0402_5%

1U_0603_25V6M
0.1U_0201_25V6-K

1
SY8180CRAC_QFN20_3X3 PC423

PC422
UVP=(0.55~0.65)*Vout
1

1000P_0402_50V7K
PC421

PR412

2
PC416
EMC_NS@ Fsw=600Khz

2
2

@
2

B PC424 B
PR413
+5VFB 1 2 1 2

1K_0402_1%
1000P_0201_25V7K

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 PWR_3VALW/5VALW

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EYG10
Date: Tuesday, January 09, 2018 Sheet 54 of 60
5 4 3 2 1
 5 4 3 2 1

@
PR521 1 2 0_0402_5%
EC_ON 39,44,54

D
PMIC_VCC 1 2 D
PR522 @ 0_0402_5%
ALW_PWRGD 11,54
+5VALW
+5VLP PR502 @
1 2
10_0603_5%
@ PR520
VDDQ_EN

PMIC_EN
PR501 1 2 0_0402_5% 1 2
44 SYSON 10_0603_5%
@ PC500
VTT_EN
PR503 1 2 0_0402_5% 1 2
5 CPU_DRAMPG_CNTL PR505
VDDQ_P 1 2
@ 2.2U_0603_6.3V6K
+1.8VALW_L_EN
PR507 1 2 0_0402_5%

VSYS_PMIC
10_0402_5%

1
@
+1.0VALW_EN PC502
PR506 1 2 0_0402_5% +3VALW
44 PCH_PWR_EN 0.1U_0201_25V6-K

2
@
+2.5V_DDR_EN
PR508 1 2 0_0402_5%
44 EC_VPP_PWREN

28

27

41
PU500

100K_0402_5%
0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

VSYS

VCC

PMIC_EN

GND
@
+2.5V_DDR_EN PMIC_SMB_DAT1

1
29 25 PR510 1 2 0_0402_5%

PC504

PC506

PC505

PC503

PC508

PR513
R_0402
EN_LDO1 SDA EC_SMB_DA3 44
@
+1.8VALW_L_EN 1 26 PMIC_SMB_CLK1
PR511 1 2 0_0402_5%
EC_SMB_CK3 44

1
EN_LDO2 SCL
+1.0VALW_EN 11 24 PMIC_ALERT# 2 1
@ @ @ @ @ PR512 @ 0_0402_5% H_PROCHOT# 4,44

2
EN_V1P0A OT
+1.05VGS_B_EN 16 22 +1.0VALW_PG 1 PAD @ PTC501
EN_V1P8A PG_V1P0A
VDDQ_EN +1.05VGS_B_PG VDDQ_PGOOD 44
PR524 31 21 1 PAD @ PTC502
0_0402_5% EN_VDDQ PG_V1P8A
PXS_PWREN 2 1 +1.05VGS_B_EN VTT_EN 36 23 VDDQ_PGOOD
8,23 PXS_PWREN EN_VTT PG_VDDQ PL500
OPTN17_NS@
+5VALW 1UH_PCMB063T-1R0MS_12A_20% PJ501 @

0.1U_0402_25V6
12 LX_1P0 1 2 +1.0VALW_FB 2 1

UMAorN17@
PJ500 @

1M_0402_5%
6A

22U_0603_6.3V6-M
+1.0VALW_B_VIN LX_V1P0A1 2 1
+1.0VALW

1
2 1 7 13

PC537

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
2 1 VIN_V1P0A1 LX_V1P0A2

LV5028RPC_QFN40_5X5
@
8 14 if need to change to R33 choke JUMP_43X118

PR519
VIN_V1P0A2 LX_V1P0A3

1
15
PR525

2
JUMP_43X39 PC510 LX_V1P0A4

PC509

PC511

PC512

PC513

PC514

PC515

PC516
1 2 +1.0VALW_FB
23,56 PXE_VDD_EN_R 0.1u_0201_10V6K 10

2
0_0402_5% VO_V1P0A 11/16 For N16 need to CLOSE
EMC_NS@
OPTN16@ PJ508 @ @ @
+1.05VGS_B_VIN PL502
2 1 17 PJ509
+5VALW 2 1 19 LX_V1P8A1 18 LX_1P05 1 2 +1.05VGS_FB 2 1
VIN_V1P8A LX_V1P8A2 2 1 +1.0VGS N16 GPU +1.05VGS setting to 1.05V, 2.1A

1
09/08 reserve one pull down PC534 1UH_PH041H-1R0MS_3.8A_20%

22U_0603_6.3V6-M

22U_0603_6.3V6-M
11/16 For N16 need to CLOSE JUMP_43X39 20 +1.05VGS_FB
22U_0603_6.3V6-M JUMP_43X79 11/16 For N17 need to open
OPTN16_NS@ VO_V1P8A OPTN16@

1
OPTN16@

PC535

PC536
2
C PJ512 C
UG_VDDQ OPTN17_NS@
33 2 1
+1.2V_P +3.3V_1.8V_AON 1A

2
PC529 1 2 10U_0603_10V6K 38 UGATE_VDDQ PR1031 PC518 2 1
VIN_VTT BST_VDDQ

OPTN16@

OPTN16@
32 1 2 2 1 JUMP_43X79
PJ504 BS_VDDQ
@ 0_0603_SM
2 1 39 0.1U_0603_25V7-M

LX_1P05
1A +0.6VS 2 1 VTT LX_VDDQ @

LX_1P0
34
LX_VDDQ N17 GPU PJ512 tinplate

1
PC519
JUMP_43X39 40 35 LG_VDDQ
22U_0603_6.3V6-M VSNS_VTT LGATE_VDDQ N16 GPU PJ509 tinplate

2
+1.2V_P

1
PR515 @ 37
1 2 30 VSNS_VDDQ PR1029 PR1030
33K_0402_1% CS_VDDQ 4.7_0603_5% 4.7_0603_5%

PJ502 PJ503
1A EMC_NS@ EMC_OPTNS@ 14" N17S-G1 1.8VGS 0.3A
@ @

2
2 1 +2.5V_DDR_VIN 5 6 +2.5V_P 2 1
+3VALW 2 1 VIN_LDO1 LDO1 2 1 +2.5V_DDR 15" N17P-G0 1.8VGS 1.6A
PC521

1
1 2
JUMP_43X39 1 2 JUMP_43X39 PC1109 PC1110
PC520 22U_0603_6.3V6-M 1200P_0402_50V7-K 1200P_0402_50V7-K
1A

2
PJ511 @ EMC_NS@ EMC_OPTNS@
10U_0603_10V6K 3 +1.8VALW_L_P 2 1
4 LDO2 2 1 +1.8VALW
VIN_LDO2 2

22U_0603_6.3V6-M
FB_LDO2 JUMP_43X39

2
110K_0402_1%

1
PR516
PJ510

PC522
@
2 1 +1.8VALW_L_VIN V20B+

+1.8VALW_L_FB
+3VALW

2
2 1

1
JUMP_43X39

1
PC523 PJ506 @
VDDQ_P 2 1
10U_0603_10V6K

2
2 1

0.1U_0201_25V6-K
5
JUMP_43X79

10U_0805_25V6-K

10U_0805_25V6-K
PC524
1

1
PC525

PC526
09/08 PR516 change from 105K to 110k

2
PQ500
UG_VDDQ

2
EMC_NS@
PR517 4
75K_0402_1% AON7408L_DFN8-5

+1.2V

1
PL501
6A

3
2
1
0.47UH_MAPM0530F-R47M10-LF_13A_20% PJ507
LX_VDDQ 1 2 +1.2V_P 2 1
2 1
JUMP_43X118

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
5

2
AON7506_DFN
@

1
B 4.7_0603_5% B
PR518

PC527

PC528

PC517

PC530
PC1113
PQ501

2
LG_VDDQ EMC_NS@

1
4
@

1
PC533
1200P_0402_50V7-K

3
2
1

2
EMC_NS@ 11/06 PL501 placement clash

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 PWR PMIC-DDR4/1.0ALW/1.8ALW
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS D 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EYG10
Date: Tuesday, January 09, 2018 Sheet 55 of 60
5 4 3 2 1
 A B C D

V20B+
1.5A PJ3601 @
2 1 PC3603
2 1

10U_0805_25V6-K

10U_0805_25V6-K
PR3601 0.1U_0603_25V7-M
JUMP_43X79 +1.35V_BST 1 2+1.35V_BST_R 1 2

1
OPT@ PC3601

OPT@ PC3602
10_0603_5% 09/09 PL3601 from 0.47uH to 0.68uH
OPT@
OPT@ +1.35VGS

2
PD3601
OPT@

18
1 2

5
PU3601 PL3601
0.68UH_PCMB053T-R68MS_8.5A_20% PJ3602 8A

VBOOT
AGND
RB751V-40_SOD323-2 +1.35V_VIN 12 3 +1.35V_LX 1 2 +1.35V_P 2 1
OPTNS@ VIN4 SW_1 2 1

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
OPT@ JUMP_43X118
1 2 +1.35V_EN 16 4
1

23 FBVDDQ_PWR_EN EN4 SW_2 @ 1

1
OPT@ PC3611

OPT@ PC3606

OPT@ PC3607

OPT@ PC3612

OPTNS@ PC3608

OPTNS@ PC3613
PR706

1
100K_0402_5% 1 2 PC3604 OPT@ PC3605 OPTNS@
0.1U_0402_25V6 15 +1.35V_FB 1 2 PR3603
OPT@

2
1.8VGS_PWR_EN 1 PR3610 2 MAIN_PWR_EN 25 FB +3V_1.8VGS 2.2_0603_5%
23,26 1.8VGS_PWR_EN EN1

1
+3.3V_1.8V_AON 0.1U_0402_25V6 EMC_OPTNS@
0_0402_5% 23
@ PR3606

2
VOUT1

2
1 2 VIN1_3.3V_1.8V 22

+1.35V_SN
GC6@ PC3614 1K_0402_1%
VIN1

1U_0402_6.3V6K
09/08 change RV73 to PR3610 0.1U_0402_25V6 OPT@

1
OPT_NS@ PR3605 PC3615 6

2
PGND_1

OPT@
PC3618
LV5095AGQUF_UQFN29_4X4
0_0402_5% 1U_0402_6.3V6K
+5VALW

1
OPTNS@ 7 PR3607

1
2 1 PC3616 24 PGND_2 PC3619 +1.35V_FB_1 42.2K_0402_1%

2
1U_0402_6.3V6K VCC_SW 8 1000P_0402_50V7K OPT@

2
PGND_3

1
EMC_OPTNS@ PC3620
OPT@ 9 560P_0402_50V7-K 09/08 change PR3607 from 41.2K to 21K
PXS_PWR_EN_R 19 PGND_4
OPT@ 09/19 change PR3609 from 21K to 42.2K
Vout=1.35V± 5%

2
23 PXS_PWR_EN_R EN2 10
PC3621 Vset=1.36V± 2%
PGND_5

2
0.1U_0402_25V6 +3.3V_1.8V_AON_IN
21 11 +1.35V_FB
OPT@ VIN2 PGND_6 OCP>12A
PC3622 +3.3V_1.8V_AON

1
1 2 OPTNS@
20
Vref=0.6V
PR3617 1U_0402_6.3V6K VOUT2 PR3609 OVP=(1.25~1.35)*Vref

1
1 2 28 PC3623 32.4K_0402_1%
23,55 PXE_VDD_EN_R EN3
1U_0402_6.3V6K OPT@ UVP=(0.7~0.8)*Vref

2
0_0201_5%

100K_0201_5%
OPT@

2
OPTN17@ VOUT3_+1.0VGS

OPTN16@

PR3616
1 26
VIN3_1 VOUT3_1 09/08 change PR3609 from 32.4K to 16.2K
Fsw=700Khz
+1.0VALW 2 27 09/19 change PR3609 from 16.2K to 32.4K
VIN3_2 VOUT3_2 +1.0VGS
LSW1 RDS=36~50mohm,Io=0.5A

2
29 PC3625
+3.3V_1.8V_AON_IN VIN3_3 OPTN17@ LSW2 RDS=18~25mohm,Io=1A
1U_0402_6.3V6K
PR3618 1 2 0_0603_5%

TH_ALT

PGOOD
OPTN17@ LSW3 RDS=5~7mohm,Io=3.5A

1
+3VS

VCC
PR3613

2
2 1
PC3624
0_0402_5% 1U_0402_6.3V6K

14

17

13
+1.8VALW OPTN16@ OPTNS@ 09/08 change CV720 to PC3625
11/16 For N16 need to open this jumper，
N17 need to short

PR3614

+1.35V_VCC
2

1
2 2 1 2

09/08 change CV718 to PC3624 PR3611 PR3612

0_0402_5%
100K_0402_1% 100K_0402_1%
OPTN17@ OPTNS@ OPTNS@

2
1
PC3629
09/08 change RV1395 to PR3613 +3V_1.8VGS 1U_0402_6.3V6K
09/08 change RV1396 to PR3614 +3.3V_1.8V_AON

2
PR3615 OPT@
2 1
0_0402_5%
NGC6@
09/08 change RV1394 to PR3615

3 3

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/15 Deciphered Date 2013/08/15 PWR-VGA-PMIC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS A2 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EYG10
Date: Tuesday, January 09, 2018 Sheet 56 of 52
A B C D
 5 4 3 2 1

PWM-VID Specification
N17 Config N16 Config B Component Value N17 N16S-GTR
RT8816 PSI RT8812 PSI Phase Configuration
Vmin(V) 0.3 0.6 R1(KΩ ) PR816 6.19 20
1.6V~5.5V 2.4~5.5V 2Phase CCM
Vmax(V) 1.3 1.2 R2(KΩ ) PR812 20.5 20
1.08~1.35V 2Phase DEM
Vboot(V) 0.8 0.9 R3(KΩ ) PR815 4.32 2
0.7~0.88V 1.2~1.8V 1Phase CCM
Vstep(mV) 6.25 6.25 R4(KΩ ) PR813 16.5 18
0~0.4V 0~0.8V 1Phase DEM
N(level) 160 96 R5(KΩ ) PR818 0.309 0 V20B+
Fpwm(KHz) 675 1.125 C(nF) PC826 4.7 2.7
D Tdmin(nS) 9.26 9.26 D

T(uS) <100 <100

EMC_OPTNS@
+5VALW

0.1U_0201_25V6-K

10U_0805_25V6-K

10U_0805_25V6-K
1

1
PC801

PC802

PC803
2

2
1
PU801 PU801 RT8816A for N17 GPU
PR801 OPTNS@ PU801 RT8812A SA00005ZZ00 for N16 GPU
2_0603_5%
OPT@
OPT@ OPT@

2
NVVDD_PVCC 18
PVCC 2 NVVDD_HG1
UGATE1

1
PC804 PR805 PC805
+3.3V_1.8V_AON 1U_0402_6.3V6K 2.2_0603_5% 0.22U_0603_25V7K PQ801

2
1 NVVDD_BS1 1 2 1 2 AON6982_DFN8-7
OPT@

2
BOOT1 1 OPT@
1

21
PR806
5.1K_0402_1%
GND OPT@ OPT@
PL801
30A +VGA_CORE
20 NVVDD_PH1 7 NVVDD_PH1 1 2
OPT@ PHASE1
2

220U_B15G_2.5VM_R30M

220U_B15G_2.5VM_R30M
1
@ 6 0.24UH_CMMS061H-R24MS_17A_20%
PR802 1 2 0_0402_5% NVVDD_PSI_R 4 PR803
26 PSI_VGA OPT@ 1 1

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
PSI 2.2_0805_5%

1
PR804 OPT@ PR807 + +

PC806

PC807

PC811
OPTNS@ EMC_OPTNS@
1 2 1 2

OPTNS@ PC808

OPT@ PC809

OPT@ PC810

OPT@ PC812
+3VS

3
4
5

2
1K_0402_1% 5.1K_0402_1% 19 NVVDD_LG1

2
13 LGATE1 2 2
PGOOD V20B+

1
8,23 DGPU_PWROK

OPTNS@

OPT@

OPT@
PR829 PC814
PR808 NVVDD_EN_R
1 2 3 12.4K_0402_1% 1000P_0402_50V7K
23 NVVDD_EN

2
EN
25.5K_0402_1% OPTN16@ EMC_OPTNS@
1

C PC815 C

2
OPT@ 0.1U_0402_10V7K
1 2 OPT@ 09/09 change PR829 from 21K to 12.4K
2

PD801 OPT@
LRB751V-40T1G_SOD323-2
NVVDD_VID_R NVVDD_HG2

EMC_OPTNS@
1 2 5 14
26 NVVDD_PWM_VID

0.1U_0201_25V6-K
VID UGATE2

10U_0805_25V6-K

10U_0805_25V6-K
1

1
PR809 @ 0_0402_5% PR810 PC817

PC830

OPT@ PC831

OPT@ PC833
PC816 2.2_0603_5% 0.22U_0603_25V7K
0.1U_0402_10V7K 15 NVVDD_BS2 1 2 1 2 PQ802
2

2
BOOT2

2
AON6982_DFN8-7
OPTNS@
OPT@ OPT@ 1 OPT@ 09/15 try to DFC
+VGA_CORE
09/08 change 1U to 0.1uh PL802
16 NVVDD_PH2 7 NVVDD_PH2 1 2
2 1 NVVDD_VREF 8 PHASE2

220U_B15G_2.5VM_R30M

220U_B15G_2.5VM_R30M
VREF

1
6 0.24UH_CMMS061H-R24MS_17A_20% 1 1

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
PC818 PR811 OPT@
1

1
0.1U_0402_25V7-K 2.2_0805_5% + +

PC840

OPT@ PC819
PR812

OPT@ PC820

OPTNS@ PC822

OPT@ PC823
OPT@ EMC_OPTNS@
20.5K_0402_1%

3
4
5

2
2 2
OPTNS@ NVVDD_LG2

OPTNS@
17
2

LGATE2

1
PC824
NVVDD_REFIN 7 1000P_0402_50V7K

2
REFIN PR814
EMC_OPTNS@
2

100_0402_1%
1

PR833 1 2
PR813 0_0402_5% OPT@
16.5K_0402_1% UPI_OPT@
OPTNS@ PR816
PR815
1

6.19K_0402_1%
2

1 2 1 2 NVVDD_VIDBUF 6 PR817 @ 0_0402_5%

1

PC825 REFADJ 10 NVVDD_FBRTN 1 2

OPTNS@ RGND NVVDD_VSS_SENSE 22
0.01U_0402_25V7K 4.32K_0402_1%
1

B B
OPTNS@ OPTNS@ OPTN17@
2

1
PR818 PC826 PC827 VR Remote Sense - Tie to GPU sense points
309_0402_1% 4700P_0402_25V7-K 11 NVVDD_FB PR830 1 2 0_0402_5% 1000P_0402_25V7-K
OPTNS@ OPTNS@
N16 SS VSNS
OPTNS@
2

2
PR819
2

PR824 @ 0_0402_5%
2 1 NVVDD_FS 9 12 NVVDD_SS PR831 1 2 0_0402_5% 1 2
TON OCSET/SS NVVDD_VCC_SENSE 22
V20B+ 475K_0402_1%
N16 VSNS OPTN16@
PR825
PR820 OPT@ 100_0402_1%
2 1 1 2 +VGA_CORE

2.2_0603_5% OPT@
RT8816AGQW_WQFN20_3X3
RT_OPT@
1

UPI_OPTNS@

PC849
1000P_0402_25V7-K
1

OPTN17@

OPTN16@
OPTN17_NS@

1U_0402_25V6-K PR832
1000P_0402_25V7-K

1000P_0402_25V7-K
2

PR834 51K_0402_1%
PC836

RT_OPT@
110K_0402_1%
2

2
PC837

PR821

PC835

115K_0402_1% UPI_OPT@
UPI_OPT@
2

PR827
Vboot=0.8V
2

0_0402_5%
2
2

1 2 NVVDD_FBRTN PC834
1000P_0402_25V7-K
Ripple=± 20mV
UPI_OPT@
UPI_OPT@ TDC=28.5A Iccmax=55A OCP>75A
1
2

PR826
0_0402_5% For UPI:AON6982 LSMOS Rdson(max)=2.45mohm, TDC=30A Iccmax=60.1A OCP>80A
PR834=115K, PR819=71.5K , Fsw=400KHZ,OCP=78.7A
RT_OPT@ PR834=78.7K，PR819=47.7K,Fsw=300KHZ,OCP=77.15A Vref=2V
1

09/09 change PR821 from 220K to 110K

FUVP:Vfb=0.2V
SUVP:Vcomp=3V
OVP:Vfb=2V
A
Fsw=320KHz A

UPI Solution only

N16 GPU_OPT@ : RT8812A for N16 GPU Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 PWR-VGA_CORE

N17 GPU_OPT@ : RT8816A for N17 GPU THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EYG10
Date: Tuesday, January 09, 2018 Sheet 57 of 60
5 4 3 2 1
 5 4 3 2 1

SVID Specification
+VCCST_CPU
Config
Vmin(V) 0
Vmax(V) 1.52 V20B+ +5VS
Vstep(mV) 5

1
+VCCST_CPU

1K_0402_1%

100_0402_1%
2.2_0603_5%

45.3_0402_1%
1

1
75_0402_1%
PR901

PR902

1U_0402_6.3V6K
09/09 add PR970 1K @

PC903

PR908

PR910
PR909
RFsw Core/GT SA

2
0.01U_0402_25V7K

2.2U_0603_10V7K

2
28.7K 550K 550K

1K_0402_5%
PC901

PC902
VR_VRMP

PR970
VR_VCC
09/08 change PU901 from NCP81218B to NCP81218
+VCCST_CPU

2
RVboot Core GT SA @ @

2 PR903 1

2 PR904 1
1K_0402_1%

54.9_0402_1%
D PR912 D

2
PU901 10_0402_1%
VR_SVID_DAT_1 2 1
35.7K 0V 0V 1.05V @

12

13
NCP81218MNTXG_QFN48_6X6 VR_SVID_DAT 12

2 PR905 1
1K_0402_1%
PR915
0_0402_5%

VCC
VRMP
VR_SVID_ALRT#_1 2 1 @
VR_SVID_ALRT# 12
PR906
49.9_0402_1%
VR_SVID_CLK_1 2 1
VR_SVID_CLK 12
@
PR911 1 2 0_0402_5% VR_EN 37 38
44 EC_VR_ON EN VR_RDY CPU_VR_READY 44

VR_SVID_ALRT#_1 33 31
ALERT# VR_HOT# VR_HOT# 44,53
@
VR_SVID_CLK_1 34 35 VR_DRON PR965 1 2 0_0402_5%
SCLK DRVON DRON 59

VR_SVID_DAT_1 32 22 PWM_1A
SDIO PW M_1A PWM_1A 59

46 29 GT_CSP PR917 1 2 7.5K_0402_1% GT_PH 59

44,53 Psys PSYS CSP_1A

1500P_0402_50V6-K

0.033U_0402_25V7-K
09/15 PR919,PR907 change from 4.99K to 4.87K
PH901
GT_CSP_1

1
PC904

PC905
1 2 1 2
+VCC_GT 12,59,60
PR919 1 2 4.87K_0402_1% PR918
22K_0402_1% 100K_0402_1%_TSM0B104F4251RZ

2
PR907 1 2 4.87K_0402_1% GT_VSP_1 1 2 GT_VSP 24
12 VCCGT_VCC_SEN VSP_1A
PC906
1000P_0402_50V7K
1

PR961
PC907 09/08 change PN only
1000P_0402_50V7K PR920 1 2 499_0402_1% 28 GT_CSN 1 2
2

CSN_1A

GT_VSN 25 10_0402_1%

1
PC908 1 2 330P_0402_50V7K 23
12 VCCGT_VSS_SEN VSN_1A TSENSE_1PH PC935
2200P_0402_50V7K

2
C C

PR923 PC910
09/09 PR923 change from 2.7K to 2.15k 2.15K_0402_1% 0.015U_0402_25V7-K @
09/09 PC910 change from 1500PF to 0.015u 1 2 GT_COMP_1 1 2 GT_COMP 26 GT_TSENSE 1 2 PR922 1 2 8.25K_0402_1%
09/09 PC911 change from 15PF to 150Pf COMP_1A PR921
PC911 1 2 150P_0402_50V8-J 0_0402_5%

1
PH902 1 2 100K_0402_1%_TSM0B104F4251RZ
PC909
PC912 1 2 1000P_0402_50V7K .1U_0402_10V6-K Place close to MOSFET

2
PR924 1 2 51K_0402_1% GT_ILIM 27
ILIM_1A
16 PWM1_2PH
PW M1_2PH PWM1_2PH 59
PC913 1 2 470P_0402_50V7K GT_IOUT 30
IOUT_1A 17 PWM2_2PH
PW M2_2PH PWM2_2PH 59
PR927 97.6K_0402_1%
1 2

11/06 PR927 change 102k to 97.6k 10 IA_CSP1 PR928 1 2 2.4K_0402_1%

CSP1_2PH IA_PH1 58,59
47
12 VCORE_VCC_SEN VSP_2PH IA_CSP2
9 PR929 1 2 2.4K_0402_1%
CSP2_2PH IA_PH2 58,59
1

PC914
U42@

1
1000P_0402_50V7K PR963
PR930 1 2 1K_0402_1% PC915 PC916 1 2
+5VS
2

0.1U_0402_10V7K 0.1U_0402_10V7K

2
U42@ 2K_0402_5%
PC917 1 2 3300P_0402_50V7-K IA_VSN 48
12 VCORE_VSS_SEN VSN_2PH 8 IA_CSREF U22@ PR932 1 2 10_0402_1%
CSREF_2PH +CPU_CORE 12,58,59,60
PC918 1 2 470P_0402_50V7K
IA_IOUT

1
PR933 1 2 24K_0402_1% 1 PR934 1 2 10_0402_1%
IOUT_2PH +CPU_CORE 12,58,59,60
PC919
0.1U_0402_10V7K
U42@

2
09/09 PR933 change from 25.5K to 24k

PR936
88.7K_0402_1%
IA_DIFFOUT 2 7 IA_CSSUM 1 2
DIFFOUT_2PH CSSUM_2PH IA_PH1 58,59
B B
IA_FB 3
FB_2PH PC920 1 2 680P_0402_50V7K

PR937 PC922 PR938 PC923 PC921 1 2 120P_0402_50V8-J

49.9_0402_1% 470P_0402_50V7K 4.75K_0402_1% 2200P_0402_50V7K PR942
1 2 IA_FB_1 1 2 1 2 IA_COMP_1 1 2 IA_COMP 4 PR939 88.7K_0402_1%
COMP_2PH 6 IA_CSCOMP 1 2 IA_CSCOMP_1 1 2 1 2
CSCOMP_2PH IA_PH2 58,59
PR940 1 2 1K_0402_1% PC924 1 2 22P_0402_50V8-J @ 75K_0402_1%
PR941
5 IA_ILIM 1 2 1 2 249K_0402_1%
U42@
ILIM_2PH PH903
09/09 PR944 and PR945 change from 887 to 787 PR944 1 2 787_0402_1% PR943 220K_0402_5%_TSM0B224J4702RE 09/09 PR936 and PR942 change from 82.5K to 88.7K
19.6K_0402_1%
PR945
1 2 SA_VSP_1 PC925 1 2 SA_VSP 45 PR943 19.6K for U42 SKU
13 VCCSA_VCC_SEN VSP_1B PR943 change to SD03497618J 9.76K for U22 SKU
787_0402_1% 1000P_0402_50V7K @
11 IA_TSENSE PR946 1 2 0_0402_5% PR947 1 2 8.25K_0402_1%
TSENSE_2PH
1

PC926
1000P_0402_50V7K
1

PR948 1 2 499_0402_1% PH904 1 2 100K_0402_1%_TSM0B104F4251RZ

2

PC927
.1U_0402_10V6-K Place close to MOSFET
2

PC928 1 2 220P_0402_50V7K SA_VSN 44

13 VCCSA_VSS_SEN VSN_1B
PR950 36 PWM_1B
PW M_1B PWM_1B 59
1.5K_0402_1% PC929
1 2 SA_COMP_1 1 2 0.015U_0402_25V7-K SA_COMP 43 40 SA_CSP PR951 1 2 7.5K_0402_1%
COMP_1B CSP_1B SA_PH 59
4700P_0402_25V7-K

1800P_0402_50V7-K

PC930 1 2 15P_0402_50V8J
SA_CSP_1
1

1
PC931

PC933

PR952 1 2 22K_0402_1% 1 2
ROSC_COREGT

09/19 PR953 change from 8.25K to 10K SA_ILIM 42 +VCCSA 13,59,60

PR953 1 2 10K_0402_1%
ADDR_VBOOT
ICCMAX_2PH

ILIM_1B
ROSC_SAUS

PH905
ICCMAX_1A

ICCMAX_1B

PC932 1 2 1000P_0402_50V7K 100K_0402_1%_TSM0B104F4251RZ

PR962
PR954 1 2 25.5K_0402_1% SA_Iout 39 41 1 2
TAB

09/09 PR954 change from 28.7K to 25.5K IOUT_1B CSN_1B

1

PC934 1 2 470P_0402_50V7K
09/09 PC933 change from 1000PF to 1800PF PC936 10_0402_1%
14

15

18

19

20

21

49

2200P_0402_50V7K
2
2 PR955 1 RSOC_COREGT

ICCMAX_2PH
RSOC_SAUS

2 PR960 1 ADDR_VBOOT
ICCMAX_1A

ICCMAX_1B

A A
102K_0402_1%

100K_0402_1%
28.7K_0402_1%

28.7K_0402_1%

19.6K_0402_1%

35.7K_0402_1%
2 PR956 1

2 PR957 1

2 PR958 1

2 PR959 1

@
PR957 102K for U42 SKU
PR957 change to SD00001TM00 51K for U22 SKU

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 PWR-CPU_CORE1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EYG10
Date: Tuesday, January 09, 2018 Sheet 58 of 60
5 4 3 2 1
 5 4 3 2 1

PJ1001 @
GT_VIN 2 1
2 1 V20B+

10U_0805_25V6-K

10U_0805_25V6-K
0.1U_0201_25V6-K

1
EMC_NS@
+5VS

PC1003

PC1004
PR1001 PC1001 JUMP_43X79

PC1002
1 2 1 2
Vboot=0V Loadline=3.1mΩ

2
2

2.2_0603_5% 0.22U_0603_16V7K

GT_BST
PR1002
Ripple=+30mV/-10mV(0A~0.5A)
2.2_0603_5%
PQ1001
+VCC_GT
PU1001 Ripple=± 10mV(0.5A~TDC)

2
1

1 1
GT_VCC 4 BST Ripple=± 15mV(TDC~Iccmax)
@
GT_PWM
VCC
DRVH
8 GT_HG PL1001 18A TDC=18A Iccmax=31A OCP=37A
1U_0402_10V6K

PR1003 1 2 0_0402_5% 2 0.15UH_PCME064T-R15MS0R667_36A_20%

58 PWM_1A PW M 7 GT_PH 7 GT_PH 1 2
SW OVP=VID+370mV~VID+430mV
1
PC1016

3
58,59 DRON EN GT_LG
5 6
DRVL Max Overshoot:70mv/10us

1
9
2

D FLAG 6 PR1004 D
GND 2.2_0805_5% UVP=VID-370mV~VID-225mV
NCP81253MNTBG_DFN8_2X2 AON6982_DFN8-7 EMC_NS@ Fsw=550Khz

3
4
5

2
+VCC_GT 12,58,60

1
PC1029
1200P_0402_50V7-K
GT_PH 58

2
EMC_NS@

@
PJ1002
CPU_VIN 2 1
2 1 V20B+

33U_D2_25VM_R40M

33U_D2_25VM_R40M
JUMP_43X118 1 1

EMC_NS@

10U_0805_25V6-K

10U_0805_25V6-K
0.1U_0201_25V6-K
+5VS

1
PC1031

U42@ PC1032

U42@ PC1033

PC1035

PC1036
+ +
PJ1004 @
PR1007 PC1030

5
2 1
1 2 1 2 2 1

2
2

2 2
JUMP_43X79
PR1008 2.2_0603_5% 0.22U_0603_16V7K
IA_BST2
@
2.2_0603_5% U42@ U42@
U42@ 4
PU1002 U42@ PQ1003
+CPU_CORE
1

NCP81151MNTBG_DFN8_2X2 AON6380_DFN8-5
IA_VCC2 4 1
VCC BST U42@
PR1009
1 2 IA_CORE_PWM_2 2 8 IA_HG2 PL1002

3
2
1
U42@ PW M DRVH
58 PWM2_2PH 0_0402_5% 0.15UH_PCME064T-R15MS0R667_36A_20%
IA_PH2 IA_PH2_2
1

PC1034 3 7 1 2
58,59 DRON EN SW
1U_0402_10V6K U42@
9 5 IA_LG2
U42@
2

FLAG DRVL

5
C C

1
6
GND PQ1004
PR1010
AON6324_DFN8-5 2.2_0805_5%
U42@ EMC_NS@ Vboot=0V Loadline=2.4mΩ
4
U22 :21A

2
+CPU_CORE 12,58,59,60 Ripple=+30mV/-10mV(0A~0.5A)
U42:42A

1
PC1037
Ripple=± 10mV(0.5A~TDC)
1200P_0402_50V7-K

3
2
1
IA_PH2 58 Ripple=± 15mV(TDC~Iccmax)

2
EMC_NS@
TDC=21A/42A Iccmax=32A/64A
OCP=37A / 74A
CPU_VIN Max Overshoot:70mv/10us
+5VS
OVP=VID+370mV~VID+430mV

0.1U_0201_25V6-K
PC1038

EMC_NS@

10U_0805_25V6-K

10U_0805_25V6-K
1 2 1 2
UVP=VID-370mV~VID-225mV
5
IA_BST1

1
PC1039

PC1040

PC1041
PR1013
PQ1005
2

2.2_0603_5% 0.22U_0603_16V7K
PR1014 AON6380_DFN8-5 Fsw=550Khz

2
2.2_0603_5%
PU1003
4
+CPU_CORE
NCP81151MNTBG_DFN8_2X2
1

IA_VCC1 4 1
VCC BST
1U_0402_10V6K

@
PR1015 1 IA_CORE_PWM_1
2 0_0402_5% 2 8 IA_HG1 PL1003
PW M DRVH
1

58 PWM1_2PH
PC1055

0.15UH_PCME064T-R15MS0R667_36A_20%
3
2
1

3 7 IA_PH1 IA_PH1_1 1 2
58,59 DRON EN SW
2

9 5 IA_LG1
5

FLAG DRVL
1

6 PR1016
GND PQ1006 2.2_0805_5%
AON6324_DFN8-5 EMC_NS@
4
2

+CPU_CORE 12,58,59,60
1

PC1068
1200P_0402_50V7-K
3
2
1

B EMC_NS@ IA_PH1 58 B

PJ1003
Vboot=0V Loadline=10.3Ω
SA_VIN @
2 1
2 1 V20B+ Ripple=+30mV/-10mV(0A~0.5A)
10U_0805_25V6-K

10U_0805_25V6-K
0.1U_0201_25V6-K

JUMP_43X79
+5VS Ripple=± 10mV(0.5A~TDC)
5

1
PC1071

PC1072

PC1069
PC1070

1 2 1 2
PR1019 PQ1007
Ripple=± 15mV(TDC~Iccmax)
2

2
2

2.2_0603_5% 0.22U_0603_16V7K AON7408L_DFN8-5

SA_BST

PR1020
TDC=4A Iccmax=4.5A OCP=7A
4
2.2_0603_5%
+VCCSA Max Overshoot:70mv/10us
PU1004
EMC_NS@ OVP=VID+370mV~VID+430mV
1

1
SA_VCC 4 BST PL1004 4A UVP=VID-370mV~VID-225mV
3
2
1

@ VCC 8 SA_HG 0.47UH_SPS-04BZ-R47M-X2_7A_20%

2 0_0402_5% VCCSA_PWM DRVH SA_PH
1U_0402_10V6K

PR1021 1 2 1 2
58 PWM_1B PW M 7 SA_PH Fsw=550Khz
SW
1
PC1073

3
58,59 DRON EN SA_LG
5

5
9 DRVL PR1022
D
2

A
FLAG 6 2.2_0805_5% A
GND PQ1008
NCP81253MNTBG_DFN8_2X2 AON7506_DFN8-5
2

4
G EMC_NS@
+VCCSA 13,58,60
1
S3
S2
S1

PC1083
1200P_0402_50V7-K
3
2
1

EMC_NS@ SA_PH 58

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 PWR_CPU_CORE2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EYG10
Date: Tuesday, January 09, 2018 Sheet 59 of 60
5 4 3 2 1
 A
B
C
D
2 1

09/09 EE delete CC1097

add PC4091 22uf for all

5
5

PC4091

09/09-2 delete CC1108 and

2 1 2 1 22U_0402_4V6-M 2 1

@ PC4013 @ PC4079 PC4045

VCCSA:
22U_0603_6.3V6-M 10U_0402_6.3V6M 2 1 22U_0603_6.3V6-M
2 1
PC4089
2 1 22U_0402_4V6-M PC4046 2 1

@
22U_0603_6.3V6-M
PC4014 PC4003
22U_0603_6.3V6-M 2 1 2 1 2 1 22U_0603_6.3V6-M

CPU_CORE U42 only:

PC4081 PC4066 PC4047 2 1

22uf ,Power add PC4089

2 1 10U_0402_6.3V6M 22U_0603_6.3V6-M 22U_0603_6.3V6-M
PC4004
PC4015 2 1 2 1 2 1 22U_0603_6.3V6-M
22U_0603_6.3V6-M
PC4067 2 1
@ PC4082 PC4048
2 1 22U_0603_6.3V6-M
22U_0402_4V6-M 22U_0603_6.3V6-M

09/09 NC PC4069,PC4049
PC4005
PC4016 2 1 2 1 2 1 22U_0603_6.3V6-M
22U_0603_6.3V6-M

09/09 PC4082 from U42 22uf to @

PC4083 PC4068 PC4049 2 1 2 1

@
@
10U_0402_6.3V6M 10U_0402_6.3V6M 22U_0603_6.3V6-M
2 1 2 1 PC4029 PC4006

6PCS 22U_0603_6.3V
@
2 1 2 1 10U_0402_6.3V6M 22U_0603_6.3V6-M
PC4019 PC4084
22U_0603_6.3V6-M 10U_0402_6.3V6M PC4069 @ PC4050 2 1 2 1
22U_0402_4V6-M 22U_0603_6.3V6-M 2 1
GT : 12PCS 22U_0603_6V + 4PCS 10U_0402_6V

2 1 2 1 2 1 PC4030

5PCS 22U_0402_4V
@ PC4007
2 1 10U_0402_6.3V6M PC4090 22U_0603_6.3V6-M

4
4

PC4070 PC4051 22U_0603_6.3V6-M

@
@ PC4085
PC4020 22U_0402_4V6-M 10U_0402_6.3V6M 22U_0603_6.3V6-M 2 1 2 1 2 1

@
22U_0603_6.3V6-M

09/09 PC4085 @

09/09 NC PC4020
@

2 1 @ PC4027 PC4028 @ PC4008

+CPU_CORE
2 1 2 1 10U_0402_6.3V6M 22U_0603_6.3V6-M 22U_0603_6.3V6-M
PC4052 2 1 2 1 2 1

09/09 PC4069 change from U22@ to for ALL

0915 NC PC4007,PC4027

PC4021 PC4071 22U_0603_6.3V6-M

1106 NC PC4028,PC4010

22U_0603_6.3V6-M 10U_0402_6.3V6M 2 1 PC4031 PC4023 PC4009

2 1 2 1 10U_0402_6.3V6M 22U_0603_6.3V6-M 22U_0603_6.3V6-M
@ PC4053 2 1 2 1 2 1
0915 NC PC4008,PC4025,PC4026,

2 1 @ PC4087 PC4072 22U_0603_6.3V6-M

@

10U_0402_6.3V6M 10U_0402_6.3V6M 2 1 @ PC4032 PC4024 PC4010

PC4022 2 1 10U_0402_6.3V6M 22U_0603_6.3V6-M 22U_0603_6.3V6-M

+VCCSA
22U_0603_6.3V6-M 2 1 PC4054 2 1 2 1 2 1
PC4073 22U_0603_6.3V6-M

@
@ PC4088 10U_0402_6.3V6M PC4033 @ PC4025 PC4011

09/09 NC PC4073
10U_0402_6.3V6M 10U_0402_6.3V6M 22U_0603_6.3V6-M 22U_0603_6.3V6-M

2 1 2 1 2 1

PC4034 @ PC4026 PC4012

10U_0402_6.3V6M 22U_0603_6.3V6-M 22U_0603_6.3V6-M

Issued Date
09/09 NC PC4087,,mount CC1317

Security Classification
+VCC_GT

2 1 2 1

2
1
+
PC4074 PC4055 PC4035

@
U42@
330U_B2_2VM_R15M 22U_0603_6.3V6-M 10U_0402_6.3V6M

3
3

2 1

1
1

+
+

2 1
CPU_CORE U22: 10PCS 22U_0603_6V + 4PCS 22U_0402_4V + 9PCS 10U_0402_6.3V

09/09 NC PC4070,PC4068 10UF,mount PC4035,PC4037 10uf

2 3
2 3

@ PC4036
PC4075 @ PC4056 22U_0402_4V6-M PC4001
220U_D2_2VM_R6M 22U_0603_6.3V6-M 2 1 220U_D2_2VM_R6M
2 1

2015/08/20
2
1
+
PC4037
2
1
+

U42@ PC4076 PC4057 10U_0402_6.3V6M

22U_0603_6.3V6-M PC4002
330U_B2_2VM_R15M 330U_B2_2.5VM_R9M
2 1

2
1
+
PC4058
@

@ PC4077
22U_0603_6.3V6-M
330U_B2_2VM_R15M 2 1

PC4059 2 1
@

22U_0603_6.3V6-M
@ PC4038
2 1 22U_0402_4V6-M

PC4060 2 1
@

Deciphered Date
22U_0603_6.3V6-M
2 1 @ PC4086
22U_0402_4V6-M
PC4061
+CPU_CORE

22U_0603_6.3V6-M 2 1

LC Future Center Secret Data

2 1 @ PC4080

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
10U_0402_6.3V6M
PC4062
@

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

2
2

22U_0603_6.3V6-M

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
2016/08/20

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

Date:
Custom
Title

Size Document Number

PC4038 from U22 22uf to U22 22uf/U42 10uf
PC4080 from U42 10uf to U42 22uf/U22 10uf
09/09 PC4086 from U42 22uf to U42 22uf/u22 10uf

Tuesday, January 09, 2018

EYG10
1
1

Sheet
PWR-CPU Decoupling Cap

60
of
1
Rev
0.3
A
B
C
D
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 NGFF_SSD_1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EYG10
Date: Tuesday, January 09, 2018 Sheet 61 of 60
5 4 3 2 1