PIC16F882/883/884/886/887

28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers

High-Performance RISC CPU: Peripheral Features:

• Only 35 Instructions to Learn: • 24/35 I/O Pins with Individual Direction Control:
- All single-cycle instructions except branches - High current source/sink for direct LED drive
• Operating Speed: - Interrupt-on-Change pin
- DC – 20 MHz oscillator/clock input - Individually programmable weak pull-ups
- DC – 200 ns instruction cycle - Ultra Low-Power Wake-up (ULPWU)
• Interrupt Capability • Analog Comparator Module with:
• 8-Level Deep Hardware Stack - Two analog comparators
• Direct, Indirect and Relative Addressing modes - Programmable on-chip voltage reference
(CVREF) module (% of VDD)
Special Microcontroller Features: - Fixed voltage reference (0.6V)
• Precision Internal Oscillator: - Comparator inputs and outputs externally
- Factory calibrated to ±1% accessible
- Software selectable frequency range of - SR Latch mode
8 MHz to 31 kHz - External Timer1 Gate (count enable)
- Software tunable • A/D Converter:
- Two-Speed Start-up mode - 10-bit resolution and 11/14 channels
- Crystal fail detect for critical applications • Timer0: 8-bit Timer/Counter with 8-bit
- Clock mode switching during operation for Programmable Prescaler
power savings • Enhanced Timer1:
• Power-Saving Sleep mode - 16-bit timer/counter with prescaler
• Wide Operating Voltage Range (2.0V-5.5V) - External Gate Input mode
• Industrial and Extended Temperature Range - Dedicated low-power 32 kHz oscillator
• Power-on Reset (POR) • Timer2: 8-bit Timer/Counter with 8-bit Period
• Power-up Timer (PWRT) and Oscillator Start-up Register, Prescaler and Postscaler
Timer (OST) • Enhanced Capture, Compare, PWM+ Module:
• Brown-out Reset (BOR) with Software Control - 16-bit Capture, max. resolution 12.5 ns
Option - Compare, max. resolution 200 ns
• Enhanced Low-Current Watchdog Timer (WDT) - 10-bit PWM with 1, 2 or 4 output channels,
with On-Chip Oscillator (software selectable programmable “dead time”, max. frequency
nominal 268 seconds with full prescaler) with 20 kHz
software enable - PWM output steering control
• Multiplexed Master Clear with Pull-up/Input Pin • Capture, Compare, PWM Module:
• Programmable Code Protection - 16-bit Capture, max. resolution 12.5 ns
• High Endurance Flash/EEPROM Cell: - 16-bit Compare, max. resolution 200 ns
- 100,000 write Flash endurance - 10-bit PWM, max. frequency 20 kHz
- 1,000,000 write EEPROM endurance • Enhanced USART Module:
- Flash/Data EEPROM retention: > 40 years - Supports RS-485, RS-232, and LIN 2.0
• Program Memory Read/Write during run time - Auto-Baud Detect
• In-Circuit Debugger (on board) - Auto-Wake-Up on Start bit
• In-Circuit Serial ProgrammingTM (ICSPTM) via Two
Low-Power Features: Pins
• Master Synchronous Serial Port (MSSP) Module
• Standby Current: supporting 3-wire SPI (all 4 modes) and I2C™
- 50 nA @ 2.0V, typical Master and Slave Modes with I2C Address Mask
• Operating Current:
- 11 A @ 32 kHz, 2.0V, typical
- 220 A @ 4 MHz, 2.0V, typical
• Watchdog Timer Current:
- 1 A @ 2.0V, typical

 2006-2012 Microchip Technology Inc. DS41291G-page 1

 PIC16F882/883/884/886/887
Pin Diagrams – PIC16F884/887, 40-Pin PDIP
40-Pin PDIP

RE3/MCLR/VPP 1 40 RB7/ICSPDAT
RA0/AN0/ULPWU/C12IN0- 2 39 RB6/ICSPCLK
RA1/AN1/C12IN1- 3 38 RB5/AN13/T1G
RA2/AN2/VREF-/CVREF/C2IN+ 4 37 RB4/AN11
RA3/AN3/VREF+/C1IN+ 5 36 RB3/AN9/PGM/C12IN2-
RA4/T0CKI/C1OUT 6 35 RB2/AN8
RA5/AN4/SS/C2OUT 7 34 RB1/AN10/C12IN3-
RE0/AN5 8 33 RB0/AN12/INT

PIC16F884/887
RE1/AN6 9 32 VDD
RE2/AN7 10 31 VSS
VDD 11 30 RD7/P1D
VSS 12 29 RD6/P1C
RA7/OSC1/CLKIN 13 28 RD5/P1B
RA6/OSC2/CLKOUT 14 27 RD4
RC0/T1OSO/T1CKI 15 26 RC7/RX/DT
RC1/T1OSI/CCP2 16 25 RC6/TX/CK
RC2/P1A/CCP1 17 24 RC5/SDO
RC3/SCK/SCL 18 23 RC4/SDI/SDA
RD0 19 22 RD3
RD1 20 21 RD2

 2006-2012 Microchip Technology Inc. DS41291G-page 7

 PIC16F882/883/884/886/887
Pin Diagrams – PIC16F884/887, 44-Pin TQFP
44-Pin TQFP

RC1/T1OSCI/CCP2
RC2/P1A/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC6/TX/CK
RC5/SDO

RD3
RD2
RD1
RD0

NC
44
43
42
41
40
39

37
36
35
34
38
RC7/RX/DT 1 33 NC
RD4 2 32 RC0/T1OSO/T1CKI
RD5/P1B 3 31 RA6/OSC2/CLKOUT
RD6/P1C 4 30 RA7/OSC1/CLKIN
RD7/P1D 5 29 VSS
VSS 6 PIC16F884/887 28 VDD
VDD 7 27 RE2/AN7
RB0/AN12/INT 8 26 RE1/AN6
RB1/AN10/C12IN3- 9 25 RE0/AN5
RB2/AN8 10 24 RA5/AN4/SS/C2OUT
RB3/AN9/PGM/C12IN2- 11 23 RA4/T0CKI/C1OUT
12
13
14
15
16
17
18
19
20
21
22
RA2/AN2/VREF-/CVREF/C2IN+
RB7/ICSPDAT

RA3/AN3//VREF+/C1IN+
RB4/AN11
NC
NC

RB5/AN13/T1G
RB6/ICSPCLK

RE3/MCLR/VPP

RA1/AN1/C12IN1-
RA0/AN0/ULPWU/C12IN0-

 2006-2012 Microchip Technology Inc. DS41291G-page 11

 PIC16F882/883/884/886/887
FIGURE 1-2: PIC16F884/PIC16F887 BLOCK DIAGRAM

Configuration PORTA
13 8 RA0
Data Bus
Program Counter RA1
Flash RA2
4K(1)/8K X 14 RA3
RA4
Program RAM RA5
Memory 8-Level Stack 256(1)/368 Bytes RA6
(13-Bit) File RA7
Registers
Program PORTB
14
Bus RAM Addr RB0
9
RB1
Addr MUX RB2
Instruction Reg
RB3
Direct Addr 7 Indirect RB4
8 Addr RB5
RB6
FSR Reg
RB7

STATUS Reg PORTC

8 RC0
RC1
RC2
3 RC3
MUX
Power-up RC4
Timer RC5
Instruction RC6
Oscillator
Decode and Start-up Timer RC7
ALU
Control
Power-on PORTD
OSC1/CLKIN Reset 8 RD0
Timing Watchdog RD1
Generation W Reg RD2
Timer
RD3
OSC2/CLKOUT Brown-out CCP2
RD4
Reset
RD5
Internal RD6
Oscillator RD7
Block CCP2
PORTE
MCLR VDD VSS
RE0
In-Circuit RE1
Debugger RE2
(ICD)
RE3

T1OSI Timer1
32 kHz
CCP1/P1A

SCK/SCL
T1OSO Oscillator
SDI/SDA
RX/DT
TX/CK

SDO
P1C

P1D
P1B

SS
T0CKI T1G T1CKI

Master Synchronous
Timer0 Timer1 Timer2 EUSART ECCP
Serial Port (MSSP)

VREF+
VREF+ Analog-To-Digital Converter 2 Analog Comparators 8
VREF- EEDATA
VREF- (ADC) and Reference
CVREF
256 Bytes
Data
EEPROM
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
AN10
AN11
AN12
AN13

C1IN+

C2IN+
C1OUT

C2OUT
C12IN0-
C12IN1-
C12IN2-
C12IN3-

EEADDR

Note 1: PIC16F884 only.

 2006-2012 Microchip Technology Inc. DS41291G-page 17

 PIC16F882/883/884/886/887
2.0 MEMORY ORGANIZATION FIGURE 2-2: PROGRAM MEMORY MAP
AND STACK FOR THE
2.1 Program Memory Organization PIC16F883/PIC16F884

The PIC16F882/883/884/886/887 devices have a 13-bit PC<12:0>

program counter capable of addressing a 2K x 14
CALL, RETURN
(0000h-07FFh) for the PIC16F882, 4K x 14 (0000h- 13
RETFIE, RETLW
0FFFh) for the PIC16F883/PIC16F884, and 8K x 14
(0000h-1FFFh) for the PIC16F886/PIC16F887 program
Stack Level 1
memory space. Accessing a location above these
boundaries will cause a wrap-around within the first 8K x Stack Level 2

14 space. The Reset vector is at 0000h and the interrupt

vector is at 0004h (see Figures 2-2 and 2-3).
Stack Level 8

FIGURE 2-1: PROGRAM MEMORY MAP Reset Vector 0000h

AND STACK FOR THE
PIC16F882

PC<12:0> Interrupt Vector 0004h

CALL, RETURN 0005h
13 Page 0
RETFIE, RETLW On-Chip
07FFh
Program
Memory 0800h
Page 1
Stack Level 1
0FFFh
Stack Level 2

Stack Level 8 FIGURE 2-3: PROGRAM MEMORY MAP

AND STACK FOR THE
Reset Vector 0000h PIC16F886/PIC16F887

PC<12:0>

CALL, RETURN 13
Interrupt Vector 0004h RETFIE, RETLW
On-Chip 0005h
Program Page 0
Memory 07FFh Stack Level 1
Stack Level 2

Stack Level 8

Reset Vector 0000h

Interrupt Vector 0004h

0005h
Page 0
07FFh
0800h
Page 1
On-Chip
0FFFh
Program
Memory 1000h
Page 2
17FFh
1800h
Page 3
1FFFh

 2006-2012 Microchip Technology Inc. DS41291G-page 23

 PIC16F882/883/884/886/887
FIGURE 2-6: PIC16F886/PIC16F887 SPECIAL FUNCTION REGISTERS
File File File File
Address Address Address Address
Indirect addr. (1) 00h Indirect addr. (1) 80h Indirect addr. (1) 100h Indirect addr. (1) 180h
TMR0 01h OPTION_REG 81h TMR0 101h OPTION_REG 181h
PCL 02h PCL 82h PCL 102h PCL 182h
STATUS 03h STATUS 83h STATUS 103h STATUS 183h
FSR 04h FSR 84h FSR 104h FSR 184h
PORTA 05h TRISA 85h WDTCON 105h SRCON 185h
PORTB 06h TRISB 86h PORTB 106h TRISB 186h
PORTC 07h TRISC 87h CM1CON0 107h BAUDCTL 187h
PORTD(2) 08h TRISD(2) 88h CM2CON0 108h ANSEL 188h
PORTE 09h TRISE 89h CM2CON1 109h ANSELH 189h
PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah
INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh
PIR1 0Ch PIE1 8Ch EEDAT 10Ch EECON1 18Ch
PIR2 0Dh PIE2 8Dh EEADR 10Dh EECON2(1) 18Dh
TMR1L 0Eh PCON 8Eh EEDATH 10Eh Reserved 18Eh
TMR1H 0Fh OSCCON 8Fh EEADRH 10Fh Reserved 18Fh
T1CON 10h OSCTUNE 90h 110h 190h
TMR2 11h SSPCON2 91h 111h 191h
T2CON 12h PR2 92h 112h 192h
SSPBUF 13h SSPADD 93h 113h 193h
SSPCON 14h SSPSTAT 94h 114h 194h
CCPR1L 15h WPUB 95h 115h 195h
CCPR1H 16h IOCB 96h General 116h General 196h
CCP1CON 17h VRCON 97h Purpose 117h Purpose 197h
Registers Registers
RCSTA 18h TXSTA 98h 118h 198h
TXREG 19h SPBRG 99h 16 Bytes 119h 16 Bytes 199h
RCREG 1Ah SPBRGH 9Ah 11Ah 19Ah
CCPR2L 1Bh PWM1CON 9Bh 11Bh 19Bh
CCPR2H 1Ch ECCPAS 9Ch 11Ch 19Ch
CCP2CON 1Dh PSTRCON 9Dh 11Dh 19Dh
ADRESH 1Eh ADRESL 9Eh 11Eh 19Eh
ADCON0 1Fh ADCON1 9Fh 11Fh 19Fh
20h A0h 120h 1A0h
General
General General
3Fh Purpose
General Purpose Purpose
Registers
Purpose 40h Registers Registers
Registers 80 Bytes
80 Bytes 80 Bytes
96 Bytes 6Fh EFh 16Fh 1EFh
70h accesses F0h accesses 170h accesses 1F0h
7Fh 70h-7Fh FFh 70h-7Fh 17Fh 70h-7Fh 1FFh
Bank 0 Bank 1 Bank 2 Bank 3
Unimplemented data memory locations, read as ‘0’.
Note 1: Not a physical register.
2: PIC16F887 only.

 2006-2012 Microchip Technology Inc. DS41291G-page 27

PIC16F882/883/884/886/887
TABLE 2-1: PIC16F882/883/884/886/887 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0
Value on Value on all
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR other Resets

Bank 0
00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx
01h TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu
02h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 0000 0000
03h STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu(5)
04h FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu
05h PORTA(3) RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx xxxx 0000 0000
06h PORTB(3) RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 0000 0000
07h PORTC(3) RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx 0000 0000
08h PORTD(3,4) RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx 0000 0000
09h PORTE(3) — — — — RE3 RE2(4) RE1(4) RE0(4) ---- xxxx ---- 0000
0Ah PCLATH — — — Write Buffer for upper 5 bits of Program Counter ---0 0000 ---0 0000
0Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF(1) 0000 000x 0000 000u
0Ch PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 0000 0000
0Dh PIR2 OSFIF C2IF C1IF EEIF BCLIF ULPWUIF — CCP2IF 0000 00-0 0000 0000
0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
10h T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu
11h TMR2 Timer2 Module Register 0000 0000 0000 0000
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
14h SSPCON(2) WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
15h CCPR1L Capture/Compare/PWM Register 1 Low Byte (LSB) xxxx xxxx uuuu uuuu
16h CCPR1H Capture/Compare/PWM Register 1 High Byte (MSB) xxxx xxxx uuuu uuuu
17h CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 0000
19h TXREG EUSART Transmit Data Register 0000 0000 0000 0000
1Ah RCREG EUSART Receive Data Register 0000 0000 0000 0000
1Bh CCPR2L Capture/Compare/PWM Register 2 Low Byte (LSB) xxxx xxxx uuuu uuuu
1Ch CCPR2H Capture/Compare/PWM Register 2 High Byte (MSB) xxxx xxxx uuuu uuuu

1Dh CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 000
1Eh ADRESH A/D Result Register High Byte xxxx xxxx uuuu uuuu
1Fh ADCON0 ADCS1 ADCS0 CHS3 CHS2 CHS1 CHS0 GO/ ADON 0000 0000 00-0 0000
DONE
Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: MCLR and WDT Reset do not affect the previous value data latch. The RBIF bit will be cleared upon Reset but will set again if the
mismatch exists.
2: When SSPCON register bits SSPM<3:0> = 1001, any reads or writes to the SSPADD SFR address are accessed through the SSPMSK
register. See Registers 13-2 and 13-4 for more details.
3: Port pins with analog functions controlled by the ANSEL and ANSELH registers will read ‘0’ immediately after a Reset even though the data
latches are either undefined (POR) or unchanged (other Resets).
4: PIC16F884/PIC16F887 only.
5: See Table 14-5 for Reset value for specific condition.

DS41291G-page 28  2006-2012 Microchip Technology Inc.

 PIC16F882/883/884/886/887

TABLE 2-2: PIC16F882/883/884/886/887 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1

Value on Value on all
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR other Resets

Bank 1
80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx
81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
82h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 0000 0000
83h STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu(5)
84h FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu
85h TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111
86h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111
87h TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111
88h TRISD(3) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 1111 1111 1111 1111
89h TRISE — — — — TRISE3 TRISE2(3) TRISE1(3) TRISE0(3) ---- 1111 ---- 1111
8Ah PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF(1) 0000 000x 0000 000u
8Ch PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 0000 0000
8Dh PIE2 OSFIE C2IE C1IE EEIE BCLIE ULPWUIE — CCP2IE 0000 00-0 0000 0000
8Eh PCON — — ULPWUE SBOREN — — POR BOR --01 --qq --0u --uu(4,6)
8Fh OSCCON — IRCF2 IRCF1 IRCF0 OSTS HTS LTS SCS -110 q000 -110 q000
90h OSCTUNE — — — TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 ---u uuuu
91h SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000
92h PR2 Timer2 Period Register 1111 1111 1111 1111
93h SSPADD(2) Synchronous Serial Port (I2C mode) Address Register 0000 0000 0000 0000
93h SSPMSK(2) MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 1111 1111 1111 1111
94h SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000
95h WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 1111 1111 1111 1111
96h IOCB IOCB7 IOCB6 IOCB5 IOCB4 IOCB3 IOCB2 IOCB1 IOCB0 0000 0000 0000 0000
97h VRCON VREN VROE VRR VRSS VR3 VR2 VR1 VR0 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 -010
99h SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 0000 0000 0000 0000
9Ah SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 0000 0000 0000 0000
9Bh PWM1CON PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 0000 0000 0000 0000
9Ch ECCPAS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 0000 0000 0000 0000
9Dh PSTRCON — — — STRSYNC STRD STRC STRB STRA ---0 0001 ---0 0001
9Eh ADRESL A/D Result Register Low Byte xxxx xxxx uuuu uuuu
9Fh ADCON1 ADFM — VCFG1 VCFG0 — — — — 0-00 ---- 0-00 ----
Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: MCLR and WDT Reset do not affect the previous value data latch. The RBIF bit will be cleared upon Reset but will set again if the mismatch
exists.
2: Accessible only when SSPCON register bits SSPM<3:0> = 1001.
3: PIC16F884/PIC16F887 only.
4: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.
5: See Table 14-5 for Reset value for specific condition.
6: If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u.

 2006-2012 Microchip Technology Inc. DS41291G-page 29

PIC16F882/883/884/886/887
TABLE 2-3: PIC16F882/883/884/886/887 SPECIAL FUNCTION REGISTERS SUMMARY BANK 2
Value on Value on all
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR other Resets

Bank 2
100h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx
101h TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu
102h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 0000 0000
103h STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu(3)
104h FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu
105h WDTCON — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN ---0 1000 ---0 1000
106h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 0000 0000
107h CM1CON0 C1ON C1OUT C1OE C1POL — C1R C1CH1 C1CH0 0000 -000 0000 0-00
108h CM2CON0 C2ON C2OUT C2OE C2POL — C2R C2CH1 C2CH0 0000 -000 0000 0-00
109h CM2CON1 MC1OUT MC2OUT C1RSEL C2RSEL — — T1GSS C2SYNC 0000 --10 0000 0--0
10Ah PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
10Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF(1) 0000 000x 0000 000u
10Ch EEDAT EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 0000 0000 0000 0000

10Dh EEADR EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 0000 0000

10Eh EEDATH — — EEDATH5 EEDATH4 EEDATH3 EEDATH2 EEDATH1 EEDATH0 --00 0000 --00 0000
10Fh EEADRH — — — EEADRH4(2) EEADRH3 EEADRH2 EEADRH1 EEADRH0 ---- 0000 ---0 0000
Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: MCLR and WDT Reset does not affect the previous value data latch. The RBIF bit will be cleared upon Reset but will set again if the
mismatch exists.
2: PIC16F886/PIC16F887 only.
3: See Table 14-5 for Reset value for specific condition.

TABLE 2-4: PIC16F882/883/884/886/887 SPECIAL FUNCTION REGISTERS SUMMARY BANK 3

Value on Value on all
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR other Resets

Bank 3
180h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx
181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
182h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 0000 0000
183h STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu(3)
184h FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu
185h SRCON SR1 SR0 C1SEN C2REN PULSS PULSR — FVREN 0000 00-0 0000 00-0
186h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111
187h BAUDCTL ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0-00 01-0 0-00
188h ANSEL ANS7(2) ANS6(2) ANS5(2) ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111
189h ANSELH — — ANS13 ANS12 ANS11 ANS10 ANS9 ANS8 --11 1111 1111 1111
18Ah PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF(1) 0000 000x 0000 000u
18Ch EECON1 EEPGD — — — WRERR WREN WR RD x--- x000 ---- q000
18Dh EECON2 EEPROM Control Register 2 (not a physical register) ---- ---- ---- ----
Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: MCLR and WDT Reset does not affect the previous value data latch. The RBIF bit will be cleared upon Reset but will set again if the
mismatch exists.
2: PIC16F884/PIC16F887 only.
3: See Table 14-5 for Reset value for specific condition.

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 PIC16F882/883/884/886/887
2.2.2.1 STATUS Register For example, CLRF STATUS, will clear the upper three
bits and set the Z bit. This leaves the STATUS register
The STATUS register, shown in Register 2-1, contains:
as ‘000u u1uu’ (where u = unchanged).
• the arithmetic status of the ALU
It is recommended, therefore, that only BCF, BSF,
• the Reset status SWAPF and MOVWF instructions are used to alter the
• the bank select bits for data memory (GPR and STATUS register, because these instructions do not
SFR) affect any Status bits. For other instructions not affect-
The STATUS register can be the destination for any ing any Status bits, see Section 15.0 “Instruction Set
instruction, like any other register. If the STATUS Summary”
register is the destination for an instruction that affects Note 1: The C and DC bits operate as a Borrow
the Z, DC or C bits, then the write to these three bits is and Digit Borrow out bit, respectively, in
disabled. These bits are set or cleared according to the subtraction.
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.

REGISTER DEFINITIONS: STATUS

REGISTER 2-1: STATUS: STATUS REGISTER
R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
IRP RP1 RP0 TO PD Z DC(1) C(1)
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 IRP: Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h-1FFh)
0 = Bank 0, 1 (00h-FFh)
bit 6-5 RP<1:0>: Register Bank Select bits (used for direct addressing)
00 = Bank 0 (00h-7Fh)
01 = Bank 1 (80h-FFh)
10 = Bank 2 (100h-17Fh)
11 = Bank 3 (180h-1FFh)
bit 4 TO: Time-out bit
1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
bit 3 PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2 Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1 DC: Digit Carry/Borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)(1)
1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result
bit 0 C: Carry/Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred

Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second
operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the
source register.

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 PIC16F882/883/884/886/887
3.0 I/O PORTS The TRISA register (Register 3-2) controls the PORTA
pin output drivers, even when they are being used as
There are as many as thirty-five general purpose I/O analog inputs. The user should ensure the bits in the
pins available. Depending on which peripherals are TRISA register are maintained set when using them as
enabled, some or all of the pins may not be available as analog inputs. I/O pins configured as analog input
general purpose I/O. In general, when a peripheral is always read ‘0’.
enabled, the associated pin may not be used as a
Note: The ANSEL register must be initialized to
general purpose I/O pin.
configure an analog channel as a digital
input. Pins configured as analog inputs
3.1 PORTA and the TRISA Registers will read ‘0’.
PORTA is a 8-bit wide, bidirectional port. The
corresponding data direction register is TRISA EXAMPLE 3-1: INITIALIZING PORTA
(Register 3-2). Setting a TRISA bit (= 1) will make the BANKSEL PORTA ;
corresponding PORTA pin an input (i.e., disable the CLRF PORTA ;Init PORTA
output driver). Clearing a TRISA bit (= 0) will make the BANKSEL ANSEL ;
corresponding PORTA pin an output (i.e., enables CLRF ANSEL ;digital I/O
BANKSEL TRISA ;
output driver and puts the contents of the output latch
MOVLW 0Ch ;Set RA<3:2> as inputs
on the selected pin). Example 3-1 shows how to MOVWF TRISA ;and set RA<5:4,1:0>
initialize PORTA. ;as outputs
Reading the PORTA register (Register 3-1) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then
written to the PORT data latch.

REGISTER 3-1: PORTA: PORTA REGISTER

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 RA<7:0>: PORTA I/O Pin bit

1 = Port pin is > VIH
0 = Port pin is < VIL

REGISTER 3-2: TRISA: PORTA TRI-STATE REGISTER

R/W-1(1) R/W-1(1) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 TRISA<7:0>: PORTA Tri-State Control bit

1 = PORTA pin configured as an input (tri-stated)
0 = PORTA pin configured as an output

Note 1: TRISA<7:6> always reads ‘1’ in XT, HS and LP Oscillator modes.

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PIC16F882/883/884/886/887
3.2 Additional Pin Functions
RA0 also has an Ultra Low-Power Wake-up option. The
next three sections describe these functions.

3.2.1 ANSEL REGISTER

The ANSEL register (Register 3-3) is used to configure
the Input mode of an I/O pin to analog. Setting the
appropriate ANSEL bit high will cause all digital reads
on the pin to be read as ‘0’ and allow analog functions
on the pin to operate correctly.
The state of the ANSEL bits has no affect on digital out-
put functions. A pin with TRIS clear and ANSEL set will
still operate as a digital output, but the Input mode will
be analog. This can cause unexpected behavior when
executing read-modify-write instructions on the
affected port.

REGISTER 3-3: ANSEL: ANALOG SELECT REGISTER

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
ANS7(2) ANS6(2) ANS5(2) ANS4 ANS3 ANS2 ANS1 ANS0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 ANS<7:0>: Analog Select bits

Analog select between analog or digital function on pins AN<7:0>, respectively.
1 = Analog input. Pin is assigned as analog input(1).
0 = Digital I/O. Pin is assigned to port or special function.

Note 1: Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups, and
interrupt-on-change if available. The corresponding TRIS bit must be set to Input mode in order to allow
external control of the voltage on the pin.
2: Not implemented on PIC16F883/886.

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PIC16F882/883/884/886/887

REGISTER 3-4: ANSELH: ANALOG SELECT HIGH REGISTER

U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
— — ANS13 ANS12 ANS11 ANS10 ANS9 ANS8
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 ANS<13:8>: Analog Select bits
Analog select between analog or digital function on pins AN<13:8>, respectively.
1 = Analog input. Pin is assigned as analog input(1).
0 = Digital I/O. Pin is assigned to port or special function.

Note 1: Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups, and
interrupt-on-change if available. The corresponding TRIS bit must be set to Input mode in order to allow
external control of the voltage on the pin.

REGISTER 3-5: PORTB: PORTB REGISTER

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 RB<7:0>: PORTB I/O Pin bit

1 = Port pin is > VIH
0 = Port pin is < VIL

REGISTER 3-6: TRISB: PORTB TRI-STATE REGISTER

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 TRISB<7:0>: PORTB Tri-State Control bit

1 = PORTB pin configured as an input (tri-stated)
0 = PORTB pin configured as an output

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 PIC16F882/883/884/886/887
15.0 INSTRUCTION SET SUMMARY TABLE 15-1: OPCODE FIELD
DESCRIPTIONS
The PIC16F882/883/884/886/887 instruction set is
highly orthogonal and is comprised of three basic Field Description
categories: f Register file address (0x00 to 0x7F)
• Byte-oriented operations W Working register (accumulator)
• Bit-oriented operations b Bit address within an 8-bit file register
• Literal and control operations k Literal field, constant data or label
Each PIC16 instruction is a 14-bit word divided into an x Don’t care location (= 0 or 1).
opcode, which specifies the instruction type and one or The assembler will generate code with x = 0.
more operands, which further specify the operation of It is the recommended form of use for
the instruction. The formats for each of the categories compatibility with all Microchip software tools.
is presented in Figure 15-1, while the various opcode
d Destination select; d = 0: store result in W,
fields are summarized in Table 15-1.
d = 1: store result in file register f.
Table 15-2 lists the instructions recognized by the Default is d = 1.
MPASMTM assembler. PC Program Counter
For byte-oriented instructions, ‘f’ represents a file TO Time-out bit
register designator and ‘d’ represents a destination
designator. The file register designator specifies which
C Carry bit
file register is to be used by the instruction. DC Digit carry bit
The destination designator specifies where the result of Z Zero bit
the operation is to be placed. If ‘d’ is zero, the result is PD Power-down bit
placed in the W register. If ‘d’ is one, the result is placed
in the file register specified in the instruction. FIGURE 15-1: GENERAL FORMAT FOR
For bit-oriented instructions, ‘b’ represents a bit field INSTRUCTIONS
designator, which selects the bit affected by the
operation, while ‘f’ represents the address of the file in Byte-oriented file register operations
which the bit is located. 13 8 7 6 0
OPCODE d f (FILE #)
For literal and control operations, ‘k’ represents an
8-bit or 11-bit constant, or literal value. d = 0 for destination W
d = 1 for destination f
One instruction cycle consists of four oscillator periods; f = 7-bit file register address
for an oscillator frequency of 4 MHz, this gives a normal
instruction execution time of 1 s. All instructions are Bit-oriented file register operations
executed within a single instruction cycle, unless a 13 10 9 7 6 0
conditional test is true, or the program counter is OPCODE b (BIT #) f (FILE #)
changed as a result of an instruction. When this occurs,
the execution takes two instruction cycles, with the b = 3-bit bit address
second cycle executed as a NOP. f = 7-bit file register address

All instruction examples use the format ‘0xhh’ to

Literal and control operations
represent a hexadecimal number, where ‘h’ signifies a
hexadecimal digit. General
13 8 7 0
15.1 Read-Modify-Write Operations OPCODE k (literal)

Any instruction that specifies a file register as part of k = 8-bit immediate value
the instruction performs a Read-Modify-Write (RMW)
operation. The register is read, the data is modified, CALL and GOTO instructions only
and the result is stored according to either the instruc- 13 11 10 0
tion, or the destination designator ‘d’. A read operation OPCODE k (literal)
is performed on a register even if the instruction writes
to that register. k = 11-bit immediate value

For example, a CLRF PORTA instruction will read

PORTA, clear all the data bits, then write the result
back to PORTA. This example would have the unin-
tended consequence of clearing the condition that set
the RAIF flag.

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PIC16F882/883/884/886/887
TABLE 15-2: PIC16F882/883/884/886/887 INSTRUCTION SET
Mnemonic, 14-Bit Opcode Status
Description Cycles Notes
Operands MSb LSb Affected

BYTE-ORIENTED FILE REGISTER OPERATIONS

ADDWF f, d Add W and f 1 00 0111 dfff ffff C, DC, Z 1, 2
ANDWF f, d AND W with f 1 00 0101 dfff ffff Z 1, 2
CLRF f Clear f 1 00 0001 lfff ffff Z 2
CLRW – Clear W 1 00 0001 0xxx xxxx Z
COMF f, d Complement f 1 00 1001 dfff ffff Z 1, 2
DECF f, d Decrement f 1 00 0011 dfff ffff Z 1, 2
DECFSZ f, d Decrement f, Skip if 0 1(2) 00 1011 dfff ffff 1, 2, 3
INCF f, d Increment f 1 00 1010 dfff ffff Z 1, 2
INCFSZ f, d Increment f, Skip if 0 1(2) 00 1111 dfff ffff 1, 2, 3
IORWF f, d Inclusive OR W with f 1 00 0100 dfff ffff Z 1, 2
MOVF f, d Move f 1 00 1000 dfff ffff Z 1, 2
MOVWF f Move W to f 1 00 0000 lfff ffff
NOP – No Operation 1 00 0000 0xx0 0000
RLF f, d Rotate Left f through Carry 1 00 1101 dfff ffff C 1, 2
RRF f, d Rotate Right f through Carry 1 00 1100 dfff ffff C 1, 2
SUBWF f, d Subtract W from f 1 00 0010 dfff ffff C, DC, Z 1, 2
SWAPF f, d Swap nibbles in f 1 00 1110 dfff ffff 1, 2
XORWF f, d Exclusive OR W with f 1 00 0110 dfff ffff Z 1, 2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF f, b Bit Clear f 1 01 00bb bfff ffff 1, 2
BSF f, b Bit Set f 1 01 01bb bfff ffff 1, 2
BTFSC f, b Bit Test f, Skip if Clear 1 (2) 01 10bb bfff ffff 3
BTFSS f, b Bit Test f, Skip if Set 1 (2) 01 11bb bfff ffff 3
LITERAL AND CONTROL OPERATIONS
ADDLW k Add literal and W 1 11 111x kkkk kkkk C, DC, Z
ANDLW k AND literal with W 1 11 1001 kkkk kkkk Z
CALL k Call Subroutine 2 10 0kkk kkkk kkkk
CLRWDT – Clear Watchdog Timer 1 00 0000 0110 0100 TO, PD
GOTO k Go to address 2 10 1kkk kkkk kkkk
IORLW k Inclusive OR literal with W 1 11 1000 kkkk kkkk Z
MOVLW k Move literal to W 1 11 00xx kkkk kkkk
RETFIE – Return from interrupt 2 00 0000 0000 1001
RETLW k Return with literal in W 2 11 01xx kkkk kkkk
RETURN – Return from Subroutine 2 00 0000 0000 1000
SLEEP – Go into Standby mode 1 00 0000 0110 0011 TO, PD
SUBLW k Subtract W from literal 1 11 110x kkkk kkkk C, DC, Z
XORLW k Exclusive OR literal with W 1 11 1010 kkkk kkkk Z
Note 1: When an I/O register is modified as a function of itself (e.g., MOVF GPIO, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external
device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if
assigned to the Timer0 module.
3: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.

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 PIC16F882/883/884/886/887
9.0 ANALOG-TO-DIGITAL
CONVERTER (ADC) MODULE
The Analog-to-Digital Converter (ADC) allows
conversion of an analog input signal to a 10-bit binary
representation of that signal. This device uses analog
inputs, which are multiplexed into a single sample and
hold circuit. The output of the sample and hold is
connected to the input of the converter. The converter
generates a 10-bit binary result via successive
approximation and stores the conversion result into the
ADC result registers (ADRESL and ADRESH).
The ADC voltage reference is software selectable to be
either internally generated or externally supplied.
The ADC can generate an interrupt upon completion of
a conversion. This interrupt can be used to wake-up the
device from Sleep.
Figure 9-1 shows the block diagram of the ADC.

FIGURE 9-1: ADC BLOCK DIAGRAM

VCFG1 = 0
AVSS
VREF- VCFG1 = 1
AVDD
VCFG0 = 0

VREF+ VCFG0 = 1

AN0 0000
AN1 0001
AN2 0010
AN3 0011
AN4 0100
AN5 0101
AN6 0110
AN7 0111
ADC
AN8 1000
GO/DONE 10
AN9 1001
AN10 1010
0 = Left Justify
ADFM
AN11 1011 1 = Right Justify
AN12 1100 ADON 10
AN13 1101
VSS ADRESH ADRESL
CVREF 1110
FixedRef 1111

CHS<3:0>

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PIC16F882/883/884/886/887
9.1 ADC Configuration 9.1.3 ADC VOLTAGE REFERENCE
When configuring and using the ADC the following The VCFG bits of the ADCON1 register provide
functions must be considered: independent control of the positive and negative
voltage references. The positive voltage reference can
• Port configuration be either VDD or an external voltage source. Likewise,
• Channel selection the negative voltage reference can be either VSS or an
• ADC voltage reference selection external voltage source.
• ADC conversion clock source
9.1.4 CONVERSION CLOCK
• Interrupt control
• Results formatting The source of the conversion clock is software select-
able via the ADCS bits of the ADCON0 register. There
9.1.1 PORT CONFIGURATION are four possible clock options:
The ADC can be used to convert both analog and digital • FOSC/2
signals. When converting analog signals, the I/O pin • FOSC/8
should be configured for analog by setting the associated • FOSC/32
TRIS and ANSEL bits. See the corresponding Port • FRC (dedicated internal oscillator)
section for more information.
The time to complete one bit conversion is defined as
Note: Analog voltages on any pin that is defined TAD. One full 10-bit conversion requires 11 TAD periods
as a digital input may cause the input buf- as shown in Figure 9-2.
fer to conduct excess current.
For correct conversion, the appropriate TAD specification
must be met. See A/D conversion requirements in
9.1.2 CHANNEL SELECTION
Section 17.0 “Electrical Specifications” for more
The CHS bits of the ADCON0 register determine which information. Table 9-1 gives examples of appropriate
channel is connected to the sample and hold circuit. ADC clock selections.
When changing channels, a delay is required before Note: Unless using the FRC, any changes in the
starting the next conversion. Refer to Section 9.2 system clock frequency will change the
“ADC Operation” for more information. ADC clock frequency, which may
adversely affect the ADC result.

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 PIC16F882/883/884/886/887
TABLE 9-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES (VDD > 3.0V)
ADC Clock Period (TAD) Device Frequency (FOSC)

ADC Clock Source ADCS<1:0> 20 MHz 8 MHz 4 MHz 1 MHz

(2) (2) (2)
FOSC/2 00 100 ns 250 ns 500 ns 2.0 s
(2) (2)
FOSC/8 01 400 ns 1.0 s 2.0 s 8.0 s(3)
(3)
FOSC/32 10 1.6 s 4.0 s 8.0 s 32.0 s(3)
FRC 11 2-6 s(1,4) 2-6 s(1,4) 2-6 s(1,4) 2-6 s(1,4)
Legend: Shaded cells are outside of recommended range.
Note 1: The FRC source has a typical TAD time of 4 s for VDD > 3.0V.
2: These values violate the minimum required TAD time.
3: For faster conversion times, the selection of another clock source is recommended.
4: When the device frequency is greater than 1 MHz, the FRC clock source is only recommended if the
conversion will be performed during Sleep.

FIGURE 9-2: ANALOG-TO-DIGITAL CONVERSION TAD CYCLES

TCY to TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11
b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Conversion Starts
Holding Capacitor is Disconnected from Analog Input (typically 100 ns)

Set GO/DONE bit

ADRESH and ADRESL registers are loaded,
GO bit is cleared,
ADIF bit is set,
Holding capacitor is connected to analog input

9.1.5 INTERRUPTS
The ADC module allows for the ability to generate an
interrupt upon completion of an Analog-to-Digital
conversion. The ADC interrupt flag is the ADIF bit in the
PIR1 register. The ADC interrupt enable is the ADIE bit
in the PIE1 register. The ADIF bit must be cleared in
software.
Note: The ADIF bit is set at the completion of
every conversion, regardless of whether
or not the ADC interrupt is enabled.
This interrupt can be generated while the device is
operating or while in Sleep. If the device is in Sleep, the
interrupt will wake-up the device. Upon waking from
Sleep, the next instruction following the SLEEP
instruction is always executed. If the user is attempting
to wake-up from Sleep and resume in-line code
execution, the global interrupt must be disabled. If the
global interrupt is enabled, execution will switch to the
Interrupt Service Routine.
Please see Section 14.3 “Interrupts” for more
information.

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PIC16F882/883/884/886/887
9.1.6 RESULT FORMATTING
The 10-bit A/D conversion result can be supplied in two
formats, left justified or right justified. The ADFM bit of
the ADCON0 register controls the output format.
Figure 9-3 shows the two output formats.

FIGURE 9-3: 10-BIT A/D CONVERSION RESULT FORMAT

ADRESH ADRESL
(ADFM = 0) MSB LSB
bit 7 bit 0 bit 7 bit 0

10-bit A/D Result Unimplemented: Read as ‘0’

(ADFM = 1) MSB LSB

bit 7 bit 0 bit 7 bit 0

Unimplemented: Read as ‘0’ 10-bit A/D Result

9.2 ADC Operation 9.2.4 ADC OPERATION DURING SLEEP

The ADC module can operate during Sleep. This
9.2.1 STARTING A CONVERSION requires the ADC clock source to be set to the FRC
To enable the ADC module, the ADON bit of the option. When the FRC clock source is selected, the
ADCON0 register must be set to a ‘1’. Setting the GO/ ADC waits one additional instruction before starting the
DONE bit of the ADCON0 register to a ‘1’ will start the conversion. This allows the SLEEP instruction to be
Analog-to-Digital conversion. executed, which can reduce system noise during the
conversion. If the ADC interrupt is enabled, the device
Note: The GO/DONE bit should not be set in the
will wake-up from Sleep when the conversion
same instruction that turns on the ADC.
completes. If the ADC interrupt is disabled, the ADC
Refer to Section 9.2.6 “A/D Conversion
module is turned off after the conversion completes,
Procedure”.
although the ADON bit remains set.
9.2.2 COMPLETION OF A CONVERSION When the ADC clock source is something other than
FRC, a SLEEP instruction causes the present conver-
When the conversion is complete, the ADC module will: sion to be aborted and the ADC module is turned off,
• Clear the GO/DONE bit although the ADON bit remains set.
• Set the ADIF flag bit
9.2.5 SPECIAL EVENT TRIGGER
• Update the ADRESH:ADRESL registers with new
conversion result The ECCP Special Event Trigger allows periodic ADC
measurements without software intervention. When
9.2.3 TERMINATING A CONVERSION this trigger occurs, the GO/DONE bit is set by hardware
If a conversion must be terminated before completion, and the Timer1 counter resets to zero.
the GO/DONE bit can be cleared in software. The Using the Special Event Trigger does not assure
ADRESH:ADRESL registers will not be updated with proper ADC timing. It is the user’s responsibility to
the partially complete Analog-to-Digital conversion ensure that the ADC timing requirements are met.
sample. Instead, the ADRESH:ADRESL register pair See Section 11.0 “Capture/Compare/PWM Modules
will retain the value of the previous conversion. Addi- (CCP1 and CCP2)” for more information.
tionally, a 2 TAD delay is required before another acqui-
sition can be initiated. Following this delay, an input
acquisition is automatically started on the selected
channel.
Note: A device Reset forces all registers to their
Reset state. Thus, the ADC module is
turned off and any pending conversion is
terminated.

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