A Novel Variable-Gain Amplifier Based on an FGMOS

Transistor
Sherif M. Sharroush, Dept. of Electrical Engineering, Fac. of Engineering, Port Said, Port Said Univ., Egypt.
EM: [email protected]

Abstract— In radio-frequency receivers, variable-gain am- switching digital signals [7]. In the second type of VGAs, the
plifiers (VGAs) are often used in order to compensate for the gain is varied in a continuous manner and thus is known as
change of the signal level during the channel transmission and an analog controlled VGA.
to relax the constraints on the succeeding analog-to-digital con-
verter (ADC). In this paper, a novel VGA is introduced using a
floating-gate MOS transistor (FGMOS). The voltage gain, the
Assuming a common-source NMOS amplifier with a re-
linearity, the valid region for proper operation, and the sensitiv- sistive load, the gain is equal to Av = -gm(RD//ro), where gm,
ity are discussed and quantitative expressions are derived for RD, and ro are the transistor's transconductance, the load re-
them. The performance of this amplifier is verified by simula- sistance, and the output resistance of the amplifying device,
tion adopting the 45 nm CMOS technology with VDD = 1 V. respectively. So, the gain of the analog controlled VGA can
be varied by one of three methods; varying the transconduct-
Index Terms—CMOS technology, floating-gate transistor, var- ance, varying the load, or using a tunable feedback element.
iable-gain amplifier. The transconductance of the amplifier can be varied by either
using a properly tunable current source or using source de-
I. INTRODUCTION generation with a voltage-controlled resistor connected to the
D ue to the need to process the data in the digital domain
in receivers, an analog-to-digital converter (ADC)
needs to be used. However, due to process, voltage, and tem-
source terminal [3 and 4]. The main advantage of this type is
its broad gain and large dynamic range.
perature (PVT) variations, the gain of the low-noise amplifi- The second method of varying the gain of the analog
er varies, thus the signal level delivered to the ADC varies controlled VGA is by tuning its load [5]. In this case, varying
accordingly. This necessitates using an ADC with a relative- the control voltage switches the mode of operation of the
ly large dynamic range, which is very expensive and difficult active load between saturation and triode, thus changing its
to design. As an alternative, an automatic-gain control equivalent resistance and accordingly changing the gain. The
(AGC) circuit can be used in order to vary the gain of the main disadvantage of this type is the need to stack several
receiver and thus relaxing the ADC requirements [1]. If the devices and a resistive load, hence the maximum allowable
gain of the VGA varies in inverse proportion to the ampli- voltage swing is limited in low-voltage applications. The
tude of the incoming signal, the signals with very small am- third and last method of varying the gain is using a voltage-
plitudes will be amplified by a relatively large gain and those controlled feedback resistor as shown in Fig. 1 (a). The main
with very large amplitudes will be attenuated through the advantage of this circuit is that the voltage gain has a linear
VGA. We can thus safely say that the VGA widens the dy- relationship with the control voltage. However, due to the
namic range of the receiver [2]. feedback path, the input resistance is much smaller than that
of the conventional common-source amplifier, thus loading
In this paper, a short survey of the VGAs is presented the driver stage and significantly lowering its gain.
along with a novel VGA that depends on using an FGMOS
transistor. The remainder of this paper is organized as fol- VDD

lows: Section II presents a short survey of the VGAs. The VC

proposed VGA is presented in Section III and analyzed in input gates
RD V1 V2 Vn
Section IV. The simulation results are presented in Section C1 C2 Cn
floating gate

V. Finally, the paper is concluded in Section VI. RF v out Drain Source

II. PREVIOUS WORK v in

n n
There are many technologies that can be adopted to real-
ize VGAs like bipolar, BiCMOS, and CMOS technologies [3
- 5]. Due to its ease of integration and lower cost, CMOS
(a) (b)
technology are widely used. Depending on the manner by Fig. 1 (a) A feedback-tunable VGA [1]. VC is the control voltage. (b) The
which the gain of the VGA is varied, CMOS VGAs can be basic structure of an N-channel FGMOS transistor with n–input gates [8].
classified into two types. The gain of the first type is varied
in a discrete manner in which proper binary weighted resis- III. THE PROPOSED VARIABLE-GAIN AMPLIFIER
tors (or capacitors) are used to control the gain [6]. This type The proposed VGA depends on the FGMOS transistor,
is aptly named a digitally controlled VGA or a programma- the basic structure of which is introduced first. Refer to Fig.
ble gain amplifier (PGA). Obviously, in order to enhance the 1 (b) for the basic structure of the N-channel multiple-input
precision (or reduce the step by which the gain is varied), a FGMOS (MIFGMOS) transistor with n input voltages, V1,
relatively large number of resistors (or capacitors) must be V2, …., and Vn. As illustrated, it has two types for the gate;
used. This certainly presents an area overhead especially if the floating gate and the control gates [8]. The floating gate
the dynamic range is wide. In addition, this type introduces is capacitively coupled to the multiple-input gates. The drain
glitches into the circuit when the gain is varied using fast- current of the N-channel MIFGMOS transistor in the satura-
978-1-5090-5306-3/16/$31.00 ©2016 IEEE
tion region can be expressed as [8] IV. ANALYSIS
The proposed VGA is analyzed quantitatively in this
1 ' W  , (1) section from four aspects; the first one is the determination
k n   [k1 (V1 − Vs ) + k 2 (V2 − Vs ) + ...... + k n (Vn − Vs ) − Vthn ] (1 + λn vDS )
2
iD =
2  L n of the valid region for proper region of operation, then the
where ki is the input-capacitive coupling ratio and is given by large-signal and the small-signal analyses are performed in
[8] order to derive the expressions for the voltage gain in terms
of the control voltage and the restriction of small-signal ap-
Ci proximation. Finally, the sensitivity of the voltage gain with
ki = , (2) respect to the control voltage is discussed.
n

C
i =1
i + CGS
A. Valid Region of Operation
where kn’ is the process-transconductance parameter, (W/L)n In order for the FGMOS transistor to operate properly as
is the aspect ratio, V1, V2, …, and Vn are the voltages of the a VGA, it must be biased in the saturation region. So, the
control gates, Vs is the source voltage, Vthn is the threshold following two conditions must be satisfied: vGS ≥ Vthn and vDS
voltage, λn is the channel-length modulation effect parameter, ≥ vGS - Vthn. Substituting by vGS results in
Ci’s are the input capacitances between the floating gate and
each of the ith input, CGS is the floating gate-to-source capac- k1vin + k2VC ≥ Vthn . (5)
itance of the transistor, and vDS is the drain-to-source voltage.
So,
It is obvious that the FGMOS transistor lends itself for
application as a variable-gain amplifier. For illustration, refer Vthn − k2VC
to Fig. 2 (a) for a conceptual circuit containing an FGMOS
vin ≥ . (6)
k1
transistor and a resistive load. The load can of course be an
active PMOS device. VC is the control voltage. Obviously, The corresponding region is shown shaded in Fig. 3 (a)
changing VC causes the drain current to accordingly change in the VC – vin plane. It is apparent from this figure that in-
(refer to Eq. (3)), thus varying the voltage drop across the creasing the control voltage relaxes the requirement on the
resistive load and varying the output voltage, vout. Since the dc level of vin required to turn on the FGMOS transistor. This
output voltage, vout, varies with VC, a variable-gain amplifier seems intuitively right as the voltage, vGS, controlling the
is obtained. The drain current is given by conduction of the FGMOS transistor is contributed by both
VC and vin. Stated another way, the dc biasing can be shared
between the two gate terminals of the FGMOS transistor,
1 ' W 
k n   [k1vin + k 2VC − Vthn ] (1 + λn vDS ) , (3)
2
iD = thus relaxing the constraint on the lower limit of VC and thus
2  L n allowing a wide range for the variable gain. Now, if vGS is
where saturation-region operation is assumed. Thus, the cor- substituted into the inequality of vDS for saturation-region
responding output voltage, vout, is operation, we get

vout = VDD − iD RD = VDD −

1 ' W 
k n RD   [k1vin + k 2VC − Vthn ] (1 + λn v DS )
2 . (4) vout ≥ k1vin + k2VC − Vthn . (7)
2  L n
The corresponding region is shown shaded in the vin –
This indicates that the gain can be changed via the con-
vout plane in Fig. 3 (b). It can be deduced from Fig. 3 (b) that
trol voltage, VC. To gain more insight into the operation of
reducing either k1, k2, or VC decreases the minimum permis-
the proposed VGA, it is analyzed quantitatively in the next
sible value of vout so that M still operates in the saturation
section. The version of the proposed VGA in the differential
region. The upper limit is, of course, dictated by VDD. The
form with active load is shown in Fig. 2 (b). In this case, the
result is that reducing any of the previously mentioned pa-
biasing current source can be implemented by a saturation-
rameters causes the maximum allowable voltage swing at the
region operated MOS transistor biased by VB. The input dif-
amplifier output to increase.
ferential voltage, vid, is the difference between vin1 and vin2.

VDD VDD
v in
VDD
Vthn saturation and
triode regions
RD k1
- v out +

vout v in1 v in2

v in VC VC cutoff region

VC VB Vthn V
C
k2
(a) (b) (a)
Fig. 2 (a) The conceptual circuit illustrating the proposed VGA. (b) The
proposed FGMOS-based VGA in the differential form with active load.
 v out The input voltage is assumed to have a zero dc average
value. The dc average value of vout can be found after deter-
mining the region of operation of M. Now, if the input volt-
saturation region
age is increased further, the output voltage continues to de-
crease, thus causing M to operate in the deep-triode region.
slope = k 1 Specifically, if vDS is much smaller than 2(vGS - Vthn), then the
term 0.5vDS2 can be safely neglected in the triode-region
k2VC - Vthn triode region equation resulting in

W 
vin iD ≈ k n'   [(k1vin + k 2VC − Vthn )v DS ] . (13)
(b)  L n
Fig. 3 (a) The region over which the FGMOS transistor is turned on is The FGMOS transistor in this case can be represented
shown shaded in the VC – vin plane. (b) The region over which the FGMOS by a resistor whose resistance is given by
transistor operates in the saturation region is shown shaded in the vin – vout
plane.
v DS 1 . (14)
RDS = =
B. Large-Signal Analysis iD W 
k n'   (k1vin + k 2VC − Vthn )
In order to gain more insight into the operation of the  L n
proposed VGA and find an expression for the gain of this This resistor appears in series with the resistive load, RD,
amplifier in terms of VC, the resistive load, RD, and the tran- resulting in an output voltage that can be found from voltage
sistor's parameters, we will perform a large-signal analysis. division as (after substituting RDS from Eq. (14))
When vGS is smaller than Vthn, then M will operate in the cut-
off region indicating that iD is equal to zero and thus vout is VDD . (15)
constant at VDD. The voltage gain, Av, is obviously zero in vout =
 
W
this region. Now, if vGS is increased above Vthn, M will oper- 1 + k n' RD   (k1vin + k 2VC − Vthn )
ate in the saturation region as long as vout ≥ k1vin + k2Vc – Vthn.  L n
The input-output relationship in the saturation region is The voltage gain in the deep-triode region is thus

1 ' W  (8) W 
vout = VDD − iD RD = VDD − k n RD   [k1vin + k 2VC − Vthn ] (1 + λn v DS )
2 − V DD k1 k n'   R D . (16)
2  L n  L n
Av = 2
where k1 and k2 are given by k1 = C1/(C1 + C2 + CGS) and k2 =  ' W  
C2/(C1 + C2 + CGS), respectively. C1, C2, and CGS are the in- 1 + k n   (k 1 v in + k 2VC − Vthn )R D 
  L n 
put capacitance between the floating gate and the input ter-
minal, the input capacitance between the floating gate and C. Small-Signal Analysis
the control terminal, and the floating gate-to-source capaci- Proceeding in the same way as in the conventional
tance of the transistor, respectively. If Eq. (8) is differentiat- MOSFET common-source amplifier, the total drain current,
ed with respect to vin to obtain the expression of the voltage iD, is the sum of two components; a pure dc component, ID,
gain, Av, we will obtain and a pure ac component, id. So,
. (9) i D = I D + id . (17)
1 W 
[
Av = − k n' RD   (k1vin + k 2VC − Vthn ) λn Av + 2k1 (k1vin + k 2VC − Vthn )(1 + λn vout )
2
2
]
 L n
Also, let the input voltage contain a pure dc component,
After simple mathematical manipulations, we obtain
Vdc, and a pure ac component (the small signal to be ampli-
fied), vgs. Substituting by vin into Eq. (3) for the FGMOS
W 
k1 k n' RD   (k1vin + k 2VC − Vthn )(1 + λ n vout ) . (10) drain current in the saturation region results in
 L n
Av = −
 1 ' W  2
1 + k n RD λ n   (k1vin + k 2VC − Vthn )  1 ' W 
 2  L  n  I D + id =
2  L n
[
k n   k1 (Vdc + vgs ) + k 2VC − Vthn ,
2
(18) ]
It is obvious from Eq. (8) that vout decreases with the in-
crease in vin. This continues until vout is reduced below k1vin + where λn is assumed to be zero for simplicity. The effect of λn
k2VC – Vthn, then M enters the triode region. The correspond- can be taken into account by the parallel combination of ro
ing input-output relationship is and the load resistance. After simple mathematical manipula-
tions, we obtain the dc and ac components of the drain cur-
W   1 2 . (11) rent as
vout = VDD − k n' RD   (k1vin + k 2VC − Vthn )vout − vout 
 n 
L 2
1 ' W 
Differentiating Eq. (11) with respect to vin yields the ex- kn   [k1Vdc + k2VC − Vthn ] (19)
2
ID =
pression for the voltage gain, Av, in the triode region as 2  L n
and
' W 
− k k RD   vout
1 n . (12)
 L n
Av =
 W  W   id =
1 ' W  2 2
[
kn   k1 vgs + 2k1vgs (k1Vdc + k2VC − Vthn ) , ] (20)
1 + k n RD   (k1vin + k 2VC − Vthn ) − k n RD   vout  2  L n
' '

  L n  L n 
respectively. If the component, k12vgs2, is much smaller than VC below this value causes the output power-supply clipping
2k1vgs(k1Vdc + k2VC - Vthn), then id can be written as and increasing it above this value causes operation in the
triode region with a relatively small transconductance.
W 
[ ]
id = k1k n'   (k1Vdc + k2VC − Vthn )vgs . (21) The voltage gain versus the control voltage.
 L n 2.5
This approximation is nothing but the small-signal ap-

The voltage gain.

2
proximation of the FGMOS transistor. It corresponds to the
condition 1.5

 k V  1
vgs << 2Vdc + 2 VC − thn  . (22)
 k 1 k1 
0.5
This means that the nonlinearity of the amplifier along
with the total harmonic distortion increases with increasing 0
0.8 1 1.2 1.4 1.6 1.8 2
k1. So, reducing k1 enhances the linearity of this amplifier. The control voltage in Volts.
This is also obvious from Eq. (20) as reducing k1 makes the Fig. 4 The plot of Av versus VC adopting an active load.
second-order term, k12vgs2, negligible with respect to the line-
ar term. Of course, this amplifier can be linearized also by VI. CONCLUSIONS
source degeneration with the associated gain reduction. Now, In this paper, a variable-gain amplifier using an FGMOS
since the small-signal drain current is simply the product of transistor was presented. This amplifier was analyzed quanti-
the transconductance, gm, and the small-signal voltage, vgs, tatively and its operation was verified by simulation using
then from Eq. (21), we get the 45 nm CMOS technology. It was found that reducing
either the control voltage or the input-capacitive coupling
ratios causes the maximum allowable voltage swing at the
W 
g m = k1k n'   (k1Vdc + k 2VC − Vthn ) . (23) amplifier output to increase. However, it was also found that
 L n both the linearity and the gain can be enhanced simultane-
This indicates that enhancing the linearity by reducing k1 ously by decreasing and increasing the input capacitive-
results in gain degradation; a well-known tradeoff. However, coupling ratios of the input terminal and of the control termi-
this degradation can be compensated for by increasing k2. nal, respectively. The sensitivity can be enhanced by increas-
That is, both the linearity and the gain can be enhanced sim- ing one or both of the coupling coefficients.
ultaneously by decreasing and increasing the input capaci-
tive-coupling ratios of the input terminal and of the control VII. REFERENCES
terminal, respectively. From Eq. (2), this can be achieved by [1] G. Wu, A Broadband Variable-Gain Amplifier and a Broadband Self-
Calibrated High-Sensitivity Power Detector for the Square Kilometre
reducing C1 and increasing C2. Obviously, the transconduct- Array, Doctor of Philosophy Thesis, University of Calgary, Calgary,
ance and hence the gain can be varied by changing VC. Alberto, Nov. 2014.
[2] J. W. Kwon and S. T. Ryu, “An inherently dB-linear all-CMOS
D. VGA Sensitivity variable gain amplifier,” Journal of Semiconductor Technology and
The sensitivity gives an indication of how easily the Science, Vol. 11, No. 4, Dec. 2011.
voltage gain is varied or controlled by the control voltage, [3] Q. H. Duong, L. Quan, and S. G. Lee, “An all CMOS 84 dB-linear
low-power variable gain amplifier,” Symposium on VLSI Circuits,
VC. The sensitivity of the proposed VGA is expressed here Pages: 114 – 117, Jun. 2005.
by the first derivative of the voltage gain with respect to VC [4] W. Hu, S. Song, B. Choi, and J. W. Kim, “Design of a 1.8 V high
in V-1. Returning to Eq. (10) for the voltage gain in the satu- frequency CMOS variable gain amplifier with a novel dB-linear gain
ration region, we obtain the following expression for the structure,” The 47th Midwest Symposium on Circuits and Systems,
sensitivity, S: Vol. 1, Pages: I - 125–8 Vol.1, 25 – 28 Jul. 2004.
[5] Z. Li, F. Guo, D. Chen, H. Li, and Z. Wang, “A wideband CMOS
variable gain amplifier with a novel linear-in-dB gain control
∂Av W  structure,” IEEE International Workshop on Radio-Frequency
S= ∂VC = −k1k 2 k n'   RD , (24) Integration Technology, Rasa Sentosa Resort, Pages: 337 – 340, 9 -11
 L n Dec. 2007.
where λn was neglected. Intuitively, the VGA can be made [6] T. Kumar, K. Ma, and K. S. Yeo, “Temperature-compensated db-
more sensitive by increasing one or both of the coupling co- linear digitally controlled variable gain amplifier with DC offset
cancellation,” IEEE Transactions on Microwave Theory and
efficients. Techniques, Vol. 61, Issue: 1, Pages: 2648 – 2661, Jul. 2013.
[7] H. D. Lee, K. A. Lee, and S. Hong, “A wideband CMOS variable gain
V. SIMULATION RESULTS amplifier with an exponential gain control,” IEEE Transactions on
The proposed VGA is simulated adopting an active Microwave Theory and Techniques, Vol. 55, Issue: 6, Pages: 1363 –
1373, Jun. 2007.
PMOS load for the 45 nm CMOS technology with VDD = 1
[8] S. Vlassis and S. Siskos, “Differential-voltage attenuator based on
V. Refer to Fig. 4 for the plot of the voltage gain versus the floating-gate MOS transistors and its applications,” IEEE Transactions
control voltage. The gain shows a linear relationship with VC on Circuits and Systems I: Fundamental Theory and Applications, Vol:
in the range from 0.9 V to 1.3 V. However, the gain shows a 48, Issue: 11, Pages: 1372 – 1378, 6 Aug. 2002.
maximum value at VC = 1.4 V due to the fact that decreasing