sensors

Article
A 45 nm Stacked CMOS Image Sensor Process
Technology for Submicron Pixel †
Seiji Takahashi *, Yi-Min Huang, Jhy-Jyi Sze, Tung-Ting Wu, Fu-Sheng Guo, Wei-Cheng Hsu,
Tung-Hsiung Tseng, King Liao, Chin-Chia Kuo, Tzu-Hsiang Chen, Wei-Chieh Chiang,
Chun-Hao Chuang, Keng-Yu Chou, Chi-Hsien Chung, Kuo-Yu Chou, Chien-Hsien Tseng,
Chuan-Joung Wang and Dun-Nien Yaung
Taiwan Semiconductor Manufacturing Company, No. 8, Li-Hsin Rd. 6, Hsinchu Science Park,
Hsinchu 300, Taiwan; [email protected] (Y.-M.H.); [email protected] (J.-J.S.); [email protected] (T.-T.W.);
[email protected] (F.-S.G.); [email protected] (W.-C.H.); [email protected] (T.-H.T.); [email protected] (K.L.);
[email protected] (C.-C.K.); [email protected] (T.-H.C.); [email protected] (W.-C.C.);
[email protected] (C.-H.C.); [email protected] (K.-Y.C.); [email protected] (C.-H.C.);
[email protected] (K.-Y.C.); [email protected] (C.-H.T.); [email protected] (C.-J.W.);
[email protected] (D.-N.Y.)
* Correspondence: [email protected]; Tel.: +886-3-563-6688 (ext. 723-5765)
† This paper is an expanded version of our published paper: Takahashi, S.; Huang, Y.-M.; Sze, J.-J.; Wu, T.-T.;
Guo, F.-S.; Hsu, W.-C.; Tseng, T-H.; Liao, K.; Kuo, C.-C.; Chen, T.-H.; et al. Low Dark Current and Low Noise
0.9 µm Pixel in a 45 nm Stacked CMOS Image Sensor Process Technology. In Proceedings of the 2017
International Image Sensor Workshop, Hiroshima, Japan, 30 May–2 June 2017.

Received: 16 October 2017; Accepted: 28 November 2017; Published: 5 December 2017

Abstract: A submicron pixel’s light and dark performance were studied by experiment and simulation.
An advanced node technology incorporated with a stacked CMOS image sensor (CIS) is promising in
that it may enhance performance. In this work, we demonstrated a low dark current of 3.2 e− /s at
60 ◦ C, an ultra-low read noise of 0.90 e− ·rms, a high full well capacity (FWC) of 4100 e− , and blooming
of 0.5% in 0.9 µm pixels with a pixel supply voltage of 2.8 V. In addition, the simulation study result
of 0.8 µm pixels is discussed.

Keywords: submicron pixel; image sensor; stacked CMOS image sensor; dark current; read noise;
random telegraph noise; full well capacity; optical crosstalk

1. Introduction
Scaling down pixel size is absolutely necessary for high resolution imaging and quanta image
sensors [1]. Recently, dual camera applications have become a major trend in the smartphone market [2],
in which a small pixel size image sensor can be used as be a high resolution image sensor for the
purpose of producing a zoomed image. In addition, phase detection auto focus function has developed.
Among various pixel types of the function, dual photodiode phase detection auto focus also needs
equivalently small pixel size [3].
However, sensor performances of the small pixel are generally inferior to those of previous
generations with larger pixel sizes [4]. Major challenges in submicron pixel generation are shown
in Figure 1. A small pixel does not have enough space for a large source follower device and a
large photodiode. This induces higher source follower noise and a smaller fill factor. These in turn
influence the dynamic range and the signal-to-noise ratio (SNR). Additionally, the required implant
dosage is higher for smaller pixels, and a higher implant dosage will induce higher dark currents and
white pixels due to ion implant damage. Moreover, crosstalk is significant due to a small pixel pitch.
These two problems significantly affect image quality.

Sensors 2017, 17, 2816; doi:10.3390/s17122816 www.mdpi.com/journal/sensors

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Backside illumination technology has been developed and has enabled drastic S/N improvement
[5,6]. Backside
Stacked CMOS illuminationimage technology
sensor (CIS)has chipsbeenenable a more and
developed flexible
has manufacturing
enabled drastic process
S/N
dedicated
improvement to image
[5,6]. sensors
Stacked[7].CMOSFurthermore, an advanced
image sensor (CIS) chipsnode technology
enable [8] withmanufacturing
a more flexible a stacked CIS
might
processboost the light
dedicated to imagesignal, reduce
sensors [7]. noise, and control
Furthermore, the process
an advanced variation caused
node technology [8] withbya stacked
critical
dimension
CIS might boost fluctuations
the light and mask
signal, overlay
reduce errors,
noise, which are
and control more serious
the process variation in caused
submicron pixel
by critical
Sensors 2017, 17, 2816 2 of 13
generation.
dimension fluctuations and mask overlay errors, which are more serious in submicron pixel generation.
In
In this
this paper,
paper,
Backside aaillumination
silicon
silicon result
result of
of 0.9
technology0.9 µm
µm pixels
pixels
has been with
with well-balanced
developed and has enabledlight
well-balanced light and
drastic S/Ndark
and dark performance,
performance,
improvement
making
making full[5,6].use
full use of
ofaahighly
Stacked CMOSmanufacturable
highly manufacturable
image sensor (CIS) 45
45nmnmadvanced
chips enable a technology
advanced flexiblewith
technology
more with aastacked
stacked CMOS
manufacturing process image
CMOS image
sensor [9], and
dedicated 0.8 µm
to pixel
image simulation
sensors
sensor [9], and 0.8 µm pixel simulation [7]. data are
Furthermore, presented.
an advanced node technology [8] with a stacked CIS
might boost the light signal, reduce noise, and control the process variation caused by critical
dimension fluctuations and mask overlay errors, which are more serious in submicron pixel
generation.
In this paper, a silicon result of 0.9 µm pixels with well-balanced light and dark performance,
making full use of a highly manufacturable 45 nm advanced technology with a stacked CMOS image
sensor [9], and 0.8 µm pixel simulation data are presented.

Figure
Figure 1.
1. Challenges
Challengesin insubmicron
submicronpixelpixelgeneration.
generation.(a)(a)Top
Top view
view of
of pixel
pixel layout
layout highlights
highlights thethe small
small
size source follower; (b) top view of pixel layout indicating the small fill factor; (c) cross-sectional
size source follower; (b) top view of pixel layout indicating the small fill factor; (c) cross-sectional view
view of pixel
of pixel depicting
depicting high
high ion ion implant
implant damage damage
induced induced
by by the
the view
high high dose photodiode;
dose (d) cross-
Figure 1. Challenges in submicron pixel generation. (a) Top of pixelphotodiode; (d) the
layout highlights cross-sectional
small
sectional view
view of pixel
size of pixel
showing
source showing
high(b)
follower; high
optical
top optical
of pixelcrosstalk.
crosstalk.
view layout indicating the small fill factor; (c) cross-sectional
view of pixel depicting high ion implant damage induced by the high dose photodiode; (d) cross-
2.
2. A
A45
45nm
nmStacked CMOS
sectional view
Stacked CMOS Image
of pixel Sensor
showing
Image high optical crosstalk.
Sensor
The
The2.test
A 45
test chip
nmarchitecture
chip Stacked CMOS
architecture is
is an
an 8-mega-pixel
Image Sensor
8-mega-pixel (3296(H)
(3296(H) ××2512(V))
2512(V))rawrawdata
dataoutput
outputCIS CIStest
testvehicle.
vehicle.
The block diagram
The block diagram of the vehicle
of architecture
The test chip the vehicle is illustrated
is anis 8-mega-pixelin Figure
illustrated (3296(H) 2.
in Figure The image
2. The
× 2512(V))
sensor
raw image
consists
sensor
data output
of two
consists
CIS test
silicon
vehicle.of two
layers.
siliconTheThetop
block
layers. wafer
The comprises
diagram
top wafer a pixelis array
of the vehicle
comprises and in
illustrated
a pixel the bottom
Figure
array wafer
2. The
and theimagecomprises
sensor
bottom a read
consists
wafer ofout
twocircuit.
comprises silicon
a readSince
out
acircuit.
stackedSince
CIS chip
layers. The has
top a small
wafer camera
comprises a module
pixel array and
and a
theflexible
bottom design,
wafer a column
comprises a level
read
a stacked CIS chip has a small camera module and a flexible design, a column level out bonding
circuit. Sincestacked
CIS a stacked was
architecture CIS chip has a small camera module and a flexible design, a column level bonding stacked
bonding stacked CIS adopted.
architecture was adopted.
CIS architecture was adopted.

Figure 2. Block diagram of 45 nm stacked CIS test vehicle.

Figure 2. Block diagram of 45 nm stacked CIS test vehicle.
Figure 2. Block diagram of 45 nm stacked CIS test vehicle.
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There are two possibilities in terms of pixel device placement in a stacked CIS chip. One is to
place There
it on aare
CIStwo possibilities
wafer, in terms
and the other is to of pixel
place device
it on placement
a logic in a 1stacked
wafer. Table CIS chip.
summarizes One and
the pros is to
place it on a CIS wafer, and the other is to place it on a logic wafer. Table 1 summarizes
cons of these two choices. Pixel devices on a CIS wafer lead to a highly flexible pixel device process the pros and
cons
but of these
a lower fulltwo choices.
well Pixel
capacity devices
(FWC) due on
to aa CIS
lower wafer lead toOn
fill factor. a highly flexible
the other hand,pixel
pixeldevice
devicesprocess
on a
but a lower full well capacity (FWC) due to a lower fill factor. On the other hand, pixel
logic wafer lead to a higher FWC and have a simple pixel structure, consisting only of a transfer gate devices on a
and a photodiode, but they have a lower conversion gain, which leads to higher noise, since gate
logic wafer lead to a higher FWC and have a simple pixel structure, consisting only of a transfer the
and a photodiode,
wiring between thebut theywafer
logic have aand
lower
theconversion
CIS wafergain,has which
some leads to higher
parasitic noise, since
capacitance, andthe wiring
it is not
between the logic wafer and the CIS wafer has some parasitic capacitance, and it is not negligible.
negligible.

Prosand
Table1.1.Pros
Table andcons
consof
oftwo
twodifferent
differentmethods
methodsof
ofpixel
pixeldevice
deviceplacement.
placement.

Choice
Choice PROS
PROS CONS
CONS
High
High conversion
conversion gaingain
Pixeldevices
Pixel devicesonon
CISCIS wafer
wafer Low fill factor
Low fill factor
Dedicated
Dedicated pixel
pixel device
device process
process
High
High fill fill factor
factor
Pixeldevices
Pixel devicesonon logic
logic wafer
wafer Low
Low conversion gain
conversion gain
Dedicated
Dedicatedphotodiode
photodiode process
process

Taking
Takinginto
intoaccount
accountthetheoverall
overallpixel
pixelperformance,
performance,all allpixel
pixeldevices
deviceswere
wereplaced
placedononaaCIS
CISwafer,
wafer,
as
as shown in Figure 3. Since pixel devices were kept on a CIS wafer, advanced 45 nm technologywas
shown in Figure 3. Since pixel devices were kept on a CIS wafer, advanced 45 nm technology was
desired
desiredininterms
termsofofits
itslow
lownoise
noiseand
andhigh
highfill
fillfactor.
factor.The
Thepixel architecture
pixel adopted
architecture adopteda 2a×22×shared 4-
2 shared
transistor without row-select, and the pixel unit cell size was 0.90
4-transistor without row-select, and the pixel unit cell size was 0.90 µm. µm.

Figure 3. A unit pixel circuit and device partition.

Figure 3. A unit pixel circuit and device partition.

The processed CIS wafer was bonded with a logic wafer, followed by backside illumination
The
process processed
including thinCIS wafer
down, was bondedcoating,
anti-reflection with a alogic
colorwafer, followed
filter, and by backside
a micro-lens illumination
array process [10].
process including thin down, anti-reflection coating, a color filter, and a micro-lens array process [10].
3. Experimental Result
3. Experimental Result
3.1. Low Noise Source Follower Device
3.1. Low Noise Source Follower Device
An input referred noise in a conventional CIS is represented as follows [11]:
An input referred noise in a conventional CIS is represented as follows [11]:
s


V circuit + V source f ollower
2 (1)
N input re f erred = N pixel 2 + ∙ (1)
Av·CG
∝ N trap density (2)
V source f ollower ∝ ∙ ∙ (2)
Cox ·W · L
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where N pixel, V circuit, and V source follower represent the noise generated at the pixel and the noise
where N pixel, V circuit, and V source follower represent the noise generated at the pixel and the noise
voltage generated in the circuit and source follower, respectively, Av is the circuit gain, CG is the
voltage generated in the circuit and source follower, respectively, Av is the circuit gain, CG is the
conversion gain, Cox is the source follower gate capacitance, W is the source follower device width,
conversion gain, Cox is the source follower gate capacitance, W is the source follower device width,
L is the source follower device length, and N trap density is the trap state density.
L is the source follower device length, and N trap density is the trap state density.
It is clear from Equation (1) that increasing conversion gain is essential for reducing noise. A 45
It is clear from Equation (1) that increasing conversion gain is essential for reducing noise. A 45 nm
nm design is beneficial for high conversion gain because the design rules are tighter than those of
design is beneficial for high conversion gain because the design rules are tighter than those of previous
previous 65 nm node technology. The silicon result showed a conversion gain of 0.90 µm pixels
65 nm node technology. The silicon result showed a conversion gain of 0.90 µm pixels reaching as high
reaching as high as 120 µV/e−.
as 120 µV/e− .
After making an effort to reduce circuit noise, the signal chain noise was almost equivalent to
After making an effort to reduce circuit noise, the signal chain noise was almost equivalent to
the source follower flicker noise in the pixel array block, which was proportional to trap density and
the source follower flicker noise in the pixel array block, which was proportional to trap density and
inversely proportional to gate capacitance, transistor width, and length.
inversely proportional to gate capacitance, transistor width, and length.
Lithography capability is a key process element in this submicron pixel development. A 193 nm
Lithography capability is a key process element in this submicron pixel development. A 193 nm
ArF immersion lithography was used for critical layers; as a result, the fill factor of 0.90 µm pixel
ArF immersion lithography was used for critical layers; as a result, the fill factor of 0.90 µm pixel
increased by 20% with respect to the 65 nm technology. With the tightened design rules, the source
increased by 20% with respect to the 65 nm technology. With the tightened design rules, the source
follower device gate area can be maximized in a given small area in order to decrease random noise
follower device gate area can be maximized in a given small area in order to decrease random noise
and random telegraph noise (RTN) [12]. The scaling of gate oxide thickness is also effective for
and random telegraph noise (RTN) [12]. The scaling of gate oxide thickness is also effective for random
random noise reduction [13].
noise reduction [13].
Traps influencing the source follower noise exist in the gate insulator, at the silicon interface,
Traps influencing the source follower noise exist in the gate insulator, at the silicon interface,
and in bulk, as shown in Figure 4. Thanks to the dedicated CIS wafer process, related processes, for
and in bulk, as shown in Figure 4. Thanks to the dedicated CIS wafer process, related processes,
instance, minimizing etching damage, eliminating dangling bonds, and device channel engineering,
for instance, minimizing etching damage, eliminating dangling bonds, and device channel engineering,
have been fully optimized [14].
have been fully optimized [14].

Figure 4.
Figure 4. Defects
Defects that
that influence
influence the
thesource
sourcefollower
followerdevice
devicenoise.
noise.

As a result, one of the key performance indexes, read noise, was reduced to 0.90 e−·rms at an
As a result, one of the key performance indexes, read noise, was reduced to 0.90 e− ·rms at
analog gain of 18 dB, as shown in Figure 5, where the gray color indicates a 1.1 µm pixel with W = 0.2
an analog gain of 18 dB, as shown in Figure 5, where the gray color indicates a 1.1 µm pixel with
µm and L = 0.8 µm, and the black color indicates a 0.9 µm pixel with W = 0.2 µm and L = 0.6 µm.
W = 0.2 µm and L = 0.8 µm, and the black color indicates a 0.9 µm pixel with W = 0.2 µm and L = 0.6 µm.
Random telegraph noise, which contributes to the tail part of the distribution, also improved in spite
Random telegraph noise, which contributes to the tail part of the distribution, also improved in spite
of the smaller source follower device.
of the smaller source follower device.
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Figure 5.Statistical
Statistical readnoise
noise distributionsof
of the0.9
0.9 µmpixel
pixel andthe
the 1.1µm
µm pixelat
at ananalog
analog gain
Figure
Figure5.5. Statistical read
read noisedistributions
distributions ofthe µm pixeland
the 0.9µm and the1.1
1.1 µmpixel
pixel atan
an analoggain
gain
of 18dB.
of dB.
of1818 dB.

3.2. Low Dark Current Pixel

3.2.
3.2. Low
Low Dark
Dark Current
Current Pixel
Pixel
Another process integration challenge in the submicron pixel is the dark current reduction.
Another
Another process
process integration
integration challenge
challenge in thethe submicron
submicron pixel is the the dark
dark current
current reduction.
reduction.
Unlike logic transistors, an image sensor basically follows a constant voltage scaling law [15]. In the
Unlike
Unlike logic
logictransistors,
transistors, an
animage
imagesensor
sensorbasically
basicallyfollows
follows aaconstant
constantvoltage
voltagescaling
scalinglawlaw[15].
[15]. In
In the
the
constant voltage scaling law, let K be a scaling factor which is greater than 1, doping concentration is
constant
constant voltage
voltage scaling law, let K be aa scaling
scaling factor
factorwhich
whichisisgreater
greaterthan
than1,1,doping
dopingconcentration
concentrationis
proportional to K squared, and electric field is proportional to K. Figure 6 shows the necessary
proportional
is proportionaltotoK Ksquared,
squared,and
andelectric
electricfield
fieldisis proportional
proportional to K. Figure 6 shows
to K. shows the the necessary
necessary
photodiode doping concentration. As expected, a smaller pixel requires a higher photodiode dosage,
photodiodedoping
photodiode dopingconcentration.
concentration. As
As expected,
expected, aa smaller
smaller pixel
pixel requires
requires aa higher
higher photodiode
photodiode dosage,
dosage,
and a higher ion implant dosage induces more higher ion implant damage in bulk silicon, in addition
andaahigher
and higherion
ion implant
implantdosage
dosageinduces
inducesmore
morehigher
higherionionimplant
implantdamage
damagein inbulk
bulksilicon,
silicon,inin addition
addition
to a higher electric field.
toaahigher
to higherelectric
electricfield.
field.
Dark current and white pixels are functions of defect density and electric field, so reducing these
Darkcurrent
Dark currentand
andwhite
whitepixels
pixelsare
arefunctions
functionsof ofdefect
defectdensity
densityand
andelectric
electricfield,
field,so
so reducing
reducingthese
these
is fundamental.
isisfundamental.
fundamental.

Figure 6. Pixel generation vs. the photodiode implant dose.

Figure6.6.Pixel
Figure Pixelgeneration
generationvs.
vs. the
the photodiode
photodiode implant
implantdose.
dose.

It is well known that defect located at the transfer gate edge is a main source of dark current and
It is well known that defect located at the transfer gate edge is a main source of dark current and
white pixels
It is well (Figure
known 7) [16].
that Concerning
defect located atdefect densitygate
the transfer reduction,
edge is key process
a main conditions
source such asand
of dark current ion
white pixels (Figure 7) [16]. Concerning defect density reduction, key process conditions such as ion
implantation
white and annealing
pixels (Figure steps were defect
7) [16]. Concerning carefully optimized
density to minimize
reduction, every
key process kind of defect
conditions and
such as to
ion
implantation and annealing steps were carefully optimized to minimize every kind of defect and to
recover damages.
implantation and annealing steps were carefully optimized to minimize every kind of defect and to
recover damages.
recover damages.
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Figure7.7.Dark
Figure Darkcurrent
currentsources
sourcesmarked
markedbyby“X”
“X”and
andpixel
pixelbiases.
biases.
Figure 7. Dark current sources marked by “X” and pixel biases.
3.3. Pixel Design and Low Dark Current Pixel
3.3.
3.3. Pixel
Pixel Design
Design and
and Low
Low Dark
Dark Current
Current Pixel
Pixel
The electric field is decreased by device engineering. Reducing floating diffusion node bias (Vfd)
The
Thetoelectric
electric field is decreased by device engineering. Reducing floating diffusion node bias
bias (Vfd)
works reducefield
darkiscurrent
decreased
dueby todevice
electricengineering. Reducing
field relaxation. floating
However, thisdiffusion
degrades node (Vfd)
anti-blooming
works
works to
to reduce
reduce dark
dark current
current due
due to
to electric
electric field
field relaxation.
relaxation. However,
However, this
this degrades
degrades anti-blooming
anti-blooming
due to a lower overflow potential [17,18]. Therefore, a new pixel structure was developed.
due
due to aa lower
toAn lower overflow
overflow potential
potential [17,18]. Therefore, aanew
newpixel structure was
wasdeveloped.
additional N-type layer [17,18]. Therefore,between
was interposed pixel structure
a shallow photodiodedeveloped.
(PD) and a deep
An additional N-type layer was interposed between a shallow photodiode (PD) aand a
photodiode, which also extended to the floating diffusion region (Figure 8). The (PD)
An additional N-type layer was interposed between a shallow photodiode anddiffusion
floating deep
deep photodiode,
photodiode, which which
alsoalso extended
extended to the
to the floating
floating diffusion
diffusion region (Figure8).
region 8).The
The floating
floating diffusion
node bias can be decreased by increasing the additional N-type(Figure
layer dosage, diffusion
and anti-blooming
node
node bias
bias can
can be
be decreased
decreased by
by increasing
increasing the
the additional
additional N-type
N-type layer
layer dosage,
dosage, and
and anti-blooming
anti-blooming
performance is not affected.
performance
performance is is not
not affected.
affected.

Figure 8. Schematic drawing of pixel design concept.

Figure 8. Schematic drawing of pixel design concept.
Figure 8. Schematic drawing of pixel design concept.
This additional n-type layer is adequate to improve image lag as well. Thanks to the larger image
This
lag This additional
margin, n-typealayer
by utilizing deepisisadequate
silicon to improve
area chargeimage
as improve lag as
storage, thewell. Thanks
pinning to the (Vpin)
voltage larger image
of the
lag additional
margin, by n-type
utilizing a layer
deep adequate
silicon area to
as charge image
storage, lag
the as well.
pinning Thanks
voltage to the larger
(Vpin) of the
photodiode
image
can be
lag margin,
decreased deep
bydecreased
whilesilicon
utilizing awhile
the same
areaFWC
FWC is maintained,
as charge
as shown
storage, theaspinning
in Figure
voltage (Vpin)
9. of
Lower
the
photodiode can
pinning voltage be
also works while
to reduce the same
dark FWC
current. is maintained, shown in Figure 9. Lower
photodiode can be
pinning voltage decreased
also works to thedark
reduce samecurrent. is maintained, as shown in Figure 9. Lower pinning
voltage also works to reduce dark current.
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Figure
Figure9.9.9.Photodiode potential
potentialprofile.
Photodiodepotential profile.Dashed
Dashedline is based
line on on
control pixel, andand
solid lineline
is based on
Figure Photodiode profile. Dashed line isisbased
based control
on control pixel,
pixel, solid
and solid line isisbased
based
the pixel in this experiment.
ononthe
thepixel
pixelininthis
thisexperiment.
experiment.

As
Asshown
As shownin Figure
ininFigure10,
Figure it is
10,
10, ititevident from
isisevident
evident the three-dimensional
from
from technology
thethree-dimensional
the three-dimensional computer
technology
technology aided design
computer
computer aided
aided
(TCAD)
design device device
design(TCAD)
(TCAD) simulation results results
devicesimulation
simulation that an that
resultsanti-blooming path was
thatanananti-blooming
anti-blooming clearly
path
path wasmade,
was and
clearly
clearly charge
made,
made, transfer
and
and charge
charge
capability
transfer improved
transfercapability
capability as well. asaswell.
improved
improved well.

Figure10.
Figure
Figure 10.3D
10. 3DTCAD
TCAD
3D TCAD simulations
simulations ofofthe
simulations the transfer
oftransfer devicestructure
device
the transfer structure
device showingshowing
showing
structure electrostatic
electrostatic potential
potential
electrostatic
contours.contours.
potential
contours. (a)(a)The
Thecontrol
control
(a) The pixel during
control
pixel pixel
during the
the integration
during phase;(b)
the integration
integration phase; (b) thepixel
phase;
the pixel
(b) ininthis
the thisexperiment
pixel experiment
in during
this experiment
during
theintegration
during
the integration phase;(c)(c)
the integration
phase; thecontrol
phase;
the control
(c) the pixel
control
pixel during
duringpixelthe
the readout
during
read out phase;
thephase;
read (d) (d)the
out thepixel
phase;pixel ininthe
(d) this
this experiment
pixel in this
experiment
duringthe
experiment
during theread
readout
duringout phase.
the read out phase.
phase.

AAhistogram
A histogramof
histogram ofofthetheindividual
the individualpixel
individual pixeldark
pixel darkcurrent
dark currentat
current atat60
60°C
60 ◦ °C
Cisisisshown
shownin
shown ininFigure
Figure11.
Figure 11.The
11. Thedark
The darkcurrent
dark current
current
peak
peak atat
6060°C
◦°C corresponds
corresponds toto 3.2
3.2 e −e−/s for the 0.9 µm pixel, and the dark current distribution of the 0.9
peak at 60 C corresponds to 3.2 e /s for the 0.9 µm pixel, and the dark current distribution of 0.9
/s
− for the 0.9 µm pixel, and the dark current distribution of the the
µm
µm pixel
pixel isis close
close toto that
that ofof the
the 1.1
1.1 µmµm pixel
pixel inin spite
spite ofof
thethe higher
higher photodiode
photodiode
0.9 µm pixel is close to that of the 1.1 µm pixel in spite of the higher photodiode dose. dose.
dose.
Sensors 2017, 17, 2816 8 of 13
Sensors 2017, 17, 2816 8 of 13
Sensors 2017, 17, 2816 8 of 13

Figure 11. Dark current histograms at 60 °C of the 0.9 µm pixel and the 1.1 µm pixel. The gray color
Figure 11.Dark
Figure11. Darkcurrent histogramsatat6060◦ C
currenthistograms °Cofofthe
the0.9 µmpixel
0.9µm pixeland
andthe
the1.1 µmpixel.
1.1µm pixel.The
Thegray
graycolor
color
indicates the 1.1 µm pixel, and the black color indicates the 0.9 µm pixel.
indicates
indicatesthe
the1.1 µmpixel,
1.1µm pixel,and
andthe
theblack
blackcolor
colorindicates
indicatesthe
the0.9 µm
0.9 µmpixel.
pixel.

3.4. Anti-Blooming Pixel

3.4.Anti-Blooming
3.4. Anti-BloomingPixelPixel
Figure 12 shows a light response curve of 0.9 µm pixels. The green color is the green channel,
Figure1212shows
Figure showsa alight
lightresponse
responsecurve
curveofof0.9
0.9µmµmpixels.
pixels.The
Thegreen
greencolor
colorisisthe
thegreen
greenchannel,
channel,
and red is the red channel, and blue is the blue channel. As the TCAD device simulation results show,
and red is the red channel, and blue is the blue channel. As the TCAD device simulation
and red is the red channel, and blue is the blue channel. As the TCAD device simulation results show, results show,
even after the green channel signal saturated, the adjacent channels, the red and blue signals, were
evenafter
even after the
the green channel
channel signal
signalsaturated,
saturated,thetheadjacent channels,
adjacent thethe
channels, redred
andandblueblue
signals, were
signals,
not distorted. From this fact we can conclude that blooming was 0.5% [19]. This data also shows a
not distorted.
were FromFrom
not distorted. this fact
thiswe
factcan
weconclude
can that blooming
conclude that was 0.5%
blooming was [19].
0.5%This
[19].data also
This shows
data also a
measured linear FWC of 4100 e−−. −
measured
shows linear FWC
a measured linearofFWC
4100 of
e .4100 e .

Figure 12. Light response curve of the 0.9 µm pixel.

Figure 12. Light response curve of the 0.9 µm pixel.
Figure 12. Light response curve of the 0.9 µm pixel.
3.5. Low Crosstalk Pixel
3.5. Low Crosstalk Pixel
3.5. Low Crosstalk Pixel
Optical crosstalk improvement is mandatory in submicron small pixels [20], so we developed
Optical crosstalk improvement is mandatory in submicron small pixels [20], so we developed
optical stack
Optical thinningimprovement
crosstalk and cross talkissuppression
mandatory in techniques.
submicron Figure
small13 shows
pixels a cross-sectional
[20], so we developedview
optical stack thinning and cross talk suppression techniques. Figure 13 shows a cross-sectional view
of thestack
optical pixelthinning
in the backside portion.
and cross The opticaltechniques.
talk suppression stack height, defined
Figure by the
13 shows distance between
a cross-sectional viewthe
of the pixel in the backside portion. The optical stack height, defined by the distance between the
ofbackside
the pixelsilicon
in thesurface
backsideand the top The
portion. of the microstack
optical lens, height,
decreased by 10%.
defined by Deep trench isolation
the distance between (DTI)
the
backside silicon surface and the top of the micro lens, decreased by 10%. Deep trench isolation (DTI)
technology was developed to suppress optical crosstalk without sacrificing dark performance in
technology was developed to suppress optical crosstalk without sacrificing dark performance in
parallel. In addition, a new color filter material was used to improve the SNR10 index.
parallel. In addition, a new color filter material was used to improve the SNR10 index.
Sensors 2017, 17, 2816 9 of 13

backside silicon surface and the top of the micro lens, decreased by 10%. Deep trench isolation
(DTI) technology was developed to suppress optical crosstalk without sacrificing dark performance
Sensors 2017, 17,
in parallel.
Sensors 2017, 17, 2816
In2816
addition, a new color filter material was used to improve the SNR10 index. 99 of
of 13
13

Figure13.
Figure
Figure 13. Schematiccross-sectional
13.Schematic
Schematic cross-sectionalviews
cross-sectional viewsof
views ofpixel.
of pixel.(a)
pixel. (a)Control
(a) Controlpixel;
Control pixel;(b)
pixel; (b)crosstalk-improved
(b) crosstalk-improved pixel.
crosstalk-improved pixel.

In
In order
Inorder totodesign
orderto design
design anan
an optical
optical structure,
structure,
optical structure,wewe
we performed
performed aa three-dimensional
performed three-dimensional
a three-dimensional finitefinite
finite difference
difference time
time
difference
domain
domain optical
optical
time domain simulation.
simulation.
optical BasedBased
Based
simulation. on the
on theonoptical
optical simulation,
simulation,
the optical aa deep
simulation, deep trench
trench
a deep isolation
isolation
trench structure
structure
isolation and
and
structure
material,
material, as
as well
well as
as the
the curvature
curvature of
of the
the micro-lens,
micro-lens, were
were determined.
determined. Figure
Figure
and material, as well as the curvature of the micro-lens, were determined. Figure 14 shows 14
14 shows
shows the
the optical
optical
simulation
simulation results.
the opticalresults.
simulationThe simulation
The simulationThe
results. result
result of the
of the improved
simulation improved pixel
result of pixel exhibits greater
exhibits
the improved greater light-gathering
light-gathering
pixel exhibits greater
capability.
capability.
light-gathering capability.

Figure 14.
Figure 14. Optical
14. Optical simulation
Opticalsimulation results
simulation atat
results
results at anan
an incident wavelength
incident
incident of 530
wavelength
wavelength of 530530
of nm.nm.
nm. (a) Control
(a) Control pixel;
(a) Control (b)
pixel;
pixel; (b)
crosstalk-improved
(b) pixel.
crosstalk-improved
crosstalk-improved pixel.pixel.

Taking
Taking into account
Taking into
into account the
account the optical
the optical simulation
optical simulation study
simulation study results,
study results, we
results, we made
we made aaa silicon
made silicon sample.
silicon sample. Obtained
sample. Obtained
Obtained
quantum
quantum efficiency (QE) spectra of the 0.9 µm pixels are shown in Figure 15. Optical
quantum efficiency (QE) spectra of the 0.9 µm pixels are shown in Figure 15. Optical crosstalk was
efficiency (QE) spectra of the 0.9 µm pixels are shown in Figure 15. Optical crosstalk
crosstalk was
was
greatly
greatly suppressed,
suppressed,and
greatly suppressed, and the
andthe blue
theblue
blue
and and
and red
redred responses
responses
responses slightly
slightly
slightly decreased
decreased
decreased due
due todue to a slightly
to a slightly
a slightly smaller
smaller
smaller aperture
aperture
aperture area
area
area of the of structure.
of
grid the grid
the grid structure.
structure.
Improving Improving
Improving the
the greenthe green channel’s
green
channel’s channel’s
quantum quantum
quantum
efficiencyefficiency
efficiency is realized
is
is realized realized by
by
by a newly
a newly
adevelopeddeveloped
newly developed color
color
color filter filter material.
filter material.
material.
Sensors 2017, 17, 2816 10 of 13
Sensors 2017, 17, 2816 10 of 13

Sensors 2017, 17, 2816 10 of 13

Figure 15. Measured quantum efficiency spectra of 0.9 µm pixels. Dashed line is the control 0.9 µm
Figure 15. Measured quantum efficiency spectra of 0.9 µm pixels. Dashed line is the control 0.9 µm pixel,
pixel, and the solid line is the improved 0.9 µm pixel.
and the solid
Figure 15.line is the improved
Measured 0.9 µm pixel.
quantum efficiency spectra of 0.9 µm pixels. Dashed line is the control 0.9 µm
pixel, and the solid line is the improved 0.9 µm pixel.
A sample color image taken with the 0.9 µm pixel in the 45 nm stacked CIS process technology
A sample color image taken with the 0.9 µm pixel in the 45 nm stacked CIS process technology
is shownAinsample
Figure 16. There was nowith
dead theline, norpixel
any in
defects,45 so
nmthis process is robust. Table 2 gives
is shown in Figurecolor 16. image
Theretaken
was no dead 0.9 µm
line, nor any the
defects, stacked
so CIS process
this process technology
is robust. Table 2
a summary
is shownofin pixel
Figureperformance. The
16. There was no process
dead technology
line, nor consists
any defects, in 45 nm
so this process 1-polyTable
is robust. 4-metal (1P4M)
2 gives
gives a summary of pixel performance. The process technology consists in 45 nm 1-poly 4-metal
stacked CIS. The
a summary of pixel supply voltage
pixel performance. Thewas 2.8 technology
process V. Image lag was in
consists less
45than 1 e. Photo
nm 1-poly 4-metalresponse
(1P4M) non-
(1P4M) stacked CIS. The pixel supply voltage was 2.8 V. Image lag was less than 1 e. Photo response
uniformity
stacked was
CIS. 0.90%, and
The pixel the QE
supply at thewas
voltage green peak
2.8 V. waslag
Image 71%.
was less than 1 e. Photo response non-
non-uniformity
uniformity waswas0.90%,
0.90%, and
and thethe
QEQE at the
at the green green
peakpeak was 71%.
was 71%.

Figure 16. A sample color image taken with the 0.9 µm pixel manufactured in the 45 nm stacked CIS.
Figure 16. A
Figure 16. A sample
sample color
color image
image taken
taken with
with the
the 0.9 µm pixel
0.9 µm pixel manufactured
manufacturedin
in the
the45
45nm
nm stacked
stacked CIS.
CIS.
Table 2. Sensor characteristics of the 0.9 µm pixel.
Table2.2. Sensor
Table Sensorcharacteristics
characteristicsof ofthe
the0.9 µmpixel.
0.9µm pixel.
Process Technology 45 nm 1P4M Stacked CIS
Process Technology
Pixel
Process size
Technology 45 1P4M
45 nm nm0.901P4M µm Stacked
Stacked CIS CIS
PixelPixel
supply
size voltage 2.80.90
V µm
Pixel size 0.90 µm
PixelConversion
supply
Pixel gain
supply voltage
voltage 120
2.8 VµV/e
−
2.8 V
Dark current at
Conversion 60 °C
gain 3.2 e /s
120 µV/e −
−
Conversion gain
at 60 ◦ Cof >200 e−/s at 60 °C
120 µV/e−
e− /s
White pixel countsDarkwithcurrent
dark current 3.2679 ppm −
Dark
White pixel counts current
with at 60 °C
dark current − ◦ 3.2 e /s
Read noise at 18 ofdB>200 e /s at 60 C 679 ppm
0.90 − e−·rms
White pixel counts with Read noise at
dark current 18 dB 0.90 e · rms
capacity of >200 e /s at 60 °C 679−ppm
−
Full
Full well
well capacity 41004100e− e −
Read noise
Bloomingat
Blooming
18 dB 0.5% e ·rms
0.90
0.5%
Full well capacity
Image lag
Image lag <1 <1e−4100
e− e−
Photo response
Blooming
Photo response non-uniformity
non-uniformity 0.9%0.9%0.5%
Quantum efficiency at green peak 71%
Quantum efficiency
Image lagat green peak 71%<1 e−
Photo response non-uniformity 0.9%
Quantum efficiency at green peak 71%
Sensors 2017, 17, 2816 11 of 13
Sensors 2017, 17, 2816 11 of 13

4. 0.8 µm Pixel Generation

4. 0.8 μm Pixel Generation
The 0.9 µm pixel performance met market requirements, so we then decided to study 0.8 µm
The 0.9 µm pixel performance met market requirements, so we then decided to study 0.8 µm
pixel generation. Assuming a 0.8 µm pixel uses a similar pixel structure and architecture, we estimated
pixel generation. Assuming a 0.8 µm pixel uses a similar pixel structure and architecture, we
the performance by simulation and calculation.
estimated the performance by simulation and calculation.
First, we considered pixel noise and pixel RTN. Regarding RTN, source follower channel length is
First, we considered pixel noise and pixel RTN. Regarding RTN, source follower channel length
a key factor, and the length should be greater than 0.5 µm to efficiently suppress RTN [14]. Our pixel
is a key factor, and the length should be greater than 0.5 µm to efficiently suppress RTN [14]. Our
layout study confirmed that a more advanced node technology can provide a source follower device
pixel layout study confirmed that a more advanced node technology can provide a source follower
with a channel length greater than 0.5 µm in 0.8 µm pixels.
device with a channel length greater than 0.5 µm in 0.8 µm pixels.
The optical cross-talk problem can be improved by deepening the DTI. In addition, a further
The optical cross-talk problem can be improved by deepening the DTI. In addition, a further
thinning down of the optical stack height is still effective.
thinning down of the optical stack height is still effective.
The most serious problem is still a low FWC. If the pixel size shrinks down from 0.9 to 0.8 µm based
The most serious problem is still a low FWC. If the pixel size shrinks down from 0.9 to 0.8 µm
on the same process technology, FWC will be about 2800 e− , and photon noise will limit the image
based on the same process technology, FWC will be about 2800 e−, and photon noise will limit the
quality [21]. To maintain a reasonable image quality, the FWC needs at least 3000 e− . A simplified
image quality [21]. To maintain a reasonable image quality, the FWC needs at least 3000 e−. A
form of FWC can be expressed as
simplified form of FWC can be expressed as
Z
FWC∝∝
FWC ∙ V pd(z) − Vov f )dz
Cpd(z)·( (3)
(3)

where
where zz isisthe
thesilicon
silicondepth,
depth,Cpd(z)
Cpd(z) and
andVpd(z)
Vpd(z) areare
thethe
photodiode
photodiodecapacitance at a at
capacitance silicon depth
a silicon of z
depth
and
of z the
anddepleted photodiode
the depleted potential
photodiode at a silicon
potential at a depth
siliconofdepth
z, respectively, and Vovfand
of z, respectively, is the overflow
Vovf is the
potential.
overflow potential.
Vovf
Vovf isis determined
determined to to fulfill anti-blooming
anti-blooming criterion
criterion and cannot be changed.
changed. Cpd(z)
Cpd(z) can
can be
be
increased
increased by by tightening
tightening thethe pixel-to-pixel
pixel-to-pixel isolation
isolation design
design rule.
rule. The
The simulated
simulated FWC
FWC withwith aa tighter
tighter
design
design rule
rule then increases from 2800 to 3500 e−−, ,rendering
then increases renderingthe thequality
qualityof
ofan
animage
imagepossibly
possiblyacceptable.
acceptable.
Comparisons
Comparisons between 0.9 0.9 µm
µmpixel
pixeland
and0.8
0.8µmµmpixel
pixelcancan
bebe made
made byby studying
studying Figure
Figure 17, 17, in which
in which the
the 0.8 µm pixel shows narrower pixel-to-pixel
0.8 µm pixel shows narrower pixel-to-pixel isolation. isolation.
Further
Further improvement
improvement can can be
be made
made by designing
designing a vertically extended photodiode
photodiode potential
potential
structure,
structure, ororby bysimply
simplyincreasing
increasing thethe
pixel supply
pixel supplyvoltage, which
voltage, would
which allowallow
would for thefor
usethe
of ause
higher
of a
Vpd(z). It should be noted that the suppression of dark current and white pixel caused
higher Vpd(z). It should be noted that the suppression of dark current and white pixel caused by a by a higher
electric field in field
higher electric a photodiode must bemust
in a photodiode takenbeinto
takenaccount.
into account.

Figure 17. Three-dimensional TCAD simulations of photodiode showing electrostatic potential

Figure 17. Three-dimensional TCAD simulations of photodiode showing electrostatic
contours. (a) Two 0.9 µm pixels; (b) two 0.8 µm pixels.
potential contours. (a) Two 0.9 µm pixels; (b) two 0.8 µm pixels.

5. Conclusions
5. Conclusions
The 45 nm advanced technology is desirable for submicron pixel generation due to tighter design
The 45 nm advanced technology is desirable for submicron pixel generation due to tighter
rules and higher controllability for process variation. In addition, the flexibility of the stacked CIS
design rules and higher controllability for process variation. In addition, the flexibility of the
process improves pixel performance. A novel 0.9 µm pixel with well-balanced light and dark
performances, making full use of a highly manufacturable 45 nm advanced technology with a stacked
CIS, is presented here. A low dark current of 3.2 e−/s at 60 °C, an ultra-low read noise of 0.90 e−·rms,
Sensors 2017, 17, 2816 12 of 13

stacked CIS process improves pixel performance. A novel 0.9 µm pixel with well-balanced light
and dark performances, making full use of a highly manufacturable 45 nm advanced technology with
a stacked CIS, is presented here. A low dark current of 3.2 e− /s at 60 ◦ C, an ultra-low read noise of
0.90 e− ·rms, a high FWC of 4100 e− , and blooming of 0.5% are demonstrated in a 0.9 µm pixel with a
pixel supply voltage of 2.8 V. A simulation study of 0.8 µm pixel indicates that more advanced node
technology with tightened pixel design rules lead to acceptable pixel performances. This technology
offers image sensors a high resolution, superior low light imaging, and small chip size features.

Author Contributions: Seiji Takahashi designed pixels, designed experiments, analyzed data, characterized pixels,
and wrote the manuscript. Yi-Min Huang, Jhy-Jyi Sze, Tung-Ting Wu, Fu-Sheng Guo, Wei-Cheng Hsu,
Tung-Hsiung Tseng, King Liao, Chin-Chia Kuo, Tzu-Hsiang Chen, Chuan-Joung Wang, and Dun-Nien Yaung
developed special process modules, integrated new and improved process workflow, optimized the process,
and performed device fabrications. Wei-Chieh Chiang, Chun-Hao Chuang, Keng-Yu Chou, and Chien Hsien Tseng
performed optical design. Chi-Hsien Chung and Chun-Hao Chuang performed the pixel characterization.
Kuo-Yu Chou designed the peripheral circuit.
Conflicts of Interest: The authors declare no conflict of interest.

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