A B C D E

1 1

LCFC Confidential
BALG1/AILG1/AILZ1 M/B Schematics Document
2 2

Intel Haswell U-Processor with DDRIIIL + NV (N15V-GM/N15S-GT) GPU

Intel Broadwell U-Processor with DDRIIIL + NV (N16V-GM/N15S-GT) GPU
MB：
： NMA331
2014-06-28
3
REV:0.4 3

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2014/06/28 Deciphered Date 2015/06/28 Cover Page
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BILG1/AILG1/AILZ1
Date: Wednesday, July 16, 2014 Sheet 1 of 60
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 A B C D E

LCFC confidential File Name : BALG1/AILG1/AILZ1

Haswell+NV (N15V-GM/N15S-GT)
Broadwell+NV (N16V-GM/N15S-GT) PCI-Express
GB2B-64 Package PCIe Port5
4x Gen2 Memory BUS (DDR3L)
Page 18~28 Dual Channel DDR3L-SO-DIMM X2
Page 14,15
1
VRAM 256/128*16 DDR3L*8 4GB/2GB 1.35V DDR3L 1600 MT/s 1

UP TO 8G x 2
Page 24~27

HDMI USB Left

HDMI Conn.
Page 34 USB 3.0 1x
USB 3.0 Port1
USB 2.0 Port1
DP to VGA DPx2 Lane USB 2.0 2x
VGA Conn.
Page 36 Page 35 Parade PS8613 Intel MCP USB 2.0 Port2
Page 41
eDP x2 Lane
eDP Conn
USB2.0 1x
Int. Camera
USB2.0 Port5 Haswell U 15W
2

Int. MIC Conn.

Broadwell U 15W 2

Page 33
USB2.0 1x USB Right
USB2.0 Port0
SATA HDD SATA Gen3
Page 42 SATA Port0 USB2.0 1x
BGA-1168 Cardreader Realtek SD/MMC Conn.
40mm*24mm RTS5170
SATA ODD SATA Gen1 USB2.0 Port3
USB Board
Page 42 SATA Port1

USB 2.0 1x
LAN Realtek NGFF Card
RJ45 Conn. PCIe 1x PCIe 1x WLAN&BT
Page 38
RTL8111GUL (1G) PCIe Port4
RTL8106EUL (10M/100M) Page 40 USB2.0 Port6
3 3
Page 37 PCIe Port3
HD Audio SPI BUS SPI ROM
Page 3~13
8MB Page 07

Codec SPI ROM 4MB

SPK Conn. for reserve Sub-board for 17"
Conexant CX20752 Page 07
Page 43
Page 43
POWER BOARD
EC
ITE IT8586E-LQFP USB Board
Page 44

HP&Mic Combo Conn.

ODD Board
USB Board
Touch Pad Int.KBD Thermal Sensor LED Board
4 Page 45 Page 45 NCT7718W 4
Page 39

Security Classification LC Future Center Secret Data Title

Issued Date 2014/06/28 Deciphered Date 2014/06/28 Block Diagram

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BILG1/AILG1/AILZ1
Date: Wednesday, July 16, 2014 Sheet 2 of 60
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 A B C D E

Voltage Rails ( O --> Means ON , X --> Means OFF )

SIGNAL
+5VS STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
+3VS
Power Plane Full ON HIGH HIGH HIGH HIGH ON ON ON ON
+1.5VS
+1.35VS S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
1
+1.05VS 1
S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
+3VALW +0.675VS
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
B+ +3VALW_PCH CPU_CORE

+5VALW +1.35V S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF

+VGA_CORE
State +3VGS
+1.8VGS
+1.35VGS
+0.95VGS
USB Port Table BOM Structure Table
USB 2.0 USB 3.0 BOM Structure BTO Item
EHCI1 XHCI Not stuff
@
S0 O O O O O 0 USB Port (Right Side) 100M@ 100M LAN Part
GIGA@ GIGA LAN Part
1 USB Port1 (Left Side) 1 USB Port1 (Left Side) Discrete GPU SKU part
OPT@
S3 O O O O X 2 USB Port2 (Left Side) 2 N15SGT@ For N15S-GT GPU part
2 N15VGM@ For N15V-GM part 2
3 Cardreader 3 For N16V-GM part
S3 N16VGM@
Battery only O O O O X 4 TOUCH PANEL 4 GC6@ GC62.0 support part
RANKA@ For VRAM RankA part
5 Camera For VRAM RankB part
RANKB@
6 UMA@ UMA SKU part
S5 S4/AC Only O O O X X NGFF(WLAN)
TS@ For support touch panel sku part
7 AOAC support part
AOAC@
S5 S4 ME@ ME part(connector, hole)
Battery only O X X X X BDW@ Follow BDW CPU
HSW@ Follow HSW CPU
S5 S4 CD@ Follow cost down
AC & Battery X X X X X
don't exist
PCIE PORT LIST
SMBUS Control Table Port Device
3 3

WLAN Thermal TP
1
SOURCE VGA BATT IT8586E SODIMM PCH charger
WiMAX Sensor Module 2
3 LAN
4 WLAN
EC_SMB_CK1 IT8586E V 5
EC_SMB_DA1 +3VALW X V +3VALW X X X X X V Discrete GPU
6
EC_SMB_CK2 IT8586E V V
X X V V X X
EC_SMB_DA2 +3VS +3VGS X +3VS +3VS +3VALW_PCH

PCH_SMB_CLK PCH
PCH_SMB_DATA +3VALW_PCH X X X V V X V X X
+3VS +3VS +3VALW_PCH

EC SM Bus1 address EC SM Bus2 address PCH SM Bus address

Device Address
Device Device Address DDR DIMMA 1010 000Xb
4 4

Smart Battery 0X16 Thermal Sensor NCT7718W 1001_100xb DDR DIMMB 1010 010Xb
Charger 0001 0010 b VGA 0x41(default) Wlan Rsvd
PCH need to update

Security Classification LC Future Center Secret Data Title

Issued Date 2014/06/28 Deciphered Date 2015/06/28 Notes List

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BILG1/AILG1/AILZ1
Date: Wednesday, July 16, 2014 Sheet 3 of 60
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 5 4 3 2 1

UC1A HSW_ULT_DDR3L

HDMI_TX2- C54 C45 CPU_EDP_TX0-

34 HDMI_TX2- C55 DDI1_TXN0 EDP_TXN0 B46 CPU_EDP_TX0- 33
HDMI D2 HDMI_TX2+ CPU_EDP_TX0+
D 34 HDMI_TX2+ HDMI_TX1- B58 DDI1_TXP0 EDP_TXP0 A47 CPU_EDP_TX1- CPU_EDP_TX0+ 33 D
34 HDMI_TX1- HDMI_TX1+ C58 DDI1_TXN1 EDP_TXN1 B47 CPU_EDP_TX1+ CPU_EDP_TX1- 33
HDMI D1 34 HDMI_TX1+ HDMI_TX0- B55 DDI1_TXP1 EDP_TXP1 CPU_EDP_TX1+ 33
34 HDMI_TX0- A55 DDI1_TXN2 C47
HDMI D0 HDMI_TX0+
34 HDMI_TX0+ HDMI_CLK- A57 DDI1_TXP2 EDP_TXN2 C46
34 HDMI_CLK- B57 DDI1_TXN3 EDP_TXP2 A49
HDMI CLK HDMI_CLK+
34 HDMI_CLK+ DDI1_TXP3 DDI EDP EDP_TXN3 B49
VGA_TX0- C51 EDP_TXP3
35 VGA_TX0- VGA_TX0+ C50 DDI2_TXN0 A45 CPU_EDP_AUX# +VCCIOA_OUT +VCCIOA_OUT & EDP_COMP :
35 VGA_TX0+ C53 DDI2_TXP0 EDP_AUXN B45 CPU_EDP_AUX# 33
DP TO VGA Converter VGA_TX1- CPU_EDP_AUX Trace Width: 20mil
35 VGA_TX1- VGA_TX1+ B54 DDI2_TXN1 EDP_AUXP CPU_EDP_AUX 33
35 VGA_TX1+ C49 DDI2_TXP1 D20 1 2 24.9_0402_1%
Space: 25mil
EDP_COMP RC1
B50 DDI2_TXN2 EDP_RCOMP A43 LCD_BKLT_CTRL_R RC2 1 @ 2 0_0402_5% Max length: 100mil
A53 DDI2_TXP2 EDP_DISP_UTIL INVT_PWM 33
B53 DDI2_TXN3
DDI2_TXP3

1 OF 19
HASWELL-ULT-DDR3L_BGA1168
HSW@

+3VS

RPC19
DDPC_CLK 1 8
DDPC_DATA 2 7
DDPB_CLK 3 6
UC1I HSW_ULT_DDR3L
DDPB_DATA 4 5

C 2.2K_0804_8P4R_5% C

PCH_EDP_PWM B8 B9 DDPB_CLK DDPx_CTRLDATA

33 PCH_EDP_PWM PCH_ENBKL A9 EDP_BKLCTL DDPB_CTRLCLK C9 DDPB_DATA DDPB_CLK 34
33 PCH_ENBKL EDP_BKLEN eDP SIDEBAND DDPB_CTRLDATA DDPB_DATA 34 The signal has a weak internal pull-down.
PCH_ENVDD C6 D9 DDPC_CLK
33 PCH_ENVDD EDP_VDDEN DDPC_CTRLCLK
DDPC_CTRLDATA
D11 DDPC_DATA * H
L
Port is detected.
Port is not detected.

PCI_PIRQA# U6
PCI_PIRQB# P4 PIRQA/GPIO77 C5
PCI_PIRQC# N4 PIRQB/GPIO78 DDPB_AUXN B6 VGA_AUX#
N2 PIRQC/GPIO79 DISPLAY DDPC_AUXN B5 VGA_AUX# 35
PCI_PIRQD#
@ PAD 1 AD4 PIRQD/GPIO80 DDPB_AUXP A6 VGA_AUX
TC1 PME PCIE DDPC_AUXP VGA_AUX 35
BOARD_ID3 U7
9 BOARD_ID3 L1 GPIO55
GPIO52
1 19 GPIO52 GPIO52
PXS_PWREN RC7 OPT@2 1K_0402_5% PXS_PWREN_R L3 C8 HDMI_HPD
21,58 PXS_PWREN 1 2 R5 GPIO54 DDPB_HPD A8 HDMI_HPD 34
PXS_RST# RC8 PXS_RST#_R VGA_HPD
19 PXS_RST# GPIO53 L4 GPIO51 DDPC_HPD D6 EDP_HPD VGA_HPD 35
19 GPIO53 GPIO53 EDP_HPD
@ 0_0402_5%

1
RC37 After confirm with vendor, HPD
1

D 9 OF 19 100K_0402_5%
RC1701 @ 2 2 QC13 HASWELL-ULT-DDR3L_BGA1168 @
has internal pull-down ~100K at
44 VGA_GATE# G PS8613, just reserve in case.
0_0402_5% 2N7002KW_SOT323-3 HSW@

2
1 RC37 can be removed next phase
CC96 @ S
if no issue.
3

.1U_0402_10V6-K
@
2
B B

+3VS +3VS

1
UC1 BDW@ RC9

2
+3VS 1M_0402_5%

G
@

2
RPC1
1 8 PCI_PIRQA# EDP_HPD @ 3 1 QC4
CPU_EDP_HPD 33

D
2 7 PCI_PIRQB# Intel Broadwell CPU
3 6 PCI_PIRQC# SA000067H00 2N7002KW_SOT323-3
4 5 PCI_PIRQD#

1
10K_0804_8P4R_5% RC13
100K_0402_5%

+3VS @

2
RC16 1 2
N15VGM@
RC10 1 2 10K_0402_5% GPIO52 0_0402_5%

RC11 1 2 10K_0402_5% GPIO53

RC14 1 2 10K_0402_5% PXS_PWREN_R

RC15 1 @ 2 10K_0402_5% PXS_RST#_R

A A

Reserve for NV GPU

RC27 1 @ 2 10K_0402_5% GPIO52

RC30 1 @ 2 10K_0402_5% GPIO53

Security Classification LC Future Center Secret Data Title

RC17 2 @ 1 100K_0402_5% PXS_PWREN_R

RC18 2 1 100K_0402_5% PXS_RST#_R

Issued Date 2014/06/28 Deciphered Date 2015/06/28 MCP (DDI,EDP)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BILG1/AILG1/AILZ1
Date: Thursday, July 17, 2014 Sheet 4 of 60
5 4 3 2 1
 5 4 3 2 1

UC1B HSW_ULT_DDR3L

+1.05V_VCCST

TC2 @ 1 PROC_DETECT# D61

PROC_DETECT

1
D TC3 @ 1 CATERR# K61 MISC D
RC19 H_PECI N62 CATERR J62 XDP_PRDY# 1 PAD @
44 H_PECI PECI PRDY K62 1 TC4
62_0402_1% XDP_PREQ# PAD @
PREQ E60 XDP_TCLK 1 TC5
PAD @
PROC_TCK E61 1 TC6
XDP_TMS PAD @

2
1 2 RC20 K63 JTAG PROC_TMS E59 1 TC7
56_0402_5% H_PROCHOT#_R XDP_TRST# PAD @
44,51,52 H_PROCHOT# PROCHOT PROC_TRST F63 1 TC8
THERMAL XDP_TDI PAD @
PROC_TDI F62 1 TC9
XDP_TDO PAD @
PROC_TDO TC10
+1.35V 1 2 RC21 CPU_PROCPWRGD C61
10K_0402_5% PROCPWRGD PWR
J60 XDP_BPM0# 1 PAD @
BPM#0 TC11

1
H60 XDP_BPM1# 1 PAD @
BPM#1 H61 1 TC12
RC22 XDP_BPM2# PAD @
BPM#2 TC13
470_0402_5% H62 XDP_BPM3# 1 PAD @
AU60 BPM#3 K59 1 TC14
SM_RCOMP_0 XDP_BPM4# PAD @
AV60 SM_RCOMP0 DDR3L BPM#4 H63 1 TC15
SM_RCOMP_1 XDP_BPM5# PAD @
TC16

2
SM_RCOMP_2 AU61 SM_RCOMP1 BPM#5 K60 XDP_BPM6# 1 PAD @
SM_RCOMP2 BPM#6 TC17
RC23 1 2 0_0402_5% CPU_DRAMRST#_R AV15 J61 XDP_BPM7# 1 PAD @
14,15 CPU_DRAMRST# AV61 SM_DRAMRST BPM#7 TC18
@ SM_PG_CNTL1
SM_PG_CNTL1
1
CC1 2 OF 19
0.01U_0402_25V7K HASWELL-ULT-DDR3L_BGA1168
2 EMC@
C C
HSW@

100_0402_1% 2 1 RC24 SM_RCOMP_2

121_0402_1% 2 1 RC25 SM_RCOMP_1

+3VALW
200_0402_1% 2 1 RC26 SM_RCOMP_0

1
RC28
100K_0402_5%

2
CPU_DRAMPG_CNTL 55
+1.35V
B B

1
C +1.35V
RC3 1 2 2 QC14
1K_0402_5% B
E

3
MMBT3904WH_SOT323-3 1 QC5
@ D
RC31 1 2 2
SM_PG_CNTL1 G
0_0402_5% 1 S
CD1 PJA138K_SOT23-3 RD1 1 2 66.5_0402_1% DDRA_ODT0
3 DDRA_ODT0 14
2

.1U_0402_10V6-K
RC29 @ DDR_ODT RD2 1 2 66.5_0402_1% DDRA_ODT1
2 DDRA_ODT1 14
10K_0402_5%
@ RD3 1 2 66.5_0402_1% DDRB_ODT0
DDRB_ODT0 15
1

RD4 1 2 66.5_0402_1% DDRB_ODT1

DDRB_ODT1 15

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/06/28 Deciphered Date 2015/06/28 MCP (MISC,THERMAL,JATG)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BILG1/AILG1/AILZ1
Date: Wednesday, July 16, 2014 Sheet 5 of 60
5 4 3 2 1
 5 4 3 2 1

UC1C HSW_ULT_DDR3L UC1D HSW_ULT_DDR3L

14 DDRA_DQ[0..15]
DDRA_DQ0 AH63 AU37
AH62 SA_DQ0 SA_CLK#0 AV37 DDRA_CLK0# 14 14 DDRA_DQ[32..47] AY31 AM38
DDRA_DQ1 DDRA_DQ32
AK63 SA_DQ1 SA_CLK0 AW36 DDRA_CLK0 14 AW31 SB_DQ0 SB_CK#0 AN38 DDRB_CLK0# 15
DDRA_DQ2 DDRA_DQ33
D AK62 SA_DQ2 SA_CLK#1 AY36 DDRA_CLK1# 14 AY29 SB_DQ1 SB_CK0 AK38 DDRB_CLK0 15 D
DDRA_DQ3 DDRA_DQ34
SA_DQ3 SA_CLK1 DDRA_CLK1 14 SB_DQ2 SB_CK#1 DDRB_CLK1# 15
DDRA_DQ4 AH61 DDRA_DQ35 AW29 AL38
AH60 SA_DQ4 AU43 AV31 SB_DQ3 SB_CK1 DDRB_CLK1 15
DDRA_DQ5 DDRA_DQ36
AK61 SA_DQ5 SA_CKE0 AW43 DDRA_CKE0 14 AU31 SB_DQ4 AY49
DDRA_DQ6 DDRA_DQ37
AK60 SA_DQ6 SA_CKE1 AY42 DDRA_CKE1 14 AV29 SB_DQ5 SB_CKE0 AU50 DDRB_CKE0 15
DDRA_DQ7 DDRA_DQ38
AM63 SA_DQ7 SA_CKE2 AY43 AU29 SB_DQ6 SB_CKE1 AW49 DDRB_CKE1 15
DDRA_DQ8 DDRA_DQ39
DDRA_DQ9 AM62 SA_DQ8 SA_CKE3 DDRA_DQ40 AY27 SB_DQ7 SB_CKE2 AV50
DDRA_DQ10 AP63 SA_DQ9 AP33 DDRA_DQ41 AW27 SB_DQ8 SB_CKE3
AP62 SA_DQ10 SA_CS#0 AR32 DDRA_CS0# 14 AY25 SB_DQ9 AM32
DDRA_DQ11 DDRA_DQ42
AM61 SA_DQ11 SA_CS#1 DDRA_CS1# 14 AW25 SB_DQ10 SB_CS#0 AK32 DDRB_CS0# 15
DDRA_DQ12 DDRA_DQ43
AM60 SA_DQ12 AP32 1 AV27 SB_DQ11 SB_CS#1 DDRB_CS1# 15
DDRA_DQ13 SA_ODT0 PAD @ DDRA_DQ44
SA_DQ13 SA_ODT0 TC19 SB_DQ12
DDRA_DQ14 AP61 DDRA_DQ45 AU27 AL32 SB_ODT0 1 PAD @
AP60 SA_DQ14 AY34 AV25 SB_DQ13 SB_ODT0 TC20
DDRA_DQ15 DDRA_DQ46
15 DDRB_DQ[0..15] AP58 SA_DQ15 SA_RAS AW34 DDRA_RAS# 14 AU25 SB_DQ14 AM35
DDRB_DQ0 DDRA_DQ47
SA_DQ16 SA_WE DDRA_WE# 14 15 DDRB_DQ[32..47] SB_DQ15 SB_RAS DDRB_RAS# 15
DDRB_DQ1 AR58 AU34 DDRB_DQ32 AM29 AK35
SA_DQ17 SA_CAS DDRA_CAS# 14 SB_DQ16 SB_WE DDRB_WE# 15
DDRB_DQ2 AM57 DDRB_DQ33 AK29 AM33
SA_DQ18 SB_DQ17 SB_CAS DDRB_CAS# 15
DDRB_DQ3 AK57 AU35 DDRB_DQ34 AL28
AL58 SA_DQ19 SA_BA0 AV35 DDRA_BS0# 14 AK28 SB_DQ18 AL35
DDRB_DQ4 DDRB_DQ35
AK58 SA_DQ20 SA_BA1 AY41 DDRA_BS1# 14 AR29 SB_DQ19 SB_BA0 AM36 DDRB_BS0# 15
DDRB_DQ5 DDRB_DQ36
SA_DQ21 SA_BA2 DDRA_BS2# 14 SB_DQ20 SB_BA1 DDRB_BS1# 15
DDRB_DQ6 AR57 DDRB_DQ37 AN29 AU49
SA_DQ22 DDRA_MA[0..15] 14 SB_DQ21 SB_BA2 DDRB_BS2# 15
DDRB_DQ7 AN57 AU36 DDRA_MA0 DDRB_DQ38 AR28 4 OF 19
SA_DQ23 SA_MA0 SB_DQ22 DDRB_MA[0..15] 15
DDRB_DQ8 AP55 AY37 DDRA_MA1 DDRB_DQ39 AP28 AP40 DDRB_MA0
DDRB_DQ9 AR55 SA_DQ24 SA_MA1 AR38 DDRA_MA2 DDRB_DQ40 AN26 SB_DQ23 SB_MA0 AR40 DDRB_MA1
DDRB_DQ10 AM54 SA_DQ25 SA_MA2 AP36 DDRA_MA3 DDRB_DQ41 AR26 SB_DQ24 SB_MA1 AP42 DDRB_MA2
DDRB_DQ11 AK54 SA_DQ26 SA_MA3 AU39 DDRA_MA4 DDRB_DQ42 AR25 SB_DQ25 SB_MA2 AR42 DDRB_MA3
DDRB_DQ12 AL55 SA_DQ27 SA_MA4 AR36 DDRA_MA5 DDRB_DQ43 AP25 SB_DQ26 SB_MA3 AR45 DDRB_MA4
DDRB_DQ13 AK55 SA_DQ28 SA_MA5 AV40 DDRA_MA6 DDRB_DQ44 AK26 SB_DQ27 SB_MA4 AP45 DDRB_MA5
DDRB_DQ14 AR54 SA_DQ29 SA_MA6 AW39 DDRA_MA7 DDRB_DQ45 AM26 SB_DQ28 SB_MA5 AW46 DDRB_MA6
DDRB_DQ15 AN54 SA_DQ30 DDR CHANNEL A SA_MA7 AY39 DDRA_MA8 DDRB_DQ46 AK25 SB_DQ29 SB_MA6 AY46 DDRB_MA7
14 DDRA_DQ[16..31] SA_DQ31 SA_MA8 SB_DQ30 SB_MA7
DDRA_DQ16 AY58 AU40 DDRA_MA9 DDRB_DQ47 AL25 AY47 DDRB_MA8
SA_DQ32 SA_MA9 14 DDRA_DQ[48..63] SB_DQ31 SB_MA8
DDRA_DQ17 AW58 AP35 DDRA_MA10 DDRA_DQ48 AY23 DDR CHANNEL B AU46 DDRB_MA9
DDRA_DQ18 AY56 SA_DQ33 SA_MA10 AW41 DDRA_MA11 DDRA_DQ49 AW23 SB_DQ32 SB_MA9 AK36 DDRB_MA10
C DDRA_DQ19 AW56 SA_DQ34 SA_MA11 AU41 DDRA_MA12 DDRA_DQ50 AY21 SB_DQ33 SB_MA10 AV47 DDRB_MA11 C
DDRA_DQ20 AV58 SA_DQ35 SA_MA12 AR35 DDRA_MA13 DDRA_DQ51 AW21 SB_DQ34 SB_MA11 AU47 DDRB_MA12
DDRA_DQ21 AU58 SA_DQ36 SA_MA13 AV42 DDRA_MA14 DDRA_DQ52 AV23 SB_DQ35 SB_MA12 AK33 DDRB_MA13
DDRA_DQ22 AV56 SA_DQ37 SA_MA14 AU42 DDRA_MA15 DDRA_DQ53 AU23 SB_DQ36 SB_MA13 AR46 DDRB_MA14
DDRA_DQ23 AU56 SA_DQ38 SA_MA15 DDRA_DQ54 AV21 SB_DQ37 SB_MA14 AP46 DDRB_MA15
DDRA_DQ24 AY54 SA_DQ39 AJ61 DDRA_DQS#0 DDRA_DQ55 AU21 SB_DQ38 SB_MA15
DDRA_DQ25 AW54 SA_DQ40 SA_DQSN0 AN62 DDRA_DQS#1 DDRA_DQ56 AY19 SB_DQ39 AW30 DDRA_DQS#4
DDRA_DQ26 AY52 SA_DQ41 SA_DQSN1 AM58 DDRB_DQS#0 DDRA_DQ57 AW19 SB_DQ40 SB_DQSN0 AV26 DDRA_DQS#5
DDRA_DQ27 AW52 SA_DQ42 SA_DQSN2 AM55 DDRB_DQS#1 DDRA_DQ58 AY17 SB_DQ41 SB_DQSN1 AN28 DDRB_DQS#4
DDRA_DQ28 AV54 SA_DQ43 SA_DQSN3 AV57 DDRA_DQS#2 DDRA_DQ59 AW17 SB_DQ42 SB_DQSN2 AN25 DDRB_DQS#5
DDRA_DQ29 AU54 SA_DQ44 SA_DQSN4 AV53 DDRA_DQS#3 DDRA_DQ60 AV19 SB_DQ43 SB_DQSN3 AW22 DDRA_DQS#6
DDRA_DQ30 AV52 SA_DQ45 SA_DQSN5 AL43 DDRB_DQS#2 DDRA_DQ61 AU19 SB_DQ44 SB_DQSN4 AV18 DDRA_DQS#7
DDRA_DQ31 AU52 SA_DQ46 SA_DQSN6 AL48 DDRB_DQS#3 DDRA_DQ62 AV17 SB_DQ45 SB_DQSN5 AN21 DDRB_DQS#6
15 DDRB_DQ[16..31] AK40 SA_DQ47 SA_DQSN7 AU17 SB_DQ46 SB_DQSN6 AN18
DDRB_DQ16 DDRA_DQ63 DDRB_DQS#7
SA_DQ48 15 DDRB_DQ[48..63] SB_DQ47 SB_DQSN7
DDRB_DQ17 AK42 AJ62 DDRA_DQS0 DDRB_DQ48 AR21
DDRB_DQ18 AM43 SA_DQ49 SA_DQSP0 AN61 DDRA_DQS1 DDRB_DQ49 AR22 SB_DQ48 AV30 DDRA_DQS4
DDRB_DQ19 AM45 SA_DQ50 SA_DQSP1 AN58 DDRB_DQS0 DDRB_DQ50 AL21 SB_DQ49 SB_DQSP0 AW26 DDRA_DQS5
DDRB_DQ20 AK45 SA_DQ51 SA_DQSP2 AN55 DDRB_DQS1 DDRB_DQ51 AM22 SB_DQ50 SB_DQSP1 AM28 DDRB_DQS4
DDRB_DQ21 AK43 SA_DQ52 SA_DQSP3 AW57 DDRA_DQS2 DDRB_DQ52 AN22 SB_DQ51 SB_DQSP2 AM25 DDRB_DQS5
DDRB_DQ22 AM40 SA_DQ53 SA_DQSP4 AW53 DDRA_DQS3 DDRB_DQ53 AP21 SB_DQ52 SB_DQSP3 AV22 DDRA_DQS6
DDRB_DQ23 AM42 SA_DQ54 SA_DQSP5 AL42 DDRB_DQS2 DDRB_DQ54 AK21 SB_DQ53 SB_DQSP4 AW18 DDRA_DQS7
DDRB_DQ24 AM46 SA_DQ55 SA_DQSP6 AL49 DDRB_DQS3 DDRB_DQ55 AK22 SB_DQ54 SB_DQSP5 AM21 DDRB_DQS6
DDRB_DQ25 AK46 SA_DQ56 SA_DQSP7 DDRB_DQ56 AN20 SB_DQ55 SB_DQSP6 AM18 DDRB_DQS7
DDRB_DQ26 AM49 SA_DQ57 AP49 DDRB_DQ57 AR20 SB_DQ56 SB_DQSP7
SA_DQ58 SM_VREF_CA DDR_SM_VREFCA 14 SB_DQ57
DDRB_DQ27 AK49 AR51 DDRB_DQ58 AK18
SA_DQ59 SM_VREF_DQ0 DDR_SA_VREFDQ 14 SB_DQ58
DDRB_DQ28 AM48 AP51 DDRB_DQ59 AL18
AK48 SA_DQ60 SM_VREF_DQ1 DDR_SB_VREFDQ 15 AK20 SB_DQ59
DDRB_DQ29 DDRB_DQ60
DDRB_DQ30 AM51 SA_DQ61 DDRB_DQ61 AM20 SB_DQ60
SA_DQ62 SMVREF SB_DQ61
DDRB_DQ31 AK51 WIDTH:20MIL DDRB_DQ62 AR18
SA_DQ63 DDRB_DQ63 AP18 SB_DQ62
SPACING: 20MIL SB_DQ63

B B

DDRA_DQS#[0..7] DDRB_DQS#[0..7]
DDRA_DQS#[0..7] 14 DDRB_DQS#[0..7] 15
DDRA_DQS[0..7] DDRB_DQS[0..7]
DDRA_DQS[0..7] 14 DDRB_DQS[0..7] 15
3 OF 19
HASWELL-ULT-DDR3L_BGA1168 HASWELL-ULT-DDR3L_BGA1168

HSW@ HSW@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/06/28 Deciphered Date 2015/06/28 MCP (DDR3L)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BILG1/AILG1/AILZ1
Date: Wednesday, July 16, 2014 Sheet 6 of 60
5 4 3 2 1
 5 4 3 2 1

TXC P/N: 9H03200042 should to be used.

LCFC P/N:SJ10000IY00
RTC_X1

+3VS
RC32 2 1 10M_0402_5% RTC_X2 1 RPC2

1
CC3 JME1 ODD_DETECT# 1 8
VCCRTC 1U_0402_10V6K SHORT PADS SATA0GP 2 7
YC1 1 2 @ SATA2GP 3 6

2
2 SATA3GP 4 5
2 32.768KHZ_12.5PF_200458-PG14 2 RC33 1 2 20K_0402_1% SRTC_RST#
CC4 RC34 1 2 20K_0402_1% RTC_RST# 10K_0804_8P4R_5%
BDW@
15P_0402_50V8J CC5
18P_0402_50V8J 1

1
1 1 CC6 JCMOS1
1U_0402_10V6K SHORT PADS
@

2
2
D D
CRYSTAL +3VALW_PCH
1, Space 15MIL
2, No trace under crystal
3, Place on oppsosit side of MCP for temp influence SML0_CLK RC35 2 1 2.2K_0402_5%

SML0_DATA RC36 2 1 2.2K_0402_5%

UC1E HSW_ULT_DDR3L

VCCRTC RPC22
RTC_X1 AW5 SMB_ALERT# 1 8
YC1 HSW@ RTC_X2 AY5 RTCX1 SML0_ALERT# 2 7
RC39 2 1 1M_0402_5% SM_INTRUDER# AU6 RTCX2 J5 SATA_PRX_DTX_N0 SML1_ALERT# 3 6
INTRUDER SATA_RN0/PERN6_L3 SATA_PRX_DTX_N0 42
RC41 2 1 330K_0402_5% INTVRMEN AV7 H5 SATA_PRX_DTX_P0 SATA_PRX_DTX_P0 42 4 5
AV6 INTVRMEN SATA_RP0/PERP6_L3 B15
SRTC_RST#
SRTCRST
RTC
SATA_TN0/PETN6_L3
SATA_PTX_DRX_N0
SATA_PTX_DRX_N0 42 HDD

Integrated
INTVRMEN RTC_RST# AU7 A15 SATA_PTX_DRX_P0 10K_0804_8P4R_5%
RTCRST SATA_TP0/PETP6_L3 SATA_PTX_DRX_P0 42
32.768KHZ_12.5PF_200458-PG14 * HL Integrated VRM enable (Default)
VRM disable SATA_RN1/PERN6_L2
J8 SATA_PRX_DTX_N1 SATA_PRX_DTX_N1 42
SJ10000I300 H8 SATA_PRX_DTX_P1
(INTVRMEN should always be pull high.) SATA_RP1/PERP6_L2 A17
SATA_PRX_DTX_P1 42
SATA_TN1/PETN6_L2
SATA_PTX_DRX_N1
SATA_PTX_DRX_N1 42 ODD
B17 SATA_PTX_DRX_P1
SATA_TP1/PETP6_L2 SATA_PTX_DRX_P1 42
+3VALW_PCH RC42 1 2 33_0402_5% HDA_BCLK AW8 J6
43 HDA_BITCLK_AUDIO HDA_BCLK/I2S0_SCLK SATA_RN2/PERN6_L1
RC43 1 2 33_0402_5% HDA_SYNC AV11 H6
43 HDA_SYNC_AUDIO HDA_SYNC/I2S0_SFRM SATA_RP2/PERP6_L1
RC44 1 2 33_0402_5% HDA_RST# AU8 B14
43 HDA_RST_AUDIO# HDA_RST/I2S_MCLK AUDIO SATA SATA_TN2/PETN6_L1
RC47 1 @ 2 1K_0402_5% HDA_SDOUT HDA_SDIN0 AY10 C15
43 HDA_SDIN0 HDA_SDI0/I2S0_RXD SATA_TP2/PETP6_L1
AU12
RC45 1 2 33_0402_5% HDA_SDOUT AU11 HDA_SDI1/I2S1_RXD F5
43 HDA_SDOUT_AUDIO HDA_SDO/I2S0_TXD SATA_RN3/PERN6_L0
EMC@ RC46 1 2 0_0402_5% TC21 @ 1 AW10 E5
1 2 44 ME_FLASH HDA_DOCK_EN/I2S1_TXD SATA_RP3/PERP6_L0
@ TC22 @ 1 AV10 C17
CA39 470P_0402_50V7K TC23 @ 1 AY8 HDA_DOCK_RST/I2S1_SFRM SATA_TN3/PETN6_L0 D17
I2S1_SCLK SATA_TP3/PETP6_L0

HDA_SDO This signal has a weak internal pull-down. V1 SATA0GP

SATA0GP/GPIO34 U1 ODD_DETECT#
* 0 = Enable security measures defined in the Flash Descriptor.
1 = Disable Flash Descriptor Security(override). This strap
SATA1GP/GPIO35
SATA2GP/GPIO36
V6 SATA2GP
ODD_DETECT# 42
IREF&RCOMP
AC1 SATA3GP +1.05VS_PSATA3PLL Width: 12-15Mil
should only be asserted high during external pull-up in TC24 @ 1 PCH_JTAG_TRST# AU62 SATA3GP/GPIO37
manufacturing/debug environments ONLY. PCH_TRST Space:12Mil
C TC25 @ 1 PCH_JTAG_TCK AE62 A12 C
TC26 @ 1 PCH_JTAG_TDI AD61 PCH_TCK SATA_IREF L11
Length: 500Mil
TC28 @ 1 PCH_JTAG_TDO AE61 PCH_TDI RSVD3 K10
TC30 @ 1 PCH_JTAG_TMS AD62 PCH_TDO RSVD4 C12 SATA_RCOMP RC48 2 1 3.01K_0402_1%
For EMI PCH_TMS
JTAG
SATA_RCOMP
HDA_SDIN0 AL11 U3 SATALED# RC49 1 @ 2 10K_0402_5%
RSVD1 SATALED +3VS
TC32 @ 1 AC4
TC33 @ 1 PCH_JTAGX AE63 RSVD2
TC34 @ 1 AV2 JTAGX
1 RSVD0
@
CC7
10P_0402_50V8J
2
5 OF 19
HASWELL-ULT-DDR3L_BGA1168

HSW@

UC1G HSW_ULT_DDR3L

AU14 AN2 SMB_ALERT#

44 LPC_AD0 LAD0 SMBALERT/GPIO11
AW12 AP2 PCH_SMB_CLK
44 LPC_AD1 LAD1 SMBCLK
AY12 LPC AH1 PCH_SMB_DATA
44 LPC_AD2 AW11 LAD2 SMBUS SMBDATA AL2 SML0_ALERT#
44 LPC_AD3 LAD3 SML0ALERT/GPIO60
AV12 AN1 SML0_CLK
44 LPC_FRAME# LFRAME SML0CLK AK1 SML0_DATA
SML0DATA AU4 SML1_ALERT#
SML1ALERT/PCHHOT/GPIO73 AU3 PCH_SML1_CLK
SPI_CLK_1 RC173 1 @ 2 33_0402_5% SML1CLK/GPIO75 AH3 PCH_SML1_DAT
SML1DATA/GPIO74 DIMM1, DIMM2, NGFF
SPI_CLK RC50 1 2 15_0402_5% SPI_CLK_R AA3
44 SPI_CLK SPI_CLK
SPI_CS0# RC51 1 @ 2 0_0402_5% SPI_CS0#_R Y7 AF2
44 SPI_CS0# SPI_CS0 CL_CLK
SPI_CS1# RC174 1 @ 2 0_0402_5% SPI_CS1#_R Y4 AD2 +3VALW_PCH +3VS +3VS
SPI_SI_1 RC175 1 @ 2 33_0402_5% AC2 SPI_CS1 SPI C-LINK
CL_DATA AF4
SPI_SI RC52 1 2 15_0402_5% SPI_SI_R AA2 SPI_CS2 CL_RST
44 SPI_SI SPI_MOSI
SPI_SO RC53 1 2 15_0402_5% SPI_SO_R AA4
44 SPI_SO SPI_MISO
SPI_SO_1 RC177 1 @ 2 33_0402_5% SPI_WP#_R Y6
SPI_IO2

1
SPI_HOLD#_R AF1
B SPI_IO3 RC56 RC57 RC58 RC59
B

2
2.2K_0402_5% 2.2K_0402_5% 2.2K_0402_5% 2.2K_0402_5%

G
7 OF 19

2
HASWELL-ULT-DDR3L_BGA1168 PCH_SMB_CLK QC2A 6 1

S
+3V_SPI SMB_CLK_S3 14,15,40

D
HSW@ 2N7002KDWH_SOT363-6

5
G
1

RC60 RC61 PCH_SMB_DATA QC2B 3 4

S
SMB_DATA_S3 14,15,40
1K_0402_5% 1K_0402_5%

D
+3V_SPI 2N7002KDWH_SOT363-6
2

UC3
SPI_WP#_R RC54 1 @ 2 33_0402_5% SPI_WP# SPI_CS0# 1 8
CS# VCC
SPI_SO 2 7 SPI_HOLD# 1
SPI_HOLD#_R RC55 1 @ 2 33_0402_5% SPI_HOLD# DO HOLD# CC8
SPI_WP# 3 6 SPI_CLK
GPU, EC, Thermal Sensor
.1U_0402_10V6-K
WP# CLK @
4 5 SPI_SI 2 +3VALW_PCH +3VS
GND DI

+3V_SPI W25Q64FVSSIG_SO8

1
RC62 RC63

2
2.2K_0402_5% 2.2K_0402_5%

G
1

+3V_SPI
RC179 RC180 UC6 @ @

2
1K_0402_5% 1K_0402_5%
@ @ SPI_CS1# 1 8 PCH_SML1_CLK QC3A 6 1

S
CS VCC EC_SMB_CK2 19,39,44

D
2

SPI_SO_1 2 7 SPI_HOLD#_1 1 2N7002KDWH_SOT363-6

DO(IO1) HOLD/RST(IO3)

5
A SPI_WP#_R RC176 1 @ 2 33_0402_5% SPI_WP#_1 CC97 A

G
SPI_WP#_1 3 6 SPI_CLK_1 .1U_0402_10V6-K
+3VALW_PCH +3V_SPI WP(IO2) CLK @ @
SPI_HOLD#_R RC178 1 @ 2 33_0402_5% SPI_HOLD#_1 4 5 SPI_SI_1 2
RC171 1 @ 2 0_0402_5% GND DI(IO0) PCH_SML1_DAT QC3B 3 4

S
EC_SMB_DA2 19,39,44
W25Q32FVSSIG_SO8

D
+3VS 2N7002KDWH_SOT363-6

RC172 1 @ 2
0_0402_5%
Security Classification LC Future Center Secret Data Title
+3V_SPI
1. If support DS3, connect to +3VS and don't support EC mirror code; Issued Date 2014/06/28 Deciphered Date 2015/06/28 MCP (RTC&AUDIO&SATA&SMBUS)
* 2. If don't support DS3, connect to +3VALW_PCH and support EC mirror code.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BILG1/AILG1/AILZ1
Date: Thursday, July 17, 2014 Sheet 7 of 60
5 4 3 2 1
 5 4 3 2 1

+3VS RC71 2 1 1M_0402_5%

RPC3 YC2
1 8 PCIE_CLKREQ1#
2 7 PCIE_CLKREQ0# 2 3 XTAL24_OUT
3 6 PCIE_CLKREQ5# GND1 OSC2
4 5 XTAL24_IN 1 4
OSC1 GND2
10K_0804_8P4R_5% 1
24MHZ_6PF_7V24000032

1
RPC4 CC11
D D
1 8 LAN_CLKREQ# CC12 3.3P_0402_50V8-C
2 7 WLAN_CLKREQ# 4.7P_0402_50V8-J 2 <BOM Structure>

2
3 6 SYS_RESET#
UC1F HSW_ULT_DDR3L
4 5 PM_CLKRUN#

10K_0804_8P4R_5%

RC120 1 2 10K_0402_5% GPU_CLKREQ#

C43 A25 XTAL24_IN
C42 CLKOUT_PCIE_N0 XTAL24_IN B25 XTAL24_OUT
PCIE_CLKREQ0# U2 CLKOUT_PCIE_P0 XTAL24_OUT
PCIECLKRQ0/GPIO18 K21
RSVD5
+1.05VS_PLPTCLKPLL DIFFCLK_BIASREF
B41 M21 Width: 12-15Mil
A41 CLKOUT_PCIE_N1 RSVD6 C26 DIFFCLK_BIASREF 2 1
CLKOUT_PCIE_P1 DIFFCLK_BIASREF Space:12Mil
PCIE_CLKREQ1# Y5 RC72 3.01K_0402_1%
PCIECLKRQ1/GPIO19 C35 MCP_TESTLOW1 Length: 500Mil
CLK_PCIE_LAN# C41 CLOCK TESTLOW_C35 C34 MCP_TESTLOW2
37 CLK_PCIE_LAN# B42 CLKOUT_PCIE_N2 TESTLOW_C34 AK8
PCIE CLK2 LAN CLK_PCIE_LAN MCP_TESTLOW3
37 CLK_PCIE_LAN AD1 CLKOUT_PCIE_P2 SIGNALS TESTLOW_AK8 AL8
LAN_CLKREQ# MCP_TESTLOW4
37 LAN_CLKREQ# PCIECLKRQ2/GPIO20 TESTLOW_AL8
CLK_PCIE_WLAN# B38 AN15 CLK_PCI_EC_R RC73 2 1 22_0402_5% RPC5
40 CLK_PCIE_WLAN# C37 CLKOUT_PCIE_N3 CLKOUT_LPC_0 AP15 CLK_PCI_EC 44 8 1
PCIE CLK3 WLAN CLK_PCIE_WLAN MCP_TESTLOW1
40 CLK_PCIE_WLAN N1 CLKOUT_PCIE_P3 CLKOUT_LPC_1 7 2
WLAN_CLKREQ# MCP_TESTLOW2
40 WLAN_CLKREQ# PCIECLKRQ3/GPIO21 B35 6 3
MCP_TESTLOW3
CLK_PCIE_GPU# A39 CLKOUT_ITPXDP A35 MCP_TESTLOW4 5 4
19 CLK_PCIE_GPU# B39 CLKOUT_PCIE_N4 CLKOUT_ITPXDP_P
PCIE CLK4 GPU CLK_PCIE_GPU
19 CLK_PCIE_GPU U5 CLKOUT_PCIE_P4
GPU_CLKREQ# 10K_0804_8P4R_5%
19 GPU_CLKREQ# PCIECLKRQ4/GPIO22
B37
C A37 CLKOUT_PCIE_N5 C
PCIE_CLKREQ5# T2 CLKOUT_PCIE_P5
+3VALW PCIECLKRQ5/GPIO23

6 OF 19
RC74 1 2 10K_0402_5% AC_PRESENT_R HASWELL-ULT-DDR3L_BGA1168 VCCRTC

RC75 1 @ 2 10K_0402_5% PCH_GPIO72 HSW@

1
RC76 1 2 10K_0402_5% WAKE# RC77
330K_0402_5%

2
+3VALW_PCH
DSWODVREN

1
RC78 1 2 10K_0402_5% SUSWARN#_R
RC80
RC90 1 2 10K_0402_5% PCH_GPIO72 330K_0402_5%
UC1H HSW_ULT_DDR3L @

2
Reserve for DS3 SYSTEM POWER MANAGEMENT RC182 1 @ 2 0_0402_5% EC_RSMRST#

RC79 1 @ 2 0_0402_5% SUSACK#_R AK2 AW7 DSWODVREN Reserve for DS3

44 SUSACK# SUSACK DSWVRMEN


SYS_RESET# AC3 AV5 PCH_DPWROK_R RC81 1 @ 2 0_0402_5% DSWODVREN - On Die DSW VR Enable
SYS_RESET DPWROK DPWROK_EC 44
RC139 1 @ 2 0_0402_5% SYS_PWROK_R AG2 AJ5 WAKE# RC82 1 @ 2 0_0402_5%
44
10,44
SYS_PWROK
PCH_PWROK
RC126 1 @ 2 0_0402_5% PCH_PWROK_R AY7 SYS_PWROK
PCH_PWROK
WAKE PCIE_WAKE# 9,37,40,44 * H Enable
RC83 1 @ 2 0_0402_5% APWROK AB5 L Disable
RC84 1 @ 2 0_0402_5% PLT_RST#_R AG7 APWROK V5 PM_CLKRUN#
B 19,37,40,44 PLT_RST# PLTRST CLKRUN/GPIO32 AG4 1 @ B
SUS_STAT# TC37
SUS_STAT/GPIO61 AE6 SUSCLK
SUSCLK/GPIO62 SUSCLK 40
AP5 PM_SLP_S5#
1 2 0_0402_5% AW6 SLP_S5/GPIO63 PM_SLP_S5# 44
RC85 @ PCH_RSMRST#_R
44 EC_RSMRST# RSMRST
RC86 1 @ 2 0_0402_5% SUSWARN#_R AV4
44 SUSWARN# SUSWARN/SUSPWRDNACK/GPIO30
RC87 1 @ 2 0_0402_5% PBTN_OUT#_R AL7 AJ6 PM_SLP_S4#_R RC140 1 @ 2 0_0402_5%
44 PBTN_OUT# AJ8 PWRBTN SLP_S4 AT4 1 2 0_0402_5% PM_SLP_S4# 44
AC_PRESENT_R PM_SLP_S3#_R RC141 @
ACPRESENT/GPIO31 SLP_S3 PM_SLP_S3# 44
@ PCH_GPIO72 AN4 AL5
CC101 1 2 1000P_0402_50V7K 1 AF3 BATLOW/GPIO72 SLP_A AP4 PM_SLP_SUS#_R RC89 1 @ 2 0_0402_5%
TC38 SLP_S0 SLP_SUS PM_SLP_SUS# 44
@ PAD 1 AM5 AJ7 1
TC39 SLP_WLAN/GPIO29 SLP_LAN
RC91 1 2 10K_0402_5% SYS_PWROK @ PAD TC40 Reserve for DS3
@ PAD
RPC21
1 8
2 7 PCH_PWROK 8 OF 19
3 6 PCH_RSMRST#_R HASWELL-ULT-DDR3L_BGA1168
4 5
HSW@
10K_0804_8P4R_5%

100K_0402_5% 2 1 RC92 PLT_RST#_R

RC88 1 @ 2 0_0402_5% AC_PRESENT_R
44 AC_PRESENT
100K_0402_1% 2 @ 1 RC94 PCH_DPWROK_R

1K_0402_5% 1 @ 2 RC95 SUSCLK

1

10K_0402_5% 2 @ 1 RC105 GPU_CLKREQ# D

2 QC8
44,53 ACIN# G
A 2N7002KW_SOT323-3 A

S
3

Security Classification LC Future Center Secret Data Title

Issued Date 2014/06/28 Deciphered Date 2015/06/28 MCP (Clock,PM)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BILG1/AILG1/AILZ1
Date: Wednesday, July 16, 2014 Sheet 8 of 60
5 4 3 2 1
 5 4 3 2 1

H_THRMTRIP#_R
@

.01U_0402_16V7-K
44 EC_LID_OUT# RC96 1 2 PCH_GPIO14
+3VALW +3VS

CC102
0_0402_5% 1
RC97 1 @ 2 10K_0402_5% PCH_GPIO12 DC2 1 2 @
RC98 1 2 10K_0402_5% DS3_WAKE# +1.05V_VCCST
RC99 1 2 10K_0402_5% PCH_GPIO25 SDM10U45LP-7_DFN1006-2-2

2
@ 2

2
RC100 RC101 RC102 RC121
UC1J HSW_ULT_DDR3L RC104 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
1K_0402_5% 4G@ @
+3VALW_PCH

1
BOARD_ID0

1
BOARD_ID1
RC103 1 2 10K_0402_5% ODD_EN PCH_GPIO76 P1 D60 H_THRMTRIP#_R RC124 1 2 0_0402_5% BOARD_ID2 OPT@
BMBUSY/GPIO76 THRMTRIP H_THRMTRIP# 19
PCH_GPIO8 AU2 V4 KBRST# @ KBRST# 44 BOARD_ID3
D GPIO8 RCIN/GPIO82 4 BOARD_ID3 D
PCH_GPIO12 AM7 T4 SERIRQ
SERIRQ 44

2
PCH_GPIO15 AD6 LAN_PHY_PWR_CTRL/GPIO12 CPU/ SERIRQ AW15 OPI_COMP RC106 2 149.9_0402_1%
BOARD_ID0 Y1 GPIO15 MISC PCH_OPI_RCOMP AF20 1 @ RC107 RC108 RC109 RC123
T3 GPIO16 RSVD7 AB21
+3VALW_PCH
42 ODD_DA#
ODD_DA#
GPIO17 RSVD8
TC41 OPI_RCOMP 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
ODD_EN AD5 Width 20Mil 2G@ UMA@ @
42 ODD_EN GPIO24
RPC6 RC110 1 @ 2 DS3_WAKE# AN5 Space 15Mil
8,37,40,44 PCIE_WAKE#

1
8 1 PCH_GPIO8 0_0402_5% PCH_GPIO28 AD7 GPIO27
7 2 PCH_GPIO26 AN3 GPIO28 Length 500Mil
6 3 PCH_GPIO28 GPIO26 R6 PCH_GPIO83
5 4 PCH_GPIO26 PCH_GPIO56 AG6 GSPI0_CS/GPIO83 L6 BOARD_ID1
PCH_GPIO57 AP1 GPIO56 GSPI0_CLK/GPIO84 N6 PCH_GPIO85
10K_0804_8P4R_5% PCH_GPIO58 AL4 GPIO57 GSPI0_MISO/GPIO85 L8 PCH_GPIO86
PCH_GPIO59 AT5 GPIO58 GSPI0_MOSI/GPIO86 R7 PCH_BT_OFF# BOARD_ID0 BOARD_ID1 BOARD_ID2 BOARD_ID3 Description
GPIO59 GSPI1_CS/GPIO87 PCH_BT_OFF# 40
RPC7 PCH_GPIO44 AK4 GPIO L5 PCH_WLAN_OFF#
GPIO44 GSPI1_CLK/GPIO88 PCH_WLAN_OFF# 40
8 1 PCH_GPIO57 PCH_GPIO47 AB6 N7 PCH_GPIO89
7 2 PCH_GPIO56 VGA_PWRGD U4 GPIO47 GSPI1_MISO/GPIO89 K2 PCH_GPIO90 0 0 1 0 N15S-GT single rank ,+ 14* panel
22,44 VGA_PWRGD GPIO48 GSPI_MOSI/GPIO90
6 3 PCH_GPIO58 PCH_GPIO49 Y3 J1 PCH_GPIO91
5 4 PCH_GPIO59 PCH_GPIO50 P3 GPIO49 UART0_RXD/GPIO91 K3 PCH_GPIO92
PCH_GPIO71 Y2 GPIO50 UART0_TXD/GPIO92 J2 PCH_GPIO93 0 0 1 1 N15S-GT single rank ,+ 17* panel
10K_0804_8P4R_5% PCH_GPIO13 AT3 HSIOPC/GPIO71 SERIAL IO UART0_RTS/GPIO93 G1 PCH_GPIO94
PCH_GPIO14 AH4 GPIO13 UART0_CTS/GPIO94 K4 PCH_GPIO0
RPC8 @ PCH_GPIO25 AM4 GPIO14 UART1_RXD/GPIO0 G2 PCH_GPIO1 0 1 1 0 N15S-GT single rank + 15* panel
8 1 PCH_GPIO47 EC_SMI# RC111 1 2 PCH_GPIO45 AG5 GPIO25 UART1_TXD/GPIO1 J3 PCH_GPIO2
44 EC_SMI# GPIO45 UART1_RST/GPIO2
7 2 PCH_GPIO44 PCH_GPIO46 AG3 J4 PCH_GPIO3
6 3 PCH_GPIO13 0_0402_5% GPIO46 UART1_CTS/GPIO3 F2 PCH_GPIO4 0 1 0 1 UMA
5 4 PCH_GPIO14 PCH_GPIO9 AM3 I2C0_SDA/GPIO4 F3 PCH_GPIO5
PCH_GPIO10 AM2 GPIO9 I2C0_SCL/GPIO5 G4 PCH_GPIO6
10K_0804_8P4R_5% DEVSLP P2 GPIO10 I2C1_SDA/GPIO6 F1 PCH_GPIO7 RC112 1 2 0_0402_5% 1 0 1 0 N15S-GT Dual rank + 14* panel
42 DEVSLP DEVSLP0/GPIO33 I2C1_SCL/GPIO7 EC_SCI# 44
PCH_GPIO70 C4 E3 PCH_GPIO64 @
RPC9 PCH_GPIO38 L2 SDIO_POWER_EN/GPIO70 SDIO_CLK/GPIO64 F4 PCH_GPIO65
8 1 PCH_GPIO45 BOARD_ID2 N5 DEVSLP1/GPIO38 SDIO_CMD/GPIO65 D3 PCH_GPIO66 1 0 1 1 N15S-GT Dual rank + 17* panel
7 2 PCH_GPIO46 PCH_BEEP V2 DEVSLP2/GPIO39 SDIO_D0/GPIO66 E4 PCH_GPIO67
43 PCH_BEEP SPKR/GPIO81 SDIO_D1/GPIO67
6 3 PCH_GPIO10 C3 CMOS_ON#
SDIO_D2/GPIO68 CMOS_ON# 33
5 4 PCH_GPIO9 E2 PCH_GPIO69 1 1 1 0 N15S-GT Dual rank + 15* panel
SDIO_D3/GPIO69
10K_0804_8P4R_5% 10 OF 19
HASWELL-ULT-DDR3L_BGA1168 1 1 0 1 UMA
C C
HSW@

+3VS

RC125 1 2 10K_0402_5% ODD_DA#

RPC10 19 PCIE_CRX_GTX_N[0..3]
8 1 DEVSLP
7 2 PCH_GPIO49 +3VALW_PCH
19 PCIE_CRX_GTX_P[0..3]
6 3 PCH_GPIO50
5 4 PCH_GPIO76 PCH_GPIO15 RC114 1 @ 2 1K_0402_5%
19 PCIE_CTX_C_GRX_N[0..3]
10K_0804_8P4R_5% UC1K HSW_ULT_DDR3L
19 PCIE_CTX_C_GRX_P[0..3]
GPIO15, Internal PD
RPC11 1: INTEL ME TLS W/ Confidentiality
8 1 PCH_GPIO83 PCIE_CRX_GTX_N0 F10 AN8 USB20_N0 *0: INTEL ME TLS W/O Confidentiality
PERN5_L0 USB2N0 USB20_N0 45
7 2 PCH_GPIO38 PCIE_CRX_GTX_P0 E10 AM8 USB20_P0
6 3 PCH_GPIO70 PERP5_L0 USB2P0 USB20_P0 45 RIGHT USB (2.0)
5 4 PCH_GPIO85 PCIE_CTX_C_GRX_N0 .1U_0402_10V6-K OPT@ 1 2 CC16 PCIE_CTX_GRX_N0 C23 AR7 USB20_N1
PETN5_L0 USB2N1 USB20_N1 41
PCIE_CTX_C_GRX_P0 .1U_0402_10V6-K OPT@ 1 2 CC14 PCIE_CTX_GRX_P0 C22 AT7 USB20_P1
10K_0804_8P4R_5% PETP5_L0 USB2P1 USB20_P1 41 LEFT USB (3.0)
PCIE_CRX_GTX_N1 F8 AR8 USB20_N2 +3VS
PERN5_L1 USB2N2 USB20_N2 41
RPC12 PCIE_CRX_GTX_P1 E8 AP8 USB20_P2
8 1 PCH_GPIO89 PERP5_L1 USB2P2 USB20_P2 41 LEFT USB (2.0) PCH_GPIO66 RC113 1 @ 2 1K_0402_5%
7 2 PCH_GPIO90 PCIE_CTX_C_GRX_N1 .1U_0402_10V6-K OPT@ 1 2 CC15 PCIE_CTX_GRX_N1 B23 AR10 USB20_N3
PETN5_L1 USB2N3 USB20_N3 45
6 3 PCH_GPIO91 PCIE_CTX_C_GRX_P1 .1U_0402_10V6-K OPT@ 1 2 CC17 PCIE_CTX_GRX_P1 A23 AT10 USB20_P3 GPIO66, Internal 20K PD
5 4 PCH_GPIO92 PETP5_L1 USB2P3 USB20_P3 45 Card reader 1: Enable Top Swap Mode
GPU PCIE5 PCIE_CRX_GTX_N2 H10 AM15 *0: Disable Top Swap Mode(default)
10K_0804_8P4R_5% PCIE_CRX_GTX_P2 G10 PERN5_L2 USB2N4 AL15
PERP5_L2 USB2P4 Touch panel
RPC13 PCIE_CTX_C_GRX_N2 .1U_0402_10V6-K OPT@ 1 2 CC18 PCIE_CTX_GRX_N2 B21 AM13 USB20_N5
PETN5_L2 USB2N5 USB20_N5 33
8 1 PCH_GPIO93 PCIE_CTX_C_GRX_P2 .1U_0402_10V6-K OPT@ 1 2 CC19 PCIE_CTX_GRX_P2 C21 AN13 USB20_P5
7 2 PCH_GPIO1 PETP5_L2 USB2P5 USB20_P5 33 Camera
6 3 PCH_GPIO94 PCIE_CRX_GTX_N3 E6 AP11 USB20_N6 +3VS
PERN5_L3 USB2N6 USB20_N6 40
5 4 PCH_GPIO0 PCIE_CRX_GTX_P3 F6 AN11 USB20_P6
PERP5_L3 USB2P6 USB20_P6 40 BT
10K_0804_8P4R_5% PCIE_CTX_C_GRX_N3 .1U_0402_10V6-K OPT@ 1 2 CC20 PCIE_CTX_GRX_N3 B22 AR13 PCH_GPIO86 RC115 2 @ 1 1K_0402_5%
B
PCIE_CTX_C_GRX_P3 .1U_0402_10V6-K OPT@ 1 2 CC21 PCIE_CTX_GRX_P3 A21 PETN5_L3 USB2N7 AP13 B
RPC14 PETP5_L3 USB2P7 RC116 2 @ 1 1K_0402_5%
8 1 PCH_GPIO3 37 PCIE_PRX_DTX_N3 PCIE_PRX_DTX_N3 G11
7 2 PCH_GPIO2 PCIE_PRX_DTX_P3 F11 PERN3 G20 USB30_RX_N1
37 PCIE_PRX_DTX_P3 PERP3 USB3RN1 USB30_RX_N1 41
6 3 PCH_GPIO4 LAN PCIE3 H20 USB30_RX_P1 GPIO86, Internal PD
USB3RP1 USB30_RX_P1 41
5 4 PCH_GPIO5 CC22 1 2 .1U_0402_10V6-K PCIE_PTX_DRX_N3 C29 1: LPC
37 PCIE_PTX_C_DRX_N3
CC23 1 2 .1U_0402_10V6-K PCIE_PTX_DRX_P3 B30 PETN3 PCIE USB C33 USB30_TX_N1
LEFT USB (3.0) *0: SPI
37 PCIE_PTX_C_DRX_P3 PETP3 USB3TN1 USB30_TX_N1 41
10K_0804_8P4R_5% B34 USB30_TX_P1
USB3TP1 USB30_TX_P1 41
PCIE_PRX_DTX_N4 F13
40 PCIE_PRX_DTX_N4 PERN4
RPC15 PCIE_PRX_DTX_P4 G13 E18
40 PCIE_PRX_DTX_P4 PERP4 USB3RN2
8 1 PCH_GPIO64 WLAN PCIE4 F18
7 2 PCH_GPIO6 CC24 1 2 .1U_0402_10V6-K PCIE_PTX_DRX_N4 B29 USB3RP2
40 PCIE_PTX_C_DRX_N4 PETN4
6 3 PCH_GPIO65 CC25 1 2 .1U_0402_10V6-K PCIE_PTX_DRX_P4 A29 B33 +3VS
40 PCIE_PTX_C_DRX_P4 PETP4 USB3TN2
5 4 PCH_GPIO7 A33
G17 USB3TP2
10K_0804_8P4R_5% F17 PERN1/USB3RN3 PCH_BEEP RC117 2 @ 1 1K_0402_5%
PERP1/USB3RP3
RPC16 C30
8 1 C31 PETN1/USB3TN3 AJ10 2 1
PCH_GPIO67
PETP1/USB3TP3 USBRBIAS
USBRBIAS RC118 GPIO81, No Reboot, Internal PD
7 2 PCH_GPIO69 AJ11 22.6_0402_1% USBRBIAS 1: Enabled No Reboot Mode
6 3 PCH_GPIO71 F15 USBRBIAS AN10
PERN2/USB3RN4 RSVD11
Width 20Mil *0: Disable No Reboot Mode
5 4 G15 AM10 Space 15Mil
PERP2/USB3RP4 RSVD12
10K_0804_8P4R_5% B31 Length 500Mil
A31 PETN2/USB3TN4
PETP2/USB3TP4 AL3 USB_OC0#
OC0/GPIO40 AT1 USB_OC1#
OC1/GPIO41 USB_OC1# 41
AH2 USB_OC2#
+1.05VS_PUSB3PLL OC2/GPIO42 USB_OC2# 45
E15 AV3 USB_OC3#
E13 RSVD9 OC3/GPIO43 +3VALW_PCH
+3VS RC119 2 1 3.01K_0402_1% PCIE_RCOMP A27 RSVD10
B27 PCIE_RCOMP
RPC18 PCIE_IREF
1 8 CMOS_ON# PCIE_RCOMP&PCIE_IREF RPC17
2 7 PCH_WLAN_OFF# Width 12~15Mil USB_OC0# 8 1
3 6 PCH_BT_OFF# Space >12Mil 11 OF 19 USB_OC1# 7 2
4 5 KBRST# HASWELL-ULT-DDR3L_BGA1168 USB_OC3# 6 3
A
Length 500Mil HSW@ USB_OC2# 5 4 A
10K_0804_8P4R_5%
10K_0804_8P4R_5%
RC122 1 2 10K_0402_5% SERIRQ

RC181 1 2 10K_0402_5% VGA_PWRGD

Security Classification LC Future Center Secret Data Title

Issued Date 2014/06/28 Deciphered Date 2015/06/28 MCP (GPIO,USB,PCIE)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BILG1/AILG1/AILZ1
Date: Wednesday, July 16, 2014 Sheet 9 of 60
5 4 3 2 1
 5 4 3 2 1

CPU_CORE +1.35V_CPU
UC1L HSW_ULT_DDR3L

+1.35V Need short +1.35V_CPU @ TC45 1 L59 C36

RSVD13 VCC8

2.2U_0603_10V6-K

2.2U_0603_10V6-K

2.2U_0603_10V6-K

2.2U_0603_10V6-K
@ TC46 1 J58 C40
JC1 @ RSVD14 VCC9 C44
VCC10 1 1 1 1

CC26

CC27

CC28

CC29
1 2 AH26 C48
1 2 AJ31 VDDQ1 VCC11 C52
AJ33 VDDQ2 VCC12 C56 CD@
JUMP_43X79 AJ37 VDDQ3 VCC13 E23 2 2 2 2
CD@
AN33 VDDQ4 VCC14 E25
AP43 VDDQ5 VCC15 E27
AR48 VDDQ6 VCC16 E29
D
AY35 VDDQ7 VCC17 E31 D
AY40 VDDQ8 VCC18 E33
CPU_CORE
VDDQ9 VCC19
For cost down, change to X5R.
AY44 E35
CPU_CORE AY50 VDDQ10 VCC20 E37
VDDQ11 VCC21

2
VCC_SENSE E39
F59 VCC22 E41
Length Match: <25Mil RC127
VCC1 VCC23

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
Space: More Than 25Mil 100_0402_1% @ TC47 1 N58 E43
RSVD15 VCC24

330U_2.5V_M
@ TC48 1 AC58 E45 1 1 1 1 1 1 1
GND Reference RSVD16 VCC25

CC34

CC30

CC35

CC31

CC32

CC33
E47

1
VCC26

CC41
+VCCIO_OUT RC128 1 @ 2 0_0402_5% E63 E49 +
59 CPU_VCC_SENSE VCC_SENSE VCC27
AB23 E51
A59 RSVD17 VCC28 E53 2 2 CD@ 2 2 2 2
E20 VCCIO_OUT VCC29 E55 2
+VCCIOA_OUT VCCIOA_OUT VCC30
1 @ TC50 1 AD23 E57 @
@ TC51 1 AA23 RSVD18 VCC31 F24 CD@
CC36 @ TC52 1 AE59 RSVD19 VCC32 F28
4.7U_0603_10V6-K RSVD20 VCC33 F32
@ 2 CPU_SVID_ALERT#_R L62 VCC34 F36
VIDALERT HSW ULT POWER VCC35 1.35V_CPU(1.4A)
CPU_SVID_CLK_R N63 F40
VIDSCLK VCC36
CPU_SVID_DAT_R L63
VIDSOUT VCC37
F44 HW 4PCS 2.2UF CAP Mounted
VCCST_PWRGD B59 F48 HW 6PCS 10UF CAP Mounted
CPU_VR_ON F60 VCCST_PWRGD VCC38 F52
59 CPU_VR_ON
CPU_VR_READY C59 VR_EN VCC39 F56
PWR 2PCS 470U Near VR Output
+1.05VS VR_READY VCC40 G23
D63 VCC41 G25
RC129 2 @ 1 150_0402_1% PWR_DEBUG H59 VSS344 VCC42 G27
P62 PWR_DEBUG VCC43 G29
@ TC53 1 P60 VSS345 VCC44 G31 +1.35V_CPU
@ TC54 1 P61 RSVD_TP1 VCC45 G33
@ TC55 1 N59 RSVD_TP2 VCC46 G35
RSVD_TP3 VCC47

CC37

CC38
RC130 2 1 N61 G37
10K_0402_5% @ TC56 1 T59 RSVD_TP4 VCC48 G39
RSVD21 VCC49

33P_0402_50V8J

33P_0402_50V8J
@ TC57 1 AD60 G41
@ TC58 1 AD59 RSVD22 VCC50 G43
RSVD23 VCC51 1 1
@ TC59 1 AA59 G45
@ TC60 1 AE60 RSVD24 VCC52 G47
@ TC61 1 AC59 RSVD25 VCC53 G49
@ TC62 1 AG58 RSVD26 VCC54 G51 2 2
C C
RSVD27 VCC55

RF@

RF@
@ TC63 1 U59 G53
+1.05VS +1.05V_VCCST @ TC64 1 V59 RSVD28 VCC56 G55
RSVD29 VCC57 G57
VCCST(0.1A) VCC58
LC1 1 @ 2 0_0402_5% AC22 H23
AE22 VCCST1 VCC59 J23
CPU_CORE AE23 VCCST2 VCC60 K23
1 1 VCCST3 VCC61 K57
CC39 CC40 AB57 VCC62 L22
22U_0805_6.3V6M 1U_0402_10V6K AD57 VCC2 VCC63 M23
For RF
2 2 AG57 VCC3 VCC64 M57
CC2
33P_0402_50V8J
@ @ C24 VCC4 VCC65 P57
1 VCC5 VCC66
C28 U57
C32 VCC6 VCC67 W57
VCC7 VCC68
2 12 OF 19
HASWELL-ULT-DDR3L_BGA1168
SVID
RF@

1, Stripline Line, No More Than 6000Mil

2, Alert# Route Between CLK and Data HSW@
3, CLK Length<Data Length<CLK Length + 2000Mil
4, Space at least 18Mil For RF
+1.05VS

1
CC42
2

.1U_0402_10V6-K
RC131 RC132 @
75_0402_1% 130_0402_1% 2
1

59 CPU_SVID_ALERT# RC133 2 1 43_0402_5% CPU_SVID_ALERT#_R

@
RC134 1 2 0_0402_5% CPU_SVID_CLK_R
59 CPU_SVID_CLK
@
B B
RC135 1 2 0_0402_5% CPU_SVID_DAT_R
59 CPU_SVID_DAT
CPU_VR_ON

+1.05V_VCCST

2
+1.05V_VCCST

2
RC146
RC145 10K_0402_5%
2

+3VALW 10K_0402_5%
+3VALW RC137 @

1
1K_0402_5%

1
0_0402_5%
2

2
2 1 CPU_VR_READY
1

RC136 VCCST_PWRGD RC144 RC147 @

10K_0402_5% 10K_0402_5%
1
3

3
D 1 D CC141
1

1
5 QC6B CC140 5 .1U_0402_10V6-K
G .1U_0402_10V6-K G 2N7002KDWH_SOT363-6 @
2N7002KDWH_SOT363-6 @ QC7B 2
6

6
RC138 D S 2 RC148 D S
4

4
2 1 2 QC6A 44,59 VR_CPU_PWROK 2 1 2
8,44 PCH_PWROK G G 2N7002KDWH_SOT363-6
0_0402_5% 2N7002KDWH_SOT363-6 0_0402_5% QC7A
1 1
CC46 S CC49 S
1

1
@ 0.01U_0402_16V7K @ 0.01U_0402_16V7K
@ @
2 2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/06/28 Deciphered Date 2015/06/28 MCP (Power)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BILG1/AILG1/AILZ1
Date: Wednesday, July 16, 2014 Sheet 10 of 60
5 4 3 2 1
 5 4 3 2 1

+3VALW_PCH

HSW_ULT_DDR3L 2
+1.05VS_VCCHSIO UC1M CC50
VCCHSIO 1.838A 1U_0402_10V6K
K9
L10 VCCHSIO[1] 1
+1.05VS VCCHSIO[2] VCCRTC

1U_0402_10V6K

1U_0402_10V6K
VCC1_05[1:9] 1.741A M9
N8 VCCHSIO[3] HSIO RTC AH11
1 1 VCC1_05[1] VCCSUS3_3[5] VCCRTC 1mA

CC53

CC51

1U_0402_10V6K
P9 AG10
VCC1_05[2] VCCRTC

CC55

CC56

CC57
1 B18 AE7 +DCPRTC CC52 2 1
+1.05VS_PUSB3PLL VCCUSB3PLL DCPRTC

CC54

0.1U_0402_10V7K

0.1U_0402_10V7K
+1.05VS_PSATA3PLL B11
D 2 2 VCCSATA3PLL D

1U_0402_10V6K
VCCSPI 0.1U_0402_10V7K
2
VCCSPI 18mA <BOM Structure> 2 2 2

0.1U_0402_10V7K
+1.05VS_POPIPLL Y20 SPI Y8
AA21 RSVD30 OPI
VCCSPI
VCCAPLL[1] 2

CC58 @
CD@ W21 +1.05VS
VCCAPLL[2] AG14 1 1 1
VCCASW[1] AG13
VCCASW[2] 1
VCCASW[1:5] 658mA +1.05VS
@ 1U_0402_10V6K 1 2 CC59 +1.05VS_DCPSUS3 J13 USB3
VCCHDA DCPSUS3 J11
VCC1_05[3]

CC63

CC64

CC65
VCCHDA 11mA H11
AH14 HDA VCC1_05[4] H15
VCCHDA VCC1_05[5]

1U_0402_10V6K

1U_0402_10V6K

10U_0603_6.3V6M
AE8 <BOM Structure>
<BOM Structure>
VCC1_05[6]
1U_0402_10V6K

AF22 1U_0402_10V6K 2 2 2
@ 1U_0402_10V6K 1 2 CC60 +1.05VS_DCPSUS2 AH13 VRM VCC1_05[7] AG19 +PCH_DCPSUSBYP CC61 2 1 +1.05VS
1 DCPSUS2 DCPSUSBYP[1]
CC62

CORE AG20
+3VALW_PCH DCPSUSBYP[2] AE9
VCCASW[3] 1 1 1

CC68

CC69
VCCSUS3_3[1:5] 65mA AF9
2 AC9 VCCASW[4] AG8
VCCSUS3_3[1] VCCASW[5]
22U_0805_6.3V6M

1U_0402_10V6K

22U_0805_6.3V6M
VCCDSW 114mA AA9 GPIO/LPC AD10 +1.05VS_DCPSUS1 CC66 2 1 @ CD@
AH10 VCCSUS3_3[2] DCPSUS1[1] AD8
1 VCCDSW3_3 VCCDSW3_3 DCPSUS1[2] 2 1
CC67

1U_0402_10V6K

V8 +1.5VS 1U_0402_10V6K
+3VS VCC3_3[1]
1 VCC3_3[1:4] 41mA W9 VCCTS1_5 3mA
VCC3_3[2]
CC70 @

22U_0805_6.3V6M J15 +3VS

2 THERMAL SENSOR VCCTS1_5 K14 1 2
1 VCC3_3[3]
CC71

@
K16
2 VCC3_3[4]

0.1U_0402_10V7K
+1.05VS_PLPTVCC1P05
+3VS 2
2

CC72
+1.05VS_PLPTCLKPLL J18 VCCSDIO 17mA
+1.05VS K19 VCCCLK[1] SERIAL IO U8
VCCCLK[2] VCCSDIO[1]

1U_0402_10V6K
A20 T9
J17 VCCACLKPLL VCCSDIO[2] 1
VCCCLK[3] 2

CC74
R21
VCCCLK[4]
1U_0402_10V6K

1U_0402_10V6K

T21 LPT LP POWER 1U_0402_10V6K

TC66 @ 1 K18 VCCCLK[5] SUS OSCILLATOR AB8 +1.05VS_DCPSUS4 CC73 2 1 @
1 1 RSVD31 DCPSUS4 1
CC75

CC76

TC67 @ 1 M20
V21 RSVD32 +1.05VS
AE20 RSVD33 AC20 @ @
C C
2 2 AE21 VCCSUS3_3[3] RSVD34 AG16
+3VALW_PCH VCCSUS3_3[4] USB2 VCC1_05[8] AG17
VCC1_05[9]

1U_0402_10V6K
CD@ 2

CC77
+3VL 13 OF 19
HASWELL-ULT-DDR3L_BGA1168 1
RC149 2 @ 1 VCCDSW3_3
+3VALW 0_0402_5% HSW@

RC150 2 1 0_0402_5%
@

+3VALW_PCH +1.05VS Need short +1.05VS_VCCHSIO +1.05VS_PUSB3PLL +1.05VS +1.05VS_PLPTVCC1P05

JC2 @ +1.05VS_PUSB3PLL 41mA +1.05VS_PLPTVCC1P05 185mA

RC151 2 @ 1 VCCHDA 1 2 LC2 1 2 LC3 1 2
+3VS 0_0402_5% 1 2 2.2UH_CIG10W2R2MNC_20% 2.2UH_CIG10W2R2MNC_20%
JUMP_43X79 1 1 1 1 1 1 1 1
RC152 2 @ 1 CC78 CC79 CC80
0_0402_5% 22U_0805_6.3V6M 22U_0805_6.3V6M 1U_0402_10V6K CC81 CC100 CC82 CC83 CC84
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 1U_0402_10V6K
2 2 2 2 CD@ 2 2 CD@ 2 2

+3VS

RC153 2 @ 1 VCCSPI
+3V_SPI 0_0402_5% +1.05VS_PSATA3PLL +1.05VS_PLPTCLKPLL 31mA +1.05VS_PLPTCLKPLL
+1.05VS_PSATA3PLL 42mA
RC154 2 @ 1 LC4 1 2 LC5 1 2
B B
0_0402_5% 2.2UH_CIG10W2R2MNC_20% 2.2UH_CIG10W2R2MNC_20%

1 1 1 1 1 1 1 1
CC85 CC86 CC87
22U_0805_6.3V6M 22U_0805_6.3V6M 1U_0402_10V6K CC88 CC95 CC98 CC99 CC89
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 1U_0402_10V6K
2 2 2 2 2 CD@ 2 CD@ 2 2

VCCDSW3_3 CC90 1 2 0.47U_0402_25V6K +PCH_DCPSUSBYP

For Intel recommend, place one 0.47uF +1.05VS_POPIPLL

capacitor to address temporary inrush @ +1.05VS_POPIPLL 57mA
LC6 1 2
current.(DOC.489999) 0_0603_5%

1 1 1
1
CC91 CC92 CC93 CC94
33P_0402_50V8J 47U_0805_4V6-M 47U_0805_4V6-M 1U_0402_10V6K
RF@ 2@ 2@ 2
2

For RF

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/06/28 Deciphered Date 2015/06/28 MCP (Power2)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BILG1/AILG1/AILZ1
Date: Wednesday, July 16, 2014 Sheet 11 of 60
5 4 3 2 1
 5 4 3 2 1

UC1N HSW_ULT_DDR3L UC1O HSW_ULT_DDR3L

A11 AJ35 AP22 AV59

A14 VSS1 VSS65 AJ39 AP23 VSS129 VSS193 AV8
A18 VSS2 VSS66 AJ41 AP26 VSS130 VSS194 AW16
D D
A24 VSS3 VSS67 AJ43 AP29 VSS131 VSS195 AW24
A28 VSS4 VSS68 AJ45 AP3 VSS132 VSS196 AW33
A32 VSS5 VSS69 AJ47 AP31 VSS133 VSS197 AW35
A36 VSS6 VSS70 AJ50 AP38 VSS134 VSS198 AW37
A40 VSS7 VSS71 AJ52 AP39 VSS135 VSS199 AW4 UC1P HSW_ULT_DDR3L
A44 VSS8 VSS72 AJ54 AP48 VSS136 VSS200 AW40 H17
A48 VSS9 VSS73 AJ56 AP52 VSS137 VSS201 AW42 D33 VSS300 H57
A52 VSS10 VSS74 AJ58 AP54 VSS138 VSS202 AW44 D34 VSS257 VSS301 J10
A56 VSS11 VSS75 AJ60 AP57 VSS139 VSS203 AW47 D35 VSS258 VSS302 J22
AA1 VSS12 VSS76 AJ63 AR11 VSS140 VSS204 AW50 D37 VSS259 VSS303 J59
AA58 VSS13 VSS77 AK23 AR15 VSS141 VSS205 AW51 D38 VSS260 VSS304 J63
AB10 VSS14 VSS78 AK3 AR17 VSS142 VSS206 AW59 D39 VSS261 VSS305 K1
AB20 VSS15 VSS79 AK52 AR23 VSS143 VSS207 AW60 D41 VSS262 VSS306 K12
AB22 VSS16 VSS80 AL10 AR31 VSS144 VSS208 AY11 D42 VSS263 VSS307 L13
AB7 VSS17 VSS81 AL13 AR33 VSS145 VSS209 AY16 D43 VSS264 VSS308 L15
AC61 VSS18 VSS82 AL17 AR39 VSS146 VSS210 AY18 D45 VSS265 VSS309 L17
AD21 VSS19 VSS83 AL20 AR43 VSS147 VSS211 AY22 D46 VSS266 VSS310 L18
AD3 VSS20 VSS84 AL22 AR49 VSS148 VSS212 AY24 D47 VSS267 VSS311 L20
AD63 VSS21 VSS85 AL23 AR5 VSS149 VSS213 AY26 D49 VSS268 VSS312 L58
AE10 VSS22 VSS86 AL26 AR52 VSS150 VSS214 AY30 D5 VSS269 VSS313 L61
AE5 VSS23 VSS87 AL29 AT13 VSS151 VSS215 AY33 D50 VSS270 VSS314 L7
AE58 VSS24 VSS88 AL31 AT35 VSS152 VSS216 AY4 D51 VSS271 VSS315 M22
AF11 VSS25 VSS89 AL33 AT37 VSS153 VSS217 AY51 D53 VSS272 VSS316 N10
AF12 VSS26 VSS90 AL36 AT40 VSS154 VSS218 AY53 D54 VSS273 VSS317 N3
C
AF14 VSS27 VSS91 AL39 AT42 VSS155 VSS219 AY57 D55 VSS274 VSS318 P59 C
AF15 VSS28 VSS92 AL40 AT43 VSS156 VSS220 AY59 D57 VSS275 VSS319 P63
AF17 VSS29 VSS93 AL45 AT46 VSS157 VSS221 AY6 D59 VSS276 VSS320 R10
AF18 VSS30 VSS94 AL46 AT49 VSS158 VSS222 B20 D62 VSS277 VSS321 R22
AG1 VSS31 VSS95 AL51 AT61 VSS159 VSS223 B24 D8 VSS278 VSS322 R8
AG11 VSS32 VSS96 AL52 AT62 VSS160 VSS224 B26 E11 VSS279 VSS323 T1
AG21 VSS33 VSS97 AL54 AT63 VSS161 VSS225 B28 E17 VSS280 VSS324 T58
AG23 VSS34 VSS98 AL57 AU1 VSS162 VSS226 B32 F20 VSS281 VSS325 U20
AG60 VSS35 VSS99 AL60 AU16 VSS163 VSS227 B36 F26 VSS282 VSS326 U22
AG61 VSS36 VSS100 AL61 AU18 VSS164 VSS228 B4 F30 VSS283 VSS327 U61
AG62 VSS37 VSS101 AM1 AU20 VSS165 VSS229 B40 F34 VSS284 VSS328 U9
AG63 VSS38 VSS102 AM17 AU22 VSS166 VSS230 B44 F38 VSS285 VSS329 V10
AH17 VSS39 VSS103 AM23 AU24 VSS167 VSS231 B48 F42 VSS286 VSS330 V3
AH19 VSS40 VSS104 AM31 AU26 VSS168 VSS232 B52 F46 VSS287 VSS331 V7
AH20 VSS41 VSS105 AM52 AU28 VSS169 VSS233 B56 F50 VSS288 VSS332 W20
AH22 VSS42 VSS106 AN17 AU30 VSS170 VSS234 B60 F54 VSS289 VSS333 W22
AH24 VSS43 VSS107 AN23 AU33 VSS171 VSS235 C11 F58 VSS290 VSS334 Y10
AH28 VSS44 VSS108 AN31 AU51 VSS172 VSS236 C14 F61 VSS291 VSS335 Y59
AH30 VSS45 VSS109 AN32 AU53 VSS173 VSS237 C18 G18 VSS292 VSS336 Y63
AH32 VSS46 VSS110 AN35 AU55 VSS174 VSS238 C20 G22 VSS293 VSS337
AH34 VSS47 VSS111 AN36 AU57 VSS175 VSS239 C25 G3 VSS294
AH36 VSS48 VSS112 AN39 AU59 VSS176 VSS240 C27 G5 VSS295 V58
AH38 VSS49 VSS113 AN40 AV14 VSS177 VSS241 C38 G6 VSS296 VSS338 AH46
AH40 VSS50 VSS114 AN42 AV16 VSS178 VSS242 C39 G8 VSS297 VSS339 V23
AH42 VSS51 VSS115 AN43 AV20 VSS179 VSS243 C57 H13 VSS298 VSS340 E62 RC158 1 @ 2 0_0402_5%
B B
AH44 VSS52 VSS116 AN45 AV24 VSS180 VSS244 D12 VSS299 VSS_SENSE AH16 CPU_VSS_SENSE 59
VSS53 VSS117 VSS181 VSS245 VSS341

2
AH49 AN46 AV28 D14 16 OF 19
AH51 VSS54 VSS118 AN48 AV33 VSS182 VSS246 D18 HASWELL-ULT-DDR3L_BGA1168 RC159
AH53 VSS55 VSS119 AN49 AV34 VSS183 VSS247 D2
VSS56 VSS120 VSS184 VSS248
100_0402_1% VSS_SENSE
AH55 AN51 AV36 D21 HSW@ Length Match: No More Than 25Mil
AH57 VSS57 VSS121 AN52 AV39 VSS185 VSS249 D23 Space: More Than 25Mil

1
AJ13 VSS58 VSS122 AN60 AV41 VSS186 VSS250 D25
AJ14 VSS59 VSS123 AN63 AV43 VSS187 VSS251 D26 GND Reference
AJ23 VSS60 VSS124 AN7 AV46 VSS188 VSS252 D27
AJ25 VSS61 VSS125 AP10 AV49 VSS189 VSS253 D29
AJ27 VSS62 VSS126 AP17 AV51 VSS190 VSS254 D30
AJ29 VSS63 VSS127 AP20 AV55 VSS191 VSS255 D31
VSS64 VSS128 VSS192 15 OF 19 VSS256
HASWELL-ULT-DDR3L_BGA1168

14 OF 19 HSW@
HASWELL-ULT-DDR3L_BGA1168

HSW@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/06/28 Deciphered Date 2015/06/28 MCP (VSS)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BILG1/AILG1/AILZ1
Date: Wednesday, July 16, 2014 Sheet 12 of 60
5 4 3 2 1
 5 4 3 2 1

UC1Q HSW_ULT_DDR3L

DC_TEST_AY2_AW2 AY2 A3 DC_TEST_A3_B3

DC_TEST_AY3_AW3 AY3 DAISY_CHAIN_NCTF_AY2 DAISY_CHAIN_NCTF_A3 A4 TP_DC_TEST_A4 1 @ TC71
TC70 @ 1 TP_DC_TEST_AY60 AY60 DAISY_CHAIN_NCTF_AY3 DAISY_CHAIN_NCTF_A4
D
DC_TEST_AY61_AW61 AY61 DAISY_CHAIN_NCTF_AY60 A60 TP_DC_TEST_A60 1 @ TC72
D
DC_TEST_AY62_AW62 AY62 DAISY_CHAIN_NCTF_AY61 DAISY_CHAIN_NCTF_A60 A61 DC_TEST_A61_B61
TC73 @ 1 TP_DC_TEST_B2 B2 DAISY_CHAIN_NCTF_AY62 DAISY_CHAIN_NCTF_A61 A62 TP_DC_TEST_A62 1 @ TC74
DC_TEST_A3_B3 B3 DAISY_CHAIN_NCTF_B2 DAISY_CHAIN_NCTF_A62 AV1 TP_DC_TEST_AV1 1 @ TC75
DC_TEST_A61_B61 B61 DAISY_CHAIN_NCTF_B3 DAISY_CHAIN_NCTF_AV1 AW1 TP_DC_TEST_AW1 1 @ TC76
DC_TEST_B62_B63 B62 DAISY_CHAIN_NCTF_B61 DAISY_CHAIN_NCTF_AW1 AW2 DC_TEST_AY2_AW2
B63 DAISY_CHAIN_NCTF_B62 DAISY_CHAIN_NCTF_AW2 AW3 DC_TEST_AY3_AW3
DC_TEST_C1_C2 C1 DAISY_CHAIN_NCTF_B63 DAISY_CHAIN_NCTF_AW3 AW61 DC_TEST_AY61_AW61
C2 DAISY_CHAIN_NCTF_C1 DAISY_CHAIN_NCTF_AW61 AW62 DC_TEST_AY62_AW62
DAISY_CHAIN_NCTF_C2 DAISY_CHAIN_NCTF_AW62 AW63 TP_DC_TEST_AW63 1 @ TC77
17 OF 19 DAISY_CHAIN_NCTF_AW63
HASWELL-ULT-DDR3L_BGA1168

HSW@

UC1R HSW_ULT_DDR3L

N23
RSVD42 R23
TC78 @ 1 RSVD43 T23
AT2 RSVD44
TC82 @ 1 RSVD35 U10 1 @ TC83
AU44 RSVD45
TC84 @ 1 AV44 RSVD36
D15 RSVD37
RSVD38 AL1 1 @ TC86
RSVD46 AM11
TC88 @ 1 RSVD47 AP7
F22 RSVD48
RSVD39 AU10
H22 RSVD49
RSVD40 AU15 1 @ TC93
J21 RSVD50
C RSVD41 AW14 C
RSVD51 AY14
RSVD52

18 OF 19
HASWELL-ULT-DDR3L_BGA1168

HSW@

UC1S HSW_ULT_DDR3L

TC96 @ 1 CFG0 AC60 AV63 1 @ TC97 CFG3 RC160 2 @ 1 1K_0402_1%

TC98 @ 1 CFG1 AC62 CFG0 RSVD_TP5 AU63 1 @ TC101
TC99 @ 1 CFG2 AC63 CFG1 RSVD_TP6
TC100 @ 1 CFG3 AA63 CFG2
1 CFG4 AA60 CFG3 C63 1 @
TC102 @
CFG4 RSVD_TP7
TC103 CFG3
TC104 @ 1 CFG5 Y62 C62 1 @ TC105 *1: Disable
TC106 @ 1 CFG6 Y61 CFG5 RSVD_TP8 B43 1 @ TC107
CFG6 RSVD58 0: Enable, Set DFX Enabled BIT
TC108 @ 1 CFG7 Y60
TC109 @ 1 CFG8 V62 CFG7 A51 1 @ TC110
In Debug Interface MSR
TC111 @ 1 CFG9 V61 CFG8 RSVD_TP9 B51 1 @ TC112
TC113 @ 1 CFG10 V60 CFG9 RSVD_TP10
TC114 @ 1 CFG11 U60 CFG10 L60 1 @ TC115
TC116 @ 1 CFG12 T63 CFG11 RSVD_TP11
TC117 @ 1 CFG13 T62 CFG12 RESERVED N60 1 @ TC118 CFG4 RC161 2 1 1K_0402_1%
B
TC119 @ 1 CFG14 T61 CFG13 RSVD59 B

TC120 @ 1 CFG15 T60 CFG14 W23

CFG15 RSVD60 Y22
1 CFG16 AA62 RSVD61 AY15 PROC_OPI_COMP 2 1
TC123 @
CFG16 PROC_OPI_RCOMP
RC162 PROC_OPI_RCOMP
TC124 @ 1 CFG18 U63 49.9_0402_1% Width 20Mil CFG4
1 AA61 CFG18 AV62 1 @
TC125 @ CFG17
CFG17 RSVD62
TC126 Space 15Mil *L: eDP enable
TC127 @ 1 CFG19 U62 D58 H: eDP disable
CFG19 RSVD63 Length 500Mil
RC163 2 1 49.9_0402_1% CFG_RCOMP V63 P22
CFG_RCOMP VSS342 N21
@ 1 A5 VSS343
CFG_RCOMP&TD_IREF TC129
RSVD53 P20
E1 RSVD64 R20
Width 20Mil RSVD54 RSVD65
Space 15Mil D1 CFG0 RC164 2 @ 1 1K_0402_1%
J20 RSVD55
Length 500Mil TC135 @ 1 H18 RSVD56 CFG1 RC165 2 @ 1 1K_0402_1%
2 1 TD_IREF B12 RSVD57
RC166 8.2K_0402_1% TD_IREF CFG8 RC167 2 @ 1 1K_0402_1%
19 OF 19
HASWELL-ULT-DDR3L_BGA1168 CFG9 RC168 2 @ 1 1K_0402_1%

HSW@ CFG10 RC169 2 @ 1 1K_0402_1%

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/06/28 Deciphered Date 2015/06/28 MCP (OTHER)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BILG1/AILG1/AILZ1
Date: Wednesday, July 16, 2014 Sheet 13 of 60
5 4 3 2 1
 5 4 3 2 1

DDR_SA_VREFDQ 6 DDR3 SO-DIMM A

DDRA_DQ[0..63] 6
+1.35V
+1.35V +1.35V
DDRA_DQS[0..7] 6

1
DDRA_DQS#[0..7] 6
RD5
1.82K_0402_1% [email protected] DDRA_MA[0..15] 6
RD6 For RF
JDDR1
2

1 2 +VREF_DQ_DIMMA 1 2
D 2_0402_5% 3 VREF_DQ VSS_2 4 DDRA_DQ4 D
VSS_1 DQ4
1
0.022U_0402_16V7-K

1.82K_0402_1%

2.2U_0603_6.3V6K

.1U_0402_10V6-K

33P_0402_50V8J

33P_0402_50V8J

33P_0402_50V8J
DDRA_DQ0 5 6 DDRA_DQ5
DDRA_DQ1 7 DQ0 DQ5 8
1 1 DQ1 VSS_4 1 1 1
RD7

CD5

CD6

CD7
1 CD4 CD2 9 10 DDRA_DQS#0 RF@ RF@ RF@
VSS_3 DQS0#
CD3

11 12 DDRA_DQS0
CD@ @ 13 DM0 DQS0 14
2

CD@ 2 2 DDRA_DQ2 15 VSS_5 VSS_6 16 DDRA_DQ6 2 2 2

2 DDRA_DQ3 17 DQ2 DQ6 18 DDRA_DQ7
19 DQ3 DQ7 20
DDRA_DQ8 21 VSS_7 VSS_8 22 DDRA_DQ12
DQ8 DQ12
1

DDRA_DQ9 23 24 DDRA_DQ13
RD8 25 DQ9 DQ13 26
24.9_0402_1% DDRA_DQS#1 27 VSS_9 VSS_10 28
CD@ DDRA_DQS1 29 DQS1# DM1 30 CPU_DRAMRST#
31 DQS1 RESET# 32 CPU_DRAMRST# 5,15
2

DDRA_DQ10 33 VSS_11 VSS_12 34 DDRA_DQ14

DDRA_DQ11 35 DQ10 DQ14 36 DDRA_DQ15
37 DQ11 DQ15 38
DDRA_DQ16 39 VSS_13 VSS_14 40 DDRA_DQ20 Layout Note: OSCON (220uF_6.3V_4.2L_ESR17m)*1=(SF000002Y0J)
DDRA_DQ17 41 DQ16 DQ20 42 DDRA_DQ21
43 DQ17 DQ21 44 Place near DIMM (10uF_0603_6.3V)*8
DDRA_DQS#2 45 VSS_15 VSS_16 46
DDRA_DQS2 47 DQS2# DM2 48 (1U_0402_6.3V)*4
49 DQS2 VSS_18 50 DDRA_DQ22
DDRA_DQ18 51 VSS_17 DQ22 52 DDRA_DQ23 (.1U_0402_10V6-K)*4
DDRA_DQ19 53 DQ18 DQ23 54
55 DQ19 VSS_20 56 DDRA_DQ28
DDRA_DQ24 57 VSS_19 DQ28 58 DDRA_DQ29 +1.35V
DDRA_DQ25 59 DQ24 DQ29 60
61 DQ25 VSS_22 62 DDRA_DQS#3
VSS_21 DQS3#

CD8

CD9

CD10

CD11

CD12

CD13

CD14

CD15

CD16

CD17

CD18

CD19

CD56

CD57

CD58

CD59
63 64 DDRA_DQS3
65 DM3 DQS3 66
VSS_23 VSS_24

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
C DDRA_DQ26 67 68 DDRA_DQ30 C
DQ26 DQ30 1
DDRA_DQ27 69 70 DDRA_DQ31 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
71 DQ27 DQ31 72 + CD20
VSS_25 VSS_26 220U_6.3V_M
CD@ CD@ CD@ CD@ CD@ CD@ @
DDRA_CKE0 73 74 DDRA_CKE1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
6 DDRA_CKE0 CKE0 CKE1 DDRA_CKE1 6
75 76
77 VDD_1 VDD_2 78 DDRA_MA15
DDRA_BS2# 79 NC_1 A15 80 DDRA_MA14 CD@ CD@ CD@
6 DDRA_BS2# BA2 A14
81 82
DDRA_MA12 83 VDD_3 VDD_4 84 DDRA_MA11
DDRA_MA9 85 A12/BC# A11 86 DDRA_MA7
87 A9 A7 88
DDRA_MA8 89 VDD_5 VDD_6 90 DDRA_MA6 EMC@ EMC@ EMC@
DDRA_MA5 91 A8 A6 92 DDRA_MA4
93 A5 A4 94
DDRA_MA3 95 VDD_7 VDD_8 96 DDRA_MA2
DDRA_MA1 97 A3 A2 98 DDRA_MA0
99 A1 A0 100
DDRA_CLK0 101 VDD_9 VDD_10 102 DDRA_CLK1
6 DDRA_CLK0 CK0 CK1 DDRA_CLK1 6
DDRA_CLK0# 103 104 DDRA_CLK1#
6 DDRA_CLK0# CK0# CK1# DDRA_CLK1# 6
105 106 +1.35V
DDRA_MA10 107 VDD_11 VDD_12 108 DDRA_BS1#
DDRA_BS0# 109 A10/AP BA1 110 DDRA_RAS#
DDRA_BS1# 6 Note:
6 DDRA_BS0# BA0 RAS# DDRA_RAS# 6 VREF trace width:20 mils at least

1
111 112
DDRA_WE# 113 VDD_13 VDD_14 114 DDRA_CS0# RD9 Spacing:20mils to other signal/planes
6 DDRA_WE# WE# S0# DDRA_CS0# 6
DDRA_CAS# 115 116 DDRA_ODT0 Trace width:20 mils 1.82K_0402_1% Place near DIMM scoket
6 DDRA_CAS# CAS# ODT0 DDRA_ODT0 5
117 118
DDRA_MA13 119 VDD_15 VDD_16 120 DDRA_ODT1
Space:20mils

2
DDRA_CS1# 121 A13 ODT1 122 DDRA_ODT1 5
6 DDRA_CS1# S1# NC_2
123 124 +VREF_CA RD10 1 2 0_0402_5%
125 VDD_17 VDD_18 126 +VREF_CA DDR_SM_VREFCA 6
@ 1
B 127 TEST VREF_CA 128 +VREF_CA 15 B
CD21
VSS_27 VSS_28

1
.1U_0402_10V6-K

DDRA_DQ32 129 130 DDRA_DQ36 0.022U_0402_16V7-K

DDRA_DQ33 131 DQ32 DQ36 132 DDRA_DQ37 RD11
DQ33 DQ37 1 1 2
CD22

133 134 CD23 1.82K_0402_1%

VSS_29 VSS_30 CD@

1
DDRA_DQS#4 135 136 2.2U_0603_6.3V6K
DDRA_DQS4 137 DQS4# DM4 138 @ CD@

2
139 DQS4 VSS_32 140 DDRA_DQ38 2 2 RD12
DDRA_DQ34 141 VSS_31 DQ38 142 DDRA_DQ39 24.9_0402_1%
DDRA_DQ35 143 DQ34 DQ39 144

2
145 DQ35 VSS_34 146 DDRA_DQ44
DDRA_DQ40 147 VSS_33 DQ44 148 DDRA_DQ45 CD@
DDRA_DQ41 149 DQ40 DQ45 150
DQ41 VSS_35 Layout Note: (10U_0603_6.3V)*2
151 152 DDRA_DQS#5
153 VSS_36 DQS5# 154 DDRA_DQS5 Place near DIMM
155 DM5 DQS5 156 (.1U_0402_10V)*4
DDRA_DQ42 157 VSS_37 VSS_38 158 DDRA_DQ46
DDRA_DQ43 159 DQ42 DQ46 160 DDRA_DQ47
161 DQ43 DQ47 162
DDRA_DQ48 163 VSS_39 VSS_40 164 DDRA_DQ52
DDRA_DQ49 165 DQ48 DQ52 166 DDRA_DQ53 +0.675VS
167 DQ49 DQ53 168
DDRA_DQS#6 169 VSS_41 VSS_42 170
DQS6# DM6
CD24

CD25

CD26

CD27

CD64

CD65
DDRA_DQS6 171 172
173 DQS6 VSS_44 174 DDRA_DQ54
VSS_43 DQ54
.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

10U_0603_6.3V6M

10U_0603_6.3V6M
DDRA_DQ50 175 176 DDRA_DQ55
DDRA_DQ51 177 DQ50 DQ55 178
DQ51 VSS_46 1 1 1 1 1 1
179 180 DDRA_DQ60
DDRA_DQ56 181 VSS_45 DQ60 182 DDRA_DQ61
DDRA_DQ57 183 DQ56 DQ61 184 CD@ EMC_NS@ CD@
185 DQ57 VSS_48 186 DDRA_DQS#7 2 2 2 2 2 2
187 VSS_47 DQS7# 188 DDRA_DQS7
189 DM7 DQS7 190
A DDRA_DQ58 191 VSS_49 VSS_50 192 DDRA_DQ62 EMC_NS@ A
DDRA_DQ59 193 DQ58 DQ62 194 DDRA_DQ63
195 DQ59 DQ63 196
1 @ 2 0_0402_5%197 VSS_51 VSS_52 198
RD13 199 SA0 EVENT# 200 SMB_DATA_S3
+3VS 201 VDDSPD SDA 202 SMB_CLK_S3 SMB_DATA_S3 7,15,40 EMC@
203 SA1 SCL 204 SMB_CLK_S3 7,15,40
1 1 VTT_1 VTT_2 +0.675VS
1

@ Security Classification LC Future Center Secret Data Title

CD28 CD29
0_0402_5%
205
GND1 GND2
206 1 [email protected]
2.2U_0603_6.3V6K .1U_0402_10V6-K 207 208 CD68
2 2 RD14 BOSS1 BOSS2 33P_0402_50V8J
Issued Date 2014/06/28 Deciphered Date 2015/06/28 DDRIII SO-DIMM A
CD@
RF@
2

2 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
LCN_DAN06-K4406-0103 Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
ME@ For RF DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
BILG1/AILG1/AILZ1 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, July 16, 2014 Sheet 14 of 60
5 4 3 2 1
 5 4 3 2 1

DDR_SB_VREFDQ 6

+1.35V
DDR3 SO-DIMM B Swap Table
Pin
+1.35V +1.35V Pin Name Net Name
Number

1
DDRB_DQ[0..63] 6
RD15 5 DQ0 DDRB_DQ17
1.82K_0402_1% [email protected] DDRB_DQS[0..7] 6 7 DQ1 DDRB_DQ23
RD16 For RF 15 DQ2 DDRB_DQ18
JDDR2
17 DQ3 DDRB_DQ21

2
1 2 +VREF_DQ_DIMMB 1 2 DDRB_DQS#[0..7] 6
2_0402_5% 3 VREF_DQ VSS1 4 DDRB_DQ16 4 DQ4 DDRB_DQ16
VSS2 DQ4 DDRB_MA[0..15] 6

1.82K_0402_1%

CD30

2.2U_0603_6.3V6K

CD31

.1U_0402_10V6-K

33P_0402_50V8J

33P_0402_50V8J

33P_0402_50V8J
DDRB_DQ17 5
DQ0 DQ5
6 DDRB_DQ22 6 DQ5 DDRB_DQ22
1
0.022U_0402_16V7-K

1 1 DDRB_DQ23 7 8 1 1 1 16 DQ6 DDRB_DQ19

DQ1 VSS3

RD17

CD33

CD34

CD35
D 9 10 DDRB_DQS#2 RF@ RF@ RF@ D
11 VSS4 DQS#0 12 DDRB_DQS2
18 DQ7 DDRB_DQ20
1 DM0 DQS0 10 DQS#0 DDRB_DQS#2
CD32

CD@ @ 13 14
CD@ 2 2 DDRB_DQ18 15 VSS5 VSS6 16 DDRB_DQ19 2 2 2 12 DQS0 DDRB_DQS2
2

DDRB_DQ21 17 DQ2 DQ6 18 DDRB_DQ20

2 19 DQ3 DQ7 20
VSS7 VSS8
21 DQ8 DDRB_DQ3
DDRB_DQ3 21 22 DDRB_DQ2 23 DQ9 DDRB_DQ5
DDRB_DQ5 23 DQ8 DQ12 24 DDRB_DQ4
DQ9 DQ13 33 DQ10 DDRB_DQ6
1

25 26
RD18 DDRB_DQS#0 27 VSS9 VSS10 28 35 DQ11 DDRB_DQ1
24.9_0402_1% DDRB_DQS0 29 DQS#1 DM1 30 CPU_DRAMRST# 22 DQ12 DDRB_DQ2
DQS1 RESET# CPU_DRAMRST# 5,14
CD@ 31
VSS11 VSS12
32 24 DQ13 DDRB_DQ4
DDRB_DQ6 33 34 DDRB_DQ0 34 DQ14 DDRB_DQ0
2

DDRB_DQ1 35 DQ10 DQ14 36 DDRB_DQ7

37 DQ11 DQ15 38 Layout Note: (10uF_0603_6.3V)*8 36 DQ15 DDRB_DQ7
DDRB_DQ8 39 VSS13 VSS14 40 DDRB_DQ13 27 DQS#1 DDRB_DQS#0
DDRB_DQ10 41 DQ16 DQ20 42 DDRB_DQ12 Place near DIMM (1U_0402_6.3V)*8 29 DQS1 DDRB_DQS0
43 DQ17 DQ21 44
DDRB_DQS#1 45 VSS15 VSS16 46 (.1U_0402_10V6-K)*4 39 DQ16 DDRB_DQ8
DDRB_DQS1 47 DQS#2 DM2 48
DQS2 VSS17 41 DQ17 DDRB_DQ10
49 50 DDRB_DQ9
DDRB_DQ14 51 VSS18 DQ22 52 DDRB_DQ11
51 DQ18 DDRB_DQ14
DDRB_DQ15 53 DQ18 DQ23 54 53 DQ19 DDRB_DQ15
55 DQ19 VSS19 56 DDRB_DQ31 +1.35V 40 DQ20 DDRB_DQ13
DDRB_DQ27 57 VSS20 DQ28 58 DDRB_DQ30 42 DQ21 DDRB_DQ12
DDRB_DQ26 59 DQ24 DQ29 60
DQ25 VSS21 50 DQ22 DDRB_DQ9

CD36

CD37

CD38

CD39

CD40

CD41

CD42

CD43
61 62 DDRB_DQS#3
63 VSS22 DQS#3 64 DDRB_DQS3
52 DQ23 DDRB_DQ11
DM3 DQS3 45 DQS#2 DDRB_DQS#1

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
65 66
DDRB_DQ28 67 VSS23 VSS24 68 DDRB_DQ29 47 DQS2 DDRB_DQS1
DQ26 DQ30 1 1 1 1 1 1 1 1
DDRB_DQ24 69 70 DDRB_DQ25 CD@ CD@
71 DQ27 DQ31 72
VSS25 VSS26
57 DQ24 DDRB_DQ27
C C
2 2 2 2 2 2 2 2 59 DQ25 DDRB_DQ26
67 DQ26 DDRB_DQ28
DDRB_CKE0 73 74 DDRB_CKE1 69 DQ27 DDRB_DQ24
6 DDRB_CKE0 CKE0 CKE1 DDRB_CKE1 6 56 DQ28 DDRB_DQ31
75 76 CD@ CD@
VDD1 VDD2
77
NC1 A15
78 DDRB_MA15 58 DQ29 DDRB_DQ30
DDRB_BS2# 79 80 DDRB_MA14 68 DQ30 DDRB_DQ29
6 DDRB_BS2# BA2 A14
81 82
DDRB_MA12 83 VDD3 VDD4 84 DDRB_MA11
70 DQ31 DDRB_DQ25
A12/BC# A11 62 DQS#3 DDRB_DQS#3

CD44

CD45

CD46

CD47

CD60

CD61

CD62

CD63
DDRB_MA9 85 86 DDRB_MA7
87 A9 A7 88 64 DQS3 DDRB_DQS3
VDD5 VDD6

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
DDRB_MA8 89 90 DDRB_MA6
91 A8 A6 92
DDRB_MA5
A5 A4
DDRB_MA4 1 1 1 1 1 1 1 1 129 DQ32 DDRB_DQ33
93 94 131 DQ33 DDRB_DQ36
DDRB_MA3 95 VDD7 VDD8 96 DDRB_MA2
DDRB_MA1 97 A3 A2 98 DDRB_MA0 CD@ CD@ CD@ CD@
141 DQ34 DDRB_DQ39
99 A1 A0 100 2 2 2 2 2 2 2 2 143 DQ35 DDRB_DQ38
DDRB_CLK0 101 VDD9 VDD10 102 DDRB_CLK1 130 DQ36 DDRB_DQ37
6 DDRB_CLK0 CK0 CK1 DDRB_CLK1 6
6 DDRB_CLK0#
DDRB_CLK0# 103
CK0# CK1#
104 DDRB_CLK1#
DDRB_CLK1# 6 CD@
132 DQ37 DDRB_DQ32
105 106 140 DQ38 DDRB_DQ35
DDRB_MA10 107 VDD11 VDD12 108 DDRB_BS1#
DDRB_BS0# 109 A10/AP BA1 110 DDRB_RAS#
DDRB_BS1# 6 142 DQ39 DDRB_DQ34
6 DDRB_BS0# BA0 RAS# DDRB_RAS# 6 135 DQS#4 DDRB_DQS#4
111 112
DDRB_WE# 113 VDD13 VDD14 114 DDRB_CS0# 137 DQS4 DDRB_DQS4
6 DDRB_WE# WE# S0# DDRB_CS0# 6 EMC@ EMC@ EMC@
DDRB_CAS# 115 116 DDRB_ODT0
6 DDRB_CAS# CAS# ODT0 DDRB_ODT0 5
117 118 147 DQ40 DDRB_DQ40
DDRB_MA13 119 VDD15 VDD16 120 DDRB_ODT1
A13 ODT1 DDRB_ODT1 5 149 DQ41 DDRB_DQ43
DDRB_CS1# 121 122
6 DDRB_CS1#
123 S1# NC2 124
157 DQ42 DDRB_DQ42
125 VDD17 VDD18 126 +VREF_CB RD19 1 2 0_0402_5% 159 DQ43 DDRB_DQ44
127 NCTEST VREF_CA 128 +VREF_CA 14 146 DQ44 DDRB_DQ45
@
VSS27 VSS28
.1U_0402_10V6-K
DDRB_DQ33 129
DQ32 DQ36
130 DDRB_DQ37 148 DQ45 DDRB_DQ41
B DDRB_DQ36 131 132 DDRB_DQ32 B
DQ33 DQ37 1 1 158 DQ46 DDRB_DQ46
133 134 CD48 CD49
DDRB_DQS#4 135 VSS29 VSS30 136 2.2U_0603_6.3V6K
160 DQ47 DDRB_DQ47
DDRB_DQS4 137 DQS#4 DM4 138 @ CD@ 152 DQS#5 DDRB_DQS#5
139 DQS4 VSS31 140 DDRB_DQ35 2 2 154 DQS5 DDRB_DQS5
DDRB_DQ39 141 VSS32 DQ38 142 DDRB_DQ34
143 DQ34 DQ39 144
DDRB_DQ38
DQ35 VSS33
163 DQ48 DDRB_DQ52
145 146 DDRB_DQ45 165 DQ49 DDRB_DQ51
DDRB_DQ40 147 VSS34 DQ44 148 DDRB_DQ41
DQ40 DQ45 Layout Note: (10U_0603_6.3V)*2 175 DQ50 DDRB_DQ50
DDRB_DQ43 149 150
151 DQ41 VSS35 152 DDRB_DQS#5 Place near DIMM 177 DQ51 DDRB_DQ48
153 VSS36 DQS#5 154 DDRB_DQS5 (.1U_0402_10V)*4 164 DQ52 DDRB_DQ49
155 DM5 DQS5 156 166 DQ53 DDRB_DQ53
DDRB_DQ42 157 VSS37 VSS38 158 DDRB_DQ46
DQ42 DQ46 174 DQ54 DDRB_DQ54
DDRB_DQ44 159 160 DDRB_DQ47
161 DQ43 DQ47 162
176 DQ55 DDRB_DQ55
DDRB_DQ52 163 VSS39 VSS40 164 DDRB_DQ49 +0.675VS 169 DQS#6 DDRB_DQS#6
DDRB_DQ51 165 DQ48 DQ52 166 DDRB_DQ53 171 DQS6 DDRB_DQS6
167 DQ49 DQ53 168
VSS41 VSS42
CD50

CD51

CD52

CD53

CD66

CD67
DDRB_DQS#6 169 170 181 DQ56 DDRB_DQ62
DDRB_DQS6 171 DQS#6 DM6 172
DQS6 VSS43 183 DQ57 DDRB_DQ57
.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

10U_0603_6.3V6M

10U_0603_6.3V6M
173 174 DDRB_DQ54
DDRB_DQ50 175 VSS44 DQ54 176 DDRB_DQ55
191 DQ58 DDRB_DQ59
DQ50 DQ55 1 1 1 1 1 1 193 DQ59 DDRB_DQ63
DDRB_DQ48 177 178
179 DQ51 VSS45 180 DDRB_DQ56 180 DQ60 DDRB_DQ56
DDRB_DQ62 181 VSS46 DQ60 182 DDRB_DQ61 EMC_NS@ EMC_NS@ CD@ 182 DQ61 DDRB_DQ61
DDRB_DQ57 183 DQ56 DQ61 184 2 2 2 2 2 2
DQ57 VSS47 192 DQ62 DDRB_DQ58
185 186 DDRB_DQS#7
187 VSS48 DQS#7 188 DDRB_DQS7
194 DQ63 DDRB_DQ60
189 DM7 DQS7 190 186 DQS#7 DDRB_DQS#7
DDRB_DQ59 191 VSS49 VSS50 192 DDRB_DQ58 188 DQS7 DDRB_DQS7
DDRB_DQ63 193 DQ58 DQ62 194 DDRB_DQ60
A 195 DQ59 DQ63 196 A
RD20 1 2 @ 197 VSS51 VSS52 198
0_0402_5% 199 SA0 EVENT# 200 SMB_DATA_S3 EMC@
1 2 201 VDDSPD SDA 202 SMB_CLK_S3 SMB_DATA_S3 7,14,40
+3VS 203 SA1 SCL 204 SMB_CLK_S3 7,14,40
RD21 10K_0402_5% +0.675VS
1 1
VTT1 VTT2
[email protected]
205 206 1
CD54 CD55 G1 G2 CD69
Security Classification LC Future Center Secret Data Title
2.2U_0603_6.3V6K .1U_0402_10V6-K LCN_DAN06-K4406-0102 33P_0402_50V8J
2 2 RF@
CD@ ME@ 2 Issued Date 2014/06/28 Deciphered Date 2015/06/28 DDRIII SO-DIMM B
<BOM Structure>
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
For RF DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
BALG1/AIGL1/AILZ1 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, July 16, 2014 Sheet 15 of 60
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/06/28 Deciphered Date 2015/06/28 Blank
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BILG1/AILG1/AILZ1
Date: Wednesday, July 16, 2014 Sheet 16 of 60
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/06/28 Deciphered Date 2015/06/28 Blank
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BILG1/AILG1/AILZ1
Date: Wednesday, July 16, 2014 Sheet 17 of 60
5 4 3 2 1
 5 4 3 2 1

N15x GPIO
Performance Mode P0 TDP at Tj = 102 C* (DDR3)
GPIO I/O ACTIVE Function Description
FBVDDQ PCI Express I/O and Other
GPU Mem NVCLK FBVDD (GPU+Mem) (1.05V) PLLVDD
GPIO0 OUT - FB Enable for GC6 2.0 (4) (1,5) /MCLK NVVDD (1.35V) (1.35V) (6) (1.05V) (3.3V)
Products (W) (W) (MHz) (V) (A) (W) (A) (W) (A) (W) (mA) (W) (mA) (W) (mA) (W)
D GPIO1 OUT N/A D

N15X
GPIO2 OUT N/A 128bit TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
2GB
DDR3
GPIO3 OUT N/A

GPIO4 OUT N/A

GPIO5 OUT N/A GPU power sequencing---3V3_MAIN_EN

GPIO6 IN - GPU wake signal for GC6 2.0

GPIO7 OUT N/A

GPIO8 I/O - System side PCIe reset Monitor

GPIO9 I/O N/A 2.2K Pull-up

N15x Multi-level Straps
GPIO10 OUT N/A

GPIO11 OUT - GPU Core VDD PWM control signal

GPIO12 IN AC Power Detect Input (10K pull High)

Physical Logical Logical Logical Logical
GPIO13 OUT - Phase Shedding Strapping pin Power Rail Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0
C ROM_SCLK +3VGS SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED C
GPIO14 IN N/A
ROM_SI +3VGS RAM_CFG[3] RAM_CFG[2] RAM_CFG[1] RAM_CFG[0]
GPIO15 IN N/A ROM_SO +3VGS DEVID_SEL PCIE_CFG SMB_ALT_ADDR VGA_DEVICE
STRAP0 +3VGS Reserved(keep pull-up and pull-down footprint and stuff 50Kohm pull-up)
GPIO16 N/A
STRAP1 +3VGS
GPIO17 IN N/A STRAP2 +3VGS
Reserved(keep pull-up and pull-down footprint and not stuff by default)
STRAP3 +3VGS
GPIO18 IN N/A
STRAP4 +3VGS
GPIO19 IN N/A

GPIO20 N/A SMBUS_ALT_ADDR

GPIO21 OUT GPU PCIe self-reset control 0 0x9E (Default)

OVERT OUT Active Low Thermal Catastrophic Over Temperature 1 0x9C (Multi-GPU usage)

N15V-GM/N16V-GM Power Sequence

B
N15x Binary Straps B

+3VG_AON Other Power rail

+VGA_CORE
+3VG_AON
Physical
tNVVDD >0
Strapping pin Power Rail Strap Mapping
+1.35VGS
Tpower-off <10ms ROM_SCLK +3VGS SMB_ALT_ADDR
tFBVDDQ >0
ROM_SI +3VGS SUB_VENDOR
+1.05VS_VGA
ROM_SO +3VGS VGA_DEVICE
tPEX_VDD >0
STRAP0 +3VGS RAM_CFG[0]
1.all GPU power rails should be turned off within 10ms STRAP1 +3VGS RAM_CFG[1]
1. all power rail ramp up time should be larger than 40us 2. Optimus system VDD33 avoids drop down earlier than NVDD and FBVDDQ
STRAP2 +3VGS RAM_CFG[2]
STRAP3 +3VGS RAM_CFG[3]
STRAP4 +3VGS PCIE_MAX_SPEED
N15S-GT Power Sequence

+3VG_AON

+VGA_CORE
A A

tNVVDD >0
+1.05VS_VGA

+1.35VGS
tPEX_VDD >0
Security Classification LC Future Center Secret Data Title

1. all power rail ramp up time should be larger than 40us

Issued Date 2014/06/28 Deciphered Date 2015/06/28 VGA Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BILG1/AILG1/AILZ1
Date: Wednesday, July 16, 2014 Sheet 18 of 60
5 4 3 2 1
 5 4 3 2 1

RV1 1 GC6@ 2 0_0402_5% FB_GC6_EN_R

4 GPIO52
RV2 1 GC6@ 2 0_0402_5% GPU_EVENT#
4 GPIO53

9 PCIE_CRX_GTX_N[0..3]

9 PCIE_CRX_GTX_P[0..3]

9 PCIE_CTX_C_GRX_N[0..3]
UV1A
9 PCIE_CTX_C_GRX_P[0..3]
+3VGS
Part 1 of 6 1 RV175 2 0_0402_5%
H_THRMTRIP# 9
PCIE_CTX_C_GRX_P0 AG6 C6 FB_GC6_EN @
D PEX_RX0 GPIO0 FB_GC6_EN 23 D
+3VG_AON +3VG_AON PCIE_CTX_C_GRX_N0 AG7 B2

.1U_0402_10V6-K
1
PCIE_CTX_C_GRX_P1 AF7 PEX_RX0_N GPIO1 D6
PEX_RX1 GPIO2 1
PCIE_CTX_C_GRX_N1 AE7 C7 RV4
PCIE_CTX_C_GRX_P2 AE9 PEX_RX1_N GPIO3 F9 10K_0402_5% CV1
2

PCIE_CTX_C_GRX_N2 AF9 PEX_RX2 GPIO4 A3 3VGS_PWR_EN @ @

3VGS_PWR_EN 21,58

3
RV3 RV5 PCIE_CTX_C_GRX_P3 AG9 PEX_RX2_N GPIO5 A4 GPU_EVENT#_R D 2

2
5
2.2K_0402_5% 2.2K_0402_5% PCIE_CTX_C_GRX_N3 AG10 PEX_RX3 GPIO6 B6 5

G
OPT@ OPT@ AF10 PEX_RX3_N GPIO7 E9 SYS_PEX_RST_MON# G
AE10 NC81 GPIO8 F8 VGA_ALERT#
A6 Symbol update to OVER QV2B
1

6
AE12 NC82 GPIO9 C5 D S 2N7002KDWH_SOT363-6

4
VGA_SMB_CK2 4
S
3 AF12 NC83 GPIO10 E7 NVVDD_PWM_VID DV1 OVERT# 2 @
EC_SMB_CK2 7,39,44 NC84 GPIO11 NVVDD_PWM_VID 58

D
AG12 D7 VGA_AC_DET_R 2 1 G
NC85 GPIO12 VGA_AC_DET 44
AG13 B4 PSI_VGA_R @ QV2A

GPIO
QV1B AF13 NC86 GPIO13 B3 RB751V-40_SOD323-2 S 2N7002KDWH_SOT363-6

1
2N7002KDWH_SOT363-6 AE13 NC87 GPIO14 C3 @
2 RV6
2

OPT@ AE15 NC88 GPIO15 D5 1 PSI_VGA

G

PSI_VGA 58

1
RV7 2 @ 1 0_0402_5% AF15 NC1 GPIO16 D4 N15SGT@ 0_0402_5% D
AG15 NC2 GPIO17 C2 PLT_RST_VGA# 1 RV8 2 0_0402_5% 2

.1U_0402_10V6-K
NC3 GPIO18 1
AG16 F7 @ G
VGA_SMB_DA2 1 6 AF16 NC4 GPIO19 E6 QV3 CV2

.1U_0402_10V6-K
S

EC_SMB_DA2 7,39,44 NC5 GPIO20

D

AE16 C4 GPU_PEX_RST_HOLD# S 2N7002KW_SOT323-3 @

3
AE18 NC6 GPIO21 @ 2
NC7 1
QV1A AF18 A6 OVERT# CV3
2N7002KDWH_SOT363-6 AG18 NC8 OVERT AB6
AG19 NC9 NC33 @
OPT@
RV9 2 @ 1 0_0402_5% PU AT EC SIDE, +3VS AND 4.7K AF19 NC10 2
AE19 NC11 PLT_RST_VGA# 1 RV174 2 0_0402_5%
AE21 NC12 AG3 @

.1U_0402_10V6-K
+3VS AF21 NC13 NC97 AF4
NC14 NC98 1
AG21 AF3 CV218

2
AG22 NC15 NC99

G
+3VGARST RV10 2 @ 1 0_0402_5% NC16 @ +3VG_AON +3VG_AON
2
+3VG_AON PCIE_CRX_GTX_P0 CV10 1 2 .1U_0402_10V6-K PCIE_CRX_C_GTX_P0 AC9 AE3

DACs
@ PCIE_CRX_GTX_N0 CV13 1 2 .1U_0402_10V6-K PCIE_CRX_C_GTX_N0 AB9 PEX_TX0 NC100 AE4 OVERT# 3 1
PEX_TX0_N NC101 WRST# 44

D
RV12 2 1 0_0402_5% PCIE_CRX_GTX_P1 CV8 1 2 .1U_0402_10V6-K PCIE_CRX_C_GTX_P1 AB10
PCIE_CRX_GTX_N1 CV9 1 2 .1U_0402_10V6-K PCIE_CRX_C_GTX_N1 AC10 PEX_TX1
QV23

2
PEX_TX1_N

.01U_0402_16V7-K
PCI EXPRESS
PCIE_CRX_GTX_P2 CV6 1 2 .1U_0402_10V6-K PCIE_CRX_C_GTX_P2 AD11

.1U_0402_10V6-K
C 1 1 C
1 2 AC11 PEX_TX2 W5 2N7002KW_SOT323-3

CV221
PCIE_CRX_GTX_N2 CV7 .1U_0402_10V6-K PCIE_CRX_C_GTX_N2 RV13
CV11 PCIE_CRX_GTX_P3 CV4 1 2 .1U_0402_10V6-K PCIE_CRX_C_GTX_P3 AC12 PEX_TX2_N NC102 AE2 10K_0402_5% CV12
1 @

2
.1U_0402_10V6-K PCIE_CRX_GTX_N3 CV5 1 2 .1U_0402_10V6-K PCIE_CRX_C_GTX_N3 AB12 PEX_TX3 NC103 AF2 GC6@ GC6@

G
2 OPT@ AB13 PEX_TX3_N NC104 2

1
AC13 NC89 @
AD14 NC90 2
UV2 AC14 NC91 GPU_EVENT#_R 3 1 GPU_EVENT#
NC92

D
AC15
PLT_RST# 1 5 AB15 NC93 QV4
8,37,40,44 PLT_RST# B VCC AB16 NC94 B7 VGA_CRT_CLK
nVidia suggest add CV221 2N7002KW_SOT323-3
2 AC16 NC95 I2CA_SCL A7 VGA_CRT_DATA GC6@
4 PXS_RST# A AD17 NC96 I2CA_SDA
I2C,if not use, can be soft grounded
Connect to CPU GPIO
3 4 SYS_PEX_RST_MON# AC17 NC17 C9 I2CB_SCL 1 2 RV15
GND Y AC18 NC18 I2CB_SCL C8 I2CB_SDA
and delete pull up resistor ---colin @ 0_0402_5%
2

NC19 I2CB_SDA

I2C
AB18
RV14 AB19 NC20 A9 I2CC_SCL
201312091 nVidia suggest
74LVC1G08GW_SOT353-1-5 NC21 I2CC_SCL
OPT@
10K_0402_5% AC19
NC22 I2CC_SDA
B9 I2CC_SDA Please add a bypass on OVERT#
OPT@ AD20
AC20 NC23 D9 VGA_SMB_CK2 2.Please install RV13, QV4 and un-install +3VG_AON +3VG_AON
1

NC24 I2CS_SCL
AC21
AB21 NC25 I2CS_SDA
D8 VGA_SMB_DA2 RV15 to avoid current leakage at
AD23 NC26
NC27 Internal Thermal Sensor GPU OPTIMUS OFF.
AE23 VGA_CRT_DATA RV17 1 2 3VGS_PWR_EN RV18 2 1
AF24 NC28 60mA OPT@ 2.2K_0402_5% OPT@ 10K_0402_5%
1 2 RV16 AE24 NC29 L6 +PLLVDD VGA_CRT_CLK RV19 1 2 OVERT# RV20 1 2
@ 0_0402_5% AG24 NC30 CORE_PLLVDD M6 OPT@ 2.2K_0402_5% OPT@ 10K_0402_5%
AG25 NC31 SP_PLLVDD I2CB_SCL RV22 1 2 VGA_ALERT# RV23 1 2
NC32 N6
45mA 1 2 RV24 +SP_PLLVDD OPT@ 2.2K_0402_5% OPT@ 10K_0402_5%
nVidia suggest RV180 change to 2.2K 20131216 VID_PLLVDD @ 0_0402_5% I2CB_SDA RV25 1 2 VGA_AC_DET_R RV26 1 2
45mA OPT@ 2.2K_0402_5% OPT@ 100K_0402_5%
+3VGS +3VG_AON CLK_PCIE_GPU AE8 I2CC_SCL RV28 1 2 PSI_VGA RV29 1 2
8 CLK_PCIE_GPU PEX_REFCLK
CLK_PCIE_GPU# AD8 OPT@ 2.2K_0402_5% OPT@ 10K_0402_5%
8 CLK_PCIE_GPU# PEX_REFCLK_N
CLK_REQ_GPU# AC6 I2CC_SDA RV30 1 2 GPU_PEX_RST_HOLD# RV31 1 2
PEX_CLKREQ_N OPT@ 2.2K_0402_5% OPT@ 10K_0402_5%
1 2 RV32 AF22 RV33 1 2

CLK
PEX_TSTCLK_OUT XTALOUT
Differential signal @ 200_0402_1% PEX_TSTCLK_OUT# AE22 PEX_TSTCLK C11 XTAL_IN @ 10K_0402_5%
2

PEX_TSTCLK_N XTAL_IN
2

B10 XTAL_OUT
B
RV37 XTAL_OUT B
RV180
10K_0402_5% PLT_RST_VGA# AC7 A10 XTALSSIN 1 OPT@ 2 RV34 10K_0402_5%
nVidia suggest RV180 change to 2.2K 20131216
2.2K_0402_5% PEX_RST_N XTAL_SSIN
GC6@ @ 1 2 RV35 PEX_TERMP AF25 C10 XTALOUT 1 OPT@ 2 RV36 10K_0402_5% Under GPU(below 150mils)
DV6 PEX_TERMP XTAL_OUTBUFF
OPT@ 2.49K_0402_1% 180ohms (ESR=0.2) Bead
1
1

GPU_PEX_RST_HOLD# 2
1 PLT_RST_VGA# N15S-GT-S-A2_FCBGA595 +SP_PLLVDD 1 2 LV1
+1.05VGS
SYS_PEX_RST_MON# 3 N15SGT@ PBY160808T-181Y-N_2P

22U_0805_6.3V6M
150mA

4.7U_0402_6.3V6M
0.1U_0402_10V7K

0.1U_0402_10V7K
1 1 1 1
CV15 CV16 CV17 CV18 OPT@
BAT54AWT1G_SOT323-3
GC6@
2 2 2 2
OPT@ OPT@ OPT@ OPT@
1 2 RV39
N15VGM@ 0_0402_5% UV1 N15VGM@

1 2 RV38
change to BAT54A for cost down OPT@ 10M_0402_5%
YV1
NV N15V-GM GPU Under GPU Near GPU 30ohms (ESR=0.05) Bead
+3VG_AON +3VG_AON SA000064R00 XTAL_IN 1 4
OSC1 GND2 +PLLVDD 1 2 LV2 +1.05VGS
2 3 XTAL_OUT
GND1 OSC2

10P_0402_50V8J

10P_0402_50V8J
1 1 PBY160808T-300Y-N_2P
2

1 1 OPT@
RV40 RV41 CV19 CV20 CV21 CV22
10K_0402_5% 10K_0402_5% OPT@ 27MHZ_10PF_7V27000050 OPT@ 0.1U_0402_10V7K 22U_0805_6.3V6M
OPT@ @ OPT@ 2 2 OPT@
OPT@
2 2
1

+3VG_AON +3VG_AON
.1U_0402_10V6-K

.1U_0402_10V6-K

1 1
CV23 CV24
OPT@ @
2

2
2

A 2 RV44 2 RV45 A
G

10K_0402_5% 10K_0402_5%
OPT@ @
1

1 3 CLK_REQ_GPU# FB_GC6_EN_R 1 3 FB_GC6_EN

8 GPU_CLKREQ#
D

QV5 QV6
2

2N7002KW_SOT323-3 2N7002KW_SOT323-3
OPT@ RV46 @ RV47
10K_0402_5% 10K_0402_5%
@
Connect to CPU GPIO GC6@
Security Classification LC Future Center Secret Data Title
1 2 RV48 1 2 RV49
1

@ 0_0402_5% GC6@ 0_0402_5%

Issued Date 2014/06/28 Deciphered Date 2015/06/28 N15X_PCIE/ DAC/ GPIO
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BILG1/AILG1/AILZ1
Date: Thursday, July 17, 2014 Sheet 19 of 60
5 4 3 2 1
 5 4 3 2 1

D D

UV1C

Part 3 of 6 F11
AC3 NC50 AD10
AC4 NC105 NC51 AD7
Y4 NC106 NC52
Y3 NC107 V5
B19 Symbol update to FBA_CMD32
AA3 NC108 FERMI_RSVD1 V6
AA2 NC109 FERMI_RSVD2 G1
AB1 NC110 NC56 G2
NC111 NC57

NC
AA1 G3
AA4 NC112 NC58 G4
AA5 NC113 NC59 G5
NC114 NC60 G6
NC61 G7
AB5 NC62 V1
AB4 NC115 NC63 V2
AB3 NC116 NC64 W1
AB2 NC117 NC65 W2
AD3 NC118 NC66 W3
AD2 NC119 NC67 W4
AE1 NC120 NC68
AD1 NC121
AD4 NC122
AD5 NC123
NC124 D11 2 1 RV50
BUFRST_N @ 10K_0402_5%

LVDS/TMDS
T2
T3 NC125 D10
T1 NC126 PGOOD
R1 NC127 E10
R2 NC128 NC71

GENERAL
R3 NC129 F10
N2 NC130 NC72
N3 NC131 Symbol update to GPIO8
NC132 D1 STRAP0
STRAP0 STRAP0 28
C D2 STRAP1 C
V3 STRAP1 E4 STRAP1 28
STRAP2
NC133 STRAP2 STRAP2 28
V4 E3 STRAP3
NC134 STRAP3 STRAP3 28
U3 D3 STRAP4
U4 NC135 STRAP4 C1 STRAP4 28
T4 NC136 NC73
T5 NC137
R4 NC138 F6 1 2 RV51
R5 NC139 MULTI_STRAP_REF0_GND F4 N15SGT@ 40.2K_0402_1%
NC140 MULTI_STRAP_REF1_GNDMLS_REF1 F5
MULTI_STRAP_REF2_GND
N1
M1 NC34
M2 NC35 F12
M3 NC36 THERMDP
K2 NC37 E12
K3 NC38 THERMDN
K1 NC39
J1 NC40
NC41

M4 F2 VCCSENSE_VGA
NC42 VDD_SENSE VCCSENSE_VGA 58
M5
L3 NC43
NC44 trace width: 16mils
L4
K4 NC45 differential voltage sensing.
NC46 differential signal routing.
K5
J4 NC47 F1 VSSSENSE_VGA
NC48 GND_SENSE VSSSENSE_VGA 58

J5
N4 NC49
N5 NC141
NC142
TEST
P3 AD9 TESTMODE 1 OPT@ 2 RV52
P4 NC143 TESTMODE AE5 @ 1 10K_0402_5%
B NC144 JTAG_TCK TV1 B
AE6 @ 1
JTAG_TDI AF6 1 TV2
@
JTAG_TDO TV3
J2 AD6 @ 1
J3 NC145 JTAG_TMS AG4 1TV4 2 RV53
NC146 JTAG_TRST_N OPT@ 10K_0402_5%

H3
H4 NC147
NC148 SERIAL
D12 @ 1
ROM_CS_N TV5
B12 ROM_SI
ROM_SI A12 ROM_SI 28
ROM_SO
ROM_SO ROM_SO 28
C12 ROM_SCLK
ROM_SCLK ROM_SCLK 28

N15S-GT-S-A2_FCBGA595
N15SGT@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/06/28 Deciphered Date 2015/06/28 N15X_LVDS/ HDMI/ THERM

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BILG1/AILG1/AILZ1
Date: Wednesday, July 16, 2014 Sheet 20 of 60
5 4 3 2 1
 5 4 3 2 1

UV1D
Near GPU
+1.35VGS Near GPU Under GPU(below 150mils)
2000mA +1.05VGS
3.5A Part 4 of 6
B26 AA10 For RF
C25 FBVDDQ_01 PEX_IOVDDQ_1 AA12

33P_0402_50V8J
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
22U_0805_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
0.1U_0402_10V7K

0.1U_0402_10V7K
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
E23 FBVDDQ_02 PEX_IOVDDQ_2 AA13

CV33

N15VGM@CV34

N15VGM@CV35

N15VGM@CV36

CV37

N15VGM@CV38

CV39

N15VGM@CV40

N15VGM@CV41

N15VGM@CV42

CV215
1 1 1 1 1 1 2 2 2 2 1

1U_0603_25V6M

1U_0603_25V6M
E26 FBVDDQ_03 PEX_IOVDDQ_3 AA16

CV25

CV26

CV27

CV28

CV29

CV30

CV31

CV32
1 2 1 1 1 1 1 1 FBVDDQ_04 PEX_IOVDDQ_4
F14 AA18
F21 FBVDDQ_05 PEX_IOVDDQ_5 AA19
G13 FBVDDQ_06 PEX_IOVDDQ_6 AA20 2 2 2 2 2 2 1 1 1 1 2
2 1 2 2 2 2 2 2 G14 FBVDDQ_07 PEX_IOVDDQ_7 AA21 OPT@ OPT@ RF@
FBVDDQ_08 PEX_IOVDDQ_8 OPT@
@ OPT@ OPT@ OPT@ OPT@ @ OPT@ OPT@ G15 AB22
G16 FBVDDQ_09 PEX_IOVDDQ_9 AC23
D
G18 FBVDDQ_10 PEX_IOVDDQ_10 AD24
Under GPU(below 150mils) +1.05VGS PEX_IOVVDD/Q Decouling D
G19 FBVDDQ_11 PEX_IOVDDQ_11 AE25
G20 FBVDDQ_12 PEX_IOVDDQ_12 AF26 1 1 1 1 MLCC N15V-GM N15S-GT

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
G21 FBVDDQ_13 PEX_IOVDDQ_13 AF27

CV43

N15VGM@CV44

N15VGM@CV45

N15VGM@CV46
L22 FBVDDQ_14 PEX_IOVDDQ_14
Symbol update to FBVDDQ_AON L24 FBVDDQ_19
H24/H26/J21/K21 L26 FBVDDQ_20 AA22 2 2 2 2
Under Near +3VG_AON 1.0uF 4 1
M21 FBVDDQ_21 PEX_IOVDD_1 AB23
N21 FBVDDQ_22 PEX_IOVDD_2 AC24 OPT@
4.7uF 2 1

1U_0402_6.3V6K
.1U_0402_10V6-K

4.7U_0603_6.3V6K
R21 FBVDDQ_23 PEX_IOVDD_3 AD25

CV47

CV48

CV49
1 1 1

POWER
T21 FBVDDQ_24 PEX_IOVDD_4 AE26
V21 FBVDDQ_25 PEX_IOVDD_5 AE27
W21 FBVDDQ_26 PEX_IOVDD_6 10uF 4 1
FBVDDQ_27 2 2 2
Symbol update to 3V3_AON OPT@ OPT@ OPT@
H24 22uF 4 1
H26 FBVDDQ_AON_1 +3VG_AON
J21 FBVDDQ_AON_2 G10
FBVDDQ_AON_3 3V3_AON_1 Place near balls(Under GPU) Place near GPU
K21 G12
FBVDDQ_AON_4 3V3_AON_2 +3VGS
+1.05VS +1.05VGS
Reserve for GPU +1.05V AON6414AL_DFN8-5 V7 G8 +VDD33 RV54 1 2 0_0402_5%
NC149 3V3_MAIN_1 G9 @

.1U_0402_10V6-K

.1U_0402_10V6-K

1U_0402_6.3V6K

4.7U_0603_6.3V6K
1 3V3_MAIN_2 +1.35VGS

CV50

CV51

CV52

CV53
1 1 1 1
2 W7
5 3 AA6 NC150
NC151 Change RV9 to 0ohm jump
W6 D22 1 2 RV55
Y6 NC152 FB_CAL_VDDQ OPT@ 40.2_0402_1% 2 2 2 2
QV7 OPT@ NC153 OPT@ OPT@ OPT@ OPT@
1

4
CV220 C24 1 2 RV56
0.1U_0402_16V4Z FB_CAL_GND OPT@ 42.2_0402_1%
+20VSB @
2 M7 B25 1 2 RV57 CALIBRATION PIN DDR3
+5VALW 1 OPT@ 2 RV58 N7 NC154 FB_CAL_TERM OPT@ 51.1_0402_1%
NC155

1
100K_0402_5% T6
RV59 P6 NC156 FB_CAL_x_PD_VDDQ 40.2Ohm

1
71.5_0603_1% NC157
RV60 1 Place near balls
1

D CV54 RV61 @
C
1 2 1.05VGS_EN# 2 QV8 0.01U_0402_25V7K 120K_0402_5%
FB_CAL_x_PU_GND 42.2Ohm C

2
G N15SGT@ OPT@ T7 +3VG_AON
2 R7 NC158
Under GPU(below 150mils) FB_CAL_xTERM_GND 51.1Ohm
47K_0402_5% OPT@ S 2 U6 NC159
3

OPT@ 2N7002KW_SOT323-3 R6 NC160 AA8

.1U_0402_10V6-K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
1
D NC161 PEX_PLL_HVDD_1 AA9

CV55

CV56

CV57
PEX_PLL_HVDD_2 1 1 1
1

D 1.05VGS_EN# 2 QV10
2 QV9 G 2N7002KW_SOT323-3 AB8
57 1.05VGS_EN G PEX_SVDD_3V3
@
S 2 2 2

3
OPT@ S J7 OPT@ OPT@ OPT@ +1.05VGS
120mA 120ohm (ESR=0.18) Bead
3

2N7002KW_SOT323-3 K7 NC76
CV54 N15VGM@ K6 NC77 AA14 +PEX_PLLVDD 2 @ 1 LV3
H6 NC78 PEX_PLLVDD_1 AA15 HCB1608KF-121T30_0603

1U_0603_25V6M
.1U_0402_10V6-K

4.7U_0805_25V6-K
J6 NC79 PEX_PLLVDD_2

CV58

CV59

CV60
NC80 1 1 1
@
2 1 RV62
0_0603_5%
S CER CAP .1U 16V Z Y5V 0402 2 2 2
SE070104Z8J OPT@ OPT@ OPT@
N15S-GT-S-A2_FCBGA595
N15SGT@
follow NV GPU rise time Place near balls
+3.3VS TO +3VG_AON

+3VS +3VG_AON

+5VALW
S

3 1
1

QV11 OPT@
1

B B
RV63 OPT@
G

1 1 1
2

47K_0402_5% @ LP2301ALT1G_SOT23-3 CV62 RV64 CV63

CV61 0.01U_0402_25V7K 470_0603_5% 10U_0603_6.3V6M +1.35V +1.35VGS
.1U_0402_10V6-K @ @ OPT@ +1.35V TO +1.35VGS AON6414AL_DFN8-5
2

2 2 2
2

PXS_PWREN# 1 2 RV65 1
10K_0402_5% 2
OPT@ 1 5 3
1

QV12 D OPT@ CV67 CV68 CV69 CV70

220U_B2_2.5VM_R15M
1

2 OPT@ CV64 QV13 D CV65 CV66 1

.1U_0402_16V7K
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
4,58 PXS_PWREN

1
G .1U_0402_10V6-K PXS_PWREN# 2 1 1 QV14 OPT@ 1 1 1

4
2 G + RV67
1

S 2N7002KW_SOT323-3 470_0603_5%
3

@ S 2N7002KW_SOT323-3 @
3

2 2 2 2 2 2

@
OPT@

OPT@

OPT@

OPT@
RV66 OPT@

2
100K_0402_5%
2

+20VSB

1
+5VALW D
1 OPT@ 2 RV68 FBVDDQ_PWR_EN# 2 QV15
100K_0402_5% G 2N7002KW_SOT323-3
@

1
+3VG_AON +3VGS S
RV69 1

3
1
D RV70
+3.3VS TO +3VGS 1 2 FBVDDQ_PWR_EN# 2 QV17 CV71 120K_0402_5%
G 2N7002KW_SOT323-3 0.01U_0402_25V7K OPT@
OPT@ 2 OPT@

2
RV171 1 2 47K_0402_5% S

3
0_0603_5% OPT@
N15VGM@

1
D
+5VALW 2 QV18
23 FBVDDQ_PWR_EN
S

3 1 G 2N7002KW_SOT323-3
QV16 GC6@ OPT@
1

3
1

RV71 GC6@
G

1 1 1
2

A 47K_0402_5% @ CV73 RV72 CV74 A

.1U_0402_10V6-K CV72 LP2301ALT1G_SOT23-3 0.01U_0402_25V7K 470_0603_5% 10U_0603_6.3V6M
@ GC6@
2

RV73 2 2 2
GC6@
2

DGPU_PWR_EN# 1 2

4.7K_0402_5% 1
1

QV19 D GC6@ GC6@

1

2 GC6@ CV75 QV20 D

19,58 3VGS_PWR_EN G .1U_0402_10V6-K 2
DGPU_PWR_EN#
2 G
Security Classification LC Future Center Secret Data Title
1

S 2N7002KW_SOT323-3
3

@ S 2N7002KW_SOT323-3
Issued Date 2014/06/28 Deciphered Date 2015/06/28 N15X_Power
3

RV74 N15SGT@
100K_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
2

C 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BILG1/AILG1/AILZ1
Date: Thursday, July 17, 2014 Sheet 21 of 60
5 4 3 2 1
 5 4 3 2 1

D D

UV1E
UV1F
A2 Part 5 of 6 K11 +VGA_CORE +VGA_CORE
A26 GND_001 GND_057 K13 Part 6 of 6
AB11 GND_002 GND_058 K15
AB14 GND_003 GND_059 K17 K10 V18
AB17 GND_004 GND_060 L10 K12 VDD_001 VDD_041 V16
AB20 GND_005 GND_061 L12 +VGA_CORE K14 VDD_002 VDD_040 V14
AB24 GND_006 GND_062 L14 K16 VDD_003 VDD_039 V12
GND_007 GND_063 Under GPU VDD_004 VDD_038
AC2 L16 K18 V10
AC22 GND_008 GND_064 L18 L11 VDD_005 VDD_037 U17
GND_009 GND_065 VDD_006 VDD_036

POWER
AC26 L2 L13 U15
AC5 GND_010 GND_066 L23 L15 VDD_007 VDD_035 U13

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
AC8 GND_011 GND_067 L25 L17 VDD_008 VDD_034 U11
AD12 GND_012 GND_068 L5 M10 VDD_009 VDD_033 T18
GND_013 GND_069 1 1 1 1 1 1 1 1 1 1 1 1 1 VDD_010 VDD_032
AD13 M11 M12 T16

CV76

CV77

CV78

CV79

CV80

CV81

CV82

CV83

CV84

CV85

CV86

CV87

CV88
AD15 GND_014 GND_070 M13 M14 VDD_011 VDD_031 T14
AD16 GND_015 GND_071 M15 M16 VDD_012 VDD_030 T12
AD18 GND_016 GND_072 M17 2 2 2 2 2 2 2 2 2 2 2 2 2 M18 VDD_013 VDD_029 T10
AD19 GND_017 GND_073 N10 N11 VDD_014 VDD_028 R17
AD21 GND_018 GND_074 N12 OPT@ OPT@ OPT@ OPT@ OPT@ OPT@ OPT@ OPT@ OPT@ OPT@ @ @ @ N13 VDD_015 VDD_027 R15
AD22 GND_019 GND_075 N14 N15 VDD_016 VDD_026 R13
AE11 GND_020 GND_076 N16 N17 VDD_017 VDD_025 R11
AE14 GND_021 GND_077 N18 P10 VDD_018 VDD_024 P18
AE17 GND_022 GND_078 P11 P12 VDD_019 VDD_023 P16
GND_023 GND_079 For RF VDD_020 VDD_022
AE20 P13 P14

33P_0402_50V8J
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
AF1 GND_024 GND_080 P15 VDD_021

CV89

CV90

CV91

CV92

CV213
GND_025 GND_081 1 1 1 1 1
AF11 P17
GND

AF14 GND_026 GND_082 P2

AF17 GND_027 GND_083 P23
AF20 GND_028 GND_084 P26 2 2 2 2 2
C C
AF23 GND_029 GND_085 P5 OPT@ OPT@ OPT@ OPT@ RF@
AF5 GND_030 GND_086 R10
AF8 GND_031 GND_087 R12
AG2 GND_032 GND_088 R14
AG26 GND_033 GND_089 R16 N15S-GT-S-A2_FCBGA595
B1 GND_034 GND_090 R18 N15SGT@

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
B11 GND_035 GND_091 T11
B14 GND_036 GND_092 T13
GND_037 GND_093 1 1 1 1 1 1 1 1 1 1
B17 T15

CV93

CV94

CV95

CV96

CV97

CV98

CV99

CV100

CV101

CV102
B20 GND_038 GND_094 T17
B23 GND_039 GND_095 U10
B27 GND_040 GND_096 U12 2 2 2 2 2 2 2 2 2 2
B5 GND_041 GND_097 U14
B8 GND_042 GND_098 U16 OPT@ OPT@ OPT@ @ @ @ @ @ @ @
E11 GND_043 GND_099 U18
E14 GND_044 GND_100 U2
E17 GND_045 GND_101 U23
E2 GND_046 GND_102 U26 For RF
22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
E20 GND_047 GND_103 U5

33P_0402_50V8J
E22 GND_048 GND_104 V11
CV103

CV104

CV105

CV214
GND_049 GND_105 1 1 1 1
E25 V13
E5 GND_050 GND_106 V15
E8 GND_051 GND_107 V17
H2 GND_052 GND_108 Y2 2 2 2 2
H23 GND_053 GND_109 Y23 OPT@ OPT@ @ RF@
H25 GND_054 GND_110 Y26
H5 GND_055 GND_111 Y5
GND_056 GND_112

Near GPU
AA7
GND_113 AB7
GND_114

N15S-GT-S-A2_FCBGA595
B B
N15SGT@

+3VGS

2
RV176
10K_0402_5%
@

1
+VGA_CORE DV5
+3VG_AON
+5VALW 2
57 +1.05VGS_PWRGD 1
@
VGA_PWRGD 9,44
1

2 1 3
RV173 +5VALW
2

470_0603_5% RV179 10K_0402_5%

RV178 BAT54AWT1G_SOT323-3
1

RV172 @ D
47K_0402_5% 1 2 2 QV25 @
1 2

@ G 2N7002KW_SOT323-3
D @
1

2 QV22 47K_0402_5% S
3

G @
1

D
2 QV21 @ S
57,58 EN_VGA
3

G 2N7002KW_SOT323-3 +1.35VGS
1

C
@ S RV177 1 @ 2 2 QV24
3

2N7002KW_SOT323-3 2.2K_0402_5% B MMBT3904WH_SOT323-3

CV219

.1U_0402_10V6-K

E
3

1 @
A A

2
@

Security Classification LC Future Center Secret Data Title

Issued Date 2014/06/28 Deciphered Date 2015/06/28 N15X_+VGA CORE, GND

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BILG1/AILG1/AILZ1
Date: Wednesday, July 16, 2014 Sheet 22 of 60
5 4 3 2 1
 5 4 3 2 1

FBA_D[0..63]
24,25,26,27 FBA_D[0..63]

24,25,26,27 FBA_DQM[7..0]
24,25,26,27 FBA_DQS[7..0]
24,25,26,27 FBA_DQS#[7..0]

24,25,26,27 FBA_CMD[30..0]

UV1B
D D

Part 2 of 6

FBA_D0 E18 C27 FBA_ODT_L +1.35VGS

FBA_D00 FBA_CMD00 FBA_ODT_L 24,26
FBA_D1 F18 C26 FBA_CS1#_L
E16 FBA_D01 FBA_CMD01 E24 FBA_CS1#_L 26
FBA_D2 FBA_CS0#_L
FBA_D02 FBA_CMD02 FBA_CS0#_L 24
FBA_D3 F17 F24 FBA_CKE_L
D20 FBA_D03 FBA_CMD03 D27 FBA_CKE_L 24,26
FBA_D4 FBA_CMD4
FBA_D5 D21 FBA_D04
FBA_D05
FBA_CMD04
FBA_CMD05
D26 FBA_CMD5 CMD mapping mod Mode E
FBA_D6 F20 F25 FBA_CMD6 FBA_CMD4 RV75 1 OPT@ 2 100_0402_5%

0.1U_0402_10V7K
E21 FBA_D06 FBA_CMD06 F26 RV76 1 OPT@ 2 100_0402_5%
FBA_D7 FBA_CMD7 Rank0 Rank1

CV106
FBA_D07 FBA_CMD07 1
FBA_D8 E15 F23 FBA_CMD8
D15 FBA_D08 FBA_CMD08 G22 RV77 1 OPT@ 2 100_0402_5%
FBA_D9
FBA_D09 FBA_CMD09
FBA_CMD9 FBA_CMD5 Address 0..31 32..63 0..31 32..63
FBA_D10 F15 G23 FBA_CMD10 RV78 1 OPT@ 2 100_0402_5%
F13 FBA_D10 FBA_CMD10 G24 2
FBA_D11
FBA_D11 FBA_CMD11
FBA_RAS#
FBA_RAS# 24,25,26,27 FBx_CMD0 ODT_L ODT_L
FBA_D12 C13 F27 FBA_CMD12 FBA_CMD6 RV79 1 OPT@ 2 100_0402_5%
FBA_D12 FBA_CMD12
FBA_D13 B13
FBA_D13 FBA_CMD13
G25 FBA_CMD13 RV80 1 OPT@ 2 100_0402_5% @ FBx_CMD1 CS1#_L
FBA_D14 E13 G27 FBA_CMD14
FBA_D14 FBA_CMD14
FBA_D15 D13
FBA_D15 FBA_CMD15
G26 FBA_CAS#
FBA_CAS# 24,25,26,27
FBA_CMD7 RV81 1 OPT@ 2 100_0402_5% FBx_CMD2 CS0#_L
FBA_D16 B15 M24 FBA_ODT_H RV82 1 OPT@ 2 100_0402_5%

0.1U_0402_10V7K
C16 FBA_D16 FBA_CMD16 M23 FBA_ODT_H 25,27
FBA_D17 FBA_CS1#_H FBx_CMD3 CKE_L CKE_L

CV107
FBA_D17 FBA_CMD17 FBA_CS1#_H 27 1
FBA_D18 A13 K24 FBA_CS0#_H FBA_CMD8 RV83 1 OPT@ 2 100_0402_5%
A15 FBA_D18 FBA_CMD18 K23 FBA_CS0#_H 25
FBA_D19 FBA_CKE_H RV84 1 OPT@ 2 100_0402_5% FBx_CMD4 A9 A9 A11 A11
FBA_D19 FBA_CMD19 FBA_CKE_H 25,27
FBA_D20 B18 M27 FBA_RST#
FBA_D20 FBA_CMD20 FBA_RST# 24,25,26,27 2
FBA_D21 A18 M26 FBA_CMD21 FBA_CMD9 RV85 1 OPT@ 2 100_0402_5% FBx_CMD5 A6 A6 A7 A7
FBA_D22 A19 FBA_D21 FBA_CMD21 M25 FBA_CMD22 RV86 1 OPT@ 2 100_0402_5%
FBA_D22 FBA_CMD22
FBA_D23 C19
FBA_D23 FBA_CMD23
K26 FBA_CMD23 @ FBx_CMD6 A3 A3 BA1 BA1
FBA_D24 B24 K22 FBA_CMD24 FBA_CMD10 RV87 1 OPT@ 2 100_0402_5%
FBA_D24 FBA_CMD24
FBA_D25 C23
FBA_D25 FBA_CMD25
J23 FBA_CMD25 RV88 1 OPT@ 2 100_0402_5% FBx_CMD7 A0 A0 A12 A12
FBA_D26 A25 J25 FBA_CMD26
A24 FBA_D26 FBA_CMD26 J24 RV89 1 OPT@ 2 100_0402_5%
FBA_D27
FBA_D27 FBA_CMD27
FBA_CMD27 FBA_RAS# FBx_CMD8 A8 A8 A8 A8
FBA_D28 A21 K27 FBA_CMD28 RV90 1 OPT@ 2 100_0402_5%

0.1U_0402_10V7K
B21 FBA_D28 FBA_CMD28 K25
FBA_D29 FBA_CMD29 FBx_CMD9 A12 A12 A0 A0

CV108
FBA_D29 FBA_CMD29 1
FBA_D30 C20 J27 FBA_CMD30 FBA_CMD12 RV91 1 OPT@ 2 100_0402_5%
C21 FBA_D30 FBA_CMD30 J26 RV92 1 OPT@ 2 100_0402_5%
FBA_D31
FBA_D31 FBA_CMD31 FBx_CMD10 A1 A1 A2 A2
C
FBA_D32
FBA_D33
R22
R24 FBA_D32 FBA_CMD32
B19
Symbol update to +1.35VGS
FBA_CMD34/35 FBA_CMD13 RV93 1 OPT@ 2 100_0402_5% 2
FBx_CMD11 RAS# RAS# RAS# RAS# C
FBA_D33

INTERFACE A
FBA_D34 T22 F22 RV121 2 @ 1 60.4_0402_1% RV94 1 OPT@ 2 100_0402_5%
FBA_D34 FBA_CMD34
FBA_D35 R23
FBA_D35 FBA_CMD35
J22 RV122 2 1 60.4_0402_1% @ FBx_CMD12 A13 A13 A14 A14
FBA_D36 N25 @ FBA_CMD14 RV95 1 OPT@ 2 100_0402_5%
N26 FBA_D36 D19 RV96 1 OPT@ 2 100_0402_5%
FBA_D37 FBA_DQM0 FBx_CMD13 BA1 BA1 A3 A3

MEMORY
FBA_D38 N23 FBA_D37 FBA_DQM0 D14 FBA_DQM1
N24 FBA_D38 FBA_DQM1 C17 RV97 1 OPT@ 2 100_0402_5%
30ohms (ESR=0.01) Bead FBA_D39
FBA_D39 FBA_DQM2
FBA_DQM2 FBA_CAS# FBx_CMD14 A14 A14 A13 A13
FBA_D40 V23 C22 FBA_DQM3 RV98 1 OPT@ 2 100_0402_5%

0.1U_0402_10V7K
V22 FBA_D40 FBA_DQM3 P24
FBA_D41 FBA_DQM4 FBx_CMD15 CAS# CAS# CAS# CAS#

CV109
FBA_D41 FBA_DQM4 1
+1.05VGS +FB_PLLAVDD FBA_D42 T23 W24 FBA_DQM5 FBA_CMD21 RV99 1 OPT@ 2 100_0402_5%
FBA_D42 FBA_DQM5
200mA FBA_D43 U22
FBA_D43 FBA_DQM6
AA25 FBA_DQM6 RV100 1 OPT@ 2 100_0402_5% FBx_CMD16 ODT_H ODT_H
FBA_D44 Y24 U25 FBA_DQM7
FBA_D44 FBA_DQM7 2
1 2 LV4 FBA_D45 AA24
FBA_D45
FBA_CMD22 RV101 1 OPT@ 2 100_0402_5% FBx_CMD17 CS1#_H
HCB1608KF-300T60_2P FBA_D46 Y22 F19 FBA_DQS#0 RV102 1 OPT@ 2 100_0402_5%
AA23 FBA_D46 FBA_DQS_RN0 C14
OPT@ FBA_D47
FBA_D47 FBA_DQS_RN1
FBA_DQS#1 @ FBx_CMD18 CS0#_H
FBA_D48 AD27 A16 FBA_DQS#2 FBA_CMD23 RV103 1 OPT@ 2 100_0402_5%
AB25 FBA_D48 FBA_DQS_RN2 A22 RV104 1 OPT@ 2 100_0402_5%
Place close to BGA FBA_D49
FBA_D49 FBA_DQS_RN3
FBA_DQS#3 FBx_CMD19 CKE_H CKE_H
FBA_D50 AD26 P25 FBA_DQS#4
AC25 FBA_D50 FBA_DQS_RN4 W22 RV105 1 OPT@ 2 100_0402_5%
FBA_D51
FBA_D51 FBA_DQS_RN5
FBA_DQS#5 FBA_CMD24 FBx_CMD20 RST RST RST RST
FBA_D52 AA27 AB27 FBA_DQS#6 RV106 1 OPT@ 2 100_0402_5%

0.1U_0402_10V7K
FBA_D52 FBA_DQS_RN6
Place close to BGA Place close to ball FBA_D53 AA26 T27 FBA_DQS#7 FBx_CMD21 A7 A7 A6 A6

CV110
FBA_D53 FBA_DQS_RN7 1
FBA_D54 W26 FBA_CMD25 RV107 1 OPT@ 2 100_0402_5%
FBA_D54
+FB_PLLAVDD FBA_D55 Y25
FBA_D55 FBA_DQS_WP0
E19 FBA_DQS0 RV108 1 OPT@ 2 100_0402_5% FBx_CMD22 A4 A4 A5 A5
FBA_D56 R26 C15 FBA_DQS1
22U_0805_6.3V6M

1U_0402_6.3V6K

0.1U_0402_10V7K

T25 FBA_D56 FBA_DQS_WP1 B16 RV109 1 OPT@ 2 100_0402_5% 2

FBA_D57 FBA_DQS2 FBA_CMD26 FBx_CMD23 A11 A11 A9 A9
CV111

CV112

CV113

1 1 1 FBA_D57 FBA_DQS_WP2
FBA_D58 N27 B22 FBA_DQS3 RV110 1 OPT@ 2 100_0402_5%
R27 FBA_D58 FBA_DQS_WP3 R25
FBA_D59
FBA_D59 FBA_DQS_WP4
FBA_DQS4 @ FBx_CMD24 A2 A2 A1 A1
FBA_D60 V26 W23 FBA_DQS5 FBA_CMD27 RV111 1 OPT@ 2 100_0402_5%
2 2 2 V27 FBA_D60 FBA_DQS_WP5 AB26 RV112 1 OPT@ 2 100_0402_5%
FBA_D61
FBA_D61 FBA_DQS_WP6
FBA_DQS6 FBx_CMD25 A10 A10 WE# WE#
FBA_D62 W27 T26 FBA_DQS7
FBA_D62 FBA_DQS_WP7
OPT@ OPT@ OPT@ FBA_D63 W25
FBA_D63
FBA_CMD28 RV113 1 OPT@ 2 100_0402_5% FBx_CMD26 A5 A5 A4 A4
D24 FBA_CLK0 RV114 1 OPT@ 2 100_0402_5%

0.1U_0402_10V7K
FBA_CLK0 FBA_CLK0 24,26
F16 D25 FBA_CLK0# FBx_CMD27 BA2 BA2

CV114
FB_PLLAVDD_1 FBA_CLK0_N FBA_CLK0# 24,26 1
P22 FBA_CMD29 RV115 1 OPT@ 2 100_0402_5%
FB_PLLAVDD_2 N22 RV116 1 OPT@ 2 100_0402_5%
FBA_CLK1
FBA_CLK1
FBA_CLK1 25,27 FBx_CMD28 WE# WE# A10 A10
D23 M22 FBA_CLK1#
FB_VREF FBA_CLK1_N FBA_CLK1# 25,27 2
+FB_PLLAVDD FBA_CMD30 RV117 1 OPT@ 2 100_0402_5% FBx_CMD29 BA0 BA0 BA0 BA0
Place close to ball D18 RV118 1 OPT@ 2 100_0402_5%
B
1 2 CV115 H22 FBA_WCK01 C18 B
FB_DLLAVDD FBA_WCK01_N
@ FBx_CMD30 BA2 BA2
OPT@ 0.1U_0402_10V7K D17
FB_GC6_EN RV119 1 @ 2 0_0402_5% FB_CLAMP F3 FBA_WCK23 D16
RV120 1 OPT@ 2 10K_0402_5% FB_CLAMP FBA_WCK23_N T24
FBA_WCK45 U24
FBA_WCK45_N V24
FBA_WCK67 V25
FBA_WCK67_N

N15S-GT-S-A2_FCBGA595
N15SGT@

RV123 DV4 GC6@

FB_GC6_EN 1 2 0_0402_5% GC6_EN 2
19 FB_GC6_EN
@ 1
FBVDDQ_PWR_EN 21
3
1

+3VGS RV124 1 2 BAV70W-7-F_SOT323-3

10K_0402_5% RV125
200K_0402_5%
OPT@ GC6@
1 2 RV126
57,58 DGPU_PWROK
2

0_0402_5%
A N15VGM@ A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/06/28 Deciphered Date 2015/06/28 N15X_MEM Interface

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BILG1/AILG1/AILZ1
Date: Wednesday, July 16, 2014 Sheet 23 of 60
5 4 3 2 1
 5 4 3 2 1

at least 16 mils width(optimal)

20 mils spacing to other signals /planes FBA_D[0..63] 23,25,26,27
+1.35VGS
D FBA_CMD[30..0] 23,25,26,27 D
1

RANKA@
FBA_DQM[7..0] 23,25,26,27
RV128
1.33K_0402_1% UV6 UV5
FBA_DQS[7..0] 23,25,26,27
2

+FBA_VREFCA0 +FBA_VREFCA0 M8 E3 FBA_D5 +FBA_VREFCA0 M8 E3 FBA_D11

+FBA_VREFCA0 26 VREFCA DQL0 VREFCA DQL0 FBA_DQS#[7..0] 23,25,26,27
+FBA_VREFDQ0 H1 F7 FBA_D1 +FBA_VREFDQ0 H1 F7 FBA_D13
1

VREFDQ DQL1 F2 FBA_D7 VREFDQ DQL1 F2 FBA_D8

1 DQL2 DQL2
RANKA@ CV116 FBA_CMD7 N3 F8 FBA_D0 FBA_CMD7 N3 F8 FBA_D15
RV127 .01U_0402_16V7-K FBA_CMD10 P7 A0
A1
DQL3
DQL4
H3 FBA_D4 Group0 FBA_CMD10 P7 A0
A1
DQL3
DQL4
H3 FBA_D10 Group1 CMD mapping mod Mode E
1.33K_0402_1% RANKA@ FBA_CMD24 P3 H8 FBA_D3 FBA_CMD24 P3 H8 FBA_D14
2 A2 DQL5 A2 DQL5
FBA_CMD6 N2 G2 FBA_D6 FBA_CMD6 N2 G2 FBA_D9 Rank0 Rank1
2

FBA_CMD22 P8 A3 DQL6 H7 FBA_D2 FBA_CMD22 P8 A3 DQL6 H7 FBA_D12

A4 DQL7 A4 DQL7
FBA_CMD26 P2
A5
FBA_CMD26 P2
A5
Address 0..31 32..63 0..31 32..63
FBA_CMD5 R8 FBA_CMD5 R8
R2 A6 D7 R2 A6 D7
FBA_CMD21
A7 DQU0
FBA_D31 FBA_CMD21
A7 DQU0
FBA_D17 FBx_CMD0 ODT_L ODT_L
FBA_CMD8 T8 C3 FBA_D25 FBA_CMD8 T8 C3 FBA_D22
R3 A8 DQU1 C8 R3 A8 DQU1 C8
FBA_CMD4
A9 DQU2
FBA_D30 FBA_CMD4
A9 DQU2
FBA_D16 FBx_CMD1 CS1#_L
FBA_CMD25 L7 C2 FBA_D24 FBA_CMD25 L7 C2 FBA_D23 Group2
R7 A10/AP DQU3 A7 R7 A10/AP DQU3 A7
+1.35VGS FBA_CMD23
A11 DQU4
FBA_D29 Group3 FBA_CMD23
A11 DQU4
FBA_D19 FBx_CMD2 CS0#_L
FBA_CMD9 N7 A2 FBA_D27 FBA_CMD9 N7 A2 FBA_D21
A12/BC DQU5 A12/BC DQU5
FBA_CMD12 T3 B8 FBA_D28 FBA_CMD12 T3 B8 FBA_D18 FBx_CMD3 CKE_L CKE_L
1

FBA_CMD14 T7 A13 DQU6 A3 FBA_D26 FBA_CMD14 T7 A13 DQU6 A3 FBA_D20

A14 DQU7 A14 DQU7
RANKA@ FBx_CMD4 A9 A9 A11 A11
RV167 +1.35VGS +1.35VGS
1.33K_0402_1% FBx_CMD5 A6 A6 A7 A7
FBA_CMD29 M2 B2 FBA_CMD29 M2 B2
2

N8 BA0 VDD_1 D9 N8 BA0 VDD_1 D9

+FBA_VREFDQ0
+FBA_VREFDQ0 26
FBA_CMD13
BA1 VDD_2
FBA_CMD13
BA1 VDD_2 FBx_CMD6 A3 A3 BA1 BA1
FBA_CMD27 M3 G7 FBA_CMD27 M3 G7
1

BA2 VDD_3 K2 BA2 VDD_3 K2

1 VDD_4 VDD_4 FBx_CMD7 A0 A0 A12 A12
RANKA@ CV216 K8 K8
.01U_0402_16V7-K VDD_5 VDD_5
RV168
VDD_6
N1
VDD_6
N1 FBx_CMD8 A8 A8 A8 A8
1.33K_0402_1% RANKA@ FBA_CLK0 J7 N9 FBA_CLK0 J7 N9
2 23,26 FBA_CLK0 CK VDD_7 CK VDD_7
23,26 FBA_CLK0#
FBA_CLK0# K7 R1 FBA_CLK0# K7 R1 FBx_CMD9 A12 A12 A0 A0
2

FBA_CKE_L K9 CK VDD_8 R9 FBA_CKE_L K9 CK VDD_8 R9

23,26 FBA_CKE_L CKE VDD_9 CKE VDD_9
FBx_CMD10 A1 A1 A2 A2
C C
FBA_ODT_L K1 A1 FBA_ODT_L K1 A1 FBx_CMD11 RAS# RAS# RAS# RAS#
23,26 FBA_ODT_L ODT VDDQ_1 ODT VDDQ_1
FBA_CS0#_L L2 A8 FBA_CS0#_L L2 A8
23 FBA_CS0#_L CS VDDQ_2 CS VDDQ_2
FBA_RAS# J3 C1 FBA_RAS# J3 C1 FBx_CMD12 A13 A13 A14 A14
23,25,26,27 FBA_RAS# K3 RAS VDDQ_3 C9 K3 RAS VDDQ_3 C9
FBA_CAS# FBA_CAS#
23,25,26,27 FBA_CAS# CAS VDDQ_4 CAS VDDQ_4
FBA_CMD28 L3
WE VDDQ_5
D2 FBA_CMD28 L3
WE VDDQ_5
D2 FBx_CMD13 BA1 BA1 A3 A3
E9 E9
VDDQ_6 VDDQ_6
VDDQ_7
F1
VDDQ_7
F1 FBx_CMD14 A14 A14 A13 A13
FBA_DQS0 F3 H2 FBA_DQS1 F3 H2
C7 DQSL VDDQ_8 H9 C7 DQSL VDDQ_8 H9
FBA_CLK0 FBA_DQS3
DQSU VDDQ_9
FBA_DQS2
DQSU VDDQ_9 FBx_CMD15 CAS# CAS# CAS# CAS#
FBx_CMD16 ODT_H ODT_H
1

FBA_DQM0 E7 A9 FBA_DQM1 E7 A9
D3 DML VSS_1 B3 D3 DML VSS_1 B3
RV129 FBA_DQM3
DMU VSS_2
FBA_DQM2
DMU VSS_2 FBx_CMD17 CS1#_H
162_0402_1% E1 E1
VSS_3 VSS_3
RANKA@
VSS_4
G8
VSS_4
G8 FBx_CMD18 CS0#_H
FBA_DQS#0 G3 J2 FBA_DQS#1 G3 J2
2

DQSL VSS_5 DQSL VSS_5

FBA_DQS#3 B7
DQSU VSS_6
J8 FBA_DQS#2 B7
DQSU VSS_6
J8 FBx_CMD19 CKE_H CKE_H
FBA_CLK0# M1 M1
VSS_7 M9 VSS_7 M9
VSS_8 VSS_8 FBx_CMD20 RST RST RST RST
P1 P1
T2 VSS_9 P9 T2 VSS_9 P9
23,25,26,27 FBA_RST#
FBA_RST#
RESET VSS_10
FBA_RST#
RESET VSS_10 FBx_CMD21 A7 A7 A6 A6
T1 T1
1 2 RV130 L8 VSS_11 T9 L8 VSS_11 T9
ZQ VSS_12 ZQ VSS_12 FBx_CMD22 A4 A4 A5 A5
243_0402_1%
RANKA@ FBx_CMD23 A11 A11 A9 A9

1
J1 B1 J1 B1
NC1 VSSQ_1 NC1 VSSQ_1
1

L1
NC2 VSSQ_2
B9 RV132 L1
NC2 VSSQ_2
B9 FBx_CMD24 A2 A2 A1 A1
RV131 J9 D1 243_0402_1% J9 D1
L9 NC3 VSSQ_3 D8 L9 NC3 VSSQ_3 D8
FBA_ODT_L 10K_0402_5%
NC4 VSSQ_4
RANKA@
NC4 VSSQ_4 FBx_CMD25 A10 A10 WE# WE#
RANKA@ M7 E2 M7 E2

2
NC5 VSSQ_5 E8 NC5 VSSQ_5 E8 FBx_CMD26 A5 A5 A4 A4
2

FBA_CKE_L VSSQ_6 F9 VSSQ_6 F9

VSSQ_7 G1 VSSQ_7 G1
VSSQ_8 VSSQ_8 FBx_CMD27 BA2 BA2
G9 G9
VSSQ_9 VSSQ_9
1

FBx_CMD28 WE# WE# A10 A10

RV133 RV134 96-BALL 96-BALL
B
10K_0402_5% 10K_0402_5% SDRAM DDR3 SDRAM DDR3 FBx_CMD29 BA0 BA0 BA0 BA0 B
RANKA@ RANKA@ K4W4G1646B-HC11_FBGA96 K4W4G1646B-HC11_FBGA96
@ @ FBx_CMD30 BA2 BA2
2

+1.35VGS UV6 SIDE +1.35VGS +1.35VGS UV5 SIDE +1.35VGS

For RF
1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M
33P_0402_50V8J

33P_0402_50V8J
0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
CV117

CV118

CV119

CV120

CV121

CV122

CV127

CV129

CV130

CV131

CV132

CV133

CV134

CV139
1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2
For RF
RANKA@ RANKA@ RANKA@ RANKA@ CD@ RANKA@ RF@ RANKA@ RANKA@ CD@ RANKA@ RANKA@ RANKA@ RF@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/06/28 Deciphered Date 2015/06/28 DDR3 VRAM Rank0_L

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BILG1/AILG1/AILZ1
Date: Wednesday, July 16, 2014 Sheet 24 of 60
5 4 3 2 1
 5 4 3 2 1

at least 16 mils width(optimal)

20 mils spacing to other signals /planes

+1.35VGS
1

D FBA_D[0..63] 23,24,26,27 D
RANKA@
RV135
1.33K_0402_1%
FBA_CMD[30..0] 23,24,26,27
UV8 UV7
2

+FBA_VREFCA1
+FBA_VREFCA1 27 FBA_DQM[7..0] 23,24,26,27
+FBA_VREFCA1 M8 E3 FBA_D34 +FBA_VREFCA1 M8 E3 FBA_D44
1

+FBA_VREFDQ1 H1 VREFCA DQL0 F7 FBA_D38 +FBA_VREFDQ1 H1 VREFCA DQL0 F7 FBA_D43

1 VREFDQ DQL1 VREFDQ DQL1 FBA_DQS[7..0] 23,24,26,27
RANKA@ CV141 F2 FBA_D35 F2 FBA_D45
RV136 .01U_0402_16V7-K FBA_CMD7 N3 DQL2 F8 FBA_D39 FBA_CMD7 N3 DQL2 F8 FBA_D40
A0 DQL3 A0 DQL3 Group5 FBA_DQS#[7..0] 23,24,26,27
1.33K_0402_1% RANKA@ FBA_CMD10 P7 H3 FBA_D32 Group4 FBA_CMD10 P7 H3 FBA_D47
2 FBA_CMD24 P3 A1 DQL4 H8 FBA_D36 FBA_CMD24 P3 A1 DQL4 H8 FBA_D42
2

FBA_CMD6 N2 A2 DQL5 G2 FBA_D33 FBA_CMD6 N2 A2 DQL5 G2 FBA_D46

FBA_CMD22 P8 A3 DQL6 H7 FBA_D37 FBA_CMD22 P8 A3 DQL6 H7 FBA_D41
FBA_CMD26 P2 A4 DQL7 FBA_CMD26 P2 A4 DQL7
FBA_CMD5 R8 A5 FBA_CMD5 R8 A5
FBA_CMD21 R2 A6 D7 FBA_D59 FBA_CMD21 R2 A6 D7 FBA_D52
FBA_CMD8 T8 A7
A8
DQU0
DQU1
C3 FBA_D62 FBA_CMD8 T8 A7
A8
DQU0
DQU1
C3 FBA_D50 CMD mapping mod Mode E
FBA_CMD4 R3 C8 FBA_D58 FBA_CMD4 R3 C8 FBA_D55
L7 A9 DQU2 C2 L7 A9 DQU2 C2
+1.35VGS FBA_CMD25
A10/AP DQU3
FBA_D63 FBA_CMD25
A10/AP DQU3
FBA_D51 Rank0 Rank1
FBA_CMD23 R7 A7 FBA_D57 Group7 FBA_CMD23 R7 A7 FBA_D53 Group6
N7 A11 DQU4 A2 N7 A11 DQU4 A2
FBA_CMD9 FBA_D60 FBA_CMD9 FBA_D48 Address 0..31 32..63 0..31 32..63
1

FBA_CMD12 T3 A12/BC DQU5 B8 FBA_D56 FBA_CMD12 T3 A12/BC DQU5 B8 FBA_D54

A13 DQU6 A13 DQU6
RANKA@ FBA_CMD14 T7
A14 DQU7
A3 FBA_D61 FBA_CMD14 T7
A14 DQU7
A3 FBA_D49 FBx_CMD0 ODT_L ODT_L
RV169
1.33K_0402_1% +1.35VGS +1.35VGS FBx_CMD1 CS1#_L
2

+FBA_VREFDQ1 FBA_CMD29 M2 B2 FBA_CMD29 M2 B2 FBx_CMD2 CS0#_L

+FBA_VREFDQ1 27 BA0 VDD_1 BA0 VDD_1
FBA_CMD13 N8 D9 FBA_CMD13 N8 D9
1

M3 BA1 VDD_2 G7 M3 BA1 VDD_2 G7

1 FBA_CMD27
BA2 VDD_3
FBA_CMD27
BA2 VDD_3 FBx_CMD3 CKE_L CKE_L
RANKA@ CV217 K2 K2
.01U_0402_16V7-K VDD_4 K8 VDD_4 K8
RV170
VDD_5 VDD_5 FBx_CMD4 A9 A9 A11 A11
1.33K_0402_1% RANKA@ N1 N1
2 VDD_6 VDD_6
FBA_CLK1 J7 N9 FBA_CLK1 J7 N9 FBx_CMD5 A6 A6 A7 A7
2

23,27 FBA_CLK1 K7 CK VDD_7 R1 K7 CK VDD_7 R1

FBA_CLK1# FBA_CLK1#
23,27 FBA_CLK1# CK VDD_8 CK VDD_8
23,27 FBA_CKE_H
FBA_CKE_H K9
CKE VDD_9
R9 FBA_CKE_H K9
CKE VDD_9
R9 FBx_CMD6 A3 A3 BA1 BA1
FBx_CMD7 A0 A0 A12 A12
C FBA_ODT_H K1 A1 FBA_ODT_H K1 A1 C
23,27 FBA_ODT_H L2 ODT VDDQ_1 A8 L2 ODT VDDQ_1 A8
23 FBA_CS0#_H
FBA_CS0#_H
CS VDDQ_2
FBA_CS0#_H
CS VDDQ_2 FBx_CMD8 A8 A8 A8 A8
FBA_RAS# J3 C1 FBA_RAS# J3 C1
23,24,26,27 FBA_RAS# RAS VDDQ_3 RAS VDDQ_3
FBA_CAS# K3 C9 FBA_CAS# K3 C9 FBx_CMD9 A12 A12 A0 A0
23,24,26,27 FBA_CAS# L3 CAS VDDQ_4 D2 L3 CAS VDDQ_4 D2
FBA_CMD28 FBA_CMD28
WE VDDQ_5 WE VDDQ_5
FBA_CLK1
VDDQ_6
E9
VDDQ_6
E9 FBx_CMD10 A1 A1 A2 A2
F1 F1
VDDQ_7 VDDQ_7
FBA_DQS4 F3 H2 FBA_DQS5 F3 H2 FBx_CMD11 RAS# RAS# RAS# RAS#
1

FBA_DQS7 C7 DQSL VDDQ_8 H9 FBA_DQS6 C7 DQSL VDDQ_8 H9

DQSU VDDQ_9 DQSU VDDQ_9
RV137 FBx_CMD12 A13 A13 A14 A14
162_0402_1%
FBA_DQM4 E7 A9 FBA_DQM5 E7 A9 FBx_CMD13 BA1 BA1 A3 A3
RANKA@ FBA_DQM7 D3 DML VSS_1 B3 FBA_DQM6 D3 DML VSS_1 B3
2

DMU VSS_2 E1 DMU VSS_2 E1

VSS_3 VSS_3 FBx_CMD14 A14 A14 A13 A13
FBA_CLK1# G8 G8
VSS_4 VSS_4
FBA_DQS#4 G3
DQSL VSS_5
J2 FBA_DQS#5 G3
DQSL VSS_5
J2 FBx_CMD15 CAS# CAS# CAS# CAS#
FBA_DQS#7 B7 J8 FBA_DQS#6 B7 J8
DQSU VSS_6 DQSU VSS_6
VSS_7
M1
VSS_7
M1 FBx_CMD16 ODT_H ODT_H
M9 M9
VSS_8 P1 VSS_8 P1
VSS_9 VSS_9 FBx_CMD17 CS1#_H
FBA_RST# T2 P9 FBA_RST# T2 P9
23,24,26,27 FBA_RST# RESET VSS_10 T1 RESET VSS_10 T1
VSS_11 VSS_11 FBx_CMD18 CS0#_H
L8 T9 L8 T9
ZQ VSS_12 ZQ VSS_12
FBA_CKE_H FBx_CMD19 CKE_H CKE_H

1
J1 B1 J1 B1 FBx_CMD20 RST RST RST RST
1

FBA_ODT_H L1 NC1 VSSQ_1 B9 RV141 L1 NC1 VSSQ_1 B9

NC2 VSSQ_2 NC2 VSSQ_2
RV140 J9
NC3 VSSQ_3
D1 243_0402_1% J9
NC3 VSSQ_3
D1 FBx_CMD21 A7 A7 A6 A6
243_0402_1% L9 D8 RANKA@ L9 D8
M7 NC4 VSSQ_4 E2 M7 NC4 VSSQ_4 E2
RANKA@ FBx_CMD22 A4 A4 A5 A5

2
NC5 VSSQ_5 NC5 VSSQ_5
1

E8 E8
2

VSSQ_6 F9 VSSQ_6 F9
RV138 RV139
VSSQ_7 VSSQ_7 FBx_CMD23 A11 A11 A9 A9
10K_0402_5% 10K_0402_5% G1 G1
VSSQ_8 G9 VSSQ_8 G9
RANKA@ RANKA@
VSSQ_9 VSSQ_9 FBx_CMD24 A2 A2 A1 A1
2

96-BALL 96-BALL FBx_CMD25 A10 A10 WE# WE#

SDRAM DDR3 SDRAM DDR3
B
K4W4G1646B-HC11_FBGA96 K4W4G1646B-HC11_FBGA96 FBx_CMD26 A5 A5 A4 A4 B
@ @
FBx_CMD27 BA2 BA2
FBx_CMD28 WE# WE# A10 A10
FBx_CMD29 BA0 BA0 BA0 BA0
FBx_CMD30 BA2 BA2

+1.35VGS UV8 SIDE +1.35VGS +1.35VGS UV7 SIDE +1.35VGS

For RF For RF
1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M
33P_0402_50V8J

33P_0402_50V8J
0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
CV142

CV143

CV144

CV145

CV146

CV147

CV152

CV154

CV155

CV156

CV157

CV158

CV159

CV164
1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2

RANKA@ RANKA@ CD@ RANKA@ RANKA@ RANKA@ RANKA@ RANKA@ RANKA@ RANKA@ RANKA@ CD@
RF@ RF@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/06/28 Deciphered Date 2015/06/28 DDR3 VRAM Rank0_H

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BILG1/AILG1/AILZ1
Date: Wednesday, July 16, 2014 Sheet 25 of 60
5 4 3 2 1
 5 4 3 2 1

FBA_D[0..63] 23,24,25,27

FBA_CMD[30..0] 23,24,25,27

FBA_DQM[7..0] 23,24,25,27

FBA_DQS[7..0] 23,24,25,27

D FBA_DQS#[7..0] 23,24,25,27 D

UV9 UV10

+FBA_VREFCA0 M8 E3 FBA_D1 +FBA_VREFCA0 M8 E3 FBA_D13

24 +FBA_VREFCA0 H1 VREFCA DQL0 F7 H1 VREFCA DQL0 F7
+FBA_VREFDQ0 FBA_D5 +FBA_VREFDQ0 FBA_D11
24 +FBA_VREFDQ0 VREFDQ DQL1 VREFDQ DQL1
at least 16 mils width(optimal) F2 FBA_D0 F2 FBA_D15
FBA_CMD9 N3 DQL2 F8 FBA_D7 FBA_CMD9 N3 DQL2 F8 FBA_D8
20 mils spacing to other signals /planes A0 DQL3 A0 DQL3 Group1
FBA_CMD24 P7 H3 FBA_D2 Group0 FBA_CMD24 P7 H3 FBA_D12
FBA_CMD10 P3 A1 DQL4 H8 FBA_D6 FBA_CMD10 P3 A1 DQL4 H8 FBA_D9
FBA_CMD13 N2 A2 DQL5 G2 FBA_D3 FBA_CMD13 N2 A2 DQL5 G2 FBA_D14
FBA_CMD26 P8 A3 DQL6 H7 FBA_D4 FBA_CMD26 P8 A3 DQL6 H7 FBA_D10
FBA_CMD22 P2 A4 DQL7 FBA_CMD22 P2 A4 DQL7
FBA_CMD21 R8 A5 FBA_CMD21 R8 A5
FBA_CMD5 R2 A6 D7 FBA_D25 FBA_CMD5 R2 A6 D7 FBA_D22
FBA_CMD8 T8 A7 DQU0 C3 FBA_D31 FBA_CMD8 T8 A7 DQU0 C3 FBA_D17
FBA_CMD23 R3 A8 DQU1 C8 FBA_D24 FBA_CMD23 R3 A8 DQU1 C8 FBA_D23
FBA_CMD28 L7 A9 DQU2 C2 FBA_D30 FBA_CMD28 L7 A9 DQU2 C2 FBA_D16
A10/AP DQU3 A10/AP DQU3 Group2
FBA_CMD4 R7 A7 FBA_D26 Group3 FBA_CMD4 R7 A7 FBA_D20
FBA_CMD7 N7 A11 DQU4 A2 FBA_D28 FBA_CMD7 N7 A11 DQU4 A2 FBA_D18
FBA_CMD14 T3 A12/BC DQU5 B8 FBA_D27 FBA_CMD14 T3 A12/BC DQU5 B8 FBA_D21
FBA_CMD12 T7 A13 DQU6 A3 FBA_D29 FBA_CMD12 T7 A13 DQU6 A3 FBA_D19
A14 DQU7 A14 DQU7 CMD mapping mod Mode E
+1.35VGS +1.35VGS
Rank0 Rank1
FBA_CMD29 M2 B2 FBA_CMD29 M2 B2
BA0 VDD_1 BA0 VDD_1
FBA_CMD6 N8 D9 FBA_CMD6 N8 D9 Address 0..31 32..63 0..31 32..63
FBA_CMD30 M3 BA1 VDD_2 G7 FBA_CMD30 M3 BA1 VDD_2 G7
BA2 VDD_3 BA2 VDD_3
VDD_4
K2
VDD_4
K2 FBx_CMD0 ODT_L ODT_L
K8 K8
VDD_5 N1 VDD_5 N1
VDD_6 VDD_6 FBx_CMD1 CS1#_L
FBA_CLK0 J7 N9 FBA_CLK0 J7 N9
23,24 FBA_CLK0 K7 CK VDD_7 R1 K7 CK VDD_7 R1
23,24 FBA_CLK0#
FBA_CLK0#
CK VDD_8
FBA_CLK0#
CK VDD_8 FBx_CMD2 CS0#_L
FBA_CKE_L K9 R9 FBA_CKE_L K9 R9
23,24 FBA_CKE_L CKE VDD_9 CKE VDD_9
FBx_CMD3 CKE_L CKE_L
C
23,24 FBA_ODT_L
FBA_ODT_L K1
ODT VDDQ_1
A1 FBA_ODT_L K1
ODT VDDQ_1
A1 FBx_CMD4 A9 A9 A11 A11 C
FBA_CS1#_L L2 A8 FBA_CS1#_L L2 A8
23 FBA_CS1#_L CS VDDQ_2 CS VDDQ_2
23,24,25,27 FBA_RAS#
FBA_RAS# J3
RAS VDDQ_3
C1 FBA_RAS# J3
RAS VDDQ_3
C1 FBx_CMD5 A6 A6 A7 A7
FBA_CAS# K3 C9 FBA_CAS# K3 C9
23,24,25,27 FBA_CAS# L3 CAS VDDQ_4 D2 L3 CAS VDDQ_4 D2
FBA_CMD25
WE VDDQ_5
FBA_CMD25
WE VDDQ_5 FBx_CMD6 A3 A3 BA1 BA1
E9 E9
VDDQ_6 F1 VDDQ_6 F1
VDDQ_7 VDDQ_7 FBx_CMD7 A0 A0 A12 A12
FBA_DQS0 F3 H2 FBA_DQS1 F3 H2
C7 DQSL VDDQ_8 H9 C7 DQSL VDDQ_8 H9
FBA_DQS3
DQSU VDDQ_9
FBA_DQS2
DQSU VDDQ_9 FBx_CMD8 A8 A8 A8 A8
FBx_CMD9 A12 A12 A0 A0
FBA_DQM0 E7 A9 FBA_DQM1 E7 A9
DML VSS_1 DML VSS_1
FBA_DQM3 D3
DMU VSS_2
B3 FBA_DQM2 D3
DMU VSS_2
B3 FBx_CMD10 A1 A1 A2 A2
E1 E1
VSS_3 G8 VSS_3 G8
VSS_4 VSS_4 FBx_CMD11 RAS# RAS# RAS# RAS#
FBA_DQS#0 G3 J2 FBA_DQS#1 G3 J2
B7 DQSL VSS_5 J8 B7 DQSL VSS_5 J8
FBA_DQS#3
DQSU VSS_6
FBA_DQS#2
DQSU VSS_6 FBx_CMD12 A13 A13 A14 A14
M1 M1
VSS_7 M9 VSS_7 M9
VSS_8 VSS_8 FBx_CMD13 BA1 BA1 A3 A3
P1 P1
VSS_9 VSS_9
23,24,25,27 FBA_RST#
FBA_RST# T2
RESET VSS_10
P9 FBA_RST# T2
RESET VSS_10
P9 FBx_CMD14 A14 A14 A13 A13
T1 T1
VSS_11 VSS_11
1 2 RV142 L8
ZQ VSS_12
T9 L8
ZQ VSS_12
T9 FBx_CMD15 CAS# CAS# CAS# CAS#
243_0402_1%
RANKB@ FBx_CMD16 ODT_H ODT_H

1
J1 B1 J1 B1
L1 NC1 VSSQ_1 B9 L1 NC1 VSSQ_1 B9
NC2 VSSQ_2
RV143
NC2 VSSQ_2 FBx_CMD17 CS1#_H
J9 D1 243_0402_1% J9 D1
L9 NC3 VSSQ_3 D8 L9 NC3 VSSQ_3 D8
NC4 VSSQ_4
RANKB@
NC4 VSSQ_4 FBx_CMD18 CS0#_H
M7 E2 M7 E2

2
NC5 VSSQ_5 NC5 VSSQ_5
VSSQ_6
E8
VSSQ_6
E8 FBx_CMD19 CKE_H CKE_H
F9 F9
VSSQ_7 VSSQ_7
VSSQ_8
G1
VSSQ_8
G1 FBx_CMD20 RST RST RST RST
G9 G9
VSSQ_9 VSSQ_9
FBx_CMD21 A7 A7 A6 A6
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 FBx_CMD22 A4 A4 A5 A5
K4W4G1646B-HC11_FBGA96 K4W4G1646B-HC11_FBGA96
B B
@ @ FBx_CMD23 A11 A11 A9 A9
FBx_CMD24 A2 A2 A1 A1
FBx_CMD25 A10 A10 WE# WE#
FBx_CMD26 A5 A5 A4 A4
FBx_CMD27 BA2 BA2
FBx_CMD28 WE# WE# A10 A10
FBx_CMD29 BA0 BA0 BA0 BA0
FBx_CMD30 BA2 BA2

+1.35VGS UV4 SIDE +1.35VGS +1.35VGS UV3 SIDE +1.35VGS

For RF For RF
1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M
33P_0402_50V8J

33P_0402_50V8J
0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
CV166

CV167

CV168

CV169

CV170

CV171

CV176

CV178

CV179

CV180

CV181

CV182

CV183

CV188
1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2

RANKB@ RANKB@ RANKB@ CD@ RANKB@ RANKB@ RF@ RANKB@ RANKB@ RANKB@ CD@ RANKB@ RANKB@ RF@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/06/28 Deciphered Date 2015/06/28 DDR3 VRAM Rank1_L

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BILG1/AILG1/AILZ1
Date: Wednesday, July 16, 2014 Sheet 26 of 60
5 4 3 2 1
 5 4 3 2 1

FBA_D[0..63] 23,24,25,26

FBA_CMD[30..0] 23,24,25,26

FBA_DQM[7..0] 23,24,25,26

FBA_DQS[7..0] 23,24,25,26
D D
FBA_DQS#[7..0] 23,24,25,26
UV11 UV12

+FBA_VREFCA1 M8 E3 FBA_D38 +FBA_VREFCA1 M8 E3 FBA_D43

25 +FBA_VREFCA1 VREFCA DQL0 VREFCA DQL0
at least 16 mils width(optimal) +FBA_VREFDQ1 H1 F7 FBA_D34 +FBA_VREFDQ1 H1 F7 FBA_D44
25 +FBA_VREFDQ1 VREFDQ DQL1 F2 VREFDQ DQL1 F2
20 mils spacing to other signals /planes FBA_D39 FBA_D40
FBA_CMD9 N3 DQL2 F8 FBA_D35 FBA_CMD9 N3 DQL2 F8 FBA_D45
FBA_CMD24 P7 A0 DQL3 H3 FBA_D37 FBA_CMD24 P7 A0 DQL3 H3 FBA_D41
A1 DQL4 Group4 A1 DQL4 Group5
FBA_CMD10 P3 H8 FBA_D33 FBA_CMD10 P3 H8 FBA_D46
FBA_CMD13 N2 A2 DQL5 G2 FBA_D36 FBA_CMD13 N2 A2 DQL5 G2 FBA_D42
FBA_CMD26 P8 A3 DQL6 H7 FBA_D32 FBA_CMD26 P8 A3 DQL6 H7 FBA_D47
FBA_CMD22 P2 A4 DQL7 FBA_CMD22 P2 A4 DQL7
FBA_CMD21 R8 A5 FBA_CMD21 R8 A5
FBA_CMD5 R2 A6 D7 FBA_D62 FBA_CMD5 R2 A6 D7 FBA_D50
FBA_CMD8 T8 A7 DQU0 C3 FBA_D59 FBA_CMD8 T8 A7 DQU0 C3 FBA_D52
FBA_CMD23 R3 A8 DQU1 C8 FBA_D63 FBA_CMD23 R3 A8 DQU1 C8 FBA_D51
FBA_CMD28 L7 A9 DQU2 C2 FBA_D58 FBA_CMD28 L7 A9 DQU2 C2 FBA_D55
A10/AP DQU3 Group7 A10/AP DQU3
FBA_CMD4 R7 A7 FBA_D61 FBA_CMD4 R7 A7 FBA_D49 Group6
FBA_CMD7 N7 A11 DQU4 A2 FBA_D56 FBA_CMD7 N7 A11 DQU4 A2 FBA_D54
FBA_CMD14 T3 A12/BC
A13
DQU5
DQU6
B8 FBA_D60 FBA_CMD14 T3 A12/BC
A13
DQU5
DQU6
B8 FBA_D48 CMD mapping mod Mode E
FBA_CMD12 T7 A3 FBA_D57 FBA_CMD12 T7 A3 FBA_D53
A14 DQU7 A14 DQU7
Rank0 Rank1
+1.35VGS +1.35VGS
Address 0..31 32..63 0..31 32..63
FBA_CMD29 M2 B2 FBA_CMD29 M2 B2
N8 BA0 VDD_1 D9 N8 BA0 VDD_1 D9
FBA_CMD6
BA1 VDD_2
FBA_CMD6
BA1 VDD_2 FBx_CMD0 ODT_L ODT_L
FBA_CMD30 M3 G7 FBA_CMD30 M3 G7
BA2 VDD_3 K2 BA2 VDD_3 K2
VDD_4 VDD_4 FBx_CMD1 CS1#_L
K8 K8
VDD_5 N1 VDD_5 N1
VDD_6 VDD_6 FBx_CMD2 CS0#_L
FBA_CLK1 J7 N9 FBA_CLK1 J7 N9
23,25 FBA_CLK1 CK VDD_7 CK VDD_7
23,25 FBA_CLK1#
FBA_CLK1# K7
CK VDD_8
R1 FBA_CLK1# K7
CK VDD_8
R1 FBx_CMD3 CKE_L CKE_L
FBA_CKE_H K9 R9 FBA_CKE_H K9 R9
23,25 FBA_CKE_H CKE VDD_9 CKE VDD_9
FBx_CMD4 A9 A9 A11 A11
FBA_ODT_H K1 A1 FBA_ODT_H K1 A1 FBx_CMD5 A6 A6 A7 A7
23,25 FBA_ODT_H ODT VDDQ_1 ODT VDDQ_1
C FBA_CS1#_H L2 A8 FBA_CS1#_H L2 A8 C
23 FBA_CS1#_H J3 CS VDDQ_2 C1 J3 CS VDDQ_2 C1
23,24,25,26 FBA_RAS#
FBA_RAS#
RAS VDDQ_3
FBA_RAS#
RAS VDDQ_3 FBx_CMD6 A3 A3 BA1 BA1
FBA_CAS# K3 C9 FBA_CAS# K3 C9
23,24,25,26 FBA_CAS# CAS VDDQ_4 CAS VDDQ_4
FBA_CMD25 L3 D2 FBA_CMD25 L3 D2 FBx_CMD7 A0 A0 A12 A12
WE VDDQ_5 E9 WE VDDQ_5 E9
VDDQ_6 VDDQ_6
VDDQ_7
F1
VDDQ_7
F1 FBx_CMD8 A8 A8 A8 A8
FBA_DQS4 F3 H2 FBA_DQS5 F3 H2
DQSL VDDQ_8 DQSL VDDQ_8
FBA_DQS7 C7
DQSU VDDQ_9
H9 FBA_DQS6 C7
DQSU VDDQ_9
H9 FBx_CMD9 A12 A12 A0 A0
FBx_CMD10 A1 A1 A2 A2
FBA_DQM4 E7 A9 FBA_DQM5 E7 A9
D3 DML VSS_1 B3 D3 DML VSS_1 B3
FBA_DQM7
DMU VSS_2
FBA_DQM6
DMU VSS_2 FBx_CMD11 RAS# RAS# RAS# RAS#
E1 E1
VSS_3 G8 VSS_3 G8
VSS_4 VSS_4 FBx_CMD12 A13 A13 A14 A14
FBA_DQS#4 G3 J2 FBA_DQS#5 G3 J2
DQSL VSS_5 DQSL VSS_5
FBA_DQS#7 B7
DQSU VSS_6
J8 FBA_DQS#6 B7
DQSU VSS_6
J8 FBx_CMD13 BA1 BA1 A3 A3
M1 M1
VSS_7 VSS_7
VSS_8
M9
VSS_8
M9 FBx_CMD14 A14 A14 A13 A13
P1 P1
T2 VSS_9 P9 T2 VSS_9 P9
23,24,25,26 FBA_RST#
FBA_RST#
RESET VSS_10
FBA_RST#
RESET VSS_10 FBx_CMD15 CAS# CAS# CAS# CAS#
T1 T1
L8 VSS_11 T9 L8 VSS_11 T9
ZQ VSS_12 ZQ VSS_12 FBx_CMD16 ODT_H ODT_H
FBx_CMD17 CS1#_H

1
J1 B1 J1 B1
NC1 VSSQ_1 NC1 VSSQ_1
1

L1
NC2 VSSQ_2
B9 RV145 L1
NC2 VSSQ_2
B9 FBx_CMD18 CS0#_H
RV144 J9 D1 243_0402_1% J9 D1
NC3 VSSQ_3 NC3 VSSQ_3
243_0402_1% L9
NC4 VSSQ_4
D8 RANKB@ L9
NC4 VSSQ_4
D8 FBx_CMD19 CKE_H CKE_H
RANKB@ M7 E2 M7 E2

2
NC5 VSSQ_5 E8 NC5 VSSQ_5 E8 FBx_CMD20 RST RST RST RST
2

VSSQ_6 F9 VSSQ_6 F9
VSSQ_7 G1 VSSQ_7 G1
VSSQ_8 VSSQ_8 FBx_CMD21 A7 A7 A6 A6
G9 G9
VSSQ_9 VSSQ_9
FBx_CMD22 A4 A4 A5 A5
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 FBx_CMD23 A11 A11 A9 A9
K4W4G1646B-HC11_FBGA96 K4W4G1646B-HC11_FBGA96
B @ @ FBx_CMD24 A2 A2 A1 A1 B

FBx_CMD25 A10 A10 WE# WE#

FBx_CMD26 A5 A5 A4 A4
FBx_CMD27 BA2 BA2
FBx_CMD28 WE# WE# A10 A10
FBx_CMD29 BA0 BA0 BA0 BA0
FBx_CMD30 BA2 BA2

+1.35VGS UV6 SIDE +1.35VGS +1.35VGS UV5 SIDE +1.35VGS

For RF For RF
1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M
33P_0402_50V8J

33P_0402_50V8J
0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
CV190

CV191

CV192

CV193

CV194

CV195

CV200

CV202

CV203

CV204

CV205

CV206

CV207

CV212
1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2

RANKB@ RANKB@ RANKB@ RANKB@ CD@ RANKB@ RANKB@ RANKB@ RANKB@ RANKB@ RANKB@ CD@
RF@ RF@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/06/28 Deciphered Date 2015/06/28 DDR3 VRAM Rank1_H

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BILG1/AILG1/AILZ1
Date: Wednesday, July 16, 2014 Sheet 27 of 60
5 4 3 2 1
 5 4 3 2 1

+3VG_AON Physical Logical Logical Logical Logical

Strapping pin Power Rail Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0
D D
ROM_SCLK +3VGS SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED
ROM_SI +3VGS RAM_CFG[3] RAM_CFG[2] RAM_CFG[1] RAM_CFG[0]
ROM_SO +3VGS DEVID_SEL PCIE_CFG SMB_ALT_ADDR VGA_DEVICE

2
RV146 RV147 RV148 RV149 RV150 STRAP0 +3VGS Reserved(keep pull-up and pull-down footprint and stuff 50Kohm pull-up)
49.9K_0402_1% 4.99K_0402_1% 24.9K_0402_1% 4.99K_0402_1% 45.3K_0402_1%
N15SGT@ @ @ @ @ STRAP1 +3VGS

1
STRAP2 +3VGS
20 STRAP0 STRAP0 Reserved(keep pull-up and pull-down footprint and not stuff by default)
20 STRAP1 STRAP1 STRAP3 +3VGS
20 STRAP2 STRAP2
20 STRAP3 STRAP3 STRAP4 +3VGS
20 STRAP4 STRAP4

DEVID_SEL
2

2
Pull-up to
RV151 RV152 RV153 RV154 RV155 Resistor Values +3VGS Pull-down to Gnd
45.3K_0402_1% 4.99K_0402_1% 15K_0402_1% 4.99K_0402_1% 45.3K_0402_1% 0 (Default)
@ @ @ @ @ 4.99K 1000 0000
1

1
10K 1001 0001 1
15K 1010 0010
20K 1011 0011 PCIE_CFG
24.9K 1100 0100
0 (Default)
30.1K 1101 0101
34.8K 1110 0110 1
+3VGS 45.3K 1111 0111
C C

SMBUS_ALT_ADDR
0 0x9E (Default)
2

2 Physical
RV156 RV157 RV158
Strapping pin Power Rail Strap Mapping
4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 1 0x9C (Multi-GPU usage)
@ @ @ ROM_SCLK +3VGS SMB_ALT_ADDR
1

ROM_SI +3VGS SUB_VENDOR

ROM_SO +3VGS VGA_DEVICE VGA_DEVICE
20 ROM_SI ROM_SI
20 ROM_SO ROM_SO STRAP0 +3VGS RAM_CFG[0] 0 3D Device (Class Code 302h)
20 ROM_SCLK ROM_SCLK
STRAP1 +3VGS RAM_CFG[1]
1 VGA Device (Default)
2

STRAP2 +3VGS RAM_CFG[2]

RV159 RV160 RV161
X76 20K_0402_1% 4.99K_0402_1% 4.99K_0402_1% STRAP3 +3VGS RAM_CFG[3]
@ @ @
STRAP4 +3VGS PCIE_MAX_SPEED
1

X76

GPU FB Memory (DDR3) ROM_SI ROM_SO ROM_SCLK STRAP0 STRAP1 STRAP2 STRAP3 STRAP4
B H5TC4G63AFR-11C 0x3 B
Hynix VRAM X76 VRAM P/N
900MHz 256M x 16 PD 20K
MT41J256M16HA-093G:E 0x4 X76409JVL01 SA00005SH10
Micron Samsung
900MHz 256M x 16 PD 24.9K
N15S-GT X76409JVL51 (1G 32Mx16)
K4W4G1646D-BC1A 0x5
Samsung PD 4.99K PD 4.99K PU 49.9K Un-stuff Un-stuff Un-stuff Un-stuff
900MHz 256M x 16 PD 30.1K X76409JVL02 SA00005M100
Micron
X76409JVL02 (2G 64Mx32)

Hynix

需需需需，Table爲G15料料
GPU FB Memory (DDR3) STRAP3 STRAP2 STRAP1 STRAP0 STRAP4 ROM_SI ROM_SO ROM_SCLK
H5TC4G63AFR-11C
Hynix PD 10K PU 10K PD 10K PD 10K
900MHz 256M x 16 0x4
MT41J256M16HA-093G:E
Micron PU 10K PU 10K PD 10K PU 10K
900MHz 256M x 16 0xD
N15V-GM
Samsung K4W4G1646D-BC1A
900MHz PU 10K PD 10K PD 10K PU 10K PD 10K PD 10K PD 10K PD 10K
256M x 16 0x9
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/06/28 Deciphered Date 2015/06/28 N15X_MISC

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BILG1/AILG1/AILZ1
Date: Wednesday, July 16, 2014 Sheet 28 of 60
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/06/28 Deciphered Date 2015/06/28 Blank

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BILG1/AILG1/AILZ1
Date: Wednesday, July 16, 2014 Sheet 29 of 60
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/06/28 Deciphered Date 2015/06/28 Blank
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BILG1/AILG1/AILZ1
Date: Wednesday, July 16, 2014 Sheet 30 of 60
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/06/28 Deciphered Date 2015/06/28 Blank
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BILG1/AILG1/AILZ1
Date: Wednesday, July 16, 2014 Sheet 31 of 60
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/06/28 Deciphered Date 2015/06/28 Blank
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BILG1/AILG1/AILZ1
Date: Wednesday, July 16, 2014 Sheet 32 of 60
5 4 3 2 1
 5 4 3 2 1

LCD POWER CIRCUIT CMOS Camera

+LCDVDD +5VALW +3VS
W=60mils +3VS Need short +3VS_CMOS_R
J1 @

1
1 2
1 2

1
R1 1
130_0603_1% R2 C1 JUMP_43X39
100K_0402_5% 4.7U_0603_6.3V6K +3VS_CMOS
CD@

2
2 LP2301ALT1G_SOT23-3

2
Q9 W=40 mils @ W=40mils

3
S

D
D Q8B R4 G Q7 3 1 R3 1 2

.01U_0402_16V7-K
D 5 1 2 2 LP2301ALT1G_SOT23-3 0_0603_5% D

C6
G 220K_0402_5% @ 1 1
2N7002KDWH_SOT363-6 +LCDVDD +LCDVDD_CON C3 C4

G
D
1 1 1

2
S C5 .1U_0402_10V6-K 10U_0603_6.3V6M

4
C2 W=60mils .1U_0402_10V6-K CD@ @
.1U_0402_10V6-K L1 1 2 0_0402_5% @ @ 2 2
2 @ 2 2

33P_0402_50V8J
.1U_0402_10V6-K
C7

C8

C43
4.7U_0603_6.3V6K
6
Q8A D 1 1 1 R5 1 @ 2
9 CMOS_ON#
R6 1 2 0_0402_5% 2 CD@ 100K_0402_5%
4 PCH_ENVDD G
@ 1 1
C9 C10

1
S 2N7002KDWH_SOT363-6 2 2 2 0.01U_0402_25V7K .1U_0402_10V6-K
For EMI

RF@
R7 EMC_NS@ Close to R5 @
100K_0402_5% 2 2

2
+3VS
For RF

2
+3VS
R8 R9
EMI request
100K_0402_1% 100K_0402_1%
2

+3VS +1.35V DMIC_CLK DISPOFF# INVT_PWM

470P_0402_50V7K
R10 @ @

470P_0402_50V7K
100P_0402_50V8J
C11

C12

C13
PCH_ENBKL R11 1 @ 2 4.7K_0402_5%

EMC_NS@
0_0402_5% @ 1 1 1

EMC_NS@
EDP_AUX C138
1

EDP_AUX# 1 2 EMC@
R12 1 2 0_0402_5% DISPOFF# B+ +LEDVDD
44 BKOFF# 2 2 2
@

2
2A 80 mil 2A 80 mil .1U_0402_10V6-K
R14 1 2 0_0402_5% ENBKL 2 R17 1 R13 R15 EMC@
4 PCH_ENBKL ENBKL 44

4.7U_0805_25V6-K

470P_0402_50V7K
@ 0_0805_5% C14 C15 100K_0402_1% 100K_0402_1%
1

C C
1 1
R16 CD@ EMC_NS@ @ @

1
100K_0402_5% AO3401A_SOT23-3
2 2

D
Q33 3 1 @
2

EMI Request JEDP1

+LEDVDD 1
2 1

G
2
3 2
+3VS R179 1 @ 2 LEDVDD_EN# 4 3
B+ 4
100K_0402_5% CPU_EDP_TX0+ C19 1 2 .1U_0402_10V6-K EDP_TX0+ 5
4 CPU_EDP_TX0+ 5
CPU_EDP_TX0- C16 1 2 .1U_0402_10V6-K EDP_TX0- 6
4 CPU_EDP_TX0- 6
2

1
7
R18 R180 CPU_EDP_TX1+ C17 1 2 .1U_0402_10V6-K EDP_TX1+ 8 7
4 CPU_EDP_TX1+ 8
1K_0402_5% 100K_0402_5% CPU_EDP_TX1- C18 1 2 .1U_0402_10V6-K EDP_TX1- 9
4 CPU_EDP_TX1- 9
@ @ 10
CPU_EDP_AUX C20 1 2 .1U_0402_10V6-K EDP_AUX 11 10
4 CPU_EDP_AUX
1

1 2
CPU_EDP_AUX# C21 1 2 .1U_0402_10V6-K EDP_AUX# 12 11
4 CPU_EDP_AUX# 12
R19 1 2 0_0402_5% INVT_PWM Q34 D 13
4 PCH_EDP_PWM 13
@ PCH_ENVDD R181 1 @ 2 2 DISPOFF# 14
0_0402_5% G 15 14
15
1

1 INVT_PWM 16
4 INVT_PWM 16
R20 C132 @ S 17
3

100K_0402_5% .1U_0402_10V6-K 2N7002KW_SOT323-3 +3VS 18 17

@ 19 18
2 4 CPU_EDP_HPD 19
R21 1 @ 2 20
2

0_0402_5% 21 20
1 +LCDVDD_CON 21
W=60mils 22
C22 23 22
Reserve for power consumption test +3VS 23
680P_0402_50V7K 43 DMIC_DATA 24
@ 2 25 24
43 DMIC_CLK 25
26 31
27 26 G1 32
R182 1 @ 2 0_0402_5% USB20_P5_R 28 27 G2 33
9 USB20_P5 28 G3
B R183 1 @ 2 0_0402_5% USB20_N5_R 29 34 B
9 USB20_N5 29 G4
+3VS_CMOS 30 35
30 G5
2
W=40mils ACES_50406-03071-001
C24 ME@
0.047U_0402_16V7K EMC_NS@
1

EMI request

For EMI
L12 EMC_NS@
USB20_P5 1 2 USB20_P5_R
1 2

USB20_N5 4 3 USB20_N5_R
4 3
CMM21T-900M-N_4P

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/06/28 Deciphered Date 2015/06/28 eDP/ CMOS/Touch screen

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Number
Document Number Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BILG1/AILG1/AILZ1
Date: Wednesday, July 16, 2014 Sheet 33 of 60
5 4 3 2 1
 5 4 3 2 1

L2 @
HDMI_CLK-_C 1 2 HDMI_CLK-_CON2 1
1 2 C26
3.3P_0402_50V8-C
@
HDMI_CLK+_C 4 3
HDMI_CLK+_CON 1 2
4 3 C27 3.3P_0402_50V8-C
HDMI2012F2SF-900T04_4P
+3VS
EMC@
D L3 @ D
HDMI_TX0-_C 1 2 HDMI_TX0-_CON 1 2
1 2 C28 3.3P_0402_50V8-C
@
HDMI_TX0+_C 4 3 HDMI_TX0+_CON 1 2
4 3 C29 3.3P_0402_50V8-C

5
HDMI2012F2SF-900T04_4P

G
Q1B D3
EMC@
L4 @ HDMI_DET 1 1 10 9 HDMI_DET
HDMI_TX1-_C 1 2 HDMI_TX1-_CON 1 2
1 2 4 3 2 2
C30 3.3P_0402_50V8-C HDMICLK_R HDMIDAT_R 9 8 HDMIDAT_R

S
4 DDPB_CLK

D
@
HDMI_TX1+_C 4 3 HDMI_TX1+_CON 1 2 2N7002KDWH_SOT363-6 HDMICLK_R 4 4 7 7 HDMICLK_R
4 3

2
C31 3.3P_0402_50V8-C

G
HDMI2012F2SF-900T04_4P Q1A +5VS_HDMI 5 5 6 6 +5VS_HDMI
EMC@
L5 @ 3 3
HDMI_TX2-_C 1 2 HDMI_TX2-_CON 1 2 1 6 HDMIDAT_R

S
1 2 4 DDPB_DATA

D
C32 3.3P_0402_50V8-C 8
@ 2N7002KDWH_SOT363-6
HDMI_TX2+_C 4 3 HDMI_TX2+_CON 1 2
4 3 C33 3.3P_0402_50V8-C AZ1045-04F_DFN2510P10E-10-9
HDMI2012F2SF-900T04_4P EMC_NS@
EMC@
For EMC
For EMC

C C
HDMI_CLK-_C R29 1 2 470_0402_5%

HDMI_CLK+_C R30 1 2 470_0402_5% +5VS

+3VS +5VS @ +5VS_HDMI_F +5VS_HDMI
HDMI_TX0-_C R31 1 2 470_0402_5% D5

2
D4 2 F1
HDMI_TX0+_C R32 1 2 470_0402_5% 1 1 2
3
HDMI_TX1-_C R33 1 2 470_0402_5% @ RB491D_SOT23-3 0.5A_8V_KMC3S050RY

2
HDMI_TX1+_C R34 1 2 470_0402_5% BAT54S-7-F_SOT23-3 AO3401A_SOT23-3
R35

1
2
Q12 D4

G
1M_0402_5%
HDMI_TX2-_C R37 1 2 470_0402_5% 1 3 Q22

S
1
C34

1
HDMI_TX2+_C R38 1 2 470_0402_5% .1U_0402_10V6-K

2
3 1

G
2
4 HDMI_HPD 2

D
R39 R40
46 SUSP
1

D Q13 2N7002KW_SOT323-3 2.2K_0402_5% 2.2K_0402_5%

2
2 <BOM Structure>
+3VS
G 2N7002KW_SOT323-3 R41

1
20K_0402_5%
S JHDMI1
3

HDMI_DET 19

1
R42 1 @ 2 18 HP_DET
17 +5V
100K_0402_5% HDMIDAT_R 16 DDC/CEC_GND
HDMICLK_R 15 SDA
14 SCL
13 Reserved
HDMI_CLK- C35 2 1 .1U_0402_10V6-K HDMI_CLK-_C R43 2 @ 1 0_0402_5% HDMI_CLK-_CON 12 CEC 20
4 HDMI_CLK- CK- GND1
11 21
B HDMI_CLK+ C36 2 1 .1U_0402_10V6-K HDMI_CLK+_C R44 2 @ 1 0_0402_5% HDMI_CLK+_CON 10 CK_shield GND2 B
4 HDMI_CLK+ CK+
HDMI_TX0- C37 2 1 .1U_0402_10V6-K HDMI_TX0-_C R45 2 @ 1 0_0402_5% HDMI_TX0-_CON 9 22
4 HDMI_TX0- D0- GND3
8 23
HDMI_TX0+ C38 2 1 .1U_0402_10V6-K HDMI_TX0+_C R46 2 @ 1 0_0402_5% HDMI_TX0+_CON 7 D0_shield GND4
4 HDMI_TX0+ D0+
HDMI_TX1- C39 2 1 .1U_0402_10V6-K HDMI_TX1-_C R47 2 @ 1 0_0402_5% HDMI_TX1-_CON 6
4 HDMI_TX1- D1-
5
HDMI_TX1+ C40 2 1 .1U_0402_10V6-K HDMI_TX1+_C R48 2 @ 1 0_0402_5% HDMI_TX1+_CON 4 D1_shield
4 HDMI_TX1+ D1+
HDMI_TX2- C41 2 1 .1U_0402_10V6-K HDMI_TX2-_C R49 2 @ 1 0_0402_5% HDMI_TX2-_CON 3
4 HDMI_TX2- D2-
2
HDMI_TX2+ C42 2 1 .1U_0402_10V6-K HDMI_TX2+_C R50 2 @ 1 0_0402_5% HDMI_TX2+_CON 1 D2_shield
4 HDMI_TX2+ D2+
FOX_QJ111A1-RC0AH1-8H
ME@

Close to JHDMI1
D6 D7
HDMI_CLK+_CON 1 1 10 9 HDMI_CLK+_CON HDMI_TX1-_CON 1 1 10 9 HDMI_TX1-_CON

HDMI_CLK-_CON 2 2 9 8 HDMI_CLK-_CON HDMI_TX1+_CON 2 2 9 8 HDMI_TX1+_CON

HDMI_TX0+_CON 4 4 7 7 HDMI_TX0+_CON HDMI_TX2-_CON 4 4 7 7 HDMI_TX2-_CON

HDMI_TX0-_CON 5 5 6 6 HDMI_TX0-_CON HDMI_TX2+_CON 5 5 6 6 HDMI_TX2+_CON

A A
3 3 3 3

8 8

AZ1045-04F_DFN2510P10E-10-9 For EMC AZ1045-04F_DFN2510P10E-10-9

EMC_NS@ EMC_NS@ Security Classification LC Future Center Secret Data Title

Issued Date 2014/06/28 Deciphered Date 2015/06/28 HDMI_CONN

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BILG1/AILG1/AILZ1
Date: Wednesday, July 16, 2014 Sheet 34 of 60
5 4 3 2 1
 5 4 3 2 1

+3VS +3VS_DVGA +3VS_DVGA AVCC33 +3VS_DVGA VDD_DAC_33

@
RVG1 1 2 0_0603_5% LVG1 1 2 LVG2 1 2
PBY160808T-331Y-N PBY160808T-331Y-N

CVG2

CVG3
10U_0603_6.3V6M

10U_0603_6.3V6M
1 <BOM Structure> 1 <BOM Structure> 1
CVG1
.47U_0402_6.3V6K
2 2 2
@ POL1_SDA ( PIN22 )
+3VS_DVGA
@ 0 1

D D
0 X EP MODE

CVG4

CVG5
.1U_0402_10V6-K

2.2U_0603_10V6-K
1 2 POL2_SCL ( PIN23 )
VDD12

CVG6

CVG7

CVG8
.1U_0402_10V6-K
1 ROM ONLY MODE EEPROM MODE

CVG37
1

POL1_SDA
POL2_SCL
10U_0603_6.3V6M

.1U_0402_10V6-K

.1U_0402_10V6-K
2 1
1 1 1

LDO_EN
AVCC33

VDD12
2
2 2 2

25

24

23

22

21

20

19
@ UVG1 <BOM Structure>

AVCC_12

AVCC_33

POL2_SCL

DVCC_33_2

VCCK_12
LDO_EN
POL1_SDA
18 +3VS_DVGA +3VS_DVGA
<BOM Structure> XO
<BOM Structure>
<BOM Structure> 17
XI/CLKIN

1
16
RED_N
15 RED 4.7K_0402_5% 4.7K_0402_5%
RED_P RED 36 RVG2 RVG3
AUXP 26 14 @

POL2_SCL 2
AUX_P GND_DAC
AUXN 27 13

POL1_SDA
RVG4 AUX_N GREEN_N
1 2 RRX 28 12 GREEN
RRX GREEN_P GREEN 36
12K_0402_1%
DRX0P 29 11
LANE0P BULL_N

2
CVG9 1 2 .1U_0402_10V6-K DRX0N DRX0N 30 10 BLUE
4 VGA_TX0- LANE0N BULL_P BLUE 36
CVG101 2 .1U_0402_10V6-K DRX0P RVG5 RVG6
4 VGA_TX0+
CVG111 2 .1U_0402_10V6-K DRX1N DRX1P 31 9 VDD_DAC_33 4.7K_0402_5% 4.7K_0402_5%
4 VGA_TX1- LANE1P VDD_DAC_33
CVG121 2 .1U_0402_10V6-K DRX1P

DVCC_33_1
4 VGA_TX1+ @
CVG131 2 32 8

SMB_SDA
.1U_0402_10V6-K AUXN DRX1N VGA_HS

VGA_SDA
SMB_SCL

CVG15

CVG16
VGA_SCL
4 VGA_AUX# VGA_HS 36

1
CVG141 2 .1U_0402_10V6-K AUXP LANE1N HSYNC
C C

10U_0603_6.3V6M
.1U_0402_10V6-K
4 VGA_AUX 33 7 VGA_VS 1 1

HPD
GND VSYNC VGA_VS 36

RTD2168-CG_QFN32_5X5

6
2 2

+3VS_DVGA

+3VS_DVGA

VGA_HPD
CRT_DDC_DAT <BOM Structure>
CRT_DDC_DAT 36

CIIC_SDA
CIIC_SCL

2
4 VGA_HPD
RVG7 RVG8

CVG17
4.7K_0402_5% 4.7K_0402_5%

.1U_0402_10V6-K
2
CRT_DDC_CLK
CRT_DDC_CLK 36 1 Connect to EC I2C for EP Mode @ @
PR9450

1
100K_0402_1% CIIC_SCL
2 CIIC_SDA
1

<BOM Structure> +3VS_DVGA

2
RVG9
4.7K_0402_5%

2LDO_EN 1
B B

RVG12
4.7K_0402_5%
@

1
Embedded LDO
0 : VCCK_V12 from External 1.2V
1 : VCCK_V12 from Embedded LDO

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/06/28 Deciphered Date 2015/06/28 DP to CRT Converter

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BILG1/AILG1/AILZ1
Date: Wednesday, July 16, 2014 Sheet 35 of 60
5 4 3 2 1
 5 4 3 2 1

CRT Connector
+CRT_VCC_CON +5VS_HDMI

+5VS @
+CRT_VCC RVG16 1 2 0_0603_5%
DVG1
@ 2 FVG1
1 1 2 @ +CRT_VCC_CON
3 1
PMEG2010ET_SOT23-3 0.5A_8V_KMC3S050RY

1
CVG23
.1U_0402_10V6-K DVG2
W=40mils

1
D 2 D
CD@ AZ5425-01F_DFN1006P2E2
EMC_NS@

2
2
JCRT1
6
@ PAD TVG1 1 CRT_DET# 11
LVG4 1 2 CRT_R_CON 1
35 RED
BLM18BA100SN1D 7 For EMC
CRT_DDC_DAT 12
EMC@ 35 CRT_DDC_DAT
LVG5 1 2 CRT_G_CON 2
35 GREEN 8
BLM18BA100SN1D
EMC@ HSYNC_CON 13
LVG6 1 2 CRT_B_CON 3
35 BLUE 9
BLM18BA100SN1D

5P_0402_50V8-C

5P_0402_50V8-C

5P_0402_50V8-C

3.3P_0402_50V8-C

3.3P_0402_50V8-C

3.3P_0402_50V8-C
EMC@ VSYNC_CON 14
1

1
1 1 1 1 1 1 4

CVG24

CVG25

CVG26

CVG27

CVG28

CVG29
RVG17 RVG18 RVG19 10 G 16
75_0402_1% 75_0402_1% 75_0402_1% CRT_DDC_CLK 15 G 17
35 CRT_DDC_CLK 5
2 2 2 2 2 2
1
2

CVG30 SUYIN_070546HR015M25KZR
100P_0402_50V8J ME@
@
2
CLOSE TO UVG1 EMC@ EMC@ EMC@
EMC@ EMC@ EMC@

C C
+5VS
+5VS
2

CVG31 RVG24

2
RVG23 1 2 @ 1 @ 2
0_0402_5% 1K_0402_5% RVG25
Need change to 1.2K ohm

1
@ .1U_0402_10V6-K 0_0402_5%
5

@ RVG27 RVG28
1

@ 1.2K_0402_1% 1.2K_0402_1%
OE#
P

1
VGA_HS RVG26 1 2 0_0402_5% 2 4 CRT_HSYNC RVG29 1 2 0_0402_5% RVG30 1 2 33_0402_5% CRT_HSYNC_R LVG7 1 2 HSYNC_CON
35 VGA_HS A Y 0_0603_5%

2
G

@ UVG3 @
74AHCT1G125GW_SOT353-5 1
3

@ CRT_DDC_CLK
CRT_DDC_CLK 35
CVG32
15P_0402_50V8-J CRT_DDC_DAT
2 CRT_DDC_DAT 35

1 1
CVG33 CVG34
100P_0402_50V8J 68P_0402_50V8J
@ 2 2 @
+5VS
2

CVG35 RVG32
2

1 2 @ 1 @ 2 RVG33
RVG31 1K_0402_5% 0_0402_5%
0_0402_5% .1U_0402_10V6-K @
5

@
1

@
OE#
P
1

VGA_VS RVG34 1 2 0_0402_5% 2 4 CRT_VSYNC RVG35 1 2 0_0402_5% RVG36 1 2 33_0402_5% CRT_VSYNC_R LVG8 1 2 VSYNC_CON
35 VGA_VS A Y 0_0603_5%
G

@ UVG4 @ 1
74AHCT1G125GW_SOT353-5
3

@ CVG36
B 15P_0402_50V8-J B
2

DVG3 DVG4
CRT_B_CON 1 1 10 9 CRT_B_CON VSYNC_CON 1 1 10 9 VSYNC_CON

CRT_G_CON 2 2 9 8 CRT_G_CON HSYNC_CON 2 2 9 8 HSYNC_CON

CRT_R_CON 4 4 7 7 CRT_R_CON CRT_DDC_CLK 4 4 7 7 CRT_DDC_CLK

CRT_DET# 5 5 6 6 CRT_DET# CRT_DDC_DAT 5 5 6 6 CRT_DDC_DAT

3 3 3 3

8 8

AZ1045-04F_DFN2510P10E-10-9 AZ1045-04F_DFN2510P10E-10-9
EMC_NS@ EMC_NS@
For EMC

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/06/28 Deciphered Date 2015/06/28 CRT

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BILG1/AILG1/AILZ1
Date: Wednesday, July 16, 2014 Sheet 36 of 60
5 4 3 2 1
 5 4 3 2 1

+3VALW TO +3VALW_LAN

+3VALW
Need short
+3VALW_LAN
0.5ms spec 100ms ＜ ＜
+3VALW_LAN rising time (10%~90%):
+3VALW_LAN +LAN_VDDREG

@
JL1 1 2 @ width : 40 mils RL1 1 2
1 2 0_0603_5%
JUMP_43X79
D D
1 1
+3VALW LP2301ALT1G_SOT23-3 CL1 CL2

.1U_0402_10V6-K

.1U_0402_10V6-K
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
1 1 1 1 4.7U_0603_6.3V6K .1U_0402_10V6-K

D
Q14 3 1 @ CL4 CL5 CL6 CL7 CD@

.1U_0402_10V6-K

.01U_0402_16V7-K
1
2 2
RL2 1 1
100K_0402_5% CL8 CL9 @ 2 @ 2 2 2

G
2
@
2

2 2
RL3 1 @ 2 @ @
44 LAN_PWR_ON#
47K_0402_5%
<BOM Structure> <BOM Structure>
Close to Pin11 Close to Pin32 Close to Pin11 Close to Pin32
+3VALW_LAN +3VS

+3VALW_LAN

2
RL4

G
2
10K_0402_5% QL1
RL5 @
10K_0402_5% UL1

1
@ LAN_CLKREQ#_R 1 3 @
LAN_CLKREQ# 8

S
1

2N7002KW_SOT323-3
RL7 1 @ 2 0_0402_5% PCIE_WAKE#_R
8,9,40,44 PCIE_WAKE#
40,44 LAN_WAKE# RL6 2 1 0_0402_5%
@ 33 0_0402_5% 2 1 RL18
C +3VALW_LAN 32 GND 16 CLK_PCIE_LAN# @ C
1 2 31 AVDD33_2 REFCLK_N 15 CLK_PCIE_LAN# 8
RL8 RSET CLK_PCIE_LAN
RSET REFCLK_P CLK_PCIE_LAN 8
2.49K_0402_1% +LAN_VDD10 30 14 PCIE_PTX_C_DRX_N3
29 AVDD10 HSIN 13 PCIE_PTX_C_DRX_N3 9
LAN_XTALO PCIE_PTX_C_DRX_P3
CKXTAL2 HSIP PCIE_PTX_C_DRX_P3 9
LAN_XTALI 28 12 LAN_CLKREQ#_R
+3VS TL3 @ 1 27 CKXTAL1 CLKREQB 11 +3VALW_LAN
LAN_PWR_ON# RL121 @ 2 LAN_DISABLE# 26 LED0 AVDD33_1 10 LAN_MDI3-
LED1/GPIO MDIN3 LAN_MDI3- 38
0_0402_5% TL4 @ 1 25 9 LAN_MDI3+
LED2 MDIP3 LAN_MDI3+ 38
1

+LAN_REGOUT 24 8 +LAN_VDD10
RL9 +LAN_VDDREG 23 REGOUT AVDD10_2 7 LAN_MDI2-
22 VDDREG MDIN2 6 LAN_MDI2- 38
1K_0402_1% +LAN_VDD10 LAN_MDI2+
21 DVDD10 MDIP2 5 LAN_MDI2+ 38
PCIE_WAKE#_R LAN_MDI1-
LANWAKEB MDIN1 LAN_MDI1- 38
ISOLATE# 20 4 LAN_MDI1+
2

19 ISOLATEB MDIP1 3 LAN_MDI1+ 38

PLT_RST# +LAN_VDD10
8,19,40,44 PLT_RST# PERSTB AVDD10_1
9 PCIE_PRX_DTX_N3 CL10 1 2 .1U_0402_10V6-K PCIE_PRX_C_DTX_N3 18 2 LAN_MDI0-
HSON MDIN0 LAN_MDI0- 38
ISOLATE# RL10 1 @ 2 LAN_PWR_ON#
9 PCIE_PRX_DTX_P3 CL11 1 2 .1U_0402_10V6-K PCIE_PRX_C_DTX_P3 17 1 LAN_MDI0+
HSOP MDIP0 LAN_MDI0+ 38
0_0402_5% CL10 close to Pin18
1

RL11 CL11 close to Pin17

15K_0402_5%
@
2

RTL8111GUL-CG_QFN32_4X4
GIGA@

B B

LAN_XTALI For RTL8111GUL/ RTL8106EUL (SWR mode)

+LAN_VDD10
YL1 LAN_XTALO

1 4
OSC1 GND2 +LAN_REGOUT LL1 1 2
2 3 2.2UH_NLC252018T-2R2J-N_5%
GND1 OSC2
1 1 1 1 1 1 1 1
1 1
CL12 CL13 CL15 CL16 CL17 CL18 CL19 CL20 CL21 CL22
10P_0402_50V8J 25MHZ_10PF_7V25000014 10P_0402_50V8J 4.7U_0603_6.3V6K .1U_0402_10V6-K .1U_0402_10V6-K .1U_0402_10V6-K .1U_0402_10V6-K .1U_0402_10V6-K 1U_0402_6.3V6K .1U_0402_10V6-K
2 2 CD@ 2 2 2 2 2 @ 2 @
2 2
<BOM Structure> <BOM Structure> <BOM Structure> <BOM Structure>
Close to Pin3, 8, 22, 30 Close to Pin22(Reserved)
Layout Note: LL1 must be
within 200mil to Pin36,
CL15,CL16 must be within
200mil to LL1
+LAN_REGOUT: Width =60mil

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/06/28 Deciphered Date 2015/06/28 LAN_RTL8111GUL/RTL8106EUL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BILG1/AILG1/AILZ1
Date: Wednesday, July 16, 2014 Sheet 37 of 60
5 4 3 2 1
 5 4 3 2 1

DL1/DL2
1'S PN:SC300003M00 TL1 GIGA SIVΤ 璶璶
TL1 GIGA@
24 1 MCT1
D MCT1 TCT1 D
LAN_MDI0- 23 2 LAN_MDO0-
37 LAN_MDI0- MX1+ TD1+
DL1 EMC_NS@
LAN_MDI3- 9 3 LAN_MDI2- LAN_MDI0+ 22 3 LAN_MDO0+
I/O4 I/O2 37 LAN_MDI0+ MX1- TD1-

1
2
NC1 10 21 4 MCT2 RL17
4 NC5 MCT2 TCT2 20_0603_5%
NC2

1
5 11 LAN_MDI1- 20 5 LAN_MDO1-
+3VALW_LAN VDD GND 37 LAN_MDI1- MX2+ TD2+ DL3

1
2
6 8 LAN_MDI1+ 19 6 LAN_MDO1+ BS4200N-C-LV_SMB-F2
NC3 NC4 37 LAN_MDI1+ MX2- TD2-
EMC@

2
LAN_MDI3+ 7 1 LAN_MDI2+ 18 7 MCT3
I/O3 I/O1 MCT3 TCT3

2
AZ3033-04F_DFN2525P10E10 LAN_MDI2+ 17 8 LAN_MDO2+
37 LAN_MDI2+ MX3+ TD3+
20131128 37 LAN_MDI2-
LAN_MDI2- 16
MX3- TD3-
9 LAN_MDO2-
Place Close to TL1
Change DL1 net name 15
MCT4 TCT4
10 MCT4
1 1
LAN_MDI3+ 14 11 LAN_MDO3+ CL25
37 LAN_MDI3+ MX4+ TD4+

68P_0402_50V8J
DL2 CL32 1000P_1206_2KV7-K
LAN_MDI1+ 9 3 LAN_MDI0+ 1 LAN_MDI3- 13 12 LAN_MDO3- 0.022U_0402_25V7K @
I/O4 I/O2 37 LAN_MDI3- MX4- TD4- 2 2

CL24
2
NC1 10
C NC5 C
4 TAIMAG IH-181 1342 <BOM Structure>
5 NC2 11 2
+3VALW_LAN VDD GND
6 8
NC3 NC4
LAN_MDI1- 7 1 LAN_MDI0-
I/O3 I/O1 CHASSIS1_GND
<BOM Structure>
EMC_NS@
AZ3033-04F_DFN2525P10E10
Place Close to TL2 20131121 JRJ1 ME@
12

DL8 DL10
Reserve DL4 ,DL5 ,DL6 ,DL7 GND_4
11
LAN_MDO0- 4 3 LAN_MDO0- LAN_MDO1- 4 3 LAN_MDO1- GND_3
10
+3VALW
RL23
+3VALW
RL25
20131212 LAN_MDO0+ 1
PR1+
GND_2
9
1 2 5 2 1 2 5 2 Del DL4 ,DL5 ,DL6 ,DL7 LAN_MDO0- 2
PR1-
GND_1

LAN_MDO1+ 3
200_0603_5% CHASSIS1_GND 200_0603_5% CHASSIS1_GND PR2+ CHASSIS1_GND
@ 6 1 @ 6 1 LAN_MDO2+ 4
PR3+
B AZ1315-04S.R7G_SOT23-6L6 AZ1315-04S.R7G_SOT23-6L6 LAN_MDO2- 5 B
PR3-
EMC_NS@ EMC_NS@
LAN_MDO1- 6
20131205 LAN_MDO3+ 7
PR2-

Reserve 10/100 LAN surge function LAN_MDO3- 8

PR4+

DL9 DL11 PR4-

LAN_MDO0+ 4 3 LAN_MDO0+ LAN_MDO1+ 4 3 LAN_MDO1+
SANTA_130460-3
+3VALW +3VALW
RL24 RL26
1 2 5 2 1 2 5 2

200_0603_5% CHASSIS1_GND 200_0603_5% CHASSIS1_GND

@ 6 1 @ 6 1

AZ1315-04S.R7G_SOT23-6L6 AZ1315-04S.R7G_SOT23-6L6
EMC_NS@ EMC_NS@
EMC_NS@
RL14 1 2 0_0603_5%
EMC_NS@
A RL15 1 2 0_0603_5% A
EMC_NS@
RL16 1 2 0_0603_5%
Security Classification LC Future Center Secret Data Title
Issued Date 2014/06/28 Deciphered Date 2015/06/28 LAN_Transformer
CHASSIS1_GND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Reserve for EMI go rural solution AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
B 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BILG1/AILG1/AILZ1
Date: Friday, July 18, 2014 Sheet 38 of 60
5 4 3 2 1
 5 4 3 2 1

D D

Close to U1
SMSC thermal sensor REMOTE1+
Near GPU&VRAM
REMOTE+_R 1
placed near DIMM

1
1 C45 C
C44 100P_0402_50V8J 2 Q15
2200P_0402_50V7K @ B MMBT3904WH_SOT323-3
+3VS 2 E OPT@

3
2 REMOTE-_R U1 REMOTE1-
1 8 EC_SMB_CK2
VDD SCL EC_SMB_CK2 7,19,44

1 REMOTE+_R 2 7 EC_SMB_DA2
D+ SDA EC_SMB_DA2 7,19,44
C47 REMOTE-_R 3 6
.1U_0402_10V6-K D- ALERT#
CD@ 2 R51 2 @ 1 4 5 REMOTE2+
Near CPU core
+3VS T_CRIT# GND
10K_0402_5% 1

1
NCT7718W_MSOP8 C46 C
100P_0402_50V8J 2 Q16
@ B MMBT3904WH_SOT323-3
2 E UMA@
Address 1001_100xb

3
REMOTE2-

REMOTE1+ R175 1 @ 2 0_0402_5%

REMOTE2+ R176 1 @ 2 0_0402_5% REMOTE+_R

C REMOTE2- R177 1 @ 2 0_0402_5% REMOTE-_R C

REMOTE1- R178 1 @ 2 0_0402_5%

REMOTE+/-_R, REMOTE1+/-, REMOTE2+/-:

Trace width/space:10/10 mil
Trace length:<8"

FAN Conn
B B

+5VS
@ JFAN1
R52 1 2 0_0603_5% +5VS_FAN 1
2 1
44 EC_FAN_SPEED 2
1 1 44 EC_FAN_PWM 3
C50 4 3
C49 .1U_0402_10V6-K 5 4
10U_0805_10V6K @ 6 GND1
2 2 GND2
ACES_85205-04001
ME@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/06/28 Deciphered Date 2015/06/28 Thermal sensor/FAN CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BILG1/AILG1/AILZ1
Date: Wednesday, July 16, 2014 Sheet 39 of 60

5 4 3 2 1
 A B C D E

Mini-Express Card(WLAN/WiMAX) +3VS_WLAN

+3VS Need short +3VS_WLAN JWLAN1

J2 @ 1 2
1 2 3 GND1 3.3VAUX1 4
1 2 9 USB20_P6 5 USB_D+ 3.3VAUX2 6 1 @ T2
9 USB20_N6 USB_D- LED#1
JUMP_43X79 7 8
GND2 NC
9 NC NC 10
+3VALW 11 NC NC 12
LP2301ALT1G_SOT23-3 13 14
NC NC 16 1
15 @ T3
NC LED#2 18

D
Q17 3 1 AOAC@ 17
1 MLDIR_SENSE GND16 20 1

.01U_0402_16V7-K
19
21 DP_ML3N DP_AUXN 22
1 1 1 DP_ML3P DP_AUXP 24
C51 C52 C53 23

G
2
.1U_0402_10V6-K @ .1U_0402_10V6-K 25 GND3 GND13 26
@ AOAC@ 27 DP_ML2N DP_ML1N 28
2 2 2 29 DP_ML2P DP_ML1P 30
R54 1 AOAC@ 2 31 GND4 GND14 32
44 AOAC_ON#
1 33 DP_HPD DP_ML0N 34
100K_0402_5% C54 35 GND5 DP_ML0P 36
9 PCIE_PTX_C_DRX_P4
.1U_0402_10V6-K 37 PETP0 GND15 38 EC_TX_RSVD R62 1 @ 2 0_0402_5% EC_TX_R
9 PCIE_PTX_C_DRX_N4
AOAC@ 39 PETN0 RESERVED1 40 EC_RX_RSVD R63 1 @ 2 0_0402_5% BT_OFF#
2 41 GND6 RESERVED2 42
9 PCIE_PRX_DTX_P4
43 PERP0 RESERVED3 44
9 PCIE_PRX_DTX_N4 45 PERN0 COEX3 46
47 GND7 COEX2 48
8 CLK_PCIE_WLAN
49 REFCLKP0 COEX1 50 SUSCLK_R R55 1 @ 2 0_0402_5%
8 CLK_PCIE_WLAN# 51 REFCLKN0 SUSCLK 52 SUSCLK 8
PLT_RST#
PLT_RST# 8,19,37,44
WLAN_CLKREQ_Q# 53 GND8 PERST0# 54 BT_OFF# R53 1 2 1K_0402_5%
55 CLKREQ0# RESERVED/W_DISABLE#2 56 1 2 PCH_BT_OFF# 9
WLAN_OFF# R56 @ 0_0402_5%
8,9,37,44 PCIE_WAKE# PCH_WLAN_OFF# 9
57 PEWAKE0# W_DISABLE#1 58 SMB_DATA_S3_R R58 1 @ 2 0_0402_5%
SMB_DATA_S3 7,14,15
R57 1 @ 2 0_0402_5% 59 GND9 I2C_DATA 60 SMB_CLK_S3_R R59 1 @ 2 0_0402_5%
37,44 LAN_WAKE# 61 PETP1 I2C_CLK 62 1 SMB_CLK_S3 7,14,15
@ T4
63 PETN1 I2C_ALERT# 64 EC_TX_R
65 GND10 RESERVED4 66
67 PERP1 PERST1# 68 +3VS_WLAN
69 PERN1 CLKREQ1# 70
71 GND11 PEWAKE1# 72
73 REFCLKP1 3.3VAUX4 74
+3VS 75 REFCLKN1 3.3VAUX5
+3VS_WLAN GND12
76 77 EC_TX_R R184 1 2 100_0402_1%
PEG1 PEG2 EC_TX 44
2

JAE_SM3ZS067U410BAR1000 BT_OFF# R185 1 2 100_0402_1%

EC_RX 44
2

R60 ME@
G

Q18 10K_0402_5%

1
AOAC@
R186
1

2 8 WLAN_CLKREQ# AOAC@ 3 1 WLAN_CLKREQ_Q# 100K_0402_5% 2

S

2N7002KW_SOT323-3

2
R61 1 @ 2 0_0402_5%

If support AOAC, NC R61;

if not support AOAC, stuff R61.

3 3

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2014/06/28 Deciphered Date 2015/06/28 NGFF WLAN

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BILG1/AILG1/AILZ1
Date: Wednesday, July 16, 2014 Sheet 40 of 60
A B C D E
 A B C D E

+USB_VCCA

LEFT SIDE USB3.0 PORT X2 C55 1 2

+
220U_6.3V_M
U2 +USB_VCCA C56 1 2
+5VALW @ 1U_0603_25V6M
1 8
GND VOUT3 C57 1 2
1 2 7 @ 470P_0402_50V7K 1
2.2U_0603_10V6-K VIN1 VOUT2
C58 1 2 3 6
VIN2 VOUT1 JUSB1 ME@
44,45 @ USB_ON# USB_ON# 4 5 USB_OC1# 1
EN/EN FLAG USB_OC1# 9 USB20_N2 R65 1 @ 2 0_0402_5% USB20_N2_R 2 VBUS
9 USB20_N2 D-
1 USB20_P2 R64 1 @ 2 0_0402_5% USB20_P2_R 3
9 USB20_P2 D+
AP2820CMMTR-G1_MSOP8 C61 4 5
1000P_0402_50V7K GND GND1 6
@ GND2 7
Low Active 2A 2 GND3 8
GND4
C-K_20267-5K11-02

USB20_P2_R
+USB_VCCA
USB20_N2_R

AZ5425-01F_DFN1006P2E2

AZ5425-01F_DFN1006P2E2

AZ5425-01F_DFN1006P2E2
1

1
D9 D10 D11

1
2 2

2
EMC_NS@ EMC_NS@ EMC_NS@

2
USB20_P1_R
L8 D12 @
USB20_P2 1 2 USB20_P2_R USB30_RX_R_N1 9 10 1 1USB30_RX_R_N1 USB20_N1_R
1 2

AZ5425-01F_DFN1006P2E2

AZ5425-01F_DFN1006P2E2
USB30_RX_R_P1 8 9 2 2 USB30_RX_R_P1

1
USB20_N2 4 3 USB20_N2_R D13 D14
4 3 USB30_TX_R_N1 7 4 USB30_TX_R_N1
7 4

1
CMM21T-900M-N_4P
EMC@ USB30_TX_R_P1 6 6 5 5 USB30_TX_R_P1

3 3

2
8 EMC_NS@ EMC_NS@

2
AZ1045-04F_DFN2510P10E-10-9

3 3
L9 For EMC
USB30_RX_N1 3 4 USB30_RX_R_N1
3 4

USB30_RX_P1 2 1 USB30_RX_R_P1
2 1 +USB_VCCA
DLW21SN900HQ2L_4P
EMC@ C62 1 2
@ 1U_0603_25V6M
L10
USB30_TX_C_N1 3 4 USB30_TX_R_N1 C63 1 2
3 4 @ 470P_0402_50V7K

USB30_TX_C_P1 2 1 USB30_TX_R_P1
2 1 JUSB2 ME@
DLW21SN900HQ2L_4P USB30_TX_P1 C64 1 2 .1U_0402_10V6-K USB30_TX_C_P1 R68 1 @ 2 0_0402_5% USB30_TX_R_P1 9
9 USB30_TX_P1 StdA_SSTX+
EMC@ 1
L11 USB30_TX_N1 C65 1 2 .1U_0402_10V6-K USB30_TX_C_N1 R69 1 @ 2 0_0402_5% USB30_TX_R_N1 8 VBUS
9 USB30_TX_N1 StdA_SSTX-
USB20_N1 1 2 USB20_N1_R USB20_P1 R70 1 @ 2 0_0402_5% USB20_P1_R 3
1 2 9 USB20_P1 D+
7
USB20_N1 R71 1 @ 2 0_0402_5% USB20_N1_R 2 GND_DRAIN 10
9 USB20_N1 D- GND_1
USB20_P1 4 3 USB20_P1_R USB30_RX_P1 R72 1 @ 2 0_0402_5% USB30_RX_R_P1 6 11
4 3 9 USB30_RX_P1 StdA_SSRX+ GND_2
4 12
CMM21T-900M-N_4P USB30_RX_N1 R73 1 @ 2 0_0402_5% USB30_RX_R_N1 5 GND_5 GND_3 13
9 USB30_RX_N1 StdA_SSRX- GND_4
EMC@
SUYIN_020053GR009M2736L
4 4
For EMC

Security Classification LC Future Center Secret Data Title

Issued Date 2014/06/28 Deciphered Date 2015/06/28 USB2.0/USB3.0 PORT (LEFT)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BILG1/AILG1/AILZ1
Date: Wednesday, July 16, 2014 Sheet 41 of 60

A B C D E
 A B C D E F G H

SATA HDD Conn.

FOR 14"
JHDD1 ME@

1
SATA ODD Conn.
SATA_PTX_DRX_P0 C66 1 2 .01U_0402_16V7-K SATA_PTX_C_DRX_P0 2 GND_1
7 SATA_PTX_DRX_P0 A+
7 SATA_PTX_DRX_N0 SATA_PTX_DRX_N0 C67 1 2 .01U_0402_16V7-K SATA_PTX_C_DRX_N0 3
4 A-
1 SATA_PRX_DTX_N0 C68 1 2 .01U_0402_16V7-K SATA_PRX_C_DTX_N0 5 GND_2 1
7 SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 C69 1 2 .01U_0402_16V7-K SATA_PRX_C_DTX_P0 6 B-
7 SATA_PRX_DTX_P0 7 B+
GND_3

8
9 V33_1
V33_2
20141114
10
9 DEVSLP
DEVSLP
+5VS
Need short
+5VS_HDD 11
12
V33_3
GND_4 Delete G14 ODD function
20141213 J3 @ 13 GND_5
GND_6
Add DEVSLP function 1
1 2
2 14
15 V5_1
JUMP_43X79 16 V5_2
17 V5_3
18 GND_7
19 DAS/DSS
+5VS_HDD 20 GND_8
21 V12_1
22 V12_2
V12_3
1 1 1 1 1
C74 C75 C76 C77 C78 SUYIN_127043HR022M28DZR
1000P_0402_50V7K .1U_0402_10V6-K 1U_0402_10V6K 10U_0805_10V6K 10U_0805_10V6K
EMC_NS@ CD@ @
2 2 2 2 2

<BOM Structure> FOR 15"

2 2

For EMC SATA ODD FFC Conn

JODD2
7 SATA_PTX_DRX_P1 SATA_PTX_DRX_P1 C79 1 2 .01U_0402_16V7-K SATA_PTX_C_DRX_P1_15 1
SATA_PTX_DRX_N1 C80 1 2 .01U_0402_16V7-K SATA_PTX_C_DRX_N1_15 2 1
7 SATA_PTX_DRX_N1 2
3
SATA_PRX_DTX_N1 C81 1 2 .01U_0402_16V7-K SATA_PRX_C_DTX_N1_15 4 3
7 SATA_PRX_DTX_N1 SATA_PRX_DTX_P1 C82 1 2 .01U_0402_16V7-K SATA_PRX_C_DTX_P1_15 5 4
7 SATA_PRX_DTX_P1 6 5
R74 1 2 0_0402_5% ODD_DETECT#_R 7 6
7 ODD_DETECT# @ 8 7
+5V_ODD 9 8
9

2
ODD_DA#_R 10
R92 10
Need solder 0_0402_5% 11
@ 12 GND_1
J4 GND_2

1
1 2 ACES_51524-01001-003
1 2 ME@
JUMP_43X79

+5VALW +5VS +5V_ODD

LP2301ALT1G_SOT23-3
3 3

3
S

1 Q19
@
.1U_0402_10V6-K

.01U_0402_16V7-K
1

+3VS
C83

C84

@
10U_0805_10V6K

.1U_0402_10V6-K
1 1
R75 R76
G

1 1
2

10K_0402_5% 10K_0402_5% CD@

@

1
@2 @2
2

1
2 2
C86

@ R77
C85

ODD_EN# 1 2 R78 R79 @ 10K_0402_5%

100K_0402_5% 1 470_0603_5%
C87 @

2
@ .01U_0402_16V7-K @
2
1

Q20 D @ R80 1 2 0_0402_5% ODD_DA#_R

2 2 9 ODD_DA#
9 ODD_EN
G R86 1 @ 2 0_0402_5%
44 ODD_DA_EC#
1

Q21 D
2

S 2N7002KW_SOT323-3 ODD_EN# 2
3

R81 G
100K_0402_5%
@ @ S 2N7002KW_SOT323-3
3
1

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2014/06/28 Deciphered Date 2015/06/28 HDD/ODD CONN

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BILG1/AILG1/AILZ1
Date: Wednesday, July 16, 2014 Sheet 42 of 60
A B C D E F G H
 5 4 3 2 1

+3VS +1.5VS
@ +3VS +5VA AVDD_HP

.1U_0402_10V6-K

.1U_0402_10V6-K
RA2 1 2 0_0603_5% +3.3VD RA8 1 @ 2 0_0402_5%
+3VS

CA11

CA12
RA3 1 @ 2 0_0603_5% 2 2
+3VL
RA11 1 @ 2 0_0402_5% DVDD_IO @
RA5 1 2 0_0603_5% AVDD_HP
+5VS 1 1

.1U_0402_10V6-K
@ 2 20131213
RA7 1 2 0_0603_5% +5VA CA1 Change AVDD_HP PWR rail to +3VALW
D @ D
RA10 1 2 0_0603_5% +5VD 1 Close to Pin28 Close to Pin24
Close to Pin3 @ @

Close to Pin7
DA1
2 @
44 BEEP#

.1U_0402_10V6-K

4.7U_0603_10V6-K
.1U_0402_10V6-K CA16 close to Pin18
1 PC_BEEP1 CA2 1 2 PC_BEEP 2 1 CA17 close to Pin2
Close to Pin27

1
3
9 PCH_BEEP
RA14 <BOM Structure>
1 2

CA3

1U_0402_6.3V6K
.1U_0402_10V6-K
BAT54CW_SOT323-3 10K_0402_5%

CA4

CD@ CA7

CA8
2 1

.1U_0402_10V6-K

2.2U_0603_6.3V6K
UA1
2

2 1

CA5

CA6
HDA_RST_AUDIO# 9 3 FILT_1.8V
7 HDA_RST_AUDIO# RESET# FILT_1.8V 7 DVDD_IO 1 2
VDD_IO 2 <BOM Structure>
HDA_BITCLK_AUDIO 5 VDDO_3.3 18 +3.3VD 1 2
7 HDA_BITCLK_AUDIO BIT_CLK DVDD_3.3
HDA_SYNC_AUDIO 8 27 AVDD_3.3
7 HDA_SYNC_AUDIO RA16 SYNC AVDD_3.3 29 VREF_1.65V
33_0402_5% 1 2 SDATA_IN 6 VREF_1.65V 28 +5VA
7 HDA_SDIN0 SDATA_IN AVDD_5V

.1U_0402_10V6-K

1U_0402_6.3V6K
HDA_SDOUT_AUDIO 4
7 HDA_SDOUT_AUDIO SDATA_OUT <BOM Structure>

CA9

CA10
MICBIASB
CX20751-11Z
+3.3VD

2 1
PC_BEEP 10 12 SPK_L+
SPKR_MUTE# 39 PC_BEEP LEFT+ 14 SPK_L-
SPKR_MUTE# LEFT- DA2
JSENSE 38 17 SPK_R+ BAT54AWT1G_SOT323-3 1 2

LINE_B_R

LINE_B_L
JSENSE RIGHT+
2

1
37 15 SPK_R-
GPIO1/PORTC_R_MIC RIGHT-

1
C RA15 @ C
5.11K_0402_1% 36 35 RA42 RA41
33_0402_5% 1 RA18 2 40 MUSIC_REQ/GPIO0/PORTC_L_MIC MICBIASC 34
33 DMIC_CLK
DMIC_CLK_R
DMIC_CLK/MUSIC_REQ/GPIO0 MICBIASB
MICBIASB 0_0603_5% 0_0603_5% Close to Pin29
0_0402_5% 1 RA19 2 DMIC_DATA_R 1
1

33 DMIC_DATA DMIC_DAT/GPIO1

1
33 LINE_B_R <BOM Structure>

2
RA17 1 2 JSENSE .1U_0402_10V6-K PORTB_R_LINE 32 LINE_B_L
45 PLUG_IN 1 2 11 PORTB_L_LINE @ @
39.2K_0402_1% +5VD RA39 RA40
CA13 CLASS-D_REF 30 PORTD_A_MIC 100_0402_5% 100_0402_5%
RA36 1 2 13 PORTD_A_MIC 31 PORTD_B_MIC

2
16 LPWR_5.0 PORTD_B_MIC

3K_0402_1%

3K_0402_1%
20K_0402_1% <BOM Structure> RPWR_5.0

1
25 RING2_CONN 1 1
HGNDA

RA37

RA38
CA14 1 2 1U_0402_6.3V6K 19 26 RING3_CONN
20 FLY_P HGNDB CA35 CA36
FLY_N 24 AVDD_HP 4.7U_0603_10V6-K 4.7U_0603_10V6-K
CA17 1 2 2.2U_0603_6.3V6K 21 AVDD_HP 2 2

2
AVEE 23 HPOUT_R RA20 1 2 82.5_0402_1%
41 PORTA_R 22 HP_OUTR 45
HPOUT_L RA21 1 2 82.5_0402_1%
GND PORTA_L HP_OUTL 45
Reserve DA2 to prevent
+5VD cross-talk between RA22
CX20752-21Z_QFN40_5X5 PORTD_A_MIC 1 2 100_0402_5% CA20 1 2 2.2U_0603_6.3V6K
HPOUT_R/L, if stuff DA2, PORTD_B_MIC 1 2 100_0402_5% CA21 1 2 2.2U_0603_6.3V6K RING3_CONN 45
RA37/RA38 need change to RING2_CONN 45
CA15

CA16

CA18

CA19
4.7U_0603_10V6-K

4.7U_0603_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

1 1 2 2 3K. RA23
RA1 1 2 0_0402_5%
EMC_NS@
CD@ CD@ RA4 1 2 0_0402_5%
2 2 1 1 EMC_NS@
RA6 1 2 0_0402_5%
EMC_NS@
RA9 1 @ 2 0_0402_5% 20131120
B
Change PIN3 and PIN4 pin define JSPK1
B
RA12 1 @ 2 0_0402_5% SPK_R+_CONN 1
+3.3VD

20131128 SPK_R-_CONN 2 1
Close to Pin11,13,16 RA13 1 @ 2 0_0402_5% 3 2
Change pin define SPK_L-_CONN
3
SPK_L+_CONN 4
4
20131213
RA24 1 @ 2 5
Change pin define
1

0_0402_5% 6 GND1
GND GNDA GND2
RA28
47K_0402_5% Use 250mils wide trace bridging ACES_88231-04001
RB751V-40_SOD323-2 @ AGND and DGND at codec ME@
HDA_RST_AUDIO# DA3 1 2 @
2

SPKR_MUTE#
RB751V-40_SOD323-2
EC_MUTE# DA4 1 2 @
44 EC_MUTE# HDA_RST_AUDIO# SPK_R+ 1 2 SPK_R+_CONN
RA26 BLM18PG221SN1D_2P
SPK_R- RA31 1 2 BLM18PG221SN1D_2P SPK_R-_CONN
HDA_SYNC_AUDIO SPK_L+ RA30 1 EMC@ 2 BLM18PG221SN1D_2P SPK_L+_CONN
@ SPK_L- RA34 1 EMC@ 2 BLM18PG221SN1D_2P SPK_L-_CONN
RA35 1 2 0_0603_5% HDA_SDOUT_AUDIO EMC@
EMC@
RA27 1 @ 2 HDA_BITCLK_AUDIO

470P_0402_50V7K

470P_0402_50V7K

470P_0402_50V7K

470P_0402_50V7K
27_0402_5%
HDA_SDIN0 20131212 1 1 1 1

CA31

CA32

CA33

CA34
delete CA27
CA23

CA24

CA25

CA26

CA28,CA29,CA30,RA25,RA29,RA32,RA33
68P_0402_50V8J

22P_0402_50V8-J

22P_0402_50V8-J

33P_0402_50V8J

33P_0402_50V8J

DMIC_CLK
2 2 2 2
1 1 1 1 1
CA22

DMIC_DATA
EMC@ EMC@
2 2 2 2 2
EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@
100P_0402_50V8J

100P_0402_50V8J
CA37

CA38

A A

1 1 EMC@ EMC@ EMC@ EMC@ EMC@

For EMI
2 2

Security Classification LC Future Center Secret Data Title

Issued Date 2014/06/28 Deciphered Date 2015/06/28 Codec_CX20752

For EMI THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BILG1/AILG1/AILZ1
Date: Friday, July 18, 2014 Sheet 43 of 60
5 4 3 2 1
 5 4 3 2 1

For EMI RE1 1 @ 2 0_0603_5%

For ESD EMC_NS@
+3VL
PLT_RST# CLK_PCI_EC RE2 1 2 10_0402_5%
@
RE3 1 2
1 1 Close EC 0_0603_5%
+3VALW
CE1 CE2 +3VALW_EC
220P_0402_50V7K 10P_0402_50V8J CE3 +3VALW_R +3VALW_R
2 EMC@ EMC_NS@ 2 1 2 VCOREVCC
LE1 1 2 HCB1608KF-181T20
.1U_0402_10V6-K +3VALW_R All capacitors close to EC +3VALW_R
1 1
@ CE4

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K
1 1 1 1 1 1 .1U_0402_10V6-K CE5

1
+3VS +3VALW_EC CE6 CE7 CE8 CE9 CE10 CE11 1000P_0402_50V7K
VCCRTC RE4 1 @ 2 0_0402_5% LE2 1 2 HCB1608KF-181T202 EC_AGND 2 RE5
D D
CD@ @ 10K_0402_5%
2 2 2 2 2 2
RE6 1 2 0_0402_5% EC_AGND

2
@
LAN_WAKE# LAN_WAKE# 37,40

minimum trace width 12 mil

114
121
127
Change RE6 to 0ohm jump

12

11

26
50
92

74
3
UE1

VSTBY1
VSTBY2
VSTBY3
VSTBY4
VSTBY5
VCC

AVCC
VBAT

VSTBY(PLL)
VCORE
+3VS

19 WRST# EC_FAN_SPEED RE10 1 2 10K_0402_5%

4 24
+3VALW_R 9 KBRST# 5 KBRST#/GPB6 PWM0/GPA0 25 PWR_LED# 45
EC_FAN_PWM RE11 1 @ 2 10K_0402_5%
9 SERIRQ SERIRQ/GPM6 PWM1/GPA1 BATT_CHG_LED# 45
LPC_FRAME# 6 28
7 LPC_FRAME# 7 LFRAME#/GPM5 PWM2/GPA2 29 BATT_LOW_LED# 45 1 2 10K_0402_5%
LPC_FRAME# RE7
7 LPC_AD3 LAD3/GPM3 PWM3/GPA3 BATT_LEN# 52
DE1 1 2 @ 8 PWM 30
7 LPC_AD2 LAD2/GPM2 PWM4/GPA4 SYS_PWROK 8
9 31 EC_FAN_PWM ENBKL RE9 1 @ 2 100K_0402_5%
7 LPC_AD1 10 LAD1/GPM1 PWM5/GPA5 32 EC_FAN_PWM 39
RB751V-40_SOD323-2 7 LPC_AD0 LAD0/GPM0 PWM6/SSCK/GPA6 BEEP# 43
CLK_PCI_EC 13 LPC 34 SUS_VCCP
1 2 100K_0402_5% 8 CLK_PCI_EC 14 LPCCLK/GPM4 PWM7/RIG1#/GPA7 120 SUS_VCCP 57
RE8 WRST# LAN_WAKE#
15 WRST# TMRI0/GPC4 124 SUSP# +3VS +5VS +3VS
9 EC_SMI# ECSMI#/GPD4 TMRI1/GPC6 SUSP# 35,46,55,56,57
1 EC_RX 16
40 EC_RX 17 PWUREQ#/BBO/SMCLK2ALT/GPC7 66
EC_TX NTC_V 52
40 EC_TX LPCPD#/GPE6 ADC0/GPI0

1
CE12 PLT_RST# 22 67
1U_0402_6.3V6K 8,19,37,40 PLT_RST# LPCRST#/GPD2 ADC1/GPI1 TURBO_V 52 @
23 68 BATT_TEMP RE52 RE51
2 9 EC_SCI# ECSCI#/GPD3 ADC2/GPI2 BATT_TEMP 52,53 10K_0402_5%
@ 1 PAD 126 ADC 69 0_0402_5% 0_0402_5%
IT9 GA20/GPB5 ADC3/GPI3 VR_IMVP_IMON 59 RE53
70 @
IT8586E/AX ADC4/GPI4 71 VR_CPU_PWROK
ADP_I 52,53
10,59

2
ADC5/DCD1#/GPI5 72

45 KSI[0..7]
KSI[0..7] KSI0 58
KSI0/STB#
LQFP-128L ADC6/DSR1#/GPI6
ADC7/CTS1#/GPI7
73 ADAPTER_ID 51,53
RE50 1 @ 2 10K_0402_5%
TP_CLK RE12 2 1 4.7K_0402_5%
@

KSI1 59 78
KSO[0..17] KSI1/AFD# DAC2/TACH0B/GPJ2 SUSWARN# 8
KSI2 60 79 @ TP_DATA RE13 2 1 4.7K_0402_5%
45 KSO[0..17] KSI2/INIT# DAC3/TACH1B/GPJ3 MAINPWON 52
C KSI3 61 DAC 80 H_PROCHOT#_EC RE14 1 2 0_0402_5% C
62 KSI3/SLIN# DAC4/DCD0#/GPJ4 81 PROCHOT# 52
KSI4 ENBKL 33
KSI4 DAC5/RIG0#/GPJ5
+3VALW_R
KSI5 63
KSI5 Change RE14 to 0ohm jump
KSI6 64 85 +5VALW
65 KSI6 PS2CLK0/TMB0/CEC/GPF0 86 VGA_PWRGD 9,22
KSI7
KSI7 PS2DAT0/TMB1/GPF1 PBTN_OUT# 8
KSO0 36 87
1 37 KSO0/PD0 GPF2 88 PM_SLP_SUS# 8
EC_SMB_CK1 PAD @ KSO1 Int. K/B PS2 USB_ON# RE15 1 2 100K_0402_5%
IT1 KSO1/PD1 GPF3 SUSACK# 8
1 RE16 2 2.2K_0402_5% EC_SMB_CK1 EC_SMB_DA1 PAD 1 @ KSO2 38 89 TP_CLK
1
IT2
KSO3 39 KSO2/PD2 Matrix PS2CLK2/GPF4 90 TP_DATA
TP_CLK 45
PAD @
1 RE17 2 2.2K_0402_5% 1 IT3 40 KSO3/PD3 PS2DAT2/GPF5 TP_DATA 45
EC_SMB_DA1 PAD @ KSO4
IT4 KSO4/PD4
PAD 1 @ KSO5 41 EXTERNAL SERIAL FLASH 96 +3VALW_R
IT5 42 KSO5/PD5 GPH3/ID3 97 CAPS_LED# 45
KSO6
KSO6/PD6 GPH4/ID4 PCH_PWR_EN 46,52
KSO7 43 98
KSO7/PD7 GPH5/ID5 ACOFF 53
KSO8 44 99
+3VS 1 45 KSO8/ACK# GPH6/ID6 PCH_PWROK 8,10
KSI7 PAD @ KSO9 SUSP# RE18 1 @ 2 100K_0402_5%
IT6 KSO9/BUSY
KSI6 PAD 1 @ KSO10 46 101 EC_SPI_CS0#
1 IT7 51 KSO10/PE NC1 102
WRST# PAD @ KSO11 EC_SPI_SI SUSP# RE19 1 2 100K_0402_5%
IT8 KSO11/ERR# NC2
1 RE20 2 2.2K_0402_5% EC_SMB_CK2 KSO12 52 SPI Flash ROM 103 EC_SPI_SO
KSO13 53 KSO12/SLCT NC3 105 EC_SPI_CLK SYSON RE21 1 2 100K_0402_5%
1 RE22 2 2.2K_0402_5% 54 KSO13 NC4
EC_SMB_DA2 For factory EC flash KSO14
KSO14
KSO15 55 SUS_VCCP RE23 1 2 100K_0402_5%
KSO16 56 KSO15 108 ACIN#
KSO17 57 KSO16/SMOSI/GPC3 AC_IN# 109 LID_SW# EC_ADAPTER_R RE28 1 @ 2 100K_0402_5%
KSO17/SMISO/GPC5 UART LID_SW# LID_SW# 45

45 ON/OFF ON/OFF 110 82 VGA_GATE#

111 PWRSW# EGAD/GPE1 83 VGA_GATE# 4
54 EC_ON XLP_OUT SM Bus EGCS#/GPE2 VDDQ_PGOOD 55
EC_SMB_CK1 115 84 ADAPTER_ID_ON# 53
52,53 EC_SMB_CK1 SMCLK1/GPC1 EGCLK/GPE3
EC_SMB_DA1 116 RE26 2 @ 1 0_0402_5%
52,53 EC_SMB_DA1 SMDAT1/GPC2 EC_ADAPTER 51
5 H_PECI RE24 1 2 43_0402_5% PECI_EC 117 GPIO 77
SMCLK2/PECI/GPF6 GPJ1 EC_MUTE# 43
118 100 GPG2
37 LAN_PWR_ON# 94 SMDAT2/PECIRQT#/GPF7 SSCE0#/GPG2 106
EC_SMB_CK2 EC_ADAPTER_R RE25 2 @ 1 0_0402_5%
7,19,39 EC_SMB_CK2 CRX1/SIN1/SMCLK3/GPH1/ID1 SSCE1#/GPG0 PM_SLP_S5# 8
EC_SMB_DA2 95 104 SYSON
+3VL 7,19,39 EC_SMB_DA2 CTX1/SOUT1/GPH2/SMDAT3/ID2 DSR0#/GPG6 ME_FLASH 7
107 SYSON
DTR1#/SBUSY/GPG1/ID7 119 SYSON 55
BKOFF#
CRX0/GPC0 BKOFF# 33
@ 123
RE27 1 2 0_0402_5% 112 CTX0/TMA0/GPB2 18 AOAC_ON# 40 EMC Request 1
VSTBY0 RI1#/GPD0 PM_SLP_S3# 8
125 21 PM_SLP_S4# 8 RE29 1 2 0_0402_5% EMC_NS@
B 59 EC_VR_ON GPE4 RI2#/GPD1 PCIE_WAKE# 8,9,37,40 B
WAKE UP 76 NOVO# 45 CE13
TACH2/GPJ0 48 .1U_0402_10V6-K
TACH1A/TMA1/GPD7 47 EC_FAN_SPEED @ 2
TACH0A/GPD6 EC_FAN_SPEED 39
USB_ON# 33 19 RE30 1 2 0_0402_5% VGA_AC_DET
41,45 USB_ON# GINT/CTS0#/GPD5 L80HLAT/BAO/GPE0 VGA_AC_DET 19
35 GPIO 20
8 DPWROK_EC RTS1#/GPE5 L80LLAT/GPE7 NUM_LED# 45
93
8 EC_RSMRST# CLKRUN#/GPH0/ID0 ODD_DA_EC# 42

2 Reserve for VGA_AC_DET

9 EC_LID_OUT# CK32KE/GPJ7
128 Clock
+3VL 8 AC_PRESENT CK32K/GPJ6

Change RE30 to 0ohm jump

RE34 1 2 0_0402_5% H_PROCHOT# 5,51,52
59 VR_HOT# +5VS +3VS
AVSS

RE35 1 2 10K_0402_5% ON/OFF

VSS1

VSS2
VSS3
VSS4
VSS5
VSS6

@ @

1
RE36 1 @ 2 10K_0402_5% BKOFF# QE1 D 1 RE37 1 @ 2 0_0402_5%
IT8586E-AX_LQFP128_14X14 H_PROCHOT#_EC 2 CE14
1

27
49
91
113
122

75

RE38 1 2 10K_0402_5% LID_SW# G 47P_0402_50V8J RE39 1 @ 2 0_0402_5% J80P1

@ 1
2N7002KW_SOT323-3 S 2 EC_TX 2 1

3
EC_RX 3 2
RE40 1 2 10K_0402_5% BKOFF# 4 3
4

1
EC_AGND +3VL 5
RE41 6 GND1
100K_0402_5% GND2
@ ACES_85205-04001
for EC version update to EX, manual modify PN to FX

1
ME@

2
RE42
10K_0402_5%
PECI_EC @ CE15 1 2 47P_0402_50V8J

2
+3VL BATT_TEMP @ CE16 1 2 100P_0402_50V8J +3VS ACIN#
8,53 ACIN#
+3VALW_R ACIN# @ CE17 1 2 100P_0402_50V8J

1
1 D QE2
A GPG2 RE43 2 @ 1 10K_0402_5% ON/OFF @ CE18 1 2 1U_0402_6.3V6K CE19 2 A
.1U_0402_10V6-K G ACIN 53
NOVO#
GPG2 RE44 2 1 10K_0402_5% EC_SPI_CS0# RE45 2 @ 1 0_0402_5% SPI_CS0#
SPI_CS0# 7 2 2N7002KW_SOT323-3 S

3
.01U_0402_16V7-K

GPG2 RE46 2 @ 1 10K_0402_5%

RE47 2 1 0_0402_5%
C48

EC_SPI_SI @ SPI_SI @
SPI_SI 7
when mirror, GPG2 pull high 1

when no mirror, GPG2 pull low EC_SPI_SO RE48 2 @ 1 0_0402_5% SPI_SO

SPI_SO 7
@ 2 Title
EC_SPI_CLK RE49 2 @ 1 0_0402_5% SPI_CLK Security Classification LC Future Center Secret Data
SPI_CLK 7
Issued Date 2014/06/28 Deciphered Date 2015/06/28 EC ITE8586LQFP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BILG1/AILG1/AILZ1
Date: Friday, July 18, 2014 Sheet 44 of 60
5 4 3 2 1
 5 4 3 2 1

ON/OFF switch K/B Connector

+3VL +3VALW +3VS 14" 15"
KB_1 KSI1_14 KSO0_15
KSI[0..7]
KSI[0..7] 44

2
KB_2 KSI7_14 KSI2_15
R82 R83 KSO[0..17]
KSO[0..17] 44 15"

1
@ 100K_0402_5% 100K_0402_5% KB_3 KSI6_14 KSI3_15
R84 R90
300_0402_5% 300_0402_5% KB_4 KSO9_14 KSO5_15

1
D15 JKB1
NOVO# 2 NUM_LED# 30 31 KB_5 KSI4_14 KSO1_15
44 NOVO# 44 NUM_LED#

2
PWR_NUM_LED 29 30 GND1 32
1 NOVO_BTN# CAPS_LED# 28 29 GND2
44 CAPS_LED# 28 KB_6 KSI5_14 KSI0_15
@ PWR_CAPS_LED 27
ON/OFF R85 1 2 0_0402_5% 3 EMC@ KSO17 26 27
26
KB_7 KSO0_14 KSO2_15
D NUM_LED# C118 1 2 0.1U_0402_10V7K KSO16 25 D
BAT54CW_SOT323-3 KSO15 24 25
24 KB_8 KSI2_14 KSO4_15
CAPS_LED# C117 1 2 0.1U_0402_10V7K KSO10 23
KSO11 22 23
22 KB_9 KSI3_14 KSO7_15
EMC@ KSO14 21
+3VALW +3VL KSO13 20 21
20
KB_10 KSO5_14 KSO8_15
KSO12 19
KSO3 18 19
18 KB_11 KSO1_14 KSO6_15

2
KSO6 17
R111
100K_0402_5%
R114
100K_0402_5%
20141114 KSO8
KSO7
16
15
17
16
15
KB_12 KSI0_14 KSO3_15
KSO4 14
@
Delete G14 KB function KSO2 13 14 KB_13 KSO2_14 KSO12_15

1
@ KSI0 12 13
12 KB_14 KSO4_14 KSO13_15
ON/OFFBTN# R119 1 2 0_0402_5% ON/OFF KSO1 11
ON/OFF 44 10 11
KSO5 KB_15 KSO7_14 KSO14_15
KSI3 9 10
J5 1 2 KSI2 8 9
KB_16 KSO8_14 KSO11_14
SHORT PADS
20140311 KSO0
KSI5
7
6
8
7
6
KB_17 KSO6_14 KSO10_15
J6 1 2 Delete KB Cap function KSI4
KSO9
KSI6
5
4
3
5
4 KB_18 KSO3_14 KSO15_15
SHORT PADS KSI7 2 3
2 KB_19 KSO12_14 KSO16_15
KSI1 1
1
KB_20 KSO13_14 KSO17_15
For EMC ACES_50504-3041-001
ME@ KB_21 KSO14_14 KB_LED_PWR_15
TP/B Connector
KB_22 KSO11_14 CAPS_LED#_15
KB_23 KSO10_14 VDD_15
KB_24 KSO15_14 NUM_LED#_15

+5VS TP_PWR TP_CLK

C R160 1 @ 2 ME@
TP_DATA PWR/B Connector C
USB I/O Connector

2
+3VS 0_0402_5% ACES_50503-0060N-001
8 DT1
R141 1 @ 2 0_0402_5% 6 GND2 7
TP_CLK 5 6 GND1
44 TP_CLK 5
TP_DATA 4
44 TP_DATA 4
.1U_0402_10V6-K

1 TP_P4 3
@ 1 @ 1 TP_P5 2 3
2
Right Side USB2.0 Port X 1 (USB/B)
100P_0402_50V8J

100P_0402_50V8J

TP_P6 1
1
2 JTP1
C114

2 2
C115

C116

EMC_NS@ AZC199-02S.R7G_SOT23-3 +3VL +5VALW U3 +USB_VCCB

1
For EMC +USB_VCCB
JPWRB1 1 8 JUSB3
1 2.2U_0603_10V6-K GND VOUT3 +3VS 18 20
@ NOVO_BTN# 2 1 C119 1 2 2 7 17 18 G2 19
ON/OFFBTN# 3 2 VIN1 VOUT2 16 17 G1
LID_SW# 4 3 3 6 R66 1 @ 2 0_0402_5% USB20_N0_CONN 15 16
CD@ 9 USB20_N0
5 4 VIN2 VOUT1 R67 1 @ 2 0_0402_5% USB20_P0_CONN 14 15
5 9 USB20_P0 14
6 7 USB_ON# 4 5 USB_OC2# 13

AZ5215-01F_DFN1006P2E2
6 GND1 41,44 USB_ON# EN/EN FLAG USB_OC2# 9 13

1
8 R87 1 @ 2 0_0402_5% USB20_N3_CONN 12
GND2 9 USB20_N3 1 2 0_0402_5% USB20_P3_CONN 11 12
D17 1 R88 @

1
9 USB20_P3 10 11
ACES_50503-0060N-001 AP2820CMMTR-G1_MSOP8 C120
ME@ 1000P_0402_50V7K 9 10
@ 8 9
ACES_51524-00801-001 Low Active 2A 2 8

2
HP_OUTR 7
For 14" For 15" 10 EMC_NS@
43 HP_OUTR
HP_OUTL 6 7
43 HP_OUTL

2
9 GND_2 5 6
8 GND_1 LID_SW# 44 4 5
TP_P6 RING2_CONN
1 VDD 1 VDD TP_P5 7 8
7
43 RING2_CONN 3 4
3
PWR_LED# 6 RING3_CONN 2
44 PWR_LED# 5 6 43 RING3_CONN 1 2
BATT_LOW_LED# PLUG_IN
44 BATT_LOW_LED# 5 43 PLUG_IN 1
BATT_CHG_LED# 4 For EMC
2 CLK 2 CLK 44 BATT_CHG_LED#
+5VALW 3 4
3
ACES_50505-0184N-P01
+3VALW 2 EMC@ ME@
1 2
1 1 .1U_0402_10V6-K
3 DAT 3 DAT JLED1 CC103
ME@ L14
USB20_P0 1 2 USB20_P0_CONN 2
B 1 2 B
4 GND 4 GND
USB20_N0 4 3 USB20_N0_CONN
4 3
EMC_NS@ CMM21T-900M-N_4P
5 TP-L 5 TP-L
L15
USB20_P3 1 2 USB20_P3_CONN
6 TP-R 6 TP-R 20141114
1 2

Delete G14 TP click function USB20_N3 4

4 3
3 USB20_N3_CONN

EMC_NS@ CMM21T-900M-N_4P

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/06/28 Deciphered Date 2015/06/28 KBD/PWR/IO/LED/TP Conn.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BILG1/AILG1/AILZ1
Date: Friday, July 18, 2014 Sheet 45 of 60
5 4 3 2 1
 A B C D E

+5VALW to +5VS +3VALW to +3VS

AP4800BGM AP4800BGM
VGS=10V, ID=9A, Rds=18m ohm VGS=10V, ID=9A, Rds=18m ohm
VGS=+-25V VGS=+-25V

+5VALW +5VS +3VALW +3VS

Q23 Q24

8 1 8 1
7 2 1 1 7 2 1 1
1 6 3 1 6 3
1 C124 5 C121 C122 C125 5 C123 C126 1
10U_0805_25V6K 10U_0805_10V6K 1U_0603_25V6M 10U_0805_25V6K 10U_0603_6.3V6M 1U_0603_25V6M

1
@ AP4800BGM-HF_SO-8 2 CD@ 2 CD@ @ AP4800BGM-HF_SO-8 2 CD@ 2 CD@

4
2 R145 2 @ R146
@ 470_0603_5% 470_0603_5%

2
R148 2 R147 1 5VS_GATE
5VS_GATE_R 1 2 5VS_GATE 2 R149 1 5VS_GATE 35
+20VSB 0_0402_5%
82K_0402_1% 150K_0402_5% R150
3VS_GATE_R 1 @ 2 2 R151 1 3VS_GATE 2 R152 1 +20VSB

1
1 D Q25 Q26 D 0_0402_5% @ 470K_0402_5%
R153 2 SUSP 2 0_0402_5% @

1
C127 820K_0402_5% G G 1 D Q27 Q28 D
0.01U_0402_25V7K @ R154 2 SUSP 2
2 S 2N7002KW_SOT323-3 @ S 2N7002KW_SOT323-3 C128 820K_0402_5% G G

3
0.01U_0402_25V7K @
<BOM Structure> 2 S 2N7002KW_SOT323-3 @ S 2N7002KW_SOT323-3

3
@
<BOM Structure>

+5VALW

+3VALW Need short +3VALW_PCH +5VLP +5VALW

2 2

1
J7 @
1 2
1 2

1
R155
100K_0402_5% R157 R156 +0.675VS
JUMP_43X79
@ 100K_0402_5% 100K_0402_5%
2

1
PCH_PWR_EN#_R R158 1 @ 2 100K_0402_5% PCH_PWR_EN#

2
LP2301ALT1G_SOT23-3 Id=3.2A R159
SUSP 47_0603_5%
34 SUSP
1

D
Q30 D Q29 3 1 @ @
PCH_PWR_EN 2
44,52 PCH_PWR_EN

2
G 1 1
C129 C130

G
2

3
@ S 2N7002KW_SOT323-3 .1U_0402_10V6-K 0.01U_0402_25V7K Q6A D D Q6B
3
1

@ @ 2 5 SUSP
2 2 35,44,55,56,57 SUSP# G G
R162
100K_0402_5% PCH_PWR_EN#_R 2N7002KDWH_SOT363-6 S S 2N7002KDWH_SOT363-6

4
@
2

1
C131
.1U_0402_10V6-K
@
2

3 3

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2014/06/28 Deciphered Date 2015/06/28 DC V TO VS INTERFACE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BILG1/AILG1/AILZ1
Date: Wednesday, July 16, 2014 Sheet 46 of 60

A B C D E
 5 4 3 2 1

B2 A2
D
+3VLP PCH_PWR_EN# 2 D

Q25,+3V_PCH

V
V
AC A1
MODE VIN

V V
A2 A4 B5
3 +3V_PCH

V
PU301 PU904

V
B+
+3VALW
BATT BATT V 1
DPWROK_EC
V
MODE

V V V
B1
4
PCH_RSMRST#
EC 14
PM_DRAM_PWRGD
5 PBTN_OUT#

V
EC_ON PM_SLP_S3# PCH 15
PM_SLP_S4# H_CPUPWRGD CPU

V V
A3 B4 PM_SLP_S5#
PM_SLP_SUS# 6

V
CPU_PLTRST# 16
12
PCH_PWROK

V V
C C

B3 13
SYS_PWROK

V
ON/OFF V
NOVO

NVDD_PWR_EN
(DIS)
Vb
+VGA_CORE

V
11 VR_REDY SYSON 7 +1.35V
PU801
PU501

V
DGPU_PWROK
DGPU_PWR_EN
10 Va (DIS)

V
PU901 VR_ON +1.5VS_VGA

V
Q31
V

PU601

V
+CPU_CORE
+5VS

B B

V
Q32 +1.05VSP_VGA

V
SUSP#,SUSP 9 +3VS PU702

V
VGA

V
PU602
+1.5VS +3VS_VGA

V
Q27

V
PU502
+0.675V
8
SUS_VCCP PU701
V
+1.05VS

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/06/28 Deciphered Date 2015/06/28 Power sequence Block

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BILG1/AILG1/AILZ1
Date: Wednesday, July 16, 2014 Sheet 47 of 60
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/06/28 Deciphered Date 2015/06/28 Virtual symbol

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BILG1/AILG1/AILZ1
Date: Wednesday, July 16, 2014 Sheet 48 of 60
5 4 3 2 1
 5 4 3 2 1

20131203
Delete NH2
NH1 NH4 20131203
HOLEA HOLEA Change H6 Footprint to PAD_C8P0D2P8
20131121
Change H11 screw hole footprint from pad_ct6p0d4p3 to PAD_C6P0D4P3
1

1
D D
Change H21 screw hole footprint from pad_ct5p5b8p0d2p5 to PAD_C6P0D2P8
pad_c2p3d2p3n pad_o2p3x2p8d2p3x2p8n
20131121
Change H16 Footprint to PAD_CB6P0D2P8
20131121
Change footprint from PAD_CB5P0D4P0 to PAD_CT6P0B5P0D4P0
H3 H4 H5 H6 H7 H8 H9 H10 H11 H12
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA

20131121
Delete H1 ,H2

1
PAD_C8P0D2P8 PAD_C8P0D2P8 PAD_CB8P0D2P8 PAD_C8P0D2P8 PAD_CT6P0B5P0D4P0 PAD_CT6P0B5P0D4P0 PAD_CT6P0B5P0D4P0 PAD_CT6P0B5P0D4P0 PAD_C6P0D4P3 PAD_C8P0D2P8

20131203
C C
Change H13 Footprint to PAD_C9P0D7P6

H13 H15 H16 H17 H18 H19 H20 H22 H23 H21
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
20131121
Delete H14
1

1
CHASSIS1_GND
PAD_C9P0D7P6 PAD_C8P0D2P8 PAD_C6P0D2P8 PAD_C8P0D2P8 PAD_ShapeT5P0X6P0-D PAD_shapeT5P0X6P0-U PAD_CB6P0D3P3 PAD_CB6P0D3P3 PAD_CT5P0B6P0D3P3
PAD_C6P0D2P8

PCB Fedical Mark PAD

FD1 FD2 FD3 FD4 FD5 FD6
B B
+VGA_CORE +3VS +5VALW +3VALW
1

C137 1 2 .1U_0402_10V6-K
EMC_NS@
1 1
C135 C136
.1U_0402_10V6-K .1U_0402_10V6-K
EMC_NS@ EMC_NS@
2 2

GP1 GP2 GP7 GP8

PAD_RT2P65X2P2 PAD_RT2P65X2P2 PAD_RT2P65X2P2 PAD_RT2P65X2P2
@ @ @ @
1

1
1

For EMC
GP11 GP12
PAD_RT2P45X2P5 PAD_RT2P45X2P5
A @ @ A
1

1
1

Security Classification LC Future Center Secret Data Title

Issued Date 2014/06/28 Deciphered Date 2015/06/28 Hole
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
FFC CONN GROUND PAD AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
B 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BILG1/AILG1/AILZ1
Date: Wednesday, July 16, 2014 Sheet 49 of 60
5 4 3 2 1
 5 4 3 2 1

B+
+5VLP/ 100mA
Silergy
D
Silergy D
SY8208CQNC +5VALW/5A SY8868QMC
Adaptor Converter QFN10_2X2 +1.05VS/5A
FOR SYSTEM Switch Mode
EC_ON EN PGOOD ALW_PWRGD
PAGE 39 FOR VDDR
SUSP# EN PGOOD

+3VLP/ 100mA
Silergy
SY8206BQNC ANPEC
Converter +3VALW/4A

FOR SYSTEM APL5930KAI-TRG_SO8 +1.5VSP/1A

EC_ON EN PGOOD ALW_PWRGD
PAGE 39 LDO
FOR VDDR
SUSP# EN PGOOD

TI +1.35V/12A
TPS51716RUKR
SYSON S5 WQFN20_3X3 Silergy
SUSP# S3 +0.675VS/2A
C
TI Switch Mode SY8032ABC C

FOR DDR PGOOD SOT23-6 +1.05VSP_VGA/2A

BQ24737RGRR Switch Mode
Battery Charger FOR VDDR
EN PGOOD
Switch Mode
PAGE 46 Onsemi
CPU Core/14A/32A
NCP81101MNTXG
QFN28_4X4
Switch Mode
VR_ON
SMBus EN FOR CPU Core PGOOD VGATE
PGOOD_NB

Battery Onsemi
B
Li-ion NCP81172MNTWG B

4S1P/41WH QFN24_4X4 +VGA_CORE/31A

VIDs
Switch Mode
NVDD_PWR_EN EN FOR GPU VDDC PGOOD VGA_PWRGD

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/06/28 Deciphered Date 2015/06/28 Power Diagram

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BILG1/AILG1/AILZ1
Date: Wednesday, July 16, 2014 Sheet 50 of 60
5 4 3 2 1
 5 4 3 2 1

@
JUMP_43X79 +3VL
PJ307 VCCRTC
1 2
1 2 VIN

2
RTC_VCC PD703
JDCIN1 PF101 PJ318 RB751V-40_SOD323-2
1 APDIN 1 2 APDIN1 2 1
1 2 2 1

1
2 3 7A_24VDC_429007.WRML @ JUMP_43X118
3

470P_0402_50V7K

470P_0402_50V7K
4
4

1000P_0402_50V7K

1000P_0402_50V7K
5 JRTC1 PR9400
5 ADAPTER_ID 44,53 PD704
560_0603_5% @

1
PC101

PC102

PC103

PC104
D ACES_50299-00501-003 2 1 1 2 BAT_D 2 1 D
ME@

2
change to 560 ohm RB751V-40_SOD323-2
EMC_NS@ EMC_NS@ FDK_ML1220-TT28

@
PR370
0_0402_5%
2 1

53 737_ACP 737_ACN 53

@
PC1257 +1.05VS +1.05VS
2 1
C C

1
0.1U_0402_25V6 PC1256

1
+5VALW 0.1U_0402_25V6 PR9405 PR9406
PC1258 @ 10K_0402_5% 10K_0402_5% PR368

1
2 1 @ 5,44,52 H_PROCHOT# @ 0_0402_5%
PU1208 2 1 H_PROCHOT#

2
2

0.1U_0402_25V6 10 9 2 @ 1

2
PR367 @ CSN PROCHOT# PR369 0_0402_5% @
@ 0_0402_5% 1 8
CSP RESET PR9409
2 7 1 2
+3VALW
1

PR9403 VCC OVSET PR9410 +3VALW

1
1 2 3 6 1 2 10K_0402_1%
+3VALW ILIM UVSET
2

PC1259 PC1260 @

GND

1
0.1U_0402_25V6 35.7K_0402_1% 2 1 4 5 15K_0402_1% @ PR9413 set OVP
@ @ EN TMER 10K_0402_1%
1

2
0.1U_0402_25V6 PR9411 @

11

2
1

1
@ @ 10K_0402_1%
1

PR9412 RT9553AGQW_WDFN10_3X3

2
PR9404 10K_0402_5% PR9407 @
PR9417 10K_0402_1% @ 124K_0402_1% UVP 12V

1
30K_0402_1% @ @
2

2
375K for 15uS
2

+3VALW 124K for 5uS

1

PQ204 @ D
2
44 EC_ADAPTER G

2N7002KW_SOT323-3 S 45W current limit 2.8A

3

65W current limit 3.6A

@
B B

New solution need verify in SDV

This solution will reverse in next phase

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/06/28 Deciphered Date 2015/06/28 DCIN / RTC

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BILG1/AILG1/AILZ1
Date: Wednesday, July 16, 2014 Sheet 51 of 60
5 4 3 2 1
 5 4 3 2 1

VMB2
VMB EMC@ For KB930 --> Keep PU1 circuit
JBATT1 PF201 PL201 PH201 under CPU botten side : (Vth = 0.825V)
1 8A_24V_F1206HI8000V024T HCB2012KF-121T50_0805
1 2 1 2 1 2 CPU thermal protection at 92+-3 degree C
2 3 EC_SMCA
BATT+ For KB9012 (Red square) --> Remove PU201 circuit, but keep PR206
3 4 EC_SMDA PL202 Recovery at 56 +-3 degree C PH201, PR205,PR211,PQ201,PR208,PR212
4 5 HCB2012KF-121T50_0805
5 6 1 2
6

1
7

1
7 8 PC201 EMC@ PC202

100_0402_1%

100_0402_1%
GND1 9 1000P_0402_50V7K 0.01U_0402_25V7K

PR201

PR202

2
GND2 EMC@
EMC@ +5VLP
SUYIN_200082GR007G232ZR +3VL

2
ME@
44,53 ADP_I

2
D D
PC203

1
0.1U_0603_25V7-M PR205
@ 4.42K_0402_1% PR206 PR207

1
@ 13.7K_0402_1% 21.5K_0402_1%
+3VS @ @

1
PU201

2
1 8 NTC_V_1
EC_SMB_CK1 44,53 VCC TMSNS1

2
2 7 OTP_N_002 2 1
GND RHYST1
EC_SMB_DA1 44,53

1
PR208 3 6 Turbo_V_1 PR209
5,44,51 H_PROCHOT# 100K_0402_1% OT1 TMSNS2
PR203 10K_0402_1% PH201
1 2 +3VALW @ 4 5 ADP_OCP_2 1 2 @

1
100K_0402_1% @ OT2 RHYST2 100K_0402_1%_TSM0B104F4251RZ

2
D G718TM1U_SOT23-8 PR210

0_0402_5%

10K_0402_1%

2
PQ201 2ADP_OCP_1 57.6K_0402_1% PR213

PR211

PR212
G

OTP_N_003
PR204 2N7002KW_SOT323-3 @ 0_0402_5%
BATT_TEMP_IN 1 2
10K_0402_5%
BATT_TEMP 44,53 A/D S
@

1
@ @
@ PR214
EC_SMCA 1 2
MAINPWON 44
1

@
PD306 0_0402_5%
1

Turbo_V

44

44
NTC_V
EC_SMDA PR215
1 2
44 PROCHOT#
2

0_0402_5% @
2

AZ5215-01F_DFN1006P2E2
+3VALW

+3VALW +5VALW +5VALW

PR109 @

2
PD305 0_0402_5%

2
C AZC199-02S.R7G_SOT23-3 PR105 @ 2 1 H_PROCHOT# C
@ 10K_0402_1% PR108 @ PR110 @
VMB2

UVP_1
221K_0402_1% 430K_0402_1%
1

1
Reverse PD305 For EMI request @

499K_0402_1%
1

3
PR106 @ D PQ101B @
1 2 5 2N7002KDWH_SOT363-6

PR103
G
1.78M_0402_1%
S

4
8

2N7002KDWH_SOT363-6
12.5V PU202B PQ101A @
20131114

6
1 PR9416 2@ 5 D @

1
+_2 7 2 D
Delete JBATT2 @ 20K_0402_1% 6 O2 G 2 PQ205

180K_0402_1%
1
-_2

G
@ G 2N7002KW_SOT323-3

1
PC107 @ @ AS393MTR-G1_SO8 S

PR114

430K_0402_1%
220P_0402_50V7K

1
S

PR116
0.1U_0402_25V6

3
1
PC1268
2

2
1 2
VIN
PR353

1
1M_0402_5%

1M_0402_5%
+5VALW

PR352
+3VALW +3VALW @
@

VMB2

2
1

PC207
100K_0402_1%
2

100K_0402_1%

0.01U_0402_25V7K
PR221

PR223
2

PR228
1

B B
PR226 10M_0402_5%
1

280K_0402_1% 1 2
BATT_OUT 53
PR222
10K_0402_1% @ PR366
8

1 2 PU202A 1 2
2

3 D PQ996B 0_0603_5%
P

+_1 1 5 2N7002KDWH_SOT363-6
2 O1 G +VSBP
1

-_1
G

PQ202
1

PC108 PR224 AS393MTR-G1_SO8 S TP0610K-T1-E3_SOT23-3

4

0.1U_0402_25V6 49.9K_0402_1% PJ201

+3VALW JUMP_43X39
2

@ B+ 3 1 1 2
2

1 2 +20VSB

0.22U_0603_25V7K
2

1
100K_0402_1%

PR225 @

100K_0402_1%

2
100K_0402_1%

PR216

PC204
PR227

1 2 +3VL PC205
2

0.1U_0603_25V7-M

1
1

2
2N7002KDWH_SOT363-6

PR230 PR229 PQ996A @

6

100K_0402_1% 10K_0402_1% D PR217 @ @

1 2 2 1
VSBP_2 2 VSBP_3
1

44 BATT_LEN# G @
22K_0402_1%
S
1

@
@ PR219

1
0_0402_5% PQ203 D
1 2 VSBP_1 2
54 ALW_PWRGD G
1

S 2N7002KW_SOT323-3
Use BATT_TEMP to implement BATT_OUT function,
3

PR220 PC206
1 2 1U_0402_6.3V6K
New solution need verify in SDV,maybe can reverse in next phase 44,46 PCH_PWR_EN
2

1K_0402_1% @ @
A A
@

Security Classification LC Future Center Secret Data Title

Issued Date 2014/06/28 Deciphered Date 2015/06/28 BATTERY CONN/OTP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BILG1/AILG1/AILZ1
Date: Wednesday, July 16, 2014 Sheet 52 of 60

5 4 3 2 1
 5 4 3 2 1

B+ Charge Option() bit[8]=1

P2 P3
PQ301 PQ302
AO4407AL_SO8 SI4483ADY-T1-GE3_SO8 PR301
8 1 1 8 0.01_1206_1% PJ301
7 2 2 7 JUMP_43X118
6 3 3 6 1 4 1 2 PQ303
VIN 5 5 1 2 AO4407AL_SO8 BATT+
2 3 1 8

0.1U_0603_25V7-M
@ 2 7

2
3 6

PC109
PC301 PC302 PC303 5

2200P_0402_50V7K
4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
D D
PQ304 1 2 10U_0805_25V6K 10U_0805_25V6K

1
1

2
@ @

PC304

PC305

PC306

PC307
0.1U_0603_25V7-M

4
1
PR302 LTA044EUBFS8TL_UMT3F-3 100P_0402_50V8J DISCHG_G
3

2
200K_0402_5% PR303

1
200K_0402_1%

PC308
EMC_NS@ PR304
2

1
2 1 2 VIN

2
1P2_G2

47K_0402_1%

2ACOFF-1
2
51 737_ACP 51 737_ACN EMC_NS@

1SS355_SOD323-2
PR305

DISCHG_G-1
10K_0402_1%
1

2
PD301
P2-1 PR306

1
2 200K_0402_1%

1
PQ305
LTC015EUBFS8TL_UMT3F-3 PR356

1
20K_0402_1% PC310 PC311 PQ308B
P2_G1

P2 2 1 2 1 2N7002KDWH_SOT363-6
3

3
D PD302
2

0.1U_0603_25V7-M 0.1U_0603_25V7-M 5PACIN_N 1 2 PACIN_P

2N7002KDWH_SOT363-6

G
6

PQ307A D PR308 PC312

1SS355_SOD323-2
6

2 PR307 D PQ990A 2 1 2 1 BQ24737_VDD S

4
G 68K_0402_1% 2 BATT_OUT 52 10_1206_5%
G PC314 0.1U_0603_25V7-M PC315

6
S 1U_0603_25V6M 1U_0603_25V6M D

1M_0402_5%
1

1
S 2N7002KDWH_SOT363-6 2 1 737_VCC 1 2 PC313 2 PACIN

PR347
1

0.1U_0603_25V7-M G
VIN

2
P2-2

PD303 S PQ308A

1
2 RB751V-40_SOD323-2 AO4466L_SO8 2N7002KDWH_SOT363-6
2 1
3

5
6
7
8
PR309 D PQ307B PR310

20

14
2

3
PACIN 1 2 5 2N7002KDWH_SOT363-6 390K_0402_1% PQ309
G

VCC

ACN

GND
CMPOUT
ACP
PACIN_G

47K_0402_1%
1

C S PR311 PR312 PC317 C

4

1 2 737_ACDET 6 17 BST_CHG 1 2 2 1 4
59K_0402_1% ACDET BTST 2.2_0603_5%
PC316 0.047U_0603_16V7K
1 2 ACPRN 5 16
PR313 ACOK REGN

3
2
1
0.1U_0402_25V6 0_0402_5% PU301
PR314
6

PQ998A D 44,52 EC_SMB_CK1 1 2 737_SCL 9 18 DH_CHG PR316

1 2ACOFF-1 2 @ SCL HIDRV 0.01_1206_1%
44 ACOFF G BQ24737RGRR_VQFN20_3P5X3P5 PL302 BATT+
0_0402_5% 44,52 EC_SMB_DA1 PR315 1 2 737_SDA 8 19 LX_CHG 1 2 CHG 1 4
S @ SDA PHASE
1

@ 0_0402_5% 4.7UH_PCMB063T-4R7MS_5.5A_20% 2 3

5
6
7
8

1
ADP_I 7 15
1

PR349 2N7002KDWH_SOT363-6 44,52 ADP_I IOUT LODRV PQ311 PR317

CMPIN
2

1M_0402_5% 4.7_1206_5%

SRN
BM#

SRP
PC318 ILIM 21 AO4466L_SO8

10U_0805_25V6K

10U_0805_25V6K
PAD EMC_NS@
100P_0402_50V8J
1

1
DL_CHG 4
2

11

10

SRN_1 12

SRP_1 13

PC319

PC320
16251_SN

2
BM#

PR318 @

3
2
1
3

PQ990B D 10K_0402_5% PC321

BATT_OUT 5 1 2 1 680P_0402_50V7K

10_0603_5%
6.8_0603_5%

+3VS
1

G EMC_NS@
PR320

2
PR321
PR319

2N7002KDWH_SOT363-6 S 2 1 737_ILIM
4

2
2

PR345 100K_0402_1% 1
316K_0402_1%

0_0402_5% PC324
2

@ 0.1U_0603_25V7-M
2

PC322 @
PR324
1

1 2 737_SRP

0.1U_0603_25V7-M
1

B B
737_SRN
2

+3VALW PC323
44,52 BATT_TEMP 0.1U_0603_25V7-M
1

+3VALW VIN

BQ24737_VDD
1

PR322
750_0603_1% PR323 @ PR327

1
1M_0402_5% 1 2
ACIN 44
PR325 PR326
2

47K_0402_1% 10K_0402_1% 10K_0402_1%

2

2
PACIN

1
PQ998B PR333
2

3
D PQ995A @ D 12K_0402_1%
PR336 2 ADAPTER_ID_ON#_G ACPRN 5
0_0402_5% G G

2
@
S 2N7002KDWH_SOT363-6 2N7002KDWH_SOT363-6 S
1

ADAPTER_ID 44,51
1

D
680P_0402_50V7K

5 ADAPTER_ID_ON# 44
1

PR328 @ G
PD304 1M_0402_5%
1
0.1U_0402_25V6

S PQ995B @
PC1267

A AZ5725-01F_DFN1006P2X A
2

4
1

2N7002KDWH_SOT363-6
PC1266
2

@ PR334
0_0402_5%
2

ACPRN 1 2 ACIN#
ACIN# 8,44
@

Security Classification LC Future Center Secret Data Title

Issued Date 2014/06/28 Deciphered Date 2015/06/28 CHARGER

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BILG1/AILG1/AILZ1
Date: Wednesday, July 16, 2014 Sheet 53 of 60
5 4 3 2 1
 5 4 3 2 1

D D

B+ PU904
PJ302
2 1
1.5A +3V_VIN 7 2 +3V_PWRGD
2 1 EN2 PG

1M_0402_5%
0.1U_0402_25V6

10U_0805_25V6K
1

SY8206BQNC_QFN10_3X3
PC1048 +3VALW

PR335
JUMP_43X79 8 6 +3VBS 1 2

PC1046

PC1047
@ IN BS
4A

2
0.1U_0603_25V7-M PL303 PJ303

2
9 10 +3VLX 1 2 +3VALW_P 2 1
GND LX 2.2UH_PCMB063T-2R2MS_8A_20% 2 1

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
PR337 EMC@ 3V_GND

1
1 2 +3VALW_EN 1 4 +3VALW_P JUMP_43X79
44 EC_ON EN1 OUT PR338 @

PC1049

PC1050

PC1051

PC1052
0_0402_5%
100mA +3VLP 4.7_1206_5%

2
+3VALW_FB 3 5 EMC_NS@
FB LDO

1 2
4.7U_0603_6.3V6K
1

1
@ PC1054 PR339 PC1106

PC1055
0.1U_0402_25V6 1M_0402_5% 1000P_0402_50V9-J
2

2
EMC_NS@
@ PTP1
2

PAD

3V_GND 3V_GND

PC1057
PR341
1 2 1 2

PJ1 0.01U_0402_25V7K 1K_0402_1%

1 2
+3VL
C JUMPER +3VLP change 470P to 10nf for soft start time 2ms C
PJ304
@ 2 1
2 1
3V_GND
JUMP_43X39
@

+3VALW

2
PR342
100K_0402_5%

PR343 @

1
+3V_PWRGD 1 2
ALW_PWRGD 52
B+ PU905
0_0402_5% @

PJ305 PR344
2 1
2.5A +5V_VIN 8 2 +5V_PWRGD 1 2
2 1 IN PG
10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6
1

SY8208CQNC_QFN10_3X3

PC1061 0_0402_5% @ +5VALW

PC1060

PC1059

JUMP_43X79 9 6 +5VBS 1 2
PC1058

@ GND BS
5A
2

PC1062 0.1U_0603_25V7-M PL304 PJ306

1 2+5VVCC 5 10 +5VLX 1 2 +5VALW_P 2 1
VCC LX PR351 @ 2 1

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
PR346 EMC@ 1U_0603_25V6M 0_0402_5% 3.3UH_PCMB063T-3R3MS_6.5A_20%

1
EC_ON 1 2 5V_GND +5VALW_EN 1 4 1 2+5VALW_P JUMP_43X79
EN OUT PR340 @

PC1063

PC1080

PC1090

PC1091
100mA +5VLP
B 4.7_1206_5% B
0_0402_5%

2
+5VFB 3 7 EMC_NS@
FB LDO
1 2
1M_0402_5%

4.7U_0603_6.3V6K
1

1
1

PC1107
PR348

PC1070

@ PC1069 1000P_0402_50V9-J
2

0.1U_0402_25V6 EMC_NS@
2

5V_GND

5V_GND 5V_GND

PC1072 PR350
1 2 1 2

6800P_0402_25V7-K 1K_0402_1%
PJ2
1 2

JUMPER

@ 6800pf soft start 2ms

5V_GND 47nf soft start 7ms

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/06/28 Deciphered Date 2015/06/28 PWR_3VALW/5VALW

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BILG1/AILG1/AILZ1
Date: Wednesday, July 16, 2014 Sheet 54 of 60
5 4 3 2 1
 A B C D

1 1

1
PC1102 @
0.1U_0402_10V7K

2
PR9350 0_0402_5%
+3VALW 1k for 500K @ 1 2 SUSP# 35,44,46,56,57
12k for 670K

1.35V_GND 1.35V_GND PR377 0_0402_5%

2 1
CPU_DRAMPG_CNTL 5 2A

S3_1.35V
10K_0402_1%
PJ309

PR375
PR376 0_0402_5% 1.35V_B+ 2 1

124K_0402_1%
2 1 B+

1
2 1

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6
SYSON 44

1
PR9415

PC1064
PR9414

1
S5_1.35V

PC857

PC856
1K_0402_1% JUMP_43X79

1
2 1 @

2
44 VDDQ_PGOOD

2
PC1101 0.1U_0402_10V7K EMC_NS@
@

5
20

19

18

17

16
PU1207 @

AON6414AL_DFN8-5
PGOOD

MODE

TRIP

S3

S5
21 PR380 PC1081
PAD

PQ997
0_0603_5% 0.1U_0603_25V7-M
1 15 1
BST_1.35V 2 2 1 4 PJ317
VTTSNS VBST 2
2 1
1 14A
PR381 @
2

+1.35V
2A 2
VLDOIN DRVH
14 2 1 UG_1.35V @ JUMP_43X118 2

0_0402_5%
2A

3
2
1
PL307 PJ316
22U_0805_6.3V6M

22U_0805_6.3V6M

+0.675VSP 3 13 LX_1.35V 1 2 2 1
VTT SW 2 1
+1.35V
1

1
PC1099

PC1100

TPS51716RUKR_WQFN20_3X3

1
0.47UH_PCMC063T-R47MN_17.5A_20% @ JUMP_43X118

22U_0805_6.3V6M
1

1
4 12

PC1053
@
2

VTTGND V5IN
+5VALW

5
PQ43 PR378 + PC1105

2
1
@ 4.7_1206_5% 330U_2.5V_M

VDDQSNS

AON6414AL_DFN8-5
5 11 PC1104
VTTREF DRVL 1U_0603_25V6M EMC_NS@ 2

2
REFIN
1

PGND
VREF

1.35V_SN
GND
+VTT_REFP PC1264 LG_1.35V 4
1U_0402_6.3V6K
2

10

1
DDR_VREF

3
2
1
2

1.35V_GND PC1103
2

1000P_0402_50V9-J
30K_0402_1%

PJ315
REFIN

2
PR374

2 1 PC1265 EMC_NS@
+0.675VSP +0.675VS
1

2 1 0.1U_0402_25V6 1.35V_GND

JUMP_43X79
1

@ 1.35V_GND
93.1K_0402_1%

+1.35VP
1

PR379

PC1263
Vout=1.367V
2

0.01U_0402_25V7K
Iocp min=23A
2

3 3

1.35V_GND 1.35V_GND

PJ4
1 2

JUMPER

@
1.35V_GND

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2014/06/28 Deciphered Date 2015/06/28 1.35VS/+0.675VS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BILG1/AILG1/AILZ1
Date: Wednesday, July 16, 2014 Sheet 55 of 60
A B C D
 A B C D

1 1

+5VALW

+3VALW
+1.5VSP +1.5VS

1
PC615 500mA
1U_0603_25V6M

2
2
500mA 2

PU602
PJ604 6 PJ603
2 1 5 VCNTL 3 2 1
2 1 9 VIN1 VOUT1 4 2 1
4.7U_0603_6.3V6K

VIN2 VOUT2
1

1
PR614
JUMP_43X39 1 2EN_1_5VSP 8 JUMP_43X39
PC616

35,44,46,55,57 SUSP# EN

1
@ 7 2 PR613 @

GND
2

0_0402_5% POK FB 21.5K_0402_1% PC728 PC617

1
220P_0402_50V7K 10U_0603_6.3V6M

2
PC618 APL5930KAI-TRG_SO8

1
.1U_0402_10V6-K @

1
@ PR616
100K_0402_5%

1
@
PR615

2
24K_0402_1%

2
+3VS
VFB=0.8V

3 3

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2014/06/28 Deciphered Date 2015/06/28 +1.35VS_VGA/+1.5VS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BILG1/AILG1/AILZ1
Date: Wednesday, July 16, 2014 Sheet 56 of 60
A B C D
 5 4 3 2 1

+3VS

2
PR701
10K_0402_5%

1_05VS_PG1
PU701 Sample need to be updated 5A

22U_0805_6.3V6M
@ @

22U_0805_6.3V6M

9
PJ704 PU701 PL701 PJ702 +1.05VS
2 1 1_05VS_PVIN 1 2 1_05VS_LX 1 2 2 1

PG
+5VALW

0.1U_0402_25V6
2 1 VIN LX1 2 1

1
PC1066
D D
5 0.68UH_PCMC063T-R68MN_15.5A_20%

PC702

PC701

1
JUMP_43X79 LX2 JUMP_43X79

2
6 PR703
@ LX3 4.7_1206_5%

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1

1
4 10 EMC_NS@ 1
@ PR704 EN OUT

PC703

PC704

PC705

PC706
1SNB_1_05VS 2
1 2 1_05VS_EN + PC707

2
35,44,46,55,56 SUSP# 0_0402_5% 8 7 330U_D2_2V_Y

GND
SS FB

2
PR994 2 @

47K_0402_5%
1 2

PR705
44 SUS_VCCP

3
1

1
SY8868QMC_QFN10_2X2
0_0402_5% PC709 PC711
.1U_0402_10V6-K 0.01U_0402_25V7K PC710
1

2
@ 680P_0402_50V7K

2
@ EMC_NS@

PR706
1_05VS_FB 2 1
75K_0402_1%

1
PR707
100K_0402_1%
2 1 PC712
22P_0402_50V8-J

2
VFB=0.6V
Vo=VFB*(1+PR706/PR705)
C C

+3VS

2
PR708
10K_0402_5%
@ +1.05VSP_VGA
1

open open
22 +1.05VGS_PWRGD PU702
2.5A
PJ703 PL702 PJ709
+3VALW 2 1 1.05VMP_VIN 4 3 1.05VMP_LX 1 2 2 1
+1.05VGS
2 1 IN LX 1UH_PH041H-1R0MS_3.8A_20% 2 1
JUMP_43X79 5 2 @ JUMP_43X79
22U_0805_6.3V6M

22U_0805_6.3V6M

68P_0402_50V8J
1

1
PG GND

4.7_1206_5%

1
6 1
PC713

PC714

PR710
@ FB EN @

PC715
2

2
1
B SY8032ABC_SOT23-6 B

75K_0402_1%

22U_0805_6.3V6M

22U_0805_6.3V6M
2

1
@
@ FB=0.6Volt

PR711
@
@ @ EMC_NS@

PC716

PC717
1

2
PC718

2
PD701 680P_0402_50V7K

2
1 2 @ EMC_NS@

PR172
2 1 1.05VGS_EN 1.05VMP_FB
23,58 DGPU_PWROK @ @

1
4.7K_0402_5% N15VGM@
1

1 PR714
PR713 100K_0402_1%
1M_0402_5% PC719 @
PR715 0.22U_0402_10V6K

2
2 1 OPT@ 2
2

22,58 EN_VGA 0_0402_5% N15VGM@

N15SGT@

1.05VGS_EN 1.05VGS_EN 21

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/06/28 Deciphered Date 2015/06/28 +1.05VS/+1.05VS_VGA

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BILG1/AILG1/AILZ1
Date: Wednesday, July 16, 2014 Sheet 57 of 60
5 4 3 2 1
 5 4 3 2 1

+3VGS

2
2 1
4,21 PXS_PWREN
PR9446 PR9442
0_0402_5% 10K_0402_5%
N15VGM@ @ PD705
RB751V-40_SOD323-2

1
OPT@
2 1 1 2 EN_VGA EN_VGA 22,57
D 19,21 3VGS_PWR_EN D
PR9445

1
0_0402_5% PC1303
N15SGT@ PR9443 .1U_0402_10V6-K
100K_0402_5% 2 1 OPT@

2
@
PR9444

2
10K_0402_1%
OPT@ +VGA_B+

NVVDD_PWM_VID PJ710
19 NVVDD_PWM_VID
2 1
2 1 B+
19 PSI_VGA PSI_VGA

VSSSENSE_VGA JUMP_43X79
20 VSSSENSE_VGA

10U_0805_25V6K

10U_0805_25V6K
0.1U_0603_25V7K
VCCSENSE_VGA
20 VCCSENSE_VGA @

1
PC1295

PC1298
AON6414AL_DFN8-5
NVVDD_PWM_VID

PC1255
23,57 DGPU_PWROK DGPU_PWROK

2
PQ991
4

PR9429 PC1300 EMCOPT@ OPT@ OPT@

N15S-GT use config-B 0_0603_5% 0.22U_0603_16V7K

3
2
1
2
N15V-GM use config-D 2 1BOOT1_2_VGA 1 2 PR9441 @
PR9430 OPT@ OPT@ 0_0402_5%
0_0402_5% 2 1 UGATE1_2_VGA OPT@ PL705 +VGA_CORE
B D reserve
@ 0.24UH_PCME063T-R24MS1R145_35A_20%
1 2

BOOT1_VGA
N15S-GT N15V-GM

5
10P_0402_50V8J
PQ992 OPT@

1
R1 PR9440 20 27 @

1
AON6554_DFN
PC1261
PC1262
R2 PR9434 20 7.5 2700P_0402_50V7-K @ PR9435

2
1 2 GPU_VID 4.7_1206_5%

330U_D2_2V_Y

330U_D2_2V_Y
1 1
LGATE1_VGA 4
C
R3 PR9436 2 0 EMC_NS@ C

OPT@ PC1293

OPT@ PC1297
reserve follow + +

1SNUB1_VGA 2
NV suggestion
R4 PR9437 18 6.2 PR9434 PR9440

1
2 2

PSI_VGA

EN_VGA
R5 PR9431 0 1.74 20K_0402_1% 20K_0402_1% OPT@

3
2
1
VREF 2 1 2 1VIDBUF UGATE1_VGA PR9438
C(nF) PC1277 2.7 5.6 N15SGT@ N15SGT@ 5.1K_0402_1%

1
@

PHASE1_VGA
PR9436

2
2K_0402_1% PC1296

1
PR9431 PR9437 N15SGT@ PU909 680P_0402_50V7K

2
OPT@ 0_0402_5% 18K_0402_1% EMC_NS@

HG1

BST1
VIDBUF

VID

PSI

EN
2
N15SGT@ 2 1 2 1N15SGT@ reserve for future tune
PR9447
2 1 PC1294 1
PC1277 2N15SGT@ 7 24
0.01U_0603_50V7K REFIN PH1 PC1301
OPT@1 2 2700P_0402_50V7-K VREF 8 23 4.7U_0603_6.3V6K
100_0402_5% PR9439 VREF LG1 OPT@
PR9449 2 1OPT@ FS 9 22 1 2
0_0402_5% 39K_0402_1% FS PGND
VSSSENSE_VGA OPT@2 1 VSS_SEN 10 21 PVCC_VGA 1 2
+5VS
FBRTN PVCC
PC1270 FB_VGA 11 20 PR9418
FB LG2
1

PC1269 47P_0402_50V8J PR9419 PC1271 0_0402_5% @ +VGA_B+

1000P_0402_50V7K 1 2FB1_VGA1 2 1 2 COMP_VGA 12 19

TALERT#
COMP PH2

PGOOD
PR9420 OPT@ 51_0402_1% OPT@ 10P_0402_50V8J
2

TSNS
0_0402_5% OPT@ PR9421 OPT@ PC1272

BST2
GND

VCC

HG2
VCCSENSE_VGA OPT@2 1 VCC_SEN 1 2 1 2FB2_VGA1 PR9422 2

10U_0805_25V6K

10U_0805_25V6K
OPT@ OPT@

0.1U_0603_25V7K
AON6414AL_DFN8-5
10K_0402_1% 100P_0402_50V8J 82K_0402_1%OPT@

25

13

14

15

16

17

18

1
PC1275

PC1276
OPT@ NCP81172MNTWG_QFN24_4X4

PC1273
PR9448 BOOT2_VGA PR9423 @

VCC_VGA

2
OPT@ PQ993
1 2 0_0402_5%
+VGA_CORE 2 1 UGATE2_2_VGA 4
UGATE2_VGA
100_0402_5% DGPU_PWROK

OPT@
100K_0402_1%_TSM0B104F4251RZ
OPT@ PR9425
2

1
B B
PC1299 10K_0402_5% PR9424 PC1278 EMCOPT@

3
2
1
2 1 +3VS 0_0603_5% 0.22U_0603_16V7K OPT@ OPT@
PH903

.1U_0402_10V6-K @ 2 1OPT@ BOOT2_2_VGA 1 2

1

1
5.9K_0402_1%
OPT@ PR9426 OPT@ PL706 +VGA_CORE
2 1 +5VS 0.24UH_PCME063T-R24MS1R145_35A_20%
2

PR9427 OPT@ PHASE2_VGA 1 2

2.2_0402_5% OPT@

5
PQ994
VREFOPT@ 2

PC1279

1
AON6554_DFN
1U_0402_10V6K
1

OPT@ PR9428
4.7_1206_5%

330U_D2_2V_Y

330U_D2_2V_Y
1 1
LGATE2_VGA 4 EMC_NS@

OPT@
@
PC1280

PC1281
PR9432 + +

1SNUB2_VGA 2
0_0402_5% @
2 1
OPT@ 2 2

3
2
1
2 1 +3VS

PR9433 OPT@
10K_0402_5% PC1282
680P_0402_50V7K

2
EMC_NS@

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1

1
PC1287

PC1288

PC1289

PC1290

PC1291

PC1292
A @ @ A

2
@ @ OPT@ OPT@

Security Classification LC Future Center Secret Data Title

Issued Date 2014/06/28 Deciphered Date 2015/06/28 PWR-VGA_CORE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BILG1/AILG1/AILZ1
Date: Wednesday, July 16, 2014 Sheet 58 of 60
5 4 3 2 1
 5 4 3 2 1

CORE_GND CORE_GND

470P_0402_50V7K
1

1
PC1157

220K_0402_5%_TSM0B224J4702RE
PR9334
27.4K_0402_1%

2
2
1 PR9337 2 B+
44 VR_IMVP_IMON
165K_0402_1%

68P_0402_50V8J
330P_0402_50V7K
1

1
75K_0402_1%

2
PR9346

PH901
PR9338

PC1159

PC1158
2 1
+5VALW 0_0402_5% 1

1
@

68U_25V_M
2

2
PJ708 +

PC989
1
D D
@ JUMP_43X79
PR9335
2

2
1 2 CPU_PH @
3A

2
140K_0603_1%

2 PR9401 1CPU_CORE
CPU_B+

1 CSCOMP

CPU_CSREF
CORE_GND
1

1
PC1065 PC100 PC99 PC98 PC113

68U_25V_M
10_0402_1%
+

CSCOMP
PR9333

PC988
10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
PR9345 16.5K_0402_1%

2
CSSUM

2
2 @ 1 CORE_GND EMC@

0.1U_0402_25V6
0_0402_5% PR9340 PC1171 2

2
102K_0402_1% 1000P_0402_50V7K

5
PQ40

CPU_CSREF
2

AON6414AL_DFN8-5
1
PR3 PC1153 PC1181 PC1172 CORE_GND
49.9_0402_1% 330P_0402_50V7K 10P_0402_50V8J CORE_GND 2.2U_0603_6.3V6K
1 2 1 2 1 2 PR365
@ @

2
1 2 CPU_HG_R 1 2CPU_HG 4 CPU_CORE
+5VALW

1
PR9330 PC1152 @ PR2 PR1 PR9341 @ 0_0603_5%
1K_0402_1% 2200P_0402_50V7K 4.02K_0402_1% 16.2K_0402_1% 0_0402_5% PR9332 32A

21
20
19
18
17
16
15
1 2 1 2 1 2 69.8K_0402_1% PL9

3
2
1
1 2 CPU_PH 1 2

PVCC
IOUT

CSREF
CSCOMP

IMAX
ILIM

CSSUM
CORE_GND

2
PR362
0_0402_5% PC1156 0.22UH_SPS-06CZ-R22M-V1_23A_20%

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
5

1
1 2 22 14 0.01U_0402_25V7K PQ39

1
23 ROSC VBOOT 13 TSENSE 1 2 PR617
COMP TSENSE CORE_GND

AON6554_DFN
24 12 CPU_LG 4.7_1206_5%

PC1073

PC1088

PC1089

PC1170

PC1148
PR9402 25 FB LG 11 EMC_NS@

2
1 2 26 DIFFOUT PGND 10 CPU_PH
12 CPU_VSS_SENSE

2
27 VSN SW 9 CPU_HG_R PC97 CPU_LG 4
2

0_0402_5% PC1154 28 VSP HG 8 1 PR80 2 1 2

VR_HOT#
VCC BST

VR_RDY
ENABLE

ALERT#
C 1000P_0402_50V7K 2_0603_5% @ @ @ @ C

1
VRMP
29

SCLK
0.22U_0603_25V7K PC621

SDIO
1

GND 680P_0402_50V7K
10 CPU_VCC_SENSE

3
2
1
PR9145 EMC_NS@

2
PC1254 @ 1 2 PU908
+5VALW

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1
2
3
4
5
6
7
1 2 NCP81101MNTXG_QFN28_4X4
1

1
2.2_0603_5% PC242 CORE_GND
560P_0402_50V7-K 1U_0603_25V6M

PC1164

PC1149

PC1177

PC1139

PC1160

PC1116
PR9343 2 @ 1 PR9331
44 EC_VR_ON
2

2
0_0402_5% 1 2
CPU_B+
PR9146
2 1 CORE_GND 1K_0402_1% @
10 CPU_VR_ON
0_0402_5% 1 @ @
1

PC1155
PC620 0.01U_0402_25V7K
2

+1.05VS .1U_0402_10V6-K
2

@ +3VS

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
2

CORE_GND CORE_GND 1

1
PR9265
499_0402_1% PR47

PC1167

PC1162

PC1165

PC1163

PC1174

PC1173
10K_0402_5%

2
1

44 VR_HOT# @
VR_CPU_PWROK 10,44
10 CPU_SVID_DAT

100K_0402_1%_TSM0B104F4251RZ
PR9147 @
10 CPU_SVID_ALERT#
0_0402_5%
TSENSE 2 1
10 CPU_SVID_CLK CORE_GND
1

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1

1
PR9098 PR31 + PC708

1
PR60 PR9339 220U_D2_2.5VY_R6M

PC1176

PC1178

PC1180
.1U_0402_10V6-K
1

75_0402_1% 130_0402_1% 59K_0402_1%

PH902

2
+1.05VS 54.9_0402_1% PC626 @ 2 3
PC622
2

@ 10U_0603_6.3V6M
2

B B
2

2
@

PJ3
1 2

JUMPER

@
CORE_GND

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/06/28 Deciphered Date 2015/06/28 PWR_CPU Core

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BILG1/AILG1/AILZ1
Date: Wednesday, July 16, 2014 Sheet 59 of 60
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 5 4 3 2 1

HW PIR (Product Improve Record)

BALG1/AIGL1/AILZ1 SCHEMATIC CHANGE LIST
REVISION CHANGE: 0.4
GERBER-OUT DATE: 2014/06/26

NO DATE PAGE MODIFICATION LIST PURPOSE

D --------------------------------------------------------------------------------------------------------------------- D

01) 06/22 21 Add virtual material CV54 0.1U Follow N15V-GM Power rise time
02) 06/22 19 Add virtual material UV1 N15V-GM Follow N15V-GM Power rise time
03) 06/22 07 Add virtual material YC1 Form SJ10000IM00 to SJ10000I300 HSW cost down
04) 06/22 03 Add BOM Structure Table list HSW cost down
05) 06/26 45 Change L15 BOM structure form EMC@ to EMC_NS@ cost down
06) 06/29 04 Add virtual material UC1 BDW Follow BDW CPU BOM structure
07) 06/29 04-13 Change UC1 BOM structure is HSW@ Follow HSW CPU BOM structure
08) 06/29 46 Change R159/R162 BOM structure is @ cost down
09) 07/09 21 Change RV59/RV64/RV72/QV10/QV13/QV20 BOM structure From OPT@ to @ cost down
10) 07/09 04 Change RC8 to PCB Short cost down
11) 07/11 43 Change RA11 Pull high form +3VL to +3VS follow G15
12) 07/11 07 Change QC3A/QC3B BOM structure is @ Cost down
13) 07/11 39 Change R176/R177 BOM structure Form UMA@ to PCB Short Cost down
14) 07/17 45 Change D17 BOM structure Form EMC@ to EMC_NS@ Cost down
15) 07/17 45 Change QC3 BOM structure is @ Cost down

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/06/28 Deciphered Date 2015/06/28 HW-PIR

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BILG1/AILG1/AILZ1
Date: Friday, July 18, 2014 Sheet 60 of 60

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