5M68HC05M

HC05M68HC
MC68HC705P6A/D
REV 2
68HC05M6
MC68HC705P6A

Advance Information

HCMOS
Microcontroller Unit
blank
 MC68HC705P6A
Advance Information

Motorola reserves the right to make changes without further notice to any products
herein. Motorola makes no warranty, representation or guarantee regarding the
suitability of its products for any particular purpose, nor does Motorola assume any
liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation consequential or incidental
damages. "Typical" parameters which may be provided in Motorola data sheets and/or
specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including "Typicals" must be vali1dated for
each customer application by customer’s technical experts. Motorola does not convey
any license under its patent rights nor the rights of others. Motorola products are not
designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life,
or for any other application in which the failure of the Motorola product could create a
situation where personal injury or death may occur. Should Buyer purchase or use
Motorola products for any such unintended or unauthorized application, Buyer shall
indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and
distributors harmless against all claims, costs, damages, and expenses, and
reasonable attorney fees arising out of, directly or indirectly, any claim of personal
injury or death associated with such unintended or unauthorized use, even if such claim
alleges that Motorola was negligent regarding the design or manufacture of the part.
Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

Motorola and are registered trademarks of Motorola, Inc.

DigitalDNA is a trademark of Motorola, Inc. © Motorola, Inc., 2001

MC68HC705P6A — Rev. 2.0 Advance Information

MOTOROLA 3
Advance Information

To provide the most up-to-date information, the revision of our

documents on the World Wide Web will be the most current. Your printed
copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://www.motorola.com/semiconductors/

The following revision history table summarizes changes contained in

this document. For your convenience, the page number designators
have been linked to the appropriate location.

Revision History
Revision Page
Date Description
Level Number(s)

Format update to current publication standards N/A

November,
2.0 Figure 11-1. Mask Option Register (MOR) — Definition of
2001 92
bit 6 corrected.

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4 MOTOROLA
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List of Sections

Section 1. General Description . . . . . . . . . . . . . . . . . . . . 19

Section 2. Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Section 3. Operating Modes. . . . . . . . . . . . . . . . . . . . . . . 35

Section 4. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Section 5. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Section 6. Input/Output Ports . . . . . . . . . . . . . . . . . . . . . 51

Section 7. Serial Input/Output Port (SIOP) . . . . . . . . . . . 59

Section 8. Capture/Compare Timer . . . . . . . . . . . . . . . . . 65

Section 9. Analog Subsystem . . . . . . . . . . . . . . . . . . . . . 77

Section 10. EPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Section 11. Mask Option Register (MOR) . . . . . . . . . . . . 91

Section 12. Central Processor Unit (CPU) Core . . . . . . . 95

Section 13. Instruction Set . . . . . . . . . . . . . . . . . . . . . . . 101

Section 14. Electrical Specifications. . . . . . . . . . . . . . . 117

Section 15. Mechanical Specifications . . . . . . . . . . . . . 125

Section 16. Ordering Information . . . . . . . . . . . . . . . . . 127

MC68HC705P6A — Rev. 2.0 Advance Information

MOTOROLA List of Sections 5

List of Sections

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Table of Contents

Section 1. General Description

1.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

1.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

1.4 Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

1.4.1 VDD and VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.4.2 OSC1 and OSC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
1.4.2.1 Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.4.2.2 Ceramic Resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.4.2.3 External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
1.4.3 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.4.4 PA0–PA7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.4.5 PB5/SDO, PB6/SDI, and PB7/SCK . . . . . . . . . . . . . . . . . . .24
1.4.6 PC0-PC2, PC3/AD3, PC4/AD2, PC5/AD1, PC6/AD0,
and PC7/VREFH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.4.7 PD5 and PD7/TCAP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.4.8 TCMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.4.9 IRQ/VPP (Maskable Interrupt Request) . . . . . . . . . . . . . . . . 25

Section 2. Memory
2.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2.3 User Mode Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2.4 Bootloader Mode Memory Map . . . . . . . . . . . . . . . . . . . . . . . .28

2.5 Input/Output and Control Registers . . . . . . . . . . . . . . . . . . . . . 29

2.6 RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

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2.7 EPROM/ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

2.8 Mask Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

2.9 Computer Operating Properly (COP) Clear Register . . . . . . . . 34

Section 3. Operating Modes

3.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.3 User Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.4 Bootloader Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.5.1 STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
3.5.1.1 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.5.1.2 Halt Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.5.2 WAIT Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

3.6 COP Watchdog Timer Considerations . . . . . . . . . . . . . . . . . . .40

Section 4. Resets
4.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

4.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

4.3 External Reset (RESET). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

4.4 Internal Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

4.4.1 Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.4.2 Computer Operating Properly (COP) Reset . . . . . . . . . . . . . 42

Section 5. Interrupts
5.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

5.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

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5.3 Interrupt Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

5.3.1 Reset Interrupt Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.3.2 Software Interrupt (SWI). . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.3.3 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.3.3.1 External Interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.3.3.2 Input Capture Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.3.3.3 Output Compare Interrupt . . . . . . . . . . . . . . . . . . . . . . . .49
5.3.3.4 Timer Overflow Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . 49

Section 6. Input/Output Ports

6.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

6.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

6.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

6.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

6.5 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

6.6 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

6.7 I/O Port Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Section 7. Serial Input/Output Port (SIOP)

7.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

7.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

7.3 SIOP Signal Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

7.3.1 Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
7.3.2 Serial Data Input (SDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
7.3.3 Serial Data Output (SDO). . . . . . . . . . . . . . . . . . . . . . . . . . . 61

7.4 SIOP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

7.4.1 SIOP Control Register (SCR) . . . . . . . . . . . . . . . . . . . . . . . .62
7.4.2 SIOP Status Register (SSR) . . . . . . . . . . . . . . . . . . . . . . . .63
7.4.3 SIOP Data Register (SDR). . . . . . . . . . . . . . . . . . . . . . . . . . 64

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Section 8. Capture/Compare Timer

8.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
8.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
8.3 Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
8.3.1 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
8.3.2 Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
8.4 Timer I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
8.4.1 Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
8.4.2 Timer Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
8.4.3 Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
8.4.4 Alternate Timer Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 72
8.4.5 Input Capture Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
8.4.6 Output Compare Registers. . . . . . . . . . . . . . . . . . . . . . . . . . 74
8.5 Timer During Wait/Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 75
8.6 Timer During Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Section 9. Analog Subsystem

9.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
9.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
9.3 Analog Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
9.3.1 Ratiometric Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
9.3.2 Reference Voltage (VREFH) . . . . . . . . . . . . . . . . . . . . . . . . . 78
9.3.3 Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
9.4 Conversion Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
9.5 Digital Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
9.5.1 Conversion Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
9.5.2 Internal versus External Oscillator . . . . . . . . . . . . . . . . . . . . 79
9.5.3 Multi-Channel Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
9.6 A/D Status and Control Register (ADSC) . . . . . . . . . . . . . . . . . 80
9.7 A/D Conversion Data Register (ADC). . . . . . . . . . . . . . . . . . . .82
9.8 A/D Subsystem Operation during Halt/Wait Modes . . . . . . . . . 82
9.9 A/D Subsystem Operation during Stop Mode. . . . . . . . . . . . . . 82

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Section 10. EPROM

10.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

10.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

10.3 EPROM Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

10.4 EPROM Programming Sequence. . . . . . . . . . . . . . . . . . . . . . . 84

10.5 EPROM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

10.6 EPROM Programming Register (EPROG) . . . . . . . . . . . . . . . . 84

10.7 EPROM Bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

10.8 Programming from an External Memory Device. . . . . . . . . . . . 87

Section 11. Mask Option Register (MOR)

11.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

11.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

11.3 Mask Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

11.4 MOR Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

Section 12. Central Processor Unit (CPU) Core

12.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

12.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

12.3 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
12.3.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
12.3.2 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
12.3.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
12.3.4 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
12.3.5 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

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Section 13. Instruction Set

13.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

13.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

13.3 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

13.3.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
13.3.2 Immediate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
13.3.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
13.3.4 Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
13.3.5 Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
13.3.6 Indexed, 8-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
13.3.7 Indexed,16-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
13.3.8 Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

13.4 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

13.4.1 Register/Memory Instructions. . . . . . . . . . . . . . . . . . . . . . .105
13.4.2 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . 106
13.4.3 Jump/Branch Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . 107
13.4.4 Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . .109
13.4.5 Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

13.5 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

13.6 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Section 14. Electrical Specifications

14.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

14.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

14.3 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

14.4 Operating Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . 118

14.5 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

14.6 5.0-Volt DC Electrical Characteristics. . . . . . . . . . . . . . . . . . .119

14.7 3.3-Volt DC Electrical Charactertistics . . . . . . . . . . . . . . . . . .120

14.8 A/D Converter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 121

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14.9 EPROM Programming Characteristics . . . . . . . . . . . . . . . . . . 122

14.10 SIOP Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

14.11 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Section 15. Mechanical Specifications

15.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

15.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

15.3 Plastic Dual In-Line Package (Case 710) . . . . . . . . . . . . . . . . 126

15.4 Small Outline Integrated Circuit Package (Case 751F) . . . . . 126

Section 16. Ordering Information

16.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

16.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

16.3 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127

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Table of Contents

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Advance Information — MC68HC705P6A

List of Figures

Figure Title Page

1-1 MC68HC705P6A Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 21

1-2 Oscillator Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2-1 MC68HC705P6A User Mode Memory Map . . . . . . . . . . . . . . . 28

2-2 MC68HC705P6A I/O and Control
Registers Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2-3 I/O and Control Register Summary. . . . . . . . . . . . . . . . . . . . . . 30
2-4 Mask Option Register (MOR) . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2-5 COP Watchdog Timer Location . . . . . . . . . . . . . . . . . . . . . . . .34

3-1 User Mode Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3-2 STOP/WAIT Flowcharts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

4-1 Reset Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

4-2 Unused Vector and COP Watchdog Timer. . . . . . . . . . . . . . . . 43

5-1 Interrupt Processing Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . 47

6-1 Port A I/O and Interrupt Circuitry . . . . . . . . . . . . . . . . . . . . . . . 52

6-2 Port B I/O Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6-3 Port C I/O Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6-4 Port D I/O Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

7-1 SIOP Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

7-2 SIOP Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
7-3 SIOP Control Register (SCR) . . . . . . . . . . . . . . . . . . . . . . . . . . 62
7-4 SIOP Status Register (SSR). . . . . . . . . . . . . . . . . . . . . . . . . . . 63
7-5 Serial Port Data Register (SDR) . . . . . . . . . . . . . . . . . . . . . . . .64

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List of Figures

Figure Title Page

8-1 Capture/Compare Timer Block Diagram. . . . . . . . . . . . . . . . . . 66

8-2 Timer Control Register (TCR). . . . . . . . . . . . . . . . . . . . . . . . . . 68
8-3 Timer Status Register (TSR) . . . . . . . . . . . . . . . . . . . . . . . . . . 70
8-4 Timer Registers (TRH and TRL). . . . . . . . . . . . . . . . . . . . . . . .71
8-5 Alternate Timer Registers (ATRH and ATRL). . . . . . . . . . . . . . 72
8-6 Input Capture Registers (ICRH and ICRL) . . . . . . . . . . . . . . . . 73
8-7 Output Compare Registers (OCRH and OCRL) . . . . . . . . . . . . 74

9-1 A/D Status and Control Register (ADSC) . . . . . . . . . . . . . . . . . 80

9-2 A/D Conversion Value Data Register (ADC) . . . . . . . . . . . . . . 82

10-1 EPROM Programming Register (EPROG) . . . . . . . . . . . . . . . . 85

10-2 MC68HC705P6A EPROM Programming Flowchart. . . . . . . . . 89
10-3 MC68HC705P6A EPROM Programming
Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

11-1 Mask Option Register (MOR) . . . . . . . . . . . . . . . . . . . . . . . . . . 92

12-1 MC68HC05 Programming Model . . . . . . . . . . . . . . . . . . . . . . . 96

14-1 SIOP Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

14-2 Power-On Reset and External Reset Timing Diagram . . . . . . 124

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Advance Information — MC68HC705P6A

List of Tables

Table Title Page

3-1 Operating Mode Conditions After Reset . . . . . . . . . . . . . . . . . . 35

5-1 Vector Addresses for Interrupts and Reset. . . . . . . . . . . . . . . . 46

6-1 Port A I/O Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

6-2 Port B I/O Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6-3 Port C I/O Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6-4 Port D I/O Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

9-1 A/D Multiplexer Input Channel Assignments . . . . . . . . . . . . . . 81

10-1 EPROM Programming Routine. . . . . . . . . . . . . . . . . . . . . . . . . 86

10-2 Bootloader Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

11-1 SIOP Clock Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

11-2 MOR Programming Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

13-1 Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . . . . . 105

13-2 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . . .106
13-3 Jump and Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . 108
13-4 Bit Manipulation Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . 109
13-5 Control Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
13-6 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
13-7 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

MC68HC705P6A — Rev. 2.0 Advance Information

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List of Tables

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Advance Information — MC68HC705P6A

Section 1. General Description

1.1 Contents
1.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

1.4 Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

1.4.1 VDD and VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.4.2 OSC1 and OSC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
1.4.2.1 Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.4.2.2 Ceramic Resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.4.2.3 External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
1.4.3 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.4.4 PA0–PA7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.4.5 PB5/SDO, PB6/SDI, and PB7/SCK . . . . . . . . . . . . . . . . . . .24
1.4.6 PC0-PC2, PC3/AD3, PC4/AD2, PC5/AD1, PC6/AD0,
and PC7/VREFH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.4.7 PD5 and PD7/TCAP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.4.8 TCMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.4.9 IRQ/VPP (Maskable Interrupt Request) . . . . . . . . . . . . . . . . 25

1.2 Introduction
The MC68HC705P6A is an EPROM version of the MC68HC05P6
microcontroller. It is a low-cost combination of an M68HC05 Family
microprocessor with a 4-channel, 8-bit analog-to-digital (A/D) converter,
a 16-bit timer with output compare and input capture, a serial
communications port (SIOP), and a computer operating properly (COP)
watchdog timer. The M68HC05 CPU core contains 176 bytes of RAM,
4672 bytes of user EPROM, 239 bytes of bootloader ROM, and 21
input/output (I/O) pins (20 bidirectional, 1 input-only). This device is

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MOTOROLA General Description 19

General Description

available in either a 28-pin plastic dual in-line (PDIP) or a 28-pin small

outline integrated circuit (SOIC) package.

A functional block diagram of the MC68HC705P6A is shown in

Figure 1-1.

1.3 Features
Features of the MC68HC705P6A include:
• Low cost
• M68HC05 core
• 28-pin SOIC, PDIP, or windowed DIP package
• 4672 bytes of user EPROM (including 48 bytes of page zero
EPROM and 16 bytes of user vectors)
• 239 bytes of bootloader ROM
• 176 bytes of on-chip RAM
• 4-channel 8-bit A/D converter
• SIOP serial communications port
• 16-bit timer with output compare and input capture
• 20 bidirectional I/O lines and 1 input-only line
• PC0 and PC1 high-current outputs
• Single-chip, bootloader, and test modes
• Power-saving stop, halt, and wait modes
• Static EPROM mask option register (MOR) selectable options:
– COP watchdog timer enable or disable
– Edge-sensitive or edge- and level-sensitive external interrupt
– SIOP most significant bit (MSB) or least significant bit (LSB)
first
– SIOP clock rates: OSC divided by 8, 16, 32, or 64
– Stop instruction mode, STOP or HALT
– EPROM security external lockout
– Programmable keyscan (pullups/interrupts) on PA0–PA7

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 General Description
Features

INTERNAL
COP CPU CLOCK OSC 1
÷2 OSC
OSC 2

÷4 16-BIT TIMER PD7/TCAP

CPU CONTROL ALU
1 INPUT CAPTURE TCMP
RESET
M68HC05 CPU 1 OUTPUT COMPARE
PORT D LOGIC PD5
IRQ/VPP
ACCUM
CPU REGISTERS PC7/VREFH

A/ D CONVERTER
INDEX REG

DATA DIRECTION REGISTER

PC6/AD0

MUX
0 0 0 0 0 0 0 0 1 1 STK PNTR PC5/AD1

PORT C
PC4/AD2
PROGRAM COUNTER
PC3/AD3
COND CODE REG 1 1 1H I NZC PC2
PC1
PC0
SRAM — 176 BYTES
PA7
PA6

DATA DIRECTION REG

USER EPROM — 4672 BYTES
PA5

PORT A
PA4
BOOTLOADER ROM — 239 BYTES
PA3
PA2
PB5/SDO PORT B AND PA1
SIOP
PB6/SDI PA0
REGISTERS
PB7/SCK AND LOGIC VDD
VSS

Figure 1-1. MC68HC705P6A Block Diagram

NOTE: A line over a signal name indicates an active low signal. For example,
RESET is active high and RESET is active low.

Any reference to voltage, current, or frequency specified in the following

sections will refer to the nominal values. The exact values and their
tolerances or limits are specified in Section 14. Electrical
Specifications.

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General Description

1.4 Functional Pin Description

The following paragraphs describe the functionality of each pin on the
MC68HC705P6A package. Pins connected to subsystems described in
other chapters provide a reference to the chapter instead of a detailed
functional description.

1.4.1 VDD and VSS

Power is supplied to the MCU through VDD and VSS. VDD is connected
to a regulated +5 volt supply and VSS is connected to ground.

Very fast signal transitions occur on the MCU pins. The short rise and fall
times place very high short-duration current demands on the power
supply. To prevent noise problems, take special care to provide good
power supply bypassing at the MCU. Use bypass capacitors with good
high-frequency characteristics and position them as close to the MCU as
possible. Bypassing requirements vary, depending on how heavily the
MCU pins are loaded.

1.4.2 OSC1 and OSC2

The OSC1 and OSC2 pins are the control connections for the on-chip
oscillator. The OSC1 and OSC2 pins can accept the following:
1. A crystal as shown in Figure 1-2(a)
2. A ceramic resonator as shown in Figure 1-2(a)
3. An external clock signal as shown in Figure 1-2(b)

The frequency, fosc, of the oscillator or external clock source is divided

by two to produce the internal bus clock operating frequency, fop. The
oscillator cannot be turned off by software unless the MOR bit, SWAIT,
is clear when a STOP instruction is executed.

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 General Description
Functional Pin Description

To VDD (or STOP) MCU To VDD (or STOP) MCU

OSC1 OSC2 OSC1 OSC2

4.7 MΩ
UNCONNECTED

EXTERNAL CLOCK

37 pF 37 pF

(a) Crystal or Ceramic (b) External Clock Source

Resonator Connections Connections

Figure 1-2. Oscillator Connections

1.4.2.1 Crystal

The circuit in Figure 1-2(a) shows a typical oscillator circuit for an

AT-cut, parallel resonant crystal. Follow the crystal manufacturer’s
recommendations, as the crystal parameters determine the external
component values required to provide maximum stability and reliable
startup. The load capacitance values used in the oscillator circuit design
should include all stray capacitances. Mount the crystal and components
as close as possible to the pins for startup stabilization and to minimize
output distortion.

1.4.2.2 Ceramic Resonator

In cost-sensitive applications, use a ceramic resonator in place of a

crystal. Use the circuit in Figure 1-2(a) for a ceramic resonator and
follow the resonator manufacturer’s recommendations, as the resonator
parameters determine the external component values required for
maximum stability and reliable starting. The load capacitance values
used in the oscillator circuit design should include all stray capacitances.
Mount the resonator and components as close as possible to the pins for
startup stabilization and to minimize output distortion.

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General Description

1.4.2.3 External Clock

An external clock from another CMOS-compatible device can be

connected to the OSC1 input, with the OSC2 input not connected, as
shown in Figure 1-2(b).

1.4.3 RESET

Driving this input low will reset the MCU to a known startup state. The
RESET pin contains an internal Schmitt trigger to improve its noise
immunity. Refer to Section 4. Resets.

1.4.4 PA0–PA7

These eight I/O pins comprise port A. The state of any pin is software
programmable and all port A lines are configured as inputs during
power-on or reset. Port A has mask-option register enabled interrupt
capability with internal pullup devices selectable for any pin. Refer to
Section 6. Input/Output Ports.

1.4.5 PB5/SDO, PB6/SDI, and PB7/SCK

These three I/O pins comprise port B and are shared with the SIOP
communications subsystem. The state of any pin is software
programmable, and all port B lines are configured as inputs during
power-on or reset. Refer to Section 6. Input/Output Ports and
Section 7. Serial Input/Output Port (SIOP).

1.4.6 PC0-PC2, PC3/AD3, PC4/AD2, PC5/AD1, PC6/AD0, and PC7/VREFH

These eight I/O pins comprise port C and are shared with the A/D
converter subsystem. The state of any pin is software programmable
and all port C lines are configured as inputs during power-on or reset.
Refer to Section 6. Input/Output Ports and Section 9. Analog
Subsystem.

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 General Description
Functional Pin Description

1.4.7 PD5 and PD7/TCAP

These two I/O pins comprise port D and one of them is shared with the
16-bit timer subsystem. The state of PD5 is software programmable and
is configured as an input during power-on or reset. PD7 is always an
input. It may be read at any time, regardless of which mode of operation
the 16-bit timer is in. Refer to Section 6. Input/Output Ports and
Section 8. Capture/Compare Timer.

1.4.8 TCMP

This pin is the output from the 16-bit timer’s output compare function. It
is low after reset. Refer to Section 8. Capture/Compare Timer.

1.4.9 IRQ/VPP (Maskable Interrupt Request)

This input pin drives the asynchronous interrupt function of the MCU in
user mode and provides the VPP programming voltage in bootloader
mode. The MCU will complete the current instruction being executed
before it responds to the IRQ interrupt request. When the IRQ/VPP pin is
driven low, the event is latched internally to signify an interrupt has been
requested. When the MCU completes its current instruction, the interrupt
latch is tested. If the interrupt latch is set and the interrupt mask bit (I bit)
in the condition code register is clear, the MCU will begin the interrupt
sequence.

Depending on the MOR LEVEL bit, the IRQ/VPP pin will trigger an
interrupt on either a negative edge at the IRQ/VPP pin and/or while the
IRQ/VPP pin is held in the low state. In either case, the IRQ/VPP pin must
be held low for at least one tILIH time period. If the edge- and level-
sensitive mode is selected (LEVEL bit set), the IRQ/VPP input pin
requires an external resistor connected to VDD for wired-OR operation.
If the IRQ/VPP pin is not used, it must be tied to the VDD supply. The
IRQ/VPP pin input circuitry contains an internal Schmitt trigger to improve
noise immunity. Refer to Section 5. Interrupts.

NOTE: If the voltage level applied to the IRQ/VPP pin exceeds VDD, it may affect
the MCU’s mode of operation. See Section 3. Operating Modes.

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General Description

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Advance Information — MC68HC705P6A

Section 2. Memory

2.1 Contents
2.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2.3 User Mode Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2.4 Bootloader Mode Memory Map . . . . . . . . . . . . . . . . . . . . . . . .28

2.5 Input/Output and Control Registers . . . . . . . . . . . . . . . . . . . . . 29

2.6 RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

2.7 EPROM/ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

2.8 Mask Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

2.9 Computer Operating Properly (COP) Clear Register . . . . . . . . 34

2.2 Introduction
The MC68HC705P6A utilizes 13 address lines to access an internal
memory space covering 8 Kbytes. This memory space is divided into
I/O, RAM, ROM, and EPROM areas.

2.3 User Mode Memory Map

When the MC68HC705P6A is in the user mode, the 32 bytes of I/O,
176 bytes of RAM, 4608 bytes of user EPROM, 48 bytes of user page
zero EPROM, 239 bytes of bootloader ROM, and 16 bytes of user
vectors EPROM are all active as shown in Figure 2-1.

MC68HC705P6A — Rev. 2.0 Advance Information

MOTOROLA Memory 27
Memory

$0000 0000 $0000

I/O
32 BYTES
$001F 0031
$0020 0032
USER EPROM I/O REGISTERS
48 BYTES SEE FIGURE 2-2
$004F 0079
$0050 0080
INTERNAL RAM
176 BYTES
$00BF 0191
$00C0 0192 $001F
STACK
64 BYTES
$00FF 0255
$0100 0256

USER EPROM
4608 BYTES COP CLEAR REGISTER(1) $1FF0
UNUSED $1FF1
UNUSED $1FF2

$12FF 4863 UNUSED $1FF3

$1300 4864 UNUSED $1FF4
UNIMPLEMENTED
UNUSED $1FF5
3071 BYTES
UNUSED $1FF6
$1EFE 7934
$1EFF 7935 UNUSED $1FF7
$1F00 MASK OPTION REGISTERS 7936 TIMER VECTOR (HIGH BYTE) $1FF8
$1F01 7937
BOOTLOADER ROM TIMER VECTOR (LOW BYTE) $1FF9
AND VECTORS 239 BYTES
$1FEF 8175 IRQ VECTOR (HIGH BYTE) $1FFA
$1FF0 8176 IRQ VECTOR (LOW BYTE) $1FFB
USER VECTORS EPROM
16 BYTES SWI VECTOR (HIGH BYTE) $1FFC
$1FFF 8191
SWI VECTOR (LOW BYTE) $1FFD
RESET VECTOR (HIGH BYTE) $1FFE
RESET VECTOR (LOW BYTE) $1FFF

Note 1. Writing zero to bit 0 of $1FF0 clears the COP watchdog timer. Reading $1FF0 returns user EPROM data.

Figure 2-1. MC68HC705P6A User Mode Memory Map

2.4 Bootloader Mode Memory Map

Memory space is identical to the user mode. See Figure 2-1.

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28 Memory MOTOROLA
 Memory
Input/Output and Control Registers

2.5 Input/Output and Control Registers

Figure 2-2 and Figure 2-3 briefly describe the I/O and control registers
at locations $0000–$001F. Reading unimplemented bits will return
unknown states, and writing unimplemented bits will be ignored.

PORT A DATA REGISTER $0000

PORT B DATA REGISTER $0001
PORT C DATA REGISTER $0002
PORT D DATA REGISTER $0003
PORT A DATA DIRECTION REGISTER $0004
PORT B DATA DIRECTION REGISTER $0005
PORT C DATA DIRECTION REGISTER $0006
PORT D DATA DIRECTION REGISTER $0007
UNIMPLEMENTED $0008
UMIMPLEMENTED $0009
SIOP CONTROL REGISTER $000A
SIOP STATUS REGISTER $000B
SIOP DATA REGISTER $000C
RESERVED $000D
UNIMPLEMENTED $000E
UNIMPLEMENTED $000F
UNIMPLEMENTED $0010
UNIMPLEMENTED $0011
TIMER CONTROL REGISTER $0012
TIMER STATUS REGISTER $0013
INPUT CAPTURE MSB $0015
INPUT CAPTURE LSB $0016
OUTPUT COMPARE MSB $0017
OUTPUT COMPARE LSB $0017
TIMER MSB $0018
TIMER LSB $0019
ALTERNATE COUNTER MSB $001A
ALTERNATE COUNTER LSB $001B
EPROM PROGRAMMING REGISTER $001C
A/D CONVERTER DATA REGISTER $001D
A/D CONVERTER CONTROL AND STATUS REGISTER $001E
RESERVED $001F

Figure 2-2. MC68HC705P6A I/O and Control

Registers Memory Map

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MOTOROLA Memory 29
Memory

Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0

Read:
Port A Data Register PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
$0000 (PORTA) Write:
See page 52.
Reset: Unaffected by reset

Read: 0 0 0 0 0
Port B Data Register PB7 PB6 PB5
$0001 (PORTB) Write:
See page 53.
Reset: Unaffected by reset

Read:
Port C Data Register PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
$0002 (PORTC) Write:
See page 54.
Reset: Unaffected by reset

Read: PD7 0 1 0 0 0 0
Port D Data Register PD5
$0003 (PORTD) Write:
See page 55.
Reset: Unaffected by reset

Read:
Port A Data Direction DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
$0004 Register (DDRA) Write:
See page 52.
Reset: 0 0 0 0 0 0 0 0

Read: 1 1 1 1 1
Port B Data Direction DDRB7 DDRB6 DDRB5
$0005 Register (DDRB) Write:
See page 53.
Reset: 0 0 0 0 0 0 0 0

Read:
Port C Data Direction DDRC7 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0
$0006 Register (DDRC) Write:
See page 54.
Reset: 0 0 0 0 0 0 0 0

Read: 0 0 0 0 0 0 0
Port D Data Direction DDRD5
$0007 Register (DDRD) Write:
See page 55.
Reset: 0 0 0 0 0 0 0 0

$0008 Unimplemented

= Unimplemented R = Reserved U = Undetermined

Figure 2-3. I/O and Control Register Summary (Sheet 1 of 4)

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30 Memory MOTOROLA
 Memory
Input/Output and Control Registers

Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0

$0009 Unimplemented

Read: 0 0 0 0 0 0
SIOP Control Register SPE MSTR
$000A (SCR) Write:
See page 62.
Reset: 0 0 0 0 0 0 0 0

Read: SPIF DCOL 0 0 0 0 0 0

SIOP Status Register
$000B (SSR) Write:
See page 63.
Reset: 0 0 0 0 0 0 0 0

Read:
SIOP Data Register SDR7 SDR6 SDR5 SDR4 SDR3 SSDR2 SDR1 SDR0
$000C (SDR) Write:
See page 64.
Reset: Unaffected by reset

$000D Reserved for Test R R R R R R R R

$000E Unimplemented

$000F Unimplemented

$0010 Unimplemented

$0011 Unimplemented

Read: 0 0 0
Timer Control Register ICIE OCIE TOIE IEDG OLVL
$0012 (TCR) Write:
See page 68.
Reset: 0 0 0 0 0 0 U 0

Read: ICF OCF TOF 0 0 0 0 0

Timer Status Register
$0013 (TSR) Write:
See page 70.
Reset: U U U 0 0 0 0 0

= Unimplemented R = Reserved U = Undetermined

Figure 2-3. I/O and Control Register Summary (Sheet 2 of 4)

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MOTOROLA Memory 31
Memory

Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0

Read: ICRH7 ICRH6 ICRH5 ICRH4 ICRH3 ICRH2 ICRH1 ICRH0

Input Capture Register
$0014 MSB (ICRH) Write:
See page 73.
Reset: Unaffected by reset

Read: ICRL7 ICRL6 ICRL5 ICRL4 ICRL3 ICRL2 ICRL1 ICRL0

Input Capture Register
$0015 LSB (ICRL) Write:
See page 73.
Reset: Unaffected by reset

Read:
Output Compare OCRH7 OCRH6 OCRH5 OCRH4 OCRH3 OCRH2 OCRH1 OCRH0
$0016 Register MSB (OCRH) Write:
See page 74.
Reset: Unaffected by reset

Read:
Output Compare OCRL7 OCRL6 OCRL5 OCRL4 OCRL3 OCRL2 OCRL1 OCRL0
$0017 Register LSB (OCRL) Write:
See page 74.
Reset: Unaffected by reset

Read: TRH7 TRH6 TRH5 TRH4 TRH3 TRH2 TRH1 TRH0

Timer Register MSB
$0018 (TRH) Write:
See page 71.
Reset: 1 1 1 1 1 1 1 1

Read: TRL7 TRL6 TRL5 TRL4 TRL3 TRL2 TRL1 TRL0

Timer Register LSB
$0019 (TRL) Write:
See page 71.
Reset: 1 1 1 1 1 1 0 0

Read: ACRH7 ACRH6 ACRH5 ACRH4 ACRH3 ACRH2 ACRH1 ACRH0

Alternate Timer
$001A Register MSB (ATRH) Write:
See page 72.
Reset: 1 1 1 1 1 1 1 1

Read: ACRL7 ACRL6 ACRL5 ACRL4 ACRL3 ACRL2 ACRL1 ACRL0

Alternate Timer
$001B Register LSB (ATRL) Write:
See page 72.
Reset: 1 1 1 1 1 1 0 0

Read: 0 0 0 0 0 0
EPROM Programming ELAT EPGM
$001C Register (EPROG) Write:
See page 85.
Reset: 0 0 0 0 0 0 0 0

= Unimplemented R = Reserved U = Undetermined

Figure 2-3. I/O and Control Register Summary (Sheet 3 of 4)

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32 Memory MOTOROLA
 Memory
RAM

Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0

Read: AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0

A/D Conversion Value
$001D Data Register (ADC) Write:
See page 82.
Reset: Unaffected by reset

Read: CC 0 0
A/D Status and Control ADRC ADON CH2 CH1 CH0
$001E Register (ADSC) Write:
See page 80.
Reset: 0 0 0 0 0 0 0 0

$001F Reserved for Test R R R R R R R R

= Unimplemented R = Reserved U = Undetermined

Figure 2-3. I/O and Control Register Summary (Sheet 4 of 4)

2.6 RAM
The user RAM consists of 176 bytes (including the stack) at locations
$0050 through $00FF. The stack begins at address $00FF. The stack
pointer can access 64 bytes of RAM from $00FF to $00C0.

NOTE: Using the stack area for data storage or temporary work locations
requires care to prevent it from being overwritten due to stacking from an
interrupt or subroutine call.

2.7 EPROM/ROM
There are 4608 bytes of user EPROM at locations $0100 through
$12FF, plus 48 bytes in user page zero locations $0020 through $004F,
and 16 additional bytes for user vectors at locations $1FF0 through
$1FFF. The bootloader ROM and vectors are at locations $1F01 through
$1FEF.

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MOTOROLA Memory 33
Memory

2.8 Mask Option Register

The mask option register (MOR) is a pair of EPROM bytes located at
$1EFF and $1F00. It controls the programmable options on the
MC68HC705P6A. See Section 11. Mask Option Register (MOR) for
additional information.

$1EFF Bit 7 6 5 4 3 2 1 Bit 0

Read:
PA7PU PA6PU PA5PU PA4PU PA3PU PA2PU PA1PU PA0PU
Write:
Erased State: 0 0 0 0 0 0 0 0

$1F00 Bit 7 6 5 4 3 2 1 Bit 0

Read:
SECURE SWAIT SPR1 SPR0 LSBF LEVEL COP
Write:
Erased State: 0 0 0 0 0 0 0 0
= Unimplemented

Figure 2-4. Mask Option Register (MOR)

2.9 Computer Operating Properly (COP) Clear Register

The computer operating properly (COP) watchdog timer is located at
address $1FF0. Writing a logical 0 to bit zero of this location will clear the
COP watchdog counter as described in 4.4.2 Computer Operating
Properly (COP) Reset.

$1FF0 Bit 7 6 5 4 3 2 1 Bit 0

Read: 0 0 0 0 0 0 0 0

Write: COPR

Reset: 0 0 0 0 0 0 0 0

= Unimplemented

Figure 2-5. COP Watchdog Timer Location

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34 Memory MOTOROLA
Advance Information — MC68HC705P6A

Section 3. Operating Modes

3.1 Contents
3.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.3 User Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.4 Bootloader Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.5.1 STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
3.5.1.1 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.5.1.2 Halt Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.5.2 WAIT Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

3.6 COP Watchdog Timer Considerations . . . . . . . . . . . . . . . . . . .40

3.2 Introduction
The MC68HC705P6A has two modes of operation that affect the pinout
and architecture of the MCU: user mode and bootloader mode. The user
mode is normally used for the application and the bootloader mode is
used for programming the EPROM. The conditions required to enter
each mode are shown in Table 3-1. The mode of operation is
determined by the voltages on the IRQ/VPP and PD7/TCAP pins on the
rising edge of the external RESET pin.

Table 3-1. Operating Mode Conditions After Reset

RESET Pin IRQ/VPP PD7/TCAP Mode

VSS to VDD VSS to VDD Single chip

VPP VDD Bootloader

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MOTOROLA Operating Modes 35

Operating Modes

The mode of operation is also determined whenever the internal

computer operating properly (COP) watchdog timer resets the MCU.
When the COP timer expires, the voltage applied to the IRQ/VPP pin
controls the mode of operation while the voltage applied to PD7/TCAP is
ignored. The voltage applied to PD7/TCAP during the last rising edge on
RESET is stored in a latch and used to determine the mode of operation
when the COP watchdog timer resets the MCU.

3.3 User Mode

The user mode allows the MCU to function as a self-contained
microcontroller, with maximum use of the pins for on-chip peripheral
functions. All address and data activity occurs within the MCU and are
not available externally. User mode is entered on the rising edge of
RESET if the IRQ/VPP pin is within the normal operating voltage range.
The pinout for the user mode is shown in Figure 3-1.

RESET 1 28 VDD
IRQ/VPP 2 27 OSC1
PA7 3 26 OSC2
PA6 4 25 PD7/TCAP
PA5 5 24 TCMP
PA4 6 23 PD5
PA3 7 22 PC0
PA2 8 21 PC1
PA1 9 20 PC2
PA0 10 19 PC3/AD3
SDO/PB5 11 18 PC4/AD2
SDI/PB6 12 17 PC5/AD1
SCK/PB7 13 16 PC6/AD0
VSS 14 15 PC7/VREFH

Figure 3-1. User Mode Pinout

In the user mode, there is an 8-bit I/O port, a second 8-bit I/O port shared
with the analog-to-digital (A/D) subsystem, one 3-bit I/O port shared with
the serial input/output port (SIOP), and a 3-bit port shared with the 16-bit
timer subsystem, which includes one general-purpose I/O pin.

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36 Operating Modes MOTOROLA

 Operating Modes
Bootloader Mode

3.4 Bootloader Mode

The bootloader mode provides a means to program the user EPROM
from an external memory device or host computer. This mode is entered
on the rising edge of RESET if VPP is applied to the IRQ/VPP pin and VDD
is applied to the PD7/TCAP pin. The user code in the external memory
device must have data located in the same address space it will occupy
in the internal MCU EPROM, including the mask option register (MOR)
at $1EFF and $1F00.

3.5 Low-Power Modes

The MC68HC705P6A is capable of running in a low-power mode in each
of its configurations. The WAIT and STOP instructions provide three
modes that reduce the power required for the MCU by stopping various
internal clocks and/or the on-chip oscillator. The SWAIT bit in the MOR
is used to modify the behavior of the STOP instruction from stop mode
to halt mode. The flow of the stop, halt, and wait modes is shown in
Figure 3-2.

3.5.1 STOP Instruction

The STOP instruction can result in one of two modes of operation

depending on the state of the SWAIT bit in the MOR. If the SWAIT bit is
clear, the STOP instruction will behave like a normal STOP instruction in
the M68HC05 Family and place the MCU in stop mode. If the SWAIT bit
in the MOR is set, the STOP instruction will behave like a WAIT
instruction (with the exception of a brief delay at startup) and place the
MCU in halt mode.

3.5.1.1 Stop Mode

Execution of the STOP instruction when the SWAIT bit in the MOR is
clear places the MCU in its lowest power consumption mode. In stop
mode, the internal oscillator is turned off, halting all internal processing,
including the COP watchdog timer. Execution of the STOP instruction
automatically clears the I bit in the condition code register so that the IRQ
external interrupt is enabled. All other registers and memory remain
unaltered. All input/output lines remain unchanged.

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MOTOROLA Operating Modes 37

Operating Modes

STOP HALT WAIT

MOR EXTERNAL OSCILLATOR ACTIVE

Y AND
SWAIT
BIT SET? INTERNAL TIMER CLOCK ACTIVE

N
STOP INTERNAL EXTERNAL OSCILLATOR ACTIVE
STOP EXTERNAL OSCILLATOR, PROCESSOR CLOCK, AND
STOP INTERNAL TIMER CLOCK, CLEAR I BIT IN CCR INTERNAL TIMER CLOCK ACTIVE
RESET STARTUP DELAY

STOP INTERNAL
STOP INTERNAL Y EXTERNAL PROCESSOR CLOCK,
PROCESSOR CLOCK, RESET? CLEAR I BIT IN CCR
CLEAR I BIT IN CCR
N

IRQ Y EXTERNAL
EXTERNAL Y Y EXTERNAL RESET?
RESET? INTERRUPT?
N
N N
IRQ
IRQ TIMER Y
Y Y EXTERNAL
EXTERNAL INTERNAL INTERRUPT?
INTERRUPT? INTERRUPT?
N
N RESTART EXTERNAL OSCILLATOR, N
START STABILIZATION DELAY
TIMER
COP Y
Y INTERNAL
INTERNAL INTERRUPT?
RESET?
N
END N
Y
OF STABILIZATION
COP
DELAY? Y
INTERNAL
N RESET?
RESTART
N
INTERNAL PROCESSOR CLOCK

1. FETCH RESET VECTOR

OR
2. SERVICE INTERRUPT
A. STACK
B. SET I BIT
C. VECTOR TO INTERRUPT ROUTINE

Figure 3-2. STOP/WAIT Flowcharts

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38 Operating Modes MOTOROLA

 Operating Modes
Low-Power Modes

The MCU can be brought out of stop mode only by an IRQ external
interrupt or an externally generated RESET. When exiting stop mode,
the internal oscillator will resume after a 4064 internal clock cycle
oscillator stabilization delay.

NOTE: Execution of the STOP instruction when the SWAIT bit in the MOR is
clear will cause the oscillator to stop, and, therefore, disable the COP
watchdog timer. To avoid turning off the COP watchdog timer, stop
mode should be changed to halt mode by setting the SWAIT bit in the
MOR. See 3.6 COP Watchdog Timer Considerations for additional
information.

3.5.1.2 Halt Mode

NOTE: Halt mode is NOT designed for intentional use. Halt mode is only
provided to keep the COP watchdog timer active in the event a STOP
instruction is executed inadvertently. This mode of operation is usually
achieved by invoking wait mode.

Execution of the STOP instruction when the SWAIT bit in the MOR is set
places the MCU in this low-power mode. Halt mode consumes the same
amount of power as wait mode (both halt and wait modes consume more
power than stop mode).

In halt mode, the internal clock is halted, suspending all processor and
internal bus activity. Internal timer clocks remain active, permitting
interrupts to be generated from the 16-bit timer or a reset to be
generated from the COP watchdog timer. Execution of the STOP
instruction automatically clears the I bit in the condition code register,
enabling the IRQ external interrupt. All other registers, memory, and
input/output lines remain in their previous states.

If the 16-bit timer interrupt is enabled, it will cause the processor to exit
the halt mode and resume normal operation. The halt mode also can be
exited when an IRQ external interrupt or external RESET occurs.
When exiting the halt mode, the internal clock will resume after a delay
of one to 4064 internal clock cycles. This varied delay time is the result
of the halt mode exit circuitry testing the oscillator stabilization delay

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MOTOROLA Operating Modes 39

Operating Modes

timer (a feature of the stop mode), which has been free-running (a

feature of the wait mode).

3.5.2 WAIT Instruction

The WAIT instruction places the MCU in a low-power mode which

consumes more power than stop mode. In wait mode, the internal clock
is halted, suspending all processor and internal bus activity. Internal
timer clocks remain active, permitting interrupts to be generated from the
16-bit timer and reset to be generated from the COP watchdog timer.
Execution of the WAIT instruction automatically clears the I bit in the
condition code register, enabling the IRQ external interrupt. All other
registers, memory, and input/output lines remain in their previous state.

If the 16-bit timer interrupt is enabled, it will cause the processor to exit
wait mode and resume normal operation. The 16-bit timer may be used
to generate a periodic exit from wait mode. Wait mode may also be
exited when an IRQ external interrupt or RESET occurs.

3.6 COP Watchdog Timer Considerations

The COP watchdog timer is active in user mode of operation when the
COP bit in the MOR is set. Executing the STOP instruction when the
SWAIT bit in the MOR is clear will cause the COP to be disabled.
Therefore, it is recommended that the STOP instruction be modified to
produce halt mode (set bit SWAIT in the MOR) if the COP watchdog
timer is required to function at all times.

Furthermore, it is recommended that the COP watchdog timer be

disabled for applications that will use the wait mode for time periods that
will exceed the COP timeout period.

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40 Operating Modes MOTOROLA

Advance Information — MC68HC705P6A

Section 4. Resets

4.1 Contents
4.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

4.3 External Reset (RESET). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

4.4 Internal Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

4.4.1 Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.4.2 Computer Operating Properly (COP) Reset . . . . . . . . . . . . . 42

4.2 Introduction
The MCU can be reset from three sources: one external input and two
internal reset conditions. The RESET pin is a Schmitt trigger input as
shown in Figure 4-1. The CPU and all peripheral modules will be reset
by the RST signal which is the logical OR of internal reset functions and
is clocked by PH1.

RESET

POWER-ON D
VDD RESET
RST TO CPU AND
(POR) RES
DFF PERIPHERALS

OSC
COP
DATA WATCHDOG PH1
(COPR)
ADDRESS

Figure 4-1. Reset Block Diagram

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MOTOROLA Resets 41
Resets

4.3 External Reset (RESET)

The RESET input is the only external reset and is connected to an
internal Schmitt trigger. The external reset occurs whenever the RESET
input is driven below the lower threshold and remains in reset until the
RESET pin rises above the upper threshold. The upper and lower
thresholds are given in Section 14. Electrical Specifications.

4.4 Internal Resets

The two internally generated resets are the initial power-on reset (POR)
function and the computer operating properly (COP) watchdog timer
function.

4.4.1 Power-On Reset (POR)

The internal POR is generated at power-up to allow the clock oscillator

to stabilize. The POR is strictly for power turn-on conditions and should
not be used to detect a drop in the power supply voltage. There is a 4064
internal clock cycle oscillator stabilization delay after the oscillator
becomes active.

The POR will generate the RST signal and reset the MCU. If any other
reset function is active at the end of this 4064 internal clock cycle delay,
the RST signal will remain active until the other reset condition(s) end.

4.4.2 Computer Operating Properly (COP) Reset

When the COP watchdog timer is enabled (COP bit in the MOR is set),
the internal COP reset is generated automatically by a timeout of the
COP watchdog timer. This timer is implemented with an 18-stage ripple
counter that provides a timeout period of 65.5 ms when a 4-MHz
oscillator is used. The COP watchdog counter is cleared by writing a
logical 0 to bit zero at location $1FF0.

The COP watchdog timer can be disabled by clearing the COP bit in the
MOR or by applying 2 x VDD to the IRQ/VPP pin (for example, during
bootloader). When the IRQ/VPP pin is returned to its normal operating

Advance Information MC68HC705P6A — Rev. 2.0

42 Resets MOTOROLA
 Resets
Internal Resets

voltage range (between VSS–VDD), the COP watchdog timer’s output will
be restored if the COP bit in the mask option register (MOR) is set.

The COP register is shared with the least significant byte (LSB) of an
unused vector address as shown in Figure 4-2. Reading this location will
return the programmed value of the unused user interrupt vector,
usually 0. Writing to this location will clear the COP watchdog timer.

Address: $1FF0

Bit 7 6 5 4 3 2 1 Bit 0

Read: 0 0 0 0 0 0 0 0

Write: COPR

= Unimplemented

Figure 4-2. Unused Vector and COP Watchdog Timer

When the COP watchdog timer expires, it will generate the RST signal
and reset the MCU. If any other reset function is active at the end of the
COP reset signal, the RST signal will remain in the reset condition until
the other reset condition(s) end. When the reset condition ends, the
MCU’s operating mode will be selected (see Table 3-1).

MC68HC705P6A — Rev. 2.0 Advance Information

MOTOROLA Resets 43
Resets

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44 Resets MOTOROLA
Advance Information — MC68HC705P6A

Section 5. Interrupts

5.1 Contents
5.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

5.3 Interrupt Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

5.3.1 Reset Interrupt Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.3.2 Software Interrupt (SWI). . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.3.3 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.3.3.1 External Interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.3.3.2 Input Capture Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.3.3.3 Output Compare Interrupt . . . . . . . . . . . . . . . . . . . . . . . .49
5.3.3.4 Timer Overflow Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . 49

5.2 Introduction
The MCU can be interrupted six different ways:
1. Non-maskable software interrupt instruction (SWI)
2. External asynchronous interrupt (IRQ)
3. Input capture interrupt (TIMER)
4. Output compare interrupt (TIMER)
5. Timer overflow interrupt (TIMER)
6. Port A interrupt (if selected via mask option register)

Interrupts cause the processor to save the register contents on the stack
and to set the interrupt mask (I bit) to prevent additional interrupts. Unlike
reset, hardware interrupts do not cause the current instruction execution
to be halted, but are considered pending until the current instruction is
completed.

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MOTOROLA Interrupts 45
Interrupts

When the current instruction is completed, the processor checks all

pending hardware interrupts. If interrupts are not masked (I bit in the
condition code register is clear) and the corresponding interrupt enable
bit is set, the processor proceeds with interrupt processing. Otherwise,
the next instruction is fetched and executed. The SWI is executed the
same as any other instruction, regardless of the I-bit state.

When an interrupt is to be processed, the CPU puts the register contents

on the stack, sets the I bit in the CCR, and fetches the address of the
corresponding interrupt service routine from the vector table at locations
$1FF8 through $1FFF. If more than one interrupt is pending when the
interrupt vector is fetched, the interrupt with the highest vector location
shown in Table 5-1 will be serviced first.

Table 5-1. Vector Addresses for Interrupts and Reset

Flag CPU Vector
Register Interrupts
Name Interrupt Address

N/A N/A Reset RESET $1FFE–$1FFF

N/A N/A Software SWI $1FFC–$1FFD

N/A N/A External Interrupt IRQ $1FFA–$1FFB

TSR ICF Timer Input Capture TIMER $1FF8–$1FF9

TSR OCF Timer Output Compare TIMER $1FF8–$1FF9

TSR TOF Timer Overflow TIMER $1FF8–$1FF9

An RTI instruction is used to signify when the interrupt software service

routine is completed. The RTI instruction causes the CPU state to be
recovered from the stack and normal processing to resume at the next
instruction that was to be executed when the interrupt took place.
Figure 5-1 shows the sequence of events that occurs during interrupt
processing.

Advance Information MC68HC705P6A — Rev. 2.0

46 Interrupts MOTOROLA
 Interrupts
Interrupt Types

FROM RESET

Y IS I BIT
SET?

N
IRQ CLEAR IRQ
Y
INTERRUPT? REQUEST
LATCH
N

TIMER Y
INTERRUPT?

N STACK
PC, X, A, CC

SET
I BIT IN CCR

LOAD PC FROM:
SWI: $1FFC, $1FFD
IRQ: $1FFA-$1FFB
TIMER: $1FF8-$1FF9

FETCH NEXT
INSTRUCTION

SWI
Y
INSTRUCTION?

N
RTI RESTORE RESISTERS
Y FROM STACK
INSTRUCTION?
CC, A, X, PC
N

EXECUTE INSTRUCTION

Figure 5-1. Interrupt Processing Flowchart

5.3 Interrupt Types

The interrupts fall into three categories: reset, software, and hardware.

MC68HC705P6A — Rev. 2.0 Advance Information

MOTOROLA Interrupts 47
Interrupts

5.3.1 Reset Interrupt Sequence

The reset function is not in the strictest sense an interrupt; however, it is

acted upon in a similar manner as shown in Figure 5-1. A low-level input
on the RESET pin or internally generated RST signal causes the
program to vector to its starting address which is specified by the
contents of memory locations $1FFE and $1FFF. The I bit in the
condition code register is also set. The MCU is configured to a known
state during this type of reset as previously described in Section 4.
Resets.

5.3.2 Software Interrupt (SWI)

The SWI is an executable instruction. It is also a non-maskable interrupt

since it is executed regardless of the state of the I bit in the CCR. As with
any instruction, interrupts pending during the previous instruction will be
serviced before the SWI opcode is fetched. The interrupt service routine
address for the SWI instruction is specified by the contents of memory
locations $1FFC and $1FFD.

5.3.3 Hardware Interrupts

All hardware interrupts are maskable by the I bit in the CCR. If the I bit is
set, all hardware interrupts (internal and external) are disabled. Clearing
the I bit enables the hardware interrupts. Four hardware interrupts are
explained in the following subsections.

5.3.3.1 External Interrupt (IRQ)

The IRQ/VPP pin drives an asynchronous interrupt to the CPU. An edge

detector flip-flop is latched on the falling edge of IRQ/VPP. If either the
output from the internal edge detector flip-flop or the level on the
IRQ/VPP pin is low, a request is synchronized to the CPU to generate the
IRQ interrupt. If the LEVEL bit in the mask option register is clear (edge-
sensitive only), the output of the internal edge detector flip-flop is
sampled and the input level on the IRQ/VPP pin is ignored. The interrupt
service routine address is specified by the contents of memory locations

Advance Information MC68HC705P6A — Rev. 2.0

48 Interrupts MOTOROLA
 Interrupts
Interrupt Types

$1FFA and $1FFB. If the port A interrupts are enabled by the MOR, they
generate external interrupts identically to the IRQ/VPP pin.

NOTE: The internal interrupt latch is cleared nine internal clock cycles after the
interrupt is recognized (immediately after location $1FFA is read).
Therefore, another external interrupt pulse could be latched during the
IRQ service routine.

Another interrupt will be serviced if the IRQ pin is still in a low state when
the RTI in the service routine is executed.

5.3.3.2 Input Capture Interrupt

The input capture interrupt is generated by the 16-bit timer as described

in Section 8. Capture/Compare Timer. The input capture interrupt flag
is located in register TSR and its corresponding enable bit can be found
in register TCR. The I bit in the CCR must be clear for the input capture
interrupt to be enabled. The interrupt service routine address is specified
by the contents of memory locations $1FF8 and $1FF9.

5.3.3.3 Output Compare Interrupt

The output compare interrupt is generated by a 16-bit timer as described

in Section 8. Capture/Compare Timer. The output compare interrupt
flag is located in register TSR and its corresponding enable bit can be
found in register TCR. The I bit in the CCR must be clear for the output
compare interrupt to be enabled. The interrupt service routine address is
specified by the contents of memory locations $1FF8 and $1FF9.

5.3.3.4 Timer Overflow Interrupt

The timer overflow interrupt is generated by the 16-bit timer as described

in Section 8. Capture/Compare Timer. The timer overflow interrupt flag
is located in register TSR and its corresponding enable bit can be found
in register TCR. The I bit in the CCR must be clear for the timer overflow
interrupt to be enabled. This internal interrupt will vector to the interrupt
service routine located at the address specified by the contents of
memory locations $1FF8 and $1FF9.

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Interrupts

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Section 6. Input/Output Ports

6.1 Contents
6.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

6.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

6.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

6.5 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

6.6 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

6.7 I/O Port Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

6.2 Introduction
In the user mode, 20 bidirectional I/O lines are arranged as two 8-bit I/O
ports (ports A and C), one 3-bit I/O port (port B), and one 1-bit I/O port
(port D). These ports are programmable as either inputs or outputs
under software control of the data direction registers (DDRs). Port D also
contains one input-only pin.

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Input/Output Ports

6.3 Port A
Port A is an 8-bit bidirectional port, which does not share any of its pins
with other subsystems (see Figure 6-1). The port A data register is
located at address $0000 and its data direction register (DDR) is located
at address $0004. The contents of the port A data register are
indeterminate at initial power up and must be initialized by user software.
Reset does not affect the data registers, but does clear the DDRs,
thereby setting all of the port pins to input mode. Writing a 1 to a DDR bit
sets the corresponding port pin to output mode. Port A has mask option
register enabled interrupt capability with an internal pullup device

NOTE: The keyscan (pullup/interrupt) feature available on port A is NOT

available in the ROM device, MC68HC05P6.

VDD
READ $0004 PULLUP MASK
OPTION REGISTER
WRITE $0004
DATA DIRECTION
RESET REGISTER BIT
(RST)
WRITE $0000 I/O
DATA OUTPUT PIN
REGISTER BIT

READ $0000

INTERNAL HC05
DATA BUS TO IRQ
INTERRUPT SYSTEM

Figure 6-1. Port A I/O and Interrupt Circuitry

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 Input/Output Ports
Port B

6.4 Port B
Port B is a 3-bit bidirectional port which can share pins PB5–PB7 with
the SIOP communications subsystem. The port B data register is located
at address $0001 and its data direction register (DDR) is located at
address $0005. The contents of the port B data register are
indeterminate at initial powerup and must be initialized by user software.
Reset does not affect the data registers, but clears the DDRs, thereby
setting all of the port pins to input mode. Writing a 1 to a DDR bit sets the
corresponding port pin to output mode (see Figure 6-2).

Port B may be used for general I/O applications when the SIOP
subsystem is disabled. The SPE bit in register SPCR is used to
enable/disable the SIOP subsystem. When the SIOP subsystem is
enabled, port B registers are still accessible to software. Writing to either
of the port B registers while a data transfer is under way could corrupt
the data. See Section 7. Serial Input/Output Port (SIOP) for a
discussion of the SIOP subsystem.

READ $0005

WRITE $0005
DATA DIRECTION
RESET REGISTER BIT
(RST)
WRITE $0001 I/O
DATA OUTPUT PIN
REGISTER BIT

READ $0001

INTERNAL HC05
DATA BUS

Figure 6-2. Port B I/O Circuitry

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Input/Output Ports

6.5 Port C
Port C is an 8-bit bidirectional port which can share pins PC3–PC7 with
the A/D subsystem. The port C data register is located at address $0002
and its data direction register (DDR) is located at address $0006. The
contents of the port C data register are indeterminate at initial powerup
and must be initialized by user software. Reset does not affect the data
registers, but clears the DDRs, thereby setting all of the port pins to input
mode. Writing a 1 to a DDR bit sets the corresponding port pin to output
mode (see Figure 6-3).

Port C may be used for general I/O applications when the A/D
subsystem is disabled. The ADON bit in register ADSC is used to
enable/disable the A/D subsystem. Care must be exercised when using
pins PC0–PC2 while the A/D subsystem is enabled. Accidental changes
to bits that affect pins PC3–PC7 in the data or DDR registers will produce
unpredictable results in the A/D subsystem. See Section 9. Analog
Subsystem.

READ $0006

WRITE $0006
DATA DIRECTION
RESET REGISTER BIT
(RST)
WRITE $0002 I/O
DATA OUTPUT PIN
REGISTER BIT

READ $0002

INTERNAL HC05
DATA BUS

Figure 6-3. Port C I/O Circuitry

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 Input/Output Ports
Port D

6.6 Port D
Port D is a 2-bit port with one bidirectional pin (PD5) and one input-only
pin (PD7). Pin PD7 is shared with the 16-bit timer. The port D data
register is located at address $0003 and its data direction register (DDR)
is located at address $0007. The contents of the port D data register are
indeterminate at initial powerup and must be initialized by user software.
Reset does not affect the data registers, but clears the DDRs, thereby
setting PD5 to input mode. Writing a 1 to DDR bit 5 sets PD5 to output
mode (see Figure 6-4).

Port D may be used for general I/O applications regardless of the state
of the 16-bit timer. Since PD7 is an input-only line, its state can be read
from the port D data register at any time.

READ $0007

WRITE $0007
DATA DIRECTION
RESET REGISTER BIT
(RST)
WRITE $0003 I/O
DATA OUTPUT PIN
REGISTER BIT

READ $0003

INTERNAL HC05
DATA BUS

Figure 6-4. Port D I/O Circuitry

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Input/Output Ports

6.7 I/O Port Programming

Each pin on port A through port D (except pin 7 of port D) can be
programmed as an input or an output under software control as shown
in Table 6-1, Table 6-2, Table 6-3, and Table 6-4. The direction of a pin
is determined by the state of its corresponding bit in the associated port
data direction register (DDR). A pin is configured as an output if its
corresponding DDR bit is set to a logic 1. A pin is configured as an input
if its corresponding DDR bit is cleared to a logic 0.

Table 6-1. Port A I/O Functions

Accesses to Accesses to Data
DDRA I/O Pin Mode DDRA @ $0004 Register @ $0000
Read/Write Read Write
0 IN, Hi-Z DDRA0–DDRA7 I/O Pin See Note
1 OUT DDRA0–DDRA7 PA0–PA7 PA0–PA7
Note: Does not affect input, but stored to data register

Table 6-2. Port B I/O Functions

Accesses to Accesses to Data
DDRB I/O Pin Mode DDRB @ $0005 Register @ $0001
Read/Write Read Write
0 IN, Hi-Z DDRB5–DDRB7 I/O Pin See Note
1 OUT DDRB5–DDRB7 PB5–PB7 PB5–PB7
Note: Does not affect input, but stored to data register

Table 6-3. Port C I/O Functions

Accesses to Accesses to Data
DDRC I/O Pin Mode DDRC @ $0006 Register @ $0002
Read/Write Read Write
0 IN, Hi-Z DDRC0–DDRC7 I/O Pin See Note
1 OUT DDRC0–DDRC7 PC0–PC7 PC0–PC7
Note: Does not affect input, but stored to data register

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 Input/Output Ports
I/O Port Programming

Table 6-4. Port D I/O Functions

Accesses to Accesses to Data
DDRD I/O Pin Mode DDRD @ $0007 Register @ $0003
Read/Write Read Write
0 IN, Hi-Z DDRD5 I/O Pin See Note 1
1 OUT DDRD5 PD5 PD5
Notes:
1. Does not affect input, but stored to data register
2. PD7 is input only

NOTE: To avoid generating a glitch on an I/O port pin, data should be written to
the I/O port data register before writing a logic 1 to the corresponding
data direction register.

At power-on or reset, all DDRs are cleared, which configures all port pins
as inputs. The DDRs are capable of being written to or read by the
processor. During the programmed output state, a read of the data
register will actually read the value of the output data latch and not the
level on the I/O port pin.

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Input/Output Ports

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Section 7. Serial Input/Output Port (SIOP)

7.1 Contents
7.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

7.3 SIOP Signal Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

7.3.1 Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
7.3.2 Serial Data Input (SDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
7.3.3 Serial Data Output (SDO). . . . . . . . . . . . . . . . . . . . . . . . . . . 61

7.4 SIOP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

7.4.1 SIOP Control Register (SCR) . . . . . . . . . . . . . . . . . . . . . . . .62
7.4.2 SIOP Status Register (SSR) . . . . . . . . . . . . . . . . . . . . . . . .63
7.4.3 SIOP Data Register (SDR). . . . . . . . . . . . . . . . . . . . . . . . . . 64

7.2 Introduction
The simple synchronous serial I/O port (SIOP) subsystem is designed to
provide efficient serial communications between peripheral devices or
other MCUs. The SIOP is implemented as a 3-wire master/slave system
with serial clock (SCK), serial data input (SDI), and serial data output
(SDO). A block diagram of the SIOP is shown in Figure 7-1. A mask
programmable option determines whether the SIOP is MSB or LSB first.

The SIOP subsystem shares its input/output pins with port B. When the
SIOP is enabled (SPE bit set in register SCR), port B DDR and data
registers are modified by the SIOP. Although port B DDR and data
registers can be altered by application software, these actions could
affect the transmitted or received data.

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Serial Input/Output Port (SIOP)

HCO5 INTERNAL BUS

SPE

7 654 32 10 7 65 432 10 7654 32 10

BAUD SDO/PB5
STATUS 8-BIT SDO I/O
CONTROL
RATE SHIFT CONTROL
REGISTER REGISTER SDI
GENERATOR REGISTER LOGIC SDI/PB6
$0A $0B $0C

SCK SCK/PB7
INTERNAL
CPU CLOCK

Figure 7-1. SIOP Block Diagram

7.3 SIOP Signal Format

The SIOP subsystem is software configurable for master or slave
operation. No external mode selection inputs are available (for instance,
slave select pin).

7.3.1 Serial Clock (SCK)

The state of the SCK output normally remains a logic 1 during idle
periods between data transfers. The first falling edge of SCK signals the
beginning of a data transfer. At this time, the first bit of received data may
be presented at the SDI pin and the first bit of transmitted data is
presented at the SDO pin (see Figure 7-2). Data is captured at the SDI
pin on the rising edge of SCK. The transfer is terminated upon the eighth
rising edge of SCK.

The master and slave modes of operation differ only by the sourcing of
SCK. In master mode, SCK is driven from an internal source within the
MCU. In slave mode, SCK is driven from a source external to the MCU.
The SCK frequency is dependent upon the SPR0 and SPR1 bits located
in the mask option register. Refer to 11.3 Mask Option Register for a
description of available SCK frequencies.

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 Serial Input/Output Port (SIOP)
SIOP Signal Format

BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7

SDO

SCK

100 ns 100 ns

SDI
BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7

Figure 7-2. SIOP Timing Diagram

7.3.2 Serial Data Input (SDI)

The SDI pin becomes an input as soon as the SIOP subsystem is

enabled. New data may be presented to the SDI pin on the falling edge
of SCK.However, valid data must be present at least 100 nanoseconds
before the rising edge of SCK and remain valid for 100 nanoseconds
after the rising edge of SCK. See Figure 7-2.

7.3.3 Serial Data Output (SDO)

The SDO pin becomes an output as soon as the SIOP subsystem is

enabled. Prior to enabling the SIOP, PB5 can be initialized to determine
the beginning state. While the SIOP is enabled, PB5 cannot be used as
a standard output since that pin is connected to the last stage of the
SIOP serial shift register. Mask option register bit LSBF permits data to
be transmitted in either the MSB first format or the LSB first format. Refer
to 11.3 Mask Option Register for MOR LSBF programming information.

On the first falling edge of SCK, the first data bit will be shifted out to the
SDO pin. The remaining data bits will be shifted out to the SDO pin on
subsequent falling edges of SCK. The SDO pin will present valid data at
least 100 nanoseconds before the rising edge of the SCK and remain
valid for 100 nanoseconds after the rising edge of SCK. See Figure 7-2.

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Serial Input/Output Port (SIOP)

7.4 SIOP Registers

The SIOP is programmed and controlled by the SIOP control register
(SCR) located at address $000A, the SIOP status register (SSR) located
at address $000B, and the SIOP data register (SDR) located at address
$000C.

7.4.1 SIOP Control Register (SCR)

This register is located at address $000A and contains two bits. Figure
7-3 shows the position of each bit in the register and indicates the value
of each bit after reset.

Address: $000A

Bit 7 6 5 4 3 2 1 Bit 0

Read: 0 0 0 0 0 0
SPE MSTR
Write:

Reset: 0 0 0 0 0 0 0 0

= Unimplemented

Figure 7-3. SIOP Control Register (SCR)

SPE — Serial Peripheral Enable

When set, the SPE bit enables the SIOP subsystem such that
SDO/PB5 is the serial data output, SDI/PB6 is the serial data input,
and SCK/PB7 is a serial clock input in the slave mode or a serial clock
output in the master mode. Port B DDR and data registers can be
manipulated as usual (except for PB5); however, these actions could
affect the transmitted or received data.
The SPE bit is readable at any time. However, writing to the SIOP
control register while a transmission is in progress will cause the SPIF
and DCOL bits in the SIOP status register (see below) to operate
incorrectly. Therefore, the SIOP control register should be written
once to enable the SIOP and then not written to until the SIOP is to
be disabled. Clearing the SPE bit while a transmission is in progress

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 Serial Input/Output Port (SIOP)
SIOP Registers

will 1) abort the transmission, 2) reset the serial bit counter, and 3)
convert the port B/SIOP port to a general-purpose I/O port. Reset
clears the SPE bit.

MSTR — Master Mode Select

When set, the MSTR bit configures the serial I/O port for master
mode. A transfer is initiated by writing to the SDR. Also, the SCK pin
becomes an output providing a synchronous data clock dependent
upon the oscillator frequency. When the device is in slave mode, the
SDO and SDI pins do not change function. These pins behave exactly
the same in both the master and slave modes.
The MSTR bit is readable and writeable at any time regardless of the
state of the SPE bit. Clearing the MSTR bit will abort any transfers that
may have been in progress. Reset clears the MSTR bit as well as the
SPE bit, disabling the SIOP subsystem.

7.4.2 SIOP Status Register (SSR)

This register is located at address $000B and contains two bits. Figure
7-4 shows the position of each bit in the register and indicates the value
of each bit after reset.

Address: $000B

Bit 7 6 5 4 3 2 1 Bit 0

Read: SPIF DCOL 0 0 0 0 0 0

Write:

Reset: 0 0 0 0 0 0 0 0

= Unimplemented

Figure 7-4. SIOP Status Register (SSR)

SPIF — Serial Port Interface Flag

SPIF is a read-only status bit that is set on the last rising edge of SCK
and indicates that a data transfer has been completed. It has no effect
on any future data transfers and can be ignored. The SPIF bit is

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Serial Input/Output Port (SIOP)

cleared by reading the SSR followed by a read or write of the SDR. If

the SPIF is cleared before the last rising edge of SCK, it will be set
again on the last rising edge of SCK. Reset clears the SPIF bit.

DCOL — Data Collision

DCOL is a read-only status bit which indicates that an illegal access
of the SDR has occurred. The DCOL bit will be set when reading or
writing the SDR after the first falling edge of SCK and before SPIF is
set. Reading or writing the SDR during this time will result in invalid
data being transmitted or received.
The DCOL bit is cleared by reading the SSR (when the SPIF bit is set)
followed by a read or write of the SDR. If the last part of the clearing
sequence is done after another transfer has started, the DCOL bit will
be set again. Reset clears the DCOL bit.

7.4.3 SIOP Data Register (SDR)

This register is located at address $000C and serves as both the

transmit and receive data register. Writing to this register will initiate a
message transmission if the SIOP is in master mode. The SIOP
subsystem is not double buffered and any write to this register will
destroy the previous contents. The SDR can be read at any time;
however, if a transfer is in progress, the results may be ambiguous and
the DCOL bit will be set. Writing to the SDR while a transfer is in
progress can cause invalid data to be transmitted and/or received.
Figure 7-5 shows the position of each bit in the register. This register is
not affected by reset.

Address: $000C

Bit 7 6 5 4 3 2 1 Bit 0

Read:
SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0
Write:

Reset: Unaffected by reset

Figure 7-5. Serial Port Data Register (SDR)

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Advance Information — MC68HC705P6A

Section 8. Capture/Compare Timer

8.1 Contents
8.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

8.3 Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

8.3.1 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
8.3.2 Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

8.4 Timer I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

8.4.1 Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
8.4.2 Timer Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
8.4.3 Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
8.4.4 Alternate Timer Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 72
8.4.5 Input Capture Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
8.4.6 Output Compare Registers. . . . . . . . . . . . . . . . . . . . . . . . . . 74

8.5 Timer During Wait/Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 75

8.6 Timer During Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

8.2 Introduction
This section describes the operation of the 16-bit capture/compare timer.
Figure 8-1 shows the structure of the capture/compare subsystem.

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Capture/Compare Timer

INTERNAL BUS

INTERNAL
HIGH LOW PROCESSOR
CLOCK 8-BIT
BYTE BYTE BUFFER
³³³
÷4 HIGH LOW
$16 OUTPUT HIGH BYTE BYTE
$17 COMPARE BYTE LOW
REGISTER BYTE
16-BIT FREE INPUT $14
$18 CAPTURE $15
RUNNING $19 REGISTER
COUNTER
COUNTER $1A
ALTERNATE $1B
REGISTER

OUTPUT OVERFLOW EDGE

COMPARE DETECT DETECT
CIRCUIT CIRCUIT CIRCUIT

D Q
CLK
TIMER OUTPUT
STATUS ICF OCF TOF $13 LEVEL
REG. REG. C

TIMER
CONTROLRESET
ICIE OCIE TOIE IEDG OLVL REG.
$12
OUTPUT EDGE
INTERRUPT CIRCUIT LEVEL INPUT
(TCMP) (TCAP)

Figure 8-1. Capture/Compare Timer Block Diagram

8.3 Timer Operation

The core of the capture/compare timer is a 16-bit free-running counter.
The counter provides the timing reference for the input capture and
output compare functions. The input capture and output compare
functions provide a means to latch the times at which external events
occur, to measure input waveforms, and to generate output waveforms
and timing delays. Software can read the value in the 16-bit free-running
counter at any time without affecting the counter sequence.

Because of the 16-bit timer architecture, the I/O registers for the input
capture and output compare functions are pairs of 8-bit registers.

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 Capture/Compare Timer
Timer Operation

Because the counter is 16 bits long and preceded by a fixed divide-by-4

prescaler, the counter rolls over every 262,144 internal clock cycles.
Timer resolution with a 4-MHz crystal is 2 µs.

8.3.1 Input Capture

The input capture function is a means to record the time at which an

external event occurs. When the input capture circuitry detects an active
edge on the TCAP pin, it latches the contents of the timer registers into
the input capture registers. The polarity of the active edge is
programmable.

Latching values into the input capture registers at successive edges of

the same polarity measures the period of the input signal on the TCAP
pin. Latching values into the input capture registers at successive edges
of opposite polarity measures the pulse width of the signal.

8.3.2 Output Compare

The output compare function is a means of generating an output signal

when the 16-bit counter reaches a selected value. Software writes the
selected value into the output compare registers. On every fourth
internal clock cycle the output compare circuitry compares the value of
the counter to the value written in the output compare registers. When a
match occurs, the timer transfers the programmable output level bit
(OLVL) from the timer control register to the TCMP pin.

The programmer can use the output compare register to measure time
periods, to generate timing delays, or to generate a pulse of specific
duration or a pulse train of specific frequency and duty cycle on the
TCMP pin.

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Capture/Compare Timer

8.4 Timer I/O Registers

The following I/O registers control and monitor timer operation:
• Timer control register (TCR)
• Timer status register (TSR)
• Timer registers (TRH and TRL)
• Alternate timer registers (ATRH and ATRL)
• Input capture registers (ICRH and ICRL)
• Output compare registers (OCRH and OCRL)

8.4.1 Timer Control Register

The timer control register (TCR), shown in Figure 8-2, performs these
functions:
• Enables input capture interrupts
• Enables output compare interrupts
• Enables timer overflow interrupts
• Controls the active edge polarity of the TCAP signal
• Controls the active level of the TCMP output

Address: $0012

Bit 7 6 5 4 3 2 1 Bit 0

Read: 0 0 0
ICIE OCIE TOIE IEDG OLVL
Write:

Reset: 0 0 0 0 0 0 U 0

= Unimplemented U = Undetermined

Figure 8-2. Timer Control Register (TCR)

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 Capture/Compare Timer
Timer I/O Registers

ICIE — Input Capture Interrupt Enable

This read/write bit enables interrupts caused by an active signal on
the TCAP pin. Resets clear the ICIE bit.
1 = Input capture interrupts enabled
0 = Input capture interrupts disabled

OCIE — Output Compare Interrupt Enable

This read/write bit enables interrupts caused by an active signal on
the TCMP pin. Resets clear the OCIE bit.
1 = Output compare interrupts enabled
0 = Output compare interrupts disabled

TOIE — Timer Overflow Interrupt Enable

This read/write bit enables interrupts caused by a timer overflow.
Reset clear the TOIE bit.
1 = Timer overflow interrupts enabled
0 = Timer overflow interrupts disabled

IEDG — Input Edge

The state of this read/write bit determines whether a positive or
negative transition on the TCAP pin triggers a transfer of the contents
of the timer register to the input capture register. Resets have no
effect on the IEDG bit.
1 = Positive edge (low to high transition) triggers input capture
0 = Negative edge (high to low transition) triggers input capture

OLVL — Output Level

The state of this read/write bit determines whether a logic 1 or logic 0
appears on the TCMP pin when a successful output compare occurs.
Resets clear the OLVL bit.
1 = TCMP goes high on output compare
0 = TCMP goes low on output compare

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MOTOROLA Capture/Compare Timer 69

Capture/Compare Timer

8.4.2 Timer Status Register

The timer status register (TSR), shown in Figure 8-3, contains flags to
signal the following conditions:

• An active signal on the TCAP pin, transferring the contents of the

timer registers to the input capture registers
• A match between the 16-bit counter and the output compare
registers, transferring the OLVL bit to the TCMP pin
• A timer roll over from $FFFF to $0000

Address: $0013
Bit 7 6 5 4 3 2 1 Bit 0
Read: ICF OCF TOF 0 0 0 0 0
Write:
Reset: U U U 0 0 0 0 0
U = Undetermined

Figure 8-3. Timer Status Register (TSR)

ICF — Input Capture Flag

The ICF bit is set automatically when an edge of the selected polarity
occurs on the TCAP pin. Clear the ICF bit by reading the timer status
register with ICF set and then reading the low byte ($0015) of the
input capture registers. Resets have no effect on ICF.

OCF — Output Compare Flag

The OCF bit is set automatically when the value of the timer registers
matches the contents of the output compare registers. Clear the OCF
bit by reading the timer status register with OCF set and then reading
the low byte ($0017) of the output compare registers. Resets have no
effect on OCF.

TOF — Timer Overflow Flag

The TOF bit is set automatically when the 16-bit counter rolls over
from $FFFF to $0000. Clear the TOF bit by reading the timer status
register with TOF set, and then reading the low byte ($0019) of the
timer registers. Resets have no effect on TOF.

Advance Information MC68HC705P6A — Rev. 2.0

70 Capture/Compare Timer MOTOROLA

 Capture/Compare Timer
Timer I/O Registers

8.4.3 Timer Registers

The timer registers (TRH and TRL), shown in Figure 8-4, contains the
current high and low bytes of the 16-bit counter. Reading TRH before
reading TRL causes TRL to be latched until TRL is read. Reading TRL
after reading the timer status register clears the timer overflow flag
(TOF). Writing to the timer registers has no effect.

Address: TRH — $0018

Bit 7 6 5 4 3 2 1 Bit 0

Read: TRH7 TRH6 TRH5 TRH4 TRH3 TRH2 TRH1 TRH0

Write

Reset: 1 1 1 1 1 1 1 1

Address: TRL — $0019

Bit 7 6 5 4 3 2 1 Bit 0

Write:

Reset: 1 1 1 1 1 1 0 0

= Unimplemented

Figure 8-4. Timer Registers (TRH and TRL)

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MOTOROLA Capture/Compare Timer 71

Capture/Compare Timer

8.4.4 Alternate Timer Registers

The alternate timer registers (ATRH and ATRL), shown in Figure 8-5,
contain the current high and low bytes of the 16-bit counter. Reading
ATRH before reading ATRL causes ATRL to be latched until ATRL is
read. Reading ATRL has no effect on the timer overflow flag (TOF).
Writing to the alternate timer registers has no effect.

Address: ATRH — $001A

Bit 7 6 5 4 3 2 1 Bit 0

Read: ACRH7 ACRH6 ACRH5 ACRH4 ACRH3 ACRH2 ACRH1 ACRH0

Write:

Reset: 1 1 1 1 1 1 1 1

Address: ATRL — $001B

Bit 7 6 5 4 3 2 1 Bit 0

Write:

Reset: 1 1 1 1 1 1 0 0

= Unimplemented

Figure 8-5. Alternate Timer Registers (ATRH and ATRL)

NOTE: To prevent interrupts from occurring between readings of ATRH and

ATRL, set the interrupt flag in the condition code register before reading
ATRH, and clear the flag after reading ATRL.

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72 Capture/Compare Timer MOTOROLA

 Capture/Compare Timer
Timer I/O Registers

8.4.5 Input Capture Registers

When a selected edge occurs on the TCAP pin, the current high and low
bytes of the 16-bit counter are latched into the input capture registers.
Reading ICRH before reading ICRL inhibits further capture until ICRL is
read. Reading ICRL after reading the status register clears the input
capture flag (ICF). Writing to the input capture registers has no effect.

Address: ICRH — $0014

Bit 7 6 5 4 3 2 1 Bit 0

Read: ICRH7 ICRH6 ICRH5 ICRH4 ICRH3 ICRH2 ICRH1 ICRH0

Write:

Unaffected by reset

Address: ICRL — $0015

Bit 7 6 5 4 3 2 1 Bit 0

Write:

Unaffected by reset

= Unimplemented

Figure 8-6. Input Capture Registers (ICRH and ICRL)

NOTE: To prevent interrupts from occurring between readings of ICRH and

ICRL, set the interrupt flag in the condition code register before reading
ICRH, and clear the flag after reading ICRL.

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MOTOROLA Capture/Compare Timer 73

Capture/Compare Timer

8.4.6 Output Compare Registers

When the value of the 16-bit counter matches the value in the output
compare registers, the planned TCMP pin action takes place. Writing to
OCRH before writing to OCRL inhibits timer compares until OCRL is
written. Reading or writing to OCRL after the timer status register clears
the output compare flag (OCF).

Address: OCRH — $0016

Bit 7 6 5 4 3 2 1 Bit 0

Write:
OCRH7 OCRH6 OCRH5 OCRH4 OCRH3 OCRH2 OCRH1 OCRH0
Read:

Unaffected by reset

Address: OCRL — $0017

Bit 7 6 5 4 3 2 1 Bit 0

Read:

Unaffected by reset

Figure 8-7. Output Compare Registers (OCRH and OCRL)

To prevent OCF from being set between the time it is read and the time
the output compare registers are updated, use this procedure:

1. Disable interrupts by setting the I bit in the condition code register.

2. Write to OCRH. Compares are now inhibited until OCRL is written.
3. Clear bit OCF by reading timer status register (TSR).
4. Enable the output compare function by writing to OCRL.
5. Enable interrupts by clearing the I bit in the condition code register.

Advance Information MC68HC705P6A — Rev. 2.0

74 Capture/Compare Timer MOTOROLA

 Capture/Compare Timer
Timer During Wait/Halt Mode

8.5 Timer During Wait/Halt Mode

The CPU clock halts during the wait (or halt) mode, but the timer remains
active. If interrupts are enabled, a timer interrupt will cause the processor
to exit the wait mode.

8.6 Timer During Stop Mode

In the stop mode, the timer stops counting and holds the last count value
if STOP is exited by an interrupt. If STOP is exited by RESET, the
counters are forced to $FFFC. During STOP, if at least one valid input
capture edge occurs at the TCAP pins, the input capture detect circuit is
armed. This does not set any timer flags or wake up the MCU, but if an
interrupt is used to exit stop mode, there is an active input capture flag
and data from the first valid edge that occurred during the stop mode. If
reset is used to exit stop mode, then no input capture flag or data
remains, even if a valid input capture edge occurred.

MC68HC705P6A — Rev. 2.0 Advance Information

MOTOROLA Capture/Compare Timer 75

Capture/Compare Timer

Advance Information MC68HC705P6A — Rev. 2.0

76 Capture/Compare Timer MOTOROLA

Advance Information — MC68HC705P6A

Section 9. Analog Subsystem

9.1 Contents
9.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

9.3 Analog Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

9.3.1 Ratiometric Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
9.3.2 Reference Voltage (VREFH) . . . . . . . . . . . . . . . . . . . . . . . . . 78
9.3.3 Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

9.4 Conversion Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

9.5 Digital Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

9.5.1 Conversion Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
9.5.2 Internal versus External Oscillator . . . . . . . . . . . . . . . . . . . . 79
9.5.3 Multi-Channel Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

9.6 A/D Status and Control Register (ADSC) . . . . . . . . . . . . . . . . . 80

9.7 A/D Conversion Data Register (ADC). . . . . . . . . . . . . . . . . . . .82

9.8 A/D Subsystem Operation during Halt/Wait Modes . . . . . . . . . 82

9.9 A/D Subsystem Operation during Stop Mode. . . . . . . . . . . . . . 82

9.2 Introduction
The MC68HC705P6A includes a 4-channel, multiplexed input, 8-bit,
successive approximation analog-to-digital (A/D) converter. The A/D
subsystem shares its inputs with port C pins PC3–PC7.

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MOTOROLA Analog Subsystem 77

Analog Subsystem

9.3 Analog Section

The following paragraphs describe the operation and performance of
analog modules within the analog subsystem.

9.3.1 Ratiometric Conversion

The A/D converter is ratiometric, with pin VREFH supplying the high
reference voltage. Applying an input voltage equal to VREFH produces a
conversion result of $FF (full scale). Applying an input voltage equal to
VSS produces a conversion result of $00. An input voltage greater than
VREFH will convert to $FF with no overflow indication. For ratiometric
conversions, VREFH should be at the same potential as the supply
voltage being used by the analog signal being measured and referenced
to VSS.

9.3.2 Reference Voltage (VREFH)

The reference supply for the A/D converter shares pin PC7 with port C.
The low reference is tied to the VSS pin internally. VREFH can be any
voltage between VSS and VDD; however, the accuracy of conversions is
tested and guaranteed only for VREFH = VDD.

9.3.3 Accuracy and Precision

The 8-bit conversion result is accurate to within ±1 1/2 LSB, including

quantization; however, the accuracy of conversions is tested and
guaranteed only with external oscillator operation.

9.4 Conversion Process

The A/D reference inputs are applied to a precision digital-to-analog
converter. Control logic drives the D/A and the analog output is
successively compared to the selected analog input which was sampled
at the beginning of the conversion cycle. The conversion process is
monotonic and has no missing codes.

Advance Information MC68HC705P6A — Rev. 2.0

78 Analog Subsystem MOTOROLA

 Analog Subsystem
Digital Section

9.5 Digital Section

The following paragraphs describe the operation and performance of
digital modules within the analog subsystem.

9.5.1 Conversion Times

Each input conversion requires 32 internal clock cycles, which must be

at a frequency equal to or greater than 1 MHz.

9.5.2 Internal versus External Oscillator

If the internal clock is 1 MHz or greater (i.e., external oscillator 2 MHz or

greater), the internal RC oscillator must be turned off and the external
oscillator used as the conversion clock.

If the MCU internal clock frequency is less than 1 MHz (2 MHz external
oscillator), the internal RC oscillator (approximately 1.5 MHz) must be
used for the A/D converter clock. The internal RC clock is selected by
setting the ADRC bit in the ADSC register.

When the internal RC oscillator is being used, these limitations apply:

1. Since the internal RC oscillator is running asynchronously with
respect to the internal clock, the conversion complete bit (CC) in
register ADSC must be used to determine when a conversion
sequence has been completed.
2. Electrical noise will slightly degrade the accuracy of the A/D
converter. The A/D converter is synchronized to read voltages
during the quiet period of the clock driving it. Since the internal and
external clocks are not synchronized, the A/D converter will
occasionally measure an input when the external clock is making
a transition.

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MOTOROLA Analog Subsystem 79

Analog Subsystem

9.5.3 Multi-Channel Operation

An input multiplexer allows the A/D converter to select from one of four
external analog signals. Port C pins PC3 through PC6 are shared with
the inputs to the multiplexer.

9.6 A/D Status and Control Register (ADSC)

The ADSC register reports the completion of A/D conversion and
provides control over oscillator selection, analog subsystem power, and
input channel selection. See Figure 9-1.

Address: $001E

Bit 7 6 5 4 3 2 1 Bit 0

Read: CC 0 0
ADRC ADON CH2 CH1 CH0
Write:

Reset: 0 0 0 0 0 0 0 0

= Unimplemented

Figure 9-1. A/D Status and Control Register (ADSC)

CC — Conversion Complete
This read-only status bit is set when a conversion sequence has
completed and data is ready to be read from the ADC register. CC is
cleared when the ADSC is written to or when data is read from the
ADC register. Once a conversion has been started, conversions of
the selected channel will continue every 32 internal clock cycles until
the ADSC register is written to again. During continuous conversion
operation, the ADC register will be updated with new data, and the CC
bit set every 32 internal clock cycles. Also, data from the previous
conversion will be overwritten regardless of the state of the CC bit.

ADRC — RC Oscillator Control

When ADRC is set, the A/D subsystem operates from the internal RC
oscillator instead of the internal clock. The RC oscillator requires a
time, tRCON, to stabilize before accurate conversion results can be

Advance Information MC68HC705P6A — Rev. 2.0

80 Analog Subsystem MOTOROLA

 Analog Subsystem
A/D Status and Control Register (ADSC)

obtained. See 9.3.2 Reference Voltage (VREFH) for more

information.

ADON — A/D Subsystem On

When the A/D subsystem is turned on (ADON = 1), it requires a time,
tADON, to stabilize before accurate conversion results can be attained.

CH2–CH0 — Channel Select Bits

CH2, CH1, and CH0 form a 3-bit field which is used to select an input
to the A/D converter. Channels 0–3 correspond to port C input pins
PC6–PC3. Channels 4–6 are used for reference measurements.
Channel 7 is reserved. If a conversion is attempted with channel 7
selected, the result will be $00. Table 9-1 lists the inputs selected by
bits CH0-CH3.
If the ADON bit is set and an input from channels 0–4 is selected, the
corresponding port C pin’s DDR bit will be cleared (making that port
C pin an input). If the port C data register is read while the A/D is on
and one of the shared input channels is selected using bit CH0–CH2,
the corresponding port C pin will read as a logic 0. The remaining port
C pins will read normally. To digitally read a port C pin, the A/D
subsystem must be disabled (ADON = 0), or input channels 5–7 must
be selected.

Table 9-1. A/D Multiplexer Input

Channel Assignments
Channel Signal

0 AD0 — port C, bit 6

1 AD1 — port C, bit 5

2 AD2 — port C, bit 4

3 AD3 — port C, bit 3

4 VREFH — port C, bit 7

5 (VREFH + VSS)/2

6 VSS

7 Reserved for factory test

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MOTOROLA Analog Subsystem 81

Analog Subsystem

9.7 A/D Conversion Data Register (ADC)

This register contains the output of the A/D converter. See Figure 9-2.

Address: $001D

Bit 7 6 5 4 3 2 1 Bit 0

Read: AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0

Write:

Reset: Unaffected by reset

= Unimplemented

Figure 9-2. A/D Conversion Value Data Register (ADC)

9.8 A/D Subsystem Operation during Halt/Wait Modes

The A/D subsystem continues normal operation during wait and halt
modes. To decrease power consumption during wait or halt mode, the
ADON and ADRC bits in the A/D status and control register should be
cleared if the A/D subsystem is not being used.

9.9 A/D Subsystem Operation during Stop Mode

When stop mode is enabled, execution of the STOP instruction will
terminate all A/D subsystem functions. Any pending conversion is
aborted. When the oscillator resumes operation upon leaving stop
mode, a finite amount of time passes before the A/D subsystem
stabilizes sufficiently to provide conversions at its rated accuracy. The
delays built into the MC68HC705P6A when coming out of stop mode are
sufficient for this purpose. No explicit delays need to be added to the
application software.

Advance Information MC68HC705P6A — Rev. 2.0

82 Analog Subsystem MOTOROLA

Advance Information — MC68HC705P6A

Section 10. EPROM

10.1 Contents
10.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

10.3 EPROM Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

10.4 EPROM Programming Sequence. . . . . . . . . . . . . . . . . . . . . . . 84

10.5 EPROM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

10.6 EPROM Programming Register (EPROG) . . . . . . . . . . . . . . . . 84

10.7 EPROM Bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

10.8 Programming from an External Memory Device. . . . . . . . . . . . 87

10.2 Introduction
The user EPROM consists of 48 bytes of user page zero EPROM from
$0020 to $004F, 4608 bytes of user EPROM from $0100 to $12FF, the
two MOR reset values located at $1EFF and $1F00, and 16 bytes of user
vectors EPROM from $1FF0 to $1FFF. The bootloader ROM and
vectors are located from $1F01 to $1FEF.

10.3 EPROM Erasing

NOTE: Only parts packaged in a windowed package may be erased. Others are
one-time programmable and may not be erased by UV exposure.

The MC68HC705P6A can be erased by exposure to a high-intensity

ultraviolet (UV) light with a wavelength of 2537 angstroms. The
recommended dose (UV intensity multiplied by exposure time) is
15 Ws/cm2. UV lamps without shortwave filters should be used, and the

MC68HC705P6A — Rev. 2.0 Advance Information

MOTOROLA EPROM 83
EPROM

EPROM device should be positioned about one inch from the UV lamp.
An erased EPROM byte will read as $00.

10.4 EPROM Programming Sequence

The bootloader software goes through a complete write cycle of the
EPROM including the MOR. This is followed by a verify cycle which
continually branches in a loop if an error is found. A sample routine to
program a byte of EPROM is shown in Table 10-1.

NOTE: To avoid damage to the MCU, VDD must be applied to the MCU before
VPP.

10.5 EPROM Registers

Three registers are associated with the EPROM: the EPROM
programming register (EPROG) and the two mask option registers
(MOR). The EPROG register controls the actual programming of the
EPROM bytes and the MOR. The MOR registers control the six mask
options found on the ROM version of this MCU (MC68HC05P6), the
EPROM security feature, and eight additional port A interrupt options.

10.6 EPROM Programming Register (EPROG)

This register is used to program the EPROM array. Only the ELAT and
EPGM bits are available. Table 10-1 shows the location of each bit in the
EPROG register and the state of these bits coming out of reset. All the
bits in the EPROG register are cleared by reset.

Advance Information MC68HC705P6A — Rev. 2.0

84 EPROM MOTOROLA
 EPROM
EPROM Programming Register (EPROG)

Address $001C

Bit 7 6 5 4 3 2 1 Bit 0

Read: 0 0 0 0 0 0
ELAT EPGM
Write:

Reset: 0 0 0 0 0 0 0 0

= Unimplemented

Figure 10-1. EPROM Programming Register (EPROG)

EPGM — EPROM Program Control

If the EPGM bit is set, programming power is applied to the EPROM
array. If the EPGM bit is cleared, programming power is removed from
the EPROM array. The EPGM bit cannot be set unless the ELAT bit
is set already.
Whenever the ELAT bit is cleared, the EPGM bit is cleared also. Both
the EPGM and the ELAT bit cannot be set using the same write
instruction. Any attempt to set both the EPGM and ELAT bit on the
same write instruction cycle will result in the ELAT bit being set and
the EPGM bit being cleared. The EPGM bit is a read-write bit and can
be read at any time. The EPGM bit is cleared by reset.

ELAT— EPROM Latch Control

If the ELAT bit is set, the EPROM address and data bus are
configured for programming to the array. If the ELAT bit is cleared, the
EPROM address and data bus are configured for normal reading of
data from the array. When the ELAT bit is set, the address and data
bus are latched in the EPROM array when a subsequent write to the
array is made. Data in the EPROM array cannot be read if the ELAT
bit is set.
Whenever the ELAT bit is cleared, the EPGM bit is cleared also. Both
the EPGM and the ELAT bit cannot be set using the same write
instruction. Any attempt to set both the EPGM and ELAT bit on the
same write instruction cycle will result in the ELAT bit being set and
the EPGM bit being cleared. The ELAT bit is a read-write bit and can
be read at any time. The ELAT bit is cleared by reset.

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MOTOROLA EPROM 85
EPROM

To program a byte of EPROM, manipulate the EPROG register as

follows:
1. Set the ELAT bit in the EPROG register.
2. Write the desired data to the desired EPROM address.
3. Set the EPGM bit in the EPROG register for the specified
programming time, tEPGM.
4. Clear the ELAT and EPGM bits in the EPROG register.

This sequence is also shown in the sample program listing in Table 10-1.

Table 10-1. EPROM Programming Routine

001C EPROG EQU $1C PROGRAMMING REG
0055 DATA EQU $55 DATA VALUE
0700 EPROM EQU $700 A SAMPLE EPROM ADX
0000 EPGM EQU $00 EPGM BIT IN EPROG REG

00D0 ORG $D0

00D0 A6 02 LDA #$04 SET LAT BIT IN EPROG

00D2 B7 1C STA EPROG
00D4 A6 55 LDA #DATA DATA BYTE
00D6 C7 07 00 STA EPROM WRITE IT TO EPROM LOC
00D9 10 1C BSET EPGM, EPROG TURN ON PGM VOLTAGE
00DB AD 03 BSR DELAY WAIT 4 ms MINIMUM
00DD 3F 1C CLR EPROG CLR LAT AND PGM BITS
00DF 81 RTS

10.7 EPROM Bootloader

Three port pins are associated with bootloader control functions: PC3,
PC4, and PC6. Table 10-2 summarizes their functionality.

Table 10-2. Bootloader Control Pins

PC6 PC4 PC3 Mode

1 1 1 Program/verify

1 1 0 Verify only

1 0 0 Dump MCU EPROM to port A

Advance Information MC68HC705P6A — Rev. 2.0

86 EPROM MOTOROLA
 EPROM
Programming from an External Memory Device

10.8 Programming from an External Memory Device

In this programming mode, PC5 must be connected to VSS. PC4 and
PC3 are used to select the programming mode. The programming circuit
shown in Figure 10-2 uses an external 12-bit counter to address the
memory device containing the code to be copied. This counter requires
a clock and a reset function. The 12-bit counter can address up to
4 Kbytes of memory, which means that a port pin has to be used to
address the remaining 4 K of the 8-K memory space.

The following procedure explains how to use the programming circuit

shown in Figure 10-2 to copy a user program from an external memory
device into the MCU’s EPROM:

1. Program a 2764-type EPROM device with the desired instructions

and data. Code programmed into the 2764 must appear at the
same addresses desired in the MC68HC705P6A. Therefore, the
page zero code must start at $0020 and end at $004F, the main
body of code must start at $0100 and end at $12FF, and the user
vectors must start at $1FF0 and end at $1FFF.

NOTE: The MOR data must appear at $1EFF and $1F00.

2. Install the programmed 2764 device into the programming circuit.

3. Install the MC68HC705P6A to be programmed into the
programming circuit.
4. Set the PROGRAM and/or VERIFY switches for the desired
operation (an open switch is the active state) and close the
RESET switch to hold the MCU in reset.
5. Make sure that the VPP source is OFF.
6. Apply the VDD source to the programming circuit.
7. Apply the VPP source to the programming circuit.
8. Open the RESET switch to allow the MCU to come out of reset
and begin execution of the software in its internal bootloader
ROM.

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MOTOROLA EPROM 87
EPROM

9. Wait for programming and/or verification to complete (about 40

seconds). The PROGRAM LED will light during programming and
the VERIFY LED will light if verification was requested and was
successful.
10. When complete, close the RESET switch to force the MCU into the
reset state.
11. Turn off the VPP source.
12. Turn off the VDD source.
13. Remove device(s).

Advance Information MC68HC705P6A — Rev. 2.0

88 EPROM MOTOROLA
 EPROM
Programming from an External Memory Device

PROGRAM 2764 TYPE EPROM

INSTALL EPROM INTO PROGRAMMER

N
PROGRAMMING?
INSTALL MC68HC705P6A INTO PROGRAMMER

WAIT FOR PROGRAMMING LED TO

N TURN ON AND OFF.
PROGRAMMING?

OPEN PROGRAM SWITCH CLOSE PROGRAM SWITCH N

VERIFYING?

N WAIT FOR 30 SECONDS

VERIFYING?

OPEN VERIFY SWITCH CLOSE VERIFY SWITCH

N
IS VERIFY
LED LIT?
CLOSE RESET SWITCH
Y

MAKE SURE VPP IS OFF VERIFICATION FAILED VERIFICATION COMPLETE

TURN VDD ON
CLOSE RESET SWITCH

TURN VPP ON
TURN OFF VPP

OPEN RESET SWITCH

TURN OFF VDD

REMOVE DEVICES

Figure 10-2. MC68HC705P6A EPROM Programming Flowchart

MC68HC705P6A — Rev. 2.0 Advance Information

MOTOROLA EPROM 89
EPROM

V
DD
MC68HC705P6A

VPP IRQ/VPP 10 kΩ
2764 MC74HC4040
PD7/TCAP V
DD
OSC1 PGM
2 MHz
PB5 A12 A11 Q12
OSC2
A10 Q11
A9 Q10
10 MΩ
20 pF 20 pF PA7 D7
A8 Q9
PA6 D6
A7 Q8
PA5 D5
A6 Q7
PA4 D4
V A5 Q6
DD
PA3 D3
A4 Q5
10 kΩ PA2 D2
A3 Q4
PA1 D1
RESET A2 Q3
RESET PA0 D0
A1 Q2
1 µF
V CE A0 Q1
DD
OE
V RST CLK
DD
10 kΩ
PC6

PC1
PROG
PB7
PC2
330 Ω VDD VDD

10 kΩ 10 kΩ
VERF
PB6 PGM
PC3 VDD = 5.0 V
330 Ω
VFY
PC5 PC4 VPP = 16.5 V

Figure 10-3. MC68HC705P6A EPROM Programming Schematic Diagram

Advance Information MC68HC705P6A — Rev. 2.0

90 EPROM MOTOROLA
Advance Information — MC68HC705P6A

Section 11. Mask Option Register (MOR)

11.1 Contents
11.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

11.3 Mask Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

11.4 MOR Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

11.2 Introduction
The mask option register (MOR) contains two bytes of EPROM used to
enable or disable each of the features controlled by mask options on the
MC68HC05P6 (a ROM version of the MC68HC705P6A).

The seven programmable options on the MC68HC705P6A are:

1. COP watchdog timer (enable or disable)
2. IRQ triggering (edge- or edge- and level-sensitive)
3. SIOP data bit order (most significant bit or least significant bit first)
4. SIOP clock rate (OSC divided by 8, 16, 32, or 64)
5. Stop instruction mode (stop mode or halt mode)
6. Secure EPROM from external reading
7. Keyscan interrupt/pullups on PA0–PA7

11.3 Mask Option Register

Mask options are programmed into the mask option register (MOR) by
the firmware in the bootloader ROM. See Figure 11-1.

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Mask Option Register (MOR)

Address: $1EFF

Bit 7 6 5 4 3 2 1 Bit 0

Read:
PA7PU PA6PU PA5PU PA4PU PA3PU PA2PU PA1PU PA0PU
Write:

Erased State: 0 0 0 0 0 0 0 0

Address: $1F00

Bit 7 6 5 4 3 2 1 Bit 0

Read:
SECURE SWAIT SPR1 SPR0 LSBF LEVEL COP
Write:

Erased State: 0 0 0 0 0 0 0 0

= Unimplemented

Figure 11-1. Mask Option Register (MOR)

COP — COP Watchdog Enable

Setting the COP bit will enable the COP watchdog timer. The COP will
reset the MCU if the timeout period is reached before the COP
watchdog timer is cleared by the application software and the voltage
applied to the IRQ/VPP pin is between VSS and VDD. Clearing the
COP bit will disable the COP watchdog timer regardless of the voltage
applied to the IRQ/VPP pin.

LEVEL — IRQ Edge Sensitivity

If the LEVEL bit is clear, the IRQ/VPP pin will only be sensitive to the
falling edge of the signal applied to the IRQ/VPP pin. If the LEVEL bit
is set, the IRQ/VPP pin will be sensitive to both the falling edge of the
input signal and the logic low level of the input signal on the IRQ/VPP
pin.

LSBF — SIOP Least Significant Bit First

If the LSBF bit is set, the serial data to and from the SIOP will be
transferred least significant bit first. If the LSBF bit is clear, the serial
data to and from the SIOP will be transferred most significant bit first.

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 Mask Option Register (MOR)
Mask Option Register

SPR0 and SPR1 — SIOP Clock Rate

The SPR0 and SPR1 bits determine the clock rate used to transfer the
serial data to and from the SIOP. The various clock rates available are
given in Table 11-1.

Table 11-1. SIOP Clock Rate

SPR1 SPR0 SIOP Master Clock

0 0 fosc ÷ 64

0 1 fosc ÷ 32

1 0 fosc ÷ 16

1 1 fosc ÷ 8

SWAIT — STOP Instruction Mode

Setting the SWAIT bit will prevent the STOP instruction from stopping
the on-board oscillator. Clearing the SWAIT bit will permit the STOP
instruction to stop the on-board oscillator and place the MCU in stop
mode. Executing the STOP instruction when SWAIT is set will place
the MCU in halt mode. See 3.5.1 STOP Instruction for additional
information.

SECURE — Security State(1)

If SECURE bit is set, the EPROM is locked.

PA(0:7)PU — Port A Pullups/Interrupt Enable/Disable

If any PA(0:7)PU is selected, that pullup/interrupt is enabled. The
interrupt sensitivity will be selected via the LEVEL bit in the same way
as the IRQ pin.

NOTE: The port A pullup/interrupt function is NOT available on the ROM device,
MC68HC05P6.

1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or

copying the EPROM/OTPROM difficult for unauthorized users.

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Mask Option Register (MOR)

11.4 MOR Programming

The contents of the MOR should be programmed in bootloader mode
using the hardware shown in Figure 10-2. In order to allow
programming, all the implemented bits in the MOR are essentially read-
write bits in bootloader mode as shown in Figure 11-1.

The programming of the MOR is the same as user EPROM.

1. Set the ELAT bit in the EPROG register.
2. Write the desired data to the desired MOR address.
3. Set the EPGM bit in the EPROG.
4. Wait for the programming time (tEPGM).
5. Clear the ELAT and EPGM bits in the EPROG.
6. Remove the programming voltage from the IRQ/VPP pin.

A sample routine to program a byte of EPROM is shown in Table 11-2.

Once the MOR bits have been programmed, the options are not loaded
into the MOR registers until the part is reset.

Table 11-2. MOR Programming Routine

001C EPROG EQU $1C PROGRAMMING REG
00FF DATA2 EQU $FF SAMPLE MOR VALUES
0023 DATA1 EQU #23
1EFF MOR2 EQU $1EFF MOPR ADDRESSES
1F00 MOR1 EQU $1F00
0000 EPGM EQU $00 EPGM BIT IN EPROG REG

00E0 ORG $E0

00E0 A6 04 LDA #$04 SET ELAT BIT

00E2 B7 1C STA EPROG IN EPGM REG AT $1C
00E4 A6 FF LDA #DATA2 DATA BYTE
00E6 C7 1E FF STA MOR2 WRITE IT TO MOR LOC
00E9 12 1C BSET EPGM,EPROG TURN ON PGM VOLTAGE
00EB AD 03 BSR DELAY WAIT 4 ms MINIMUM
00ED 3F 1C CLR EPROG CLR EPGM REGISTER
00EF 81 RTS

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Section 12. Central Processor Unit (CPU) Core

12.1 Contents
12.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

12.3 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
12.3.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
12.3.2 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
12.3.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
12.3.4 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
12.3.5 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

12.2 Introduction
The MC68HC705P6A has an 8-K memory map. Therefore, it uses only
the lower 13 bits of the address bus. In the following discussion, the
upper three bits of the address bus can be ignored. Also, the STOP
instruction can be modified to place the MCU in either the normal stop
mode or the halt mode by means of a MOR bit. All other instructions and
registers behave as described in this section.

12.3 Registers
The MCU contains five registers which are hard-wired within the CPU
and are not part of the memory map. These five registers are shown in
Figure 12-1 and are described in the following paragraphs.

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Central Processor Unit (CPU) Core

7 6 5 4 3 2 1 0

ACCUMULATOR A

INDEX REGISTER X
15 14 13 12 11 10 9 8

0 0 0 0 0 0 0 0 1 1 STACK POINTER SP

PROGRAM COUNTER PC

CONDITION CODE REGISTER 1 1 1 H I N Z C CC

HALF-CARRY BIT (FROM BIT 3)

INTERRUPT MASK
NEGATIVE BIT
ZERO BIT
CARRY BIT

Figure 12-1. MC68HC05 Programming Model

12.3.1 Accumulator

The accumulator is a general-purpose 8-bit register as shown in Figure

12-1. The CPU uses the accumulator to hold operands and results of
arithmetic calculations or non-arithmetic operations. The accumulator is
unaffected by a reset of the device.

12.3.2 Index Register

The index register shown in Figure 12-1 is an 8-bit register that can
perform two functions:
• Indexed addressing
• Temporary storage

In indexed addressing with no offset, the index register contains the low
byte of the operand address, and the high byte is assumed to be $00. In
indexed addressing with an 8-bit offset, the CPU finds the operand
address by adding the index register contents to an 8-bit immediate
value. In indexed addressing with a 16-bit offset, the CPU finds the

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 Central Processor Unit (CPU) Core
Registers

operand address by adding the index register contents to a 16-bit

immediate value.

The index register can also serve as an auxiliary accumulator for

temporary storage. The index register is unaffected by a reset of the
device.

12.3.3 Stack Pointer

The stack pointer shown in Figure 12-1 is a 16-bit register internally. In

devices with memory maps less than 64 Kbytes, the unimplemented
upper address lines are ignored. The stack pointer contains the address
of the next free location on the stack. During a reset or the reset stack
pointer (RSP) instruction, the stack pointer is set to $00FF. The stack
pointer is then decremented as data is pushed onto the stack and
incremented as data is pulled from the stack.

When accessing memory, the 10 most significant bits are permanently

set to 0000000011. The six least significant register bits are appended
to these 10 fixed bits to produce an address within the range of $00FF
to $00C0. Subroutines and interrupts may use up to 64 ($40) locations.
If 64 locations are exceeded, the stack pointer wraps around and writes
over the previously stored information. A subroutine call occupies two
locations on the stack and an interrupt uses five locations.

12.3.4 Program Counter

The program counter shown in Figure 12-1 is a 16-bit register internally.

In devices with memory maps less than 64 Kbytes, the unimplemented
upper address lines are ignored. The program counter contains the
address of the next instruction or operand to be fetched.

Normally, the address in the program counter increments to the next

sequential memory location every time an instruction or operand is
fetched. Jump, branch, and interrupt operations load the program
counter with an address other than that of the next sequential location.

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12.3.5 Condition Code Register

The CCR shown in Figure 12-1 is a 5-bit register in which four bits are
used to indicate the results of the instruction just executed. The fifth bit
is the interrupt mask. These bits can be individually tested by a program,
and specific actions can be taken as a result of their state. The condition
code register should be thought of as having three additional upper bits
that are always ones. Only the interrupt mask is affected by a reset of the
device. The following paragraphs explain the functions of the lower five
bits of the condition code register.

H — Half Carry Bit

When the half-carry bit is set, it means that a carry occurred between
bits 3 and 4 of the accumulator during the last ADD or ADC (add with
carry) operation. The half-carry bit is required for binary-coded
decimal (BCD) arithmetic operations.

I — Interrupt Mask Bit

When the interrupt mask is set, the internal and external interrupts are
disabled. Interrupts are enabled when the interrupt mask is cleared.
When an interrupt occurs, the interrupt mask is automatically set after
the CPU registers are saved on the stack, but before the interrupt
vector is fetched. If an interrupt request occurs while the interrupt
mask is set, the interrupt request is latched. Normally, the interrupt is
processed as soon as the interrupt mask is cleared.
A return from interrupt (RTI) instruction pulls the CPU registers from
the stack, restoring the interrupt mask to its state before the interrupt
was encountered. After any reset, the interrupt mask is set and can
only be cleared by the clear I bit (CLI), STOP, or WAIT instructions.

N — Negative Bit
The negative bit is set when the result of the last arithmetic operation,
logical operation, or data manipulation was negative. (Bit 7 of the
result was a logic one.)
The negative bit can also be used to check an often-tested flag by
assigning the flag to bit 7 of a register or memory location. Loading
the accumulator with the contents of that register or location then sets
or clears the negative bit according to the state of the flag.

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Registers

Z — Zero Bit
The zero bit is set when the result of the last arithmetic operation,
logical operation, data manipulation, or data load operation was zero.

C — Carry/Borrow Bit
The carry/borrow bit is set when a carry out of bit 7 of the accumulator
occurred during the last arithmetic operation, logical operation, or
data manipulation. The carry/borrow bit is also set or cleared during
bit test and branch instructions and during shifts and rotates. This bit
is not set by an INC or DEC instruction.

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Central Processor Unit (CPU) Core

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Section 13. Instruction Set

13.1 Contents
13.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

13.3 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

13.3.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
13.3.2 Immediate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
13.3.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
13.3.4 Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
13.3.5 Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
13.3.6 Indexed, 8-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
13.3.7 Indexed,16-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
13.3.8 Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

13.4 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

13.4.1 Register/Memory Instructions. . . . . . . . . . . . . . . . . . . . . . .105
13.4.2 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . 106
13.4.3 Jump/Branch Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . 107
13.4.4 Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . .109
13.4.5 Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
13.5 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

13.6 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

13.2 Introduction
The MCU instruction set has 62 instructions and uses eight addressing
modes. The instructions include all those of the M146805 CMOS Family
plus one more: the unsigned multiply (MUL) instruction. The MUL
instruction allows unsigned multiplication of the contents of the
accumulator (A) and the index register (X). The high-order product is

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Instruction Set

stored in the index register, and the low-order product is stored in the
accumulator.

13.3 Addressing Modes

The CPU uses eight addressing modes for flexibility in accessing data.
The addressing modes provide eight different ways for the CPU to find
the data required to execute an instruction. The eight addressing modes
are:
• Inherent
• Immediate
• Direct
• Extended
• Indexed, no offset
• Indexed, 8-bit offset
• Indexed, 16-bit offset
• Relative

13.3.1 Inherent

Inherent instructions are those that have no operand, such as return

from interrupt (RTI) and stop (STOP). Some of the inherent instructions
act on data in the CPU registers, such as set carry flag (SEC) and
increment accumulator (INCA). Inherent instructions require no operand
address and are one byte long.

13.3.2 Immediate

Immediate instructions are those that contain a value to be used in an

operation with the value in the accumulator or index register. Immediate
instructions require no operand address and are two bytes long. The
opcode is the first byte, and the immediate data value is the second byte.

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 Instruction Set
Addressing Modes

13.3.3 Direct

Direct instructions can access any of the first 256 memory locations with
two bytes. The first byte is the opcode, and the second is the low byte of
the operand address. In direct addressing, the CPU automatically uses
$00 as the high byte of the operand address.

13.3.4 Extended

Extended instructions use three bytes and can access any address in
memory. The first byte is the opcode; the second and third bytes are the
high and low bytes of the operand address.

When using the Motorola assembler, the programmer does not need to
specify whether an instruction is direct or extended. The assembler
automatically selects the shortest form of the instruction.

13.3.5 Indexed, No Offset

Indexed instructions with no offset are 1-byte instructions that can

access data with variable addresses within the first 256 memory
locations. The index register contains the low byte of the effective
address of the operand. The CPU automatically uses $00 as the high
byte, so these instructions can address locations $0000–$00FF.

Indexed, no offset instructions are often used to move a pointer through

a table or to hold the address of a frequently used RAM or I/O location.

13.3.6 Indexed, 8-Bit Offset

Indexed, 8-bit offset instructions are 2-byte instructions that can access
data with variable addresses within the first 511 memory locations. The
CPU adds the unsigned byte in the index register to the unsigned byte
following the opcode. The sum is the effective address of the operand.
These instructions can access locations $0000–$01FE.

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Indexed 8-bit offset instructions are useful for selecting the kth element
in an n-element table. The table can begin anywhere within the first 256
memory locations and could extend as far as location 510 ($01FE). The
k value is typically in the index register, and the address of the beginning
of the table is in the byte following the opcode.

13.3.7 Indexed,16-Bit Offset

Indexed, 16-bit offset instructions are 3-byte instructions that can access
data with variable addresses at any location in memory. The CPU adds
the unsigned byte in the index register to the two unsigned bytes
following the opcode. The sum is the effective address of the operand.
The first byte after the opcode is the high byte of the 16-bit offset; the
second byte is the low byte of the offset.

Indexed, 16-bit offset instructions are useful for selecting the kth element
in an n-element table anywhere in memory.

As with direct and extended addressing, the Motorola assembler

determines the shortest form of indexed addressing.

13.3.8 Relative

Relative addressing is only for branch instructions. If the branch

condition is true, the CPU finds the effective branch destination by
adding the signed byte following the opcode to the contents of the
program counter. If the branch condition is not true, the CPU goes to the
next instruction. The offset is a signed, two’s complement byte that gives
a branching range of –128 to +127 bytes from the address of the next
location after the branch instruction.

When using the Motorola assembler, the programmer does not need to
calculate the offset, because the assembler determines the proper offset
and verifies that it is within the span of the branch.

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 Instruction Set
Instruction Types

13.4 Instruction Types

The MCU instructions fall into the following five categories:
• Register/memory instructions
• Read-modify-write instructions
• Jump/branch instructions
• Bit manipulation instructions
• Control instructions

13.4.1 Register/Memory Instructions

These instructions operate on CPU registers and memory locations.

Most of them use two operands. One operand is in either the
accumulator or the index register. The CPU finds the other operand in
memory.

Table 13-1. Register/Memory Instructions

Instruction Mnemonic
Add Memory Byte and Carry Bit to Accumulator ADC
Add Memory Byte to Accumulator ADD
AND Memory Byte with Accumulator AND
Bit Test Accumulator BIT
Compare Accumulator CMP
Compare Index Register with Memory Byte CPX
EXCLUSIVE OR Accumulator with Memory Byte EOR
Load Accumulator with Memory Byte LDA
Load Index Register with Memory Byte LDX
Multiply MUL
OR Accumulator with Memory Byte ORA
Subtract Memory Byte and Carry Bit from Accumulator SBC
Store Accumulator in Memory STA
Store Index Register in Memory STX
Subtract Memory Byte from Accumulator SUB

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13.4.2 Read-Modify-Write Instructions

These instructions read a memory location or a register, modify its

contents, and write the modified value back to the memory location or to
the register.

NOTE: Do not use read modify-write operations on write-only registers.

Table 13-2. Read-Modify-Write Instructions

Instruction Mnemonic

Arithmetic Shift Left (Same as LSL) ASL

Arithmetic Shift Right ASR

Bit Clear BCLR (1)

Bit Set BSET(1)

Clear Register CLR

Complement (One’s Complement) COM

Decrement DEC

Increment INC

Logical Shift Left (Same as ASL) LSL

Logical Shift Right LSR

Negate (Two’s Complement) NEG

Rotate Left through Carry Bit ROL

Rotate Right through Carry Bit ROR

Test for Negative or Zero TST(2)

1. Unlike other read-modify-write instructions, BCLR and
BSET use only direct addressing.
2. TST is an exception to the read-modify-write sequence
because it does not write a replacement value.

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 Instruction Set
Instruction Types

13.4.3 Jump/Branch Instructions

Jump instructions allow the CPU to interrupt the normal sequence of the
program counter. The unconditional jump instruction (JMP) and the
jump-to-subroutine instruction (JSR) have no register operand. Branch
instructions allow the CPU to interrupt the normal sequence of the
program counter when a test condition is met. If the test condition is not
met, the branch is not performed.

The BRCLR and BRSET instructions cause a branch based on the state
of any readable bit in the first 256 memory locations. These 3-byte
instructions use a combination of direct addressing and relative
addressing. The direct address of the byte to be tested is in the byte
following the opcode. The third byte is the signed offset byte. The CPU
finds the effective branch destination by adding the third byte to the
program counter if the specified bit tests true. The bit to be tested and its
condition (set or clear) is part of the opcode. The span of branching is
from –128 to +127 from the address of the next location after the branch
instruction. The CPU also transfers the tested bit to the carry/borrow bit
of the condition code register.

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Table 13-3. Jump and Branch Instructions

Instruction Mnemonic
Branch if Carry Bit Clear BCC
Branch if Carry Bit Set BCS
Branch if Equal BEQ
Branch if Half-Carry Bit Clear BHCC
Branch if Half-Carry Bit Set BHCS
Branch if Higher BHI
Branch if Higher or Same BHS
Branch if IRQ Pin High BIH
Branch if IRQ Pin Low BIL
Branch if Lower BLO
Branch if Lower or Same BLS
Branch if Interrupt Mask Clear BMC
Branch if Minus BMI
Branch if Interrupt Mask Set BMS
Branch if Not Equal BNE
Branch if Plus BPL
Branch Always BRA
Branch if Bit Clear BRCLR
Branch Never BRN
Branch if Bit Set BRSET
Branch to Subroutine BSR
Unconditional Jump JMP
Jump to Subroutine JSR

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 Instruction Set
Instruction Types

13.4.4 Bit Manipulation Instructions

The CPU can set or clear any writable bit in the first 256 bytes of
memory, which includes I/O registers and on-chip RAM locations. The
CPU can also test and branch based on the state of any bit in any of the
first 256 memory locations.

Table 13-4. Bit Manipulation Instructions

Instruction Mnemonic
Bit Clear BCLR
Branch if Bit Clear BRCLR
Branch if Bit Set BRSET
Bit Set BSET

13.4.5 Control Instructions

These instructions act on CPU registers and control CPU operation

during program execution.

Table 13-5. Control Instructions

Instruction Mnemonic
Clear Carry Bit CLC
Clear Interrupt Mask CLI
No Operation NOP
Reset Stack Pointer RSP
Return from Interrupt RTI
Return from Subroutine RTS
Set Carry Bit SEC
Set Interrupt Mask SEI
Stop Oscillator and Enable IRQ Pin STOP
Software Interrupt SWI
Transfer Accumulator to Index Register TAX
Transfer Index Register to Accumulator TXA
Stop CPU Clock and Enable Interrupts WAIT

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13.5 Instruction Set Summary

Table 13-6. Instruction Set Summary (Sheet 1 of 6)

Operand
Address
Effect on

Opcode

Cycles
Mode
Source Operation Description CCR
Form
H I N Z C
ADC #opr IMM A9 ii 2
ADC opr DIR B9 dd 3
ADC opr EXT C9 hh ll 4
ADC opr,X
Add with Carry A ← (A) + (M) + (C)  —    IX2 D9 ee ff 5
ADC opr,X IX1 E9 ff 4
ADC ,X IX F9 3

ADD #opr IMM AB ii 2

ADD opr DIR BB dd 3
ADD opr EXT CB hh ll 4
ADD opr,X
Add without Carry A ← (A) + (M)  —    IX2 DB ee ff 5
ADD opr,X IX1 EB ff 4
ADD ,X IX FB 3

AND #opr IMM A4 ii 2

AND opr DIR B4 dd 3
AND opr EXT C4 hh ll 4
AND opr,X
Logical AND A ← (A) ∧ (M) — —   —
IX2 D4 ee ff 5
AND opr,X IX1 E4 ff 4
AND ,X IX F4 3

ASL opr DIR 38 dd 5

ASLA INH 48 3
ASLX Arithmetic Shift Left (Same as LSL) C 0 — —    INH 58 3
ASL opr,X b7 b0 IX1 68 ff 6
ASL ,X IX 78 5

ASR opr DIR 37 dd 5

ASRA INH 47 3
ASRX Arithmetic Shift Right C — —    INH 57 3
ASR opr,X b7 b0 IX1 67 ff 6
ASR ,X IX 77 5

BCC rel Branch if Carry Bit Clear PC ← (PC) + 2 + rel ? C = 0 — — — — — REL 24 rr 3

DIR (b0) 11 dd 5
DIR (b1) 13 dd 5
DIR (b2) 15 dd 5
DIR (b3) 17 dd 5
BCLR n opr Clear Bit n Mn ← 0 — — — — —
DIR (b4) 19 dd 5
DIR (b5) 1B dd 5
DIR (b6) 1D dd 5
DIR (b7) 1F dd 5
BCS rel Branch if Carry Bit Set (Same as BLO) PC ← (PC) + 2 + rel ? C = 1 — — — — — REL 25 rr 3
BEQ rel Branch if Equal PC ← (PC) + 2 + rel ? Z = 1 — — — — — REL 27 rr 3
BHCC rel Branch if Half-Carry Bit Clear PC ← (PC) + 2 + rel ? H = 0 — — — — — REL 28 rr 3
BHCS rel Branch if Half-Carry Bit Set PC ← (PC) + 2 + rel ? H = 1 — — — — — REL 29 rr 3
BHI rel Branch if Higher PC ← (PC) + 2 + rel ? C ∨ Z = 0 — — — — — REL 22 rr 3
BHS rel Branch if Higher or Same PC ← (PC) + 2 + rel ? C = 0 — — — — — REL 24 rr 3

Advance Information MC68HC705P6A — Rev. 2.0

110 Instruction Set MOTOROLA

 Instruction Set
Instruction Set Summary

Table 13-6. Instruction Set Summary (Sheet 2 of 6)

Operand
Address
Effect on

Opcode

Cycles
Mode
Source CCR
Operation Description
Form
H I N Z C
BIH rel Branch if IRQ Pin High PC ← (PC) + 2 + rel ? IRQ = 1 — — — — — REL 2F rr 3
BIL rel Branch if IRQ Pin Low PC ← (PC) + 2 + rel ? IRQ = 0 — — — — — REL 2E rr 3
BIT #opr IMM A5 ii 2
BIT opr DIR B5 dd 3
BIT opr EXT C5 hh ll 4
BIT opr,X
Bit Test Accumulator with Memory Byte (A) ∧ (M) — —   —
IX2 D5 ee ff 5
BIT opr,X IX1 E5 ff 4
BIT ,X IX F5 3
BLO rel Branch if Lower (Same as BCS) PC ← (PC) + 2 + rel ? C = 1 — — — — — REL 25 rr 3
BLS rel Branch if Lower or Same PC ← (PC) + 2 + rel ? C ∨ Z = 1 — — — — — REL 23 rr 3
BMC rel Branch if Interrupt Mask Clear PC ← (PC) + 2 + rel ? I = 0 — — — — — REL 2C rr 3
BMI rel Branch if Minus PC ← (PC) + 2 + rel ? N = 1 — — — — — REL 2B rr 3
BMS rel Branch if Interrupt Mask Set PC ← (PC) + 2 + rel ? I = 1 — — — — — REL 2D rr 3
BNE rel Branch if Not Equal PC ← (PC) + 2 + rel ? Z = 0 — — — — — REL 26 rr 3
BPL rel Branch if Plus PC ← (PC) + 2 + rel ? N = 0 — — — — — REL 2A rr 3
BRA rel Branch Always PC ← (PC) + 2 + rel ? 1 = 1 — — — — — REL 20 rr 3
DIR (b0) 01 dd rr 5
DIR (b1) 03 dd rr 5
DIR (b2) 05 dd rr 5
DIR (b3) 07 dd rr 5
BRCLR n opr rel Branch if Bit n Clear PC ← (PC) + 2 + rel ? Mn = 0 — — — — 
DIR (b4) 09 dd rr 5
DIR (b5) 0B dd rr 5
DIR (b6) 0D dd rr 5
DIR (b7) 0F dd rr 5
BRN rel Branch Never PC ← (PC) + 2 + rel ? 1 = 0 — — — — — REL 21 rr 3
DIR (b0) 00 dd rr 5
DIR (b1) 02 dd rr 5
DIR (b2) 04 dd rr 5
DIR (b3) 06 dd rr 5
BRSET n opr rel Branch if Bit n Set PC ← (PC) + 2 + rel ? Mn = 1 — — — —  DIR (b4) 08 dd rr 5
DIR (b5) 0A dd rr 5
DIR (b6) 0C dd rr 5
DIR (b7) 0E dd rr 5
DIR (b0) 10 dd 5
DIR (b1) 12 dd 5
DIR (b2) 14 dd 5
DIR (b3) 16 dd 5
BSET n opr Set Bit n Mn ← 1 — — — — —
DIR (b4) 18 dd 5
DIR (b5) 1A dd 5
DIR (b6) 1C dd 5
DIR (b7) 1E dd 5
PC ← (PC) + 2; push (PCL)
SP ← (SP) – 1; push (PCH)
BSR rel Branch to Subroutine — — — — — REL AD rr 6
SP ← (SP) – 1
PC ← (PC) + rel
CLC Clear Carry Bit C←0 — — — — 0 INH 98 2

CLI Clear Interrupt Mask I←0 — 0 — — — INH 9A 2

MC68HC705P6A — Rev. 2.0 Advance Information

MOTOROLA Instruction Set 111

Instruction Set

Table 13-6. Instruction Set Summary (Sheet 3 of 6)

Operand
Address
Effect on

Opcode

Cycles
Mode
Source CCR
Operation Description
Form
H I N Z C
CLR opr M ← $00 DIR 3F dd 5
CLRA A ← $00 INH 4F 3
CLRX Clear Byte X ← $00 — — 0 1 — INH 5F 3
CLR opr,X M ← $00 IX1 6F ff 6
CLR ,X M ← $00 IX 7F 5

CMP #opr IMM A1 ii 2

CMP opr DIR B1 dd 3
CMP opr EXT C1 hh ll 4
CMP opr,X
Compare Accumulator with Memory Byte (A) – (M) — —    IX2 D1 ee ff 5
CMP opr,X IX1 E1 ff 4
CMP ,X IX F1 3

COM opr M ← (M) = $FF – (M) DIR 33 dd 5

COMA A ← ( A) = $FF – (A) INH 43 3
COMX Complement Byte (One’s Complement) X ← ( X) = $FF – (X) — —   1 INH 53 3
COM opr,X M ← (M) = $FF – (M) IX1 63 ff 6
COM ,X IX 73 5
M ← (M) = $FF – (M)
CPX #opr IMM A3 ii 2
CPX opr DIR B3 dd 3
CPX opr EXT C3 hh ll 4
CPX opr,X
Compare Index Register with Memory Byte (X) – (M) — —    IX2 D3 ee ff 5
CPX opr,X IX1 E3 ff 4
CPX ,X IX F3 3

DEC opr M← (M) – 1 DIR 3A dd 5

DECA A← (A) – 1 INH 4A 3
DECX Decrement Byte X← (X) – 1 — —   — INH 5A 3
DEC opr,X M← (M) – 1 IX1 6A ff 6
DEC ,X M← (M) – 1 IX 7A 5

EOR #opr IMM A8 ii 2

EOR opr DIR B8 dd 3
EOR opr EXCLUSIVE OR Accumulator with Memory EXT C8 hh ll 4
EOR opr,X Byte
A ← (A) ⊕ (M) — —   —
IX2 D8 ee ff 5
EOR opr,X IX1 E8 ff 4
EOR ,X IX F8 3

INC opr M ← (M) + 1 DIR 3C dd 5

INCA A ← (A) + 1 INH 4C 3
INCX Increment Byte X ← (X) + 1 — —   — INH 5C 3
INC opr,X M ← (M) + 1 IX1 6C ff 6
INC ,X M ← (M) + 1 IX 7C 5

JMP opr DIR BC dd 2

JMP opr EXT CC hh ll 3
JMP opr,X Unconditional Jump PC ← Jump Address — — — — — IX2 DC ee ff 4
JMP opr,X IX1 EC ff 3
JMP ,X IX FC 2

Advance Information MC68HC705P6A — Rev. 2.0

112 Instruction Set MOTOROLA

 Instruction Set
Instruction Set Summary

Table 13-6. Instruction Set Summary (Sheet 4 of 6)

Operand
Address
Effect on

Opcode

Cycles
Mode
Source CCR
Operation Description
Form
H I N Z C
JSR opr DIR BD dd 5
PC ← (PC) + n (n = 1, 2, or 3)
JSR opr EXT CD hh ll 6
Push (PCL); SP ← (SP) – 1
JSR opr,X Jump to Subroutine — — — — — IX2 DD ee ff 7
Push (PCH); SP ← (SP) – 1
JSR opr,X IX1 ED ff 6
PC ← Effective Address
JSR ,X IX FD 5

LDA #opr IMM A6 ii 2

LDA opr DIR B6 dd 3
LDA opr EXT C6 hh ll 4
LDA opr,X
Load Accumulator with Memory Byte A ← (M) — —   —
IX2 D6 ee ff 5
LDA opr,X IX1 E6 ff 4
LDA ,X IX F6 3

LDX #opr IMM AE ii 2

LDX opr DIR BE dd 3
LDX opr EXT CE hh ll 4
LDX opr,X
Load Index Register with Memory Byte X ← (M) — —   —
IX2 DE ee ff 5
LDX opr,X IX1 EE ff 4
LDX ,X IX FE 3

LSL opr DIR 38 dd 5

LSLA INH 48 3
LSLX Logical Shift Left (Same as ASL) C 0 — —    INH 58 3
LSL opr,X b7 b0 IX1 68 ff 6
LSL ,X IX 78 5

LSR opr DIR 34 dd 5

LSRA INH 44 3
LSRX Logical Shift Right 0 C — — 0   INH 54 3
LSR opr,X b7 b0 IX1 64 ff 6
LSR ,X IX 74 5

MUL Unsigned Multiply X : A ← (X) × (A) 0 — — — 0 INH 42 11

NEG opr M ← –(M) = $00 – (M) DIR 30 dd 5

NEGA A ← –(A) = $00 – (A) INH 40 3
NEGX Negate Byte (Two’s Complement) X ← –(X) = $00 – (X) — —    INH 50 3
NEG opr,X M ← –(M) = $00 – (M) IX1 60 ff 6
NEG ,X M ← –(M) = $00 – (M) IX 70 5

NOP No Operation — — — — — INH 9D 2

ORA #opr IMM AA ii 2

ORA opr DIR BA dd 3
ORA opr EXT CA hh ll 4
ORA opr,X
Logical OR Accumulator with Memory A ← (A) ∨ (M) — —   —
IX2 DA ee ff 5
ORA opr,X IX1 EA ff 4
ORA ,X IX FA 3

ROL opr DIR 39 dd 5

ROLA INH 49 3
ROLX Rotate Byte Left through Carry Bit C — —    INH 59 3
ROL opr,X b7 b0 IX1 69 ff 6
ROL ,X IX 79 5

MC68HC705P6A — Rev. 2.0 Advance Information

MOTOROLA Instruction Set 113

Instruction Set

Table 13-6. Instruction Set Summary (Sheet 5 of 6)

Operand
Address
Effect on

Opcode

Cycles
Mode
Source CCR
Operation Description
Form
H I N Z C
ROR opr DIR 36 dd 5
RORA INH 46 3
RORX Rotate Byte Right through Carry Bit C — —    INH 56 3
ROR opr,X b7 b0 IX1 66 ff 6
ROR ,X IX 76 5

RSP Reset Stack Pointer SP ← $00FF — — — — — INH 9C 2

SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A)
RTI Return from Interrupt SP ← (SP) + 1; Pull (X)      INH 80 9
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
SP ← (SP) + 1; Pull (PCH)
RTS Return from Subroutine — — — — — INH 81 6
SP ← (SP) + 1; Pull (PCL)
SBC #opr IMM A2 ii 2
SBC opr DIR B2 dd 3
SBC opr Subtract Memory Byte and Carry Bit from EXT C2 hh ll 4
SBC opr,X Accumulator
A ← (A) – (M) – (C) — —    IX2 D2 ee ff 5
SBC opr,X IX1 E2 ff 4
SBC ,X IX F2 3

SEC Set Carry Bit C←1 — — — — 1 INH 99 2

SEI Set Interrupt Mask I←1 — 1 — — — INH 9B 2

STA opr DIR B7 dd 4

STA opr EXT C7 hh ll 5
STA opr,X Store Accumulator in Memory M ← (A) — —   — IX2 D7 ee ff 6
STA opr,X IX1 E7 ff 5
STA ,X IX F7 4

STOP Stop Oscillator and Enable IRQ Pin — 0 — — — INH 8E 2

STX opr DIR BF dd 4

STX opr EXT CF hh ll 5
STX opr,X Store Index Register In Memory M ← (X) — —   — IX2 DF ee ff 6
STX opr,X IX1 EF ff 5
STX ,X IX FF 4

SUB #opr IMM A0 ii 2

SUB opr DIR B0 dd 3
SUB opr EXT C0 hh ll 4
SUB opr,X
Subtract Memory Byte from Accumulator A ← (A) – (M) — —    IX2 D0 ee ff 5
SUB opr,X IX1 E0 ff 4
SUB ,X IX F0 3
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
SWI Software Interrupt — 1 — — — INH 83 10
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; I ← 1
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte

Advance Information MC68HC705P6A — Rev. 2.0

114 Instruction Set MOTOROLA

 Instruction Set
Opcode Map

Table 13-6. Instruction Set Summary (Sheet 6 of 6)

Operand
Address
Effect on

Opcode

Cycles
Mode
Source CCR
Operation Description
Form
H I N Z C
TAX Transfer Accumulator to Index Register X ← (A) — — — — — INH 97 2

TST opr DIR 3D dd 4

TSTA INH 4D 3
TSTX Test Memory Byte for Negative or Zero (M) – $00 — —   — INH 5D 3
TST opr,X IX1 6D ff 5
TST ,X IX 7D 4

TXA Transfer Index Register to Accumulator A ← (X) — — — — — INH 9F 2

WAIT Stop CPU Clock and Enable Interrupts — 0 — — — INH 8F 2

A Accumulator opr Operand (one or two bytes)
C Carry/borrow flag PC Program counter
CCR Condition code register PCH Program counter high byte
dd Direct address of operand PCL Program counter low byte
dd rr Direct address of operand and relative offset of branch instruction REL Relative addressing mode
DIR Direct addressing mode rel Relative program counter offset byte
ee ff High and low bytes of offset in indexed, 16-bit offset addressing rr Relative program counter offset byte
EXT Extended addressing mode SP Stack pointer
ff Offset byte in indexed, 8-bit offset addressing X Index register
H Half-carry flag Z Zero flag
hh ll High and low bytes of operand address in extended addressing # Immediate value
I Interrupt mask ∧ Logical AND
ii Immediate operand byte ∨ Logical OR
IMM Immediate addressing mode ⊕ Logical EXCLUSIVE OR
INH Inherent addressing mode () Contents of
IX Indexed, no offset addressing mode –( ) Negation (two’s complement)
IX1 Indexed, 8-bit offset addressing mode ← Loaded with
IX2 Indexed, 16-bit offset addressing mode ? If
M Memory location : Concatenated with
N Negative flag  Set or cleared
n Any bit — Not affected

13.6 Opcode Map

See Table 13-7.

MC68HC705P6A — Rev. 2.0 Advance Information

MOTOROLA Instruction Set 115

 Instruction Set
116

Advance Information Table 13-7. Opcode Map

Bit Manipulation Branch Read-Modify-Write Control Register/Memory
DIR DIR REL DIR INH INH IX1 IX INH INH IMM DIR EXT IX2 IX1 IX
MSB MSB
0 1 2 3 4 5 6 7 8 9 A B C D E F
LSB LSB
5 5 3 5 3 3 6 5 9 2 3 4 5 4 3
0 BRSET0 BSET0 BRA NEG NEGA NEGX NEG NEG RTI SUB SUB SUB SUB SUB SUB 0
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX
5 5 3 6 2 3 4 5 4 3
1 BRCLR0 BCLR0 BRN RTS CMP CMP CMP CMP CMP CMP 1
3 DIR 2 DIR 2 REL 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX
5 5 3 11 2 3 4 5 4 3
2 BRSET1 BSET1 BHI MUL SBC SBC SBC SBC SBC SBC 2
3 DIR 2 DIR 2 REL 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX
5 5 3 5 3 3 6 5 10 2 3 4 5 4 3
3 BRCLR1 BCLR1 BLS COM COMA COMX COM COM SWI CPX CPX CPX CPX CPX CPX 3
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX
5 5 3 5 3 3 6 5 2 3 4 5 4 3
4 BRSET2 BSET2 BCC LSR LSRA LSRX LSR LSR AND AND AND AND AND AND 4
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX
5 5 3 2 3 4 5 4 3
5 BRCLR2 BCLR2 BCS/BLO BIT BIT BIT BIT BIT BIT 5
3 DIR 2 DIR 2 REL 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX
5 5 3 5 3 3 6 5 2 3 4 5 4 3
6 BRSET3 BSET3 BNE ROR RORA RORX ROR ROR LDA LDA LDA LDA LDA LDA 6
Instruction Set

3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX
5 5 3 5 3 3 6 5 2 4 5 6 5 4
7 BRCLR3 BCLR3 BEQ ASR ASRA ASRX ASR ASR TAX STA STA STA STA STA 7
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 2 DIR 3 EXT 3 IX2 2 IX1 1 IX
5 5 3 5 3 3 6 5 2 2 3 4 5 4 3
8 BRSET4 BSET4 BHCC ASL/LSL ASLA/LSLA ASLX/LSLX ASL/LSL ASL/LSL CLC EOR EOR EOR EOR EOR EOR 8
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX
5 5 3 5 3 3 6 5 2 2 3 4 5 4 3
9 BRCLR4 BCLR4 BHCS ROL ROLA ROLX ROL ROL SEC ADC ADC ADC ADC ADC ADC 9
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX
5 5 3 5 3 3 6 5 2 2 3 4 5 4 3
A BRSET5 BSET5 BPL DEC DECA DECX DEC DEC CLI ORA ORA ORA ORA ORA ORA A
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX
5 5 3 2 2 3 4 5 4 3
B BRCLR5 BCLR5 BMI SEI ADD ADD ADD ADD ADD ADD B
3 DIR 2 DIR 2 REL 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX
5 5 3 5 3 3 6 5 2 2 3 4 3 2
C BRSET6 BSET6 BMC INC INCA INCX INC INC RSP JMP JMP JMP JMP JMP C
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 2 DIR 3 EXT 3 IX2 2 IX1 1 IX
5 5 3 4 3 3 5 4 2 6 5 6 7 6 5
D BRCLR6 BCLR6 BMS TST TSTA TSTX TST TST NOP BSR JSR JSR JSR JSR JSR D
MC68HC705P6A — Rev. 2.0

3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 2 REL 2 DIR 3 EXT 3 IX2 2 IX1 1 IX
5 5 3 2 2 3 4 5 4 3
E BRSET7 BSET7 BIL STOP LDX LDX LDX LDX LDX LDX E
3 DIR 2 DIR 2 REL 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX
5 5 3 5 3 3 6 5 2 2 4 5 6 5 4
F BRCLR7 BCLR7 BIH CLR CLRA CLRX CLR CLR WAIT TXA STX STX STX STX STX F
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 1 INH 2 DIR 3 EXT 3 IX2 2 IX1 1 IX
MSB
INH = Inherent REL = Relative 0 MSB of Opcode in Hexadecimal
MOTOROLA

IMM = Immediate IX = Indexed, No Offset LSB

DIR = Direct IX1 = Indexed, 8-Bit Offset 5 Number of Cycles
EXT = Extended IX2 = Indexed, 16-Bit Offset LSB of Opcode in Hexadecimal 0 BRSET0 Opcode Mnemonic
3 DIR Number of Bytes/Addressing Mode
Advance Information — MC68HC705P6A

Section 14. Electrical Specifications

14.1 Contents
14.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

14.3 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

14.4 Operating Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . 118

14.5 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

14.6 5.0-Volt DC Electrical Characteristics. . . . . . . . . . . . . . . . . . .119

14.7 3.3-Volt DC Electrical Charactertistics . . . . . . . . . . . . . . . . . .120

14.8 A/D Converter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 121

14.9 EPROM Programming Characteristics . . . . . . . . . . . . . . . . . . 122

14.10 SIOP Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

14.11 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

14.2 Introduction
This section contains the electrical and timing specifications.

14.3 Maximum Ratings

Maximum ratings are the extreme limits to which the MCU can be
exposed without permanently damaging it.

MC68HC705P6A — Rev. 2.0 Advance Information

MOTOROLA Electrical Specifications 117

Electrical Specifications

The MCU contains circuitry to protect the inputs against damage from
high static voltages; however, do not apply voltages higher than those
shown in the table below. Keep VIn and VOut within the range
VSS ≤ (VIn or VOut) ≤ VDD. Connect unused inputs to the appropriate
voltage level, either VSS or VDD.

Rating(1) Symbol Value Unit

Supply voltage VDD –0.3 to +7.0 V

VSS –0.3 to
Input voltage VIn V
VDD +0.3

VSS –0.3 to
Bootloader mode (IRQ/VPP pin only) VIn V
2 x VDD +0.3

Current drain per pin excluding VDD and VSS I 25 mA

Storage temperature range Tstg –65 to +150 °C

1. Voltages are referenced to VSS.

NOTE: This device is not guaranteed to operate properly at the maximum

ratings. Refer to 14.6 5.0-Volt DC Electrical Characteristics and
14.7 3.3-Volt DC Electrical Charactertistics for guaranteed operating
conditions.

14.4 Operating Temperature Range

Characteristic Symbol Value Unit

Operating temperature range TL to TH
MC68HC705P6A (standard) TA 0 to +70 °C
MC68HC705P6AC (extended) –40 to +85

14.5 Thermal Characteristics

Characteristic Symbol Value Unit

Thermal resistance
PDIP θJA 60 °C/W
SOIC 60

Advance Information MC68HC705P6A — Rev. 2.0

118 Electrical Specifications MOTOROLA

 Electrical Specifications
5.0-Volt DC Electrical Characteristics

14.6 5.0-Volt DC Electrical Characteristics

Characteristic(1) Symbol Min Typ(2) Max Unit

Output voltage
ILoad = 10.0 µA VOL — — 0.1 V
ILoad = –10.0 µA VOH VDD –0.1 — —

Output high voltage

(ILoad = –0.8 mA) PA0:7, PB5:7, PC2:7, PD5, TCMP VOH VDD –0.8 — — V
(ILoad = –5.0 mA) PC0:1 VDD –0.8 — —

Output low voltage

(ILoad = 1.6 mA) PA0:7, PB5:7, PC2:7, PD5, TCMP VOL — — 0.4 V
(ILoad = 10 mA) PC0:1 — — 0.4

Input high voltage

PA0:7, PB5:7, PC0:7, PD5, TCAP/PD7, IRQ/VPP, VIH 0.7 x VDD — VDD V
RESET, OSC1
Input low voltage
PA0:7, PB5:7, PC0:7, PD5, TCAP/PD7, IRQ/VPP, VIL VSS — 0.2 x VDD V
RESET, OSC1
Supply current(3), (4)
Run — 4.0 7.0 mA
Wait(5) (A/D converter on) — 2.0 4.0 mA
Wait(5) (A/D converter off) — 1.3 2.0 mA
IDD
Stop(6)
25°C — 2 30 µA
0°C to +70°C (standard) — — 50 µA
–40°C to +85°C (extended) — — 100 µA
I/O ports high-z leakage current
IIL — — ±10.0 µA
PA0:7, PB5:7, PC0:7, PD5, TCAP/PD7
A/D ports hi-z leakage current
IOZ — — ±1.0 µA
PC3:7
Input current
IIn — — ±1.0 µA
RESET, IRQ/VPP, OSC1, PD7/TCAP
Input pullup current
IIn 175 385 750 µA
PA0:7 (with pullup enabled)
Capaitance
Ports (as input or output) COut — — 12 pF
RESET, IRQ/VPP CIn — — 8
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40°C to +85°C, unless otherwise noted. All values shown refelect pre-silicon
estimates.
2. Typical values at midpoint of voltage range, 25°C only.
3. Run (Operating) IDD, Wait IDD: To be measured using external square wave clock source (fosc = 4.2 MHz), all inputs 0.2 V
from rail; no dc loads, less than 50 pF on all outputs, CL = 20 pF on OSC2.
4. Wait, Stop IDD: All ports configured as inputs, VIL = 0.2 V, VIH = VDD –0.2 V.
5. Wait IDD will be affected linearly by the OSC2 capacitance.
6. Stop IDD to be measured with OSC1 = VSS.

MC68HC705P6A — Rev. 2.0 Advance Information

MOTOROLA Electrical Specifications 119

Electrical Specifications

14.7 3.3-Volt DC Electrical Charactertistics

Characteristic(1) Symbol Min Typ(2) Max Unit
Output voltage
ILoad = 10.0 µA VOL — — 0.1 V
ILoad = –10.0 µA VOH VDD –0.1 — —

Output high voltage

(ILoad = –0.2 mA) PA0:7, PB5:7, PC2:7, PD5, TCMP VOH VDD –0.3 — — V
(ILoad = –1.2 mA) PC0:1 VDD –0.3 — —

Output low voltage

(ILoad = 0.4 mA) PA0:7, PB5:7, PC2:7, PD5, TCMP VOL — — 0.3 V
(ILoad = 2.5 mA) PC0:1 — — 0.3

Input high voltage

PA0:7, PB5:7, PC0:7, PD5, TCAP/PD7, IRQ/VPP, VIH 0.7 x VDD — VDD V
RESET, OSC1
Input low voltage
PA0:7, PB5:7, PC0:7, PD5, TCAP/PD7, IRQ/VPP, VIL VSS — 0.2 x VDD V
RESET, OSC1

Supply current(3), (4)

Run — 1.8 2.5 mA
Wait(5) (A/D converter on) — 1.0 1.4 mA
Wait(5) (A/D converter off) IDD — 0.6 1.0 mA
Stop(6)
— 2 20 µA
25°C
— — 40 µA
0°C to +70°C (standard)
— — 50 µA
–40°C to +85°C (extended)
I/O ports high-z leakage current
IIL — — ±10.0 µA
PA0:7, PB5:7, PC0:7, PD5, TCAP/PD7
A/D ports hi-z leakage current
IOZ — — ±1.0 µA
PC3:7
Input current
IIn — — ±1.0 µA
RESET, IRQ/VPP, OSC1, PD7/TCAP
Input pullup current
IIn 75 175 350 µA
PA0:7 (with pullup enabled)
Capaitance
Ports (as input or output) COut — — 12 pF
RESET, IRQ/VPP CIn — — 8
1. VDD = 3.3 Vdc ± 0.3 Vdc, VSS = 0 Vdc, T A = –40°C to +85°C, unless otherwise noted. All values shown reflect pre-silicon
estimates.
2. Typical values at midpoint of voltage range, 25°C only.
3. Run (Operating) IDD, Wait IDD: To be measured using external square wave clock source (fosc = 4.2 MHz), all inputs 0.2 V
from rail; no dc loads, less than 50 pF on all outputs, CL = 20 pF on OSC2.
4. Wait, Stop IDD: All ports configured as inputs, VIL = 0.2 V, VIH = VDD –0.2 V.
5. Wait IDD will be affected linearly by the OSC2 capacitance.
6. Stop IDD to be measured with OSC1 = VSS.

Advance Information MC68HC705P6A — Rev. 2.0

120 Electrical Specifications MOTOROLA

 Electrical Specifications
A/D Converter Characteristics

14.8 A/D Converter Characteristics

Characteristic(1) Min Max Unit Comments

Resolution 8 8 Bits

Absolute accuacy
— ± 1 1/2 LSB Including quanitization
(VDD ≥ VREFH > 4.0)

A/D accuracy may decrease

Conversion range VSS VREFH
V proportionately as VREFH is
VREFH VSS VDD
reduced below 4.0

Input leakage
AD0, AD1, AD2, AD3 — ±1 µA
VREFH — ±1

Conversion time
MCU external oscillator — 32 tcyc Includes sampling time
Internal RC oscillator — 32 µs

Monotonicity Inherent (within total error)

Zero input reading 00 01 Hex Vin = 0 V

Full-scale reading FE FF Hex Vin = VREFH

Sample time
MCU external oscillator — 12 tcyc
Internal RC oscillator — 12 µs

Input capacitance — 12 pF

Analog input voltage VSS VREFH V

A/D on current stabilization time — 100 µs tADON

A/D ports hi-z leakage current (PC3:7) — ±1 µA IOZ

1. V DD = 5.0 Vdc ± 10%, V SS = 0 Vdc, TA = –40°C to +85°C, unless otherwise noted.

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MOTOROLA Electrical Specifications 121

Electrical Specifications

14.9 EPROM Programming Characteristics

Characteristic Symbol Min Typ Max Unit
Programming voltage
VPP 16.25 16.5 16.75 V
IRQ/VPP

Programming current
IPP — 5.0 10 mA
IRQ/VPP

Programming time per byte tEPGM 4 — — ms

14.10 SIOP Timing

Number Characteristic Symbol Min Max Unit

Operating frequency
Master fop(m) 0.25 0.25 fop
Slave fop(s) dc 0.25

Cycle time
1 Master tcyc(m) 4.0 4.0 tcyc
Slave tcyc(s) — 4.0

2 SCK low time tcyc 932 — ns

3 SDO data valid time tv — 200 ns

4 SDO hold time tho 0 — ns

5 SDI setup time ts 100 — ns

6 SDI hold time th 100 — ns

t1 t2

SCK

t5 t6

SDI
BIT 0 BIT 1 ... 6 BIT 7

t3 t4

SDO
BIT 0 BIT 1 ... 6 BIT 7

Figure 14-1. SIOP Timing Diagram

Advance Information MC68HC705P6A — Rev. 2.0

122 Electrical Specifications MOTOROLA

 Electrical Specifications
Control Timing

14.11 Control Timing

Characteristic(1) Symbol Min Max Unit

Frequency of operation
Crystal option fOSC — 4.2 MHz
External clock option DC 4.2

Internal operating frequency

Crystal (fOSC ÷ 2) fOP — 2.1 MHz
External clock (fOSC ÷ 2) DC 2.1

Cycle time tCYC 476 — ns

Crystal oscillator startup time tOXOV — 100 ms

Stop mode recovery startup time (crystal oscillator) tILCH — 100 ms

RESET pulse width tRL 1.5 — tCYC

Interrupt pulse width low (edge-triggered) tILIH 125 — ns

Interrupt pulse period(2) tILIL Note 2 — tCYC

OSC1 pulse width tOH, tOL 200 — ns

A/D On current stabilization time tADON Q 100 µs

1. V DD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40°C to +125°C, unless otherwise noted
2. The minimum period, tILIL, should not be less than the number of cycle times it takes to execute the interrupt service routine
plus 19 tCYC.

MC68HC705P6A — Rev. 2.0 Advance Information

MOTOROLA Electrical Specifications 123

 Electrical Specifications
124

Advance Information

t
VDDR

V THRESHOLD (1-2 V TYPICAL)

V DD
DD

OSC1(2)
4064 t
cyc

tcyc
INTERNAL
PROCESSOR
Electrical Specifications

(1)
CLOCK

INTERNAL
ADDRESS 1FFE 1FFF NEW PC NEW PC 1FFE 1FFE 1FFE 1FFE 1FFF NEW PC NEW PC
(1)
BUS

INTERNAL
DATA NEW NEW OP PCH PCL OP
(1) PCH PCL CODE CODE
BUS
tRL

RESET NOTE 3

Notes:
1. Internal timing signal and bus information are not available externally.
MC68HC705P6A — Rev. 2.0

2. OSC1 line is not meant to represent frequency. It is only used to represent time.
3. The next rising edge of the internal clock following the rising edge of RESET initiates the reset sequence.

Figure 14-2. Power-On Reset and External Reset Timing Diagram

MOTOROLA
Advance Information — MC68HC705P6A

Section 15. Mechanical Specifications

15.1 Contents
15.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

15.3 Plastic Dual In-Line Package (Case 710) . . . . . . . . . . . . . . . . 126

15.4 Small Outline Integrated Circuit Package (Case 751F) . . . . . 126

15.2 Introduction
The MC68HC705P6A is available in either a 28-pin plastic dual in-line
(PDIP) or a 28-pin small outline integrated circuit (SOIC) package.

To make sure that you have the latest case outline specifications,
contact one of the following:
• Local Motorola Sales Office
• World Wide Web at
http://www.motorola.com/semiconductors

Follow World Wide Web on-line instructions to retrieve the current

mechanical specifications.

MC68HC705P6A — Rev. 2.0 Advance Information

MOTOROLA Mechanical Specifications 125

Mechanical Specifications

15.3 Plastic Dual In-Line Package (Case 710)

NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D),
SHALL BE WITHIN 0.25mm (0.010) AT
MAXIMUM MATERIAL CONDITION, IN
RELATION TO SEATING PLANE AND
EACH OTHER.
28 15 2. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE
B MOLD FLASH.
MILLIMETERS INCHES
1 14 DIM MIN MAX MIN MAX
A 36.45 37.21 1.435 1.465
A L B 13.72 14.22 0.540 0.560
C C 3.94 5.08 0.155 0.200
D 0.36 0.56 0.014 0.022
N F 1.02 1.52 0.040 0.060
G 2.54 BSC 0.100 BSC
H 1.65 2.16 0.065 0.085
J 0.20 0.38 0.008 0.015
H G J K 2.92 3.43 0.115 0.135
K M
F D L 15.24 BSC 0.600 BSC
SEATING M 0° 15° 0° 15°
PLANE
N 0.51 1.02 0.020 0.040

15.4 Small Outline Integrated Circuit Package (Case 751F)

-A-
28 15 NOTES:
1. DIMENSIONING AND TOLERANCING PER
14X P ANSI Y14.5M, 1982.
-B- 0.010 (0.25) M B M 2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
1 14 4. MAXIMUM MOLD PROTRUSION 0.15
(0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
28X D DAMBAR PROTRUSION SHALL BE 0.13
M (0.005) TOTAL IN EXCESS OF D
0.010 (0.25) M T A S B S
DIMENSION AT MAXIMUM MATERIAL
R X 45° CONDITION.
MILLIMETERS INCHES
-T- C DIM MIN MAX MIN MAX
A 17.80 18.05 0.701 0.711
-T- B 7.40 7.60 0.292 0.299
26X G SEATING C 2.35 2.65 0.093 0.104
PLANE
D 0.35 0.49 0.014 0.019
K
F F 0.41 0.90 0.016 0.035
G 1.27 BSC 0.050 BSC
J 0.23 0.32 0.009 0.013
J K 0.13 0.29 0.005 0.011
M 0° 8° 0° 8°
P 10.05 10.55 0.395 0.415
R 0.25 0.75 0.010 0.029

Advance Information MC68HC705P6A — Rev. 2.0

126 Mechanical Specifications MOTOROLA

Advance Information — MC68HC705P6A

Section 16. Ordering Information

16.1 Contents
16.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

16.3 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127

16.2 Introduction
This section contains ordering information for the available package
types.

16.3 MC Order Numbers

The following table shows the MC order numbers for the available
package types.

Operating
MC Order Number Temperature Range
MC68HC705P6ACP(1) (extended) –40°C to 85°C

MC68HC705P6ACDW (2) (extended) –40°C to 85°C

1. P = Plastic dual in-line package

2. DW = Small outline integrated circuit (SOIC) package

MC68HC705P6A — Rev. 2.0 Advance Information

MOTOROLA Ordering Information 127

Ordering Information

Advance Information MC68HC705P6A — Rev. 2.0

128 Ordering Information MOTOROLA

blank
 MC68HC05P6 Technical Data
How to Reach Us:
USA/EUROPE/LOCATIONS NOT LISTED:
Motorola Literature Distribution
P.O. Box 5405
Denver, Colorado 80217
1-303-675-2140
1-800-441-2447

TECHNICAL INFORMATION CENTER:

1-800-521-6274

JAPAN:
Motorola Japan Ltd.
SPS, Technical Information Center
3-20-1, Minami-Azabu, Minato-ku
Tokyo 106-8573 Japan
81-3-3440-3569

ASIA/PACIFIC:
Motorola Semiconductors H.K. Ltd.
Silicon Harbour Centre
2 Dai King Street
Tai Po Industrial Estate
Tai Po, N.T., Hong Kong
852-26668334

HOME PAGE:
http://www.motorola.com/semiconductors/

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REV 2