5 4 3 2 1

Project code:
LV115SK:4PD08B010001
LV114SK:4PD08A010001
PCB P/N: 15277/15309
Eletro-XTechnical
Revision: SA
IO Board:
D D

El
LV115/LV114 SKL-U
et
C C

ro
Block Diagram

-X
Te
ch
B B

ni
ca
l
PCB Halogen PN No Halogen PN
LV115SK MB 15277 15309
LV115SK BTN BD 15902 15939
LV115SK AUDIO IO BD 15903 15940
A LV115SK ODD BD 15904 15941 <Core Desiiign> A

Wistron Corporation
21F, 88, Sec.1, Hsiiin Taiii Wu Rd., Hsiiichiiih,
TaiiipeiiiHsiiien 221, Taiiiwan, R.O.C.

Eletro-XTechnical Eletro-XTechnical
Title

Cover Page
Siize DocumentNumber Rev
A3
LV115 SKL-U -1
Date: Monday, Apriiilll25,2016 Sheet 1 of 102
5 4 3 2 1
 5 4 3 2 1

CHARGER
PCB LAYER BQ24780RUYR 44

LV115/LV114 SKL-U Block Diagram L1:Top

INPUTS
AD+
OUTPUTS

DCBATOUT
L2:VCC
32.768KHz 24MHz L3:Signal
L4:Signal
Eletro-XTechnical
BT+
SYSTEM DC/DC
L5:GND TPS51275CRUKR 45
X7901 L6:Signal
27MHz INPUTS OUTPUTS
3D3V_AUX_S5
D SM Bus AMD GPU VRAM x4 5V_PWR_2 D

EXO Pro S3 GDDR3 / 1.5V DCBATOUT 5V_S5

DDR4 SO-DIMM x1 13 DDR4 1866/2133MHz Channel A 900MHz 3D3V_S5
PEG x4 18W 76~80 81~84
Intel CPU CPU Core Power
Skylake U NCP81208MNTXG 46~50
DDR4 MD x4 pcs DDR4 1866/2133MHz Channel B LAN 10/100/1000
14
RJ45 NCP81382MNTXG x 2
28W (UMA only) PCIe x 1
RealTek RTL8111H NCP81382MNTXG(23e)
15W (UMA&DIS)
30
Conn. NCP81253MNTBG
Left side
USB3.0 x 2 INPUTS OUTPUTS
USB 3.0 SKT x2
DCBATOUT VCC_CORE
25MHz DCBATOUT +VCCGT
SKL PCH-LP
Right side DCBATOUT+V_VCCGTUS_VR

El
USB2.0 x 1 10 USB 2.0/1.1 ports PCIe x 1 NGFF WLAN
USB 2.0 SKT x (23e only)
6 USB 3.0 ports
High Definition Audio W/ Bluetooth DCBATOUT+VCCSA_VR
USB2.0 x 1 COMBO
3 SATA ports
61 DDR3L SUS

et
6 PCIEports TPS51716RUKR 51
LPC I/F INPUTS OUTPUTS
ACPI 5.0
14.0"/15.6" (FHD) eDP DCBATOUT 1D35V_S3
C
0D65V_S0 C

ro
CPU VCCIO 0.975V
HDMI V1.4b RT8068AZQWID 52
HDMI
57 INPUTS OUTPUTS
SATA(Gen3) x 1
HDD 60 3D3V_S5 +VCCIO_VR

-X
CRT eDP SATA(Gen2) x 1 CPU VCCPRIM_CORE
Travis ODD 61
0.95V
TPS22961DNYT 52
INPUTS OUTPUTS

Te
LPC BUS LPC Debug Port
Camera (HD) 3D3V_S5 VCCPRIM_CORE
USB2.0 x 1 65
52 CPU DCDC-V1D00A
D-MIC AOZ1268QI 53
SMBUS Thermal INPUTS OUTPUTS
SPI NUVOTON
2CH SPEAKER NCT7718W 26 DCBATOUT 1D0V_S5

ch
(2CH 2W/4ohm) HDA
KBC LDO-V1D5V
CODEC TLV70215DBVR 54

Realtek Flash ROM NPCE285 SMBUS 1ST Battery INPUTS OUTPUTS

B

MIC_IN/GND
HDA B

ALC3240 16MB 25 3D3V_S5 1D5V_S0

Universal Jack HP_R/L 29

ni
27 LDO-V1D8V
RT9025-25ZSP 54
24
INPUTS OUTPUTS
3D3V_S5 1D8V_S5

ca
SD Card Slot PS2 PWM 5V/3V S0
CardReader G5016KD1U 40
SDR50 USB2.0 x 1
INPUTS OUTPUTS
SSD/MMC Clickpad Int. 5V_S5 5V_S0
I2C FAN 3D3V_S5 3D3V_S0
62
KB 26 VCCSTG EOPIO/EDRAM (23e)

l
M5938ARD1U TPS22961DNYT 52
INPUTS OUTPUTS INPUTS OUTPUTS
1D0V_S5 +V_EDRAM_VR
1D0V_S5 +V1.00DX
40 1D0V_S5 +V_EOPIO_VR

VCCST 3D3V VGA

M5938ARD1U G5016KD1U 86
INPUTS OUTPUTS INPUTS OUTPUTS
3D3V_S0 +V_EDRAM_VR
A 1D0V_S5 +V1.00U_CPU 40 A
3D3V_S0 +V_EOPIO_VR

<Core Desiiign>

Wistron Corporation
Eletro-XTechnical Eletro-XTechnical
21F,,, 88,,, Sec.1,,, HsiiinTaiiiWu Rd., Hsiiichiiih,,,
Taipei Hsiiien221, Taiwan, R...O...C...

Tiitttlle

Block Diagram
Siize Document Number Rev
C
LV115 SKL-U -1
Date: Monday,,, Apriiilll25, 2016 Sheet 2 off 102
5 4 3 2 1
 A B E
C D

PCH SMBus Block Diagram

3D3V_S5_PCH 3D3V_S0 KBC SMBus Block Diagram
‧ ‧
TP_VDD
Eletro-XTechnical
3D3V_S0 ‧
SRN2K2J-1-GP SRN10KJ-5-GP
‧
DIMM 1 SRN10KJ-5-GP

‧ ‧ PCH_S M B C L K
1 SMBCLK SMB_CLK

SMBDATA SMB_DATA
‧ ‧ PCH_SMBDATA SDA
SCL
TouchPad Conn. 1

PSDAT1 TPDATA
‧ TPDATA TPDATA

SMBus Address:0xA0/0xA1 PSCLK1 TPCLK

‧ TPCLK TPCLK
2N7002SPT
3D3V_AUX_KBC

TPAD
PCH_SMBCLK
SCL
‧
PCH_SMBDATA SDA
3D3V_S5_PCH
SRN4K7J-8-GP
SMBus Address:0x58/0x59
‧
SRN33J-7-GP Battery Conn.
‧‧BAT_SCL
PTN3355 GPIO17/SCL1 PBAT_SMBCLK1 CLK_SMB
SMBus address:16
‧BAT_SDA
SRN2K2J-1-GP
‧
GPIO22/SDA1 PBAT_SMBDAT1 DAT_SMB

El
PCH_SMBCLK
VDDA33_DP
PCH_SMBDATA TMS
(Janus Only)
SML0CLK SML0_CLK
SML0DATA SML0_DATA
SMBus Address:0xC0H/0x40H HPA02224RGRR
KBC SCL

SMBus address:12

et
SDA

NPCE285P
2 2

GPIO73/SCL2

ro
GPIO74/SDA2

PCH 3D3V_S0 SMBus Address:

3D3V_S5_PCH 0x94/0x95/0x96/0x97

-X
‧
3D3V_S0
SRN2K2J-8-GP

‧ SRN2K2J-8-GP

‧ ‧SML1_CLK ‧
THM_SML1_CLK SCL Thermal

Te
SML1CLK

SML1DATA ‧ ‧ SML1_DATA
‧
THM_SML1_DATA SDL
NCT7718W
SMBus Address:0x82/0x83 SMBus Address:0x98/0x99
2N7002SPT
3D3V_VGA_S0

ch
SRN4K7J-8-GP
3D3V_VGA_S0
dGPU
3 ‧ 3

I2CS_SCL
‧
SMBC_Therm_NV

‧
SMBD_Therm_NV I2CS_SDA

ni
SMBus Address:0x9E/0x9F

3D3V_S0 5V_S0

ca
0R2J-2-GP
‧ ‧ DY
3D3V_S0
SRN2K2J-1-GP
‧
SRN2K2J-1-GP GPIO47/SCL4A PROCHOT_EC
‧ H_PROCHOT_EC
‧ ‧
GPIO53/SDA4A LCD_TST_EN LCD_TST_EN

l
0R2J-2-GP
DDPB_CTRLCLK ‧ PCH_HDMI_ CL K DDC_CLK_HDMI
‧
DDPB_CTRLDATA ‧ PCH_HDMI_DATA ‧ ‧ DDC_DATA_HDMI ‧ HDMI CONN LCD_TST

2N7002DW-1-GP

4 4

<Corrre Desiiign>

Wistron Corporation
21F,,, 88, Sec...1, HsiiinTai W u Rd...,,,Hsiiichih,

Eletro-XTechnical Eletro-XTechnical
Taiiipeiii Hsiiien 221,,, Taiiiwan,,, R.O.C...

Title

SMBUS BLOCK DIAGRAM

Siize Document Number Rev
A2
LV115 SKL-U -1
Date: Monday,,, Aprrriill25, 2016 Sheet 104 offf 102
A B C D E
 A B C D E

Thermal Block Diagram Audio BlockEletro-XTechnical

Diagram
1 1

3D3V_S5_PCH 3D3V_S0
PCH
PAGE28 D+ NCT7718_DXP
SPKR_L+

SPEAKER
MMBT3904-3-GP SPKR_L-
SC2200P50V2KX-2GP SPKR_R-
SPKR_R+

Thermal
D- NCT7718_DXN

Place near CPU

NCT7718 PWM CORE
Codec
SML1DATA/GPIO74 ‧
S ML1_DATA
‧‧ ‧
THM _SML1_DATA SDA

El
2N7002
SML1CLK/GPIO75 SML1_ CL K
‧ ‧ ‧ ‧THM_SML1_CLK SCL ALC3223
HP MIC
MMBT3904-3-GP

T8 AUD_HP1_JACK_L

et
AUD_HP1_JACK_R
COMBO
SML1_DATA

SML1_CLK

3D3V_S0
T_CRIT# THERM_SYS_SHDN#
2N7002
D
PURE_HW_SHUTDOWN#
EN 3V/5V SLEEVE
PAGE20 S PCH_PWROK
G RING2

‧ Put under CPU(T8 HW shutdown)

2 2

ro
PAGE27 PAGE86
GPIO74

KBC GPIO73 Digital

-X
NPCE285P 2N7002
SMBD_THERM_NV I2CS_SCL
VGA GPIO0/DMIC_DATA
DMIC_DATA_R R27 14
0R2J -2-GP
DMIC_DATA
MIC
SMB C_THERM_NV DMIC_CLK_R
R27 16
I2CS_SDA DMIC_CLK
GPIO1/DMIC_CLK
0R2J -2-GP

N15V-GM-S-A2

Te
GPIO4
GPIO94 GPIO56
GB2-64 (23x23)
FAN_TACH1
FAN1_DAC_1

ch
3 3
TACH

FAN

ni
VIN
FAN_VCC1

5V

ca
VIN VSET VOUT

FAN CONTROL

l
APL5606AKI
PAGE28

4 4
<Core Desiiign>

Wistron Corporation
21F, 88, Sec.1, Hsiiin Taiii W u Rd., Hsiiichiiih,
Taipei Hsiiien 221, Taiwan, R.O.C.

Eletro-XTechnical Title
Eletro-XTechnical
THERMAL/AUDIO BLOCK DIAGRAM
Siiize Document Number Rev
Custom

Monday, Apriiilll 25, 2016

ODYSSEY SKL-U -1
Date: Sheet 105 of 102
A B C D E
 5 4 3 2 1

SKL-U/Y Timing Diagram for G3 to S0/M0 [Non Deep Sx Platform]

[#543016 Rev0.9]
(DC mode) Red Words: Controlled by EC GPIO Skylake POWER UP SEQUENCE DIAGRAM
Red: Power Rail
+RTC_VCC t01 >9ms
Orange: Output from KBC
1D0V_S5 5V_S5
RTC_RST# Light Blue: Output from CPU

DCBATOUT

Eletro-XTechnical
Vin VDD
3D3V_AUX_S5 DC AON740 3
BT+ Page43
a Battery EN SW +V1.00U_CPU(VCCST)
Page43 Page43
Sense the power button status
Press Power button
Platform to KBC PSL_IN2
SLG59M1470VTR
KBC_PWRBTN# c Page40
PSL_OUT#(GPIO71) keep low AC +DC_IN AON740 3
3D3V_AUX_KBC a Adapter in S5_ENABLE 3D3V_S5
KBC GPIO34 control power on by 3V_5V_EN Page43
Page43
S5_ENABLE
AD+ 3D3V_S5
5V_S5 IN 1D5V_S0
5V_S5 & 3D3V_S5 need meet 0.7V difference Out
V5REF_Sus must be powered up before EN1 EN2
VccSus3_3, or after VccSus3_3 within
0.7 V. Also, V5REF_Sus must power
3D3V_S5
5V_S5 & 3D3V_S5 need meet 0.7V difference
3D3V_S5 TLV70215DBVR
D
down after VccSus3_3, or before Charger EN Vin +VCCIO_VR D

VccSus3_3 within 0.7 V. +5VA_PCH_VCC5REFSUS Ta DCBATOUT TPS51275CRUKR Lx

BQ24780RUYR VIN
KBC GPIO43 to PCH DC/DC Page54
4 PM_SLP_S3# RT8068AZQWID
PM_RSMRST#(RSMRST#_RST) t05 >10ms (3.3V/5V) 5V_S5 EN VCCIO_PWRGD
t07 >100ms PCH to KBC GPIO00 ACOK Page44 PGOOD
In case of a non-Deep S4/S5 Platform
timing t42 should be added to t07 PCH_SUSCLK_KBC Page45 Page52 5
which will make it 100mS minimum.

KBC GPIO20 to PCH 3D3V_AUX_S5 d PM_SLP_S4#

1D35V_S3
3 S5
PM_PWRBTN#

PM_SLP_S4#
TPS51716RUKR

PM_SLP_S3#
3V_5V_POK
DDR_VTT_PG_CTRL 0D675V_S0
S3

1D35V_VTT_PWRGD
2N7002 3D3V_AUX_KBC PM_SLP_SUS# PGOOD
g Page51
DC PM_PWRBTN# 3 4 4 5
After Power Button
SLP_S4# SLP_S3# DDR_PG_CTL
PCH to KBC GPIO44
PM_SLP_S4# GPIO71 GPIO05 H_VR_ENABLE
t10 PCH to KBC GPIO01 VR_EN
KBC_PWRBTN#
PM_SLP_S3# >30us PSL_IN 2# S5_ENABLE DPWROK 7
GPIO34
KBC GPIO47 to LAN 1
PM_LAN_ENABLE c
Enable by PM_SLP_S4# The DS W ra ils must be stab le f or a t l east
1D5V_S3
KBC_DPWROK 10 m s be fore DSW _PWR OK i s as sert ed t o PCH.
GPIO66 DSW_PWROK
DDR_VREF_S3(0.75V)
5V_S0 & 3D3V_S0 need meet 0.7V difference f
5V_S0 AC_IN# b PM_PWRBTN# Skylake-U MCP
PSL_IN 1# GPIO20 PWRBTN#
3D3V_S0 RSMRST_PWRGD# 2
V5REF must be powered up before
Vcc3_3, or after Vcc3_3 within 0.7 j TBD KBC 3D3V_S5
V. Also, V5REF must power down ALL_SY S_PW RGD and VR_R DY asse rt,
MEC1404

Delay 10ms
after Vcc3_3, or before Vcc3_3 +5VS_PCH_VCC5REF Tb delay 10ms ; PC H_PW ROK asse rt.
within 0.7 V.
RSMRST #_KB C: D elay 10 ms a fter re ceiv e 8

El
PCH_PWROK APWROK
1D5V_S0 RSMRST _PWR GD# and PM_ SLP_ SUS# . AND 4 PM_SLP_S3#
Vcc

AND
RSMRST#_KBC k AND Gate
1D8V_S0 PCH_PWROK PCH_PWROK PM_SLP_S0# VCCSTG_EN
GPIO36 GPIO93 SLP_S0# U74LVC1G08G-AL5 Y

0D75V_S0 6
1D8V_S0 & 1D5V_S3 power ready 7
VR_RDY TBD PM_SUSWARN# 5
GPIO02 SUSWARN# PROCPWRGD
RUNPWROK
ALL_SYS_PWRGD l 9
1D05V_PCH
6 GPIO26
PM_SUSACK#
1D0V_S5 5V_S5
GPIO81 SUSACK#
PLTRST# 11 PCI_PLTRST#
VCCP_CPU m AND
VIN VDD
It is reco mmen ded that SYS _PWR OK b e as sert ed afte r RSMRST#_KBC RSMRST# VCCSTG_EN
both P WROK ass erti on a nd p roce ssor cor e VR PWR GD as sert ion. EN +V1.00DX(VCCSTG)
1D05_VTT_PWRGD VOUT
k

et
0D85V_S0 SY6288C10CAC
PM_SLP_S4#
GPIO44 Page41
3

Delay 100ms
PM_SLP_S3#
4 GPIO01 H_VCCST_PWRGD ALL_SYS_PWRGD
0D85V_S0 6 Level Shifter
D85V_PWRGD
C
10 SYS_PWROK
74LVC1G07GW Page17
C

GPIO77 SYS_PWROK
ACK
CPU SVID BUS SetVID 50us< t36 <2000us
EXT_PWR_GATE#
Page24 1D35VTT_PWRGD
EXT_PWR_GATE#
VCC_CORE 5
g ALL_SYS_PWRGD

ro
ALL_SY S_PW RGD ass ert, SLP_SUS#
VCC_GFXCORE VCCIO_PWRGD
delay 100m s; S YS_P WROK asse rt.
t37
3D3V_S5 5 6
g
IMVP_PWRGD <5ms

VIN

PM_SLP_SUS# 3D3V_S5_PCH
PCH_CLOCK_OUT SVID Transanctions EN SW

ALL_SYS_PWRGD=D85V_PWRGD t14 >99ms KBC GPIO77 to PCH

SY6288C10CAC
This signal represents the Power
Good for all the non-CORE and PWROK(S0_PWR_GOOD) Page41
non-graphics power rails. t18
D85V_PWRGD >0us

-X
PCHto CPU
DRAMPWROK(VDDPWRGOOD) 2ms< t17 <650ms IMVP8 3D3V_S5
CPU SVID Rails
t19 >1ms
6 ALL_SYS_PWRGD SA/Core/GT/GTx
t20 >2ms VR_ON
1D8V_S0 VR_RDY
5ms< t13 <650ms VR_READY VIN
PCHto CPU PM_SLP_SUS#
UNCOREPWRGOOD(H_CPUPWRGD) 7 VCCPRIM_CORE
EN LX

SYS_PWROK t21+t22 >1ms+60us RT8068AZQWID VCCPRIMCORE_PWROK

PGOOD

1ms< t25 <100ms 1D0V_S5 5V_S5 Page52 h

PCH to all system
PLT_RST#
t39 <200us
3D3V_S5 5V_S5
DMI
Vin VDD

Te
+VCCMPHYGTAON_1P0_LS_SIP
EXT_PWR_GATE# EN SW
g Vin VCNTL
SLG59M1470VTR PM_SLP_SUS#
1D8V_S5
EN Vout
Page17
APL5930KAI 1D8V_S5_PWROK
PGOOD

Page54 h

3V_5V_POK
e 0R 0402
PWR_DCBATOUT_1D0V
VCCPRIMCORE_PWROK RSMRST_PWRGD#
h 0R 0402

j VIN
1D8V_S5_PWROK
h 0R 0402
1D0V_S5

ch
LX
1D0V_S5_PWRGD VCCPRIMCORE_PWROK
i
0R 0402 EN
SY8208DQNC 1D0V_S5_PWRGD
h PGOOD

[dGPU] N16x Power-Up/Down Sequence Page53 i

B B

[DG-07158-001_v03]

a b c d e f g h i j k l m

1 2 3a 4 4a 4b 5 6 7 8 9 10 11 12

ni
ca
l
A A

<<<CCCoreee DDDesiiign>

Eletro-XTechnical Eletro-XTechnical
Wistron Corporation
2211FF,8888,,SSSeeccc.11,HHHssinnnTTTaai WuuuRRRdd., HHHssiccchhihh,
TTTaipeii HHHssienn 221,, TTTaiwwwanR , RR.O.CCC.
Titititle

POWER SEQUENCE
SSSizzzeee DDDocument NNNumber RRRev
AA00
LV115 SKL--U -1
DDDate:Monday,,,AAApr25,2016
il SSSheet102 ooof 102
5 4 3 2 1
 5 4 3 2 1

Main Func = CPU

+VCCST_CPU

Eletro-XTechnical

1
R419
+VCCSTG = 1.0 V 1KR2J-1-GP +VCCSTG = 1.0 V
+VCCSTG

2
R420 +VCCSTG
PCH_THERMTRIP
D 1 DY 2 H_THERMTRIP# 40 D

1
R401 0R2J-2-GP
P
[PECI] and [PROCHOT#] Rb 1KR2J-1-GP
Impedance control: 50 ohm TP401 CPU1D 4 OF 20

2
1 H_CATERR# SKYLAKE_ULT
D63 CATERR#
24 H_PECI A54 PECI
499R2F-2-GP 1 R403 2 H_PROCHOT#_R C65 JTAG
24,46 H_PROCHOT# PROCHOT#
Ra PCH_THERMTRIP C63 PCH_JTAG_TDO 1 2
THERMTRIP#
TP402 1SKTOCC# A65 SKTOCC# B61 PROC_TCK 99 51R2J-2-GP R407
PROC_TCK
CPU MIISC D60 PROC_TDI 99
PROC_TDI DY
C55 BPM#[0] PROC_TDO A61
#543016 Rev0.7: Ra = 500 ohm / Rb = 1k ohm D55
BPM#[1] PROC_TMS C60 PROC_TMS 99
#544669 Rev0.52: B54 BPM#[2] PROC_TRST# B59 PROC_TRST# 99
Ra = 56 ohm (TO BE CHANGED TO 100 OHMS) / Rb = 62 ohm and 150 ohm C56 BPM#[3]

El
TP403 1 GPP_E3/CPU_GP0 A6 GPP_E3/CPU_GP0 PCH_JTAG_TCK B56 PCH_JTAG_TCK 99
A7 GPP_E7/CPU_GP1 D59
PCH_JTAG_TDI
BA5 GPP_B3/CPU_GP2 A56 PCH_JTAG_TDO 99
PCH_JTAG_TDO
TP404 1 GPP_B4/CPU _GP3 AY5 GPP_B4/CPU_GP3 PCH_JTAG_TMS C59
PROC_TCK R406 1 2 51R2J-2-GP
PCH_TRST# C61
2 1 CPU_POPIRCOMP AT16 PROC_POPIRCOMP A59
49D9R2F-GP 2 R412 1 PCH_POPIRCOMP AU16
JTAGX DY

et
49D9R2F-GP 2 R413 PCH_OPIRCOMP
1EDRAM_OPIO_RCOMP H66
49D9R2F-GP 2 R414 OPCE_RCOMP
1 EOPIO_RCOMP H65
OPC_RCOMP
49D9R2F-GP R415
SKYLAKE-U-GP
C C

ro
071.SKYLA.000U

CPU BOMCTRL

(#543016) PROCHOT# Routing Guidelines

-X
Te
ch
B B

ni
M1,2,3,4,5: <3 inches
M6: 1-11 inches
MCPU: 0.3-1.5 inches
Mt <0.3 mils
Main route(M1+M2+M3+M4+M5+M6+MCPU): 1-12 inches

ca
l
A <Core Desiiign> A

Wistron Corporation
21F, 88, Sec.1, Hsiiin Taiii Wu Rd., Hsiiichiiih,
TaiiipeiiiHsiiien 221, Taiiiwan, R.O.C.

Eletro-XTechnical Eletro-XTechnical
Tiitlle

CPU_(JTAG/CPU SIDE BAND)

Siize DocumentNumber Rev
A3
LV115 SKL-U -1
Date: Monday, Apriiilll25,2016 Sheet 4 of 102
5 4 3 2 1
 5 4 3 2 1

Main Func = CPU

DDR4 ball type: Interleaved Type
Eletro-XTechnical

M_A_BG1
D M_VREF_DQ_DIMM0 D

Reserve Testpoint only

CPU1C 3 OF 20
CPU1B 2 OF 20

SKYLAKE_ULT M_A_DQ32 SKYLAKE_ULT

12 M_A_DQ32 AY39 DDR0_DQ[32]/DDR1_DQ[0] DDR1_CKN[0] AN45 M_B_CLK#0 13
M_A_DQ0 AL71 DDR0_DQ[0] M_A_DQ33
12 M_A_DQ0
M_A_DQ1 DDR0_CKN[0] AU53 M_A_CLK#0 12 12 M_A_DQ33
M_A_DQ34
AW 39 DDR0_DQ[33]/DDR1_DQ[1] DDR1_CKN[1] AN46 M_B_CLK#1 13
12 M_A_DQ1 AL68 DDR0_DQ[1] DDR0_CKP[0] AT53 12 M_A_DQ34 AY37 DDR0_DQ[34]/DDR1_DQ[2] DDR1_CKP[0] AP45 M_B_CLK0
M_A_DQ2 M_A_CLK0 12 M_A_DQ35 13
12 M_A_DQ2 AN68 DDR0_DQ[2] DDR0_CKN[1] AU55 12 M_A_DQ35 AW 37 DDR0_DQ[35]/DDR1_DQ[3] DDR1_CKP[1] AP46 M_B_CLK1
M_A_DQ3 AN69 DDR0_DQ[3] M_A_DQ36 13
12 M_A_DQ3 M_A_DQ4 DDR0_CKP[1] AT55 12 M_A_DQ36 M_A_DQ37
BB39 DDR0_DQ[36]/DDR1_DQ[4]
AL70 DDR0_DQ[4] BA39 DDR0_DQ[37]/DDR1_DQ[5] DDR1_CKE[0] AN56 M_B_CKE0 13
12 M_A_DQ4 M_A_DQ5 AL69 DDR0_DQ[5] BA56 12 M_A_DQ37 M_A_DQ38 BA37 DDR0_DQ[38]/DDR1_DQ[6] AP55
M_A_DQ6 DDR0_CKE[0] M_A_CKE0 12 M_A_DQ39 DDR1_CKE[1] M_B_CKE1 13
12 M_A_DQ5 AN70 DDR0_DQ[6] 12 M_A_DQ38
M_A_DQ7 DDR0_CKE[1] BB56 M_A_DQ40
BB37 DDR0_DQ[39]/DDR1_DQ[7] DDR1_CKE[2] AN55
12 M_A_DQ6 AN71 DDR0_DQ[7] 12 M_A_DQ39
M_A_DQ8 DDR0_CKE[2] AW 56 M_A_DQ41
AY35 DDR0_DQ[40]/DDR1_DQ[8] DDR1_CKE[3] AP53
12 M_A_DQ7 AR70 DDR0_DQ[8] DDR0_CKE[3] AY56 12 M_A_DQ40 AW 35 DDR0_DQ[41]/DDR1_DQ[9]
M_A_DQ9 AR68 DDR0_DQ[9] M_A_DQ42 AY33 DDR0_DQ[42]/DDR1_DQ[10]
12 M_A_DQ8
M_A_DQ10
12 M_A_DQ41
M_A_DQ43 DDR1_CS#[0] BB42 M_B_CS#0 13
12 M_A_DQ9 AU71 DDR0_DQ[10] AU45 12 M_A_DQ42 AW 33 DDR0_DQ[43]/DDR1_DQ[11] AY42
M_A_DQ11 DDR0_CS#[0] M_A_CS#0 12 M_A_DQ44 DDR1_CS#[1] M_B_CS#1 13
AU68 DDR0_DQ[11] DDR0_CS#[1] AU43 BB35 DDR0_DQ[44]/DDR1_DQ[12] DDR1_ODT[0] BA42 M_B_ODT0
12 M_A_DQ10 M_A_DQ12 12 M_A_DQ43 M_A_DQ45 13
AR71 DDR0_DQ[12] DDR0_ODT[0] AT45 M_A_ODT0 12 BA35 DDR0_DQ[45]/DDR1_DQ[13] DDR1_ODT[1] AW 42 M_B_ODT1
12 M_A_DQ11 M_A_DQ13 AR69 DDR0_DQ[13] AT43 12 M_A_DQ44 M_A_DQ46 BA33 DDR0_DQ[46]/DDR1_DQ[14] 13
12 M_A_DQ12 DDR0_ODT[1] 12 M_A_DQ45

El
M_A_DQ14 AU70 DDR0_DQ[14] M_A_DQ47 BB33 DDR0_DQ[47]/DDR1_DQ[15] AY48 M_B_A5 M_B_A5 13
M_A_DQ15 M_A_A5 M_B_DQ32 DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] M_B_A9
12 M_A_DQ13 AU69 BA51 M_A_A5 12 12 M_A_DQ46 AU40 DDR1_DQ[32]/DDR1_DQ[16] AP50 M_B_A9 13
M_B_DQ0 DDR0_DQ[15] DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] M_A_A9 M_B_DQ33 DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9]
12 M_A_DQ14 AF65 BB54 12 M_A_DQ47 AT40 DDR1_DQ[33]/DDR1_DQ[17] BA48 M_B_A6
DDR1_DQ[0]/DDR0_DQ[16D]DR0_DQ[16] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] M_A_A9 12 DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] M_B_A6 13
13
12 M_B_DQ1
M_A_DQ15 M_B_DQ1 AF64 BA52 M_A_A6 13 M_B_DQ32 M_B_DQ34 AT37 DDR1_DQ[34]/DDR1_DQ[18] BB48 M_B_A8
M_B_DQ2 DDR1_DQ[1]/DDR0_DQ[17D]DR0_DQ[17] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] M_A_A6 12 DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] M_B_A8 13
AK65 AY52 M_A_A8 M_B_DQ35 AU37 DDR1_DQ[35]/DDR1_DQ[19] AP48 M_B_A7
13 M_B_DQ2
M_B_DQ0 DDR1_DQ[2]/DDR0_DQ[18D]DR0_DQ[18] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] M_A_A8 M 13 M_B_DQ33 DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]
M_B_DQ3 AK64 DDR1_DQ[3]/ DDR0_DQ[19D]DR0_DQ[19] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] AW 52 M_A_A7 M_A_A7 12_B_DQ[32:39]
12 M_B_DQ36 AR40 DDR1_DQ[36]/DDR1_DQ[20] AP52
M_B_A7 13
DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]
M_B_DQ[0:7] 13
13
M_B_DQ3
M_B_DQ4 M_B_DQ4 AF66
DDR1_DQ[4]/DDR0_DQ[20D] DR0_DQ[20] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]
AY55 M_A_BG0 12
13
13
M_B_DQ34
M_B_DQ35
M_B_DQ37 AP40 DDR1_DQ[37]/DDR1_DQ[21] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] AN50 M_B_A12 M_B_BG0 13
M_B_A12 13
13 M_B_DQ5 M_B_DQ5 AF67 AW 54 M_A_A12 M_A_A12 12 M_B_DQ38 AP37 DDR1_DQ[38]/DDR1_DQ[22] AN48 M_B_A11
DDR1_DQ[5]/DDR0_DQ[21D] DR0_DQ[21]DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] 13 M_B_DQ36 DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] M_B_A11 13
13 M_B_DQ6 M_B_DQ6 AK67 BA54 M_A_A11 M_B_DQ39 AR37 DDR1_DQ[39]/DDR1_DQ[23]
M_B_DQ7 DDR1_DQ[6]/ DDR0_DQ[22D]DR0_DQ[22]DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] M_A_A11 12
M_B_DQ40 DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# AN53 M_B_ACT_N 13 DDR4 DDR3L
13 M_B_DQ7 AK66 DDR1_DQ[7]/ DDR0_DQ[23D]DR0_DQ[23] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# BA55 M_A_ACT_N 12 13 M_B_DQ37 AT33 DDR1_DQ[40]/DDR1_DQ[24] AN52
DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]

et
M_B_DQ8 AF70 M_A_BG1 1 13 M_B_DQ38 M_B_DQ41 M_B_BG1 13
13 M_B_DQ8
M_B_DQ9 DDR1_DQ[8]/DDR0_DQ[24] DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] AY54 TP504 TPAD14--OP-GP M_B_DQ42
AU33 DDR1_DQ[41]/DDR1_DQ[25]
M_B_A13 M_B_A14 AY44 AN52
13 M_B_DQ9 AF68 DDR1_DQ[9]/DDR0_DQ[25] 13 M_B_DQ39 AU30 DDR1_DQ[42]/DDR1_DQ[26] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] BA43 M_B_A13 13
M_B_DQ10 AH71 AU46 M_A_A13 M_B_DQ43 AT30 DDR1_DQ[43]/DDR1_DQ[27] M_B_A15_CAS#
13 M_B_DQ10 DDR1_DQ[10]/DDR0_DQ[26] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] M_A_A13 12 13 M_B_DQ40 DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] AY43 M_B_A14_WE# M_B_A15_CAS# 13 M_B_A15 AY43 AN53
M_B_DQ11 AH68 DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] AU48
M_A_A15_CAS# M_A_A15M_C_ABS_#D1Q2[40:47] 13 M_B_DQ41
M_B_DQ44 AR33 DDR1_DQ[44]/DDR1_DQ[28] DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14] AY44 M_B_A14_WE# 13
M_B_DQ[8:15] 13
13
M_B_DQ11
M_B_DQ12 M_B_DQ12 AF71
DDR1_DQ[11]/DDR0_DQ[27]
DDR1_DQ[12]/DDR0_DQ[28]
M_A_A14_WE#
DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] AT46 M_A_A16_RAS# M_A_A14_WE# 12 13 M_B_DQ42
M_B_DQ45 AP33 DDR1_DQ[45]/DDR1_DQ[29] DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16] AW 44
M_B_A16_RAS#
M_B_A16_RAS# 13 M_B_A16 AW44 N/A
13 M_B_DQ13 M_B_DQ13 AF69 AU50 M_A_A16_RAS# 12 M_B_DQ46 AR30 DDR1_DQ[46]/DDR1_DQ[30] BB44
M_B_DQ14 DDR1_DQ[13]/DDR0_DQ[29] DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] 13 M_B_DQ43 M_B_DQ47 DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] M_B_A2 M_B_BA0 13
13 M_B_DQ14 AH70 AU52 M_A_BA0 12 AP30 DDR1_DQ[47]/DDR1_DQ[31] AY47 M_B_A2 13
C M_B_DQ15 DDR1_DQ[14]/DDR0_DQ[30] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]
M_A_A2 13 M_B_DQ44 M_A_DQ48 DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2] M_B_BG1 AN52 N/A C
13 M_B_DQ15 AH69 DDR1_DQ[15]/DDR0_DQ[31] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] AY51 M_A_A2 12 AY31 DDR0_DQ[48]/DDR1_DQ[32] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] BA44 M_B_BA1 13
M_A_DQ16 BB65 AT48 13 M_B_DQ45 M_A_DQ49 AW 31 DDR0_DQ[49]/DDR1_DQ[33] M_B_A10_AP
12 M_A_DQ16 DDR0_DQ[16]/DDR0_DQ[32] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] M_A_BA1 12 DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] AW 46 M_B_A10_AP 13 M_B_BG0 AP52 N/A

ro
M_A_DQ17 AW 65 M_A_A10_AP M_A_DQ50 M_B_A1
12 M_A_DQ17
M_A_DQ18 DDR0_DQ[17]/DDR0_DQ[33] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] AT50 M_A_A1
M_A_A10_AP 12 13 M_B_DQ46
M_A_DQ51
AY29 DDR0_DQ[50]/DDR1_DQ[34] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] AY46
M_B_A0
M_B_A1 13
AW 63 BB50 M_A_A1 12 13 M_B_DQ47 AW 29 DDR0_DQ[51]/DDR1_DQ[35] BA46
12 M_A_DQ18 M_A_DQ19 DDR0_DQ[18]/DDR0_DQ[34] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] M_A_A0 M_A_DQ52 DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0] M_B_A0 13 M_B_PARITY AP43 N/A
AY63 AY50 12 M_A_DQ48 BB31 DDR0_DQ[52]/DDR1_DQ[36] DDR1_MA[3] BB46 M_B_A3
12 M_A_DQ19 M_A_DQ20 DDR0_DQ[19]/DDR0_DQ[35] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] M_A_A0 12 M_A_DQ53 M_B_A3 13
BA65 DDR0_DQ[20]/DDR0_DQ[36] DDR0_MA[3] BA50 M_A_A3 BA31 DDR0_DQ[53]/DDR1_DQ[37] DDR1_MA[4] BA47 M_B_A4
12 M_A_DQ20 M_A_DQ21 M_A_A3 12 12 M_A_DQ49 M_A_DQ54 M_B_A4 13 M_B_ALERT_N AN43 GND
AY65 DDR0_DQ[21]/DDR0_DQ[37] DDR0_MA[4] BB52 M_A_A4 BA29 DDR0_DQ[54]/DDR1_DQ[38]
12 M_A_DQ21 M_A_DQ22 M_A_A4 12 12 M_A_DQ50 M_A_DQ55 M_A_DQS_DN4
BA63 DDR0_DQ[22]/DDR0_DQ[38] BB29 DDR0_DQ[55]/DDR1_DQ[39] DDR0_DQSN[4]/DDR1_DQSN[0] BA38 M_A_DQS_DP4
M_A_DQ23 M_A_DQS_DN0 12 M_A_DQ51 M_A_DQ56 M_B_ACT_N AN53 N/A
12 M_A_DQ22 BB63 DDR0_DQ[23]/DDR0_DQ[39]
M_A_DQ24 DDR0_DQSN[0] AM70 M_A_DQ57
AY27 DDR0_DQ[56]/DDR1_DQ[40] DDR0_DQSP[4]/DDR1_DQSP[0] AY38 M_A_DQS_DN5
BA61 DDR0_DQ[24]/DDR0_DQ[40] M_A_DQS_DP0 12 M_A_DQ52
12 M_A_DQ23
M_A_DQ25 DDR0_DQSP[0] AM69 M_A_DQ58
AW 27 DDR0_DQ[57]/DDR1_DQ[41] DDR0_DQSN[5]/DDR1_DQSN[1] AY34
M_A_DQS_DN1 M_A_DQS_DP5
12 M_A_DQ24 AW 61 DDR0_DQ[25]/DDR0_DQ[41] DDR0_DQSN[1] AT69 12 M_A_DQ53 AY25 DDR0_DQ[58]/DDR1_DQ[42] DDR0_DQSP[5]/DDR1_DQSP[1] BA34 M_B_DQS_DN4
M_A_DQ26 M_A_DQS_DP1 M_A_DQ59
BB59 DDR0_DQ[26]/DDR0_DQ[42] DDR0_DQSP[1] AT70 12 M_A_DQ54 AW 25 DDR0_DQ[59]/DDR1_DQ[43] DDR1_DQSN[4]/DDR1_DQSN[2] AT38 M_B_DQS4

-X
12 M_A_DQ25
M_A_DQ27 AW 59 DDR0_DQ[27]/DDR0_DQ[43] M_B_DQS_DN0 M_A_DQ60 M_B_DQS_DP4
12 M_A_DQ26 M_A_DQ28 DDR1_DQSN[0]/DDR0_DQSN[2] AH66 M_B_DQS_DP0 M_B_DQS0 12 M_A_DQ55
M_A_DQ61
BB27 DDR0_DQ[60]/DDR1_DQ[44] DDR1_DQSP[4]/DDR1_DQSP[2] AR38 M_B_DQS_DN5
BB61 DDR0_DQ[28]/DDR0_DQ[44] DDR1_DQSP[0]/DDR0_DQSP[2] AH65 M_B_DQS_DN1 BA27 DDR0_DQ[61]/DDR1_DQ[45] DDR1_DQSN[5]/DDR1_DQSN[3] AT32 M_B_DQS_DP5
12 M_A_DQ27 M_A_DQ29 AY61 DDR0_DQ[29]/DDR0_DQ[45]
12 M_A_DQ56
M_A_DQ62 M_B_DQS5
12 M_A_DQ28 M_A_DQ30 DDR1_DQSN[1]/DDR0_DQSN[3] AG69 M_B_DQS1 12 M_A_DQ57 M_A_DQ63
BA25 DDR0_DQ[62]/DDR1_DQ[46] DDR1_DQSP[5]/DDR1_DQSP[3] AR32
BA59 DDR0_DQ[30]/DDR0_DQ[46] AG70 M_B_DQS_DP1 BB25 DDR0_DQ[63]/DDR1_DQ[47] M_A_DQS_DN6
M_A_DQ31 DDR1_DQSP[1]/DDR0_DQSP[3] M_A_DQS_DN2 12 M_A_DQ58 M_B_DQ48 DDR0_DQSN[6]/DDR1_DQSN[4] BA30 M_A_DQS_DP6
12 M_A_DQ29 AY59 DDR0_DQ[31]/DDR0_DQ[47] BA64 AU27 DDR1_DQ[48] AY30
M_B_DQ16 DDR0_DQSN[2]/DDR0_DQSN[4] 12 M_A_DQ59 M_B_DQ49 DDR0_DQSP[6]/DDR1_DQSP[4] 1D2V_S3
12 M_A_DQ30 AT66 DDR1_DQ[16]/DDR0_DQ[48] M_A_DQS_DP2 M_A_DQS_DN7
M_B_DQ17 DDR0_DQSP[2]/DDR0_DQSP[4] AY64 M_A_DQS_DN3 M_B_DQ50
AT27 DDR1_DQ[49] DDR0_DQSN[7]/DDR1_DQSN[5] AY26 M_A_DQS_DP7
AU66 DDR1_DQ[17]/DDR0_DQ[49] 12 M_A_DQ60
12 M_A_DQ31 DDR0_DQSN[3]/DDR0_DQSN[5] AY60 M_A_DQS_DP3 AT25 DDR1_DQ[50] DDR0_DQSP[7]/DDR1_DQSP[5] BA26 M_B_DQS_DN6
M_B_DQ18 AP65 DDR1_DQ[18]/DDR0_DQ[50] DDR0_DQSP[3]/DDR0_DQSP[5] BA60
M_B_DQ[48:55] 12 M_A_DQ61 M_B_DQ51 AU25 DDR1_DQ[51] DDR1_DQSN[6] AR25
13 M_B_DQ18
M_B_DQ[16:23]13 M_B_DQ16 M_B_DQS6

1
13 M_B_DQ19 M_B_DQ19 M_B_DQS_DN2 M_B_DQ52 M_B_DQS_DP6
M_B_DQ17 AN65 DDR1_DQ[19]/DDR0_DQ[51] DDR1_DQSN[2]/DDR0_DQSN[6] AR66 M_B_DQS_DP2 M_B_DQS2 12 M_A_DQ62 AP27 DDR1_DQ[52] DDR1_DQSP[6] AR27
M_B_DQ20 M_B_DQ53 M_B_DQS_DN7 R505
13 M_B_DQ20 AN66 DDR1_DQ[20]/DDR0_DQ[52] DDR1_DQSP[2]/DDR0_DQSP[6] AR65 12 M_A_DQ63 AN27 DDR1_DQ[53] DDR1_DQSN[7] AR22 M_B_DQS7 470R2F--GP
M_B_DQ21 M_B_DQS_DN3 M_B_DQ54 M_B_DQS_DP7
13 M_B_DQ21 AP66 DDR1_DQ[21]/DDR0_DQ[53] DDR1_DQSN[3]/DDR0_DQSN[7] AR61 AN25 DDR1_DQ[54] DDR1_DQSP[7] AR21

Te
13 M_B_DQ22 M_B_DQ22 AT65 DDR1_DQ[22]/DDR0_DQ[54] DDR1_DQSP[3]/DDR0_DQSP[7] AR60 M_B_DQS_DP3 M_B_DQS3 13 M_B_DQ48 M_B_DQ55 AP25 DDR1_DQ[55]
M_B_DQ23 13 M_B_DQ49 M_B_DQ56
13 M_B_DQ23 AU65 DDR1_DQ[23]/DDR0_DQ[55] AT22 DDR1_DQ[56] DDR1_ALERT# AN43 M_B_ALERT_N 13

2
M_B_DQ24 13 M_B_DQ50 M_B_DQ57 M_B_PARITY R504
13 M_B_DQ24 AT61 DDR1_DQ[24]/DDR0_DQ[56] DDR0_ALERT# AW 50 M_A_ALERT_N 12 AU22 DDR1_DQ[57] DDR1_PAR AP43 M_B_PARITY 13
M_B_DQ25 M_A_PARITY M_B_DQ58 SM_DRAMRST#
13 M_B_DQ25 AU61 DDR1_DQ[25]/DDR0_DQ[57] DDR0_PAR AT52 M_A_PARITY 12 13 M_B_DQ51 AU21 DDR1_DQ[58] DRAM_RESET# AT13 1 2 DDR4_DRAMRST# 12,13
M_B_DQ26 AP60 DDR1_DQ[26]/DDR0_DQ[58] M_B_DQ[56:63] 13 M_B_DQ52 M_B_DQ59 AT21 DDR1_DQ[59] DDR_RCOMP[0] AR18
SM_RCOMP_0 1 R501 2 121R2F--GP
M_B_DQ[24:31]13 M_B_DQ26
13
M_B_DQ27 M_B_DQ27 AN60 DDR1_DQ[27]/DDR0_DQ[59] DDR_VREF_CA AY67 V_SM_VREF_CA 12 13 M_B_DQ53 M_B_DQ60 AN22 DDR1_DQ[60] DDR_RCOMP[1] AT18
SM_RCOMP_1 1 R502 2 80D6R2F--L-GP 0R0402-PAD
M_B_DQ28 M_VREF_DQ_DIMM01 TP503 TPAD14--OP-GP M_B_DQ61 SM_RCOMP_2 1 R503 2 100R2F--L1-GP--U
13 M_B_DQ28 AN61 DDR1_DQ[28]/DDR0_DQ[60] DDR0_VREF_DQ AY68 13 M_B_DQ54 AP22 DDR1_DQ[61] DDR_RCOMP[2] AU18
13 M_B_DQ29 M_B_DQ29 AP61 DDR1_DQ[29]/DDR0_DQ[61] M_B_DQ62
DDR1_VREF_DQ BA67 V_SM_VREF_CNTB 13 13 M_B_DQ55 AP21 DDR1_DQ[62]

1
13 M_B_DQ30 M_B_DQ30 AT60 DDR1_DQ[30]/DDR0_DQ[62] M_B_DQ63 AN21 DDR1_DQ[63] DDR CH--B
M_B_DQ31 13 M_B_DQ56 #543016

ED501

ED502
13 M_B_DQ31 AU60 DDR1_DQ[31]/DDR0_DQ[63] DDR CH --A AW 67 SM_PGCNTL C501
DDR_VTT_CNTL

PESD5V0U1BL--GP-U1

PESD5V0U1BL--GP-U1
13 M_B_DQ57

SCD1U25V2KX--L-GP
DY

2 1
13 M_B_DQ58 SKYLAKE-U-GP
SKYLAKE-U-GP

ch
13 M_B_DQ59

2
13 M_B_DQ60 071.SKYLA.000U
071.SKYLA.000U 13 M_B_DQ61
Design Guideline:
13 M_B_DQ62
CPU BOM CTRL Layout Note:
SM_RCOMP keep routing length less than 500 mils.
13 M_B_DQ63
B
CPU BOM CTRL B
M_A_DQS_DN0 M_A_DQS_DN0 12 M_B_DQS_DN0 M_B_DQS_DN0 13
M_A_DQS_DN1 M_A_DQS_DN1 12 M_B_DQS_DN1 M_B_DQS_DN1 13
M_A_DQS_DN2 M_A_DQS_DN2 12 M_B_DQS_DN2 M_B_DQS_DN2 13
M_A_DQS_DN3 M_A_DQS_DN3 12 M_B_DQS_DN3 M_B_DQS_DN3 13

ni
M_A_DQS_DN4 M_A_DQS_DN4 12 M_B_DQS_DN4 M_B_DQS_DN4 13
M_A_DQS_DN5 M_A_DQS_DN5 12 M_B_DQS_DN5 M_B_DQS_DN5 13
M_A_DQS_DN6 M_A_DQS_DN6 12 M_B_DQS_DN6 M_B_DQS_DN6 13
M_A_DQS_DN7 M_A_DQS_DN7 12 M_B_DQS_DN7 M_B_DQS_DN7 13

M_B_DQS_DP0 M_B_DQS_DP0 13
M_A_DQS_DP0 M_A_DQS_DP0 12 M_B_DQS_DP1
1D2V_S3 3D3V_S0 M_B_DQS_DP1 13
M_A_DQS_DP1 M_A_DQS_DP1 12 M_B_DQS_DP2 M_B_DQS_DP2 13

ca
M_A_DQS_DP2 M_A_DQS_DP2 12 M_B_DQS_DP3 M_B_DQS_DP3 13
M_A_DQS_DP3 M_A_DQS_DP3 12 M_B_DQS_DP4
1

M_B_DQS_DP4 13
M_A_DQS_DP4 M_A_DQS_DP4 12 M_B_DQS_DP5
R506 M_B_DQS_DP5 13
220KR2F--GP M_A_DQS_DP5 M_A_DQS_DP5 12 M_B_DQS_DP6 M_B_DQS_DP6 13
G

M_A_DQS_DP6 M_A_DQS_DP6 12 M_B_DQS_DP7 M_B_DQS_DP7 13

M_A_DQS_DP7 M_A_DQS_DP7 12
2

SM_PGCNTL S D DDR_PG_OUT 51

l
Q501 DMN5L06K-
-7-GP
84.05067.031
2nd = 084.00138.0A31

A A

<Corrre Desiiign>

Wistron Corporation
21F,,, 88, Sec...1, HsiiinTai W u Rd...,,,Hsiiichih,

Eletro-XTechnical Eletro-XTechnical
Taiiipeiii Hsiiien 221,,, Taiiiwan,,, R.O.C...

Title

CPU_(DDR)
Siize Document Number Rev
A2
LV115 SKL-U -1
Date: Monday,,, Aprrriill25, 2016 Sheet 5 off 102
5 4 3 2 1
 5 4 3 2 1

Main Func = CPU CPU1S 19 OF 20

RESERVEDSIGNALS-1

E68
SKYLAKE_ULT [#543016 Rev0.9]
CFG[0] RSVD_TP#BB68 BB68
B67 CFG[1] RSVD_TP#BB69 BB69
D65

Eletro-XTechnical
CFG[2] RSVD_TP_AK13
CFG3 D67 1
99 CFG3 CFG[3] RSVD_TP#AK13 AK13 RSVD_TP_AK12
CFG4 E70 1 TP605 TPAD14--OP-GP
CFG[4] RSVD_TP#AK12 AK12
C68 CFG[5] TP606 TPAD14--OP-GP
D68 CFG[6] RSVD#BB2 BB2
C67 CFG[7] RSVD#BA3 BA3
F71 CFG[8]
G69 CFG[9]
F70 TP5 AU5 TP5_AU5 1
CFG[10]
G68 TP6 AT5 TP6_AT5 1 TP607 TPAD14--OP-GP
CFG[11]
H70 CFG[12] TP608 TPAD14--OP-GP
G71 CFG[13]
D H69 CFG[14] RSVD#D5 D5 D
G70 CFG[15] RSVD#D4 D4
RSVD#B2 B2
E63 CFG[16] RSVD#C2 C2
F63 CFG[17]
RSVD#B3 B3
E66 CFG[18] RSVD#A3 A3
F66 CFG[19]

49D9R2F--GP 2 1 R601 CFG_RCOMP E60 RSVD#AW 1 AW 1

CFG_RCOMP
RSVD#E1 E1
99 ITP_PMODE E8 ITP_PMODE RSVD#E2 E2
AY2 RSVD#AY2 RSVD#BA4 BA4
AY1 RSVD#AY1 RSVD#BB4 BB4
D1 RSVD#D1 RSVD#A4 A4
D3 RSVD#D3 RSVD#C4 C4
K46 RSVD#K46 BB5 TP4_BB5 1
TP4
K45 RSVD#K45 TP609 TPAD14--OP-GP
RSVD#A69 A69
AL25 RSVD#AL25 RSVD#B69 B69
AL27 RSVD#AL27

El
AY3 RSVD_AY3 1 R606 2
RSVD#AY3 0R2J--2-GP
C71 RSVD#C71
B70 RSVD#B70 RSVD#D71 D71
DY
F60 RSVD#F60 RSVD#C70 C70

A52 RSVD#C54 C54

RSVD#A52 RSVD#D54 D54
TP1_AY4
BA70 RSVD_TP#BA70 TP1 AY4 1
TP2_BB3 TP610 TPAD14--OP-GP
BA68 RSVD_TP#BA68 TP2 BB3 1

et
TP611 TPAD14--OP-GP
J71 RSVD#J71 VSS AY71
VSS_AY71 1 R602 2 0R0402-PAD #54469 CRB.
ZVM#
J68 RSVD#J68 ZVM# AR56 ZVM# 40

1 RSVD_F65 F65 VSS

RSVD_TP_AW7R1 SVD_TP#AW71 AW 71
TPAD14--OP-GP TP612 1 RSVD_G65 G65 VSS +VCCST_CPU
RSVD_TP_AW7R0 SVD_TP#AW70 AW 70
TPAD14--OP-GP TP613 R607
C MSM# 1 2 0R2J--2-GP MSM#_R 1 TP617 C
F61 RSVD#F61 MSM# AP56
E61 RSVD#E61 DY TPAD14--OP-GP
PROC_SELECT# C64

ro
PROC_SELECT# 1 2
R603
SKYLAKE-U-GP 100KR2J--1-GP

PCH strap pin: 071.SKYLA.000U CPU BOM CTRL

CFG3
1

[BDW Only]PHYSICAL_DEBUG_ENABLED (DFX PRIVACY)

-X
R604
DY 1KR2J--1-GP 0 : ENABLED
CFG[3] SET DFX ENABLED BIT IN DEBUG INTERFACE MSR
2

1 : DISABLED

(#543016)
CFG4

DISPLAY PORT PRESENCE STRAP

1

Te
R605
1KR2J--1-GP
1 : ENABLED
CFG[4]
An external Display Port device is connected to the Embedded Display Port.
2

1 : DISABLED (Default)
No Physical Display Port attached to Embedded DisplayPort*. No connect for disable.

SKL(#543016):

ch
Processor strap CFG[4] should be pulled low to enable embedded DisplayPort*
B B

ni
ca
l
A A

<Core Desiiign>

Wistron Corporation
21F,,, 88,,, Sec.1,,, Hsiiin Taiii W u Rd., Hsiiichiih,,,

Eletro-XTechnical Eletro-XTechnical
Taipei Hsiiien 221, Taiwan, R...O...C...

Tiitttlle

CPU_(RESERVED)
Siize Document Number Rev
A2
LV115 SKL-U -1
Datte:: Monday,,, Aprrriill25,,, 2016 Sheet 6 off 102
5 4 3 2 1
 5 4 3 2 1

Main Func = CPU

CPU1L 12 OF 20 CPU1M 13 OF 20
VCC_CORE VCC_CORE +VCCGT

Eletro-XTechnical
CPU POWER 11OF44
+VCCGT CPU POWER 22OF44

A30 VCC VCC G32 N70

VC C GT
A34 VCC VCC G33 A48 N71
SKYLAKE_UL
LT VC C GT SKYLAKE_ULLT VC C GT +VDDQ_CPU_CLK 1D2V_S3
A39 VCC VCC G35 A53 R63
VC C GT VC C GT
A44 VCC VCC G37 A58 R64
VC C GT VC C GT
AK33 VCC VCC G38 A62 R65
VC C GT VC C GT
AK35 VCC VCC G40 A66 R66
VC C GT VC C GT
AK37 VCC VCC G42 AA63 R67
VC C GT VC C GT C722
AK38 VCC VCC J30 AA64 VC C GT VC C GT R68 DY

2 1
AK40 J33 AA66 R69 SC1U10V2KX--1GP
VCC VCC VC C GT VC C GT
AL33 VCC VCC J37 AA67 R70
VC C GT VC C GT C719 +VCCIO
AL37 VCC VCC J40 AA69 R71
VC C GT VC C GT

2 1
AL40 K33 SC1U10V2KX--1GP CPU1N 14 OF 20
VCC VCC AA70 VC C GT VC C GT T62
AM32 K35 +VCCIO(ICCMAX.=2.73A
VCC VCC AA71 VC C GT VC C GT U65 CPU POWER 33OF44
AM33 VCC VCC K37 AC64 U68
VC C GT VC C GT
AM35 VCC VCC K38 AC65 U71 AU23 VD D Q AK28
D VC C GT VC C GT VCCIO D
AM37 VCC VCC K40 AC66 W 63 AU28 VD D Q AK30
VC C GT VC C GT SKYLAKE_UL
LT VCCIO
AM38 VCC VCC K42 AC67 W 64 AU35 VD D Q AL30
VC C GT VC C GT VCCIO
G30 VCC VCC K43 AC68 W 65 AU42 VD D Q AL42
VC C GT VC C GT VCCIO
AC69 W 66 BB23 VD D Q AM28
VC C GT VC C GT VCCIO
TPAD14-OP--GP TP701 1 +VCCCOREG0 K32 E32 AC70 W 67 BB32 VD D Q AM30
RSVD#KR3S2VD_K32 VCC_SENSE VCC_SENSE 46 VC C GT VC C GT VCCIO +VCCSA
E33 AC71 W 68 BB41 VD D Q AM42
VSS_SENSE VSS_SENSE 46 VC C GT VC C GT VCCIO
TPAD14-OP--GP TP702 1 +VCCCOREG1 AK32 J43 W 69 BB47 VD D Q
RSVD#ARKS3VD2_AK32 VC C GT VC C GT +VDDQ_CPU_CLK
B63 H_CPU_SVIDALRT# J45 W 70 BB51 VD D Q AK23

3A
VIDALERT# VC C GT VC C GT VC C SA
+V_EDRAM_VR AB62 A63 H_CPU_SVIDCLK J46 W 71 AK25
VC C OPC VIDSCK +VCCSTG VC C GT VC C GT VC C SA
P62 D64 H_CPU_SVIDDAT J48 Y62 SC10U6D3V3MX--GP2 1 C715 G23
VC C OPC VI D SOUT VC C GT VC C GT +VCCST_CPU VC C SA
V62 J50 AM40 VD D QC G25
VC C OPC VC C GT +VCCGT VC C SA
G20 +VCCFUSEPRG 1 R703 2 J52 G27
140mA +V1.8S_EDRAM H63 VC C _OPC _1P8
VC C STG
0R0603-PAD
J53
J55
VC C GT
VC C GT
VC C GT
VC C GTX
VC C GTX
AK42
AK43
SC1U10V2KX--1GP 2 1 C716
+VCCSTG
0.04 A A18
VC C ST
VC C SA
VC C SA
VC C SA
G28
J22
1 R702 2 VCC_EDRAM_FUSEPRG G61 VC C _OPC _1P8 J56 AK45 A22 VC C STG J23
VC C GT VC C GTX SC1U10V2KX--1GP 2 1 C717 VC C SA
J58 VC C GT VC C GTX AK46 VC C SA J27
0R0603-PAD VCCSENSE_EDRAM_VR AC63 J60 AK48 DY AL23 VC C PLL_OC K23
+V_EDRAM_VR VSSSENSE_EDRAM_VR AE63 VC C OPC _SENSE K48
VC C GT VC C GTX
AK50
1D2V_S3 VC C SA
K25
VSSOPC _SE NSE VC C GT VC C GTX VC C SA
K50 AK52 K20 VCCPLL K27

3A
VC C GT VC C GTX SCD1U16V2KX--3GP2 1 C718 VC C SA
+V_EOPIO_VR AE62 VC C EOPI O K52 VC C GT VC C GTX AK53 K21 VCCPLL VC C SA K28
AG62 VC C EOPI O K53 VC C GT VC C GTX AK55 VC C SA K30
K55 VC C GT VC C GTX AK56
#544669 CRB.
C701

C702

VCCSENSE_EOPIO_VR AL63 +V1.00U_CPU AM23 VCCIO_VR_FB

1

K56 AK58
C710 C711 VSSSENSE_EOPIO_VR AJ62 VC C EOPI O_SENSE VC C GT VC C GTX VCCIO_SENSE
AM22 VSSIO_VR_FB
23e 23e VSSEOPI O_SE NSE K58 VC C GT VC C GTX AK60 VSSIO_SENSE
2 1

2 1
SCD1U25V2KX--L-GP

SCD1U25V2KX--L-GP

23e 23e K60 AK70

2

VC C GT VC C GTX
SC10U6D3V3MX--GP

SC10U6D3V3MX--GP

L62 AL43
1D2V_S3 +VDDQ_CPU_CLK 0.12 A H21 VSSSA_SENSE 46
VC C GT VC C GTX VSSSA_SE NSE

C720
SKYLAKE-U--GP

1
L63 AL46 VCCSA_SENSE H20 VCCSA_SENSE 46

SCD1U16V2KX--3GP C721
VC C GT VC C GTX
L64 VC C GT VC C GTX AL50

2 1
071.SKYLA..000U L65 AL53 1 R705 2

2
VC C GT VC C GTX

SCD1U16V2KX--3GP
SKYLAKE-U--GP
L66 VC C GT VC C GTX AL56
L67 AL60 0R0603-PAD
VC C GT VC C GTX (#543016 SKL U/Y PDG rev1.0)
CPU BOM CTRL L68 VC C GT VC C GTX AM48 071.SKYLA..000U
L69 VC C GT VC C GTX AM50
+V_EOPIO_VR

El
L70 VC C GT VC C GTX AM52
L71 VC C GT VC C GTX AM53 CPU BOM CTRL
+V_EDRAM_VR R724
M62 VC C GT VC C GTX AM56
100R2J--2-GP
23e N63 VC C GT VC C GTX AM58
+VCCIO +VCCSTG +VCCIO
N64 VC C GT VC C GTX AU58
C703

C704

VCCSENSE_EDRAM_VR R710
23e 23e 1 2
1

N66 VC C GT VC C GTX AU63

1 2 VSSSENSE_EDRAM_VR N67 BB57 1 2 RN705
VC C GT VC C GTX 0R0402-PAD VCCIO_VR_FB
N69 BB66 1 4
2

VC C GT VC C GTX
SC10U6D3V3MX--GP

SC10U6D3V3MX--GP

R725 23e 2 3 VSSIO_VR_FB

100R2J--2-GP J70 VC C GT_SENSE
46 VCCGT_SENSE VCCGTX_SEN SE AK62 +VCCSTG(ICCMAX.=0.16A)
46 VSSGT_SENSE J69 VSSGT_SENSE VSSGTX_SEN SE AL61 SRN100J--3-GP

+V_EOPIO_VR SKYLAKE-U--GP

et
R729
100R2J--2-GP 23e +VCCSA
071.SKYLA..000U
1 2 VCCSENSE_EOPIO_VR RN706
1 2 VSSSENSE_EOPIO_VR CPU BOM CTRL 1 4 VCCSA_SENSE
2 3 VSSSA_SENSE
R731
23e +VCCSA +VCCSA
100R2J--2-GP
SRN100J--3-GP

VCC_CORE
C C723 C724 C
SC1U10V2KX--1GP SCD1U16V2KX--3GP RN701

ro
2 1

2 1
DY DY 2
R2
3 VCC_SENSE 46
1 4 VSS_SENSE 46
R1

SRN100F-1-GP

Layout Note:
1. Place close to CPU
2. VCC_SENSE/ VSS_SENSE
impedance=50 ohm
3. Length match<25mil
SVID DATA
Layout Note:
The total Length of Data and Clock (from CPU to each VR) must be equal (±0.1 inch).

-X
Route the Alert signal between the Clock and the Data signals.

+VCCST_CPU

+VCCGT

RN702
CLOSE TO CPU
1

1 R1
4 VCCGT_SENSE 46
R726 2 R2
3 VSSGT_SENSE 46
100R2F-L1-GP--U #544669
SRN100F-1-GP
2

R709

Te
H_CPU_SVIDDAT 1 2 VR_SVID_DATA 46
0R0402-PAD

SVID CLOCK
+VCCST_CPU

#544669
CLOSE TO VR
R723

ch
DY 54D9R2F-L1-GP
2 1

R732
H_CPU_SVIDCLK 1 2 VR_SVID_CLK 46
0R0402-PAD
SVID_543016:
B B

ni
+VCCST_CPU

#544669
1

CLOSE TO CPU
R727

ca
56R2J--4-GP
2

R728
H_CPU_SVIDALRT# 2 1 VR_SVID_ALERT# 46
220R2J--L2-GP

l
A A

Eletro-XTechnical Eletro-XTechnical
<Core Desiiign>

Wistron Corporation
21F,,, 88,,,Sec.1,,, Hsiiin Taiii W u Rd., Hsiiichiiih,,,
Taipei Hsiiien 221, Taiwan, R...O...C...

Title

CPU(VCC_CORE)
Siiize Document Number Rev
A1
LV115 SKL-U -1
Date: Monday,,, Apriiilll 25, 2016 Sheet 7 off 102
5 4 3 2 1
 5 4 3 2 1

Main Func = CPU

Eletro-XTechnical

D D

CPU1A 1 OF 20

SKYLAKE_ULT
57 HDMI_CRT_N0 E55 DDI1_TXN[0] EDP_TXN[0] C47 eDP_TX_CPU_N0 55
57 HDMI_CRT_P0 F55 DDI1_TXP[0] EDP_TXP[0] C46 eDP_TX_CPU_P0 55
57 HDMI_CRT_N1 E58 DDI1_TXN[1] EDP_TXN[1] D46 eDP_TX_CPU_N1 55
HDMI 57 HDMI_CRT_P1
57 HDMI_DATA0#
F58
F53
DDI1_TXP[1]
DDI1_TXN[2]
EDP_TXP[1]
EDP_TXN[2]
C45
A45
eDP_TX_CPU_P1 55

57 HDMI_DATA0 G53 DDI1_TXP[2] EDP_TXP[2] B45

57 HDMI_CLK# F56 DDI1_TXN[3] EDP_TXN[3] A47
57 HDMI_CLK G56 B47

El
DDI1_TXP[3] EDP_TXP[3]
56 PCH_DPC_N0 C50 DDI2_TXN[0] DDII EDP_AUXN E45 eDP_AUX_CPU_N 55
EDP
56 PCH_DPC_P0 D50 DDI2_TXP[0] EDP_AUXP F45 eDP_AUX_CPU_P 55
CRT 56
56
PCH_DPC_N1
PCH_DPC_P1
C52
D52
DDI2_TXN[1]
DDI2_TXP[1] EDP_DISP_UTIL B52
EDP_DISP_UTIL 1
A50 TP801 TPAD14-OP-GP
DDI2_TXN[2]
B50 DDI1_AUXN G50

et
DDI2_TXP[2]
D51 DDI2_TXN[3] DDI1_AUXP F50
C51 DDI2_TXP[3] DDI2_AUXN E48 PCH_DPC_AUXN 56
3D3V_S0
DDI2_AUXP F48 PCH_DPC_AUXP 56
DIISPLAY SIDEBANDS RSVD#G46 G46
RN801 RSVD#F46 F46
HDMI
C C
57 CPU_DP1_CTRL_CLK L13 GPP_E18/DDPB_CTRLCLK

ro
2 3 CPU_DP1_CTRL_CLK L12 GPP_E19/DDPB_CTRLDATA Strap
57 CPU_DP1_CTRL_DATA GPP_E13/DDPB_HPD0 L9 CPU_DP1_HPD 57
1 4 CPU_DP1_CTRL_DATA
GPP_E14/DDPC_HPD1 L7 CRT_HPD_PCH 56
N7 GPP_E20/DDPC_CTRLCLK EC_SMI#
56 DDPC_CLK
Strap GPP_E15/DDPD_HPD2 L6 EC_SMI# 24
SRN2K2J-1-GP 56 DDPC_DATA N8 GPP_E21/DDPC_CTRLDATA GPP_E16/DDPE_HPD3 N9 EC_SCI# 24
GPP_E17/EDP_HPD L10 EDP_HPD 55
RN804 Check +VCCIO TPAD14-OP-GP N11 GPP_E22
TP802 1 DDPD_CTRLDATA N12 Strap R12 L_BKLT_EN 55

-X
R801 GPP_E23 EDP_BKLTEN
2 3 DDPC_CLK
EDP_BKLTCTL
R11 L_BKLT_CTRL 55
1 4 DDPC_DATA 1 2 EDP_COMP E52 EDP_RCOMP EDP_VDDEN
U13 EDP_VDD_EN 55
24D9R2F-L-GP SKYLAKE-U-GP
SRN2K2J-1-GP
CPU BOM CTRL
CRT 071.SKYLA.000U
(#543016) The Skylake U/Y processor supports only two DDI ports - Port 1 and Port 2.

Te
3D3V_S0
(#543016) eDP_RCOMP Guideline
Signal Trace Isolation Resistor Length
Width Spacing Value 3D3V_S5 EC_SMI# 1 R802 2 10KR2J-3-GP

ch
eDP_RCOMP 20 mils 25 mils 24.9 Ω ±1% Max = 100 mils
EC_SMI# 1 R806 2 10KR2J-3-GP EC_SCI# 1 R803 2 10KR2J-3-GP

B DY DY B

(#543016) DDI Disabling and Termination Guidelines

ni
R804
1 2 L_BKLT_EN
Port Strap Enable Port Disable Port 100KR2J-4-GP

PU to 3.3 V with 2.2-k

Port 1 DDPB_CTRLDATA ±5% resistor NC

ca
PU to 3.3 V with 2.2-k R805
Port 2 DDPC_CTRLDATA ±5% resistor NC 1 2 CPU_DP1_HPD
100KR2J-4-GP

DY

l
A <Core Desiiign> A

Wistron Corporation
21F, 88, Sec.1, Hsiiin Taiii Wu Rd., Hsiiichiiih,
TaiiipeiiiHsiiien 221, Taiiiwan, R.O.C.
Design Guideline:

Eletro-XTechnical
Skylake processor signal eDP_RCOMP should be connected to the VCCIO rail via a single 24.9 ±1% Ω resistor.
Eletro-XTechnical
Tiiitllle

CPU_(DISPLAY)
Siize DocumentNumber Rev
A3
LV115 SKL-U -1
Date: Monday, Aprilll 25, 2016 Sheet 8 of 102
5 4 3 2 1
 5 4 3 2 1

Main Func = DDR4 On Board with Single Rank

1D2V_S3 ODDIMM1 1D2V_S3 ODDM

I M2

Eletro-XTechnical
B3 A3 M_A_DQ7M_A_DQ7 5 B3 A3 M_A_DQ24 M_A_DQ24 5
B9
D1
VDD
VDD
VDD
DQU0
DQU1
DQU2
B8 M_A_DQ0M_A_DQ0 5
C3 M_A_DQ3M_A_DQ35
B9
D1
VDD
VDD
VDD
DQU0
DQU1
DQU2
B8 M_A_DQ25 M_A_DQ25 5
C3 M_A_DQ26 M_A_DQ26 5 Ref. 549360_SKL_U_6L WP P47
G7 C7 M_A_DQ4M_A_DQ45 G7 C7 M_A_DQ27 M_A_DQ27 5
VDD DQU3 VDD DQU3
J1 C2 M_A_DQ6M_A_DQ65 J1 C2 M_A_DQ28 M_A_DQ28 5
VDD DQU4 VDD DQU4 1D2V_S3 M_VREF_DQ_DIMMB RR12082 1 243R2F--L1-GPP DDR4_ZQ_RAM1
J9 C8 M_A_DQ5M_A_DQ55 J9 C8 M_A_DQ29 M_A_DQ29 5
VDD DQU5 VDD DQU5 ODDIIMM
L1 D3 M_A_DQ2M_A_DQ25 L1 D3 M_A_DQ30 M_A_DQ30 5 RR1212
VDD DQU6 VDD DQU6
L9 D7 M_A_DQ1M_A_DQ15 L9 D7 M_A_DQ31 M_A_DQ31 5 1K8R2F--GPP ODDIIMM
VDD DQU7 VDD DQU7
R1 R1 RR1214
VDD M_A_DQ115 VDD M_A_DQ16 1 2
T9 G2 M_A_DQ11 T9 G2 M_A_DQ16 5
ODDIIMM
VDD DQL0 VDD DQL0
F7 M_A_DQ8 M_A_DQ85 F7 M_A_DQ23 M_A_DQ23 5 1 2 12
V_SM_VREF_CA 5
RR12092 1 243R2F--L1-GPP DDR4_ZQ_RAM2
DQL1 DQL1
A1 H3 M_A_DQ14 M_A_DQ14 5 A1 H3 M_A_DQ18 M_A_DQ18 5 ODDIIMM
VDDQ DQL2 VDDQ DQL2
A9
VDDQ H7 M_A_DQ12 M_A_DQ12 5 A9
VDDQ H7 M_A_DQ19 M_A_DQ19 5 RR1213ODIID M M
DQL3 DQL3 2D7R2F--1-GPP
C1 H2 M_A_DQ15M_A_DQ15 5 C1 H2 M_A_DQ20 M_A_DQ20 5 1K8R2F--GPP
VDDQ DQL4 VDDQ DQL4
D9 H8 M_A_DQ9 M_A_DQ9 5 D9 H8 M_A_DQ21 M_A_DQ21 5 CC1221 SSCCDD022U16V2KXX-
VDDQ DQL5 J3 VDDQ DQL5
C1201 close to ODIMM1.M1 F2
VDDQ DQL6 M_A_DQ10
M_A_DQ13
M_A_DQ10 5 F2
VDDQ DQL6
J3 M_A_DQ22M_A_DQ22 5 3GPP RR12102 1 243R2F--L1-GPP DDR4_ZQ_RAM3
F8
G1
VDDQ DQL7
J7 M_A_DQ13 5 C1202 close to ODIMM2.M1 F8
G1
VDDQ DQL7
M_A_DQ17
J7 M_A_DQ17 5 ODDIIMM
+V_VREF_PATH3
ODDIIMM

VDDQ VDDQ
G9 A7 M_A_DQS_DN0
M_A_DQS_DN0 5 G9 A7 M_A_DQS_DN3
M_A_DQS_DN3 5
VDDQ DQSU_C M_A_DQS_DP0 VDDQ DQSU_C M_A_DQS_DP3 RR1215
J2 B7 M_A_DQS_DP0 5 J2 B7 M_A_DQS_DP3 5
2D5V_S3 VDDQ DQSU_T 2D5V_S3 VDDQ DQSU_T RR12112 1 243R2F--L1-GPP DDR4_ZQ_RAM4

212 1
J8 J8 24D9R2F--L-GPP
VDDQ VDDQ ODDIIMM
D F3 M_A_DQS_DN1
M_A_DQS_DN1 5 F3 M_A_DQS_DN2
M_A_DQS_DN2 5 ODDIIMM
D
M_VREF_DQ_DIMMB DQSL_C M_A_DQS_DP1 1D2V_S3 M_VREF_DQ_DIMMB DQSL_C M_A_DQS_DP2 1D2V_S3
B1 G3 M_A_DQS_DP1 5 B1 G3 M_A_DQS_DP2 5
VPP DQSL_T VPP DQSL_T
R9 R9
VPP VPP
E2 E2
M1 DMU#/DBIU# E7 M1 DMU#/DBIU# E7
VREFCA DML#/DBIL# VREFCA DML#/DBIL#
DDR4_ZQ_RAM1 F9 DDR4_ZQ_RAM2 F9
ZQ P9 ZQ P9
ALERT# M_A_ALERT_N 5 ALERT# M_A_ALERT_N 5
C1201 S M_A_A0 P3 A0 C1202 M_A_A0 P3 A0
5 M_A_A0 5 M_A_A0
21

21
SC
CD047U25V2KX
X-GP
P M_A_A1 P7 A1 M2 SSCCDD047U25V2KXX--GPP M_A_A1 P7 A1 M2
5 M_A_A1 M_A_A2 R3 A2 BG0 M_A_BG0 5 5 M_A_A1 M_A_A2 R3 A2 BG0 M_A_BG0 5
OD
DIM M OD
DIM M
5 M_A_A2 M_A_A3 N7 A3 N2 5 M_A_A2 M_A_A3 N7 A3 N2
BA0 M_A_BA0 5 BA0 M_A_BA0 5
5 M_A_A3 M_A_A4 N3 A4 N8 5 M_A_A3 M_A_A4 N3 A4 N8
BA1 M_A_BA1 5 BA1 M_A_BA1 5
5 M_A_A4 M_A_A5 P8 A5 5 M_A_A4 M_A_A5 P8 A5
5 M_A_A5 M_A_A6 P2 A6 T7 5 M_A_A5 M_A_A6 P2 A6 T7
M_A_A7 R8 A7 NC#T7 M_A_A7 R8 A7 NC#T7
5 M_A_A6 5 M_A_A6
M_A_A8 R2 A8 M_A_A8 R2 A8
5 M_A_A7 M_A_A9 R7 A9 5 M_A_A7 M_A_A9 R7 A9
B2 B2
5 M_A_A8 M_A_A10_APM3 A10/AP VSS 5 M_A_A8 M_A_A10_APM3 A10/AP VSS
E1 E1
5 M_A_A9 M_A_A11 T2 A11 VSS 5 M_A_A9 M_A_A11 T2 A11 VSS
E9 E9
5 M_A_A10_AP M_A_A12 M7 VSS 5 M_A_A10_AP M_A_A12 M7 VSS
A12/BC# G8 A12/BC# G8
M_A_A13 T8 A13 VSS M_A_A13 T8 A13 VSS
5 M_A_A11 K1 5 M_A_A11 K1
M_A_A14_WE# L2 WE#/A14 VSS M_A_A14_WE# L2 WE#/A14 VSS
5 M_A_A12 K9 5 M_A_A12 K9
VSS VSS
5 M_A_A13 M9 5 M_A_A13 M9
VSS VSS
K2 N1 K2 N1
5 M_A_A14_WE#
5 M_A_CKE0 CKE VSS 5 M_A_A14_WE#
5 M_A_CKE0 CKE VSS
K8 T1 K8 T1
5 M_A_CLK#0 CK_C VSS 5 M_A_CLK#0 CK_C VSS
K7 K7
5 M_A_CLK0 CK_T 5 M_A_CLK0 CK_T
A2 A2
VSSQ VSSQ
5 M_A_A16_RAS# M_A_A16_RAS# L8
VSSQ
A8 5 M_A_A16_RAS# M_A_A16_RAS# L8 VSSQ
A8
M_A_A15_CAS# M8 RAS# C9 5 M_A_A15_CAS# M_A_A15_CAS# M8
RAS# C9
5 M_A_A15_CAS# CAS# VSSQ CAS# VSSQ
D2 D2
VSSQ VSSQ
5 M_A_ODT0 K3 D8 5 M_A_ODT0 K3 D8
ODT VSSQ ODT VSSQ
5 M_A_ACT_N L3 E3 5 M_A_ACT_N L3 E3
ACT# VSSQ ACT# VSSQ
L7 E8 L7 E8
5 M_A_CS#0 CS# VSSQ 5 M_A_CS#0 CS# VSSQ
TTPPAADD14-OPPG
- PP TTPP1204 1DDR4_TEST_MODE_1 N9 F1 TTPPAADD14-OPPG
- PP TTPP1205 1DDR4_TEST_MODE_2 N9 F1
TEN VSSQ TEN VSSQ
P1 H1 P1 H1
5,13 DDR4_DRAMRST# RESET# VSSQ 5,13 DDR4_DRAMRST# RESET# VSSQ
T3 H9 T3 H9
5 M_A_PARITY PAR VSSQ 5 M_A_PARITY PAR VSSQ

KK4A4G165WDD-BBCCPPBB-GPP K4AA44G116655WDD-BCPB-GPP

072.44165.000U 072.44165.000U

ODIMM BOM CTRL ODIMM BOM CTRL

1D2V_S3 ODDM
I M4

El
1D2V_S3 ODDM
I M3
B3 A3 M_A_DQ62 M_A_DQ62 5
VDD DQU0
B3 A3 M_A_DQ46 M_A_DQ46 5 B9 B8 M_A_DQ56 M_A_DQ56 5
VDD DQU0 VDD DQU1
B9 B8 M_A_DQ47 M_A_DQ47 5 D1 C3 M_A_DQ63 M_A_DQ63 5
D1
G7
VDD
VDD
VDD
DQU1
DQU2
DQU3
C3 M_A_DQ45 M_A_DQ45 5
C7 M_A_DQ40 M_A_DQ40 5
G7
J1
VDD
VDD
VDD
DQU2
DQU3
DQU4
C7 M_A_DQ60 M_A_DQ60 5
C2 M_A_DQ59 M_A_DQ59 5 DDR4 On Board RAM Power Decouple Cap
J1 C2 M_A_DQ42 M_A_DQ42 5 J9 C8 M_A_DQ61 M_A_DQ61 5
VDD DQU4 VDD DQU5
J9 C8 M_A_DQ44 M_A_DQ44 5 L1 D3 M_A_DQ58 M_A_DQ58 5
VDD DQU5 VDD DQU6
L1 D3 M_A_DQ43 M_A_DQ43 5 L9 D7 M_A_DQ57 M_A_DQ57 5
VDD DQU6 VDD DQU7
L9 D7 M_A_DQ41 M_A_DQ41 5 R1
VDD DQU7 VDD
R1 T9 G2 M_A_DQ51 M_A_DQ51 5
VDD VDD DQL0 1D2V_S3
T9 G2 M_A_DQ32 M_A_DQ32 5 F7 M_A_DQ53 M_A_DQ53 5

A1
VDD

VDDQ
DQL0
DQL1
DQL2
F7 M_A_DQ33 M_A_DQ33 5
H3 M_A_DQ34 M_A_DQ34 5
A1
A9
VDDQ
VDDQ
DQL1
DQL2
DQL3
H3 M_A_DQ54 M_A_DQ54 5
H7 M_A_DQ52 M_A_DQ52 5 VDDQ/VDD 10uF x10
A9
C1
VDDQ DQL3
H7 M_A_DQ35 M_A_DQ35 5
H2 M_A_DQ36 M_A_DQ36 5
C1
D9
VDDQ DQL4
H2 M_A_DQ50 M_A_DQ50 5
H8 M_A_DQ49 M_A_DQ49 5
LV115 use 1ch memory down , only need half of Caps
VDDQ DQL4 VDDQ DQL5
D9 H8 M_A_DQ37 M_A_DQ37 5 F2 J3 M_A_DQ55 M_A_DQ55 5
VDDQ DQL5 VDDQ DQL6
F2
VDDQ DQL6
J3 M_A_DQ38 M_A_DQ38 5 C1204 close to ODIMM4.M1 F8
VDDQ DQL7
J7 M_A_DQ48 M_A_DQ48 5

1
F8 J7 M_A_DQ39 M_A_DQ39 5 G1 CC1205 CC1206 CC1207 CC1208 CC1209 CC1210 CC1265 CC1266 CC1267 CC1268
VDDQ DQL7 VDDQ
C1203 close to ODIMM3.M1

et
G1 G9 A7 M_A_DQS_DN7 M_A_DQS_DN7 5 SSCC10U6D3V3MXX--L-GPP SSCC10U6D3V3MXX-L-GPP SSCC10U6D3V3MXX--L-GPP SSCC10U6D3V3MXX-L-GPP SSCC10U6D3V3MXX--L-GPP SSCC10U6D3V3MXX-L-GPP SSCC10U6D3V3MXX--L-GPP SSCC10U6D3V3MXX--L-GPP SSCC10U6D3V3MXX-L-GPP SSCC10U6D3V3MXX-L-GPP
VDDQ VDDQ DQSU_C
G9 A7 J2 B7 M_A_DQS_DP7 M_A_DQS_DP7 5 OD
DIM M ODIID M M ODIID M M ODIID M M ODIID M M ODIID M M ODIID M M ODIID M M ODIID M M ODIID M M
VDDQ DQSU_C VDDQ DQSU_T

2
2

2
J2 M_A_DQS_DN5 2D5V_S3 J8
VDDQ M_A_DQS_DN5 5 VDDQ
2D5V_S3 J8 B7 M_A_DQS_DP5 F3 M_A_DQS_DN6 M_A_DQS_DN6 5
VDDQ DQSU_T F3 M_A_DQS_DN4 M_A_DQS_DP5 5 DQSL_C G3 M_A_DQS_DP6 1D2V_S3
M_A_DQS_DN4 5 M_VREF_DQ_DIMMB B1 M_A_DQS_DP6 5
DQSL_C VPP DQSL_T
M_VREF_DQ_DIMMB B1 G3 M_A_DQS_DP4 M_A_DQS_DP4 5 1D2V_S3 R9
VPP DQSL_T VPP
R9 E2
VPP DMU#/DBIU#
E2 M1 E7
DMU#/DBIU# DML#/DBIL#
M1 E7 DDR4_ZQ_RAM4 VREFCA
F9
DDR4_ZQ_RAM3 F9 VREFCA
ZQ
DML#/DBIL#

ALERT#
P9
M_A_ALERT_N 5
ZQ
ALERT#
P9
M_A_ALERT_N 5
1D2V_S3
VDDQ/VDD 1uF x32
C1204 5 M_A_A0 M_A_A0 P3
A0
21

C C1203 S 5 M_A_A0 M_A_A0 P3 SSCCDD047U25V2KXX--GPP 5 M_A_A1 M_A_A1 P7 M2 M_A_BG0 5 C

BG0
M_A_A1 P7 A0 M_A_A2 R3 A1
21

SC
CD047U25V2KX
X-GP
P M2 OD
DIM M
5 M_A_A1 BG0 M_A_BG0 5 5 M_A_A2
OD
DIM M M_A_A2 R3 A1 M_A_A3 N7 A2 N2
5 M_A_A2 A2 5 M_A_A3 A3 BA0 M_A_BA0 5
M_A_A3 N7 N2 M_A_BA0 5 M_A_A4 N3 N8 CC1213 CC1214 CC1215 CC1216 CC1217 CC1218 CC1219 CC1220 CC1222 CC1223
5 M_A_A3 M_A_A4 N3 A3 BA0 N8 BA1 5 M_A_A4 M_A_A5 P8 A4 BA1 M_A_BA1 5 SSCC1U10V2KXX--L1-GPP SSCC1U10V2KXX--L1-GPP SSCC1U10V2KXX-L1-GPP SSCC1U10V2KXX--L1-GPP SSCC1U10V2KXX-L1-GPP SSCC1U10V2KXX--L1-GPP SSCC1U10V2KXX-L1-GPP SSCC1U10V2KXX--L1-GPP SSCC1U10V2KXX-L1-GPP SSCC1U10V2KXX-L1-GPP
A4 M_A_BA1 5 A5

21

21

21

21

21

21
T7

21

21

21

21
5 M_A_A4 M_A_A5 P8 5 M_A_A5 M_A_A6 P2 NC#T7
ODIID M M ODDIIMM ODDIIMM ODDIIMM ODDIIMM ODDIIMM ODDIIMM ODDIIMM ODDIIMM ODDIIMM

5 M_A_A5 M_A_A6 P2 A5 T7 5 M_A_A6 M_A_A7 R8 A6

ro
M_A_A7 R8 A6 NC#T7 M_A_A8 R2 A7
5 M_A_A6 A7 5 M_A_A7 A8
M_A_A8 R2 M_A_A9 R7 B2
5 M_A_A7 5 M_A_A8
M_A_A9 R7 A8 B2 M_A_A10_APM3 A9 VSS E1
5 M_A_A8 A9 VSS 5 M_A_A9 A10/AP VSS
M_A_A10_APM3 E1 M_A_A11 T2 E9
5 M_A_A9 M_A_A11 T2 A10/AP VSS E9 5 M_A_A10_AP M_A_A12 M7 A11 VSS G8
5 M_A_A10_AP M_A_A12 M7 A11 VSS G8 5 M_A_A11 M_A_A13 T8 A12/BC# VSS K1
A12/BC# VSS A13 VSS 1D2V_S3
5 M_A_A11 M_A_A13 T8 K1 5 M_A_A12 M_A_A14_WE# L2 W E#/A14 K9
VSS VSS M9
5 M_A_A12 M_A_A14_WE# L2 A13 W E#/A14 VSS
K9 5 M_A_A13 VSS
5 M_A_A13 M9 5 M_A_A14_WE# K2 N1
VSS 5 M_A_CKE0
5 M_A_CKE0 K2 N1 K8 CKE VSS T1
5 M_A_A14_WE# CKE VSS T1 5 M_A_CLK#0 K7 CK_C VSS
K8
5 M_A_CLK#0 CK_C VSS 5 M_A_CLK0 CK_T
K7 A2
5 M_A_CLK0 CK_T M_A_A16_RAS# L8 RAS# VSSQ A8
A2 5 M_A_A16_RAS# VSSQ CC1237 CC1232 CC1238 CC1235 CC1236 CC1234 CC1249 CC1250 CC1251 CC1252 SSCC1U10V2KXX--
VSSQ M_A_A15_CAS# M8 CAS#
5 M_A_A16_RAS# M_A_A16_RAS# L8 A8 5 M_A_A15_CAS# C9 L1-GPPSSCC1U10V2KXX--L1-GPP SSCC1U10V2KXX--L1-GPP SSCC1U10V2KXX--L1-GPP SSCC1U10V2KXX--L1-GPP SSCC1U10V2KXX--L1-GPP SSCC1U10V2KXX-L1-GPP SSCC1U10V2KXX--L1-GPP SSCC1U10V2KXX-L1-GPP SSCC1U10V2KXX-L1-GPP
M8 RAS# VSSQ C9 VSSQ D2

21

21

21

21

21
M_A_A15_CAS#

21

21

21

21

21
5 M_A_A15_CAS# CAS#
ODIID M M ODDIIMM ODDIIMM ODDIIMM ODDIIMM ODDIIMM ODDIIMM ODDIIMM ODDIIMM ODDIIMM
VSSQ D2 K3 VSSQ D8
VSSQ 5 M_A_ODT0 ODT VSSQ
5 M_A_ODT0 K3 D8 L3 E3
5 M_A_ACT_N
L3 ODT VSSQ E3 L7 ACT# VSSQ E8
5 M_A_ACT_N ACT# VSSQ 5 M_A_CS#0 CS# VSSQ
L7 E8 TTPPAADD14-OPPG
- PP TTPP1207 1DDR4_TEST_MODE_4 N9 F1
TTPPAADD14-OPPG
- PP TTPP1206 1DDR4_TEST_MODE_3 5 M_A_CS#0 N9 CS# VSSQ F1 P1 TEN VSSQ H1

-X
P1 TEN VSSQ H1 5,13 DDR4_DRAMRST#
5,13 DDR4_DRAMRST# T3 RESET# VSSQ H9
RESET# VSSQ 5 M_A_PARITY PAR VSSQ
5 M_A_PARITY T3 H9
PAR VSSQ
K4AA44G116655WDD-BCPB-GPP 1D2V_S3
KK4A4G165WDD-BBCCPPBB-GPP
072.44165.000U
072.44165.000U
ODIMM BOM CTRL
ODIMM BOM CTRL CC1253 CC1254 CC1255 CC1256 CC1257 CC1258 CC1259 CC1260 CC1261 CC1262
SSCC1U10V2KXX--L1-GPP SSCC1U10V2KXX--L1-GPP SSCC1U10V2KXX-L1-GPP SSCC1U10V2KXX--L1-GPP SSCC1U10V2KXX-L1-GPP SSCC1U10V2KXX--L1-GPP SSCC1U10V2KXX-L1-GPP SSCC1U10V2KXX--L1-GPP SSCC1U10V2KXX-L1-GPP SSCC1U10V2KXX-L1-GPP

21

21

21

21

21
21

21

21

21

21
OD
DIM M ODIID M M ODIID M M ODIID M M ODIID M M ODIID M M ODIID M M ODIID M M ODIID M M ODIID M M

1D2V_S3

ALERT
RR12201 2 49D9R2F--GPP ODDIIMM M_A_ALERT_N

1D2V_S3

0D6V_S0

Te
RR12211 2 36R2F--1-GPP ODDIIMM M_A_CLK0 CC1263 CC1264
CLK SSCC1U10V2KX-X L1-GPPSSCC1U10V2KX-X L1-GPP

21
21
ODIID M M ODDIIMM
RR12221 2 36R2F--1-GPP ODDIIMM M_A_CLK#0

RR1223 1
RR1224 1
2 34D8R2F--GPP ODDIIMM M_A_CKE0
2 34D8R2F--GPP ODDIIMM M_A_A0
2D5V_S3
VPP 1uF x16
RR1225 1 2 34D8R2F--GPP ODDIIMM M_A_A1
RR1226 1 2 34D8R2F--GPPODDIIMMODDIIMM M_A_A2
2 34D8R2F--GPP M_A_A3
RR1227 1 2 34D8R2F--GPP ODDIIMM M_A_A4
RR1228 1 2 34D8R2F--GPP ODDIIMM M_A_A5 CC1224 CC1225 CC1226 CC1227 CC1228 CC1229 CC1230 CC1231 CC1269 CC1270
RR1229 1 2 34D8R2F--GPP ODDIIMM M_A_A6 SSCC1U10V2KXX--L1-GPP SSCC1U10V2KXX--L1-GPP SSCC1U10V2KXX-L1-GPP SSCC1U10V2KXX--L1-GPP SSCC1U10V2KXX-L1-GPP SSCC1U10V2KXX--L1-GPP SSCC1U10V2KXX-L1-GPP SSCC1U10V2KXX--L1-GPP SSCC1U10V2KXX-L1-GPP SSCC1U10V2KXX--L1-GPP

21

21

21

21

21

21
CTRL/CKE/CMD

21

21

21

21
RR1230 1 2 34D8R2F--GPPODDIIMMODDIIMM M_A_A7
OD
DIM M ODIID M M ODIID M M ODIID M M ODIID M M ODIID M M ODIID M M ODIID M M ODIID M M ODIID M M

RR1231 1 2 34D8R2F--GPP M_A_A8

RR1232 1 2 34D8R2F--GPP ODDIIMM M_A_A9
RR1233 1 2 34D8R2F--GPP ODDIIMM M_A_A10_AP
ODDIIMM
RR1234 1 2 34D8R2F--GPP M_A_A11

ch
RR1235 1 2 34D8R2F--GPPODDIIMMODDIIMM M_A_A12
2 34D8R2F--GPP M_A_A13
RR1236 1 2 34D8R2F--GPP ODDIIMM M_A_A14_WE# 2D5V_S3
RR1237 1 2 34D8R2F--GPP ODDIIMM M_A_A15_CAS#
2 34D8R2F--GPP ODDIIMM M_A_A16_RAS#
RR1238 1
RR1239 1 2 34D8R2F--GPP ODDIIMM M_A_BA0
RR12421 2 34D8R2F--GPP ODDIIMM M_A_BA1
RR12401 1
RR1243 2 34D8R2F--GPP ODDIIMM M_A_BG0
B
RR1241
RR12441 1
2 34D8R2F--GPP ODDIIMM M_A_PARITY CC1271 CC1272 CC1273 CC1274 CC1275 CC1276 SSCC1U10V2KX--X L1- B
RR1245 1 2 34D8R2F--GPP ODDIIMM M_A_ACT_N GPPSSCC1U10V2KX--X L1-GPPSSCC1U10V2KX-X L1-GPPSSCC1U10V2KX-X L1-GPPSSCC1U10V2KX-X L1-GPPSSCC1U10V2KX-X L1-GPP

21

21
21

21

21

21
RR1246 1 2 34D8R2F--GPP ODDIIMM M_A_CS#0 ODIID M M ODDIIMM ODDIIMM ODDIIMM ODDIIMM ODDIIMM
ODDIIMM
RR1247 1 2 34D8R2F--GPP M_A_ODT0

2D5V_S3

VPP 10uF x5

ni
CC1233 CC1211 CC1212 CC1277 CC1278
0D6V_S0 SSCC10U6D3V3MXX--L-GPP SSCC10U6D3V3MXX-L-GPP SSCC10U6D3V3MXX--L-GPP SSCC10U6D3V3MXX-L-GPP SSCC10U6D3V3MXX--L-GPP

21

21

21

21
VTT 1uF x16
OD
DIM M ODIID M M ODIID M M ODIID M M ODIID M M

21
CC1239 CC1240 CC1241 CC1242 CC1243 CC1244 CC1245 CC1246 CC1279 CC1280
SSCC1U10V2KXX--L1-GPP SSCC1U10V2KXX--L1-GPP SSCC1U10V2KXX-L1-GPP SSCC1U10V2KXX--L1-GPP SSCC1U10V2KXX-L1-GPP SSCC1U10V2KXX--L1-GPP SSCC1U10V2KXX-L1-GPP SSCC1U10V2KXX--L1-GPP SSCC1U10V2KXX-L1-GPP SSCC1U10V2KXX--L1-GPP
21

21

21

21

21

21
21

21

21

21
0D6V_S0
VTT 10uF x4
ODIID M M ODDIIMM ODDIIMM ODDIIMM ODDIIMM ODDIIMM ODDIIMM ODDIIMM ODDIIMM ODDIIMM

ca
1
CC1247 CC1248 CC1287 CC1288
SSCC10U6D3V3MXX--L-GPP SSCC10U6D3V3MXX-L-GPP SSCC10U6D3V3MXX--L-GPP SSCC10U6D3V3MXX--L-GPP

21

21

21
0D6V_S0 OD
DIM M ODIID M M ODIID M M ODIID M M

2
CC1281 CC1282 CC1283 CC1284 CC1285 CC1286
SSCC1U10V2KXX--L1-GPP SSCC1U10V2KXX--L1-GPP SSCC1U10V2KXX-L1-GPP SSCC1U10V2KXX--L1-GPP SSCC1U10V2KXX-L1-GPP SSCC1U10V2KXX--L1-GPP
21

21

21
21

21

21
ODIID M M ODDIIMM ODDIIMM ODDIIMM ODDIIMM ODDIIMM

l
DDR4_DRAMRST#

For ODIMM1,ODIMM2,ODIMM3,ODIMM4
A A

ED1201 ED1202 ED1203 ED1204

PESD55V0UU11BL--GP-UU11

PESD55V0UU11BL--GP-UU11

PESD55V0UU11BL--GP-UU11

PESD55V0UU11BL--GP-UU11

ODDIIMM ODDIIMM ODDIIMM ODDIIMM

2 1

2 1

2 1

2 1

<<<CCCoreee DDDesiiign>

Eletro-XTechnical Eletro-XTechnical
Wistron Corporation
222111FFF, 888888,SSSeeeccc.1,HHHssinnnTTTaaai WuuuRRRddd., HHHssiccchhhihhh,
TTTaipei HHHssiien 221, TTTaiwwwan,RRR.O.CCC.
Titititle
e
DDR4-SODIMM1
SSSizzzeee DDDocument NNNumber RRRev
A0
LV115 SKL-U -1
DDDate:Monday,,,AAApr25,2016
il SSSheet12 ooof 102
5 4 3 2 1
 5 4 3 2 1

DIMM1A 1 OF 4 DIMM1B 2 OF 4 DIMM1D 4 OF 4

11
5 M_B_A0 144 A0 8 M_B_DQ10 5 M_B_DQS_DN1 5 1 99
DQ0 DQS0_C 13 VSS VSS
5 M_B_A1 133 A1 7 M_B_DQ14 5 M_B_DQS_DP1 5 2 VSS 102
DQ1 DQS0_T 32 VSS
5 M_B_A2 132 A2 20 M_B_DQ15 5 M_B_DQS_DN0 5 5 VSS 103
DQ2 DQS1_C 34 VSS
5 M_B_A3 131 A3 21 M_B_DQ12 5 M_B_DQS_DP0 5 6 VSS 106
DQ3 DQS1_T 53 VSS
5 M_B_A4 128 A4 4 M_B_DQ11 5 M_B_DQS_DN2 5 9 VSS 107
DQ4 DQS2_C 55 VSS
5 M_B_A5 126 A5 3 M_B_DQ9 5 M_B_DQS_DP2 5 10 VSS 167
DQ5 DQS2_T 74 VSS
5 M_B_A6 127 A6 16 M_B_DQ13 5 M_B_DQS_DN3 5 14 VSS 168
DQ6 DQS3_C 76 VSS
5 M_B_A7 122 M_B_DQ8 5 M_B_DQS_DP3 5 171

Eletro-XTechnical
A7 DQ7 17 DQS3_T 177 15 VSS VSS
5 M_B_A8 125 A8 28 M_B_DQ0 5 M_B_DQS_DN4 5 18 VSS 172
DQ8 DQS4_C 179 VSS
5 M_B_A9 121 A9 29 M_B_DQ1 5 M_B_DQS_DP4 5 19 VSS 175
DQ9 DQS4_T 198 VSS
5 M_B_A10_AP 146 41 M_B_DQ7 5 M_B_DQS_DN5 5 22 VSS 176
5 M_B_A11 A10/AP DQ10 M_B_DQ3 5 DQS5_C 200 M_B_DQS_DP5 5 VSS
120 A11 42 23 VSS 180
5 M_B_A12 DQ11 M_B_DQ4 5 DQS5_T 219 M_B_DQS_DN6 5 VSS
119 A12 24 26 VSS 181
5 M_B_A13 DQ12 M_B_DQ5 5 DQS6_C 221 M_B_DQS_DP6 5 VSS
158 A13 25 27 VSS 184
5 M_B_A14_WE# DQ13 M_B_DQ6 5 DQS6_T 240 M_B_DQS_DN7 5 VSS
151 38 30 VSS 185
5 M_B_A15_CAS# W E#/A14 DQ14 M_B_DQ2 5 DQS7_C 242 M_B_DQS_DP7 5 VSS
156 37 31 VSS 188
5 M_B_A16_RAS# CAS#/A15 DQ15 M_B_DQ17 5 DQS7_T 95 VSS
152 50 35 VSS 189
RAS#/A16 DQ16 M_B_DQ20 5 DQS8_C 97 1D2V_S3 VSS
49 36 VSS 192
DQ17 M_B_DQ22 5 DQS8_T VSS
5 M_B_BA0 150 BA0 62 39 VSS 193
DQ18 M_B_DQ18 5 VSS
5 M_B_BA1 145 BA1 63 12 40 VSS 196
DQ19 M_B_DQ16 5 DM0#/DBI0# VSS
5 M_B_BG0 115 BG0 46 33 43 VSS 197
DQ20 M_B_DQ21 5 DM1#/DBI# VSS
5 M_B_BG1 113 BG1 45 54 44 VSS 201
DQ21 M_B_DQ23 5 DM2#/DBI2# VSS
58 75 47 202
DQ22 M_B_DQ19 5 DM3#/DBI3# VSS VSS
92 59 178 48 205
CB0/NC DQ23 M_B_DQ24 5 DM4#/DBI4# VSS VSS
D
91 70 199 51 206 D
CB1/NC DQ24 M_B_DQ31 5 DM5#/DBI5# VSS VSS
220 209
101 CB2/NC DQ25 71 M_B_DQ26 5 DM6#/DBI6# 52 VSS VSS
241 210
105 CB3/NC DQ26 83 M_B_DQ29 5 DM7#/DBI7# 56 VSS VSS
96 213
88 84 M_B_DQ28 5 57 VSS
CB4/NC DQ27 DM8#/DBI#/NC VSS
87 66 M_B_DQ25 5 60 VSS 214
CB5/NC DQ28 VSS
100 67 M_B_DQ30 5 062.10011.00W1 61 VSS 217
CB6/NC DQ29 DDR4-260P--40-GP--U VSS
104 79 M_B_DQ27 5 64 VSS 218
CB7/NC DQ30 VSS
DQ31 80 M_B_DQ33 5 1ST = 062.10011.00W1 65 VSS VSS 222
137 C K0_T 174 M_B_DQ34 5 68 223
5 M_B_CLK0 DQ32 VSS VSS
5 M_B_CLK#0 139 C K0_C DQ33 173 M_B_DQ35 5 2ND = 062.10011.00V1 69 VSS VSS 226
M_B_DQ39 5 227
5 M_B_CLK1 138 CK1_T/ NF 187 72 VSS
5 M_B_CLK#1 140 CK1_C/NF
DQ34
186
M_B_DQ36 5 3RD = 062.10011.0F71 73
VSS
VSS 230
DQ35 M_B_DQ37 5 VSS
170 77 VSS 231
DQ36 M_B_DQ38 5 VSS
5 M_B_CKE0 109 CKE0 169 78 VSS 234
DQ37 M_B_DQ32 5 1D2V_S3 VSS
5 M_B_CKE1 110 CKE1 183 81 VSS 235
DQ38 M_B_DQ41 5 DIMM1C 3 OF 4 3D3V_S0 VSS
182 82 VSS 238
DQ39 M_B_DQ44 5 VSS
5 M_B_CS#0 149 CS0# 195 M_B_DQ42 5 85 VSS 239
DQ40 VSS
157 CS1# 194 111 243
5 M_B_CS#1 DQ41 M_B_DQ47 5 VDD VD D SPD 255 86 VSS VSS
162 C0/CS2#/NC 207 M_B_DQ45 5 112 VDD 89 VSS 244
DQ42 2D5V_S3 VSS
165 C1/CS3#/NC 208 M_B_DQ40 5 117 VDD 90 VSS 247
DQ43 VSS
191 M_B_DQ46 5 118 VDD VPP 257 93 VSS 248
DQ44 C1328 C1329 VSS
5 M_B_ODT0 155 190 M_B_DQ43 5 123 VDD VPP 259 94 VSS 251
161
ODT0 DQ45
124 0D6V_S0 DY VSS
252

SCD1U16V2KX-L--GP

SC2D2U10V3KX--L-GP
5 M_B_ODT1 OD T1 DQ46 203 M_B_DQ53 5 VDD 98 VSS VSS

2 1

2 1
204 M_B_DQ49 5 129 VDD VTT 258
SA0_CHB_DIM0 256 DQ47
216 M_B_DQ55 5 130 VDD
SA1_CHB_DIM0 260 SA0 DQ48
215 M_B_DQ54 5 135 DDR4-260P--40-GP--U
VDD
SA2_CHB_DIM0 166 SA1 DQ49
228 M_B_DQ51 5 136
SA2 DQ50 VDD
229 M_B_DQ52 5 141 062.10011.00W1
DQ51 VDD
254 SDA 211 M_B_DQ48 5 142
18,65 PCH_SMBDATA DQ52 VDD
253 SCL M_B_DQ50 5 147 1ST = 062.10011.00W1
1D2V_S3 18,65 PCH_SMBCLK DQ53 212 VDD 261 261
M_B_DQ56 5 148
DQ54 224
M_B_DQ57 5 VDD 262 262
DQ55 225
M_B_DQ62 5
153 VDD 2ND = 062.10011.00V1
5,12 DDR4_DRAMRST# 108 RESET# 237 154 VDD
DQ56 M_B_DQ63 5
3RD = 062.10011.0F71

El
5 M_B_ACT_N 114 ACT# 236 159 VDD NP1 NP1
116 DQ57 M_B_DQ61 5
ALERT# 249 160 VDD NP2 NP2
5 M_B_ALERT_N TS#_DIMM1_1 DQ58 M_B_DQ58 5
1 R1313 2 240R2F--1-GP 134 EVENT#/NF DQ59 250 M_B_DQ59 5
163 VDD
DQ60 232 M_B_DQ60 5
DY 5 M_B_PARITY 143 PARITY DQ61 233
DDR4-260P--40-GP--U
DQ62 245
M_VREF_CA_DIMMB 164 246
VREFC A DQ63
062.10011.00W1
DDR4-260P--40-GP--U
1ST = 062.10011.00W1
C1302 062.10011.00W1 2ND = 062.10011.00V1
2 1

SCD1U16V2KX-L-GP
1ST = 062.10011.00W1 3RD = 062.10011.0F71

et
2ND = 062.10011.00V1
3RD = 062.10011.0F71 1D2V_S3
3D3V_S0 0D6V_S0 0D6V_S0 0D6V_S0 2D5V_S3

DY
20151007 Change DIMM1 SKT PN DDR4_DRAMRST# R1302 2 1 10KR2F-L1-GP SA0_CHB_DIM0

C1311 C1312 C1313 C1314

2 R1303 1 0R0402-PAD C1326 C1327

1
EC1301 C1303 C1304 C1305 C1306 C1307 C1308 C1309 C1310 C1324 C1325 DY DY

SC100UU6D3V3MX--L-GP

SC100UU6D3V3MX--L-GP
1 1

2 1

2 1

2 1

2 1

2 1

21
C SC33P50V2JN--3GP C
DY

SC100UU6D3V3MX--L-GP

SC100UU6D3V3MX--L-GP

SC100UU6D3V3MX--L-GP

SC100UU6D3V3MX--L-GP

SC100UU6D3V3MX--L-GP

SC100UU6D3V3MX--L-GP

SC100UU6D3V3MX--L-GP

SC100UU6D3V3MX--L-GP

SC100UU6D3V3MX--L-GP

SC100UU6D3V3MX--L-GP

SC1U10V2KX--L1-GP

SC1U10V2KX--L1-GP

SC1U10V2KX--L1-GP

SC1U10V2KX--L1-GP
1 1 1 1 1 1 1 1 1 1

ro
2

2
DY 3D3V_S0

Ref. 549360_SKL_U_6L WP P47 DY DY

R1306 2 1 10KR2F-L1-GP SA1_CHB_DIM0

1D2V_S3 2 R1307D1Y 0R2J-L-GP

R1301
1KR2F-3-GP C1315 C1316 C1317 C1318 C1319 C1320 C1321 C1322
R1305

2 1

2 1

2 1

2 1

2 1

2 1

2 1

2 1
1 2

SC1U10V2KX-L1--GP

SC1U10V2KX-L1--GP

SC1U10V2KX-L1--GP

SC1U10V2KX-L1--GP

SC1U10V2KX-L1--GP

SC1U10V2KX-L1--GP

SC1U10V2KX-L1--GP

SC1U10V2KX-L1--GP
1 2 M_VREF_CA_DIMMB 3D3V_S0
1 2 V_SM_VREF_CNTB 5

-X
R1304 2R2F-GP DY
1

1KR2F-3-GP R1308 2 1 10KR2F-L1-GP SA2_CHB_DIM0

C1323 SCD022U16V2KX-
-3GP 2 R1311 1 0R0402-PAD
DY DY
+V_VREF_PATH2
12

R1309
24D9R2F--L-GP
2

Te
ch
B B

ni
ca
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A A

Eletro-XTechnical Eletro-XTechnical
<Core Desiiign>

Wistron Corporation
21F,,, 88,,,Sec.1,,, Hsiiin Taiii W u Rd., Hsiiichiiih,,,
Taiiipeiii Hsiiien 221,,, Taiiiwan,,, R.O.C...

Tiittlle

DDR4-SODIMM2
Siiize Document Number Rev
A1
LV115 SKL-U -1
Dattte:: Monday,,, Apriiilll 25, 2016 Sheett 13 off 102
5 4 3 2 1
 5 4 3 2 1

Main Func = PCH

CPU1I 9 OF 20
Eletro-XTechnical
CSII-2 SKYLAKE_ULT

A36 CSI2_DN0 CSI2_CLKN0 C37

B36 CSI2_DP0 CSI2_CLKP0 D37
D C38 CSI2_DN1 CSI2_CLKN1 C32 D
D38 CSI2_DP1 CSI2_CLKP1 D32
C36 CSI2_DN2 CSI2_CLKN2 C29
D36 D29 DC resistance < 0.5ohm.
CSI2_DP2 CSI2_CLKP2
A38 CSI2_DN3 CSI2_CLKN3 B26
B38 CSI2_DP3 CSI2_CLKP3 A26 R1501
C31 CSI2_COMP 1 2
CSI2_DN4 CSI2_COMP E13
D31 CSI2_DP4 GPP_D4/FLASHTRIG B7
C33 CSI2_DN5 100R2F-L1-GP-U
D33 CSI2_DP5 EMMC
A31 CSI2_DN6
B31 CSI2_DP6 GPP_F13/EMMC_DATA0 AP2
A33 AP1 [#545659 Rev0.7]
CSI2_DN7 GPP_F14/EMMC_DATA1
B33 CSI2_DP7 GPP_F15/EMMC_DATA2 AP3
AN3 GPP_F: VCCPGPPF = 1.8V Only
GPP_F16/EMMC_DATA3
A29 AN1

El
CSI2_DN8 GPP_F17/EMMC_DATA4
B29 CSI2_DP8 GPP_F18/EMMC_DATA5 AN2
C28 CSI2_DN9 GPP_F19/EMMC_DATA6 AM4
D28 CSI2_DP9 GPP_F20/EMMC_DATA7 AM1
A27 CSI2_DN10
B27 CSI2_DP10 GPP_F21/EMMC_RCLK AM2
C27 CSI2_DN11 GPP_F22/EMMC_CLK AM3
D27 AP4

et
CSI2_DP11 GPP_F12/EMMC_CMD R1502
AT1 EMMC_RCOMP 1 2
EMMC_RCOMP
SKYLAKE-U-GP 200R2F-L-GP
C C
071.SKYLA.000U

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CPU BOMCTRL

-X
Te
ch
B B

ni
ca
l
A <Core Desiiign> A

Wistron Corporation
21F, 88, Sec.1, Hsiiin Taiii Wu Rd., Hsiiichiiih,
TaiiipeiiiHsiiien 221, Taiiiwan, R.O.C.

Eletro-XTechnical Eletro-XTechnical
Title

CPU_(CS-2/EMMC)
Siize DocumentNumber Rev
A3
LV115 SKL-U -1
Date: Monday, Apriiilll25,2016 Sheet 15 of 102
5 4 3 2 1
 5 4 3 2 1

Main Func = PCH

#543016:
220 nF nominal capacitors are recommended for Gen 3. CPU1H 8 OF 20
100 nF nominal capacitors are recommended for Gen 2. SKYLAKE_UL
LT
SSIC //USB3
PCIIE/USB3//SATA
H8 (#545659) The xHCI controller supports USB Debug port on all USB3.0 capable ports.
USB3_1_RXN USB30_RX_CPU_N1 36

Eletro-XTechnical
USB3_1_RXP G8 USB30_RX_CPU_P1 36
76 PEG_RX_CPU_N0
76 PEG_RX_CPU_P0
H13
G13 PCIE1_RXN/ USB3_5_R XN USB3_1_TXN C13
D13
USB30_TX_CPU_N1 36
USB30_TX_CPU_P1 36 USB1 (USB3.0 Port1)
C1606 SCD22U10V2KX--L1-GP PCIE1_RXP/ USB3_5_R XP USB3_1_TXP
76 PEG_TX_GPU_N0 1 2 PX PEG_TX_CPU_N0 B17
PCIE1_TXN/ USB3_5_TXN
76 PEG_TX_GPU_P0 C1605 1 2 SCD22U10V2KX--L1-GP PX PEG_TX_CPU_P0 J6
USB2 (USB3.0 Port2)
A17 PCIE1_TXP/ USB3_5_TXP USB3_2_RXN/SSIC_R XN USB30_RX_CPU_N2 36
USB3_2_RXP/SSIC_R XP H6 USB30_RX_CPU_P2 36
76 PEG_RX_CPU_N1 G11 B13 USB30_TX_CPU_N2 36
F11 PCIE2_RXN/ USB3_6_R XN USB3_2_TXN/SSIC_TXN
76 PEG_RX_CPU_P1 A13 USB30_TX_CPU_P2 36
C1608 SCD22U10V2KX--L1-GP PCIE2_RXP/ USB3_6_R XP USB3_2_TXP/SSIC_TXP
76 PEG_TX_GPU_N1 1 2 PX PEG_TX_CPU_N1 D16
PCIE2_TXN/ USB3_6_TXN
76 PEG_TX_GPU_P1 C1607 1 2 SCD22U10V2KX--L1-GP PX PEG_TX_CPU_P1 C16 PCIE2_TXP/ USB3_6_TXP J10
USB3_3_RXN
GPU H16
USB3_3_RXP H10
76 PEG_RX_CPU_N2
G16 PC I E3_RXN USB3_3_TXN B15
76 PEG_RX_CPU_P2
C1610 SCD22U10V2KX--L1-GP D 17 PC I E3_RXP USB3_3_TXP A15
76 PEG_TX_GPU_N2 1 2 PX PEG_TX_CPU_N2 PC I E3_TXN
76 PEG_TX_GPU_P2 C1609 1 2 SCD22U10V2KX--L1-GP PX PEG_TX_CPU_P2 C17 PC I E3_TXP E10
USB3_4_RXN
USB3_4_RXP F10
76 PEG_RX_CPU_N3 G15 PC I E4_RXN USB3_4_TXN C15
D F15 D
76 PEG_RX_CPU_P3
C1612 SCD22U10V2KX--L1-GP B19 PC I E4_RXP USB3_4_TXP D15
76 PEG_TX_GPU_N3 1 2 PX PEG_TX_CPU_N3 PC I E4_TXN
USB1 (USB2.0 port1)
76 PEG_TX_GPU_P3 C1611 1 2 SCD22U10V2KX--L1-GP PX PEG_TX_CPU_P3 A19 PC I E4_TXP AB9
USB2N_1 USB_CPU_PN0 36
AB10 USB_CPU_PP0 36
USB2P_ 1
61 PCIE_RX_CPU_N5 F16
PC I E5_RXN
WLAN USB2 (USB2.0 Port2)
61 PCIE_RX_CPU_P5 SCD1U16V2KX--3GP E16 AD6 USB_CPU_PN1 36
61 PCIE_TX_CON_N5 C1601 1 2 PCIE_TX_CPU_N5 C19 PC I E5_RXP USB2N_2
AD7 USB_CPU_PP1 36
61 PCIE_TX_CON_P5 C1602 1 2 PCIE_TX_CPU_P5 D19 PC I E5_TXN USB2P_ 2
PC I E5_TXP
USB3 (IO BD/USB2.0 Port3)
SCD1U16V2KX--3GP AH3 USB_CPU_PN2 USB_CPU_PN2 66
USB2N_3
G18 AJ3 USB_CPU_PP2 USB_CPU_PP2 66
PC I E6_RXN USB2P_ 3
F18
PC I E6_RXP
D20 AD9 USB_CPU_PN3 1 TP1605
PC I E6_TXN USB2N_4
C20 AD10 USB_CPU_PP3 1 TP1606
PC I E6_TXP USB2P_ 4

60 SATA_RX_CPU_N0
60 SATA_RX_CPU_P0
F20 PCIE7_RXN/SATA0_RXN
E20 PCIE7_RXP/SATA0_RXP
USB2N_5
USB2P_5
AJ1
AJ2
USB_CPU_PN4
USB_CPU_PP4
55
55
CAMERA (USB2.0 Port5)
HDD (SATA GEN.3) 60 SATA_TX_CPU_N0
60 SATA_TX_CPU_P0
B21 PCIE7_TXN/SATA0_TXN
A21 PCIE7_TXP/SATA0_TXP
USB2

USB2N_6 AF6
USB_CPU_PN5 1 TP1603
USB_CPU_PP5 1 TP1604
USB2P_6 AF7
60 SATA_RX_CPU_N1 G21 PCIE8_RXN/SATA1A_RXN
F21 PCIE8_RXP/SATA1A_R XP USB_CPU_PN6 1 TP1601
60 SATA_RX_CPU_P1 USB2N_7 AH1
ODD (SATA GEN.2) D21 PCIE8_TXN/SATA1A_TXN USB_CPU_PP6 1 TP1602
60 SATA_TX_CPU_N1 USB2P_7 AH2
60 SATA_TX_CPU_P1 C21 PCIE8_TXP/SATA1A_TXP

E22
USB2N_8 AF8
AF9
USB_CPU_PN7
USB_CPU_PP7
61
61
Bluetooth (USB2.0 Port8)
PC I E9_RXN USB2P_8
E23 PC I E9_RXP
B23 PC I E9_TXN
A23 PC I E9_TXP
USB2N_9
USB2P_9
AG1
AG2
USB_CPU_PN8
USB_CPU_PP8
33
33 USB2.0 Card Reader (USB2.0 Port9)
F25 PC I E10_RXN USB2N_10 AH7
E25 PC I E10_RXP USB2P_10 AH8
D23 PC I E10_TXN
C23 PC I E10_TXP AB6 USBCOMP 1 R1603 2 113R2F-GP USBCOMP DC resistance < 0.5ohm.
USB2_C OMP

El
PCIE_RCOMPN USB2_ID AG3 Unused SATA[3:0]GP pins must be terminated to either
F5
R1604 1 PCIE_RCOMPP PC I E_RC OMPN USB2_VBUSSENSE AG4 3.3V rail or GND using 8.2K to 10K on the
2 E5
100R2F-L1-GP--U PC I E_RC OMPP motherboard. Either pull-up or pull-down is acceptable.
USB_OC0#
GPP_E9/USB2_OC 0# A9 USB_OC0# 36
D56 PROC_PR D Y# USB_OC1#
99 XDP_PRDY# GPP_E10/ USB2_OC 1# C9 USB_OC1# 36
D61 PROC _PREQ# USB_OC2#
99 XDP_PREQ# GPP_E11/ USB2_OC 2# D9 USB_OC2# 66
3D3V_S0 10KR2J--3-GP 2 1R1607 PIRQA# BB11 GPP_A7/PIRQA# USB_OC3#
GPP_E12/ USB2_OC 3# B9

E28 PCIE11_RXN/SATA1B_RXN (#543016) When used as DEVSLP, no external pull -up or pull-down
GPP_E4/DEVSLP0 J1 SATA_ODD_DA# DEVSLP0_HDD_CON 60
3D3V_S0
DY E27 PCIE11_RXP/SATA1B_R XP GPP_E5/DEVSLP1 J2 DEVSLP2_mSATA SATA_ODD_DA# 60 termination required from SATA Host DEVSLP.
1
PESD5V0U1BL--GP-U1

D24 PCIE11_TXN/SATA1B_TXN GPP_E6/DEVSLP2 J3 R1610

ED1602

C24 PCIE11_TXP/SATA1B_TXP
E30 PCIE12_RXN/SATA2_RXN H2 GPP_E0/SATAXPCIE0/SATAGP0 DEVSLP0_HDD_CON 2 1 10KR2J--3-GP
31 PCIE_RX_CPU_N6 GPP_E0/SATAXPCIE0/SATAGP0
SCD1U16V2KX--3GP SATA_ODD_PRSNT# 3D3V_S5
31 PCIE_RX_CPU_P6 F30
PCIE_TX_CPU_N6 PCIE12_RXP/SATA2_RXP
H3 DY

et
GPP_E1/SATAXPCIE1/SATAGP1 SATA_ODD_PRSNT# 60
LAN
C1603 1 2 A25 SATAXPCIE2 3D3V_S0
31 PCIE_TX_CON_N6 PCIE12_TXN/SATA2_TXN GPP_E2/SATAXPCI E2/SATAGP2 G4
2

31 PCIE_TX_CON_P6 C1604 1 2 PCIE_TX_CPU_P6 B25 PCIE12_TXP/SATA2_TXP RN1602 R1611

SCD1U16V2KX--3GP H1 SATA_LED# SATA_LED# 64 USB_OC2# 8 1
GPP_E8/SATALED # DEVSLP2_mSATA 2
USB_OC0# 7 2 1 10KR2J--3-GP
USB_OC3# 3
SKYLAKE-U--GP
6 DY
RN1601 USB_OC1# 5 4
R1608
SATAXPCIE2 8 1
071.SKYLA..000U GPP_E0/SATAXPCIE0/SATAGP0 7 2 SATA_ODD_DA# 2 1 10KR2J--3-GP
Recommended Layout for PCIE_RCOMPP/N: SATA_LED# 6 3 SRN10KJ--6-GP
1.Trace Width: 4 mils min (breakout) 12-15 mils (trace) SATA_ODD_PRSNT# 5 4

C
Note: Must maintain low DC resistance routing (<0.1 ohm). CPU BOM CTRL C
2.Isolation Spacing: At least 12 mils to any adjacent SRN10KJ--6-GP

ro
high speed I/O.

PCIE Table USB 2.0 Table (#543016) Unused SATAGP[2:0]/GPP_E[2:0] pins must be terminated to either 3.3 V rail or GND
using 8.2 KΩ to 10 KΩ on the motherboard.
Pair Device Do not use both pull-up and pull-down. Either pull-up or pull-down is acceptable.

0 USB3.0 port1 (Debug Port)

Port Device Share BUS
1 USB2.0 Port2
1 GPU L0

-X
2 USB2.0 Port3 (IOBD)
2 GPU L1
3
3 GPU L2
4 CAMERA
4 GPU L3
5
5 WLAN
6
6 N/A

Te
7 Bluetooth
7 N/A SATA0 (HDD)
8 USB2.0 Card Reader
8 N/A SATA1 (ODD)
9
9 N/A

10 N/A

11 N/A
20151024 Modify PCIE/USB2.0 Mapping Table
12 LAN

ch
B B

ni
ca
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A A

Eletro-XTechnical Eletro-XTechnical
<Core Desiiign>

Wistron Corporation
21F,,, 88,,,Sec.1,,, Hsiiin Taiii W u Rd., Hsiiichiiih,,,
Taipei Hsiiien 221, Taiwan, R...O...C...

Title

CPU_(PCIE/SATA/USB)
Siiize Document Number Rev
A1
LV115 SKL-U -1
Date: Monday,,, Apriiilll 25, 2016 Sheet 16 off 102
5 4 3 2 1
 5 4 3 2 1

Main Func = PCH

3D3V_S5

R1709
1 2 AC_PRESENT

Eletro-XTechnical
10KR2J--3-GP

RN1701 SIO_SLP_S3# 1 TP1701

1 4 SIO_PWRBTN#
2 3 PCH_WAKE#
SRN10KJ--5-GP
R1723 R1713
24,31,40,61,68,76 PLT_RST# 1 2PCH_PLTRST#
D 1 2 PCH_BATLOW# D

1
10KR2J--3-GP 33R2J--2-GP
RTC_AUX_S5 3D3V_S0 3D3V_S5 R1715
47KR2J--2-GP C1701

2 1
SC100P50V2JN--3GP [#543016 Rev0.7]
DY EXT_PWR_GATE#: Due to a bug on A0, a temporary pull-up resistor will be required to overcome the internal 20k

2
1

1
1 2 SM_INTRUDER# pull-down that is active during the early portion of the power up sequence
R1730 1MR2J--1-GP R1711 R1701
3KR2J-2-GP CPU1K 11 OF 20
10KR2J--3-GP
DY SYSTEM POWERMANAGEMENT

2
SIO_SLP_S0# 1 TP1709
ED1704 SKYLAKE_ULT GPP_B12/SLP_S0# AT11
GPD4/SLP_S3# AP15 SIO_SLP_S3# 24,40,51,52,54
R1733 1 2 10KR2J--3-GP PM_RSMRST# 2 1 PCH_PLTRST# AN10 GPP_B13/PLTRST# GPD5/SLP_S4# BA16 SIO_SLP_S5# SIO_SLP_S4# 24,40,51 3D3V_S5
XDP_DBRESET# B5 SYS_RESET# GPD10/SLP_S5# AY16 1
PM_RSMRST# AY17 RSMRST# TP1703
PESD5V0U1BL--GP-U1 SIO_SLP_SUS# TP1710
DY H_CPUPWRGD
SLP_SUS# AN15 1
0R2J--2-G1P R1736 2 SLP_LAN#
40 H_THERMTRIP_EN A68 PROCPW RGD SLP_LAN# AW 15 1 R1731
#544669 Rev0.52 CRB: H_VCCST_PW RGD_R 1 2 60D4R2F--GP H_VCCST_PWRGD B65 VCCST_PW RGD GPD9/SLP_WLAN# BB17
GPD9/SLP_WLAN# 1 TP1704
No PL resistor on THERMTRIP#. R1734
GPD6/SLP_A# AN16
SIO_SLP_A# 1 TP1705 EXT_PWR_GATE# 2 1
ED1701 SYS_PWROK B6 SYS_PW ROK TP1706
24 SYS_PWROK
2 1 H_CPUPWRGD R1706 1 2 0R0402-PAD PM_PCH_PWROK BA20 PCH_PW ROK
40 PCH_PWROK PM_RSMRST# PCH_DPW ROK GPD3/PW RBTN# BA15 AC_PRESENT SIO_PWRBTN# 24 20KR2J--L2-GP
DY R1704 1 2 0R0402-PAD BB20 DSW _PWROK GPD1/ACPRESENT AY15 PCH_BATLOW# AC_PRESENT 24
PESD5V0U1BL--GP-U1 GPD0/BATLOW # AU13
1

BATLOW#:

El
ME_SUS_PWR_ACK_R AR13
20,24 ME_SUS_PWR_ACK_R GPP_A13/SUSW ARN#/SUSPW RDNACK

1
SUSACK#_R AP11 Pull-up required even if not implemented.
1 R1735 GPP_A15/SUSACK#
1 2 PM_PCH_PWROK AU11 PME# 1
R1732 8K2R2F--1-GP PCH_WAKE# GPP_A11/PME#
AP16 SM_INTRUDER# TP1707
ED1703 DY 10KR2J--3-GP 24,31,79 PCH_WAKE# BB15 W AKE#
PESD5V0U1BL--GP-U1

AFTP1702 R1707 INTRUDER#

3D3V_S5 1 2 10KR2J--3-GP GPD2/LAN_WAKE# AM15
R1717 2 GPD2/LAN_WAKE#
DY 1 10KR2J--3-GP SYS_PWROK AW 17 AM10 EXT_PWR_GATE#

2
GPD11/LANPHYPC GPP_B11/EXT_PWR_GATE#
AT15 AM11 GPP_B2/VRALERT# 1
2

GPD7/RSVD#AT15 GPP_B2/VRALERT# TP1708

(PDG#543016)
SKYLAKE-U-GP
WAKE#: Ensure that WAKE# signal Trise (Maximum) is <100 ns.

et
071.SKYLA.000U CPU BOM CTRL

3D3V_S5

SCD1U16V2KX-3GP
C C1702 C
+VCCST_CPU

ro

2 1
Dis-wire with XDP_PM_RSMRST_PWRGD_XDP

1
U1701 R1722
1KR2J-1-GP
1 NC#1 VCC 5

VCCST_PWRGD / HWM201:

2
24,40 ALL_SYS_PWRGD 2 A

-X
3 4 H_VCCST_PW RGD_R
GND Y
EC1708
74LVC1G07GW--GP
DY
73.01G07.0HG

SCD1U16V2KX-3GP
2 1
1 DY 2
R1716

Te
100KR2F--L1-GP

1
R1719
DY 47KR2F--GP
EC1709
DY

2 1
SCD1U16V2KX-3GP

2
ch
#543016 Rev0.7
1. VCCST_PWRGD is only 1.0 V tolerant.
2. VCCST_PWRGD must go low during Sx pwr states, regardless of the voltage level of VCCST
B B

XDP_DBRESET#
SYS_PWROK
PLT_RST#

ni
PCH_PW ROK

DY

1
R1708 DY DY DY DY ED1702
ME_SUS_PWR_ACK_R 1 2 0R2J--2-GP SUSACK#_R EC1706 EC1702 EC1703 EC1704

21

21

21

21

ca
PESD5V0U1BL--GP-U1

SC1KP50V2KX--1GP

SC1KP50V2KX--1GP

SC1KP50V2KX--1GP

SC1KP50V2KX--1GP
DY

2
3D3V_AUX_KBC R1727
100KR2J--1-GP

l
1 2
2

R1726
10KR2J--3-GP

Q1701 1KR2J--1-GP
1

R1702
4 3 PM_RSMRST# 1 2 PCH_RSMRST# 24
3V_5V_POK# 5 2 3V_5V_POK_C 1 R1728 2 3V_5V_POK 45,54

6 1 0R0402-PAD EC1711 EC1712

DY DY
SCD1U16V2KX--3GP

SCD1U16V2KX--3GP

A 2N7002KDW--GP A
21

21

84.2N702.A3F
2nd = 075.063D1.007C <Core Desiiign>

Wistron Corporation
21F,,, 88,,, Sec.1,,, Hsiiin Taiii W u Rd., Hsiiichiih,,,

Eletro-XTechnical Eletro-XTechnical
Taipei Hsiiien 221, Taiwan, R...O...C...

Tiitle
CPU_(POWER MANAGEMENT)
Siize Document Number Rev
A2
LV115 SKL-U -1
Date: Monday,,, Aprrriill25,,, 2016 Sheet 17 off 102
5 4 3 2 1
 5 4 3 2 1

Main Func = PCH PCH strap pin: PCH Prim

PCH strap pin: PCH Prim
eSPI orLPC Sampled at rising edge of RSMRST# 3D3V_S5
BOOT HALT 3D3V_S5
SML0ALERT# / This signal has a weak internal pull-down. 3D3V_S5
0 = ENABLED

1
GPP_C5 0 = LPC Is selected for EC. SPI0_MOSI

1
DY R1822 1 = DISABLED
1 = eSPI Is selected for EC. R1824
1KR2J--1-GP W EAK INTERNAL PU DY RN1807
This signal has a weak internal pull-down. 1KR2J--1--GP SML1_SMBDATA 8 1
This signal has a weak internal pull-up. SML1_SMBCLK 7 2

Eletro-XTechnical
SML0_DATA 6 3
GPP_C5/SML0ALERT# SML0_CLK 5 4

1 2
SPI_SI0_R

1 2
SRN2K2J--4--GP
DY R1823
1KR2J--1-GP DY R1825
1KR2J--1--GP

2
3D3V_S5
3D3V_S5 PLACE WITHIN 1.1 INCH OF PCH GPP_C2/SMBALERT# 1 R1827 2
(#543016)Optional, can be left as OPEN/No-Connect. DY 10KR2J--3--GP
1

RN1811
1

R1835
D R1834 1KR2J--1-GP MEM_SMBCLK 4 1 D

DY MEM_SMBDATA
DY 1KR2J--1-GP 3 2
2
2

SPI_HOLD_0# SRN2K2J--1--GP
1

24,68 LPC_AD0
LPC_AD0 1 R1805 2 0R0402-PAD LPC_LAD0_R add Circuit for NFC
R1836 LPC_AD2 1 R1806 2 0R0402-PAD LPC_LAD2_R
24,68 LPC_AD2
SPI0_WP# 1KR2J--1-GP
24,68 LPC_AD1
LPC_AD1 1 R1807 2 0R0402-PAD LPC_LAD1_R
24,68 LPC_AD3
LPC_AD3 1 R1808 2 0R0402-PAD LPC_LAD3_R
2

3D3V_S0 CPU1E 5 OF 20
Resister value will check later
SPII--FLLASH
SMBUS, SMLLIINK
R1840 SKYLAKE_UL
LT 3D3V_S5
AV2 SPI0_CLK MEM_SMBCLK
SIO_RCIN#
24,25 SPI_CLK_R GPP_C0/SMBCLK R7
12 AW 3 SPI0_MISO MEM_SMBDATA
24,25 SPI_SO_R GPP_C1/SMBDATA R8 GPP_C2/SMBALERT#
10KR2J--3-GP 24,25 SPI_SI0_R AV3 SPI0_MOSI Strap GPP_C2/SMBALER T# R10
25 SPI0_WP# AW 2 SPI0_IO2 R1814
R1841
25 SPI_HOLD_0# AU4 SPI0_IO3 R9 SML0_CLK SUS_STAT#/LPCPD# 2 DY 1
12 INT_SERIRQ 24,25 SPI_CS0#_R GPP_C3/SML0C LK
AU3 SPI0_CS0# W2 SML0_DATA
10KR2J--3-GP GPP_C4/SML0D ATA GPP_C5/SML0ALERT# 10KR2J--3-GP
AU2 SPI0_CS1# Strap GPP_C5/SML0ALER T# W 1 3D3V_S0
AU1 SPI0_CS2#
SERIRQ PH: W 3 SML1_SMBCLK
GPP_C6/SML1CLK SML1_SMBCLK 24,79 R1818
PDG: 8.2k GPP_C7/SML1D ATA
V3 SML1_SMBDATA SML1_SMBDATA 24,79
SPII--TOUCH
AM7 CLKRUN#_R 1 2
CRB: 10k GPP_B23/SML1ALER T#/PC H HOT#
MD_ID1 M2 GPP_D1/SPI1_C LK
MD_ID2 8K2R2F-1-GP
M3 GPP_D2/SPI1_MISO
MD_ID3 J4 GPP_D3/SPI1_MOSI
TPAD14-OP-GP TP1804 1 CPU_D4_TP TPAD14- 20140820 DAIVD
V1 GPP_D21/SPI1_IO2
OP-GP TP1805 1 CPU_D5_TP V2 GPP_D22/SPI1_IO3
MD_ID0 M1 GPP_D0/SPI1_CS# LPC AY13 LPC_LAD0_R
GPP_A1/LAD0/ESPI_IO0
BA13 LPC_LAD1_R
GPP_A2/LAD1/ESPI_IO1 LPC_LAD2_R

El
BB13
C LLIINK GPP_A3/LAD2/ESPI_IO2 LPC_LAD3_R R1801
AY12
GPP_A4/LAD3/ESPI_IO3
G3 C L_C LK BA12 LPC_LFRAME#_R 2 1 LPC_FRAME# 24,68
61 CL_CLK GPP_A5/LFRAME#/ESPI_C S#
61 CL_DATA G2 CL_DATA BA11 SUS_STAT#/LPCPD# 0R0402-PAD
GPP_A14/SUS_STAT#/ESPI_RESET#
61 CL_RST# G1 CL_RST#

AW 9 PCI_CLK_LPC0 R1820 1 2 22R2J--2-GP

GPP_A9/CLKOU T_LPC 0/ESPI_C LK CLK_PCI_KBC 24
RCIN#: AW 13 GPP_A0/RCI N# R1804 1 2 22R2J--2-GP
24 SIO_RCIN# GPP_A10/C LKOU T_LPC 1 AY9 PCI_CLK_LPC1 CLK_PCI_DB 68
Frequency to Avoid: 33 MHz GPP_A8/CLKRU N# AW 11
CLKRUN#_R 1 R1819 2 PM_CLKRUN#_EC_R 24
24 INT_SERIRQ AY11 GPP_A6/SERI RQ
0R0402-PAD

SKYLAKE-U--GP
EC1805

et
2 1

SCD1U16V2KX--3GP
071.SKYLA..000U
DY 3D3V_S0
CPU BOM CTRL
RN1810
3 2 3D3V_S0
4 1

SRN10KJ--5--GP
3D3V_S5
Memory Down Strap
2N7002KDW--GP
C R1839 1 C
2 1KR2J--1-GP MIID0_H MD_ID0 R1828 1 2 1KR2J--1-GP MIID0_L
R1831 1 2 1KR2J--1-GP MIID1_L
MEM_SMBDATA 6 1 2 1KR2J--1-GP MIID1_H MD_ID1 R1830 1

ro
PCH_SMBDATA 13,65 R1832 1 2 1KR2J--1-GP MIID2_H MD_ID2 R1833 1 2 1KR2J--1-GP MIID2_L
R1837 1 MD_ID3 R1838 1 2 1KR2J--1-GP MIID3_L
84.2N702.A3F 5 2 2 1KR2J--1-GP MIID3_H
2nd = 075.063D1.007C
4 3

Q1801

PCH_SMBCLK 13,65 0=L,1=H

RAMID MD_ID3 MD_ID2 MD_ID1 MD_ID0 LENOVO PN VENDOR PN WISTRON PN VENDOR Density
MEM_SMBCLK
0 0 0 0 0 SAMSUNG 1GB

-X
1 0 0 0 1 MICRON 1GB
RTC_X1
C1801 2 0 0 1 0 HYNIX 1GB
1 2 RTC_X2 XTAL24_IN 2 1
R1815 10MR2J--L-GP 3 0 0 1 1 SAMSUNG 2GB
X1802 SC15P50V2JN-L-GP 4 0 1 0 0 MICRON 2GB

1
1 4 X1801 5 0 1 0 1 HYNIX 2GB

1
XTAL--24MHZ--81--GP
R1802 6 0 1 1 0 SM30K11219 K4A8G165WB-BCPB 072.48165.000U SAMSUNG 4GB
1MR2J--1-GP 82.30004.841
2 3 7 0 1 1 1 SM30K59902 MT40A512M16HA-083E:A 072.40512.0A0U MICRON 4GB

4
C1804 C1803
8 1 0 0 0 SM30K59899 H5AN8G6NAFR-TFC N/A HYNIX 4GB

2
C1802

1 2

1 2
SC4P50V2CN-GP SC4P50V2CN-GP XTAL24_OUT

Te
X
XTAL-32D768KHZ-67-GP XTAL24_OUT 2 1
CPU1J 10 OF 20 T 9 1 0 0 1
82.30001.G11 SC15P50V2JN-L-GP 10 1 0 1 0
CLOCKSIIGNALS DY

1
11 1 0 1 1
GPU

ED1803
76 PEG_CLK_CPU# D42 CLKOUT_PCI E_N 0
SKYLAKE_UL
LT

PESD5V0U1BL--GP-U1
76 PEG_CLK_CPU C42 CLKOUT_PCIE_P0
76 CLKREQ_PEG#0 CLKREQ_PEG#0 AR10 GPP_B5/SRCC LKREQ0# 12 1 1 0 0
13 1 1 0 1

2
WLAN 61 PEG_CLK1_CPU# B42 CLKOUT_PCIE_N1
A42 CLKOUT_PCIE_P1 SUSCLK_R
61 PEG_CLK1_CPU
CLKREQ_PCIE#1 CLKOUT_I TPXD P_N F43 14 1 1 1 0
61 CLKREQ_PCIE#1 AT7 GPP_B6/SRC C LKREQ1# CLKOUT_I TPXD P_P E43 R1813 RTC_AUX_S5
D41 CLKOUT_PCI E_N 2 GPD8/SUSCLK BA17
SUSCLK_R
1 2 PCH_SUSCLK_KBC 61 DY EC1803 15 1 1 1 1

1 2
C41 CLKOUT_PCIE_P2
1D0V_S5

SC4D7P50V2BN-GP
CLKREQ_PCIE#5 AT8 GPP_B7/SRC C LKREQ2# XTAL24_IN 0R0402-PAD
XTAL24_I N E37 XTAL24_OUT +V1.05S_AXCK_LCPLL
XTAL24_OU T E35

2
1
ch
3D3V_S0 D 40
CLKOUT_PCI E_N 3 1 R1803 2 RN1813
C40 E42 XCLK_BIASREF
RN1802 CLKREQ_PCIE#3 CLKOUT_PCIE_P3 XC LK_BI ASREF 2K7R2F-GP
AT10 SRN20KJ--1--GP
GPP_B8/SRCC LKREQ3#
1 4 CLKREQ_PEG#0 RTCX1 AM18
RTC_X1 R1810
2 3 CLKREQ_PCIE#1 RTC_X2 Intel recommend: 2.71k ohm 5%
B40 CLKOUT_PCIE_N4 RTCX2 AM20 1 2

Check Clock Mapping A40 CLKOUT_PCIE_P4 0R0402-PAD

3
4
CLKREQ_PCIE#4 SRTC_RST#
AU8 GPP_B9/SRCC LKREQ4# SRTC RST# AN18
SRN10KJ--5-GP RTC_RST# Q1803
RTC RST# AM16
31 PEG_CLK2_CPU# E40 CLKOUT_PCIE_N5 24 RTCRST_ON G
B
8
RN1801
1 CLKREQ_PCIE#5 LAN 31 PEG_CLK2_CPU
31 CLKREQ_PCIE#2 CLKREQ_PCIE#2
E38 CLKOUT_PCIE_P5
AU7 GPP_B10/SR CC LKREQ5# D
SRTC_RST#
RTC_RST# B

7 2 CLKREQ_PCIE#2 DY R1821
1

3 CLKREQ_PCIE#4

SC1U10V2KX--1GP
6 Y D10KYR2J--3-GPS DY
5 4 CLKREQ_PCIE#3 D
Notice:ZZ.2N702.J3101
G1801
ED1802

C1806
1
2 1

2N7002K--2-GP <Core Desiiign>

PESD5V0U1BL--GP-U1

C1805
SCD1U16V2KX--3GP

SKYLAKE-U--GP SC1U10V2KX--1GP
DY 84.2N702.J31
EC1808

SCD1U16V2KX--3GP

SCD1U16V2KX--3GP
GAP--OPEN
SRN10KJ--6-GP

1 2
2 1

2 1

ni EC1806

EC1807
Wistron Corporation
2

2 1

2 1
071.SKYLA..000U DY DY 21F,,, 88,,,Sec.1,,, Hsiiin Taiii W u Rd., Hsiiichiiih,,,
(#514849) Taiiipeiii Hsiiien 221,,, Taiiiwan,,, R.O.C...
CPU BOM CTRL 2ND = 84.2N702.031
3rd =84.2N702.W31 Tiitle

Layout: Place at the open door area. CPU_(LPC/SPI/SMBUS/CL/CLK)

Siiize Document Number Rev
A1
LV115 SKL-U -1
Dattte::: Monday,,, Apriiill 25, 2016 Sheettt 18 off 102

ca
l
A A

Eletro-XTechnical Eletro-XTechnical

5 4 3 2 1
 5 4 3 2 1

Main Func = PCH

Strap pin:
Port B /
Sampled at rising edge of PCH_PWROK
Port C Detected

0 = Port B is not detected.

Eletro-XTechnical
DDPB_CTRLDATA * 1 = Port B is detected.

D
DDPC_CTRLDATA * D
R1915
CPU1G 7 OF 20 BT_DISABLE# 2 1
These two signals have weak internal pull-down.
0 = Port C is not detected.
AUDIO 10KR2J-3-GP
1 = Port C is detected. SKYLAKE_ULT
HDA_SYNC BA22 HDA_SYNC/I2S0_SFRM
HDA_BITCLK AY22 HDA_BLK/I2S0_SCLK
HDA_SDOUT BB22 SDIIO//SDXC
HDA_SDO/I2S0_TXD
27 HDA_SDIN0 BA21 HDA_SDI0/I2S0_RXD
AY21 HDA_SDI1/I2S1_RXD GPP_G0/SD_CMD AB11 BT_DISABLE# 61
HDA_RST# AW22 HDA_RST#/I2S1_SCLK GPP_G1/SD_DATA0 AB13 SATA_ODD_PWRGT 60
J5 GPP_D23/I2S_MCLK GPP_G2/SD_DATA1 AB12
AY20 I2S1_SFRM GPP_G3/SD_DATA2 W12 PE_GPIO0 76
AW20 I2S1_TXD GPP_G4/SD_DATA3 W11
GPP_G5/SD_CD# W10
AK7 GPP_G6/SD_CLK W8

El
GPP_F1/I2S2_SFRM
AK6 GPP_F0/I2S2_SCLK GPP_G7/SD_WP W7
AK9 GPP_F2/I2S2_TXD
AK10 GPP_F3/I2S2_RXD GPP_A17/SD_PWR_EN#/ISH_GP7 BA9 CPU_A16_TP
1 TP1902
GPP_A16/SD_1P8_SEL BB9 TPAD14-OP-GP
H5 GPP_D19/DMIC_CLK0 SD_RCOMP 1 R1901 2
SD_RCOMP AB7
D7 GPP_D20/DMIC_DATA0

et
200R2F-L-GP
DGPU_PW ROK
D8 GPP_D17/DMIC_CLK1 GPP_F23 AF13
24,76,85 DGPU_PWROK C8 GPP_D18/DMIC_DATA1

27 SPKR SPKR AW5 GPP_B14/SPKR

C C

ro
SKYLAKE-U-GP
PCH strap pin:
PCH strap pin: CPU BOM CTRL
Flash Descriptor Security Overide/ NO REBOOT

-X
3D3V_S0
Intel ME Debug Mode 1KR2J-1-GP
Low = Default * * Low = Enable (Default) R1916
HDA_SDOUT High = Enable HDA_SPKR High = Disable 1 DY 2 SPKR

The internal pull-down is disabled after

PLTRST# deasserts The internal pull-down is disabled after

Te
PLTRST# deasserts

27 HDA_CODEC_BITCLK R1917 1 2 0R0402-PAD HDA_BITCLK

27 HDA_CODEC_SDOUT R1918 1 2 0R0402-PAD HDA_SDOUT

ch
24 ME_FW P_EC R1909 1 2 1KR2J-1-GP

EC1901 1 2 HDA_CODEC_BITCLK
B B

SC10P50V2JN-L1-GP

ni
DY R1919
27 HDA_CODEC_SYNC 1 2 0R0402-PAD HDA_SYNC
27 HDA_CODEC_RST# R1920 1 2 0R0402-PAD HDA_RST#

HDA_CODEC_RST#

ca
DY EC1902
2 1

SCD1U16V2KX-3GP

l
A <Core Desiiign> A

Wistron Corporation
21F, 88, Sec.1, Hsiiin Taiii Wu Rd., Hsiiichiiih,
TaiiipeiiiHsiiien 221, Taiiiwan, R.O.C.

Eletro-XTechnical Eletro-XTechnical
Title

CPU_(AUDIO/SDIO/SDXC)
Siize DocumentNumber Rev
A3
LV115 SKL-U -1
Date: Monday, Apriiilll25,2016 Sheet 19 of 102
5 4 3 2 1
 5 4 3 2 1

Main Func = PCH 3D3V_S0

R2004 RN2007
10KR2J--3-GP 2
2
1 DGPU_HOLD_RST#
1 DGPU_PWR_EN
20151013 Change VIDEO_THERM_ALERT# PIN to GPP_B20 NO_USE_PCH_I2C0_SCL 2
NO_USE_PCH_I2C0_SDA 1
3
4
10KR2J--3-GP R2006 DY DY SRN2K2J--1--GP

Eletro-XTechnical
R2011 1 CAMERA_EN RN2008
2
10KR2J--3-GP EC2002
DY CPU1F 6 OF 20 I2C1_SCL 1 4

21
I2C1_SDA DY
2 3

SC1KP50V2KX-1GP
DY LPSS ISH
SKYLAKE_ULT
USB_UART_SEL_D9 1 TP2006 TPAD14-OP--GP SRN2K2J--1--GP
AN8 GPP_B15/GSPI0_CS# GPP_D9 P2
AP7 P3 DGPU_HOLD_RST# DGPU_HOLD_RST# 76
GPP_B16/GSPI0_CLK GPP_D10
AP8 RN2009
GPP_B18/GSPI0_MOSI GPP_B17/GSPI0_MISO GPP_D11 P4 ISH_GP_0_R 1 4
PCH strap pin: AR7 GPP_B18/GSPI0_MOSI
Strap GPP_D12 P1 CAMERA_EN 55
ISH_GP_1_R 2 3
RTC_DET_R AM5
25 RTC_DET_R
VIDEO_THERM_ALERT#_R GPP_B19/GSPI1_CS# GPP_D5/ISH_I2C0_SDA M4 SRN10KJ--5-GP
Boot BIOS Strap Bit BBS 1 R2040 20R0402-PAD AN7 GPP_B20/GSPI1_CLK
D 79 VIDEO_THERM_ALERT# GPP_D6/ISH_I2C0_SCL N3 D
AP5 GPP_B21/GSPI1_MISO DY
GPP_B22/GSPI1_MOSI AN5 GPP_B22/GSPI1_MOSI N1 I2C1_SDA
GPP_D7/ISH_I2C1_SDA
Boot BIOS * Low = SPI (Default) GPP_D8/ISH_I2C1_SCL N2
I2C1_SCL
ON_BOARD_RAM_CFG AB1
Destination High = LPC GPP_C8/UART0_RXD
DIMM_SKT_CFG AB2 AD11 1.8V Only

The internal pull-down is disabled after PLTRST# deasserts

CPU_15W_28W_CFG
DGPU_PRSNT#
W4
AB3
GPP_C9/UART0_TXD
GPP_C10/UART0_RTS#
GPP_F10/I2C5_SDA/ISH_I2C2_SDA
GPP_F11/I2C5_SCL/ISH_I2C2_SCL
AD12
20151013 ADD R2041 to Connect DGPU_PWR_EN and PE_GPIO1
GPP_C11/UART0_CTS#

Need double confirm, GPIO table set to GPI AD1 GPP_C20/UART2_RXD GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA U1
DGPU_PWR_EN 1 R2041 2 0R0402-PAD PE_GPIO1 85,86
AD2 GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL U2
if that's needed PH or PL AD3
GPP_C21/UART2_TXD
GPP_C22/UART2_RTS# GPP_D15/ISH_UART0_RTS# U3 UART0_CTS# TP2011 TPAD14--OP-GP
AD4 1
GPP_C23/UART2_CTS# GPP_D16/ISH_UART0_CTS#/SML0BALERT# U4 (PDG#543016) Ensure that all I2C interface on-board terminations are pulled up
GPP_C12/UART1_RXD/ISH_UART1_RXD AC1 UART1_RXD 1 TP2012 TPAD14--OP-GP to the same voltage rail as the device/end point.
3D3V_S0 NO_USE_PCH_I2C0_SDA U7 GPP_C16/I2C0_SDA AC2 UART1_TXD 1 TP2013 TPAD14-OP--GP
NO_USE_PCH_I2C0_SCL GPP_C13/UART1_TXD/ISH_UART1_TXD TP2014 TPAD14-OP--GP
U6 GPP_C17/I2C0_SCL AC3 UART1_RTS# 1
GPP_C14/UART1_RTS#/ISH_UART1_RTS# TP2015 TPAD14--OP-GP
GPP_C15/UART1_CTS#/ISH_UART1_CTS# AB4 UART1_CTS# 1
U8 GPP_C18/I2C1_SDA
U9 GPP_C19/I2C1_SCL ISH_GP_0_R
GPP_A18/ISH_GP0 AY8 ISH_GP_1_R
CAMERA_EN GPP_A19/ISH_GP1 BA8
R2001 1 DY 2 10KR2J--3-GP AH9 GPP_F4/I2C2_SDA GPP_A20/ISH_GP2 BB7
AH10 GPP_F5/I2C2_SCL GPP_A21/ISH_GP3 BA7
GPP_A22/ISH_GP4 AY7 NO_USE_PCH_01

El
AH11
GPP_F6/I2C3_SDA GPP_A23/ISH_GP5 AW 7
AH12 GPP_F7/I2C3_SCL SX_EXIT_HOLDOFF#/GPP_A12/BM_BUSY#/ISH_GP6 AP13
AF11 GPP_F8/I2C4_SDA
AF12 GPP_F9/I2C4_SCL

R2003 1 2 1KR2J--L2-GP GPP_B22/GSPI1_MOSI SKYLAKE-U-GP

071.SKYLA.000U (PDG#543016) If the UART/GPIO functionality is also not used,

DY

et
the signals can be left as no-connect.
PCH Prim CPU BOM CTRL
PCH strap pin: 3D3V_S0 3D3V_S0 3D3V_S0

C C
No Reboot Sampled at rising edge of PCH_PW ROK
1

1
ro
GSPI0_MOSI / 0 = Disable “No Reboot” mode. DY R2007
1KR2J--1-GP
UMA R2005
10KR2J--3-GP DY R2053
10KR2J--3-GP
GPP_B18 1 = Enable “No Reboot” mode (PCH will disable the TCO
Timer system reboot feature). This function is useful
2

2
when running ITP/XDP. GPP_B18/GSPI0_MOSI DGPU_PRSNT# NO_USE_PCH_01
1

The signal has a weak internal pull-down.

1
DY R2019
1KR2J--1-GP R2008 R2054

-X
PX 10KR2J--3-GP DY 10KR2J--3-GP
2

2
3D3V_S5 3D3V_S5 3D3V_S5

Te
1

1
R2010 R2013 R2015
ON BOARD RAM STUFF 10KR2J--3-GP DIMM SKT STUFF 10KR2J--3-GP CPU_28W 10KR2J--3-GP
2

2
ON_BOARD_RAM_CFG DIMM_SKT_CFG CPU_15W_28W_CFG
1

1
R2009 R2012 R2014

3D3V_S5 ON BOARD RAM DY 10KR2J--3-GP DIMM SKT DY 10KR2J--3-GP CPU_15W 10KR2J--3-GP

ch
2

2
R2039 1 2 10KR2J--3-GP
ME_SUS_PWR_ACK_R 17,24
B B

ni
ca
l
A A

<Corrre Desiiign>

Wistron Corporation
21F,,, 88, Sec...1, HsiiinTai W u Rd...,,,Hsiiichih,

Eletro-XTechnical Eletro-XTechnical
Taiiipeiii Hsiiien 221,,, Taiiiwan,,, R.O.C...

Title

CPU_(LPSS/ISH)
Siize Document Number Rev
A2
LV115 SKL-U -1
Date: Monday,,, Aprrriill25, 2016 Sheet 20 off 102
5 4 3 2 1
 5 4 3 2 1

Main Func = PCH

RTC_AUX_S5

1D0V_S5 CPU1O
CPUPOWER4 OF 4
15 OF 20

3D3V_S5 C2119 C2118 C2117

Eletro-XTechnical

2 1

2 1

21
AB19 VCCPRIM_1P0 SCD1U16V2KX-3GP SCD1U16V2KX-3GP SC1U10V2KX-1GP
AB20 VCCPRIM_1P0
SKYLAKE_ULT VCCPGPPA AK15 +VCCPGPPA DY
P18 VCCPRIM_1P0 VCCPGPPB AG15
VCCPGPPC Y16
2.57A AF18
VCCPRIM_CORE VCCPGPPD Y15 CAP need close to VCCRTC
AF19 VCCPRIM_CORE VCCPGPPE T16
V20 VCCPRIM_CORE 1.8V Only VCCPGPPF AF16 +V1.8A
D V21 VCCPRIM_CORE AD15 C2106 C2107 D
VCCPGPPG

21

21
+VCCDSW_1P0 SC1U10V2KX--1GP SC1U10V2KX-1GP
AL1 DCPDSW _1P0 VCCPRIM_3P3 V19 3D3V_S5
1

C2120 1D0V_S5
SC1U10V2KX--1GP K17 VCCMPHYAON_1P0 VCCPRIM_1P0 T1 1D0V_S5
L1 VCCMPHYAON_1P0
2

VCCATS_1P8 AA1 +V1.8A

N15 VCCMPHYGT_1P0
N16 VCCMPHYGT_1P0 VCCRTCPRIM_3P3 AK17 3D3V_S5
N17 VCCMPHYGT_1P0
P15 VCCMPHYGT_1P0 VCCRTC AK19 RTC_AUX_S5
+VCCAMPHYPLL_1P0 P16 VCCMPHYGT_1P0 VCCRTC BB14
VCCRTCEXT C2112 1 2 SCD1U16V2KX--3GP
+VCCAPLL_1P0
K15 VCCAMPHYPLL_1P0 DCPRTC BB10
L15 VCCAMPHYPLL_1P0
VCCCLK1 A14 1D0V_S5
V15 VCCAPLL_1P0
1D0V_S5 K19
VCCCLK2 1D0V_S5
AB17 C2109 C2110 C2111
VCCPRIM_1P0

2 1

2 1

2 1
3D3V_S5 Y18 L21 SC1U10V2KX-1GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP
VCCPRIM_1P0 VCCCLK3 1D0V_S5

AD17 VCCDSW_3P3 VCCCLK4 N20 1D0V_S5

AD18 VCCDSW_3P3
+VCCPAZIO
AJ17 VCCDSW_3P3 VCCCLK5 L19 1D0V_S5
3D3V_S5

El
AJ19 VCCHDA VCCCLK6 A10 1D0V_S5

AJ16 VCCSPI V0.85A_VID0 1 TP2101 TPAD14-OP--GP

GPP_B0/CORE_VID0 AN11
V0.85A_VID1 1 TP2102 TPAD14-OP--GP
GPP_B1/CORE_VID1 AN13
1D0V_S5 AF20 VCCSRAM_1P0
AF21 VCCSRAM_1P0
3D3V_S5
T19 VCCSRAM_1P0
T20 VCCSRAM_1P0

et
AJ21 VCCPRIM_3P3
1D0V_S5 AK20 VCCPRIM_1P0
1

N18 VCCAPLLEBB_1P0
C2105
SC1U10V2KX--1GP
2

C SKYLAKE-U-GP C

ro
071.SKYLA.000U

CPU BOM CTRL

-X
1D0V_S5 +VCCDSW_1P0 +V1.8A

Te
1

C2101 C2102 C2104 C2103 C2108

2 1

21

SC18P50V2JN--1-GP SC18P50V2JN--1-GP SC1U10V2KX--1GP SC1U10V2KX--1GP SC1U10V2KX--1GP

2

DY DY

1D0V_S5

ch
B B

C2113 C2114 C2115 C2116 C2121

2 1
21

21

21

21

SC22U6D3V5MX--L3-GP SC22U6D3V5MX--L3-GP SC22U6D3V5MX--L3-GP SC1U10V2KX--1GP SC2D2U10V3KX--L-GP

ni
ca
l
A A

<Corrre Desiiign>

Wistron Corporation
21F,,, 88, Sec...1, HsiiinTai W u Rd...,,,Hsiiichih,

Eletro-XTechnical Eletro-XTechnical
Taiiipeiii Hsiiien 221,,, Taiiiwan,,, R.O.C...

Title

CPU_(POWER1)
Siize DocumentttNumberr Rev
A2
LV115 SKL-U -1
Date: Monday,,, Aprrriill25, 2016 Sheet 21 off 102
5 4 3 2 1
 5 4 3 2 1

Main Func = PCH

Eletro-XTechnical

D D

CPU1T 20 OF 20
SKYLAKE_ULT
SPARE

AW69 F6
RSVD#AW69 RSVD#F6
AW68 RSVD#AW68 RSVD#E3 E3
AU56 RSVD#AU56 RSVD#C11 C11
AW48 RSVD#AW48 RSVD#B11 B11
C7 RSVD#C7 RSVD#A11 A11

El
U12 RSVD#U12 RSVD#D12 D12
U11 RSVD#U11 RSVD#C12 C12
H11 RSVD#H11 RSVD#F52 F52

et
SKYLAKE-U-GP

071.SKYLA.000U

ro
C

CPU BOM CTRL

-X
Te
ch
B B

ni
ca
l
<Core Design>

Wistron Corporation
A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, A
Taipei Hsien 221, Taiwan, R.O.C.

Title

Eletro-XTechnical CPU_(RSVD)
Eletro-XTechnical
Size Document Number Rev
A4
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 22 of 102
5 4 3 2 1
 5 4 3 2 1

Main Func = PCH

Eletro-XTechnical
CPU1P 16 OF 20

GND 1 OF 3
CPU1Q 17 OF 20 CPU1R 18 OF 20
SKYLAKE_ULT AL65
A5 VSS VSS
D A67 AL66 GND 2 OF 3 GND 3 OF 3 D
VSS VSS
A70 VSS VSS AM13 F8 VSS VSS L18
AA2 AM21 AT63 VSS SKYLAKE_ULT BA49 G10
VSS VSS VSS VSS VSS L2
AA4 AM25 AT68 VSS BA53 G22 SKYLAKE_ULT L20
VSS VSS VSS VSS VSS
AA65 VSS VSS AM27 AT71 VSS VSS BA57 G43 VSS VSS L4
AA68 VSS VSS AM43 AU10 VSS VSS BA6 G45 VSS VSS L8
AB15 VSS VSS AM45 AU15 VSS VSS BA62 G48 VSS VSS N10
AB16 VSS VSS AM46 AU20 VSS VSS BA66 G5 VSS VSS N13
AB18 VSS VSS AM55 AU32 VSS VSS BA71 G52 VSS VSS N19
AB21 VSS VSS AM60 AU38 VSS VSS BB18 G55 VSS VSS N21
AB8 VSS VSS AM61 AV1 VSS VSS BB26 G58 VSS VSS N6
AD13 VSS VSS AM68 AV68 VSS VSS BB30 G6 VSS VSS N65
AD16 VSS VSS AM71 AV69 VSS VSS BB34 G60 VSS VSS N68
AD19 VSS VSS AM8 AV70 VSS VSS BB38 G63 VSS VSS P17
AD20 VSS VSS AN20 AV71 VSS VSS BB43 G66 VSS VSS P19
AD21 VSS VSS AN23 AW10 VSS VSS BB55 H15 VSS VSS P20
AD62 VSS VSS AN28 AW12 VSS VSS BB6 H18 VSS VSS P21

El
AD8 VSS VSS AN30 AW14 VSS VSS BB60 H71 VSS VSS R13
AE64 VSS VSS AN32 AW16 VSS VSS BB64 J11 VSS VSS R6
AE65 VSS VSS AN33 AW18 VSS VSS BB67 J13 VSS VSS T15
AE66 VSS VSS AN35 AW21 VSS VSS BB70 J25 VSS VSS T17
AE67 VSS VSS AN37 AW23 VSS VSS C1 J28 VSS VSS T18
AE68 VSS VSS AN38 AW26 VSS VSS C25 J32 VSS VSS T2
AE69 AN40 AW28 VSS C5 J35 T21

et
VSS VSS VSS VSS VSS
AF1 VSS VSS AN42 AW30 VSS VSS D10 J38 VSS VSS T4
AF10 VSS VSS AN58 AW32 VSS VSS D11 J42 VSS VSS U10
AF15 VSS VSS AN63 AW34 VSS VSS D14 J8 VSS VSS U63
AF17 VSS VSS AP10 AW36 VSS VSS D18 K16 VSS VSS U64
AF2 VSS VSS AP18 AW38 VSS VSS D22 K18 VSS VSS U66
C AF4 AP20 D25 K22 U67 C
VSS VSS VSS VSS VSS

ro
AF63 VSS VSS AP23 AW41 VSS VSS D26 K61 VSS VSS U69
AG16 VSS VSS AP28 AW43 VSS VSS D30 K63 VSS VSS U70
AG17 VSS VSS AP32 AW45 VSS VSS D34 K64 VSS VSS V16
AG18 VSS VSS AP35 AW47 VSS VSS D39 K65 VSS VSS V17
AG19 VSS VSS AP38 AW49 VSS VSS D44 K66 VSS VSS V18
AG20 VSS VSS AP42 AW51 VSS VSS D45 K67 VSS VSS W13
AG21 AP58 AW53 VSS D47 K68 W6

-X
VSS VSS VSS VSS VSS
AG71 VSS VSS AP63 AW55 VSS VSS D48 K70 VSS VSS W9
AH13 VSS VSS AP68 AW57 VSS VSS D53 K71 VSS VSS Y17
AH6 VSS VSS AP70 AW6 VSS VSS D58 L11 VSS VSS Y19
AH63 VSS VSS AR11 AW60 VSS VSS D6 L16 VSS VSS Y20
AH64 VSS VSS AR15 AW62 VSS VSS D62 L17 VSS VSS Y21
AH67 VSS VSS AR16 AW64 VSS VSS D66
AJ15 VSS VSS AR20 AW66 VSS VSS D69

Te
AJ18 VSS VSS AR23 AW8 VSS VSS E11
AJ20 VSS VSS AR28 AY66 VSS VSS E15
AJ4 AR35 B10 VSS E18 SKYLAKE-U-GP
VSS VSS VSS
AK11 VSS VSS AR42 B14 VSS VSS E21
AK16 VSS VSS AR43 B18 VSS VSS E46 071.SKYLA.000U
AK18 VSS VSS AR45 B22 VSS VSS E50
AK21 VSS VSS AR46 B30 VSS VSS E53
AK22 VSS VSS AR48 B34 VSS VSS E56 CPU BOM CTRL
AK27 VSS VSS AR5 B39 VSS VSS E6

ch
AK63 VSS VSS AR50 B44 VSS VSS E65
AK68 VSS VSS AR52 B48 VSS VSS E71
AK69 VSS VSS AR53 B53 VSS VSS F1
AK8 VSS VSS AR55 B58 VSS VSS F13
AL2 VSS VSS AR58 B62 VSS VSS F2
B B
AL28 VSS VSS AR63 B66 VSS VSS F22
AL32 VSS VSS AR8 B71 VSS VSS F23
AL35 VSS VSS AT2 BA1 VSS VSS F27

ni
AL38 VSS VSS AT20 BA10 VSS VSS F28
AL4 VSS VSS AT23 BA14 VSS VSS F32
AL45 VSS VSS AT28 BA18 VSS VSS F33
AL48 VSS VSS AT35 BA2 VSS VSS F35
AL52 VSS VSS AT4 BA23 VSS VSS F37
AL55 VSS VSS AT42 BA28 VSS VSS F38

ca
AL58 VSS VSS AT56 BA32 VSS VSS F4
AL64 VSS VSS AT58 BA36 VSS VSS F40
F68 VSS VSS F42
BA45 VSS VSS BA41
SKYLAKE-U-GP

071.SKYLA.000U

l
SKYLAKE-U-GP

CPU BOM CTRL 071.SKYLA.000U

CPU BOM CTRL

A <Core Desiiign> A

Wistron Corporation
21F, 88, Sec.1, Hsiiin Taiii Wu Rd., Hsiiichiiih,
TaiiipeiiiHsiiien 221, Taiiiwan, R.O.C.

Eletro-XTechnical Eletro-XTechnical
Title

CPU_(VSS)
Siize DocumentNumber Rev
A3
LV115 SKL-U -1
Date: Monday, Apriiilll25,2016 Sheet 23 of 102
5 4 3 2 1
 5 4 3 2 1

SSID = KBC
3D3V_AUX_KBC
MODEL ID
Model_ID_BOM Ctrl
P CB VERSION A/D(P IN98) P ULL-LOW RESISTOR P ULL-HIGH RESISTOR VOLTAGE

1
R2441 LV115 Intel skylake 100.0K 10.0K 64.10025.6DL 3.0V
10KR2F-2-GP
BOM Ctrl_Model LV114 Intel skylake 100.0K 20.0K 64.20025.L0L 2.75V

Eletro-XTechnical

2
NA 100.0K 33.0K 64.33025.L0L 2.48V
MODEL_ID
NA 100.0K 47.0K 64.47025.6DL 2.24V

1
R2442 NA 100.0K 64.9K 64.64925.6DL 2.0V
100KR2F-L1-GP
NA 100.0K 76.8K 64.76825.6DL 1.87V

2
NA 100.0K 215.0K 64.21535.6DL 1.048V

3D3V_AUX_KBC 3D3V_AUX_S5

R2479
D Non PSL SPEC: ADT PWR Detection Function V1 3 D

0R5J--5-GP
1 R2493 2
2

VBAT 3D3V_AUX_KBC
PCB VERSION
0R0603-PAD

1
C2426 C2420 P CB VERSION A/D(P IN98) P ULL-LOW RESISTOR P ULL-HIGH RESISTOR VOLTAGE
R2469 R2437

SC2D2U10V3KX--L-GP

SCD1U16V2KX--L-GP
2D2R3-1-U-GP 64K9R2F-1-GP
SA 100.0K 10.0K 3.0V

2
BOM Ctrl_VER
SB 100.0K 20.0K 2.75V
2 PCB_VER SC 100.0K 33.0K 2.48V
NPCE285G

1 2
EC_AGND
3D3V_AUX_KBC_VCC SD 100.0K 47.0K 2.24V
R2436
100KR2F-L1-GP -1 100.0K 64.9K 2.0V
U2403
KROW[0..7] 65
SE 100.0K 76.8K 1.87V

2
1

1
C2401 C2404 C2405 C2430 C2429 C2421 19 VCC 54 KROW0
KBSIN0/GPIOA0/ N2TC K
DY KROW1 Reserved 100.0K 100.0K 1.65V
SC2D2U10V3KX--L-GP

SCD1U16V2KX--L-GP

SCD1U25V2KX--L-GP

SCD1U16V2KX--L-GP

SCD1U16V2KX--L-GP

SCD1U16V2KX--L-GP
46 VCC KBSIN1/GPIOA1/ N2TMS 55
76 VCC 56 KROW2
2

2
KBSIN2/GPIOA2
88 VCC 57 KROW3
3D3V_S0 KBSIN3/GPIOA3
115 VCC 58 KROW4
KBSIN4/GPIOA4
59 KROW5
KBSIN5/GPIOA5
102 AVC C 60 KROW6
KBSIN6/GPIOA6
61 KROW7
KBSIN7/GPIOA7 3D3V_AUX_KBC
4 VDD KCOL[0..17] 65
R2481
45W_65W#
1D0V_S5 1 2 EC_VTT 12 VTT KBSOUT0/GPOB0/SOUT_C R/JENK# 53
KCOL0 DELTA Model:ADP65FD BB-PD03 ADP
0R0402-PAD
KBSOUT1/GPIOB1/ TC K 52
KCOL1
High: 45W / Low 65W

1
C2402 C2428 EC_AGND C2427 1 DY2 SCD1U25V2KX--L-GP
KBSOUT2/GPIOB2/ TMS 51
KCOL2 R2407
ADP internal Resis 287ohm
1

C2425
DISCRETE#

El
KCOL3
SCD1U16V2KX--L-GP

SC2D2U10V3KX--L-GP

44 AD_IA 97 GPIO90/AD0 KBSOUT3/GPIOB3/ TDI 50

3.3*287/1037=0.91V (65W)
2 1

2 1

SCD1U16V2KX--3GP PCB_VER 98 GPIO91/AD1 KCOL4 RN2405 750R2F-L-GP

KBSOUT4/GPOB4 49 1 8
ADT_TYPE 99 GPIO92/AD2 48 KCOL5
LPC_AD3_C1 LPC_AD3
High: UMA / Low: Discrete
2

MODEL_ID KBSOUT5/GPIOB5/ TD O LPC_AD2_C1 2 7 LPC_AD2 LPC_AD3 18,68

100 GPIO93/AD3 KCOL6
KBSOUT6/GPIOB6/ RD Y# 47 LPC_AD1_C1 3 6 LPC_AD1 LPC_AD2 18,68
108 GPIO05/AD4 KCOL7
17,31,79 PCH_WAKE#
NO_USE_07 KBSOUT7/GPIOB7 43 LPC_AD0_C1 4 5 LPC_AD0 LPC_AD1 18,68 ADT_TYPE R2499 1 2
96 KCOL8
NO_USE_08 GPIO04/AD5 KBSOUT8/GPIOC0 42 LPC_AD0 18,68
0R0402-PAD AD_ID 43
95 GPIO03/EXT_PU RST#/AD 6KBSOU T9/GPOC 1/SD P_VIS# 41 KCOL9
Thermal VD 26 VD_IN2
VD_IN2 94 GPIO07/AD7/VD_I N2 KBSOUT10/P80_CLK/GPIOC 2 40 KCOL10
KCOL11 SRN33J--4-GP
KBSOUT11/P80_D AT/GPIOC 3 39 R2408
KCOL12
KBB_DEFINE1_R 101 KBSOUT12/GPO64/ TEST# 38 100KR2F-L1-GP
KCOL13
GPIO94/DA0
KB_MATRIX_DEBUG 105 KBSOUT13/GP(I)O63/ TRIST# 37
KCOL14
DY

212
FAN_REVERSE_CTRL# 106
GPIO95/DA1 KBSOUT14/GP(I)O62/XORTR# 36 LPC_FRAME#_C1 33R2J--2-GP
KCOL15 1 2 R2498
26 FAN_REVERSE_CTRL# GPIO96/DA2 KBSOUT15/GPI O61/XOR_OU T 35
17,40 ALL_SYS_PW RGD 107 GPIO97/DA3 GPIO60/KBSOU T16/D SR1# 34
KCOL16
LPC_FRAME# 18,68
SA

et
1 1D0V_S5 KCOL17
AFTP2404 GPIO57/KBSOU T17/D CD 1# 33
NOTE:
43,44 BAT_SCL 70 GPIO17/SCL1/ N2TC K P lease be aware that the SP I interface trace length between
BATTERY / CHARGER ----> 43,44 BAT_SDA 69 GPIO22/SDA1/ N2TMS LAD0/GPIOF1 126 LPC_AD0_C1
P CH and EC should not exceed 6500mils,. The mismatch
67 GPIO73/SCL2/ N2TC K 127 LPC_AD1_C1 EM I
18,79 SML1_SMBCLK LAD1/GPIOF2 of SP I interface signals between EC and SP I flash should
LPC_AD2_C1 C2431
18,79 SML1_SMBDATA 68 GPIO74/SDA2/ N2TMS LAD2/GPIOF3 128
NO_USE_03 LPC_AD3_C1 not exceed 500mils.
NO_USE_06
119 GPIO23/SCL3/ N2TC K LAD3/GPIOF4 1
CLK_PCI_KBC_R 2 R2457 1 CLK_PCI_KBC 18
DYSC220P50V2KX--3GP
1 2
120 GPIO31/SDA3/ N2TMS LCLK/GPIOF5 2
PROCHOT_EC
NO_USE_05
24
GPIO47/SCL4A/ N2TC K LFRAME#/GPIOF6 3 LPC_FRAME#_C1 0R0402-PAD
PLT_RST#_EC 1 R2473 2
Prevent BIOS data loss solution
28 GPIO53/SDA4A/ N2TMS LRESET#/GPIOF7 7 PLT_RST# 17,31,40,61,68,76
R2445 2 1 0R0402-PAD DGPU_PWROK_EC 26 GPIO51/TA3/ N2TC K 0R0402-PAD
C 19,76,85 DGPU_PW ROK 3D3V_AUX_KBC C
STOP_CHG# 123 GPIO67/SOUT1/ N2TMS
44 STOP_CHG#
EC_SPI_CS#_C R2485 2 1 33R2J--2-GP
GPIOC6/F_CS0# 90

ro
SPI_CS0#_R 18,25
GPIOC7/F_SCK 92
EC_SPI_CLK_C R2497 2 1 33R2J--2-GP SPI_CLK_R 18,25 NOTE: ECRST#
TP---->

1
72 RTCRST_ON Locate resistors R2415 and R2417 close
65 TPCLK GPIO37/PSCLK1 GPIO30/F_W P#/RTS1# 109 RTCRST_ON 18
65 TPDATA 71 GPIO35/PSDAT1 GPIO41/F_W P#/PSL_GPIO41 80 EC_SPI_DO_C BAT_IN# 43 to the U2401.
1 AOU_IFLG# 10 2 3 R2471
TP2424 GPIO26/PSCLK2 GPIOC5/F_SDIO/F_SDIO0 87 EC_SPI_DI_C RN2411 1 SPI_SI0_R 18,25
10KR2J--3-GP
11 86 4 SPI_SO_R 18,25
61 WLAN_PCIE_WAKE# DGPUHOT GPIO27/PSDAT2 GPIOC4/F_SDI/F_SDIO1 NUM_LED
79 DGPUHOT 25 GPIO81/F_W P#/F_SDIO2 91 NO_USE_13

2
GPIO50/PSCLK3 NUM_LED 65 SRN33J--5-GP--U
20150724 Need check DGPUHOT 55 BLON_OUT 27 GPIO52/PSDAT3 GPIO00/32KC LKI N/ F_SDIO3 77
1 < ----06/26 LT41 USB_CHAR_SEL 8 EC_SMI#
1 R2489 2 R2495 C2424
SC1U10V2KX--L1-GP

2 1
TP2421 0R0402-PAD PURE_HW_SHUTDOW N# 1 2 PURE_HW_SHUTDOW N#_B B Q2401
26,40 PURE_HW_SHUTDOW N#
R2416 2 100KR2J--1-GP 10KR2J--3-GP MMBT3906-4-GP
1 3D3V_AUX_S5 DY

C E
31 AC_IN_KBC# 1 R2433 2 R2486 84.T3906.A11
26 FAN_TACH1 GPIO56/TA1 PSL_IN1#/GPI70 73 0R0402-PAD AC_IN# 44
17 SIO_PWRBTN# 117 GPIO20/TA2/IOX_DIN_DIPOSL_IN2#/GPI06/EXT_PURST# 93 KBC_PWRBTN_EC#
PSL 8 EC_SCI#
1 DY 2 ECSCI#_KBC
65 CAP_LED CAP_LED 63 PSL_OUT#/ GPIO71 74
EC_ENABLE# 1 0R2J--2-GP 1ST = 84.T3906.A11
17,40,51,52,54 SIO_SLP_S3#
GPIO14/TB1
64 GPIO01/TB2 TP2418 PSL
2nd = 84.T3906.E11

-X
WLAN_PCIE_WAKE# R2405 1 2 0R2J--2-GP PCH_WAKE#
ECSCI#_KBC
ECSCI#/GPIO54 29 3D3V_AUX_KBC
DY 32 ECRST#
EXT_RST# 85
64 DC_BATFULL
27 KBC_BEEP
44 CHG_ON#
KBC_BEEP
CHG_ON#
118
62
GPIO15/A_PW M
GPIO21/B_PW M KBRST#/GPIO86 122 SIO_RCIN# 18 KBC PWR supply at PSL mode. U2402
GPIO13/C_PW M
Modified 20151007 64 CHARGE_LED 65 GPIO32/D_PW M VSBY 75 KBC_VSBY 0R0402-PAD 1
KBC_VBKUP 0R0402-PAD 1
2 R2494 3D3V_AUX_S5 1 GND DY
NO_USE_04 22 114 2 R2488
VBKUP RTC_AUX_S5 VDD 3
Delete DS3 RelativeComponents TP2425 1 NO_USE_09 GPIO45/E_PW M/D TR1#_BOU T1 KBC_VCORF C2422 1 2
16 GPIO40/F_PW M/1_W IRE/ RI1# VC ORF 44 2 RESET#
PECI R2474 1 2 SC1U10V2KX--L1-GP
26 FAN1_PWM 81 GPIO66/G_PW M/PSL_GPIO66 PECI 13 H_PECI 4 74.03809.07B
KBC_DPW ROK 1 2 VD1_EN# 66 GPO33/H_PW M/VD 1_EN # SERIRQ/GPIOF0 125
43R2J--GP
INT_SERIRQ 18 < ---- Viber Del TPM
R2463 0R0402-PAD
GPIO24 6 AD_OFF 43,44 < ---08/06 AD_OFF TPS3809K33-2-GP
VD_IN1 104
26 VD_IN1 GPIO80/VD_I N1 GPIO36/TB3/C TS1# 15 PCH_RSMRST# 17
1

R2430 Thermal VD 26 VD_OUT1# VD_OUT1# 110 GPIO44/SCL4B 21 KBC_NOVO_BTN# SIO_SLP_S4# 17,40,51 NOVO button Fun define: one key to recover OS.
Nuvoton KBC PSL Power Switched Logic
GPIO82/IOX_LDSH/VD _OU T1
1KR2J--L2-GP 26 VD_OUT2# VD_OUT2# 112 GPIO84/IOX_SCLK/VD_OU T2 PSL_IN4#/GPI43 20 < ---06/24 AOU_IFLG# 3D3V_AUX_S5 3D3V_AUX_KBC

Te
LID_CLOSE#
PSL_IN3#/GPI42 17
06/16 MAX R1717 DY DY GPIO46/SDA4B/CI RR XM 23 ME_FWP_EC 19
LID_CLOSE# 66 NOVO button wake KBC at PSL mode.
2

17 SYS_PWROK 84 GPIO77/SPI_MISO
3D3V_AUX_S5 C2406
17 AC_PRESENT 83 GPIO76/SPI_MOSI GPIO87/CIRRXM/ SI N_C R 113 USB_PW R_EN 36
W IRELESS_EN 82 GPIO75/SPI_SC K KBC_NOVO_BTN# KBC_PWRBTN_EC#
61 WIRELESS_EN GPIO34/SIN1/CI RR XL 14
1.Enter PSL mode (Entry S5 after 10sec) :
5V_EN 1 S5_ENABLE 40
79 GPIO02/SPI_CS# 1 2
40,45 5V_EN AFTP2403
Low Low 3D3V_AUX_KBC : OFF (KBC PWR supply)

1
5 SCD1U16V2KX--L-GP
GND PECI R2410
124 GPIO10/LPCPD # 18 PSL
17,20 ME_SUS_PWR_ACK_R
31 LAN_PW R_ON
1 2 PM_SUSWARN#_KBC 121
GPIO85/GA20
GND
GND 45 2. At PSL mode (SPEC: S5<10mW) 330KR2J--L-GP
R2402 0R2J--2-GP E51_TXD_KBC 111
GPIO83/SOUT_C R GND 78 PSL

1
DY 55 PANEL_BLEN 9 GPIO65/SMI# 89 R2409 R2411

S
GND
PSL mode(AC or DC):
18 PM_CLKRUN#_EC_R 1
R2403
2 PM_CLKRUN#_EC 8
GND 116
DY C2403
SC100P50V2JN-3GP KBC_PWRBTN_EC#:Low EC_ENABLE# 1 2 EC_ENABLE#_G_1 1 2 EC_ENABLE#_G G Q2402
PSL

2
GPIO11/CLKRU N#
0R0402-PAD 30 1 R2472 2
(1)4sec: PWR
G
103 R2472 close to Pin103 DMP2130L-7-GP
27 AMP_MUTE# GPIO55/CLKOU T/IOX_DI N_DIO AGND 0R0402-PAD EC_ENABLE#_G S5_ENABLE 3D3V_AUX_KBC
1KR2F-3-GP 20KR2J--L3-GP D 84.02130.031
61 WLAN_PW RON R2404 1 AOAC 2 0R2J--2-GP NPCE285PA0DX--1-GP Button shut down PSL PSL 2nd = 84.00102.031
Hi Low OFF

D
2013/9/12

ch
Reserved AOAC 071.00285.0A0G
EC_AGND
GPIO83/SOUT_CR & GPIO87/SIN_CR
(2) 8sec: KBC reset
Need reserved TP for Debug
6/18 U2403 Change Part Number to 71.00285.0A0G (285P)
PSL Wake(AC or DC): Q2403
NOTE: G
P WM Signal :
B EC_ENABLE#_G S5_ENABLE 3D3V_AUX_KBC D S5_ENABLE
B
NOTE: 1.If unused, select altrnative GP IO function
Connect GND and AGND planes via either and enable internal pull-down. S PSL
0R resistor or one point layout connection. 2.P lease measure and make sure that the Low Hi ON Notice:ZZ.2N702.J3101

2N7002K--2-GP
rise time of VCC_P OR is less than 10us.
84.2N702.J31
2ND = 84.2N702.031

ni
3rd = 84.2N702.W31

EC GPIO PH EC GPIO PL EC_GPIO47 High Active

3D3V_AUX_KBC
Q2405
3D3V_S5 R2450 PROCHOT_EC G
RN2403
AMP_MUTE# 1 2 10KR2J--3-GP R2478
BAT_SCL
DY
2 3 D H_PROCHOT#_EC 1 2 H_PROCHOT# 4,46

1
ca
1 4 BAT_SDA R2448
1 2 USB_PW R_EN S 0R0402-PAD
100KR2J--1-GP R2480 Notice:ZZ.2N702.J3101

SRN4K7J--8-GP DY
KBB_DEFINE1_R 2 R2440 1 10KR2J--3-GP 100KR2J--1-GP 2N7002K--2-GP
R2452 65 KBB_DEFINE1_R
RN2407 1 2 WLAN_PCIE_WAKE# 84.2N702.J31

2
1 4 NO_USE_04 10KR2J--3-GP DGPUHOT 2 R2443 1 10KR2J--3-GP 2ND = 84.2N702.031
2 NO_USE_05
3 3rd = 84.2N702.W31
AD_OFF 1 R2476 2 1KR2J--1-GP
SRN4K7J--8-GP DY 3D3V_AUX_S5
R2435
1 2 BAT_IN#
R2458 100KR2J--1-GP RN2404 RN2410
CAP_LED 1 4
E51_TXD_KBC 2 1 E51_TXD
E51_TXD 61 1 4 LID_CLOSE# NUM_LED 2 3
0R0402-PAD R2434 2 3 KBC_NOVO_BTN# KBC_NOVO_BTN# 66
2 1 ECRST#

l
R2451 10KR2J--3-GP SRN10KJ--5-GP SRN10KJ--5-GP
USB_PW R_EN E51_RXD RN2406 3D3V_AUX_S5
1 2 E51_RXD 61
S5_ENABLE KB_MATRIX_DEBUG 2 R2444 1
DY
10KR2J--3-GP
0R2J--2-GP 1 4
5V_EN 3D3V_S0
DY 2 3

1
SRN10KJ--5-GP
RN2408 R2477
1 4 NO_USE_03 R2447 2 1 FAN_REVERSE_CTRL# 10KR2J--3-GP
2 3 NO_USE_06 100KR2J--4-GP
DY DY

2
SRN10KJ--5-GP R2484
1 2 KBC_PWRBTN_EC#
65,66 KBC_PWRBTN# 470R2J--2-GP
RN2409
1 4 NO_USE_07

1
2 3 NO_USE_08
R2492 C2423
SRN10KJ--5-GP
DY 100KR2J--1-GP SC220P50V2KX--3GP

2 1
R2438
2 1 KBB_DEFINE1_R
DY

2
10KR2J--3-GP
R2439 DY
2 1 KB_MATRIX_DEBUG
10KR2J--3-GP

A A

R2446 2
DY
1 FAN_REVERSE_CTRL#
100KR2J--4-GP

Nuvoton KBC PSL Logic

KBB_DEFINE1_R use MODEL_ID to Define Lenovo Key:

LV115: "Fast Forward" Key

Eletro-XTechnical Eletro-XTechnical
<Core Desiiign>
LV114: "Delete" Key
Wistron Corporation
21F,,, 88,,,Sec.1,,, Hsiiin Taiii W u Rd., Hsiiichiiih,,,
Taipei Hsiiien 221, Taiwan, R...O...C...

Title

NPCE285
Siiize Document Number Rev
A1
LV115 SKL-U -1
Date: Monday,,, Apriiilll 25, 2016 Sheet 24 off 102
5 4 3 2 1
 5 4 3 2 1

3D3V_SPI
3D3V_S5
R2501

0R0402-PAD

SSID = Flash.ROM 1 2

SPI ROM Equal length need to less than 500mil

C2501 C2502 Eletro-XTechnical
SC10U6D3V3MX--L-GP SCD1U16V2KX--L-GP
Test point

2 1

2 1
DY
U2502
1ST GIGA DEVICE 8MB 072.25B64.0C01 3D3V_SPI

3D3V_S5 1 TP2503 TPAD14--

2ND WINBOND 8MB 72.25Q64.Q01
D 3RD OP-GP D

1
DY
R2505 R2506
4K7R2J--2-GP 10KR2J--3-GP

2
3D3V_SPI
U2502
R2502
2 1 SPI_CS0# 1
RN2501 2
18,24 SPI_CS0#_R
0R0402-PAD SPI_SO CS# VCC 8 SPI_HOLD_0#_1 R2551 1
3 2 2 33R2J--2-GP
18,24 SPI_SO_R
SPI0_W P#_1 SO IO3 7 SPI_CLK_R_1
SPI_HOLD_0# 18
1 4 3 R2552 1 2 33R2J--2-GP
18 SPI0_WP# IO2 SCLK 6 SPI_SI0_R_1 R2553 1
SPI_CLK_R 18,24
4 5 2 33R2J--2-GP
SRN33J--5-GP--U VSS SI SPI_SI0_R 18,24
C2503
SC4D7P50V2CN--1GP GD25B64CSIIGR--GP C2504 C2505

2 1

SC4D7P50V2CN--1GP

SC4D7P50V2CN--1GP
DY DY DY

2 1

2 1
072.25B64.0C01

El
1ST = 072.25B64.0C01

2ND = 72.25Q64.Q01

et
C C

ro
-X
Te
ch
B B

ni
SSID = RBATT

ca
SSID = RBATT

l
High Detect
3D3V_AUX_S5 Need to Check whether to PD in PCH Side
RTC_AUX_S5 Q2501
Q2503
2
+RTC_VCC DMN5L06K--7-GP
-GP
3 RTC1
R2504 RTC_PWR D S RTC_DET 1 R2514 2
0R0402-PAD RTC_DET_R 20
1 RTC_PWR 1 2 1
PW R
1

1KR2J--1-GP 2
GND
84.05067.031
C2506 BAS40CW--GP NP1
NP1

1
SC1U10V2KX--L1-GP 83.00040.E81 NP2 2nd = 084.00138.0A31
G
2

NP2 5V_S0 R2508

A 6D2MR2J--GP A

Width=20mils
BAT--060003HA002M213ZL-GP--U1

2
62.70014.001
<Corrre Desiiign>
1ST = 62.70014.001
Test point 2ND = 62.70001.061 Wistron Corporation
21F,,, 88, Sec...1, HsiiinTai W u Rd...,,,Hsiiichih,
1 +RTC_VCC

Eletro-XTechnical Eletro-XTechnical
Taiiipeiii Hsiiien 221,,, Taiiiwan,,, R.O.C...
AFTP2501
1 Title
AFTP2502
Flash(KBC+PCH)/RTC
Siize Document Number Rev
A2
LV115 SKL-U -1
Date: Monday,,, Aprrriill25, 2016 Sheet 25 off 102
5 4 3 2 1
 5 4 3 2 1

Main Func = Thermal Sensor

*Layout* 15 mil

Eletro-XTechnical
5V_FAN_S0

1
1
D2601 C2604 C2605

SC4D7U25V5KX--L2-GP
RB551V30-GP SCD1U16V2KX-L--GP
83.R5003.H8H

2
2
A
2nd = 83.R5003.T8F
D D

07/31 C2604 Change part number 78.47523.5BL to 78.47522.L4L,

4.uF, 0805, 不
原
值 25V
FAN1
7
24 FAN_REVERSE_CTRL# 1

24 FAN1_PWM 2
FAN_TACH1_C 3
4
5V_FAN_S0 5 1 FAN_REVERSE_CTRL#
6 AFTP2605 1 FAN1_PWM
AFTP2601 1 FAN_TACH1_C
AFTP2602 1 5V_FAN_S0
3D3V_S0 5V_FAN_S0 AFTP2603 1 5V_S0 5V_FAN_S0
ACES--CON5--22--GP--U AFTP2604
20.F1639.005

1
El
1ST = 20.F1639.005 R2630
R2614 R2613 1 2
10KR2J--L-GP DY 10KR2J--L-GP 2ND = 020.F0146.0005 0R0603-PAD

2
D2602
2.System Sensor, Put on palm rest 24 FAN_TACH1 A K FAN_TACH1_C

Close to Thermal sensor RB551V30-GP

TBD PU 3D3V_AUX_KBC

et
83.R5003.H8H
Note: Need R1717 PD: Enable Thermal VD Fun.
3D3V_AUX_KBC
2nd = 83.R5003.T8F DY
Note: (1) VD_IN1 for System sensor R2618
1

3D3V_S0 3D3V_S0
06/11 Delete R2611 & R2621 Connect to 3D3V_AUX_S5

2
(2) VD_IN2 for CPU sensor
1
R2615
16KR2F--GP 0R2J--L-GP
C TV C

1
Close to CPU chips

ro
R2617 R2624 R2625
2

3D3V_S0 1 2 DY 2KR2F--3-GP DY 2KR2F--3-GP

0R0402-PAD

2
1
VD_IN1 24
R2607
1

2KR2F--3-GP D2603
R2610
1

TV NTC--100K--11-GP--U C2615 C2616 2

-X
VD_OUT1# 24

2
SCD1U16V2KX--L-GP SC100P50V2JN--3GP Q2603
69.60013.201 Not ic e: ZZ .2N 70 2. J3 10 1
S THERM_SYS_SHDN# 3 DY
TV TV
2

24,40 PURE_HW_SHUTDOWN# D 1 VD_OUT2# 24

2

VD_IN1_C 1 R2612 2
0R0402-PAD G BAW 56--5--GP

TBD PU 3D3V_AUX_KBC
VR_RDY 40,46

1
C2607 2N7002K--2-GP
3D3V_AUX_KBC
R2606
84.2N702.J31 83.00056.Q11
DY

SC4D7U6D3V3KX--GP
10KR2J--L-GP

2 1
2ND = 84.2N702.031 1ST =83.00056.Q11
DY 3rd = 84.2N702.W31

Te
2
2ND = 75.00056.07D
1

R2616
16KR2F--GP
TV
Close to KBC chips
2

VD_IN2 24
1

R2619
1

ch
NTC--100K--11-GP--U C2617 C2618
SCD1U16V2KX--L-GP SC100P50V2JN--3GP
TV 69.60013.201
TV TV
2

2
2

B
VD_IN2_C 1 R2620 2
0R0402-PAD
T8=85 degree B

Thermal config
Function

ni
Thermal VD NCT7718W
LOCATION
U2601 DY ASM
Q2601 DY ASM
Q2602 DY ASM

ca
RN2601 DY ASM
R2601 DY ASM
R2605 DY ASM
C2601 DY ASM
C2602 DY ASM

l
C2603 DY ASM

R2610 ASM DY
R2619 ASM DY
R2615 ASM DY
R2616 ASM DY
A R2612 ASM DY A

R2620 ASM DY
R2624 ASM DY
R2625 ASM DY <Corrre Desiiign>
C2615 ASM DY
C2617 ASM DY Wistron Corporation
21F,,, 88, Sec...1, HsiiinTai W u Rd...,,,Hsiiichih,
C2616 ASM DY
Eletro-XTechnical Eletro-XTechnical
Taiiipeiii Hsiiien 221,,, Taiiiwan,,, R.O.C...

C2618 ASM DY Title

D2603 ASM DY THERMAL NCT7718W/Fan

R1717 ASM DY Siize Document Number Rev
A2
LV115 SKL-U -1
Date: Monday,,, Aprrriill25, 2016 Sheet 26 off 102
5 4 3 2 1
 5 4 3 2 1

5V_S0 AUD_5VD
Current > 2A
1 R2703 2

Eletro-XTechnical

1
0R0603-PAD C2706 C2716 SCD1U25V2KX--L-GP SCD1U25V2KX--L-GP
C2705
C2707 C2708
2 1

2 1
SC1U10V2KX--L1-GP

DY

2
SC10U6D3V3MX--L-GP

SC10U6D3V3MX--L-GP
D D

MOAT
5V_S0 AUD_5VA

1 R2726 2
1

0R0603-PAD C2727
SC10U6D3V3MX--L-GP
2

AUD_3VD

ALC_AGND

1
SCD1U25V2KX--L-GP R2702 1 2 0R0402-PAD
C2701
C2702
MOAT

SC1U10V2KX--L1-GP
C2704 1 2 SCD1U25V2KX--L-GP

2
3D3V_S5 AUD_3V3_S5 Place close to pin1 Place close to pin8
1 R2705 2
1

0R0603-PAD C2712
AUD_5VA

El
SC10U6D3V3MX--L-GP
2

1
ALC_AGND SCD1U25V2KX--L-GP
C2709
SC2D2U10V3KX--L-GP C2714

2
3D3V_S0 AUD_3VD
Place close to pin26
1 R2701 2

et
ALC_AGND
0R0603-PAD C2703
SC10U6D3V3MX--L-GP
2 1

AUD_1D8VD

MOAT

1
C C
1D8V_S0 AUD_1D8VD C2711

ro
SC4D7U6D3V3KX--L-GP

2
1 R2704 2
RING2/SLEEVE Trace width must > 40mils
1

0R0603-PAD C2710 ALC_AGND U2701

SC10U6D3V3MX--L-GP RN2701
1 DVDD AUDIO_PC_BEEP C2723 1 2 AUDIO_BEEP 1 4
PCBEEP 11 19
2

AUD_3V3_S5 SCD1U25V2KX-L--GP SPKR

2 3
DVDD_IO KBC_BEEP 24
8 DVDD-IO MIC2-L(PORT-F-L)/RING2 13 RING2 66
ALC_AGND 14
MIC2-R(PORT-F-R)/SLEEVE SLEEVE

1
MIC2 C2724 1 2 SC4D7U6D3V3KX--L-GP 66 SRN10KJ--5--GP
20
MIC2-CAP 15

-X
AUD_5VD AVDD1 R2709
33 AVDD2
LINE1-R(PORT-C-R) 17 2K2R2J--L1-GP
16 VD33STB LINE1-L(PORT-C-L) 18 ALC_AGND

2
34 PVDD1 SPK-OUT-LP 35 AUD_SPK_L+ 29
AUD_1D8VD
39 PVDD2 SPK-OUT-LN 36 AUD_SPK_L- 29 SPK 4Ω 40mils

MOAT 20151024 modify

29 CPVDD SPK-OUT-RP 38
SPK-OUT-RN 37
AUD_SPK_R+ 29
C2715 1 2 SC1U10V2KX--L1-GP VREF 22 RN2702 AUD_SPK_R- 29
C2713 CPVEE VREF ALC_AGND
C2717 1 2 SC1U10V2KX--L1-GP 27 25 HP_OUT_L_AUD 1 4

Te
CPVEE HPOUT-L(PORT-I-L) HP_OUT_L 66
2 1

SC4D7U6D3V3KX--L-GP R2720 1 2 100KR2J--1-GP DY 26 HP_OUT_R_AUD 2 3

C2718 1 2 SC4D7U6D3V3KX--L-GP LDO1_CAP HPOUT-R(PORT-I-R) HP_OUT_R 66
21 LDO1-CAP
ALC_AGND C2719 1 2 SC4D7U6D3V3KX--L-GP LDO2_CAP 32 LDO2-CAP SRN47J--7--GP
C2720 1 2 SC4D7U6D3V3KX--L-GP LDO3_CAP 6 LDO3-CAP
1 R2719 2 Tied at one point only under AUD_CBN C2725 1 2 SC1U10V2KX--L1-GP
CBN 28
Codec or near the Codec ALC_AGND
CBP 30
AUD_CBP
0R0603-PAD C2726 1 2 SC22P50V2JN--L-GP DMIC_DATA_C 2 GPIO0/DMIC-DATA12
C2721 1 2 SC22P50V2JN--L-GP DMIC_CLK_C 3 GPIO1/DMIC-CLK R2715 R2716 1 2 2KR2F--3-GP SLEEVE
MIC2V 1 2 MIC2_VREFO R2717 2 2KR2F--3-GP RING2
4 MIC2-VREFO 23 1
19 HDA_CODEC_SDOUT
R2710 1 AC97_DATIN SDATA-OUT LINE1-VREFO-L 24 0R0402-PAD
2 7 SDATA-IN
19 HDA_SDIN0 0R0402-PAD
HDA_CODEC_BITCLK_C

ch
R2713 1 2 0R0402-PAD 5
19 HDA_CODEC_BITCLK BCLK
G2701 1 2 GAP--CLOSE 1 2 9
Near AVDD1 and AVDD2 power source input C2722 SC22P50V2JN--L-GP SYNC AVSS1 19
10 DC_DET AVSS2 31
G2702 1 2 GAP--CLOSE AUD_SD# 40 PDB
12 HP/LINE1-JD(JD1) GND 41
B 19 HDA_CODEC_SYNC B
ALC_AGND ALC_AGND
ALC3240-VA3-CG--GP
ERN2701
1 4 DMIC_DATA_C
55 DMIC_DATA 071.03240.0A03
0R3J--0-U--GP DMIC_CLK_C
ER2722 1 DY 2
SA_ESD 55 DMIC_CLK
2 3

ni
0R3J--0-U--GP SRN22-3-GP
DY
ER2721 1 2 AUD_3VD
ERN2701 SET 22 ohm in SA
R2708 1 2 100KR2J--L-GP
EC2701 1 2 SCD1U25V2KX--L-GP DY 66 HP_DET#
R2721 1 2 200KR2F--L-3-GP ALC233_SENSE_A

2 SCD1U25V2KX--L-GP

ca
EC2702 1 DY R2708 power should follow DVDD (pin1) power rail.
EC2703 1 2 SCD1U25V2KX--L-GP DY If DVDD=3.3V, R7 power source should be change to 3.3V
EC2704 1 2 SCD1U25V2KX--L-GP DY

ALC_AGND

l
3D3V_S5

Q2701
1 6
3D3V_S0
2 5
AUD_PD#_1 3
4 HDA_CODEC_RST#
1

DMN5L06DW K--7-GP R2722

DY 1KR2J--1-GP
D2701 DY
24 AMP_MUTE# R2724 1 2 0R2J--2-GP DY AUD_PD#_2 2
2

A A

DY 3 AUD_SD#

19 HDA_CODEC_RST# R2723 1 2 0R2J--2-GP DY AUD_PD#_1 1

R2725 1 2 22R2J--2-GP BAW56-5-GP

<Corrre Desiiign>
83.00056.Q11
FAE 1ST =83.00056.Q11 Wistron Corporation
HDA_RST#_CODEC: 21F,,, 88, Sec...1, HsiiinTai W u Rd...,,,Hsiiichih,
High=1.8V 2ND = 75.00056.07D
Eletro-XTechnical Eletro-XTechnical
Taiiipeiii Hsiiien 221,,, Taiiiwan,,, R.O.C...
Low=0V
this signal might cause AUD_SD# always low when R2710=0ohm Title
You should add level shift on HDA_RST#_CODEC signal when Codec PIN9 DVDDIO= 1.5V.
Audio Codec ALC3234
Siiize Document Number Rev
A2
LV115 SKL-U -1
Date: Monday,,, Aprrriill25, 2016 Sheet 27 off 102
5 4 3 2 1
 5 4 3 2 1

Eletro-XTechnical
INTERNAL STEREO SPEAKERS
D D

RIGHT SIDE
R2903 1 2 0R0603-PAD AUD_SPK_R+_C
27 AUD_SPK_R+
R2904 1 2 0R0603-PAD AUD_SPK_R-_C
27 AUD_SPK_R-

1
Place these EMI components C2902 C2903
close to speaker connector. DY DY

SC1KP50V2KX-1GP

SC1KP50V2KX-1GP
SPK1

2
5

Only needed if speaker 1

El
connector is physically far from 2
audio codec. When in doubt, it's 3
always a good idea to have 4
population option.
LEFT SIDE 6

et
ACES-CON4-17-GP-U1 1 R2907 2
20.F1621.004 0R0402-PAD
R2905 1 2 0R0603-PAD AUD_SPK_L+_C
27 AUD_SPK_L+
2nd = 20.F1937.004 1 R2908 2
R2906 1 2 0R0603-PAD AUD_SPK_L-_C 0R0402-PAD
27 AUD_SPK_L-
C
3rd = 020.F0243.0004 C

ro
R2909 1 DY 2 0R2J-2-GP
1

C2904 C2905 R2910 2 0R2J-2-GP

1 DY
2 1

08/12 SPK1 20.F2348.007 Change to 20.F1621.004

SC1KP50V2KX-1GP

SC1KP50V2KX-1GP
2

-X
06/12 SPK1 原
4Pin, 換
7 pin 接Hall Sensor 訊 訊

ALC_AGND

Te
1 AUD_SPK_L+_C 1 AUD_SPK_R+_C
AFTP2910 1 AUD_SPK_L-_C AFTP2908 1 AUD_SPK_R-_C
AFTP2911 AFTP2909
1
AFTP2912
1

1
1
ED2901 ED2902 ED2904 ED2903

ch
Only needed if speaker
ESD5B5D0ST1G-GP-U

ESD5B5D0ST1G-GP-U

ESD5B5D0ST1G-GP-U

ESD5B5D0ST1G-GP-U
connector is physically far from
Place these EMI components audio codec. When in doubt, it's DY DY DY DY
close to speaker connector. always a good idea to have
B B
population option.
2

2
2

2
ni
ca
l
A <Core Desiiign> A

Wistron Corporation
21F, 88, Sec.1, Hsiiin Taiii Wu Rd., Hsiiichiiih,
TaiiipeiiiHsiiien 221, Taiiiwan, R.O.C.

Eletro-XTechnical Eletro-XTechnical
Tiitlle

Audio IO
Siize DocumentNumber Rev
A3
LV115 SKL-U -1
Date: Monday, Apriiilll25,2016 Sheet 29 of 102
5 4 3 2 1
 5 4 3 2 1

REGOUT R3103 1 2 0R0805-PAD VDD10

C3138 close to Pin3 , C3139 close to Pin8
3D3V_LAN_S5 C3140 close to Pin30,C3136 close to Pin22

1
C3140 C3138 C3139 C3137 C3136 C3141
R3102 1 DY 2 0R3J--0-U--GP C3142

SCD1U16V2KX--L-GP

SCD1U16V2KX--L-GP

SCD1U16V2KX--L-GP

SCD1U16V2KX--L-GP

SCD1U16V2KX--L-GP

SC1U10V2KX--L1-GP
Eletro-XTechnical
SCD1U16V2KX-3GP

2
3D3V_S5 Q3101 DY
AO3413L-GP
S D Need check whether change to R3101

1
1

1
C3152 C3150
For RTL8111G(S) Series/ RTL8111GUS Series/ RTL8111H(S) Series/

G
C3154 C3153 R3131 SC1U10V2KX--L1-GP SC1U10V2KX--L1-GP
SCD1U16V2KX--3GP SCD1U16V2KX--3GP 100KR2J--1-GP 84.03413.B31 RTL8106EUS Series/ RTL8107E(S) Series/ RTL8118AS Series
2

2
DY For RTL8111G(S)/ RTL8111GUS/ RTL8106EUS

2
*Place C3138 to C3141 close to each VDD10 pin-- 3, 8, 22, 30
D C3132,C3133 close to Pin22 D

LAN_PWR_ON_T 1 2 LAN_PWR_ON_T2 For RTL8111G(S)/ RTL8111GUS/ RTL8106EUS

*Place C20 and C21 close to each VDD10 pin-- 22 (Reserved)

1
R3132 VDD10
Q3102 1KR2J--1-GP C3151
24 LAN_PWR_ON G SC1U10V2KX--L1-GP

2
DY
D C3130 C3131
For RTL8106E Series

SCD1U16V2KX--L-GP

SC1U10V2KX--L1-GP
2 1

2 1
S
Not ic e: ZZ .2N 70 2. J3 10 1

2N7002K--2-GP
C3130,C3131 close to Pin30
84.2N702.J31
2ND = 84.2N702.031
3rd = 84.2N702.W31 08/12 add 3D3V_S5 to 3D3V_LAN_S5 Circuit

U3101

VDD10 3 12
AVDD10 CLKREQ# PCIE_LAN_WAKE#_R 1 R3130 2 CLKREQ_PCIE#2 18

El
8 21
AVDD10 LANW AKE# 0R0402-PAD PCH_WAKE# 17,24,79 R3108
30 20 ISOLATE# 1 2 1KR2J--1-GP 3D3V_S0
AVDD10 ISOLATE# PLT_RST#
19 PLT_RST# 17,24,40,61,68,76
PERST#
3D3V_LAN_S5 32
AVDD33
11 28 LAN_XTAL1 R3111 1 2 15KR2J--1-GP
AVDD33 CKXTAL1
29 LAN_XTAL2
1

1
C3147 C3143 C3144 C3145 C3146 23 CKXTAL2
3D3V_LAN_S5 VDDREG
DY DY
SCD1U16V2KX--L-GP

SCD1U16V2KX--L-GP

SCD1U16V2KX--L-GP

SC4D7U6D3V3KX--L-GP

SC4D7U6D3V3KX--L-GP
16 PEG_CLK2_CPU# 18
22 REFCLK_N 15 PEG_CLK2_CPU 18
2

2
2

DVDD10 REFCLK_P
RSET 1 R3113 2 2K49R2F--GP

et
31
1 RSET
32 MDI0+ MDIP0
2 24 REGOUT
32 MDI0- MDIN0
4 REGOUT
MDI1+
For RTL8111G(S) Series/ RTL8111GUS Series/ RTL8111H(S) Series/
32 MDIP1
MDI1- 5
32 MDIN1
MDI2+ 6 14 PCIE_TX_CON_N6 16
MDIP2 HSIN
RTL8106EUS Series/ RTL8107E(S) Series/ RTL8118AS Series
32 7 13
MDI2- MDIN2 HSIP PCIE_TX_CON_P6 16
C 32 9 C
MDI3+ MDIP3
10 18 PCIE_RXN4_L C3117 1 2 SCD1U16V2KX--L-GP
32 MDI3- MDIN3 PCIE_RX_CPU_N6 16
C3132,C3133 close to Pin22

ro
32 HSON 17 PCIE_RXP4_L C3116 1 2 SCD1U16V2KX--L-GP PCIE_RX_CPU_P6 16
C3147 close to Pin23 32 MB_LAN_ACT# 27
26 LED0
HSOP

LED1/GPO
C3143 close to Pin32 32 MB_LAN_LINKUP# 25
LED2 GND
33
VDD10

C3144 close to Pin11 RTL8111GUS--CG--GP--U2

71.08111.W03 BOM CHANGE TO RTL8111H:SC50H01259 C3133 C3132

SCD1U16V2KX--L-GP

SC1U10V2KX--L1-GP
-X

2 1

2 1
25MHz XTAL LAN_BOM_CTRL

C3109
1 2

Te
X3101 SC15P50V2JN--L-GP

LAN_XTAL1 1 4
LAN and Transformer Config:
1

R3114
1MR2J--L3-GP C3108

DY 2 3 1 2
LAN/Transformer
2

LAN_XTAL2 SC15P50V2JN--L-GP

ch
XTAL-25MHZ--181-GP

82.30020.G71
B 2nd = 82.30020.D41 B

Crystal 27MHz
MAIN HASONIC 82.30020.G71 78.15034.L1L

ni
2ND HARMONY 82.30020.D41 78.18034.1FL

ca
l
A A

<Corrre Desiiign>

Wistron Corporation
21F,,, 88, Sec...1, HsiiinTai W u Rd...,,,Hsiiichih,

Eletro-XTechnical Eletro-XTechnical
Taiiipeiii Hsiiien 221,,, Taiiiwan,,, R.O.C...

Title

LAN_RTL8111
Siiize Document Number Rev
A2
LV115 SKL-U -1
Date: Monday,,, Aprrriill25, 2016 Sheet 31 off 102
5 4 3 2 1
 5 4 3 2 1

10/100M/1000M Lan Transformer 10/100/1000 LAN surge circuit

For test stuff
XF3201
Change LAN CONN 20151007 LAN Connector Eletro-XTechnical
1 12 RJ45_6
31 MDI1- RD+ RX+
2 11 RJ45_3
XRF_TDC_1 31 MDI1+ RD- RX-
3 10 MCT4
4 RDCT RXCT 9 MCT4 RJ45
1

C3204
31 MDI0-
5 TDCT TXCT 8 RJ45_2 31 MB_LAN_ACT# R3220 2 1 330R2J--3-GP MB_LAN_ACT#_R B2
B2 AMBER
SCD1U16V2KX--L-GP
31 MDI0+
6 TD+ TX+ 7 RJ45_1 3D3V_LAN_S5 R3223 1 2 0R0402-PAD MB_LAN_ACT_PWR B1
B1
TD- TX-
2

D
XFORM--208-GP
1ST = 68.HD081.30B RJ45_1
9
CHASSIS#9
D
1
MDO0+
2ND = 68.68167.30D
68.68161.30A RJ45_2 2
MDO0- 1ST = 022.10001.00B1
RJ45_3 3
RJ45_4 MDO1+
4 2ND = 022.10001.00U1
XF3202 RJ45_5 MDO2+
5
RJ45_6 MDO2-
6
1 12 RJ45_4 RJ45_7 7
MDO1- 3RD =022.10001.00Z1
31 MDI2+ RD+ RX+ RJ45_8 MDO3+
2 11 RJ45_5 8
31 MDI2- RD- RX- MDO3-
3 10 MCT4 10
RDCT RXCT MCT4 CHASSIS#10
4 9
31 MDI3+
5 TDCT TXCT 8 RJ45_7 31 MB_LAN_LINKUP# R3222 2 1 330R2J--3-GP MB_LAN_LINKUP#_R A2
A2 Green
6 TD+ TX+ 7 RJ45_8 3D3V_LAN_S5 R3224 1 2 0R0402-PAD MB_LAN_LINKUP_PWR A1
A1
1

31 MDI3- RJ45
TD- TX-
C3202 RJ45-12P--64-GP--U
SCD1U25V2KX--L-GP XFORM--208-GP 022.10001.00B1
2

DY 68.68161.30A 1ST = 68.HD081.30B

LAN GIGA 2ND = 68.68167.30D
RJ45_1 1
ED3202
RJ45_2 1 AFTP3202

El
RJ45_3 1 AFTP3203
MCT4 R3214 MCT4_C
RJ45_4 1 AFTP3204 2 1 1 2
RJ45_5 1 AFTP3205 75R5F--1-GP
AFTP3206
RJ45_6 1
RJ45_7 1 AFTP3207
AFTP3208 THW 4006KV-SMB-GP
RJ45_8 1
AFTP3209 069.A0002.0001
RJ45 Pin define 1ST = 069.A0002.0001 C3203

1 2
SC100P3KV8JN--2-GP
2ND = 069.A0007.0001

et
3rd = 069.A0007.0011
10/6 Change ED3202 1st & 3rd source

C C

ro
3D3V_S0
3D3V_S0

ED3203 ED3204

-X
MDI0+ 6 1 MDI1+ MDI2+ 6 1 MDI3+
31 MDI0+ I/O4 I/O1 MDI1+ 31 31 MDI2+ I/O4 I/O1 MDI3+ 31
5 VDD GND 2 5 VDD GND 2

MDI0- 4 3 MDI1- MDI2- 4 3 MDI3-

31 MDI0- I/O3 I/O2 MDI1- 31 31 MDI2- I/O3 I/O2 MDI3- 31

AZC099-04S--2-GP AZC099-04S--2-GP

075.09904.0A7C 075.09904.0A7C

Te
DY DY

8/25 將
ED3203,ED3204 屬
ESD STUFF OPTION 改
DY, 上
Wake on Lan

10/13 ED3203,ED3204 改
跟 , 增
一
ED3501一 加
Source
10/23 將 將75.09904.07C, 因
3rd Source將 有
原 不
此
米
50米 跟
(Part number跟 一
ED3501一 別
,BOM別
)

ch
改
10/23 ED3203, ED3204 ESD STUFF OPTION改 上
不
DY,不

B B

ni
ca
l
A A

<Corrre Desiiign>

Wistron Corporation
21F,,, 88, Sec...1, HsiiinTai W u Rd...,,,Hsiiichih,

Eletro-XTechnical Eletro-XTechnical
Taiiipeiii Hsiiien 221,,, Taiiiwan,,, R.O.C...

Title

RJ45&Transformer
Siiize Document Number Rev
A2
LV115 SKL-U -1
Date: Monday,,, Aprrriill25, 2016 Sheet 32 off 102
5 4 3 2 1
 5 4 3 2 1

Card Reader RTS5170

R3320
6K2R2F--GP

16 USB_CPU_PP8 1 R3327 2 0R0402-PAD USB_SD_DP

2 1
Eletro-XTechnical

USB_SD_DM
USB_SD_DP
1 R3328 2 0R0402-PAD USB_SD_DM

RREF
16 USB_CPU_PN8

SD_CLK_L and CARD_CTRL0 trace length shorter , surround with GND.

U3301

25

17

3
2
RTS5170-GR--GP +3.3V_RUN_CARD

DP
DM
GND

RREF
GPIO0
D D
OPEN TYPE SD Socket
22 SP14 SP7 14 SD_CD#
SD_DATA2 21 SP13 SP6 13

SC4D7U6D3V3KX--GP
SD_DATA3 20 12

SCD1U16V2KX-3GP
SP12 SP5 SD_DATA0 C3307 C3308
19 SP11 SP4 11 SD_DATA1
SD_CMD

1
18 SP10 SP3 10
16 SP9 SP2 9 SD_WP

CARD_3V3

2 1
SD_CLK 15 SP1 8

2
SP8

XD_CD#
SD1

SDREG
XD_D7

3V3_IN

V18
4 NP1
VDD NP1
NP2
SD_CLK trace length shorter , 71.05170.003 NP2

24
23

6
surround with GND. SD_CMD_L

7
2
SD_CLK_L CMD
5 12

+3.3V_RUN_CARD
SD_CD#_L CLK 12
10 13
VDD18 1 2 SD_WP_L CD 13
11 14

SDRGE
WP 14
C3302 SC1U10V2KX--1GP 3D3V_S0 15
SD_DATA0 _L 7 15
C3301 2 DAT0
SD_DATA1 _L 8
3D3V_S0_CARD_VIN R3317 1 DAT1
1 2 0R0603-PAD SD_DATA2 _L 9 3
DAT2 VSS
SD_DATA3 _L 1 6
SC1U10V2KX--1GP CD/DAT3 VSS

SCD1U16V2KX-3GP
SC4D7U6D3V3KX--GP
El
C3305 C3306 CARDBUS11P-SKT--11--GP

2 1

2 1
020.I0004.0001

1ST = 020.I0004.0001
SD_CLK_L and CARD_CTRL0 trace length shorter , surround with GND.
2ND = 020.I0003.0001
20151013 move R3317,Delete C3303/C3304

et
3RD = 020.I0002.0001

C C

ro
SD_WP_L 1 R3323 2 0R0402-PAD SD_WP
SD_DATA1_L 1 R3324 2 0R0402-PAD SD_DATA1

SD_CMD_L R3302 1 2 0R0402-PADSD_CMD

SD_CLK_L R33011 2 0R0402-PADSD_CLK

-X
SD_DATA0_L 1 R3321 2 0R0402-PAD SD_DATA0
SD_CD#_L 1 R3322 2 0R0402-PAD SD_CD#

SD_DATA2_L 1 R3325 2 0R0402-PAD SD_DATA2

SD_DATA3_L 1 R3326 2 0R0402-PAD SD_DATA3

EC3313 EC3315 EC3314 EC3312 EC3311

Te
DY DY DY DY DY
21

21

21

21

21
SC15P50V2JN--L-GP

SC15P50V2JN--L-GP

SC15P50V2JN--L-GP

SC15P50V2JN--L-GP

SC15P50V2JN--L-GP

ch
B B

ni
ca
l
A A

<Core Desiiign>

Wistron Corporation
21F,,, 88,,, Sec.1,,, Hsiiin Taiii W u Rd., Hsiiichiih,,,

Eletro-XTechnical Eletro-XTechnical
Taipei Hsiiien 221, Taiwan, R...O...C...

Tiitttlle

Reserved
Siiize Document Number Rev
A2
LV115 SKL-U -1
Datte:: Monday,,, Aprrriill25,,, 2016 Sheet 33 off 102
5 4 3 2 1
 5 4 3 2 1

USB3.0 Port1 5V_USB1_S3 5V_USB1_S3

5V_S5
U3601
Support 2A AFTP3606
at least 80mil
Eletro-XTechnical
5V_USB1_S3
at least 80mil AFTP3610
5 1 1
R3613 IN OUT USB31
2

1
1 2 USB_PWR_EN_D1 GND
C3605 4 3 USB30_OC#0_D 1 R3615 2 USB_OC0# 16
C3630 24 USB_PWR_EN EN OC# AFTP3608
SCD1U16V2KX--L-GP

D C3612 C3625 1 10 1
VBUS CHASSIS#10
2 1

2 1
SC10U6D3V3MX--L-GP 0R0402-PAD 0R0402-PAD

SC10U10V5KX--L1-GP

SC1U10V2KX--L1-GP
DY DY 11

2 1

2 1
G524B1T11U--GP USB_PN0_TVS 2 CHASSIS#11 12
074.00524.0B9F TC3603 USB_PP0_TVS 3 D- CHASSIS#12 13
SE220U6D3VM--30-GP C3626 D+ CHASSIS#13

2 1

2 1
2ND = 74.06288.07F 77.52271.09L SCD1U16V2KX-L--GP
USB3_1_RX1_N_R 5
SSRX-
D 2ND = 77.92271.03L USB3_1_RX1_P_R 6
SSRX+
D
4
USB3_1_TX1_N_R PGND
DY 8
USB3_1_TX1_P_R 9 SSTX- 7
GND
SSTX+
USB3.0
AFTP3607 1
20151012 Modify TC3603 PN AFTP3609 1 SKT--USB13--206--GP
C3629
1 2 USB3_1_TX1_P_1 R3617 1 2 USB3_1_TX1_P_R
16 USB30_TX_CPU_P1 022.10005.00P1
SCD1U16V2KX--L-GP 0R0402-PAD

1ST =022.10005.00P1
2ND =022.10005.00Z1
3RD = 022.10005.01B1
EMI Request ED3602
5V_USB1_S3
ED3601 USB_PN0_TVS 1 6 USB_PN0_TVS

C3628 USB3_1_TX1_P_R 1 10 USB3_1_TX1_P_R

1 2 USB3_1_TX1_N_1 R3610 1 2 USB3_1_TX1_N_R 2 5
16 USB30_TX_CPU_N1
SCD1U16V2KX--L-GP 0R0402-PAD USB3_1_TX1_N_R 2 9 USB3_1_TX1_N_R

El
3 8

USB3_1_RX1_P_R 4 7 USB3_1_RX1_P_R
USB_PP0_TVS 3 4 USB_PP0_TVS
USB3_1_RX1_N_R 5 6 USB3_1_RX1_N_R

L12ESDL5V0C6-4C--GP
L05ESDL5V0NA--4-GP
075.01256.007C
075.00550.0071
2ND = 075.09904.0A7C
2ND = 75.01043.073

et
R3611 1 2 USB3_1_RX1_P_R EMI TEST
16 USB30_RX_CPU_P1
0R0402-PAD
EMI TEST

TR3603
3 4 USB_PP0_TVS
16 USB_CPU_PP0
C 2 1 USB_PN0_TVS C
16 USB_CPU_PN0

ro
FIILTER--4P--137-GP--U

68.01012.20B
1ST = 68.01012.20B
16 USB30_RX_CPU_N1 R3616 1 2 USB3_1_RX1_N_R 2ND = 68.00396.001
0R0402-PAD
EMI TEST

-X
USB2.0 Port2 5V_USB1_S3
5V_USB2_S3

Te
20151012 ADD Circuit to support USB3.0 R3620 1 2 0R0805-PAD AFTP3601
5V_USB2_S3

5V_S5 R3621 1 2 0R0805-PAD

Support 2A 5V_USB2_S3 USB32

1
at least 80mil U3602
at least 80mil 1
VBUS CHASSIS#10
10
5 1 11
R3607 IN OUT USB_PN1_TVS CHASSIS#11
2 AFTP3602 1 2 12
GND
1

1
C3604 1 2 USB_PW R_EN_D2 4 3 USB20_OC#1_D 1 R3609 2 1 USB_PP1_TVS 3 D- CHASSIS#12 13
24 USB_PWR_EN OC# USB_OC1# 16 AFTP3603

1
C3622 EN C3611 C3652 C3618 D+ CHASSIS#13
SCD1U16V2KX--L-GP

DY C3617 TC3602
SC10U6D3V3MX--L-GP 0R0402-PAD 0R0402-PAD

SC1U10V2KX--L1-GP

SC22U6D3V5MX--L3-GP
ST150U6D3VDM--28-GP SCD1U16V2KX-L--GP
2

2
21
G524B1T11U--GP

ch
SC22U6D3V5MX--L3-GP
DY DY 077.51571.0001 USB3_2_RX2_N_R 5

2
SSRX-
074.00524.0B9F USB3_2_RX2_P_R 6 AFTP3605 1
SSRX+ 4
PGND
2ND = 74.06288.07F USB3_2_TX2_N_R 8
USB3_2_TX2_P_R 9 SSTX- 7
DY SSTX+ GND
B USB3.0 B
SKT--USB13--206--GP

022.10005.00P1
USB_P2 BOM CTRL

ni
C3621
For USB2.0 Change to 022.10005.0S91 1ST = 022.10005.0S91
1 2 USB3_2_TX2_P_1 R3602 1 2 USB3_2_TX2_P_R
16 USB30_TX_CPU_P2
SCD1U16V2KX--L-GP 0R0402-PAD
2nd = 022.10005.03J1
3RD = 022.10005.03N1

EMI Request USB_P2 BOM CTRL

ca
ED3603 ED3604
5V_USB2_S3
USB3_2_TX2_P_R 1 10 USB3_2_TX2_P_R USB_PN1_TVS 1 6 USB_PN1_TVS

USB3_2_TX2_N_R 2 9 USB3_2_TX2_N_R
C3620 3 8 2 5
1 2 USB3_2_TX2_N_1 R3603 1 2 USB3_2_TX2_N_R
16 USB30_TX_CPU_N2
SCD1U16V2KX--L-GP 0R0402-PAD USB3_2_RX2_P_R 4 7 USB3_2_RX2_P_R

USB3_2_RX2_N_R
USB_P2 BOM CTRL 5 6 USB3_2_RX2_N_R

l
USB_PP1_TVS 3 4 USB_PP1_TVS

L05ESDL5V0NA--4-GP
075.00550.0071 L12ESDL5V0C6-4C--GP
2ND = 75.01043.073 075.01256.007C
USB_P2 BOM CTRL 2ND = 075.09904.0A7C
EMI TEST
R3604 1 2 USB3_2_RX2_P_R
16 USB30_RX_CPU_P2
0R0402-PAD

A A
TR3604
3 4 USB_PP1_TVS
16 USB_CPU_PP1

2 1 USB_PN1_TVS
16 USB_CPU_PN1
FIILTER--4P--137-GP--U <Corrre Desiiign>

R3605 1 2 USB3_2_RX2_N_R 68.01012.20B

16 USB30_RX_CPU_N2
0R0402-PAD Wistron Corporation
1ST = 68.01012.20B 21F,,, 88, Sec...1, HsiiinTai W u Rd...,,,Hsiiichih,

Eletro-XTechnical Eletro-XTechnical
Taiiipeiii Hsiiien 221,,, Taiiiwan,,, R.O.C...
2ND = 68.00396.001
Title
EMI TEST
USB30
Siiize Document Number Rev
A2
LV115 SKL-U -1
Date: Monday,,, Aprrriill25, 2016 Sheet 36 off 102
5 4 3 2 1
 5 4 3 2 1

Main Func = Power Plane & Sequence

Power Good 3D3V_S0

OSLO do not connect to 3D3V_S0

So reserved 20150724 R4005
1KR2J--1-GP
51 1D2V_VTT_PWRGD 1 R4011 2 0R0402-PAD

2 1
ROSA Run Power Eletro-XTechnical
D4002
53 RSMRST_PWRGD# RSMRST_PWRGD# 3 1 ALL_SYS_PWRGD 17,24
DY 2
R4002
LBAS16LT1G--GP 1 2 VR_EN 46,52
83.00016.P11
2ND = 83.00016.H11 0R0402-PAD
5V_S5

5V_S0
5V_S5 5V_S0 3D3V_S5
U4001 C4024

2 1
SCD1U16V2KX--3GP
SCD47U25V3KX--1GP
4 VBIAS 5V_S0 1 C4023
OUT1#13 13 AFTP4001
OUT1#14 14

1
D
CT1 12
3V5V_CT1 3D3V_S0 5V_S0 Comsumption D
C4005
1 IN1#1 Peak current 5A

SC10U25V5KX--L-GP
R4010 2 IN1#2 OUT2#8 8

3D3V_S0

2
17,24,51,52,54 SIO_SLP_S3# 1 2 3V5V_S0_ON 3 EN1 9 3D3V_S0 1
OUT2#9 3V5V_CT2 AFTP4002
0R0402-PAD CT2 10 U4007
3D3V_S5

C4002
SC470P50V2KX--3GP

C4001
SC470P50V2KX--3GP
6 IN2#6

1
7 IN2#7 GND 11 3D3V_S0 Comsumption 26,46 VR_RDY 1
A VCC
5
5 EN2 C4004 ALL_SYS_PWRGD 2
GND 15 Peak current 2.5A B

SC10U25V5KX--L-GP
3 4 PCH_PWROK 17

2
GND Y
G5016KD1U--GP
SN74AUP1G08DCKR--GP

074.05016.0093
2ND = 074.22966.0093 R4018
1 2
H_THERMTRIP# 4
0R2J--2-GP
DY

Q4002
MMBT2222A--3-GP DY DY

1
H_THERMTRIP_EN
84.02222.V11

ED4003

ED4004
17 H_THERMTRIP_EN B

PESD5V0U1BL--GP-U1

PESD5V0U1BL--GP-U1
DY

C E

El
R4007

2
C4003

1
17,24,31,61,68,76 PLT_RST# 1 2 SCD1U16V2KX--3GP
DY
4K7R2J--2-GP
VCCSTG

2
1

DY R4003
2K2R2J--2-GP

DY DY
DY 20151007 Delete Reserved Circuit
2
1

R4015 1 2 0R2J--2-GP
DY
Power Source Keep VCCIO (R710)
ED4001

ED4002

ED4005

ED4006

et
PESD5V0U1BL--GP-U1

PESD5V0U1BL--GP-U1

PESD5V0U1BL--GP-U1
PESD5V0U1BL--GP-U1
2

D4001 +VCCSTG(ICCMAX.=0.16A)
45,54 3V_EN 1 3 PURE_HW_SHUTDOWN# 24,26
2
VCCSTG should only ramp up equal to or after VCCST.
LBAS16LT1G--GP
C C
83.00016.P11
1

2ND = 83.00016.H11
DY R4006

ro
DY
GT3 Low Power Circuit (ZVM)
200KR2F--L-GP

-
2

L R4009
1 2 S5_ENABLE 24 20151209 Reserved Circuit 3D3V_S0 3D3V_S0
2KR2F--3-GP

1
1
R4030
2K2R2J--L1-GP R4031

-X
100KR2J--1-GP
23e
23e

2
Q4003 DY
D4003 ZVM#_G G 23e
24,45 5V_EN 1 3 R4029 D4004 DY

C
2 D ZVM#_EN_EDRAM A K ZVM#_EN_EDRAM_D R4019 1 2 ALL_SYS_PWRGD
ZVM# 1 2 ZVM#_B B Q4001 0R2J--2-GP
6 ZVM#
1

LBAS16LT1G--GP 2K2R2J--L1-GP METR3904-G--GP S RB551V30-GP

DY R4008 83.00016.P11 23e 23e Notice:ZZ.2N702.J3101

E
2ND = 83.00016.H11 2N7002K--2-GP 84.2N702.J31 83.R5003.H8H
200KR2F--L-GP

2ND = 84.2N702.031 2nd = 83.R5003.T8F

- 3rd = 84.2N702.W31
2

L
DY

Te
R4024 1 2 0R2J--2-GP DY R4025 1 2 0R0402-PAD EN_EDRAM_VR 52

Need to Check V1.8A

1D8V_S5 +V1.8A

PG4004 1 2 GAP-CLOSE-PWR--3--GP

PG4005 1 2 GAP--CLOSE--PWR--3--GP

ch
Discharge circuit

1
C4021 PG4006 1 2 GAP-CLOSE-PWR--3--GP C4020
C4017 SC1U10V2KX--1GP

SCD1U16V2KX--3GP
DY

2 1
SC22U6D3V5MX--L3-GP

2
B B
+VCCSTG
+V1.8S_EDRAM

Q4008 3D3V_S5
220R3F--1-GP 1 R4021 2 1D8V_DIS_Q 3 4
Q4009 3D3V_S5 DY

ni
220R3F--1-GP 1 R4028 2 1D0V_DIS_Q 3 4 2 5
17,24,51,52,54 SIO_SLP_S3#
DY
2 5 1 6 1D8V_DIS 2 R4020 1
17,24,51,52,54 SIO_SLP_S3#
1 6 1D0V_DIS 2 R4022 1 100KR2J--4-GP
2N7002KDW--GP
100KR2J--4-GP 84.2N702.A3F DY
2N7002KDW--GP 2nd = 075.063D1.007C
84.2N702.A3F DY
2nd = 075.063D1.007C

ca
DY
DY

V1.8S
MANAGEMENT RAIL POWER GENERATION VCCST, VCCSTG, and VCCPLL can remain powered during S4 and S5 power states for board VR optimization. +V1.8A
Q4006
+V1.8S_EDRAM

VCCST
DMP2130L-7-GP
5V_S5 1D0V_S5
1D0V_S5 +V1.00U_CPU
100mA
S

l
D

D
1

G
SC1U10V2KX--L1-GP

R4027 C4026 R4044 23e

23e

2 1

G
1

C4015 C4006 23e 10KR2J--3-GP

SCD1U16V2KX-3GP

1 DY 2 C4022 84.02130.031 C4027

2 1
0R6J--3-GP

SCD1U16V2KX--3GP
DY

SCD1U16V2KX-3GP
DY U R4041 SC1U10V2KX-1GP DY

2 1
1 2nd = 84.00102.031
2

2
1 2 1D8S_EN_R#
+V1.00U_CPU
23e 23e
20KR2J--L2-GP

1D8S_EN#
U4006 Q4007
17,24,51,52,54 SIO_SLP_S3# G 23e
1 IN#1 OUT#8 8
2 IN#2 D
R4023 OUT#7 7
3 VBIAS OUT#6 6
1 2 VCCSTU_EN_R 4 ON S
17,24,51 SIO_SLP_S4# GND 5 Notice:ZZ.2N702.J3101

0R2J--2-GP EC4001 2N7002K--2-GP

A
IN#9 9 1D0V_S5
84.2N702.J31
A
DY C4012
2 1

SC10U25V5KX-L--GP 2ND = 84.2N702.031

2 1
SCD1U16V2KX-3GP

AOZ1335DII--GP C4013 3rd = 84.2N702.W31

2 1

074.01335.0093 SC10U25V5KX--L-GP
2ND = 074.08939.0093

+VCCSTG +VCCST_CPU
VIL > 0.7 V, VIH < 2 V <Core Desiiign>
Rds(on) = 11 mΩ @ VDD = 4 V 0.04 A
Ids(max) 10 A
R4045
1 DY 2
Wistron Corporation

Eletro-XTechnical Eletro-XTechnical
21F,,, 88,,,Sec..1,, HsiiinTaii Wu Rd..,, Hsiichiih,,,
0R2J--2-GP Taipei Hsiiien 221, Taiwan, R...O...C...

+V1.00U_CPU Tiitle

R4036
Power Plane EN Sequence
1 2 Siiize Document Number Rev

0R0402-PAD
Custttom
LV115 SKL-U -1
Date: Monday,,, Apriiill25,2016 Sheet 40 offf 102
5 4 3 2 1
 5 4 3 2 1

BT+

F4301
1

FUSE--10A32V--1-GP
2
1ST BATTERY CONNECTOR
69.41002.101

1
EC4301

Eletro-XTechnical
PC4301 PC4302 SCD1U50V3KX--GP

2 1
SCD1U50V3KX--L-GP SC2K2P50V2KX--L-GP BAT1

2
9 11
1
RN4301 1ST = 020.F0266.0008
24 BAT_IN# 1 8 BAT_IN#_1 BT+_IN1 2
24,44 BAT_SCL 2 7 BATA_SCL_1 3 2ND = 020.F0661.0008
3 6 BATA_SDA_1 4
24,44 BAT_SDA
4 5 BAT_IN#_1 5
6
K

SRN33J--4-GP 7
PD4301 PL4301 PL4302 PL4303PC4304 PC4305 8

2
MMSZ5232BS--7-F-GP PC4303 10 12

VARISTOR-5D5V-29--GP

VARISTOR-5D5V-29--GP

VARISTOR-5D5V-29--GP
ALP--CON8-24-GP
DY

SC1KP50V2KX-L--1--GP

SC100P50V2JN-L-GP

SC100P50V2JN-L-GP
DY DY DY
A

2 1

2 1
2
D D
020.F0266.0008

1
AFTP4301 1 BAT_IN#_1
AFTP4302 1 BATA_SDA_1
AFTP4303 1 BATA_SCL_1

AFTP4305 1 BT+_IN1
AFTP4306 1
AFTP4309 1

AFTP4307 1
AFTP4308 1
AFTP4310 1

El
et
C C

ro
-X
Te
ch
B AD_ID
Adaptor in to generate DCBATOUT B

DY
AD_JK PD4302
08/01 EC4308 Change part number 78.10622.L5L to 78.10622.51L(1206 to 0805)

ni
AZ5013-01HDR7G--GP
83.05013.0AF
DC Jack
A K

TP4312 TP4313

AD+
AD_JK AD_JK_F
1

F4302 PU4301
SC10U25V5KX--GP

DCCN1 1 2 1S D 8
EC4308 2S D 7
DY D 6
7 FUSE--10A32V--1-GP 3S
2

G D 5

ca
AD+_2 4
5 69.41002.101
K

4 EC4307 PC4307 PR4301

2 1

SCD1U50V3KX--L-GP PD4303 PC4308 AO4407AL-GP

3
SCD1U50V3KX-L-GP

1
2 1

2 P6SMB27A--GP

200KR2F-L-GP

SCD22U25V3KX--GP
AFTP4311 1 1 83.P6SMB..JAG 84.04407.G37

2
A

6
PQ4301

2
R2
2
ACES-CON5-38-GP AD_OFF#_1 1
R1
AD_ID_R 3
020.F0498.0005
LTA024EUB--FS8-GP

1
1ST = 020.F0498.0005
PR4303 PR4302
2ND = 020.F0698.0005 84.00024.01K 100KR2J--1-GP

l
100KR2J--1-GP
2 1

R4304 06/25 Delete PR4303,PR4304,PR4305,PR4306 DY

2
AD_ID_R 1 2 AD_ID

0R0402-PAD

PQ4302
AD+_2 trace width > 8mil
PR4304 3 Length < 500mil
AD_ID 24 24,44 AD_OFF 1 2AD_OFF_RC 1 R1
0R0402-PAD 2
R2 08/06 add AD_OFF Circuit
PC4309 LTC024EUB--FS8-GP
2 1

SCD01U50V2KX--L-GP 84.00024.A1K
DY

Test point
AFTP4314 1 AD_JK
A AFTP4315 A
1
AFTP4316 1

AFTP4317 1

Eletro-XTechnical Eletro-XTechnical
<Core Desiiign>
AFTP4318 1 AD_ID

Wistron Corporation
21F,,, 88,,,Sec.1,,, Hsiiin Taiii W u Rd., Hsiiichiiih,,,
Taipei Hsiiien 221, Taiwan, R...O...C...

Title

DCIN & BATTCom

Siiize Document Number Rev
A1
LV115 SKL-U -1
Date: Monday,,, Apriiilll 25, 2016 Sheet 43 offf 102

5 4 3 2 1
 5 4 3 2 1

20151012 Modify PU4401 PN 84.08131.037 20151012 Modify PU4402 PN Eletro-XTechnical

SSID = Charger
AD+_TO_SYS DCBATOUT BT+
1ST = 84.08131.037 PU4402
PU4401 2ND = 84.07403.037 1 S D 8 84.08131.037
AD+ 8 D S 1 2 S D 7
7 D S 2 1 PR4402 2 3 S D 6 1ST = 84.08131.037

1
6 D S 3 D01R3721F--GP--U D 5
G
20151230 Power Team update Table 5 D
G
PR4403 AD+
TPCC8131-GP
2ND = 84.07403.037
D 100KR2J--1-GP D

4
TPCC8131-GP

4
1
A8( ANNIE/ASTRO)

1
PR4404 AD+_G_2
PR4007,PR4008

1
10KR2F--2-GP Id= -10A PG4402 PG4403 Id= -10A

1
PR4406
Qg= -22nC PR4405
GAP-CLOSE-PWR--3--GP GAP--CLOSE--PWR--3--GP Qg= -22nC
470KR2J--2-GP
Rdson=14~22mohm

2
AD+ total power R1 R2 Rdson=14~22mohm 49K9R2F--L-GP

DC_IN_D

2
51K
64.51025.6DL

2
45w 100K PQ4402
PC4402 2 1 SCD1U50V3KX--L-GP

AD+_G_1
120K 3 4
65w 64.12035.6DL 100K
AC_IN 2 5
DCBATOUT
100K 1 6

1
AD_JK_F PC4403 PC4404
2N7002KDW--GP
100K

2 1
SCD1U50V3KX--L-GP SCD1U50V3KX--L-GP

2
84.2N702.A3F

PWR_CHG_ACN
PWR_CHG_ACP
2ND = 075.063D1.007C PC4406 PC4407
BQ24737_VCC BQ24737_REGN PC4405

SC10U25V5KX--L-GP

SC10U25V5KX--L-GP
1 2

2 1

2 1
21
PR4407 CHG_AGND SCD1U25V2KX--L-GP
CHG_AGND

El
20R5F--1GP

5
6
7
8
PR4408 PC4408
PR4409

2 1
3D3V_AUX_KBC

D
D
D
D
SC1U50V5ZY--1-GP--U PC4409 PU4403

1 BQ24737_BTST_R
316KR3F--2-GP
1 2 K A 1 2 SC1U10V2KX--L1-GP SIIS412DN--T1-GE3-GP
CHG_AGND 1D5R2F--GP

1
PU4404 PD4401 84.00412.037
BQ24737_REGN RB520SM--30T2R--GP

ACP

ACN
2

PW R_CHG_IOUT 83.1R003.N8F

G
S
S
S
20 VCC 1ST = 84.00412.037

1
PR4401
STOP_CHG#

4
3
2
1
10KR2F--2-GP PR4410 PR4411
R1 2ND = 084.03319.0A37

et
12K4R2F--GP BQ24737_ACDET
connects to KBC 100KR2J--1-GP 6 ACDET BTST 17
BQ24737_BTST
Charger Current=1.4~3.6A
1
ADT BOM CTRL PC4410
1

PR4412 SCD1U50V3KX--L-GP

2
1 2
49K9R2F--L-GP PC4411 BQ24737_CMPOUT
24 STOP_CHG# REG 16
2 1

12
SCD01U50V2KX--L-GP

1
PR4414 3 CMPOUT
D

PQ4401 PR4413 BQ24737_HIDRV

120KR2F--L-GP HIDRV 18
C R2 100KR2F--L1-GP PR4415 PL4403 PR4416 BT+ C
Not ic e: ZZ .2N 70 2. J3 10 1

CHG_AGND 3D3MR2J--GP 4 CMPIN D01R3721F--GP--U

ro
BQ24737_PHASE 1 2 BT+_R 1 2
84.2N702.J31 PHASE 19

2
CHG_AGND BQ24737_CMPIN IIND-4D7UH-88--GP--U
2ND = 84.2N702.031 68.4R710.20D

GAP-CLOSE-PWR--3--GP

GAP-CLOSE-PWR--3--GP
BQ24737_LODRV
3rd = 84.2N702.W31 24,43 BAT_SCL 9 SCL LODRV 15

1
2N7002K--2-GP CHG_AGND PC4413 PC4414 PC4401

PG4401

PG4404
S

5
6
7
8
PC4415

SC10U25V5KX--L-GP

SC10U25V5KX--L-GP

SC10U25V5KX--L-GP
D
D
D
D
8 SDA PU4405 SCD1U50V3KX-L--GP
24,43 BAT_SDA

2
3D3V_AUX_S5

SIIS412DN--T1-GE3-GP
PR4417 PC4412

1
2 1
BQ24737_CMPOUT 10R2F--L-GP SC470P50V2KX--L-GP
BQ24737_SRP
SRP 13 1 2

-X
1

BQ24737_ILIM 10 ILIM
PR4418 BQ24737_SRN 1 2

G
S
S
S
SRN 12 PR4419
100KR2J--1-GP

4
3
2
1
CHG_AGND BQ24737_REGN_R 11 BM# 7D5R2F--GP 84.00412.037
2

1
PR4420
1ST = 84.00412.037
10KR2F--2-GP
PWR_CHG_IOUT
2ND = 084.03319.0A37
DY 5 ACOK# IOUT 7 1 2 AD_IA 24
PR4421 BQ24737_CSOP_1

GND

GND
2
0R0402-PAD

Te
BQ24737_REGN
1

21

14
PR4422 HPA02224RGRR--1-GP

1
33KR2F--GP
DY 74.02224.073
D

PQ4403 3D3V_AUX_KBC PC4416

1 2 SCD1U50V3KX-L--GP
Not ic e: ZZ .2N 70 2. J3 10 1
2

2
PR4424
1

0R0402-PAD PC4417 BQ24737_CSON_1

PR4423 SC100P50V2JN--L-GP

2 1
100KR2J--1-GP
CHG_AGND
3D3V_AUX_KBC 2N7002K--2-GP CHG_AGND
84.2N702.J31
S

2
G

ch
PC4418

2 1
2ND = 84.2N702.031 SCD1U25V2KX-L--GP
1 DY 2 BAT_SCL 3D3V_AUX_S5
CHG_ON# 24
PR4425 3K3R2J--3-GP 3rd = 84.2N702.W31
1

CHG_AGND CHG_AGND
B PR4427 B
1 DY 2 BAT_SDA 100KR2J--1-GP
PR4426 3K3R2J--3-GP
3D3V_AUX_S5 DY
2

ni
1

PR4428
100KR2J--1-GP AC_IN#
24 AC_IN#
2

AC_IN

ca
PQ4404 PQ4405
AC_IN# G G AD_OFF 24,43
D D

S S
Not ic e: ZZ .2N 70 2. J3 10 1 Not ic e: ZZ .2N 70 2. J3 10 1

2N7002K--2-GP 2N7002K--2-GP

84.2N702.J31 84.2N702.J31
2ND = 84.2N702.031 2ND = 84.2N702.031

l
3rd = 84.2N702.W31 3rd = 84.2N702.W31

A A

<Corrre Desiiign>

Wistron Corporation
21F,,, 88, Sec...1, HsiiinTai W u Rd...,,,Hsiiichih,

Eletro-XTechnical Eletro-XTechnical
Taiiipeiii Hsiiien 221,,, Taiiiwan,,, R.O.C...

Title

CHARGER
Siize Document Number Rev
A2
LV115 SKL-U -1
Date: Monday,,, Aprrriill25, 2016 Sheet 44 off 102
5 4 3 2 1
 A B C D E

08/20 add 5V_EN

PWR_5V_EN1 1 PR4501 2 DCBATOUT PWR_DCBATOUT_5V

Eletro-XTechnical
5V_EN 24,40
0R2J--2-GP PG4510

2
DY 1 2
EC4501 PR4507 GAP-CLOSE-PWR--6--GP

21
0R0402-PAD
SCD1U16V2KX--L-GP PG4511
1 2

1
GAP-CLOSE-PWR--6--GP
PWR_3D3V_EN2 1 PR4502 2
3V_EN 40,54 PG4512
0R0402-PAD 1 2

1
4 EC4502 GAP-CLOSE-PWR--6--GP 4
SC68P50V2JN--1GP
PG4513
DY

2
1 2
12/18 PR4501,PR4502 Change to Short PAD GAP-CLOSE-PWR--6--GP
08/06 Change to Close GAP
PG4514
1 2
DCBATOUT PWR_DCBATOUT_3D3V GAP-CLOSE-PWR--6--G1P2/11 上
Change Part number ZZ.CLOSE.001(上
)
PG4504 PG4524
1 2 1 2
GAP-CLOSE-PWR--6--GP GAP-CLOSE-PWR--6--GP

PG4505
1 2 PG4525
GAP-CLOSE-PWR--6--GP 1 2
GAP-CLOSE-PWR--6--GP
08/06 Change to Close GAP PG4515
1 2
GAP-CLOSE-PWR--6--GP
上
12/11 Change Part number ZZ.CLOSE.001(上
)

DCBATOUT

El
PWR_DCBATOUT_5V
PWR_DCBATOUT_3D3V

PC4508

SC10U25V5KX--GP
PC4507

5
6
7
8
PC4501 PC4502 EC4503 PC4512 PC4513 PC4514

SCD01U50V2KX--L-GP
DY

2 1
21

D
D
D
D
PU4504
SC4D7U25V5KX--L2-GP

SC4D7U25V5KX--L2-GP

SCD1U50V3KX--L-GP

SCD1U50V3KX--L-GP

SC10U25V5KX--L-GP

SC10U25V5KX--L-GP
D

et
2 1

2 1

2 1

2 1

2 1

2 1
EC4504 AON7410-GP

SCD1U50V3KX--L-GP
2 1
8
7
6
5
D
D
D
D
PU4502
AON7410-GP

12
PU4501 84.07410.A37

G
S
S
S
84.07410.A37

VIN

4
3
2
1
Design Current=3.1A 2nd = 84.01528.037 2nd = 84.01528.037
OCP <6.2A
S
S
S
G
3 3
PC4503 PR4503 PR4509 PC4509 Design Current=6.4A
1
2
3
4
S G

ro
1 PWR_5V_VBST1
2PWR_3D3V_VBS1T2_1 2PWR_3D3V_VBST2 9 BOOT2
SCD1U50V3KX--L-GP 1D5R3F--GP
BOOT1 17 1 2PWR_5V_VBST1_1 1
1D5R3F--GP
2
SCD1U50V3KX-L--GP
OCP < 12.8A
3D3V_S5 PL4502 5V_S5
PL4501 PWR_3D3V_DRVH2 PWR_5V_DRVH1
10 UGATE2 UGATE1 16
1 2 PWR_3D3V_LL2 PWR_5V_LL1 1 2
8 PHASE2 PHASE1 18 IND-2I D2UH-179--GP
COIIL-3D3UH--26-GP
D
1

PWR_3D3V_DRVL2 PWR_5V_DRVL1
68.3R310.20V 11 LGATE2 LGATE1 15

1
2nd = 68.3R31A.10V 68.2R21A.20B
8
7
6
5

PR4504 PR4511 PC4516 TC4503

D
D
D
D

PG4506 2D2R5F--2-GP PU4503 PWR_5V_VO1 2D2R5F--2-G2P nd = 68.2R21B.10J DY

BYP1 14

-X
1

5
6
7
8

2 1
21
SCD1U25V2KX--L-GP

SE220U6D3VM--30-GP
DY AON7410-GP DY
1

D
D
D
D
PC4504 TC4501 PWR_3D3V_FB2 PWR_5V_FB1 PG4509
GAP-CLOSE-PWR--3--GP

4 FB2 PU4505
FB1 2

1PWR_5V_SNU2B
1PWR_3D3V_SNUB 2

DY AON7410-GP
21
SCD1U25V2KX--L-GP

SE220U6D3VM--30-GP

GAP-CLOSE-PWR--3--GP
G
2

S
S
S
G

21
PWR_3D3V_EN2 6 20 PWR_5V_EN1
1
2
3
4

S EN2 EN1

G
S
S
S
77.52271.09L

4
3
2
1
PWR_3D3V_CS2 5 1 PWR_5V_CS1 PC4515
CS2 CS1 SC560P50V--GP
84.07410.A37
3V_FEEDBACK

1
77.52271.09L PC4505 2ND = 77.92271.03L
DY

Te

2
SC330P50V3KX--GP PR4505 PR4510 2nd = 84.01528.037
105KR2F--1-GP VCLK 19 210KR2F--GP
DY 84.07410.A37
2

2ND = 77.92271.03L 20151012 Modify TC4503 PN

2nd = 84.01528.037 7 PGOOD GND 21
2

2
LDO3

LDO5
20151012 Modify TC4501 PN 074.06575.0A43
1

PR4516 PR4506 RT6575DGQW--GP

3
6K65R2F--GP 0R2J--2-GP 5V_AUX_S5

1
3D3V_AUX_S5 PR4512
DY

1 PWR_5V3D3V_VREG5 13
PG4507 PG4508 R402--PAD-H16--GP

1 PWR_5V3D3V_VREG3
2

1
ch
3D3V_S5
1 2 1 2 ZZ.00RES.021 PR4514
AFTP4501 1 PWR_3D3V_FB2_R
AFTP4502 1 5V_S5 PC4506 GAP-CLOSE-PWR--3--GP GAP-CLOSE-PWR--3--GP
ASM_RES_PAD_DY 15KR2F--GP

1 2
PWR_5V_FB1_R
21 2

SC18P50V2JN--1-GP
PC4517
DY

2
SC18P50V2JN--1-GP
2 2
DY

2
3D3V_S5
1

PR4517

1
10KR2F--2-GP PC4510 PC4511
1

SC10U25V5KX--L-GP SC10U25V5KX-L--GP PR4515

PR4508 10KR2F--2-GP

ni
2

100KR2J--1-GP
DY Close to VFB Pin (pin2)

2
2

17,54 3V_5V_POK 3V_5V_POK

Close to VFB Pin (pin5)

ca
l
1 1

<Corrre Desiiign>

Wistron Corporation
21F,,, 88, Sec...1, HsiiinTai W u Rd...,,,Hsiiichih,

Eletro-XTechnical Eletro-XTechnical
Taiiipeiii Hsiiien 221,,, Taiiiwan,,, R.O.C...

Title

SYN256_5V/3D3V
Siize Document Number Rev
A2
LV115 SKL-U -1
Date: Monday,,, Aprrriill25, 2016 Sheet 45 off 102
A B C D E
 5 4 3 2 1

Main Func = CPU_CORE

PR4611 23e change to 64.27425.6DL

Eletro-XTechnical
1 2 33K2R2F--GP

PC4632
1 2

SC1KP50V2KX--L-1-GP
PR4602
D PC4602 81208_AGND D
1 2 PWR_VCCSA_COMP_R 1 2 PWR_VCCSA_CSN 50

2
SCD015U25V2KX--GP
1K5R2F--2-GP
PC4606 PR4606
SCD015U25V2KX--GP NTC-100K-1-GP-U
PC4603 SC1KP50V2KX- PC4604 1 2 SC15P50V2JN--L-GP

21
-L-1-GP PC4607
69.60028.011

2 1
SC3300P50V2KX-1GP 14K3R2F--GP

1
PWR_VCCSA_VSN_R 1 2 23e:DY PR4609 1 2 PWR_VCCSA_CSN_NTC
81208_AGND
PR4605
7 VSSSA_SENSE PR4604 1 2 0R0402-PAD 1 2 PR4612 1 2 8K06R3F--AS-GP PWR_VCCSA_CSP 50
3D3V_S0
PR4613
825R2F--GP
1 2 102KR2F--GP

1
PC4605

12
PR4614
SC1KP50V2KX-L--1--GP 23e change to 64.84525.6DL
PC4609 1 2 SC220P50V2KX--3GP 10KR2F--2-GP
7 VCCSA_SENSE PR4607 1 2 0R0402-PAD PR4608 1 2 2K61R2F--1-GP

2
PC4608 81208_AGND PR4670 1 2 0R0402-PAD VR_RDY
PWR_VCCSA_VSP_R 1 2 1 2 VR_RDY 26,40
SC1KP50V2KX--L-1-GP

El
PR4616 PR4630 1 2 0R0402-PAD
VR_EN 40,52
0R0402-PAD
+VCCST_CPU
PWR_VCCSA_VSP_RC PSYS

PR4615 2 1 20KR2F--L-GP

100R2F--L1-GP--U
PR4623
GP
75R2F--2-
PR4622
PC4610

et

2 1
81208_AGND SCD1U25V2KX--L--GP +VCCST_CPU +VCCSTG Check +VCCST_CPU or +VCCSTG
7 VCCGT_SENSE PR4617 1 2 0R0402-PAD

1
45D3R2F--L--GP
PR4621
DY

1
[#543016]
PC4611 SC1KP50V2KX-
-L-1-GP

1
C PR4619 C
7 VSSGT_SENSE PR4618 1 2 0R0402-PAD 2 1 1KR2F--3-GP PR4624 PR4669

ro
VR_SVID_CLK 7 DY 1KR2F--3-GP DY 75R2F--2-GP
PWR_VCCGT_VSN_R 1 2 VR_SVID_ALERT# 7

2
PC4612 SC2K2P50V2KX--L-GP
PG4601 VR_SVID_DATA 7
GAP-CLOSE-PWR--3--GP

50
PR4668

47,48,50
2 1

PWR_VCCSA_PWM

PWR_VCORE_DRVON
1

PR4665

PR4666

PR4667
1 2 H_PROCHOT# 4,24
PR4625 100R2F--L1-GP--U
37D4R2F--GP

-X
81208_AGND

PWR_VCORE_VR_RDY
1

PR4626

PWR_VCCSA_CSP1B
P PWR_VCCSA_ILIM
2

PWR_VCCSA_COM

PWR_VCCSA_IOUT
PC4613 1 2 SC470P50V2KX--L-GP

PWR_VCCGT_VSP

49D9R2F--GP

0R0402-PAD

10R2F--L-GP
PWR_VCCGT_VSN

PWR_VCCSA_VSN
PWR_VCCSA_VSP
1KR2F--3--GP

PWR_VCORE_EN

1
PWR_VCCGT_FB_R PR4627
PR4628 1 2 110KR2F--GP 1 2 PWR_VCORE_CSP 47
1

8K06R3F--AS--GP
PR4632
2

PC4614 23e change tto64.10035.6DL

SC470P50V2KX-L--GP 1 2 26K1R2F--2-GP 81208_AGND
PR4629

2
2

81208_AGND
1 2 PWR_VCORE_CSNNTC
1

Te
PWR_VCORE_VRHOT#
PWR_VCORE_ALERT#

2
PR4631 14KR2F--GP

48
47
46
45
44
43
42
41
40
39
38
37
49

PWR_VCORE_SCLK

PWR_VCORE_SDIO
PC4617 4K75R2F--1-GP 1 2 PU4601
SC10P50V2JN--L1-GP PR4633

VSN_2PH

VR_RDY
EN
VSP_2PH
PSYS
VSP_1B
VSN_1B
COMP_1B
ILIM_1B
CSN_1B
CSP_1B
IOUT_1B
GND
PC4615 PC4634 PC4616 NTC-100K-1-GP-U
PWR_VCCGT_ILIM_R

21

21

21
SC470P50V2KX--L-GP SCD022U25V2KX--GP SCD01U50V2KX--L-GP 69.60028.011
PWR_VCCGT_COMP_R
PR4634 81208_AGND PWR_VCORE_CSN 47

1
PC4618 PWR_VCCGT_IOUT
21 2

1 2 1
SC2K2P50V2KX-L--GP IOUT_2PH PW M_1B 36
PWR_VCCGT_DIFFOUT 2 1 PR4635 2 59KR2F--GP
PR4638 NTC--220K--5-GP--U DIFFOUT_2PH DRVON 35
PWR_VCCGT_FB 3
PR4637 165KR2F--GP FB_2PH SCLK 34
PW R_VCCGT_COMP 4 COMP_2PH ALERT# 33
1 2 2 1 1 PR4639 2 PR4640 1 2 PWR_VCCGT_ILIM 5
48 PWR_VCCGT_CSPA ILIM_2PH SDIO 32

ch
12K4R2F--GP PWR_VCCGT_CSCOMP 6 074.81208.0D73 VR_HOT# 31
CSCOMP_2PH PR4636
47K5R3F--GP PC4621 23e change to 64.16225.6DL PWR_VCCGT_CSSUM PWR_VCORE_IOUT PC4633 81208_AGND
75KR2F--GP 7 CSSUM_2PH IOUT_1A 30
23e change to 64.73225.55L PC4620 SC100P50V2JN--L-GP PW R_VCCGT_CSREF PWR_VCORE_CSP_1A 1 2 PC4601 1 2 PWR_VCORE_COMP_R
8 CSREF_2PH CSP_1A 29 1 2
2 1

2 1

SC1KP50V2KX-L--1--GP 9 SC1KP50V2KX--L-1-GP SC1500P50V2KX--2GP

CSP2_2PH CSN_1A 28 PWR_VCORE_ILIM 2K49R2F--GP
48 PWR_VCCGT_CSPB 1 PR4641 2 23e 10 CSP1_2PH ILIM_1A 27
11 26 PWR_VCORE_COMP PC4619 1 2 SC15P50V2JN--L-GP
TSENSE_2PH COMP_1A

ROSC_COREGT
B 73K2R3F--1-GP PWR_VCORE_VSN 81208_AGND B
VSN_1A 25 2 1PWR_VCORE_VSN_R

ADDR_VBOOT
12

TSENSE_1PH
ICCMAX_2PH
VRMP

ROSC_SAUS
PR4643 2 1 10R2F--L-GP PC4622 SC1KP50V2KX--L-1-GP

ICCMAX_1A
ICCMAX_1B
PW M1_2PH
PW M2_2PH
48 PWR_VCCGT_CSNB
23e 5V_S5
PWR_VCORE_VRMP

PW M_1A

VSP_1A
1 2 PR4645 2 1 0R0402-PAD VSS_SENSE 7
1

PR4644
VCC

PR4646 2 1 10R2F--L-GP PC4623 PC4624 PR4671 422R2F--2-GP

48 PWR_VCCGT_CSNA

ni
SCD033U25V2KX--GP SCD033U25V2KX-GP 1KR2F--3-GP PC4625 SC1KP50V2KX-
2 1

2 1

2 1
NCP81208MNTXG--4-GP PR4647 -L-1-GP
2
23e 23e:DY
13
14
15
16
17
18
19
20
21
22
23
24
1 2 3K83R2F--GP PR4648 2 1 0R0402-PAD VCC_SENSE 7
2

PWR_VCCGT_CSP2
PWR_VCORE_VCC_R

PC4626 2 3 e : change to 64 .34815 .6 DL

PWR_VCORE_ROSC_SAUS

SCD01U50V2KX--L-GP PWR_VCCGT_CSP1 PWR_VCORE_VSP PR4649 1 2 PWR_VCORE_VS P _ R C 1 2 P WR _ V C O RE _V S P_R

PWR_VCORE_ROSC_COREGT
2 1

PWR_VCCGT_TSENSE 3K83R2F--GP PC4627 SC1KP50V2KX--L-1-GP

PR4650
PWR_VCORE_TSENSE PW R_VCORE_NTC

ca
DCBATOUT 2 1
PR4651 81208_AGND 0R0402-PAD
PWR_VCORE_PWM 47
1 2 PR4601 PWR_VCORE_ADDR_BOOT
48 PWR_VCCGT_CSPA

2
1 2 1KR2F--3-GP PWR_VCCSA_ICCMAX

1
4K87R2F--GP PWR_VCORE_ICCMAX PR4652
PR4654 1 2 PWR_VCCGT_ICCMAX PC4628 12K7R2F--GP PR4653
48 PWR_VCCGT_CSPB SCD1U25V2KX-L--GP
6K98R2F--GP NTC-100K-1-GP-U

2
PC4629 69.60028.011

2
2 1

SCD01U50V2KX--L-GP

1
PR4662 PR4658 PR4660 PR4663

1
PW R_VCCGT_NTC 1 2

48D7KR2F--GP

90K9R2F--GP

10KR2F--2-GP
PR4655

15K8R2F--GP

l
0R0402-PAD 81208_AGND 81208_AGND
2

5V_S5
2

2
1

1
1

PR4656 PR4657
NTC--100K--1-GP--U PR4661 PC4630 2D2R2F--GP PR4664 PR4659
12K7R2F--GP SCD1U25V2KX-L--GP 24KR2F--GP 24KR2F--GP
1 2 23e:change to 64.19125.6DL
2

69.60028.011 23e:change to 64.10035.6DL

2

2
1
1

PC4631
SC1U10V2KX--L1-GP 81208_AGND
2

81208_AGND PWR_VCCGT_PWMB 48
81208_AGND 81208_AGND 81208_AGND
PWR_VCCGT_PWMA 48
A A

<Core Desiiign>

Wistron Corporation
21F,,, 88, Sec...1, HsiiinTai W u Rd...,,,Hsiiichih,
Taipei Hsiiien 221, Taiwan, R...O...C...

Eletro-XTechnical Eletro-XTechnical
Tiitle

CPU_VCORE(1/3)
Siize Document Number Rev
A2
LV115 SKL-U -1
Datte::: Monday,,, Aprrriill25,,, 2016 Sheet 46 off 102
5 4 3 2 1
 5 4 3 2 1

Main Func = CPU_CORE

Eletro-XTechnical
DCBATOUT

1
D PC4701 PC4702 PC4703 PC4704 PC4705 D

SC10U25V5KX-L-GP

SC10U25V5KX-L-GP

SC10U25V5KX-L-GP

SC10U25V5KX-L-GP

SC10U25V5KX-L-GP
PC4710
SCD1U25V2KX-L-GP

2
2

2
PR4701
1 2 PWR_VCORE_BOOT_RC

PWR_VCORE_BOOT
3D9R3-GP

El

1
5V_S5 PC4706
SCD22U25V3KX-GP
PR4702

2
2D2R2F-GP

33
25
26
27
28
29
30

35
et 1
2 1 PWR_VCORE_VCC PU4701

THWN

GH

BOOT
1

VI

VI

VI

VI

VI

VI
N

N
PC4708 VCC_CORE
SC1U10V2KX-L1-GP 6 VCC
C 2 PW R_VCORE_PHASED 1ST = 68.R1510.20A C
PHASED 34 PL4701

ro
7 VCCD PHASEF 32
1

PW R_VCORE_SW
2ND = 68.R1510.201
PC4707 1 2
SC2D2U10V3KX-L-GP VSW#12 12
5 CGND VSW#13 13
2

VSW#14 14 COIL-D15UH-2-GP
074.81382.0CE3 VSW#15 15
4 PWM VSW#16 16 68.R1510.20A

-X
46 PWR_VCORE_PWM PR4704
VSW#17 17
1 2 PWR_VCORE_DISB# 2 DISB# VSW#18 18

1
2

2
46,48,50 PWR_VCORE_DRVON PT4701
0R0402-PAD 36 ZCD_EN

1
PG4707 PG4708

ST220U2VDM-5-GP
2
GAP-CLOSE-PWR-3-GP

GAP-CLOSE-PWR-3-GP
5V_S5 3 SMOD# 2D2R5F-2-GP

1
PR4703 D
Y
GL#10
GL#11

Te
GL#8
GL#9

PGN

PGN

PGN

PGN

PGN

PGN

PGN

PGN

2
D

D
NCP81382MNTXG-3-GP PW R_VCORE_SNUB
8
9
10
11

19
20
21
22
23
24
31
37

1
PC4709
PW R_VCORE_GL SC2200P50V2KX-2GP
79.22719.2BL
DY
Y

2
ch
1ST = 074.81382.0CE3 Confirm with EE:
2ND = 074.81381.0A73 for Pentium 22uF/0805 total 32pcs (DY 5 pcs)
B B
46 PWR_VCORE_CSP

ni
46 PWR_VCORE_CSN

ca
l
A <Core Desiiign> A

Wistron Corporation
21F, 88, Sec.1, Hsiiin Taiii Wu Rd., Hsiiichiiih,
TaiiipeiiiHsiiien 221, Taiiiwan, R.O.C.

Eletro-XTechnical Eletro-XTechnical
Title

CPU_VCORE(2/3)
Siize DocumentNumber Rev
A3
LV115 SKL-U -1
Date: Monday, Apriiilll25,2016 Sheet 47 of 102
5 4 3 2 1
 5 4 3 2 1

Main Func = CPU_CORE

DCBATOUT
Eletro-XTechnical

1
PC4820 PC4827 PC4828 PC4829 PC4830
PC4811

SC10U25V5KX--L-GP

SC10U25V5KX--L-GP

SC10U25V5KX--L-GP

SC10U25V5KX--L-GP

SC10U25V5KX--L-GP
D D

21

21
SCD1U25V2KX--L-GP

2
PR4802
1 2

PWR_VCCGT_BOOTA
3D9R3-GP
PWR_VCCGT_BOOTA_RC

5V_S5

PC4809
SCD22U25V3KX--GP

2 1
PR4803
2D2R2F--GP

25
26
27
28
29
30
33

35
1
2 1 PWR_VCCGT_VCCA PU4801

El GH
VIN
VIN
VIN
VIN
VIN
VIN

BOOT
THWN
PC4808
2 1

SC1U10V2KX--L1-GP +VCCGT
6 VCC PWR_VCCGT_PHASEDA
PHASED 34 PL4801 1ST = 68.R1510.20A
7 VCCD PHASEF 32
PC4807 2ND = 68.R1510.201
SC2D2U10V3KX--L-GP VSW #12 12
PWR_VCCGT_SWA 1 2 Confirm with EE:
2 1

COIIL--D15UH-2--GP
5 CGND VSW #13 13 22uF/0805 total 35pcs (DY 5 pcs)
VSW #14 14
68.R1510.20A

et
074.81382.0CE3 VSW #15 15
4 PW M VSW #16 16
46 PWR_VCCGT_PWMA PR4808
VSW #17 17
1 2 PWR_VCCGT_DISB#_A 2
46,47,50 PWR_VCORE_DRVON DISB# VSW #18 18
0R0402-PAD 36 ZCD_EN

1
5V_S5 PG4808 PG4809

12

12
GAP-CLOSE-PWR--3--GP

GAP-CLOSE-PWR--3--GP
C 3 SMOD# C
2D2R5F--2-GP
PR4804 D
Y
GL#10
GL#11

ro
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
GL#8
GL#9

2
NCP81382MNTXG--3-GP
8
9
10
11

19
20
21
22
23
24
31
37
PWR_VCCGT_SNUB_1

1
PWR_VCCGT_GL1
PC4810
SC2200P50V2KX--2GP
DY
Y

-X
2
1ST = 074.81382.0CE3
2ND = 074.81381.0A73 for Pentium
46 PWR_VCCGT_CSPA

Te
46 PWR_VCCGT_CSNA

DCBATOUT

ch
1

PC4802 PC4803 PC4804 PC4805 PC4806

PC4812
SC10U25V5KX--L-GP

SC10U25V5KX--L-GP

SC10U25V5KX--L-GP

SC10U25V5KX--L-GP

SC10U25V5KX--L-GP
2 1

2 1

2 1

2 1
SCD1U25V2KX--L-GP
23e 23e 23e 23e 23e 23e
2

B B

PR4805

ni
1 2
PWR_VCCGT_BOOTB

3D9R3-GP
PWR_VCCGT_BOOTB_RC

23e
5V_S5

ca
PC4845
23e SCD22U25V3KX--GP
2 1

PR4806
2D2R2F--GP
25
26
27
28
29
30
33

35

23e
1

2 1 PWR_VCCGT_VCCB PU4802
GH
VIN
VIN
VIN
VIN
VIN
VIN

BOOT
THWN

23e
PC4847
2 1

SC1U10V2KX--L1-GP 6 VCC
PWR_VCCGT_PHASEDB +VCCGT
PHASED 34 PL4802 1ST = 68.R1510.20A
7 VCCD PHASEF 32

l
1

PC4846 23e 2ND = 68.R1510.201

SC2D2U10V3KX--L-GP PWR_VCCGT_SWB 1 2
VSW #12 12 COIIL--D15UH-2--GP
5 CGND VSW #13 13
2

VSW #14 14
68.R1510.20A
074.81382.0CE3 VSW #15 15
46 PWR_VCCGT_PWMB
4 PW M VSW #16 16 23e
PR4809

1 PT4801

1 PT4803
VSW #17 17
1 2 PWR_VCCGT_DISB#_B 2 23e
DISB# VSW #18 18
2

46,47,50 PWR_VCORE_DRVON
0R0402-PAD 36 ZCD_EN
1

PG4815 PG4816
PR4807
5V_S5
GAP-CLOSE-PWR--3--GP

GAP-CLOSE-PWR--3--GP

3 SMOD# DY
1

2D2R5F--2-GP
DY
2
GL#10
GL#11

PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
GL#8
GL#9

SE330U2VDM--L-GP 2
SE330U2VDM--L-GP
2

A A
NCP81382MNTXG--3-GP
8
9
10
11

19
20
21
22
23
24
31
37

PWR_VCCGT_SNUB_2

PWR_VCCGT_GL2
PC4814 <Corrre Desiiign>
2 1

SC2200P50V2KX--2GP
DY
Y
Wistron Corporation
1ST = 074.81382.0CE3 21F,,, 88, Sec...1, HsiiinTai W u Rd...,,,Hsiiichih,

Eletro-XTechnical Eletro-XTechnical
Taiiipeiii Hsiiien 221,,, Taiiiwan,,, R.O.C...
2ND = 074.81381.0A73 for Pentium 79.33719.L01 79.33719.L01
46 PWR_VCCGT_CSPB Title
1ST = 79.33719.L01 1ST = 79.33719.L01
CPU_VCCGT3/3)
2ND = 79.33719.20C 2ND = 79.33719.20C Siize Document Number Rev
46 PWR_VCCGT_CSNB A2
LV115 SKL-U -1
Date: Monday,,, Aprrriill25, 2016 Sheet 48 off 102
5 4 3 2 1
 5 4 3 2 1

Main Func = CPU_CORE

Eletro-XTechnical

D D

DCBATOUT

El

1
PC5029

SC10U25V5KX-L-GP
PC5002

5
6
7
8
PR5013 SCD1U25V2KX-L-GP

2
D
D
D
D
1 2 PWR_VCCSA_BST_RC PU5002
SIS412DN-T1-GE3-GP #544669 Intel CRB Rev0.53
2D2R3-1-U-GP +VCCSA(ICCMAX.=6A)

et
PWR_VCCSA_BST

1
PC5008

G
S
S
S
SCD22U25V3KX-GP 84.00412.037

4
3
2
1
2
C PU5001
1ST = 84.00412.037 +VCCSA C
1ST = 68.R4710.10M

ro
2ND = 084.03319.0A37 PL5001
1 BST PW R_VCCSA_DRVH 2ND = 68.R4710.20K
DRVH 8 PWR_VCCSA_SW
2 PWM SW 7 1 2
46 PWR_VCCSA_PWM 3 EN
46,47,48 PWR_VCORE_DRVON GND 6 IND-D47UH-22-GP-U
5V_S5 4 VCC DRVL 5
68.R4710.10M

1
GND 9

-X
1

PC5001 PR5014
SC2D2U10V3KX-L-GP 2D2R5F-2-GP
DY

5
6
7
8

1
NCP81253MNTBG-1-GP
2

D
D
D
D
PU5003

SC47U6D3V5MX-1-GP
074.81253.0AE3 PC5003

2
SIS412DN-T1-GE3-GP PG5021 PG5022

PWR_VCCSA_SNUB

2
GAP-CLOSE-PWR-3-GP

GAP-CLOSE-PWR-3-GP
DY

1
PW R_VCCSA_DRVL

Te
G
S
S
S
4
3
2
1

1
84.00412.037
1ST = 84.00412.037
DY PC5031
SC2200P50V2KX-2GP

2
ch
2ND = 084.03319.0A37

B B

Confirm with EE:

ni
46 PWR_VCCSA_CSP 22uF/0805 total 20pcs (DY 5 pcs)

ca
46 PWR_VCCSA_CSN

l
A <Core Desiiign> A

Wistron Corporation
21F, 88, Sec.1, Hsiiin Taiii Wu Rd., Hsiiichiiih,
TaiiipeiiiHsiiien 221, Taiiiwan, R.O.C.

Eletro-XTechnical Eletro-XTechnical
Tiiitllle

CPU_VCCSA
Siize DocumentNumber Rev
A3
LV115 SKL-U -1
Date: Monday, Aprilll 25, 2016 Sheet 50 of 102
5 4 3 2 1
 5 4 3 2 1

Main Func = VDDQ

DCBATOUT PWR_DCBATOUT_VDDQ

PG5117
1 2
GAP--CLOSE--PWR--6--GP

PG5118
1 2
GAP--CLOSE--PWR--6--GP

Eletro-XTechnical
PG5137

VID 1 2
GAP--CLOSE--PWR--6--GP 1D2V_PW R 1D2V_S3
Logic-High = 0.75V
Logic-Low = 0.3V
PG5138
1 2
PR5107 GAP--CLOSE--PWR--6--GP
5D1R2F-GP
PWR_VDDQ_VID 2 1 5V_S5 PG5139
1 2
PC5102 GAP--CLOSE--PWR--6--GP
SC1U10V2KX--L1-GP

2 1
PWR_DCBATOUT_VDDQ PG5140
RF RESERVED 1 2
GAP--CLOSE--PWR--6--GP

D
OCP setting PG5141 D

1 2
PR5109 PC5103 PC5104 PC5105 FC5101 FC5102 GAP--CLOSE--PWR--6--GP
PWR_VDDQ_CS PWR_VDDQ_VDD

SC4D7U25V5KX--L2-GP

SC4D7U25V5KX--L2-GP

SCD1U25V2KX--L-GP
1 2 5V_S5

2 1

2 1

2 1

2 1

2 1
SCD1U25V2KX--L-GP

SCD1U25V2KX--L-GP
PG5142
0R0402-PAD 1 2
PR5114 PC5107 GAP--CLOSE--PWR--6--GP
287KR2F-GP SC1U10V2KX--L1-GP

2 1
PG5143

2 1

5
6
7
8
12

D
D
D
D
PU5108 GAP--CLOSE--PWR--6--GP
AON7410-GP
3D3V_S5 84.07410.A37 PG5144
PU5101 1 2
RT8231AGQW--GP GAP--CLOSE--PWR--6--GP
1ST = 84.07410.A37
PR5111 074.08231.0073 PR5112 PC5108
Design Current : 15.6A

G
S
S
S
CS 13
10KR2F-L1-GP 2D2R3F-L-GP SCD1U50V3KX--L-GP 2ND = 84.01528.037 PG5145
OCP : 21.84A

VID

VDD

4
3
2
1
PWR_DCBATOUT_VDDQ

11
DY

12
1 2
PWR_VDDQ_BOOT 2 PWR_VDDQ_BOOT_A 1 2 GAP--CLOSE--PWR--6--GP
BOOT 18 1

2 1
PR5113 1D2V_VTT_PW RGD 10
40 1D2V_VTT_PWRGD PGOOD
Freq. setting 750KR2F-L-GP PG5146
1 2 PWR_VDDQ_TON PWR_VDDQ_HG
9 TON UGATE 17 1 2
750K -> 350K Hz GAP--CLOSE--PWR--6--GP
PWR_VDDQ_EN 8 S5 PL5101 1D2V_PWR
P-
IIND-1UH-94-GP-U PG5147
PWR_VTT_EN PWR_VDDQ_PH
7 S3 PHASE 16 1 2 1 2
PG5115 68.1R01B..10K GAP--CLOSE--PWR--6--GP
PWR_VDDQ_VLDOIN 19 2nd = 68.1R010.20I
1D2V_PWR 1 2 VLDOIN
GAP-CLOSE-PW R-3-GP PC5109 PWR_VDDQ_LG
RF RESERVED PG5148
LGATE 15 12

7
8
5
6
PG5116 2 1 SC10U6D3V3MX--L-GP Close to output cap pin1, not GAP--CLOSE--PWR--6--GP
PC5110 PC5111 PC5112 PC5113 PC5114 FC5104 FC5103

D
D
D
D
1 2 PU5104
inside of the output cap AON7506-- GP DY DY

SC22U6D3V5MX--L3-GP

SC22U6D3V5MX--L3-GP

SC22U6D3V5MX--L3-GP

SC22U6D3V5MX--L3-GP
PG5149

2 1

2 1

2 1

2 1

2 1

2 1

2 1
SCD1U25V2KX--L-GP

SCD1U25V2KX--L-GP
GAP-CLOSE-PW R-3-GP

El
1 VTTGND PGND 14 84.07506.037 1 2
GAP--CLOSE--PWR--6--GP
PWR_VDDQ_VTT PG5101 4 1ST = 84.07506.037

SC22U6D3V5MX--L3-GP
G
PWR_VDDQ_VDDQ PG5150
VD D Q 5 2

S
S
S
1 1D2V_PWR
PWR_2D5V_PG 1 PR5108 2 0R0402-PAD PWR_VDDQ_EN 2ND = 84.01525.037 1 2

2
1
3
PWR_VDDQ_FB GAP--CLOSE--PWR--3--GP GAP--CLOSE--PWR--6--GP
20 VTT FB 6
PC5106 2 VTTSNS PG5151
2 1

SCD1U16V2KX--L-GP
12
S5
DY DY GAP--CLOSE--PWR--6--GP

4 VTTREF
PR5116

R1
15K4R2F-GP PC5115 PG5152

GND
GND
SC18P50V2JN--1-GP 1 2

3
21

2 1

2 1
GAP--CLOSE--PWR--6--GP

et
PG5153
1 2
1 PR5119 2 0R0402-PAD PWR_VTT_EN GAP--CLOSE--PWR--6--GP
5 DDR_PG_OUT

2 0R2J--L-GP
R2
PR5120 1
2 1 PWR_VDDQ_VTTREF
17,24,40,52,54 SIO_SLP_S3#
S3

1
PR5117
DY 20KR2F-L3-GP

Vout Setting
C C

ro
Vout = Vref * ( 1 + R1/R2 )

2
PC5116
SCD033U25V2KX--GP
= 0.675 * ( 1 + 15.8K / 20K)
= 1.2V

VID vs Vref Table

VID Logic-High => Vref = 0.675 V
VID Logic-Low => Vref = 0.75 V
2D5V_LDO 3D3V_S5
PD = (Vin Vout ) x Iout
= ( 3.3 - 2.5 ) x 0.3A = 0.24W
note. Vref can only be changed form PWR_2D5V_LDO 2D5V_S3
Vout = 0.6V
PD de-rating(%) = 0.24W/1.33W = 18.0%
Iomax = 1.2A 0.675v to 0.75v after power-on

-X
PG5110 PG5112
1 2 1 2
0D6V_S0 PWR_VDDQ_VTT GAP--CLOSE--PWR--6--GP GAP--CLOSE--PWR--6--GP
PG5113
1 2 PG5111 PU5106 PG5119
GAP-CLOSE-PW R-6-GP 1 2 PC5130 PC5131 1 2
PWR_2D5V_PG 1 PGOOD GND 9 GAP--CLOSE--PWR--6--GP

2 1

2 1
PG5114 PWR_2D5V_S3_EN PC5144 PC5143

SC10U6D3V3MX--L-GP

SC10U6D3V3MX--L-GP
DY GAP--CLOSE--PWR--6--GP PWR_2D5V_S3_LDO_PVDD 3
2 EN GND 8 PWR_2D5V_S3_LDO_FB
1 2 5V_S5 VIN ADJ 7

2 1

2 1
PWR_2D5V_S3_LDO_VDD 4

SC10U6D3V3MX--L-GP

SC10U6D3V3MX--L-GP
PC5117 PC5118 VDD VOUT 6
SC10U6D3V3MX-L-GP

SC10U6D3V3MX-L-GP

NC#5 5
2 1

2 1

GAP-CLOSE-PW R-6-GP

RT9025-25ZSP--2-GP

R1
074.09025.003D PC5136

Te

2 1
PR5131
PR5130 24K3R2F-1-GP SC22P50V2JN--L-GP
2D2R2F-GP 1ST = 074.09025.003D
1 2
2ND = 74.09661.07D PWR_2D5V_S3_LDO_FB

PC5135 R2 PR5134

2 1
PWR_2D5V_S3_EN 11K3R2F-2-GP

SC1U10V2KX--L1-GP

21 2 1
SY8288 For DDR4 PC5139
CS
Enable DY Vout Setting

Vout = 2.5V

CDD1U16V2KX--L-GP
2 1
EN_Logic-High = 1.4V Vout = 0.8 * ( 1 + R1/R2 )

ch
EN_Logic-Low = 0.8V = 0.8 * ( 1 + 24.3 / 11.3K)
= 2.5204V

B B
PWR_DCBATOUT_2D5V

ni
1

PC5142 PC5141 PC5140

SC4D7U25V5KX-L2-GP

SC4D7U25V5KX-L2-GP

SCD1U25V2KX-L--GP
2 1

2 1

DCBATOUT PWR_DCBATOUT_2D5V
2

DY DY DY PG5103
1 2
GAP-CLOSE-PW R-6-GP
3D3V_S5

ca
PG5104
PR5137 PC5137
1 2
2D2R3F-L-GP SCD1U50V3KX--L--GP GAP-CLOSE-PW R-6-GP
PR5133
DY
100KR2J--1-GP PWR_2D5V_BOOT 1 2 PWR_2D5V_BOOT_A 1 2 Design Current :4A
PC5132
OCP : 7 A
2 1

2 1

SC2D2U10V3KX--L-GP DY 2D5V_PWR 2D5V_S3

DY
PU5105 PL5102 2D5V_PWR
P-
IIND-1UH-94-GP-U
PWR_DCBATOUT_2D5V SY8288RAC_LDO_OUT 17 PWR_2D5V_PH 1 2 PG5105
VCC LX#6 6 2
LX#19 19 68.1R01B..10K 1
GAP-CLOSE-PW R-6-GP
PWR_2D5V_PG 2nd = 68.1R010.20I
LX#20 20
2 IN#2
PG5106
3 IN#3 NC#10 10 DY DY

l
4 IN#4 1 2
NC#12 12 GAP-CLOSE-PW R-6-GP
5 IN#5 NC#16 16 PC5150 PC5149 PC5148 PC5147 PC5151 PC5145
SC22U6D3V5MX--L3-GP

SC22U6D3V5MX--L3-GP

SC22U6D3V5MX--L3-GP

SC22U6D3V5MX--L3-GP

SC22U6D3V5MX--L3-GP

SCD1U16V2KX-L--GP
2 1

2 1

2 1

2 1

2 1

2 1
PWR_2D5V_BOOT 1 BS PG5107
PWR_2D5V_PG 9 PG 1 2
3D3V_S5 PWR_2D5V_S3_EN 11 EN GAP-CLOSE-PW R-6-GP
PWR_2D5V_CS GND 7
PWR_2D5V_FB
13 ILMT GND 8 Close to output cap pin1, not
PG5136 14 FB PG5108
PWR_2D5V_BYP GND 18 inside of the output cap
2 1 15 BYP GND 21 1 2
GAP-CLOSE-PW R-6-GP
GAP--CLOSE--PWR--3--GP

Reference OSLO & LT41S 20150724 PC5134

SY8288RAC--GP
PWR_2D5V_FB_G 2
PG5135
1 2D5V_PWR DY DY
SC1U10V2KX--L1-GP 074.08288.0043 DY DY DY
2 1

DY GAP--CLOSE--PWR--3--GP
DY
2

1 PR5135 2 0R0402-PAD PWR_2D5V_S3_EN

17,24,40 SIO_SLP_S4# PC5138
1

SC22P50V2JN--L-GP
1

PR5138
DY
R1
PC5133 63K4R2F-2-GP PWR_2D5V_FB_A
SCD1U16V2KX--L-GP
DY
2
2 1

DY
2

PR5140

Enable
A 0R0402-PAD A

20150604 power modify

1

PWR_2D5V_FB

OCP setting R2
1

PR5139
20KR2F-L3-GP
DY
PWR_2D5V_CS
Vout Setting
Vout = Vref * ( 1 + R1/R2 )
2
2

PR5103
= 0.6 * ( 1 + 63.4K / 20K)

Eletro-XTechnical Eletro-XTechnical
<Core Desiiign>
0R0402-PAD

= 2.502 V
Wistron Corporation
1

21F,,, 88,,,Sec.1,,, Hsiiin Taiii W u Rd., Hsiiichiiih,,,

Taiiipeiii Hsiiien 221,,, Taiiiwan,,, R.O.C...

Current Limit Tiittllle

Low : OCP8A MEM&MEMVTT
Floating : OCP12A Siiize Document Number Rev
A1
LV115 SKL-U -1
Dattte:: Monday,,, Apriiilll 25, 2016 Sheett 51 off 102

5 4 3 2 1
 A B C D E

VCCIO
+VCCIO(ICCMAX = 2.73A)

+VCCIO 1D0V_S5
5V_S5 1D0V_S5
Cyntec. 2.5mm×2.0mmX1.2mm
DCR: 59m Ohm

1
2
PU5203

VIN#1 VOUT#8
8
7
Idc : 3 A , Isat : 3A
Eletro-XTechnical
3 VIN#2 VOUT#7 6
17,24,40,51,54 SI O_SLP_S3# 1 2 PW R_VC C I O_EN 4 VBIAS VOUT#6 5
PR5216 0R2J -2-GP ON GND
9
PC 5227 VIN#9
1 2 SC 22P50V2J N--L-GP

2 1
40,46 VR_EN PR5218 0R2J -2-GP DY TPS22961D NYT-GP

DY 074.22961.0093
Power modify 20140815
4 4

El
EOPIO and EDRAM 5V_S5 1D0V_S5
PU5204
PR5221
+V_EDRAM_VR
+V_EDRAM_VR
40 EN_ED RAM_VR 1 VIN#1 VOUT#8 8
V_EDRAM_EOPIO_R 1 2 Voltage = 1.0 V ± 50 mV
2 VIN#2 0R1206-PAD- 1-GP
VOUT#7 7 Imax = 3.2 A

et
PR 5217 3 VBIAS Imax = 6 A
1 2 EN_ED RAM_VR VOUT#6 6 Rds on = 4.65mohm TRISE = 240 us
17,24,40,51,54 SI O_SLP_S3# 4 ON GND 5
0R2J -2-GP
[#544669 Rev0.7] CRB: ALL_SYS_PWRGD_PMIC
23e VIN#9 9 1D0V_S5
DY
[#543977 Rev0.7] PDDG: PM_SLP_S3#

+V_EOPIO_VR
TPS22961D NYT-GP V_EDRAM_EOPIO_R
074.22961.0093
PC 5211
3 3
PC 5210 Voltage = 1.0 V ± 50 mV

SCD1U16V2KX--L-GP
DY

SC10U10V5KX--2GP
23e Imax = 2.8 A

ro
21

21
TRISE = 240 us
V_EDRAM_EOPIO_R + V_EOPI O_VR

PR5222 2 1
1D0V_S5 0R1206-PAD- 1-GP

-X
PC5215 PC 5216 PC 5217
21

21

21

SC1U10V2KX -L1-GP SC D 1U16V2KX -L-GP SC 10U6D 3V3MX--L-GP

23e DY DY

Te
ch
2 2

ni
ca
l
1 1

<Core Desiiign>

Eletro-XTechnical Wistron Corporation

21F,,, 88,,,Sec.1,,, Hsiiin Taiii W u Rd., Hsiiichiiih,,,
Taiiipeiii Hsiiien 221,,, Taiiiwan,,, R..O..C...
Eletro-XTechnical
Tiittllle

DCDC-0D975V_VCCIO
Siiize Documenttt Number Rev
C usttom
LV115 SKL-U -1
Dattte: Monday,,, Apriiilll 25, 2016 Sheet 52 offf 102
A B C D E
 5 4 3 2 1

Main Func = 1D0V

DCBATO UT PW R_DCBATOUT_1D0V
AOZ1268 for 1D0V
D
PG5311 5V_S5
Eletro-XTechnical D

1 2

GAP-CLOSE-PW R-6-G P
PG5312
TDC : 10A

1
1 2
PC5302 MAG. 7*7*3
DCR: 8.9m +/-7% Ohm

SC1U10V2KX-L1-GP
GAP-CLOSE-PW R-6-G P

2
PG5313
1 2 Idc : 11 A , Isat : 22A
PW R_DCBATOUT_1D0V PU5301 1D0V_S5
GAP-CLOSE-PWR-6-GP
PL5301
21 VCC 18 PW R_1D0V_LX 1 2 IIND-1UH-94-GP-U PC5303 PC5305 PC5301 PC5316 PC5318 PC5306 PC5307
LX#18
LX#17 17 68.1R01B.10K 11/25 JAIME
2nd = 68.1R010.20I

SC22U6D3V5MX-L3-GP

SC22U6D3V5MX-L3-GP

SC22U6D3V5MX-L3-GP

SC22U6D3V5MX-L3-GP

SC22U6D3V5MX-L3-GP

SC22U6D3V5MX-L3-GP

SCD1U25V2KX-L-GP
LX#16 16
LX#11 11

1
7 IN#7 LX#10 10

2
8 IN#8 PC5304

2 1

2 1

2 1
PR5301 PG5315

PC5308 SCD1U25V2KX-L-GP
PWR1_1D0V2_BOOTSCD1U25V2KX-L-GP
BST 20
C 9 IN#9 C

2
93K1R2F-L-G P
PW R_1D0V_FB GAP-CLOSE-PWR-6-GP
DY DY
FB 5

1
1

1
PC5309 PC5312 PC5317 1 2 PW R_1D0V_TON 6 TON

SC10U25V5KX-L-GP

SC10U25V5KX-L-GP

SC10U25V5KX-L-GP
PW R_1D0V_PG 1 PGOOD AGND 4

2
PW R_1D0V_VFB1
PW R_1D0V_EN 2 EN 19
PGND
PGND 14
PW R_1D0V_PFM 3 13
PFM# PGND
12 DY

El
PGND

1
PW R_1D0V_SS 22 15
SS PGND PC5319
2K8R2F-GP
R1

SC220P50V2KX-3GP
PR5302

2
PR5303 AOZ2262QII-10-GP-U

1
100KR2F-L1-GP 074.02262.0043

2
PC5313
SCD01U50V2KX-L-GP

2
P W R_1D0V_LX

et
B
3D3V_S5 B

1
1 PR5305 2 10KR2J-3-GP

11/07 jaime
PR5304
R2
10K2R2F-G P
Vo=0.8x(1+R1/R2) RFC5301

2 1
0R0402-PAD SC8P50V2DN-1GP
1 PR5306 2 PW R_1D0V_PG =0.8x(1+8.06/31.6) DY

2
40 RSMRST_PW RGD#
=1.004

ro
0R0402-PAD
54 PW R_1D8V_PWRGD# 1 PR5312 2 PW R_1D0V_EN

PC5314
2 1

SC1KP50V2KX -L-1-G P
<Core Desiiign>

-X
Wistron Corporation
A 21F,,, 88,,, Sec.1,,, Hsiiin Taiii W u Rd., Hsiiichiiih,,, A
TaiiipeiiiHsiiien 221,,, Taiiiwan,,, R.O.C...

Title

DCDC-V1D00A
Siiize Documenttt Number Rev

Te
Custt om
LV115 SKL-U -1
Date: Monday,,, Apriiilll 25, 2016 Sheet 53 off 102
5 4 3 2 1

ch
ni
ca
Eletro-XTechnical
l Eletro-XTechnical
 5 4 3 2 1

Main Func = 1D5V

3D3V_S5
S-1339D18for 1D8V_S0

Eletro-XTechnical

1
PC5408
SC1U10V2KX--L1-GP

2
Design Current = 16mA

PU5402 1D8V_PWR_AUDIO 1D8V_S0

PG5404
D 1 5 1 2 D
VIN VOUT
2
VSS
17,24,40,51,52 SIO_SLP_S3# 1 2PWR_1D8V_EN_AUDIO 3 4
ON/OFF NC#4 GAP-CLOSE-PWR--6--GP
PR5405 PC5407
0R0402-PAD DY S--1339D18-N5T3U3-GP
PC5409

SCD1U16V2KX--3GP
2 1

2 1
SC1U10V2KX--L1-GP
074.01339.0B3F

El
3D3V_S5

1
PR5414
11/07 jaime

et
100KR2F--L1-GP

1D8V_S5 Design Current = 665mA

2
1 PR5416 2 0R0402-PAD
53 PWR_1D8V_PWRGD#
C 3D3V_S5 C
1D8V_PWR 11/25 jaime 1D8V_S5

ro
PG5401 PG5405
GAP-CLOSE-PWR--6--GP GAP-CLOSE-PWR--6--GP
1 2 1 2

PG5402 PG5406
GAP-CLOSE-PWR--6--GP PU5401 GAP-CLOSE-P W R
--6--GP
1 2 PC5406 PC5402 1 2
PC5401 PWR_1D8V_POK
SC10U6D3V3MX--L-GP

SC22P50V2JN--L-GP

1 PGOOD GND 9
2 1

2 1

21

11/25 jaime PWR_1D8V_EN PC5410 PC5411

SC1U10V2KX--L1-GP

2 EN 8 PG5407
GND 1.8V_RUN_FB
PWR_1D8V_S5_PVDD 3 VIN 7 GAP-CLOSE-PWR--6--GP

-X
ADJ

2 1

21
SC10U6D3V3MX--L-GP

SC10U6D3V3MX--L-GP
PWR_1D8V_S5_VDD 4 VDD 6 1 2
VOUT
NC#5 5

RT9025-25ZSP--2-GP
PC5405

1
074.09025.003D R1 PR5406 SC22P50V2JN--L-GP

2 1
12K7R2F--GP
5V_S5 PR5408
2D2R2F--GP
1ST = 074.09025.003D

2
1 2 2ND = 74.09661.07D

Te
1.8V_RUN_FB
PC5421

1
R2
SC1U10V2KX--L1-GP
2 1

PR5403
10KR2F--L1-GP

2
Vout Setting

ch
Vout = 0.8 * ( 1 + R1/R2 )
1 PR5407 2 0R0402-PAD PWR_1D8V_EN = 0.8 * ( 1 + 12K7 / 10K)
17,45 3V_5V_POK
= 1.816V
B PC5404 11/28 jaime B
SC22P50V2JN--L-GP
2 1

PR5409 1 2 0R2J--L-GP
40,45 3V_EN DY
DY

ni
ca
l
A A

<Corrre Desiiign>

Wistron Corporation
21F,,, 88, Sec...1, HsiiinTai W u Rd...,,,Hsiiichih,

Eletro-XTechnical Eletro-XTechnical
Taiiipeiii Hsiiien 221,,, Taiiiwan,,, R.O.C...

Title

DCDC V1D8V
Siiize Document Number Rev
A2
LV115 SKL-U -1
Date: Monday,,, Aprrriill25, 2016 Sheet 54 off 102
5 4 3 2 1
 5 4 3 2 1

SSID = VIDEO
SSID = VIDEO LCD POWER (Do Not use SW 74.09724.09F)
INVERTER POWER Close to eDP connector

DCBATOUT_LCD
DCBATOUT
LCD_BRIGHTNESS
2014/2/5:Change U5201 to 074.06288.007B
3D3V_S0
Layout 40mil Eletro-XTechnical LCDVDD

F5501 U5501
2 1
5 1
POLYSW--1D1A24V-GP-U R5507 IN OUT
GND 2
1

1
C5506 C5504 C5505 C5511 EC5502 1 2 LCDVDD_EN 4
OC# 3

SC33P50V2JN--3GP
8 EDP_VDD_EN EN
DY DY
SC4D7U25V5KX--L2-GP

SC1KP50V2KX-1GP

SCD1U50V3KX-GP

SC68P50V2JN--1GP 69.50007.A31 DY
2 1

2 1

2 1
0R0402-PAD C5508
2

D 2 FC5501 SY6288C20AAC--GP D

SC33P50V2JN--3GP
1

SC4D7U6D3V3KX--GP
2 1
1ST = 69.50007.A31 DY

2 1
C5509 C5507

SCD1U16V2KX--3GP

SC4D7U6D3V3KX--GP
R5514 074.06288.007B
2ND = 69.50007.A41 DY

2 1

2 1
100KR2J--1-GP

2
eDP Device
Panel BL brightness/Power En/BL En
R5510
Item Device 8 L_BKLT_EN
1 2
PANEL_BLEN 24
0R0402-PAD
1 eDP Panel EMB_HPD_R R5503
1 21KR2J--1-GP BLON_OUT_C
24 BLON_OUT
2

2
Camera
R5516
3 DMIC

El
100KR2F--L1-GP
4

1
R5508
5 L_BKLT_CTRL_1 C5510

SC100P50V2JN--3GP
1 2

eDP connector
8 L_BKLT_CTRL 0R0402-PAD
6

1
2 1
R5532
R5530 100KR2J--1-GP
100KR2J--1-GP DY

et

2
DCBATOUT_LCD

EDP1 C5527
31 SC100P50V2JN--3GP

21
1
C C
2

ro
3
4 R5515
5 LCD_BRIGHTNESS 1 2 L_BKLT_CTRL_1
6 BLON_OUT_C 33R2J--2-GP
7
8
9
10
DMIC_DATA 27
DMIC_CLK 27
DMIC Test point
11 USB_PN4_R
Camera
12 USB_PP4_R
CAMERA POWER

-X
13
14 eDP_AUXN_CPU_C C5528 1 2 SCD1U16V2KX--L-GP
Layout 40 mil
eDP_AUX_CPU_N 8
15 eDP_AUXP_CPU_C C5526 1 2 SCD1U16V2KX--L-GP eDP_AUX_CPU_P 8
16 3D3V_CAMERA_S0 3D3V_S0 1 AFTP5525
17
18
eDP_TXN1_CPU_C C5514 1
eDP_TXP1_CPU_C C55131
2 DYSCD1U16V2KX--L-GP
2 DYSCD1U16V2KX--L-GP
eDP_TX_CPU_N1 8
eDP_TX_CPU_P1 8
eDP Panel 1
R5518
2
19 0R0603-PAD LCDVDD_R 1 AFTP5501
20 eDP_TXN0_CPU_C C5532 1 2 SCD1U16V2KX--L-GP U5504
21 eDP_TXP0_CPU_C C5529 1 2 SCD1U16V2KX--L-GP eDP_TX_CPU_N0 8 R5522
eDP_TX_CPU_P0 8 2 3D3V_S0_CAMERA 1 OUT DCBATOUT_LCD 1 AFTP5535
22
23 EMB_HPD_R 1 2 R5542
1 DY 0R3J-0-U-GP IN 5
BLON_OUT_C 1 AFTP5543
2 GND

Te
EDP_DCR_EN 0R0402-PAD EDP_HPD 8
24 3 OC# DY EN 4 CAMERA_EN 20 LCD_BRIGHTNESS 1 AFTP5542
25 3D3V_CAMERA_S0 C5531
26 DMIC1_VCC SC10U6D3V3MX--L-GP

2 1
27 G524B1T11U--GP C5530
28 074.00524.0B9F SC10U6D3V3MX--L-GP

2 1
29 R5528
DY
1

30 LCDVDD_R 1 2 C5523 C5525 2ND = 74.06288.07F

0R0603-PAD LCDVDD
EDP_DCR_EN AFTP5538
SCD1U16V2KX--L-GP

SC1U10V2KX--L1-GP

32 1
DY
2

2
1

C5522 C5524
ACES-CON30--20--GP-U
SCD1U16V2KX--L-GP

SC1U10V2KX--L1-GP

20.K0848.030 R5509
2

USB_PN4_R USB_CPU_PN4

ch
1 2 USB_CPU_PN4 16
1ST = 20.K0848.030 10/20 AFTP5503, AFTP5504 USB_PN3, USB_PP3 change to USB_PN3_R, USB_PP3_R
0R2J--L-GP
2ND = 20.K0809.030 R5506
08/18 add C5523(0.1uF), C5525(1uF) USB_PP4_R 1 2 USB_CPU_PP4
USB_CPU_PP4 16
B
3RD = 020.K0160.0030 B
0R2J--L-GP 1 AFTP5541

EMB_HPD_R 1 AFTP5545
eDP_TXP0_CPU_C 1 AFTP5546
R5531 eDP_TXN0_CPU_C 1 AFTP5547

ni
3D3V_S0 3D3V_S0 eDP_TXP1_CPU_C 1 AFTP5548
0R0402-PAD eDP_TXN1_CPU_C 1 AFTP5549
DMIC1_VCC 1 2 eDP_AUXP_CPU_C 1 AFTP5550
ED5507 eDP_AUXN_CPU_C 1 AFTP5551
1

C5534 DMIC_DATA USB_PP4_R

SCD1U16V2KX--3GP

1 6
2

ca
2 5

DMIC_CLK 3 4 USB_PN4_R

AZC199-04S--R7G--GP

75.00199.07C

l
1ST = 75.00199.07C
2ND = 75.00005.D7C

DY

A A

<Corrre Desiiign>

Wistron Corporation
21F,,, 88, Sec...1, HsiiinTai W u Rd...,,,Hsiiichih,

Eletro-XTechnical Eletro-XTechnical
Taiiipeiii Hsiiien 221,,, Taiiiwan,,, R.O.C...

Title
LCD&CAM&DMC&Touch
Siize Document Number Rev
A2
LV115 SKL-U -1
Date: Monday,,, Aprrriill25, 2016 Sheet 55 off 102
5 4 3 2 1
 5 4 3 2 1

5V_CRT_S0_R

Eletro-XTechnical

1
EMI Request C5602
SCD1U16V2KX--L-GP
5V_S0

2
CRT
CRT ED5603 CRT_DDCDATA_CON
1 2 CRT1 5V_CRT_S0_R 1
CRT_DDCDATA_CON 1 AFTP5601
ESD5B5D0ST1G--GP-U 9 4 CRT_DDCCLK_CON 1 AFTP5602 ED5602
ED5604 VCC_CRT NC#4
CRT CRT_DDCCLK_CON NC#11
11 CRT_R 1 AFTP5603
CRT_VSYNC_CON 5V_CRT_S0_R 5V_CRT_S0 5V_S0
1 2 CRT_G 1 AFTP5604 1 6
D 12 CRT_B 1 AFTP5605 D
DDCDATA_ID1 D5601
ESD5B5D0ST1G--GP-U 15 CRT_VSYNC_CON 1 AFTP5606
DDCCLK_ID3 F5601
CRT ED5605 5 CRT_HSYNC_CON 1 AFTP5607 2 5
GND AFTP5608
1 2 CRT_R 1 6 2 1 K A
CRT_RED GND
ESD5B5D0ST1G--GP-U
CRT_G
CRT_B
2
CRT_GREEN GND
7
CRT_HSYNC_CON
75.00099.07C FUSE--1D1A6V--8GP
3 8 3 4
ED5606 CRT_BLUE GND
CRT CRT_VSYNC_CON 14 GND
10 RB551VM--30TE--17-GP
1 2
VSYNC GND
16 CRT CRT
CRT_HSYNC_CON 13 17 BAV99S-4--GP FC5603

SC33P50V2JN--3GP
HSYNC GND
ESD5B5D0ST1G--GP-U
DY 83.R5003.N8F

2 1
CRT ED5607 CRT
1 2 D-SUB-15-148-GP-U3
1ST = 83.R5003.N8F
20.20978.015
ESD5B5D0ST1G--GP-U near CRT conn
CRT ED5608 2nd = 83.55130.08F
1 2
CRT
ESD5B5D0ST1G--GP-U 05/12 Add FC5603 for RF.
CRT ED5609
1 2

ESD5B5D0ST1G--GP-U

El
DP_CRT_HSYNC_CON R5620 1
CRT 2 47R2J--2-GP CRT_HSYNC_CON

L5601
DP_CRT_VSYNC_CON R5621 1
CRT 2 47R2J--2-GP CRT_VSYNC_CON
DP_CRT_R
CRT CRT_R CRT_DDCDATA_CON
1 2
CRT_DDCCLK_CON
BLM18BB220SN--GP CRT_VSYNC_CON
CRT_HSYNC_CON

et
L5602
CRT
DP_CRT_G 1 2 CRT_G
C5603 C5604 C5605 C5606

SC100P50V2JN--3GP

SC100P50V2JN--3GP

SC33P50V2JN--3GP

SC33P50V2JN--3GP
BLM18BB220SN--GP DY DY CRT CRT

2 1

2 1

2 1

2 1
CRT_HPD_PCH
CRT_HPD_PCH 8
C C
L5603
CRT 04/23 Change Net Name to CRT_HPD_PCH

1
ro
DP_CRT_B 1 2 CRT_B
5V_CRT_S0 R5611
BLM18BB220SN--GP 100KR2J--4-GP
CRT

2
LAYOUT NOTE:
1

C5610 C5611 C5612

R5617 R5618 R5619 C5607 C5608 C5609
CRT CRT CRT

-X

2
1
2 1

2 1
21

CRT CRT CRT CRT CRT CRT

All cap need close to chip
75R3F--GP

75R3F--GP

75R3F--GP

SC2P50V2CN--GP

SC2P50V2CN--GP

SC2P50V2CN--GP
2 1

2 1

2 1

RN5604
SC2P50V2CN--GP

SC2P50V2CN--GP

SC2P50V2CN--GP

especially C616 close pin5 SRN2K2J--5--GP

2

CRT
C618 and C619 close pin19

3
4
C620 and C621 close pin9 CRT_DDCDATA_CON

C617 close pin20 CRT_DDCCLK_CON

Te
C614 close pin25
C613 lose pin24
3D3V_S0 AVCC33
5V_S0 HVSYNC_POWER

L5605
1 2 R5630 1 2

ch
MHC1005S600LBP--GP 0R0402-PAD
1

CRT C5615
SC10U10V5KX--L1-GP
C5640 C5641
2 1

SC4D7U6D3V3KX--GP SCD1U16V2KX--L-GP
CRT
21

CRT CRT U5602

2

B CRT C5614 1 2 SCD1U16V2KX--L--GP VCCK_12 4

AVCC_12 AUX_P
2 PCH_DPC_AUXP_C SCD1U16V2KX--L-GP 2 1 C5634 CRT
PCH_DPC_AUXP 8
B
CRT C5618 1 2 SCD1U16V2KX--L--GP
AUX_N
3 PCH_DPC_AUXN_C SCD1U16V2KX--L-GP 2 1 C5623 CRT
PCH_DPC_AUXN 8
CRT C5632 1 2 SC2D2U10V3KX--L-GP 25 VCCK_12
3D3V_S0 VDD_DAC_33 CRT C5631 1 2 SC10U6D3V3MX--L-GP 5 PCH_DPC_P0_C SCD1U16V2KX--L--GP 2 1 C5624 CRT
LANE0_P 1 C5625 CRT PCH_DPC_P0 8
CRT C5613 1 2 SCD1U16V2KX--L-GP AVCC33 1 AVCC_33 6 PCH_DPC_N0_C SCD1U16V2KX--L-GP 2
LANE0_N PCH_DPC_P1_C SCD1U16V2KX--L-GP 2 1 C5627 CRT PCH_DPC_N0 8
7

ni
L5606 CRT C5616 1 LANE1_P CRT
2 SCD1U16V2KX--L-GP 3D3V_S0 14 VCC_33 8 PCH_DPC_N1_C SCD1U16V2KX--L-GP 2 1 C5628 PCH_DPC_P1 8
1 2 LANE1_N PCH_DPC_N1 8
CRT C5620 1 2 SCD1U16V2KX--L--GP VDD_DAC_33 20 17
VDD_DAC_33 HVSYNC_PW R HVSYNC_POWER
1

MHC1005S600LBP--GP CRT C5633 1 2 SC10U10V5KX--L1-GP 19 DP_CRT_HSYNC_CON

C5626 CRT C5617 1
HSYNC
CRT 2 SCD1U16V2KX--L--GP 3D3V_S0 26 18 DP_CRT_VSYNC_CON
SC10U10V5KX--L1-GP PVCC_33 VSYNC
2

CRT BLUE_P
21 DP_CRT_B
CRT_DDCCLK_CON 15
VGA_SCL GREEN_P
22 DP_CRT_G
CRT_DDCDATA_CON 23 DP_CRT_R

ca
16
VGA_SDA RED_P
DDPC_CLK 30 27
29 SMB_SCL LDO_RSTB
DDPC_DATA 28 RTD2166_EXT_CLK_IN
SMB_SDA EXT_CLK_IN 31
RTD2166_GPI1 11 EXT1.2V_CTRL 32 CRT_HPD_PCH
3D3V_S0 3D3V_S0 RTD2166_GPI2 12 GPI1/SPI_CLK HPD
13 GPI2/SPI_SI
GPI3/SPI_SO 24
3D3V_S0 3D3V_S0 POL1 GND
10 33
POL2 9 POL1/SPI_CEB GND
RTD2166_EXT_CLK_IN POL2

l
1

R5625
RTD2166-CGT--GP
1

R5623 R5622 4K7R2J--L-GP

1

1
1

R5616 R5624 R5614 R5615 DY 071.02166.0003

4K7R2J--L-GP 4K7R2J--L-GP
2

DY CRT 4K7R2J--L-GP 4K7R2J--L-GP 4K7R2J--L-GP 4K7R2J--L-GP CRT

DY DY DY DY
2

POL1 POL2

RTD2166_GPI1
DDPC_CLK 8
1

R5608 R5609
RTD2166_GPI2 DDPC_DATA 8
A A
4K7R2J--L-GP 4K7R2J--L-GP
CRT DY 04/23 Change Net Name to DDPC_CLK
04/23 Change Net Name to DDPC_DATA
2

<Corrre Desiiign>

Wistron Corporation
21F,,, 88,,, Sec.1,,, Hsiiin Taiii W u Rd., Hsiiichiiih,,,
Taiiipeiii Hsiiien 221,,, Taiiiwan,,, R.O.C...

Eletro-XTechnical Eletro-XTechnical
Title
CRT
Siize Document Number Rev
A2 LV115 SKL-U -1
Date: Monday,,, Aprrriill25, 2016 Sheet 56 offf 102

5 4 3 2 1
 5 4 3 2 1

SSID = VIDEO HDMI CONNECTOR 3D3V_S0

AFTP5701 1 HDMI_DATA2_R_C 5V_S0 5V_CRT_PH

Eletro-XTechnical
AFTP5702 1 HDMI_DATA2_R_C#
AFTP5703 1 HDMI_DATA1_R_C R5721 5V_HDMI

2
AFTP5704 1 HDMI_DATA1_R_C# 1 2 0R3J-0-U-GP
AFTP5705 1 HDMI_DATA0_R_C HDMII1 R5720
AFTP5706 1 HDMI_DATA0_R_C# D5702
69.48001.081 10KR2J--3-GP
AFTP5707 1 HDMI_CLK_R_C A K F5701 1 2 5V_HDMI 18
+5V_POWER SCL
15 DDC_CLK_HDMI
AFTP5708 1 HDMI_CLK_R_C# 16 DDC_DATA_HDMI

1
AFTP5709 DDC_CLK_HDMI B0530WS--7-F--GP SDA
1 DY

1
HDMI Passive Level Shifter
AFTP5710 1 DDC_DATA_HDMI DY HDMI_DATA0_R_C 7
TMDS_DATA0+
AFTP5711 1 5V_HDMI 83.R5003.G8H POLYSW--1D1A6V-9--GP-U C5701 HDMI_DATA0_R_C# 9 13 HDMI_CEC 1 AFTP5714
AFTP5712 TMDS_DATA0- CEC
1 HPD_HDMI_CON HDMI_DATA1_R_C 4 17

2
AFTP5713 R5704 2 SCD1U16V2KX-L--GP HDMI_DATA1_R_C# TMDS_DATA1+ DDC/CEC_GROUNG HPD_HDMI_CON
D 1 1 6 19 D
Close to HDMI Connector 0R3J--0--U-GP HDMI_DATA2_R_C 1
TMDS_DATA1-
TMDS_DATA2+
HOT_PLUG_DETECT
DY HDMI_DATA2_R_C# 3
TMDS_DATA2- RESERVED#14
14

8
TMDS_DATA0_SHIELD
5
TMDS_DATA1_SHIELD
2
TMDS_DATA2_SHIELD
20
GND
C5702 1 2 SCD1U16V2KX--L-GP HDMI_CLK_C 11 21
8 HDMI_CLK TMDS_CLOCK_SHIELD GND
C5703 1 2 SCD1U16V2KX--L-GP HDMI_CLK_C# HDMI_CLK_R_C 10 22
8 HDMI_CLK# TMDS_CLOCK+ HDMI GND
HDMI_CLK_R_C# 12 23
C5704 1 2 SCD1U16V2KX--L-GP HDMI_DATA0_C# TMDS_CLOCK- (A_Type) GND
8 HDMI_DATA0#
8 HDMI_DATA0 C5705 1 2 SCD1U16V2KX--L-GP HDMI_DATA0_C
SKT-HDMII23-156-GP-U
C5706 1 2 SCD1U16V2KX--L-GP HDMI_DATA1_C
8 HDMI_CRT_P1 C5707 1 2 SCD1U16V2KX--L-GP HDMI_DATA1_C#
8 HDMI_CRT_N1 022.10025.00J1
8 HDMI_CRT_N0
C5708 1 2 SCD1U16V2KX--L-GP HDMI_DATA2_C# ESD STUFF OPTION
8 HDMI_CRT_P0
C5709 1 2 SCD1U16V2KX--L-GP HDMI_DATA2_C HDMI_DATA2_R_C R5706 1 2 HDMI_DATA2_R_C# 1ST = 022.10025.00J1
150R2F--4-L-GP ESD STUFF OPTION
HDMI_DATA1_R_C R5707 1 2 HDMI_DATA1_R_C#
150R2F--4-L-GP ESD STUFF OPTION 2ND = 022.10025.00L1
HDMI_DATA0_R_C R5708 1 2 HDMI_DATA0_R_C#
150R2F--4-L-GP ESD STUFF OPTION 3RD = 022.10025.00K1

5
6
7
8

5
6
7
8
HDMI_CLK_R_C R57091

El
2 HDMI_CLK_R_C#
RN5705 RN5706 150R2F--4-L-GP
SRN470J--5-GP SRN470J--5-GP

4
3
2
1

4
3
2
1
Q5704
5V_CRT_PH 5V_S0
HDMI_PLL_GND AO3413L-GP

et
S D

HDMI DDC Passive Level Shifter 5V_S0

C5710
DY 84.03413.B31

3
C5711

2Q5105_VDD_EN# G
SC4D7U6D3V3KX--GP

SCD1U16V2KX--L-GP
DY

2 1

2 1
C D5701 DY C
BAW56-5-GP

ro
83.00056.Q11

1
1ST =83.00056.Q11
HDMI A type pin define

DDC_DATA_HDMI_R

2
DDC_CLK_HDMI_R
2ND = 75.00056.07D R5713 R5714
10KR2J--3-GP 10KR2J--3-GP
DY DY
(Total: 19pin)

-X

1
3D3V_S0
Q5101_VDD_EN#
1

3D3V_S0

D
3
4
R5701 EC5701 Q5705
Q5701 1MR2J--1-GP 3D3V_S0 RN5707

Not ic e: ZZ .2N 70 2. J3 10 1
1 6 HDMI_PLL_GND SRN2K2J--5-GP
21

84.2N702.J31 DY
2

SCD1U16V2KX--L-GP

2 5
2ND = 84.2N702.031

Te
2
1
HPD_HDMI_CON 3 4 CPU_DP1_HPD 8 3rd = 84.2N702.W31 2N7002K--2-GP

G
Q5703 5V_S0
2N7002KDW--GP 1 6 DDC_DATA_HDMI
8 CPU_DP1_CTRL_DATA
1

84.2N702.A3F
R5703 2nd = 075.063D1.007C 2 5
100KR2J--1-GP
3 4
2

HPD_HDMI_CON_R 2N7002KDW--GP 待
禁
07/02 Change Part Number 84.07002.I31(禁
) to 84.2N702.J31
1

84.2N702.A3F DDC_CLK_HDMI
R5712

ch
2nd = 075.063D1.007C
0R0402-PAD 8 CPU_DP1_CTRL_CLK
2

B ED5701 B

HDMI_DATA2_R_C 1 10 HDMI_DATA2_R_C

HDMI_DATA2_R_C# 2 9 HDMI_DATA2_R_C#
3 8

ni
HDMI_DATA0_C 1 R5705 2 HDMI_DATA0_R_C HDMI_DATA1_C 1 R5718 2 HDMI_DATA1_R_C
0R0402-PAD 0R0402-PAD HDMI_DATA1_R_C 4 7 HDMI_DATA1_R_C

HDMI_DATA1_R_C# 5 6 HDMI_DATA1_R_C#

L05ESDL5V0NA--4-GP
075.00550.0071

ca
2ND = 75.01043.073
EMI TEST
HPD_HDMI_CON DDC_CLK_HDMI DDC_DATA_HDMI
HDMI_DATA0_C# 1 R5715 2 HDMI_DATA0_R_C# HDMI_DATA1_C# 1 R5719 2 HDMI_DATA1_R_C# ED5702
0R0402-PAD 0R0402-PAD
HDMI_CLK_R_C 1 10 HDMI_CLK_R_C

HDMI_CLK_R_C#
EMI Request
2 9 HDMI_CLK_R_C#
3 8

1
1

1
l
HDMI_CLK_C 1 R5710 2 HDMI_CLK_R_C HDMI_DATA2_C 1 R5711 2 HDMI_DATA2_R_C HDMI_DATA0_R_C 4 7 HDMI_DATA0_R_C ED5705 ED5703 ED5704
0R0402-PAD 0R0402-PAD VARIISTOR--27V-2--GP VARIISTOR--27V-2--GP VARIISTOR--27V-2--GP
HDMI_DATA0_R_C# 5 6 HDMI_DATA0_R_C# 69.80005.081 69.80005.081 69.80005.081
EMI TEST DY DY

2
L05ESDL5V0NA--4-GP
075.00550.0071
2ND = 75.01043.073
EMI TEST

ED5706
HDMI_CLK_C# 1 R5717 2 HDMI_CLK_R_C# HDMI_DATA2_C# 1 R5716 2 HDMI_DATA2_R_C#
0R0402-PAD 0R0402-PAD DDC_CLK_HDMI 1 10 DDC_CLK_HDMI
A A
DDC_DATA_HDMI 2 9 DDC_DATA_HDMI
3 8

HPD_HDMI_CON 4 7 HPD_HDMI_CON

HDMI_CEC 5 6 HDMI_CEC <Corrre Desiiign>

L05ESDL5V0NA--4-GP Wistron Corporation

075.00550.0071 21F,,, 88, Sec...1, HsiiinTai W u Rd...,,,Hsiiichih,

Eletro-XTechnical Eletro-XTechnical
2ND = 75.01043.073 Taiiipeiii Hsiiien 221,,, Taiiiwan,,, R.O.C...

EMI TEST Title

HDMI
Siize Document Number Rev
A2
LV115 SKL-U -1
Date: Monday,,, Aprrriill25, 2016 Sheet 57 off 102
5 4 3 2 1
 5 4 3 2 1

SSID = SATA 5V_S0_HDD

HDD1

AFTP6001 1 HDD_CON_P1 P1 V33 16 16

AFTP6002 1 HDD_CON_P2 P2 V33 17 17
16 DEVSLP0_HDD_CON 1 R6002 2HDD_CON_P3 P3 V33
R6001 0R0402-PAD ED6001
1 2 5V_S0_HDD P7 V5
5V_S0

Eletro-XTechnical
0R0805-PAD P8 V5 8520B_SATA_TXP0_C 1 10 8520B_SATA_TXP0_C
P9 V5
C6005 C6006 C6007 8520B_SATA_TXN0_C 2 9 8520B_SATA_TXN0_C

2 1

2 1

2 1
SC10U25V5KX--L-GP SCD1U16V2KX--L-GP SC18P50V2JN--1-GP AFTP6003 1 HDD_CON_P13 P13 V12 S1 3 8
AFTP6004 GND
DY 1 HDD_CON_P14 P14 V12
GND S4
8520B_SATA_RXN0_C
AFTP6005 1 HDD_CON_P15 P15 V12 S7 8520B_SATA_RXN0_C 4 7
GND
GND P4
E P5 8520B_SATA_RXP0_C 5 6 8520B_SATA_RXP0_C E
SCD01U50V2KX--L-GP 8520B_SATA_TXP0_C GND
2 1C6001 S2 TX+ P6
16 SATA_TX_CPU_P0 8520B_SATA_TXN0_C GND
SCD01U50V2KX--L-GP 2 1C6002 S3 TX- P10
16 SATA_TX_CPU_N0 GND
P12 L05ESDL5V0NA--4-GP
GND
SCD01U50V2KX--L-GP 2 1C6004 8520B_SATA_RXP0_C S6 RX+ R6008
16 SATA_RX_CPU_P0 SCD01U50V2KX--L-GP 2 1C6003 8520B_SATA_RXN0_C S5 RX- DAS/DSS P11 DAS1 2
16 SATA_RX_CPU_N0 075.00550.0071
SATA_HDD 0R0402-PAD
SKT--SATA7P-15P-195--GP
2ND = 75.01043.073
022.10014.0101

3D3V_S0 5V_S0 3D3V_S0 1ST = 022.10014.0101

2ND = 022.10014.0131
1

1
1

R6005 R6006 R6007

100KR2J--1-GP 100KR2J--1-GP 47KR2J--2-GP
DY DY DY
2

2
3D3V_S0
ODD_PW RGT# SATA_ODD_DA#_C SATA Zero Power ODD
SUPPORT ZERO SATA ODD
5V_S0

El
PG6001 1 2 GAP-CLOSE-PWR--6--GP
1

2
1
6

R6009 RN6001 R6004

Q6001 DY 0R2J--2-GP SRN10KJ--5-GP PG6002 1 2 GAP-CLOSE-PWR--6--GP ODD_PWR_5V_IN 1 2 0R0805-PAD ODD_PW R_5V
2N7002KDW--GP
D DY U6001 Currentlimit D
84.2N702.A3F DY
2

C6008 PG6003 1 2 GAP-CLOSE-PWR--6--GP

Active High
1

3
4

2 1
2nd = 075.063D1.007C SC10U25V5KX--GP
OC# 5
ODD 4 EN OUT#6 6 typ =>2A
SATA_ODD_DA# 16 3 IN#3 OUT#7 7

et
2 IN#2 OUT#8 8 100 mil
1 GND GND 9
SATA_ODD_DA# SATA_ODD_DA#
19 SATA_ODD_PWRGT SATA_ODD_PW RGT
G548A1F51U--GP
DY C6009
SATA_ODD_PWRGT GPIO setting change to NC

2 1
SC1U10V2KX--1GP
2016/4/21 74.00548.A79 ODD

ro
2015/10/3
Change Switch IC to 74.00548.A79

-X
ODD_PWR_5V
Need check PIN Define
ODD1

P2 P4 SATA_ODD_DA#_C
+5V MD
P3 P1 SATA_ODD_PRSNT# SATA_ODD_PRSNT# 16
+5V DP
C ODD14 C

1
S1
SATA_TX_CPU_N1 C6016 2 SCD01U50V2KX--L-GP SATA_TX_CPU_N1_C2 S3 GND S4 R6003

Te
SATA_TX_CPU_P1 C6017 1 A- GND S7 10KR2J--3-GP
ODD14 2 SCD01U50V2KX--L-GP SATA_TX_CPU_P1_C2 S2
ODD14 A+ GND P5
GND P6
DY

2
SATA_RX_CPU_N1 C6014 1 2 SCD01U50V2KX--L-GP SATA_RX_CPU_N1_C2 S5 GND 14
SATA_RX_CPU_P1 C6015 1 2 SCD01U50V2KX--L-GP SATA_RX_CPU_P1_C2 S6 B- GND 15
B+ GND
ODD14 NP1
NP2 NP1
NP2
SKT--SATA7P-6P-123--GP
22.10300.H81 ED6002

ch
ODD14 SATA_TX_CPU_P1_C2 1 10 SATA_TX_CPU_P1_C2
1ST = 22.10300.H81 SATA_TX_CPU_N1_C2 2 9 SATA_TX_CPU_N1_C2 8
2ND = 22.10300.H31 3

SATA_RX_CPU_N1_C2 4 7 SATA_RX_CPU_N1_C2
OAD1 3RD = 22.10300.H61
SATA_RX_CPU_P1_C2 5 6 SATA_RX_CPU_P1_C2
ODD15 14
16SATA_TX_CPU_P1 ODD15 SCD01U50V2KX--L-GP 2 1C6010 SATA_TX_CPU_P1_C1 12
16 SATA_TX_CPU_N1 SCD01U50V2KX--L-GP 2 1C6011 SATA_TX_CPU_N1_C1 11 L05ESDL5V0NA--4-GP

ni
ODD15 10
16 SATA_RX_CPU_N1 SCD01U50V2KX--L-GP 2 1C6012SATA_RX_CPU_N1_C1 9
16 SATA_RX_CPU_P1 ODD15 SCD01U50V2KX--L-GP 2 1 C6013SATA_RX_CPU_P1_C1 8 075.00550.0071
7
16 SATA_ODD_PRSNT# R6010 1 2 0R2J--2-GP SATA_ODD_PRSNT#_ODD15 6 ODD15
SATA_ODD_DA#_C 5
2ND = 75.01043.073
B DY 4 B
ODD_PW R_5V 3 LV115

ca
2

1
13

ACES-CON12--21--GP-U

20.K0422.012
1ST = 20.K0422.012

l
2ND = 20.K0391.012

A A

<Corrre Desiiign>

Wistron Corporation
21F,,, 88, Sec...1, HsiiinTai W u Rd...,,,Hsiiichih,

Eletro-XTechnical Eletro-XTechnical
Taiiipeiii Hsiiien 221,,, Taiiiwan,,, R.O.C...

Title

SATA IF_HDD/ODD
Siiize Document Number Rev
A2
LV115 SKL-U -1
Date: Monday,,, Aprrriill25, 2016 Sheet 60 off 102
5 4 3 2 1
 5 4 3 2 1

3D3V_S5 3D3V_WLAN

AOAC
Q6103 3D3V_S0 3D3V_WLAN 3D3V_WLAN Eletro-XTechnical

1
AO3413L-GP

100KR2J--1-GP
C6111 S D 1 R6121 2
R6102

SCD1U16V2KX--L-GP
2 1
AOAC 84.03413.B31 0R0603-PAD

1
AOAC C6112 C6113 C6110

SCD1U16V2KX--L-GP

SC1U10V2KX--L1-GP
10/16 R6121 原
NON_AOAC, 改
原
DUMMY PAD

SC10U6D3V3MX--GP
2

2
D D
WLAN_PWRON#_C 10/20 R6121 改
原
NON_AOAC DY

1
AOAC R6125 AOAC Change to 100K (TBC)

1
10KR2J--3-GP
Q6101 R6126

2
3 WLAN_PWRON#
24 WLAN_PWRON 1 R1 100KR2J--1-GP
2

SB

2
R2
LTC024EUB--FS8-GP
84.00024.A1K
1
100KR2J--1-GP

DY
R6127 AOAC
2

3D3V_WLAN

El
W LAN1

76 76 77 77
74 3_3VAUX GND 75
72 3_3VAUX RESERVED#73 73
70 RESERVED#70 RESERVED#71 71

et
68 GND 69
66
RESERVED#68
RESERVED#66 RESERVED#67/2ND_LANE_PERN1 67 06/27 WLan1 不
62.10043.I91, 此
待 待 1ST 062.10007.0291 , 2nd 062.10007.0251
64 GPIO0_NFC_RESET#/MGPIO7 RESERVED#65/2ND_LANE_PERP1 65
62 NFC_I2C_IRQ/MGPIO5 GND 63
60 NFC_I2C_SM_CLK RESERVED#61/2ND_LANE_PETN1 61
58 NFC_I2C_SM_DATA RESERVED#59/2ND_LANE_PETP1 57 59
24 WIRELESS_EN 56 W _DISABLE#1 GND
C 1 R6110 2 BT_DISABLE#_R 54 PCIE_WAKE#_1 1 R6108 2 C
19 BT_DISABLE#
0R0402-PAD RESERVED#54/W_DISABLE#2 PEW AKE0# 55 0R0402-PAD
WLAN_PCIE_WAKE# 24
17,24,31,40,68,76 PLT_RST# 52 PERST0# CLKREQ0# 53 PCIE_CLK_W LAN_REQ#_R

ro
1 2 PCH_SUSCLK_KBC_R 50
18 PCH_SUSCLK_KBC R6109 0R2J--2-GP SUSCLK_32KHZ GND 51
DY E51_RXD_R
48 COEX1 REFCLKN0 49 PEG_CLK1_CPU# 18
46 COEX2 REFCLKP0 47 PEG_CLK1_CPU 18
E51_TXD_R 44 COEX3 GND 45
18 CL_CLK DY1 2 CL_CLK_WLAN_R 42 CLINK_CLK PERN0 43 PCIE_RX_CPU_N5 16
R6111 02R2J--2-GP
DY1 R6112 CL_DATA_WLAN_R 40 CLINK_DATA PERP0 41 PCIE_RX_CPU_P5 16
18 CL_DATA 02R2J--2-CGLPP_RST_WLAN#_R
18 CL_RST#
DY1 38 CLINK_RESET GND 39
R6113 0R2J--2-GP 36 UART_CTS 37 PCIE_TX_CON_N5 16
PETN0
34 UART_RTS PETP0 35 PCIE_TX_CON_P5 16
32 UART_TX GND 33

-X
22 UART_RX SDIO_RESET 23
20 SDIO_W AKE 21
18
UART_W AKE
GND SDIO_DAT3 19 06/05 Wlan_DP_MLDIR 此
, 待
線 ,將
此
16 WLAN_DP_MLDIR 1 2
LED#2 SDIO_DAT2 17 R6114 0R2J--2-GP
14 PCM_OUT SDIO_DAT1 15 DY
12 PCM_IN SDIO_DAT0 13
10 PCM_SYNC SDIO_CMD 11
8 PCM_CLK SDIO_CLK 9
6 GND 7

Te
LED#1
4 3_3VAUX USB_D- 5 USB_CPU_PN7 16
2 3_3VAUX NGFF_KEY_E_75P USB_D+ 3 USB_CPU_PP7 16
AFTP6103 1
GND 1
NP2 NP2 NP1 NP1
AFTP6104 1 PCIE_WAKE#_1
AFTP6105 1 BT_DISABLE#_R
SKT--MIINII67P-2--GP-U AFTP6106 1 PCIE_CLK_WLAN_REQ#_R
3D3V_WLAN AFTP6107 PEG_CLK1_CPU#
1
1

2
AFTP6108 1 PEG_CLK1_CPU
62.10043.I91 ED6101 AFTP6109
AFTP6110
1 WIRELESS_EN
PLT_RST#
ESDR0502BT1G--GP 1

ch
1st = 62.10043.I91 83.00502.BA1
B

AFTP6111 1 PCIE_RX_CPU_N5
2nd = 062.10003.0B11 DY
3

AFTP6112 1 PCIE_RX_CPU_P5
R1

Q6102
3rd = 062.10007.0511
LTC015TEBFS8TL-GP
B
4TH = 062.10007.0371 ESD RESERVED B
84.00015.B1H AFTP6115 1 PCIE_TX_CON_N5
AFTP6116 1 PCIE_TX_CON_P5
E

2ND = 84.00015.01H
PCIE_CLK_WLAN_REQ#_R
CLKREQ_PCIE#1 18

ni
DY AFTP6119 1 CL_CLK_WLAN_R
1 2
R6123 DY 0R2J--2-GP
E51_RXD_R R6119 1
R6120 1
DY 2 0R2J--2-GP
2 0R2J--2-GP
E51_RXD 24 AFTP6120
AFTP6121
1 CL_DATA_WLAN_R
E51_TXD_R E51_TXD 24 1 CL_RST_WLAN#_R

R6122 1
DY 2 0R2J--2-GP
E51_TXD_R AFTP6113 1 E51_RXD_R
E51_RXD_R R6124 1 DY 2 0R2J--2-GP AFTP6114 1 E51_TXD_R

ca
06/05 E51_RXD_R & E51_TXD_R 此
?
原
10/8 84.00115.E1K EOL(原 有
SIT有 , 加
將
,SIV將 84.00015.01H) AFTP6122 1 E51_RXD
AFTP6123 1 E51_TXD

AFTP6124 1 3D3V_WLAN

l
A A

<Corrre Desiiign>

Wistron Corporation
21F,,, 88, Sec...1, HsiiinTai W u Rd...,,,Hsiiichih,

Eletro-XTechnical Eletro-XTechnical
Taiiipeiii Hsiiien 221,,, Taiiiwan,,, R.O.C...

Title

NGFF_WLAN CONN
Siiize Document Number Rev
A2
LV115 SKL-U -1
Date: Monday,,, Aprrriill25, 2016 Sheet 61 off 102
5 4 3 2 1
 5 4 3 2 1

Test point
CHARGER LED
Eletro-XTechnical
5V_AUX_S5
LED1
ORG
Q6401 3 Orange

R6415 1 5V_AUX_S5_R 1 R6411 2

4 3 DC_BATFULL#_Q 1 2 330R2J--3-GP DC_BATFULL#_R 0R0402-PAD
2
Yellow Green
83.12222.070
24 DC_BATFULL
5 2
CHARGE_LED 24
GREEN
LED-OYG-1-GP 1ST = 83.12222.070
6 1

CHARGE_LED
LED14 2ND = 83.00326.B70
D D
2N7002KDW--GP
ORG LED2
84.2N702.A3F
1
2

2nd = 075.063D1.007C CHARGE_LED#_R 3 Orange

RN6401 1 5V_AUX_S5_R AFTP6409 1

SRN100KJ--6-GP DC_BATFULL#_R 2
Yellow Green

R6414 GREEN 83.12222.070

CHARGE_LED#_Q 1 2330R2J--3-GP CHARGE_LED#_R LED-OYG-1-GP
4
3

1ST = 83.12222.070
LED15 AFTP6401
2ND = 83.00326.B70 1 5V_AUX_S5
AFTP6402 1 DC_BATFULL
AFTP6403 1 CHARGE_LED

AFTP6406 1

El
et
C C

ro
SATA LED 3D3V_S0

-X
1

R6418
120R2J--2-GP
2

LED3

K A SATA_LED#_D

Te
16 SATA_LED#

LED--G--107-GP--U 1ST = 83.00270.B70

LV114
2ND = 83.02721.H70
83.00270.B70
LED4

K A

ch
LED--G--107-GP--U 1ST = 83.00270.B70
LV115
2ND = 83.02721.H70
83.00270.B70
B B

ni
ca
l
A A

<Corrre Desiiign>

Wistron Corporation
21F,,, 88, Sec...1, HsiiinTai W u Rd...,,,Hsiiichih,

Eletro-XTechnical Eletro-XTechnical
Taiiipeiii Hsiiien 221,,, Taiiiwan,,, R.O.C...

Title

LED Board&Power Button

Siiize Document Number Rev
A2
LV115 SKL-U -1
Date: Monday,,, Aprrriill25, 2016 Sheet 64 off 102
5 4 3 2 1
 5 4 3 2 1

Internal KeyBoard Connector

KROW[0..7] 24

3D3V_S5
KCOL[0..17] 24

For 14" and 15" CONN

SSID = Touch.Pad
CAP_LED_3V3 R6512 1 2 330R2J--3-GP DY

KBB1
33
1 CAP_LED_3V3
3D3V_S0 3D3V_S0 TouchPad
Eletro-XTechnical
NUM_LED_C 1 R6502
2 CAP_LED_C NUM_LED_3V3 R6510 1 2 330R2J--3-GP NUM_LED_3V3 1 AFTP6543 1 2
3 KCOL15 CAP_LED_3V3 R6511 1 2 330R2J--3-GP AFTP6542 0R0402-PAD
CAP_LED_C 1 4 KCOL10
CAP_LED_3V3 1 AFTP6541 5 KCOL11
KCOL15 1 AFTP6540 6 KCOL14 TouchPad
KCOL10 1 AFTP6501 7 KCOL13
KCOL11 1 AFTP6502 8 KCOL12 C6502 C6501
KCOL14 1 AFTP6503 9 KCOL3
DY

SCD1U16V2KX--L-GP
2 1

2 1
KCOL13 1 AFTP6504 10 KCOL6

SCD1U25V2KX--L-GP
1
2
KCOL12 1 AFTP6505 11 KCOL8 R6505 2 1 100R2J--L-GP KBB_DEFINE1_R 24
D KCOL3 1 AFTP6506 12 KCOL7 RN6501 D
KCOL6 1 AFTP6507 13 KCOL4 SRN10KJ--5-GP TP2
KCOL8 1 AFTP6508 14 KCOL2
KCOL7 1 AFTP6509 15 KROW0 R6503
KCOL4
DY 8
1 AFTP6510 16 KCOL1 KBB1_DEFINE1 R6506 2 1 100R2J--L-GP KBC_PWRBTN# 24,66 13,18 PCH_SMBDATA 1 2 0R2J--L-GP TP_SW_R_CON 6

4
3
KCOL2 1 AFTP6511 17 KCOL5 1 R6504 2 0R2J--L-GP TP_SW_L_CON 5
13,18 PCH_SMBCLK
KROW0 AFTP6512 18 KROW3 RN6502
KCOL1
1
DY DY 4
1 AFTP6513 19 KROW2 24 TPDATA TPDATA 2 3 TP_DATA 3

2
KCOL5 1 AFTP6514 20 KCOL0 24 TPCLK TPCLK 1 4 TP_CLK 2

1
KROW3 1 AFTP6515 21 KROW5 L6501 C6508 C6507

VARISTOR-5D5V-29--GP
KROW2 1 AFTP6516 22 KROW4 SRN33J--5-GP--U 1
KCOL0 1 AFTP6517 23 KCOL9 SC1KP50V2KX--L--1--GP SC1KP50V2KX--L--1--GP 7

2
KROW5 1 AFTP6518 24 KROW6
KROW4 1 AFTP6519 25 KROW7 C6506 C6505

1
KCOL9 AFTP6520 26 KROW1 DY DY
1 DY

SC100P50V2JN-3GP

SC100P50V2JN-3GP
2 1

2 1
KROW6 1 AFTP6521 27 KCOL16 1 FOX--CON6--6--GP
KROW7 1 AFTP6522 28 KCOL17 1 AFTP6530
AFTP6523 29 NUM_LED_3V3 AFTP6529
020.K0048.0006
KROW1 1 30 NUM_LED_C
AFTP6524 31 KBB1_DEFINE1 1ST = 020.K0206.0006
1 32 KBB1_DEFINE2 R6507 2 1 0R0402-PAD
AFTP6525 34 2ND = 20.K0841.006
AFTP6501~AFTP6525 PTWO-CON32--3--GP 020.K0223.0032
CLOSE keyboard connector
1ST = 020.K0223.0032
2ND = 020.K0233.0032

TP_SW_R

El
1 TP_DATA
AFTP6536 1 TP_CLK
Q6501 Q6502 AFTP6537
G G TPSW 41 TPSW 51
24 CAP_LED 24 NUM_LED SW-TACT-124-GP SW--TACT--124-GP

5
D CAP_LED_C D NUM_LED_C
1 TouchPad 2 1 TP_SW_R 2 1
KCOL3 EC6501 1 AFTP6533
S S 2SC100P50V2JN-3GP
Notice:ZZ.2N702.J3101 Notice:ZZ.2N702.J3101 KCOL4 EC6502 1
KCOL6 EC6503 1
2SC100P50V2JN-3GP 62.40078.001 62.40078.001
2N7002K--2-GP 2N7002K--2-GP 2SC100P50V2JN-3GP 1
84.2N702.J31 84.2N702.J31 KCOL7 EC6504 1 2SC100P50V2JN-3GP AFTP6532 4 3 4 3
2ND = 84.2N702.031 2ND = 84.2N702.031 KCOL8 EC6505 1 2SC100P50V2JN-3GP
3rd = 84.2N702.W31 3rd =84.2N702.W31 LV114 LV115

6
et
1ST = 62.40078.001 1ST = 62.40078.001
RN6504
TP_SW_R_CON 2ND = 62.40009.D71
1 4 2ND = 62.40009.D71
For EMC Recommend TP_SW_L_CON 2 3
3RD = 62.40056.041
C
3RD = 62.40056.041 C

SRN100J--3-GP

ro
TP_SW_L

TPSW 42 TPSW 52
SW--TACT-124--GP SW--TACT-124--GP

5
2 1 TP_SW_L 2 1

62.40078.001 62.40078.001

-X
4 3 4 3

LV114 LV115

6
1ST = 62.40078.001 1ST = 62.40078.001
2ND = 62.40009.D71 2ND = 62.40009.D71
3RD = 62.40056.041 3RD = 62.40056.041

Te
ch
B B

ni
ca
l
A A

Eletro-XTechnical Eletro-XTechnical
<Core Desiiign>

Wistron Corporation
21F,,, 88,,,Sec.1,,, Hsiiin Taiii W u Rd., Hsiiichiiih,,,
Taipei Hsiiien 221, Taiwan, R...O...C...

Title

Key Board&Touch Pad

Siiize Document Number Rev
A1
LV115 SKL-U -1
Date: Monday,,, Apriiilll 25, 2016 Sheet 65 off 102
5 4 3 2 1
 5 4 3 2 1

IO BD Device
Item Device
1
2 Eletro-XTechnical
3
4

D D

IO BD connector
3D3V_S0
IOCN1
13
1

24 KBC_NOVO_BTN# 2 1 HP_OUT_R
AFTP6601 HP_OUT_R 27
3 1 HP_OUT_L
4 AFTP6602 HP_OUT_L 27 3D3V_S0
5 1 SLEEVE SLEEVE 27
2

27 HP_OUT_R
6 AFTP6603 1 RING2
L6602 27 HP_OUT_L RING2 27
VARIISTOR--5D5V-29--GP

27 HP_DET# 7 AFTP6604 1 HP_DET#

1
8 HP_DET# 27
AFTP6605
Audio Jack 27 SLEEVE 9
10 1 ALC_AGND
C6604
SCD1U25V2KX-L--GP

2
11 AFTP6606
27 RING2
1

12
14

STAR-CON12--1--GP 1ST = 020.K0125.0012

El
ALC_AGND 020.K0125.0012 2ND = 020.K0049.0012

3RD = 020.K0190.0012

5V_S5

et
IO2
21
1

3D3V_S0 2
3
4
C 5 C
16 USB_OC2#
KBC_NOVO_BTN# 6 5V_S5

ro
7
8
USB_CPU_PN2 9
16 USB_CPU_PN2
USB_CPU_PP2 10
16 USB_CPU_PP2
11 C6603

2 1
12 SCD1U25V2KX--L-GP
13
27 HP_OUT_R
14
DY
27 HP_OUT_L
27 HP_DET# 15
16

-X
27 SLEEVE 17
18
27 RING2 19
20
22

ACES-CON20--29--GP-U
20.K0637.020
ALC_AGND
DY

Te
PWR BTN BD connector

ch
B B

Modified Pin Define and PN 20151208

ni
PW1
6

4
3 KBC_PWRBTN# 1
2 AFTP6607

ca
24,65 KBC_PWRBTN# 1

PTWO-CON4-9-GP-U1
1

G6601 G6602 L6601

VARIISTOR--5D5V-29--GP

20.K0382.004

GAP-OPEN GAP-OPEN 1ST = 20.K0382.004

2

l
1

2ND = 020.K0150.0004

3D3V_AUX_S5
HALL2

LID_CLOSE# R6601 1 2 100R2J--2-GP LID_CLOSE#_2 3

A 24 LID_CLOSE# OUT A
R6610 2 1 3D3V_AUX_S5_HALL 2
0R0402-PAD VDD
1
VSS
D6601
A K C6610 C6601
2 1

SCD1U16V2KX--3GP SCD047U16V2KX--1-GP C6602 S--5712ACDL1-M3T1U--GP

2 1

2 1

RB551V30-GP DY DY SCD1U16V2KX--L-GP 74.05712.0BB <Corrre Desiiign>

83.R5003.H8H
2nd = 83.R5003.T8F 1ST = 74.05712.0BB
DY 2ND = 074.08132.007B Wistron Corporation
21F,,, 88, Sec...1, HsiiinTai W u Rd...,,,Hsiiichih,
3RD = 074.09247.009B
Eletro-XTechnical Eletro-XTechnical
Taiiipeiii Hsiiien 221,,, Taiiiwan,,, R.O.C...

Title

IO Board Connector
Siize Document Number Rev
A2
LV115 SKL-U -1
Date: Monday,,, Aprrriill25, 2016 Sheet 66 off 102
5 4 3 2 1
 5 4 3 2 1

Main Func = Debug

Eletro-XTechnical

D D

Debug Connector

El
3D3V_S0
DB1
11

et
1

R6801 1
DY 0R2J-2-GP LPC_AD0_R
18,24 LPC_AD0 R6802 1
DY 2 2
DY 2 0R2J-2-GP LPC_AD1_R 3
18,24 LPC_AD1 0R2J-2-GP LPC_AD2_R
R6803 1 DY

ro
C
18,24 LPC_AD2 2 4 C
R6804 1 DY 2 0R2J-2-GP LPC_AD3_R 5
18,24 LPC_AD3
R6805 1 2 0R2J-2-GP LPC_FRAME#_R 6
18,24 LPC_FRAME#
17,24,31,40,61,76 PLT_RST# 7
8

-X
18 CLK_PCI_DB 9
10
12
ACES-CON10-1-GP-U1

Te
20.F0714.010
DY

ch
B B

ni
ca
l
<Core Design>

Wistron Corporation
A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, A
Taipei Hsien 221, Taiwan, R.O.C.

Title

Eletro-XTechnical DebugEletro-XTechnical
connector
Size Document Number Rev
A4
LV115 SKL-U -1
Date: Monday, April 25, 2016 Sheet 68 of 102
5 4 3 2 1
 5 4 3 2 1

PCIE lane maping GPU1A 1 OF 7

CPU >> GPU Eletro-XTechnical

1 0
2 1 16 PEG_TX_GPU_P0
AF30
AE31
PCIE_RX0P PCIE_TX0P
AH30 PEG_RX_CON_P0 C7669 1
AG31 PEG_RX_CON_N0 C7670 1
2 SCD22U10V2KX--L1-GP PX
2 SCD22U10V2KX--L1-GP PX
PEG_RX_CPU_P0
PEG_RX_CPU_N0 PEG_RX_CPU_P0 16
16 PEG_TX_GPU_N0 PCIE_RX0N PCIE_TX0N PEG_RX_CPU_N0 16
3 2
2 SCD22U10V2KX--L1-GP PX PEG_RX_CPU_P1
D 4 3 16 PEG_TX_GPU_P1
16 PEG_TX_GPU_N1
AE29
AD28 PCIE_RX1P
PCIE_RX1N
PCIE_TX1P
PCIE_TX1N
AG29 PEG_RX_CON_P1 C7671 1
AF28 PEG_RX_CON_N1 C76721
2 SCD22U10V2KX--L1-GP PX PEG_RX_CPU_N1 PEG_RX_CPU_P1 16
PEG_RX_CPU_N1 16 D

AD30 AF27 PEG_RX_CON_P2 C7666 1 AF26 2 SCD22U10V2KX--L1-GP PX PEG_RX_CPU_P2

16 PEG_TX_GPU_P2 PCIE_RX2P PCIE_TX2P 2 SCD22U10V2KX--L1-GP PX PEG_RX_CPU_N2 PEG_RX_CPU_P2 16
AC31 PEG_RX_CON_N2 C7667 1
16 PEG_TX_GPU_N2 PCIE_RX2N PCIE_TX2N PEG_RX_CPU_N2 16

AC29 AD27 PEG_RX_CON_P3 C7668 1 2 SCD22U10V2KX--L1-GP PX PEG_RX_CPU_P3

16 PEG_TX_GPU_P3 PCIE_RX3P PCIE_TX3P 2 SCD22U10V2KX--L1-GP PX PEG_RX_CPU_N3 PEG_RX_CPU_P3 16
AB28 AD26 PEG_RX_CON_N3 C7673 1
16 PEG_TX_GPU_N3 PCIE_RX3N PCIE_TX3N PEG_RX_CPU_N3 16

AB30 AC25
PCIE_RX4P PCIE_TX4P
AA31 AB25
PCIE_RX4N PCIE_TX4N AC-Coupling Capacitor:
PCIe Gen1,Gen2 : 0.1uF
AA29 Y23
Y28
PCIE_RX5P PCIE_TX5P
Y24 PCIe Gen3 : 0.22uF
PCIE_RX5N PCIE_TX5N

Y30 AB27
PCIE_RX6P PCIE_TX6P
W 31 AB26
PCIE_RX6N PCIE_TX6N

3D3V_VGA_S0
W 29 Y27
PCIE_RX7P PCIE_TX7P

El
V28 Y26
PCIE_RX7N PCIE_TX7N

2
V30 W 24
NC#V30 NC#W 24 R7301
U31 W 23
NC#U31 NC#W 23
0R2J--2-GP
20141119_KAMUS
U29 V27 DY

1
NC#U29 NC#V27 R7602 DGPU_PWROK_G
T28 U26 19,24,85 DGPU_PWROK 2 1
NC#T28 NC#U26
0R0402-PAD

PCII EXPRESS IINTERFACE

et
T30 U24
NC#T30 NC#U24
R31 U23
NC#R31 NC#U23 Q7601
G
R29 T26
NC#R29 NC#T26 D
P28 T27 18 CLKREQ_PEG#0
C NC#P28 NC#T27 C
PX S

ro
Not ic e: ZZ .2N 70 2. J3 10 1
P30 T24
NC#P30 NC#T24 2N7002K--2-GP
N31 T23
NC#N31 NC#T23 84.2N702.J31
2ND = 84.2N702.031
N29
NC#N29 NC#P27
P27 3rd = 84.2N702.W31
M28 P26
NC#M28 NC#P26

PE_GPIO0 PE_GPIO0 = ATI_RST# M30

NC#M30 NC#P24
P24
L31 P23

-X
NC#L31 NC#P23
H dGPUmode
L29 M27
NC#L29 NC#M27
L IGPU K30
NC#K30 NC#N26
N26

H IGPU with BACO

CLOCK
1 R7604 2 0R0402-PAD CLK_PCIE_VGA_R AK30
18 PEG_CLK_CPU PCIE_REFCLKP
18 PEG_CLK_CPU# 1 R7605 2 0R0402-PAD CLK_PCIE_VGA#_R AK32
PCIE_REFCLKN Mars/Sun setting

Te
CALIIBRATIION
PX
Y22 PCIE_CALR_TX 1K69R2F--2-GP 2 1 R7622 0D95V_VGA_S0
PCIE_CALR_TX
PX PX 1 R7618
1KR2F--3-GP 2 1 R7601 PWRGOOD N10 AA22 PCIE_CALR_RX 1KR2F--3-GP 2
TEST_PG PCIE_CALR_RX

2 R7603 1 0R0402-PAD VGA_RST# AL27

20 DGPU_HOLD_RST# PERST#

JET--XT--S3--GP
C7609
DY SC47P50V2JN--3GP PX

ch
2 1

3D3V_VGA_S0
1

B PX support B
PE_GPIO0: VGA_RESET
PE_GPIO1: VGA_PowerEnable R7625
10KR2J--L-GP
DY DY
2

R7623 2 1 0R2J--2-GP

ni
2 D7601
19 PE_GPIO0
BAW56-5-GP
DY 3

17,24,31,40,61,68 PLT_RST# 1

ca
83.00056.Q11
1ST =83.00056.Q11
2ND = 75.00056.07D

l
A A

<Corrre Desiiign>

Wistron Corporation
21F,,, 88, Sec...1, HsiiinTai W u Rd...,,,Hsiiichih,

Eletro-XTechnical Eletro-XTechnical
Taiiipeiii Hsiiien 221,,, Taiiiwan,,, R.O.C...

Title

GPU(1/5) PEG
Siiize Document Number Rev
A2
LV115 SKL-U -1
Date: Monday,,, Aprrriill25, 2016 Sheet 76 off 102
5 4 3 2 1
 5 4 3 2 1

GPU1E 5 OF 7 GPU1G 7 OF 7

DPPOWER NC//DPPOWER

AA27 GND
AB24 GND
AB32 GND
GND
GND
A3
A30
AA13
1.8V and 0.95V for Clock resource AG15 NC_DP_VDDR#AG15
AG16 NC_DP_VDDR#AG16
AF16 NC_DP_VDDR#AF16
NC#AE11 AE11
NC#AF11 AF11
Eletro-XTechnical
AC24 GND
GND
AA16 NC#AE13 AE13
GND AG17 NC_DP_VDDR#AG17 NC#AF13 AF13
AC26 GND AB10 1D8V_VGA_S0 DPLL_PVDD DPLL_PVDD AG18 NC_DP_VDDR#AG18
AC27 GND
GND
AB15 NC#AG8 AG8
AD25 GND
GND
GND AB6 1 R7704 2
40mA AG19
NC_DP_VDDR#AG19
AF14 DP_VDDR
NC#AG10 AG10
AD32 GND GND AC9

1
AE27 GND GND AD6 0R0603-PAD C7713 C7711 SC1U10V2KX- C7710
AF32 GND GND AD8 SC10U6D3V3MX--L-GP -L1-GP SCD1U16V2KX--L-GP
D AG27 GND GND AE7 DY PX PX D

2
AH32 GND AG12 AG20 NC_DP_VDDC#AG20
K28 GND
GND
AH10 NC#AF6 AF6
GND AG21 NC_DP_VDDC#AG21 NC#AF7 AF7
K32 GND AH28 0D95V_VGA_S0 DPLL_VDDC DPLL_VDDC
GND AF22 NC_DP_VDDC#AF22 NC#AF8 AF8
L27 GND B10
M32 GND
GND
GND B12 1 R7705 2
32mA AG22
NC_DP_VDDC#AG22
AD14 DP_VDDC
NC#AF9 AF9
N25 GND GND B14
N27 GND GND B16 0R0603-PAD C7715 SC1U10V2KX- C7714
P25 GND GND B18 -L1-GP SCD1U16V2KX--L-GP

2 1

2 1
P32 GND B20 AG14
R27 GND
GND
B22 PX PX NC_DP_VSSR#AG14 NC#AE1 AE1
GND AH14 NC_DP_VSSR#AH14 NC#AE3 AE3
T25 GND B24 AM14
T32 GND
GND
B26 NC_DP_VSSR#AM14 NC#AG1 AG1
GND AM16 NC_DP_VSSR#AM16 NC#AG6 AG6
U25 GND B6 AM18
U27 GND
GND
B8 GPU1F 6 OF 7 NC_DP_VSSR#AM18 NC#AH5 AH5
GND AF23 NC_DP_VSSR#AF23 NC#AF10 AF10
V32 GND C1 AG23
W 25 GND
GND
C32 1V_VGACORE_S0_TOPAZ NC_DP_VSSR#AG23 NC#AG9 AG9
GND AM20 NC_DP_VSSR#AM20 NC#AH8 AH8
W 26 GND E28 AM22
W 27 GND
GND
F10 NC_DP_VSSR#AM22 NC#AM6 AM6
GND NC_VARY_BL AB11 Topaz only AM24 NC_DP_VSSR#AM24 NC#AM8 AM8
Y25 GND F12
Y32 GND
GND
F14 NC_DIGON AB12 AF19 NC_DP_VSSR#AF19 NC#AG7 AG7
GND AF20 NC_DP_VSSR#AF20 NC#AG11 AG11
GND F16 AE14
F18 DP_VSSR
GND
GND F2
F20

El
GND
F22 NC_UPHYAB_TMDPA_TX0N AL15
M6 GND
N13 GND
GND
F24 NC_UPHYAB_TMDPA_TX0P AK14 AF17 NC_UPHYAB_DP_CALR NC#AE10 AE10
GND
N16 GND F26
N18 GND
GND NC_UPHYAB_TMDPA_TX1N AH16
F6
N21 GND GND
GND
F8 NC_UPHYAB_TMDPA_TX1P AJ15
GND JET--XT--S3--GP
P6 GND G10 PX
GND
G27 NC_UPHYAB_TMDPA_TX2N AL17
P9 GND
R12 GND
GND
G31 NC_UPHYAB_TMDPA_TX2P AK16
GND
R15 GND G8
GND NC_UPHYAB_TMDPA_TX3N AH18

et
R17 GND H14
R20 GND
GND
H17 NC_UPHYAB_TMDPA_TX3P AJ17
GND
T13 GND H2
T16 GND
GND
H20 NC_TXOUT_L3P AL19
T18 GND
GND NC_TXOUT_L3N AK18
GND H6
T21 GND GND J27
T6 GND J31 TMDP
GND
C U15 GND GND K11 C
U17 GND K2
GND NC_UPHYAB_TMDPB_TX0N AH20

ro
U20 GND K22
U9 GND
GND
K6 NC_UPHYAB_TMDPB_TX0P AJ19
GND
V13 GND
V16 GND NC_UPHYAB_TMDPB_TX1N AL21
V18 GND NC_UPHYAB_TMDPB_TX1P AK20
Y10 GND
Y15 GND NC_UPHYAB_TMDPB_TX2N AH22
Y17 GND NC_UPHYAB_TMDPB_TX2P AJ21
Y20 GND
R11 GND VSS_MECH1 TP7701 NC_UPHYAB_TMDPB_TX3N AL23
A32 1
VSS_MECH AM1 NC_UPHYAB_TMDPB_TX3P AK22

-X
T11 GND VSS_MECH VSS_MECH2 1 TP7740
VSS_MECH3
AA11 GND 1 TP7730
VSS_MECH AM32 NC_TXOUT_U3P AK24
M12 GND
N11 GND NC_TXOUT_U3N AJ23
V11 GND

JET--XT--S3--GP JET--XT--S3--GP
PX PX

Te
1V_VGACORE_S0 1V_VGACORE_S0_TOPAZ

R7706
1 2

0R3J--0-U--GP

ch
PX_TOPAZ C7716 SC1U10V2KX-
-L1-GP
2 1

PX_TOPAZ
B B

ni
ca
l
A A

<Corrre Desiiign>

Wistron Corporation
21F,,, 88, Sec...1, HsiiinTai W u Rd...,,,Hsiiichih,

Eletro-XTechnical Eletro-XTechnical
Taiiipeiii Hsiiien 221,,, Taiiiwan,,, R.O.C...

Title

GPU (2/5) DIGITALOUT

Siiize Document Number Rev
A2
LV115 SKL-U -1
Date: Monday,,, Aprrriill25, 2016 Sheet 77 off 102
5 4 3 2 1
 5 4 3 2 1

GPU1C 3 OF 7

GDDR5//DDR3 GDDR5//DDR3
81 DQA0_[31..0]
DQA0_0 K27 K17

Eletro-XTechnical
DQA0_0 MAA0_0 MAA0 81,83
DQA0_1 J29 J20
DQA0_2 DQA0_1 MAA0_1 MAA1 81,83
H30 H23
DQA0_3 DQA0_2 MAA0_2 MAA2 81,83
H32 G23
DQA0_4 DQA0_3 MAA0_3 MAA3 81,83
G29 G24
DQA0_5 DQA0_4 MAA0_4
F28 H24 MAA4 81,83
DQA0_5 MAA0_5
DQA0_6 F32 J19 MAA5 81,83
DQA0_6 MAA0_6
DQA0_7 F30 K19 MAA6 81,83
DQA0_7 MAA0_7
DQA0_8 C30 G20
DQA0_8 MAA0_8 MAA7 81,83
DQA0_9 F27 L17
DQA0_9 MAA0_9 MAA13 81,83
DQA0_10 A28
DQA0_10 MAA15 81,83
DQA0_11 C28 J14
DQA0_12 DQA0_11 MAA1_0
D E27 K14 D
DQA0_13 DQA0_12 MAA1_1 MAA8 81,83
G26 J11
DQA0_14 DQA0_13 MAA1_2 MAA9 81,83
D26 J13
DQA0_15 DQA0_14 MAA1_3
F25 H11 MAA10 81,83
DQA0_15 MAA1_4
DQA0_16 A25 G11 MAA11 81,83
DQA0_16 MAA1_5
DQA0_17 C25 J16 MAA12 81,83
DQA0_18 DQA0_17 MAA1_6
E25 L15
DQA0_18 MAA1_7 MAA_BA2 81,83
DQA0_19 D24 G14
DQA0_20 DQA0_19 MAA1_8 MAA_BA0 81,83 TP7801
E23 L16 VSSRHA 1

MEMORYIINTERFACE
DQA0_20 MAA1_9 MAA_BA1 81,83
DQA0_21 F23
DQA0_21 MAA14 81,83
DQA0_22 D22 E32
DQA0_22 W CKA0_0 DQMA0 81
DQA0_23 F21 E30
DQA0_23 W CKA0#_0 DQMA1 81
DQA0_24 E21 A21
DQA0_24 W CKA0_1 DQMA2 81
DQA0_25 D20 C21
DQA0_25 W CKA0#_1 DQMA3 81
DQA0_26 F19 E13
DQA0_27 DQA0_26 W CKA1_0
A19 D12 DQMA4 83
DQA0_28 DQA0_27 W CKA1#_0
D18 E3
Please MVREF drivers and Caps close to ASIC DQA0_29 F17
DQA0_28 W CKA1_1
F4
DQMA5 83
DQMA6 83
DQA0_30 DQA0_29 W CKA1#_1
A17
DQA0_30 DQMA7 83
DQA0_31 C17 H28
83 DQA1_[31..0] DQA0_31 EDCA0_0 QSAP_0 81
E17 C27
DDR3/GDDR3 Memory Stuff Option(JET/TOPAZ) DQA1_0
DQA1_1 D16
DQA1_0 EDCA0_1
A23
QSAP_1 81
DQA1_1 EDCA0_2 QSAP_2 81
DQA1_2 F15 E19
DQA1_3 DQA1_2 EDCA0_3 QSAP_3 81
A15 E15
DQA1_3 EDCA1_0
GDDR5 GDDR3 DDR3 QSAP_4 83

El
DQA1_4 D14 D10
DQA1_4 EDCA1_1
DQA1_5 F13 D6 QSAP_5 83
DQA1_5 EDCA1_2
DQA1_6 A13 G5 QSAP_6 83
DQA1_6 EDCA1_3
MVDDQ 1.5V 1D35V 1.5V DQA1_7 C13
DQA1_7 QSAP_7 83
DQA1_8 E11 H27
DQA1_8 DDBIA0_0 QSAN_0 81
DQA1_9 A11 A27
DQA1_9 DDBIA0_1 QSAN_1 81
Ra 40.2R 40.2R 40.2R DQA1_10 C11
DQA1_10 DDBIA0_2
C23
QSAN_2 81
DQA1_11 F11 C19
DQA1_12 DQA1_11 DDBIA0_3 QSAN_3 81
A9 C15
DQA1_12 DDBIA1_0
Rb 100R 100R 100R DQA1_13 C9
DQA1_13 DDBIA1_1
E9 QSAN_4 83

et
DQA1_14 F9 C5 QSAN_5 83
DQA1_14 DDBIA1_2
DQA1_15 D8 H4 QSAN_6 83
DQA1_15 DDBIA1_3
DQA1_16 E7
DQA1_16 QSAN_7 83
DQA1_17 A7 L18
1D5V_VGA_S0 1D5V_VGA_S0 DQA1_17 ADBIA0 ODTA0 81
DQA1_18 C7 K16 ODTA1
DQA1_18 ADBIA1 83
DQA1_19 F7
DQA1_20 DQA1_19
A5 H26
DQA1_20 CLKA0 CLKA0 81
1

C DQA1_21 E5 H25 C
DQA1_21 CLKA0# CLKA0#
R7817 Ra R7830 DQA1_22 C3
DQA1_22
81
Ra

ro
40D2R2F--GP 40D2R2F--GP DQA1_23 E1 G9
DQA1_23 CLKA1 CLKA1 83
DQA1_24 G7 H9
PX PX DQA1_25 G6
DQA1_24 CLKA1# CLKA1# 83
2

MVREFDA MVREFSA DQA1_26 DQA1_25

G1 G22
DQA1_27 DQA1_26 RASA0# RASA0# 81
G3 G17
DQA1_27 RASA1#
1
1

DQA1_28 J6 RASA1# 83
PX PX DQA1_28
Rb R7818
100R2F--L1-GP--U SC1U10V2KX--L1-GP
Rb R7814
100R2F--L1-GP--U SC1U10V2KX--L1-GP
DQA1_29 J1
J3
DQA1_29 CASA0#
G19
G16
CASA0# 81
DQA1_30 DQA1_30 CASA1# CASA1# 83
12

12

C7805 C7801 DQA1_31 J5

PX PX DQA1_31
CSA0#_0 H22

-X
CSA0#_0 81
2

MVREFDA K26 MVREFDA CSA0#_1 J22

MVREFSA J26 MVREFSA Modify 20151007
Jet Setting CSA1#_0 G13 CSA1#_0 83
J25 NC#J25 CSA1#_1 K13
R7820 1 2 120R2F--GP MEM_CALRP0 K25 MEM_CALRP0
CKEA0 K20 CKEA0 81
Place all these componets very close to GPU (within 25mm) and keep all PX CKEA1 J17 CKEA1 83
components close to each other
DRAM_RST_VGA1 W EA0# G25 W EA0# 81
This basic topology should be used for DRAM_RST for DDR3/GDDR5 L10 DRAM_RST# W EA1# H10 W EA1# 83

Te
CLKTESTA K8
1D5V_VGA_S0 L7 CLKTESTA
CLKTESTB
CLKTESTB
1

C7822 C7821 JET--XT--S3--GP

2 1

2 1

R7802 SCD1U16V2KX--3GP SCD1U16V2KX--3GP

2K2R2J--2-GP
49D9R2F--GP 10R2J--L-GP
DY DY PX
PX
CLKTESTA_C

CLKTESTB_C

DY R7804 R7803 Debug only, for

2

1 DRAM_RST_R DRAM_RST_VGA1
81,83 DRAM_RST 2 1 2 clock observation,
PX if not needed, DNI
1

ch
1
1

C7802 R7819
SC120P50V2JN--1GP 5K1R2F--2-GP R7810 R7809
2

51D1R2F--GP
PX PX 51D1R2F--GP
DY DY
2

B B

ni
ca
l
A A

<Corrre Desiiign>

Wistron Corporation
21F,,, 88, Sec...1, HsiiinTai W u Rd...,,,Hsiiichih,

Eletro-XTechnical Eletro-XTechnical
Taiiipeiii Hsiiien 221,,, Taiiiwan,,, R.O.C...

Title

GPU (3/5) VRAM I/F

Siiize Document Number Rev
A2
LV115 SKL-U -1
Date: Monday,,, Aprrriill25, 2016 Sheet 78 off 102
5 4 3 2 1
 5 4 3 2 1

3D3V_VGA_S0

RR7910 2 1 10KRR2J--3-GPP PX_JJEETTVIDEO_THERM_ALERT#

RR7903 1 2 1KRR2F-3-GPP DYY TESTEN
#3
PS0 ~ PS3 Setting Pull-High Pull-Low AMD suggest Aperture Size = 256MB
R7928 R7929
11000
Cap Value (nF) Bits [5:4] R_pu (Ω) R_pd (Ω) Bits [3:1] 11001
GPPUU11BB 22OF77 680 00 NC 4750 000 1D8V_VGA_S0
1D8V_VGA_S0
82 01 8450 2000 001
10 10 4530 2000 010 8K45R2F--2-GPP

Eletro-XTechnical
NC#AF2
AF2 NC 11 6980 4990 011 8K45R2F--2-GPP DY RR7930
PINs fordebug AF4
NC#AF4 4530 4990 100 PX RR7926
TTPP7909 1 DBG_DATA16 N9 DBG_DATA16 AG3 3240 5620 101
TTPP7914 1 DBG_DATA15 L9 DBG_DATA15 NC#AG3
AG5 PS_2
TTPP7915 1 DBG_DATA14 AE9 DBG_DATA14 DPA
NC#AG5 3400 10000 110 PS_0
TTPP7916 1 DBG_DATA13 Y11 DBG_DATA13
NC#AH3
AH3 4750 NC 111 PX
TTPP7917 1 DBG_DATA12 AE8 DBG_DATA12 AH1 DY RR7931
NC#AH1 4K75R2F--1-GPP
AD9 Note: 0402 1% resistors are required. CC7918

212 1
DBG_DATA11 R7927 CC7920 SCD68U16V3KX
X-

21
AC10 AK3 SSCCDD082U16V2KXX--GPP

212 1
DBG_DATA10 NC#AK3 2KR
R2F--3-GP
P -GP
P-U

21
AD7
AC8
DBG_DATA9
DDVVOO
NC#AK1
AK1
PX 680nF
DBG_DATA8
AC7 AK5
AB9
DBG_DATA7 NC#AK5
AM3 Board Configure [5:1] DY
DBG_DATA6 NC#AM3
AB8
DBG_DATA5
AB7 AK6
AB4
DBG_DATA4 NC#AK6
AM5 Bit 5 4 3 2 1
DBG_DATA3 NC#AM5
AB2
DBG_DATA2
DPB
## PS_3[3-1] => MEM_ID setting, need decide for AMD
3D3V_VGA_S0 Y8
DBG_DATA1 NC#AJ7
AJ7
PS0 1 1 0 0 1 PS_1[1]=0 => KABINI only PCIe GEN2 is supported
Y7
DBG_DATA0 NC#AH6
AH6 11101
RRNN7901
AK8 11001 SC_change to GEN3
D 1D8V_VGA_S0 3 2 TOPAZ_U1 NC#AK8
AL7
PS1 0 0 0 0 0 1D8V_VGA_S0 D

3
4
4 1 TOPAZ_U3 NC#AL7 1D8V_VGA_S0
RRNN7902 SRN4K
7J--8-GP
P SSRRNN4K7J-8-GPPPX_TOPAZ W6 PS2 0 0 0 0 0
NC#W6 RR7932
PX PX V6
NC#V6 8K45R2F--2-GPP
V4 3K24R2F--GP
P
Q7901 AC6
NC#V4
U5 PS3 1 1 refer below table PX RR7928 VRAM Strapping
2 NC#AC6 NC#U5
18,24 SML1_SMBCLK 6 1 1 GPIO_VGA_04_CLK 1 2RR7912
GPIO_VGA_04_CLK_R AC5
NC#AC5 PS_3
0R0402-PPAADD W3
NC#W3
5 2 AA5
NC#AA5 NC#V2
V2 PS_1 SVT
AA6 DDPPCC
NC#AA6 R7929 RR7933 CC7921
4 3 Y4
NC#Y4 DY

212 1
W5 5K62R2F--GP
P SSCCDD01U50V2KXX-1GPP

21
NC#W5 2KRR2F--L1-GPP CC7919
DY

212 1
2N7002KDDW--GPP VRAM Strapping DY
68 n0
SSCCDD68U16 V 3KX-XK3
F
GPPU
-U

21
TOPAZ_U1 U1 NC#U1
84. 2N702. A3F NC#AA3 AA3 TOPAZ_AA3 RR79041 2 16K2R2F--GPP
2nd = 075.063D1.007C RR7914 W1 Y2
18,24 SML1_SMBDATA NC#Y2
GPIO_VGA_03_DATA
1 2 GPIO_VGA_03_DATA_R TOPAZ_U3 U3 NC#W1 PX
NC#U3
0R0402-PPAADD Y6 J8
AA1 NC#Y6 NC#J8
TTPP7902 1 TOPAZ_AA1 NC#AA1

I2C PX_TTOPAZZ__CCHHEECCKK
Pull-High Pull-Low
DD7901
R1 TOPAZ_AJ27 1 3
Board Configure [2:0] R7932 R7933 Lenov o PN W istron PN Vendor PN
SCL PCH_WAKE# 17,24,31
3D3V_VGA_S0 R3 2
SDA
0 0 0 NC 4750
SV20H30107 072.4563C.0A0U Hynix H5TC4G63CFR-N0C 512MB GDDR3/GDDR3L
AM26 LBAASS16LT1G-GPP
NC_R
AK26 83.00016.PP11
SV20K59920 072.41256.0D0U MICRON MT41J256M16LY-091G:N 512MB GDDR3
1

TTPP7918 1 GPU_DPRSLP_R U6 GPIO_0 GGENERALPURRPOSEII//OONC_AVSSN#AK26 2ND = 83.00016.H11 0 0 1 8450 2000

R7921 U10 AL25
NC_GPIO_1 NC_G
RR7937 Q7902 10KRR2J--3-GPP T10
NC_GPIO_2 NC_AVSSN#AJ25
AJ25 SV20H30106 072.4G164.0B0U SAMSUNG K4W 4G1646E-BC1A 512MB GDDR3/GDDR3L
24 DGPUHOT
1 2 DGPUHOT_R G PX GPIO_VGA_03_DATA_R U8
SMBDATA 0 1 0 4530 2000
GPIO_VGA_04_CLK_R U7 AH24
2

0R0402-PPAADD SMBCLK NC_B

D GPIO_5_AC_BATT GPIO_5_AC_BATT T9 AG25 3D3V_VGA_S0
GPIO_5_AC_BATT NC_AVSSN#AG25
85 TOPAZ_OCP T8
GPIO_6 T7 DDAACC11 6980 4990 SV20H30107 072.4563C.0A0U Hynix H5TC4G63CFR-N0C 512MB GDDR3/GDDR3L
S NC_HSYNC AH26
AJ27 TOPAZ_AJ27 RR7916 1 2 4K7R2J--2-GPP P X _TOPAZ 0 1 1
No ti c e: Z Z. 2N TTPP7905 1 GPIO_8_ROMSO P10 NC_GPIO_7 NC_VSYNC
70 2. J 31 0 1
2N7002K--2-GPP TTPP7906 1 GPIO_9_ROMSI P4 GPIO_8_ROMSO
84.2N702.J31 TTPP7901 1 GPIO_10_ROMSCK P2
GPIO_9_ROMSI
1 0 0 4530 4990
2ND = 84.2N702.031 N6 GPIO_10_ROMSCK AD22
NC_GPIO_11 NC_RSET
3rd=84.2N702.W31 N5
3240 5620
NC_GPIO_12 1 0 1
PX 1V_VGACORE_S0_TOPAZ Topa z only N3 AG24
Y9 NC_GPIO_13 NC_AVDD AE22
NC_GPIO_14 NC_AVSSQ
JET_SVD N1
TTPP7903 1 GPIO16_VGA M4 GPIO_15_PWRCNTL_0 AE23 1 1 0 3400 10000
GPIO_16 NC_VDD1DI
R6 AD23
20 VIDEO_THERM_ALERT#
W10 GPIO_17_THERMAL_INT NC_VSS1DI

CLK REQUEST ? M2 NC_GPIO_18 FFuutuurreeASICC/SEYMOOUURR/PARKK

1 1 1 4750 NC
GPIO_19_CTF

El
JET_SVC P8 AM12
P7 GPIO_20_PWRCNTL_1 CEC_1
GPIO_21
TTPP7910 1 GPIO_22_ROMCS# N8
TTPP7919 1 H_VID3 AK10 GPIO_22_ROMCS# NC_SVI2#AK12 AK12 TOPAZ_SVD
TTPP7920 1 H_VID4 AM10 GPIO_29 NC_SVI2#AL11 AL11 VGA_SVT 85 64.84515.6DL 8450
GPIO_30 AJ11 TOPAZ_SVC
TTPP7921 1 PEG_CLKREQ#_VGA N7 CLKREQ# NC_SVI2#AJ11
18,76 CLKREQ_PEG#0
TTPP7907 1 JTAG_TRST#_VGA L6 JTAG_TRST# 64.69815.6DL 6980
TTPP7908 1 JTAG_TDI_VGA L5 JTAG_TDI
TTPP7911 1 JTAG_TCK_VGA L3 JTAG_TCK
TTPP7912 1 JTAG_TMS_VGAL1 JTAG_TMS AL13 64.49915.6DL 4990
TTPP7913 1 JTAG_TDO_VGA K4 JTAG_TDO NC_GENLK_CLK
AJ13
NC_GENLK_VSYNC
RR79022 1 4K7R2J--2-GPP PPXX TESTEN K7 Pre-PWROK METAL VID CODES
TESTEN
AF24
NC#AF24 64.45315.6DL 4530
LK41:R7902 10K PD NC_SWAPLOCKA
AG13
AH12 SVC SVD Output Voltage
NC_SWAPLOCKB
1V_VGACORE_S0_TOPAZ Topa z only AB13
NC_GENERICA 64.20015.L0L 2000
W8
NC_GENERICB
0 0 1.1
SVID PW R Sequencing W9
NC_GENERICC
W7
NC_GENERICD PS_0
AC19 PS_0 0 1 1.0 64.34015.6DL 3400

et
AD10
JET AJ9
NC_GENERICE_HPD4
AD19 PS_1 #3 AMD suggestion 1 0 0.9
AL9
NC#AJ9 PS_1 NC on JET
DBG_CNTL0 63.10334.1DL 10000
PS_2
AE17 PS_2 1 1 0.8 AB13 U10 W 9 Y9 W10 T10 AC14 AB12 AB11 AC11 AC13
TOPAZ AC14
NC_HPD1
TTPP7930 1 PX_EN AB16 AE20 PS_3 64.47515.6DL 4750
PX_EN PS_3

AE19
TS_A
AC16
NC_DBG_VREFG
VRAM R8105 R8106 R8301 R8302
C
CPU Side C
Single Rank 40.2OHM 64.40R25.6DL DDC/AAUX
GPIOxx GPIOxx
AE6
PPLL/CCLOCCKK NC_DDC1CLK
AE5
NC_DDC1DATA
Dual Rank 80.6OHM 64.80R65.6DL UMA 0 900M Hz 0
AD2
NC_AUX1P
AD4 PX 1 1G 1

ro
NC_AUX1N
AC11 Topaz only 1V_VGACORE_S0_TOPAZ
NC_DDC2CLK
AC13
TTPP7904 NC_DDC2DATA
XTALIN AM28 AD13 VDDCI Voltage and Ground Sense Feedback on TOPAZ only
XTALIN NC_AUX2P
XTALOUT AK28 AD11
XTALOUT NC_AUX2N
RRNN7904
1

3 2 XO_IN AC22
XO_IN NC#AD20 AD20 TOPAZ_VGA_CORE_FBN 1 TTPP7922
4 1 XO_IN2 AB22
XO_IN2 NC#AC20 AC20 TOPAZ_VGA_CORE_FBP 1 TTPP7923
SSRRNN10KJJ-5-GPP P X AE16
NC#AE16
AD16
NC#AD16
SEYMOOUURR/FFuutuurreeASICC
AC1
1 GPU_DPLUS NC_DDCVGACLK
RR7935DY T4 AC3
TTPP7924 1 GPU_DMINUS DPLUS TTHHERMMAL NC_DDCVGADATA
T2
DMINUS
3D3V_VGA_S0 12 TTPP7925 MLPS_EN#
1D8V_VGA_S0
13mA R5
R79 36 10KRR2J--3-GPP GPIO28_FDO

-X
PWR_VGA_CORE_VDDIO RR7936 AD17
0: Enable MLPS, disable GPIO PINSTRAP
TSVDD
10KRR2J--3-GPP AC17
1: Disable MLPS, enable GPIO PINSTRAP TSVSS
PX CC7914
2 1

21

PX SSCC1U10V2KXX--L1-GPP
1

JJEETT-XTT-S33-GPP
RR7918 PX
1KR
R2F--3-GP
P
PX
RR79231 2 0R2J--2-GPP PX_TTOPAZZTOPAZ_SVC
2

RR79191 2 0R2J--2-GPP PX_JJEETTJET_SVC

85 VGA_SVC

RR79241 2 0R2J--2-GPP PX_TTOPAZZTOPAZ_SVD

85 VGA_SVD RR79201 2 0R2J--2-GP PX_JJEETTJET_SVD PX

21 XTALIN
SSCC5D6P50V2CNN--1GPP CC7901

PX
RR7922
1

XXTTAAL-27MHHZZ-159-GPP
1KR
R2F--3-GP
P

Te
PX
PX
2 1

41 1MR
R2J--1-GP
P
RR7901
2

3 2

X7901

2 1 PX XTALOUT
SSCC5D6P50V2CNN--1GPP CC7903

ch
B B

ni
ca
l
A A

<<<CCCoreee DDDesiiign>

Eletro-XTechnical Eletro-XTechnical
Wistron Corporation
222111FFF, 888888,SSSeeeccc.1,HHHssinnnTTTaaai WuuuRRRddd., HHHssiccchhhihhh,
TTTaipei HHHssiien 221, TTTaiwwwan,RRR.O.CCC.
Titititle
e
GPU (4/5) GPIO/STRAP
SSSizzzeee DDDocument NNNumber RRRev
A0
LV115 SKL-U -1
DDDate:Monday,,,AAApr25,2016
il SSSheet79 ooof 102
5 4 3 2 1
 5 4 3 2 1

AMD ORB 10U x 1 LF145M 10U x 1

2.2U x5 1U x10 GPU1D 4 OF 7 1D8V_VGA_S0

1D5V_VGA_S0 0.1U x1 0.1U x1 AM30 0.1A

20141117
Eletro-XTechnical
0.01U x1 0.01U x 1 MEM II//O PCIE_PVDD

PCIIE
1A
7" to 13" H13 VDDR1
H16 VDDR1
NC#AB23 AB23
C8008 SC1U10V2KX-
-L1-GP
C8002
NC#AC23 AC23 SC10U6D3V3MX-L--GP
KAMUS

2 1

2 1
C8003 SC1U10V2KX- C8010 SC1U10V2KX- C8004 SC1U10V2KX-
C8001
-L1-GP -L1-GP -L1-GP
H19 VDDR1
J10 VDDR1
NC#AD24 AD24 PX PX
SC10U6D3V3MX--L-GP NC#AE24 AE24

2 1

2 1

2 1

2 1
PX PX PX PX J23 VDDR1
J24 VDDR1
NC#AE25 AE25
1D5V_VGA_S0 NC#AE26 AE26
J9 VDDR1 NC#AF25 AF25
20141121_7" to 13"_KAMUS K10 VDDR1 NC#AG26 AG26 0D95V_VGA_S0
K23 VDDR1 AMD ORB 10U x 1 LF145M 10U x 1
D C8042 SC1U10V2KX- C8005 SC1U10V2KX- C8006 SC1U10V2KX- PX C8007
K24 VDDR1
K9 VDDR1 L23
2.5A 1U x6 1U x6 D
C8014 PCIE_VDDC
-L1-GP -L1-GP -L1-GP SCD1U16V2KX--L-GP L11 VDDR1 L24
PCIE_VDDC
2 1

2 1

2 1

2 1

2 1
SCD01U50V2KX--L-GP L12 VDDR1 L25 C8011 SC1U10V2KX- C8012 SC1U10V2KX- C8013 C8015 SC1U10V2KX- C8017 SC1U10V2KX- C8016 C8057 SC1U10V2KX-
PX PX PX PX L13 VDDR1
PCIE_VDDC
L26 -L1-GP -L1-GP SC4D7U6D3V3KX-L--GP -L1-GP -L1-GP SC10U6D3V3MX--L-GP -L1-GP
PCIE_VDDC

2 1

2 1

2 1

2 1

2 1

2 1

2 1
L20 VDDR1 PCIE_VDDC M22
PX PX PX PX PX PX PX
L21 VDDR1 PCIE_VDDC N22
L22 VDDR1 PCIE_VDDC N23
PCIE_VDDC N24
1

1
C8034 SC1U10V2KX- C8031 SC1U10V2KX- C8032 SC1U10V2KX- C8033 SC1U10V2KX- R22
-L1-GP -L1-GP -L1-GP -L1-GP PCIE_VDDC
PCIE_VDDC T22
LEVEL
PX PX PX PX U22
2

2
TRANSLATIION PCIE_VDDC 1V_VGACORE_S0
13mA PCIE_VDDC V22 AMD ORB 10U x 6 LF145M 4.7U x 6
1D8V_VGA_S0 AA20 VDD_CT
AA21 VDD_CT 2.2U x 16 1U x20
C8018 SC1U10V2KX- AB20 VDD_CT AA15
CORE VDDC
-L1-GP AB21 VDD_CT N15 C8019 SC1U10V2KX- C8035 SC1U10V2KX- C8020 SC1U10V2KX- C8021 SC1U10V2KX- C8022 C8023
VDDC

21
N17 -L1-GP -L1-GP -L1-GP -L1-GP SC1U10V2KX--L1-GP SC10U6D3V3MX--L-GP
PX VDDC

2 1

2 1

2 1

2 1

2 1

2 1
I/O VDDC R13
PX PX PX PX PX PX
25mA AA17 VDDC R16
R18
3D3V_VGA_S0 VDDR3 VDDC
AA18 Y21
VDDR3 VDDC
AB17 VDDR3 VDDC T12
AB18 VDDR3 T15 NC on JET 1V_VGACORE_S0
VDDC
T17
Memory phase lock loop power: Dedicated
VDDC AB13 U10 W9 Y9 W10 T10 AC14 AB12 AB11 AC11 AC13

El
V12 T20
C8024 NC_VDDR4#V12 VDDC
Y12 U13
analogue power in for memory PLLs SC1U10V2KX--L1-GP NC_VDDR4#Y12 VDDC

21
U12 NC_VDDR4#U12 U16 C8025 C8026 C8027 C8028 SC1U10V2KX- C8029 SC1U10V2KX- C8030 SC1U10V2KX-
1D8V_VGA_S0 MPV18 PX VDDC SC10U6D3V3MX--L-GP SC1U10V2KX--L1-GP SC10U6D3V3MX--L-GP -L1-GP -L1-GP -L1-GP
L8001 VDDC U18

21

21

21

21

21

21
1 VDDC V21 PX PX PX PX PX PX 20141117_7" to 13"
2 MMZ1005S241C--GP V15
VDDC
PX
C8043 C8044 C8045 VDDC V17
V20
KAMUS 1V_VGACORE_S0

SC1U10V2KX--L1-GP VDDC

POWER
SC10U6D3V3MX--L-GP SC10U6D3V3MX--L-GP Y13
VDDC
21

21

21

PX PX PX VDDC Y16

et
Y18 C8059 C8036 C8037 C8038 C8039 C8040 C8041 C8063 C8064
VDDC
20141117_7" to 13" VDDC AA12 SC1U10V2KX--L1-GP SC1U10V2KX--L1-GP SC1U10V2KX--L1-GP SC10U6D3V3MX--L-GP SC10U6D3V3MX--L-GP SC10U6D3V3MX--L-GP SC10U6D3V3MX--L-GP SC10U6D3V3MX--L-GP SC10U6D3V3MX--L-GP

2 1
21

21

21

21

21

21

21

21
M11 PX PX PX PX PX PX PX PX PX
KAMUS VDDC
VDDC N12
VDDC U11
Engine phase loop power: Dedicated analogue 1V_VGACORE_S0

C power pin for engine PLL PLL C

1D8V_VGA_S0 BLM15BD121SN1D--GP SPV18

ro
0D95V_VGA_S0 C8058 C8066 C8060 C8061 C8062
L8002 PX SC1U10V2KX--L1-GP SC1U10V2KX--L1-GP SC1U10V2KX--L1-GP SC1U10V2KX--L1-GP SC1U10V2KX--L1-GP
1 2
1.4A

21

21

21

21

21
C8054 SC1U10V2KX- BIF_VDDC R21 PX PX PX PX PX
C8053 MPV18
SC10U6D3V3MX--L-GP -L1-GP BIF_VDDC U21
C8065
90mA
21

21

PX PX L8 MPLL_PVDD AMD ORB 10U x 2 SC10U6D3V3MX--L--GP LF145M 4.7U x 2

2 1
1U x3 PX 1U x 3
ISOLATED 1V_VGACORE_S0
SPV18 COREI/O
5A 0.1U x2 0.1U x 2
75mA M13

-X
VDDCI
Engine phase loop power: Dedicated digital H7 SPLL_PVDD VDDCI M15
C8051
0D95V_VGA_S0 M16 C8046 C8047 C8048 SC1U10V2KX- C8049 C8050 C8052
power pin for engine PLL VDDCI SC1U10V2KX--L1-GP SC10U6D3V3MX--L-GP PX SC10U6D3V3MX--L-GP

SC4D7U6D3V3KX--L--GP
M17 SCD1U16V2KX-L--GP SCD1U16V2KX-L--GP -L1-GP
VDDCI

21

21

21

21

21

21

21
BLM15BD121SN1D--GP SPV10 SPV10
VDDCI M18
PX PX PX PX PX PX
L8003 PX M20
1 2 100mA H8 SPLL_VDDC
VDDCI
M21
VDDCI
VDDCI N20
C8055 SC1U10V2KX- C8056 SC1U10V2KX- J7
SPLL_PVSS
-L1-GP -L1-GP
2 1

2 1

PX PX

Te
JET--XT--S3--GP
PX

ch
B B

ni
ca
l
A A

<Core Desiiign>

Wistron Corporation
21F,,, 88,,, Sec.1,,, Hsiiin Taiii W u Rd., Hsiiichiih,,,

Eletro-XTechnical Eletro-XTechnical
Taipei Hsiiien 221, Taiwan, R...O...C...

Tiitttlle

GPU (5/5) PWR/GND

Siize Document Number Rev
A2
LV115 SKL-U -1
Date: Monday,,, Aprrriill25,,, 2016 Sheet 80 off 102
5 4 3 2 1
 5 4 3 2 1

Channel 0 DATA0:15 Channel 0 DATA16:31

Eletro-XTechnical
1D5V_VGA_S0 1D5V_VGA_S0
VRAM1 VRAM2
DQA0_[31..0] 78 DQA0_[31..0] 78
B2 VDD DQ0 E3 DQA0_14 B2 DQ0 E3 DQA0_18
VDD
D9 DQ1 F7 DQA0_10 D9 DQ1 F7 DQA0_19
VDD VDD
G7 DQ2 F2 DQA0_15 G7 DQ2 F2 DQA0_17
VDD VDD
K2 DQ3 F8 DQA0_11 K2 DQ3 F8 DQA0_22 DATA GROUP 2
VDD VDD
D K8 DQ4 H3 DQA0_13 DATA GROUP 1 K8 DQ4 H3 DQA0_20 D
VDD VDD
N1 DQ5 H8 DQA0_8 N1 DQ5 H8 DQA0_21
VDD VDD
N9 DQ6 G2 DQA0_12 N9 DQ6 G2 DQA0_16
VDD VDD
R1 DQ7 H7 DQA0_9 R1 DQ7 H7 DQA0_23
VDD VDD
R9 DQ8 D7 DQA0_3 R9 DQ8 D7 DQA0_31
VDD VDD
DQ9 C3 DQA0_7 DQ9 C3 DQA0_27
A1 DQ10 C8 DQA0_1 A1 DQ10 C8 DQA0_30
VDDQ VDDQ
A8 DQ11 C2 DQA0_6 A8 DQ11 C2 DQA0_25
VDDQ VDDQ
C1 DQ12 A7 DQA0_0 DATA GROUP 0 C1 DQ12 A7 DQA0_28 DATA GROUP 3
VDDQ VDDQ
C9 DQ13 A2 DQA0_5 C9 DQ13 A2 DQA0_24
VDDQ VDDQ
D2 DQ14 B8 DQA0_2 D2 DQ14 B8 DQA0_29
VDDQ VDDQ
E9 DQ15 A3 DQA0_4 E9 DQ15 A3 DQA0_26
VDDQ VDDQ
F1 F1
VDDQ VDDQ
H2
VDDQ LDQS F3 QSAP_1 78 H2 VDDQ LDQS F3 QSAP_2 78
H9
VDDQ LDQS# G3 QSAN_1 78 DQS1 H9 VDDQ LDQS# G3 QSAN_2 78 DQS2

FBA_VREF_1 UDQS C7 QSAP_0 78

FBA_VREF_2 UDQS C7
QSAP_3 78
H1
VREFDQ UDQS# B7 QSAN_0 78 DQS0 H1
VREFDQ UDQS# B7 QSAN_3 78 DQS3
FBA_VREF_1_CA M8 VREFCA FBA_VREF_2_CA M8 VREFCA
243R2F--2-GP 2 1 R8101 VRAM_CH_A_ZQ_1 L8 ZQ K1 ODTA0 243R2F--2-GP 2 1 R8102 VRAM_CH_A_ZQ_2 L8 ZQ K1
ODT 78 ODT ODTA0 78
VRAM_CH0 VRAM_CH0
CS# L2 CSA0#_0 78 CS# L2 CSA0#_0 78
N3 N3
78,83 MAA0 A0 RESET# T2 DRAM_RST 78,83 78,83 MAA0 A0 RESET# T2 DRAM_RST 78,83
78,83 MAA1 P7 A1 78,83 MAA1 P7 A1

El
P3 P3
78,83 MAA2 A2 NC#J1 J1 78,83 MAA2 A2 NC#J1 J1
N2 N2
78,83 MAA3 A3 NC#J9 J9 78,83 MAA3 A3 NC#J9 J9
P8 P8
78,83 MAA4 A4 NC#L1 L1 78,83 MAA4 A4 NC#L1 L1
P2 P2
A5 NC#L9 L9 A5 NC#L9 L9
78,83 MAA5 R8 78,83 MAA5 R8
A6 NC#M7 M7 MAA15 78,83 A6 NC#M7 M7 MAA15 78,83
78,83 MAA6 R2 78,83 MAA6 R2
A7 NC#T3 T3 MAA13 78,83 A7 NC#T3 T3 MAA13 78,83
T8 T8
78,83 MAA7 A8 NC#T7 T7 MAA14 78,83 78,83 MAA7 A8 NC#T7 T7 MAA14 78,83
78,83 MAA8 R3 A9 78,83 MAA8 R3 A9
78,83 MAA9 L7 A10/AP 78,83 MAA9 L7 A10/AP
R7 A11 VSS A9 R7 A11 VSS A9
78,83 MAA10 78,83 MAA10

et
N7 B3 N7 B3
78,83 MAA11 A12/BC# VSS 78,83 MAA11 A12/BC# VSS
E1 E1
78,83 MAA12 VSS 78,83 MAA12 VSS
G8 G8
VSS VSS
78,83 MAA_BA0 M2 BA0 J2 78,83 MAA_BA0 M2 BA0 J2
VSS VSS
78,83 MAA_BA1 N8 BA1 J8 78,83 MAA_BA1 N8 BA1 J8
VSS VSS
M3 BA2 M1 M3 BA2 M1
78,83 MAA_BA2 VSS 78,83 MAA_BA2 VSS
M9 M9
VSS VSS DRAM_RST
C P1 P1 C
VSS VSS
Data Mask 1 78 DQMA1 E7 P9 Data Mask 2 78 DQMA2 E7 LDM P9
LDM VSS VSS
For VRAM1,VRAM2

ro
Data Mask 0 78 DQMA0 D3 T1 Data Mask 3 78 DQMA3 D3 UDM T1
UDM VSS VSS
T9 T9
VSS VSS

78 CLKA0 J7 CK B1 78 CLKA0 J7 CK B1
VSSQ VSSQ
78 CLKA0# K7 CK# B9 78 CLKA0# K7 CK# B9
VSSQ VSSQ
D1 D1
VSSQ VSSQ

1
78 CKEA0 K9 CKE D8 78 CKEA0 K9 CKE D8
VSSQ VSSQ

ED8101

ED8102
E2 E2

PESD5V0U1BL--GP-U1

PESD5V0U1BL--GP-U1
VSSQ VSSQ
VSSQ
E8
VSSQ E8 VRAM_CH0 VRAM_CH0
78 WEA0# L3 W E# F9 78 WEA0# L3 W E# F9

-X
VSSQ VSSQ
78 CASA0# K3 CAS# G1 78 CASA0# K3 CAS# G1

2
VSSQ VSSQ
J3 RAS# G9 J3 G9
78 RASA0# VSSQ 78 RASA0# RAS# VSSQ

MT41K256M16HA--107G--E--GP MT41K256M16HA--107G--E--GP
VRAM_CH0_BOM_CTRL VRAM_CH0_BOM_CTRL

Te
1D5V_VGA_S0 1D5V_VGA_S0 1D5V_VGA_S0 1D5V_VGA_S0

R8105 R8106 R8301 R8302

1
1

1
R8103 R8109 R8107 R8111 Single Rank, 40.2 Ohm 64.40R25.6DL
4K99R2F--L-GP 4K99R2F--L-GP 4K99R2F--L-GP 4K99R2F--L-GP
Dual Rank, 80.6 Ohm 64.80R65.6DL

ch
VRAM_CH0 VRAM_CH0 VRAM_CH0 VRAM_CH0
2

2
CLKA0 CLKA0#
FBA_VREF_1 FBA_VREF_1_CA FBA_VREF_2 FBA_VREF_2_CA

1
SCD1U16V2KX--L-GP

SCD1U16V2KX--L-GP

SCD1U16V2KX-L--GP
B R8105 R8106 B

SCD1U16V2KX-L--GP
40D2R2F--GP 40D2R2F--GP
1

1
VRAM_CH0 VRAM_CH0
VRAM_CH0 VRAM_CH0 VRAM_CH0 VRAM_CH0

2
R8104 C8113 R8110 C8118 R8108 C8117 R8112 C8119 CLKA0_CLKA0#
2 1

2 1

2 1
4K99R2F--L-GP 4K99R2F--L-GP 4K99R2F--L-GP 4K99R2F--L-GP

ni 2
VRAM_CH0 VRAM_CH0 VRAM_CH0 VRAM_CH0
2

2
C8116

2 1
SCD01U50V2KX-L--GP
VRAM_CH0

ca
Close to VRAM1 Close to VRAM2
0.1uF(X7R) 1D5V_VGA_S0 0.1uF(X7R) 1D5V_VGA_S0

K0402 ×4 K0402 ×4

l
SCD1U16V2KX--L--GP

SCD1U16V2KX--L--GP

SCD1U16V2KX--L--GP
SCD1U16V2KX--L--GP

SCD1U16V2KX--L--GP
SCD1U16V2KX--L--GP

SCD1U16V2KX--L--GP
SCD1U16V2KX-L--GP

VRAM_CH0 VRAM_CH0 VRAM_CH0 VRAM_CH0 VRAM_CH0 VRAM_CH0 VRAM_CH0 VRAM_CH0

1
1
1

C8101 C8102 C8103 C8104 C8127 C8121 C8124 C8109

2 1

2 1

2 1

2 1
2
2

10uF(X5R) 10uF(X5R)
1.0uF(X7R) M0805 ×2 1.0uF(X7R) M0805 ×2
K0603 ×8 K0603 ×8
A A
SC10U10V5KX--L1-GP

SC10U10V5KX--L1-GP
VRAM_CH0 VRAM_CH0 VRAM_CH0 VRAM_CH0 VRAM_CH0 VRAM_CH0 VRAM_CH0 VRAM_CH0 VRAM_CH0 VRAM_CH0 VRAM_CH0 VRAM_CH0 VRAM_CH0 VRAM_CH0 VRAM_CH0 VRAM_CH0
SC10U25V5KX-L--GP

SC10U25V5KX--L-GP
SC1U10V2KX--L1-GP

SC1U10V2KX--L1-GP

SC1U10V2KX--L1-GP

SC1U10V2KX--L1-GP

SC1U10V2KX--L1-GP

SC1U10V2KX--L1-GP

SC1U10V2KX--L1-GP

SC1U10V2KX--L1-GP

SC1U10V2KX--L1-GP

SC1U10V2KX--L1-GP

SC1U10V2KX--L1-GP

SC1U10V2KX--L1-GP

SC1U10V2KX--L1-GP

SC1U10V2KX--L1-GP
C8115 C8114 C8126 C8122
C8105 C8106 C8107 C8108 C8110 C8111 C8112 DY C8128 C8123 C8129 C8131 C8130 C8120 C8125 DY
2 1

2 1
2 1

2 1

2 1

2 1

2 1

2 1

2 1

2 1

2 1

2 1

2 1

2 1

2 1

2 1
2 1

2 1
<Corrre Desiiign>

Wistron Corporation
21F,,, 88, Sec...1, HsiiinTai W u Rd...,,,Hsiiichih,

Eletro-XTechnical Eletro-XTechnical
Taiiipeiii Hsiiien 221,,, Taiiiwan,,, R.O.C...

Title

VRAM1,2 (1/4)
Siize Document Number Rev
A2
LV115 SKL-U -1
Date: Monday,,, Aprrriill25, 2016 Sheet 81 off 102
5 4 3 2 1
 5 4 3 2 1

Channel 1 DATA16:31 Channel 1 DATA0:15

1D5V_VGA_S0 1D5V_VGA_S0
VRAM5 VRAM6
DQA1_[31..0] 78 DQA1_[31..0] 78
B2 E3 DQA1_30 B2 VDD DQ0 E3
DQA1_0

Eletro-XTechnical
VDD DQ0
D9 DQ1 F7 DQA1_27 D9 DQ1 F7
DQA1_4
VDD VDD
G7 DQ2 F2 DQA1_29 G7 DQ2 F2
DQA1_2
VDD VDD
K2 DQ3 F8 DQA1_25 DATA GROUP 7 K2 DQ3 F8
DQA1_7 DATA GROUP 4
VDD VDD
K8 DQ4 H3 DQA1_28 K8 DQ4 H3
DQA1_3
VDD VDD
N1 DQ5 H8 DQA1_24 N1 DQ5 H8
DQA1_5
VDD VDD
N9 DQ6 G2 DQA1_31 N9 DQ6 G2
DQA1_1
VDD VDD
R1 DQ7 H7 DQA1_26 R1 H7 DQA1_6
VDD VDD DQ7
R9 DQ8 D7 DQA1_19 R9 D7 DQA1_12
VDD VDD DQ8
DQ9 C3 DQA1_22 C3 DQA1_11
DQ9
A1 C8 DQA1_18 A1
VDDQ DQ10 VDDQ DQ10 C8 DQA1_15
A8 DQ11 C2 DQA1_21 A8 DATA GROUP 5
VDDQ VDDQ DQ11 C2 DQA1_10
D C1 DQ12 A7 DQA1_17 DATA GROUP 6 C1 D
VDDQ VDDQ DQ12 A7 DQA1_13
C9 DQ13 A2 DQA1_23 C9
VDDQ VDDQ DQ13 A2 DQA1_8
D2 DQ14 B8 DQA1_16 D2
VDDQ VDDQ DQ14 B8 DQA1_14
E9 DQ15 A3 DQA1_20 E9
VDDQ VDDQ DQ15
F1 F1 A3 DQA1_9
VDDQ VDDQ
H2 H2
VDDQ LDQS F3 QSAP_7 78 VDDQ LDQS F3 QSAP_4 LDQS# G3 78
H9 VDDQ LDQS# G3 QSAN_7 78 DQS7 H9
VDDQ QSAN_4 78 DQS4

FBA_VREF_5 UDQS C7 QSAP_6 78 FBA_VREF_6 UDQS C7 QSAP_5 78

H1
UDQS# B7 DQS6 H1 UDQS# B7 QSAN_5 DQS5
FBA_VREF_5_CA M8 VREFDQ QSAN_6 78 FBA_VREF_6_CA M8 VREFDQ 78
VRAM_CH_A_ZQ_5 VREFCA VRAM_CH_A_ZQ_6 VREFCA
243R2F--2-GP 2 1 R8308 L8 K1 ODTA1 78 243R2F--2-GP 2 1 R8309 L8 K1 ODTA1 78
ZQ ODT ZQ ODT
VRAM_CH1 VRAM_CH1
CS# L2 CSA1#_0 78 CS# L2 CSA1#_0 78
N3 DRAM_RST 78,81 N3 DRAM_RST 78,81
78,81 MAA0 A0 RESET# T2 78,81 MAA0 A0 RESET# T2
78,81 MAA1 P7 A1 78,81 MAA1 P7 A1
P3 P3
78,81 MAA2 A2 NC#J1 J1 78,81 MAA2 A2 NC#J1 J1
N2 N2
78,81 MAA3 A3 NC#J9 J9 78,81 MAA3 A3 NC#J9 J9
P8 P8
78,81 MAA4 A4 NC#L1 L1 78,81 MAA4 A4 NC#L1 L1
P2 P2
78,81 MAA5 A5 NC#L9 L9 78,81 MAA5 A5 NC#L9 L9
R8 R8
A6 NC#M7 M7 MAA15 78,81 A6 NC#M7 M7 MAA15 78,81
78,81 MAA6 R2 78,81 MAA6 R2
A7 NC#T3 T3 MAA13 78,81 A7 NC#T3 T3 MAA13 78,81
78,81 MAA7 T8 78,81 MAA7 T8
A8 NC#T7 T7 MAA14 78,81 A8 NC#T7 T7 MAA14 78,81
78,81 MAA8 R3 A9 78,81 MAA8 R3 A9

El
78,81 MAA9 L7 A10/AP 78,81 MAA9 L7 A10/AP
78,81 MAA10 R7 A11 VSS A9 78,81 MAA10 R7 A11 VSS A9
N7 B3 N7 B3
78,81 MAA11 A12/BC# VSS 78,81 MAA11 A12/BC# VSS
E1 E1
78,81 MAA12 VSS 78,81 MAA12 VSS
G8 G8
VSS VSS
78,81 MAA_BA0 M2 BA0 J2 78,81 MAA_BA0 M2 BA0 J2
VSS VSS
78,81 MAA_BA1 N8 BA1 J8 78,81 MAA_BA1 N8 BA1 J8
VSS VSS
78,81 MAA_BA2 M3 BA2 M1 78,81 MAA_BA2 M3 BA2 M1
VSS VSS
M9 M9
VSS VSS
P1 P1
VSS VSS

et
Data Mask 7 78 DQMA7 E7 LDM VSS P9 Data Mask 4 78 DQMA4 E7
VSS
P9
D3 LDM T1
Data Mask 6 78 DQMA6 D3 UDM VSS T1 Data Mask 5 78 DQMA5 VSS
T9 UDM T9 DRAM_RST
VSS VSS

78 CLKA1 J7 CK
K7 CK#
VSSQ B1
B9
78 CLKA1 J7 CK
K7 CK#
VSSQ
B1
B9
For VRAM5,VRAM6
78 CLKA1# VSSQ 78 CLKA1# VSSQ
D1 D1
VSSQ VSSQ
C K9 CKE D8 K9 CKE D8 C
78 CKEA1 VSSQ 78 CKEA1 VSSQ
E2 E2
VSSQ VSSQ

ro
E8 E8
VSSQ VSSQ

1
78 WEA1# L3 W E# F9 78 WEA1# L3 W E# F9
VSSQ VSSQ

ED8301

ED8302
78 CASA1# K3 CAS# G1 78 CASA1# K3 CAS# G1

PESD5V0U1BL--GP-U1

PESD5V0U1BL--GP-U1
VSSQ VSSQ
78 RASA1# J3 RAS# VSSQ G9 78 RASA1# J3 RAS# VSSQ
G9 VRAM_CH0 VRAM_CH0

2
MT41K256M16HA--107G--E--GP MT41K256M16HA--107G--E--GP
VRAM_CH1_BOM_CTRL VRAM_CH1_BOM_CTRL

-X
1D5V_VGA_S0 1D5V_VGA_S0
R8105 R8106 R8301 R8302

Te
1D5V_VGA_S0 1D5V_VGA_S0

Single Rank, 40.2 Ohm

1

Dual Rank, 80.6 Ohm

1
R8305 R8376
4K99R2F--L-GP 4K99R2F--L-GP R8374 R8378
VRAM_CH1 VRAM_CH1 CLKA1 CLKA1# 4K99R2F--L-GP 4K99R2F--L-GP
VRAM_CH1 VRAM_CH1
2

1
1

2
R8301 R8302
FBA_VREF_5 FBA_VREF_5_CA 40D2R2F--GP 40D2R2F--GP
VRAM_CH1 VRAM_CH1 FBA_VREF_6 FBA_VREF_6_CA

ch
2

CLKA1_CLKA1#
1

VRAM_CH1 VRAM_CH1

1
R8306 R8375 VRAM_CH1 VRAM_CH1
4K99R2F--L-GP C8324 4K99R2F--L-GP C8330 C8301 R8373 R8377
21

21

21

SCD01U50V2KX--L-GP 4K99R2F--L-GP C8329 4K99R2F--L-GP C8331

VRAM_CH1 VRAM_CH1

2 1

2 1
B VRAM_CH1 VRAM_CH1 VRAM_CH1 B
2

SCD1U16V2KX--L-GP SCD1U16V2KX-L--GP

2
SCD1U16V2KX-L--GP SCD1U16V2KX--L-GP

ni
ca
Close to VRAM5 Close to VRAM6
0.1uF(X7R) 1D5V_VGA_S0 0.1uF(X7R) 1D5V_VGA_S0

K0402 ×4 K0402 ×4
SCD1U16V2KX--L--GP

SCD1U16V2KX--L--GP

SCD1U16V2KX--L--GP

SCD1U16V2KX--L--GP

SCD1U16V2KX--L--GP

SCD1U16V2KX--L--GP

SCD1U16V2KX--L--GP
SCD1U16V2KX--L--GP

VRAM_CH1 VRAM_CH1 VRAM_CH1 VRAM_CH1 VRAM_CH1 VRAM_CH1 VRAM_CH1 VRAM_CH1

l
1

C8319 C8326 C8318 C8322 C8334 C8336 C8335 C8341

2 1

2 1

2 1

2 1

2 1

2 1

2 1
2

10uF(X5R) 10uF(X5R)
1.0uF(X7R) M0805 ×2 1.0uF(X7R) M0805 ×2
K0603 ×8 K0603 ×8
SC10U10V5KX--L1-GP

SC10U10V5KX--L1-GP
VRAM_CH1 VRAM_CH1 VRAM_CH1 VRAM_CH1 VRAM_CH1 VRAM_CH1 VRAM_CH1 VRAM_CH1 VRAM_CH1 VRAM_CH1 VRAM_CH1 VRAM_CH1 VRAM_CH1 VRAM_CH1 VRAM_CH1 VRAM_CH1 VRAM_CH1 VRAM_CH1
SC10U25V5KX--L-GP

SC10U25V5KX--L-GP
SC1U10V2KX--L1-GP

SC1U10V2KX--L1-GP

SC1U10V2KX--L1-GP

SC1U10V2KX--L1-GP

SC1U10V2KX--L1-GP

SC1U10V2KX--L1-GP

SC1U10V2KX--L1-GP

SC1U10V2KX--L1-GP

SC1U10V2KX--L1-GP

SC1U10V2KX--L1-GP

SC1U10V2KX--L1-GP

SC1U10V2KX--L1-GP

SC1U10V2KX--L1-GP

SC1U10V2KX--L1-GP

SC1U10V2KX--L1-GP

SC1U10V2KX--L1-GP
1

1
A C8327 C8333 A
C8328 C8337
C8314 C8315 C8317 C8316 C8323 C8321 C8320 C8325 DY C8339 C8332 C8340 C8344 C8342 C8338 C8345 C8343 DY
2 1

2 1

2 1

2 1

2 1

2 1

2 1

2 1

2 1

2 1

2 1

2 1

2 1

2 1
2

2
<Core Desiiign>

Wistron Corporation
21F,,, 88,,, Sec.1,,, Hsiiin Taiii W u Rd., Hsiiichiih,,,

Eletro-XTechnical Eletro-XTechnical
Taipei Hsiiien 221, Taiwan, R...O...C...

Tiitle

VRAM5,6 (3/4)
Siiize Document Number Rev
A2
LV115 SKL-U -1
Date: Monday,,, Aprrriill25,,, 2016 Sheet 83 off 102
5 4 3 2 1
 5 4 3 2 1

AMD EXO pro DCBATOUT

PG8503
PWR_VGA_CORE_DCBATOUT_2 DCBATOUT

PG8501
PWR_VGA_CORE_DCBATOUT_1

1
1 2 1 2

Eletro-XTechnical
PR8501 PR8502
10KR2J--3-GP 10KR2J--3-GP GAP-CLOSE-PWR--3--GP GAP--CLOSE--PWR--3--GP
PX PX PG8504 PG8502

2
1 2 1 2

PR8503 1 2 10KR2F--2-GP PX EN/DEM_VGA GAP-CLOSE-PWR--3--GP GAP-CLOSE-PWR-3-GP PWR_VGA_CORE_DCBATOUT_1

PWR_VGA_CORE_UGATE_LX_NB
3D3V_VGA_S0 TP8503
PC8502 2 1 SCD1U16V2KX--L-GP PX

PWR_VGA_CORE_LGATE_NB
PG8506 PG8505
1 2 1 2
3D3V_VGA_S0 PR8550 1 2 0R2J--2-GP PX_JET

1
D GAP-CLOSE-PWR--3--GP GAP-CLOSE-PWR--3--GP D
2 0R2J--2-GP PX_TOPAZ PWR_VGA_CORE_VDDIO
PR8505 1
1D8V_VGA_S0 2 SC1KP50V2KX--L-1-GP PX
PC8503 1

PU8504 PU8501
2 2

PU8201_36
PU8201_39
5V_S5 3 3

1
1 4 1 4 PC8504 PC8505 PC8506
PX PX PX

SC10U25V5KX--L-GP

SC10U25V5KX--L-GP

SC10U25V5KX--L-GP
10 10
PWR_VGA_CORE_VDDIO 9 9

2
PR8504 7 7
PWR_VGA_CORE_VR_HOT# 1 2 8 6 8 6
5 5

40

39

38

37

36

35

34

33

32

31
PX_TOPAZ 10KR2F--2-GP PU8502

FB_NB

PHASE_NB
LGATE_NB
VSEN_NB

COMP_NB
ISUMP_NB

BOOT_NB
ISUMN_NB

UGATE_NB
PGOOD_NB
5V_S5 FDMS3600-02-RJK0215-COLAY--GP FDMS3600-02-RJK0215-COLAY--GP
ZZ PX PWR Change 84.08S36.037

PR8507
PR8506 1 100KR2F--L1-GP PWR_VGA_CORE_NTC_NB 2 PC8507 PR8510 1st = 84.08S36.037
PX 2 1 NTC_NB BOOT2 30
PWR_VGA_CORE_BOOT21 PX 2 1
PWR_VGA_CORE BOOT2_1
TDC=36A
2D2R3-1-U--GP 1R2F--GP 2nd = 075.06992.0073

1
PR8508 1 PX 2 100KR2F--L1-GP PWR_VGA_CORE_IMON_NB 2 IMON_NB UGATE2 29
PWR_VGA_CORE_UGATE2 SCD22U25V3KX--GP
PX
OCP<54A
PR8509 1
PX
2 0R0402-PAD PWR_VGA_CORE_SVC 3
SVC PHASE2 28
PWR_VGA_CORE_PHASE2 1V_VGACORE_S0
79 VGA_SVC PWR_VGA_CORE_UGATE1

El
PL8502
PR8511 1 2 0R0402-PAD PWR_VGA_CORE_VR_HOT# 4 27 PWR_VGA_CORE_LGATE2 1ST = 68.R3610.20X
79 TOPAZ_OCP

2
VR_HOT# LGATE2
PWR_VGA_CORE_PHASE1
2ND = 068.R3610.1001
PR8512 1 2 0R0402-PAD PWR_VGA_CORE_SVD 5 SVD 1 2 COIIL--D36UH-6--GP
79 VGA_SVD IISL62771HRTZ--GP--U VDDP 26
PWR_VGA_CORE_VDD A

GAP-CLOSE-PWR--3--GP

GAPP--CLOSE-PWR--3--GP
PWR_VGA_CORE_VDDIO 6 VDDIO VDD 25
PWR_VGA_CORE_LGATE1
PX
PR8513 1 2 0R2J--2-GP PWR_VGA_CORE_SVT PWR_VGA_CORE_LGATE1 L
79 VGA_SVT 7 SVT LGATE1 24

2
PX_TOPAZ

PG8507
PC8509 PC8508
2 PWR_VGA_CORE_ENABLE

PG8508
PR8514 1 PWR_VGA_CORE_PHASE1
8 ENABLE PHASE1 23 SC1U10V2KX-L1--GP SC1U10V2KX--L1-GP

et

2 1

2 1
0R0402-PAD
PX PX PX PT8501
PWR_VGA_CORE_PWROK 9 PW ROK PWR_VGA_CORE_UGATE1
UGATE1 22

1
79.33719.L01

SE330U2VDM--L-GP
PR8515 PC8510

2 1
PD8501
PWR_VGA_CORE_IMON 10 IMON BOOT1 21
PWR_VGA_CORE_BOOT1 1 PX2PW R_VGA_CORE BOOT1_11 2
K AEN/DEM_VGA 2D2R3-1-U--GP
1ST = 79.33719.L01

PWR_VGA_CORE_PH1
20,86 PE_GPIO1
1

PWR_VGA_CORE_VO1
RB551VM--30TE--17-GP 41 GND SCD22U25V3KX-GP
3D3V_VGA_S0 PX PR8517 2ND = 79.33719.20C
1

PX PR8516 PWR_VGA_CORE_ISUMP 1 PX 2

PGOOD
C C

ISUMN
ISUMP

COMP
ISEN2
PC8511 ISEN1

VSEN
133KR2F--GP 3K65R2F--1-GP

1
NTC

RTN

ro
PE_GPIO1 is for 83.R5003.N8F PX S
SC1KP50V2KX-L-
-1--GP

FB
PR8518
2

PX 1KR2J--L2-GP PR8519
turning off PWR IC PX PX PWR_VGA_CORE_ISEN1 1
1ST = 83.R5003.N8F PX X2
11

12

13

14

15

16

17

18

19

20
10KR2F--2-GP

2
2nd = 83.55130.08F PWR_VGA_CORE_PGOOD PR8520 1 2 0R0402-PAD
PWR_VGA_CORE_NTC

PWR_VGA_CORE_ISEN2

PWR_VGA_CORE_ISEN1

PWR_VGA_CORE_ISUMP

PWR_VGA_CORE_ISUMN

PWR_VGA_CORE_VSEN

PWR_VGA_CORE_RTN
DGPU_PWROK 19,24,76
PX
PC8512 PWR_VGA_CORE_VSUM- PR8521 1 2 1R2F--GP
SC100P50V2JN--L-GP

2 1
PX

-X
PX
PWR_VGA_CORE_ISEN2 PR8522 1 2 10KR2J--3-GP
PR8523
PWR_VGA_CORE_FB 2 PX 1 PWR_VGA_CORE_FB_R 2 1 PC8513
301R2F--GP SC1KP50V2KX--L-1-GP
2

20141208_KAMUS PX
PR8524
100KR2F--L1-GP PR8525
PWR_VGA_CORE_COMP PC8514 2 1 SC100P50V2JN--L-GP PX 1 2 PWR_VGA_CORE_VSEN PWR_VGA_CORE_DCBATOUT_2
PX
1K2R2F--1-GP
1

PX

Te
PR8527 PC8516
PC8515 2 PR8526
1PWR_VGA_CORE_FB2_R2 1 1 PX 2 PWR_VGA_CORE_COMP_1 1 PX 2 X
2KR2F--3-GP
PX SC390P50V2KX-GP-U 47KR2F--GP
1

SC330P50V2KX--3GP
PR8528 PX
PC8517 PC8518 32K4R2F--1-GP DY
1

PX PX
SCD22U10V2KX--L1-GP

SCD22U10V2KX--L1-GP

PC8519 PC8520 PC8521

PU8505 PU8503

SC10U25V5KX--L-GP

SC10U25V5KX--L-GP

SC10U25V5KX--L-GP
PX PX PX
2

2 1

2 1
21
2 2
2

3 3
1 4 1 4

ch
10 10
1

9 9
PR8529 PX PX 7 7
2K61R2F--1-GP PR8530 1 2 0R0402-PAD PR8531 1 2 10R2J--L-GP
20141124_KAMUS 8 6
5
8 6
5
1VGA_VSUM2-_1

B PR8532 PC8523 VGA_VDD_RUN_FB_L 1 TP8501 B

1

PC8522 PX
SCD22U10V2KX--L1-GP

PX FDMS3600-02-RJK0215-COLAY--GP FDMS3600-02-RJK0215-COLAY--GP
PC8501 2 1 SCD01U50V2KX--L-GP
11KR2F--L-GP

PX PX ZZ PX PWR Change 84.08S36.037

2

PC8524
1st = 84.08S36.037
2

SCD022U25V2KX--GP

1DY 2

ni
PR8533
NTC-10K-29-GP-U SC330P50V2KX--3GP VGA_VDD_RUN_FB_H 1 TP8502
2nd = 075.06992.0073
PX PR8534 1 2 0R0402-PAD 2 1 1V_VGACORE_S0 1V_VGACORE_S0
PWR_VGA_CORE_UGATE2
PL8501 1ST = 68.R3610.20X
PR8535 SC
2

PWR_VGA_CORE_VSUM- PX 10R2J--L-GP
1 2
PWR_VGA_CORE_PHASE2
2ND = 068.R3610.1001
1 2 COIIL--D36UH-6--GP 1
PR8536

ca
69.60011.201 806R2F--GP
PX AFTP8501
1

PC8525 PWR_VGA_CORE_LGATE2
1ST = 69.60011.201 SCD1U25V2KX--L-GP PX

2
PX PG8509 PG8510
2nd = 69.60037.011
2

2
GAP-CLOSE-PWR--3--GP
20141208_KAMUS PX PT8503

GAP--CLOSE--PWR--3--GP
1
79.33719.L01

SE330U2VDM--L-GP
1

2 1
LT415:PR8536=604R 1ST = 79.33719.L01

PWR_VGA_CORE_PH2

PWR_VGA_CORE_VO2
l
2ND = 79.33719.20C
PR8537
PWR_VGA_CORE_ISUMP 1 PX2
3K65R2F--1-GP

PR8538
PWR_VGA_CORE_ISEN2 1 P2X
10KR2F--2-GP

PWR_VGA_CORE_PWROK PR8544 1 2 0R0402-PAD PWR_VGA_CORE_VSUM- PR8540 1 PX 2

PWR_VGA_CORE_PGOOD 1R2F--GP
A
PX A
PWR_VGA_CORE_ISEN1 PR8543 1 2 10KR2J--3-GP

<Corrre Desiiign>

Wistron Corporation
21F,,, 88, Sec...1, HsiiinTai W u Rd...,,,Hsiiichih,

Eletro-XTechnical Eletro-XTechnical
Taiiipeiii Hsiiien 221,,, Taiiiwan,,, R.O.C...

Title

GPU CORE
Siiize Document Number Rev
A2
LV115 SKL-U -1
Date: Monday,,, Aprrriill25, 2016 Sheet 85 off 102
5 4 3 2 1
 5 4 3 2 1

20151106 need Add MOS to Control 1D35V_EN# IN SB version

3D3V_VGA_S0
3D3V_S0 to 3D3V_VGA_S0 Transfer Discharge circuit 1V_VGACORE_S0 1D8V_VGA_S0 GPU PWR Sequencing
Peak current: 25mA 3D3V_VGAS0

Eletro-XTechnical
1D5V_VGA_S0

1
1

1
R8606
Q8601
AO3413L-GP
R8603
24R2J--GP
R8604
24R2J--GP
75R2F-2-GP => 0D95V_VGA_S0/1D8V_VGA_S0
S D PX
3D3V_S0 R8605 DY DY

DIS_1D8V_NV_2L
75R2F-2-GP
PX => 1D35V_VGA_S0

2
Q8307_D
1 PX

G
R8607 84.03413.B31
100KR2J--1-GP

D
PX Q8602 => VGA_CORE

Notice:ZZ.2N702.J3101
DIS_FBVDD_L
2

2N7002K--2-GP
3.3V_ALW_1
3D3V_VGAdischarge 0D95V_VGA_S0 84.2N702.J31

5 1D35V_EN#
2ND = 84.2N702.031 All the ASIC supplies must reach their respective
3rd = 84.2N702.W31 nominal voltages withing 20ms of the start of the
6

2
D Q8603 D
2N7002KDW--GP R8608 DY

S
84.2N702.A3F 75R2F-2-GP ramp-up sequence, though a shorter ramp-up

4
Q8604 1D35V_EN#

1
2nd = 075.063D1.007C PX PX 2N7002KDW--GP duration is preferred. The maximum slew rate on

D
R8609
1

1
84.2N702.A3F 75R2F-2-GP

Notice:ZZ.2N702.J3101
Q8605
2nd = 075.063D1.007C PX PX 2N7002K--2-GP
all rails is 50mV/us.
Different To Intel, AMD Is High Active 3.3V_RUN_VGA_1

1
84.2N702.J31

2
20,85 PE_GPIO1 2ND = 84.2N7I0t2i.s03r1ecommended that the 3.3V rail ramp up first.

DIS_0D95V_NV_L
3rd = 84.2N702.W31
1

S
PX

1D35V_EN# 2
R8601
10KR2J--L-GP
1D35V_EN# It is recommended that the 0.95V rail reach at least
PX C8602 90% of its normal value no later than 2ms from the
2 1

SCD1U25V2KX--L-GP
2

SB: DY start of VDDC ramping up.

Follow BDW pull down to GDN

1D8V_S5 1D8V_S5 to 1D8V_VGA_S0 Transfer Peak current: 311mA

1
R8620
2 3D3V_VGA_S0
1D0V_S5 to 0D95V_VGA_S0 Transfer 1D8V_VGA_S0
0R0402-PAD
1D8_0D95VGA_EN

U8601
C8603
SC1U10V2KX--L1-GP
GND 15
2 1

C8607

El
PX 1
VIN1#1 VOUT1#14 14 SCD1U16V2KX--L-GP
2 VIN1#2 VOUT1#13 13

2 1
R8610 1 2 1D8VGA_EN 1D8VGA_EN 3
EN1 SS1
12 VTT_CT_1D8VG PX
0R0402-PAD 1D0V_S5
5V_S0 4 PX
BIAS GND 11 0D95V_VGA_S0
1D0VGA_EN 5 VTT_CT_0D95VG
EN2 SS2 10
6 VIN2#6 VOUT2#9 9
7 8
Peak current: 2A
C8611 SC1U10V2KX- VIN2#7 VOUT2#8
R8612 1 2 1D0VGA_EN -L1-GP C8608 C8609
2 1

0R0402-PAD PX APL3523AQBII--TRG--GP SC1KP50V2KX--1GP SC1KP50V2KX--1GP

1

2 1

2 1
PX PX C8614
C8604 C8605 SCD1U16V2KX--L-GP

2 1
SCD1U25V2KX--L-GP SCD1U25V2KX--L-GP PX
2

DY DY

et
C
NN30331A for VGA_1D5V(For VRAM DDR3) C

ro
Reference OSLO 1D5V_VGA_S0

DCBATOUT PWR_VGA_DCBATOUT_1D5V

-X
PG8601
1 2 GAP-CLOSE-PWR-3--GP

PG8602 5V_S5
1 2 GAP-CLOSE-PWR-3--GP

1D5V_VGA_S0

MAG. 7 x 7 x 3.0mm
1

PC8632
SC1U10V2KX--L1-GP
PX DCR: 9m~10mOhm
TDC : 6A
2

Idc : 10 A , Isat : 22A

Te
U8603 1D5V_VGA_S0 PC8623

SC22U6D3V5MX--L3-GP

2 1
PX DY
PWR_VGA_DCBATOUT_1D5V 21 18 PWR_1D5V_PH PL8603 1 2 PC8613 PC8614 PC8615 PC8617
VC C LX#18
17
LX#17 IIND-1UH-129-GP-U
16
LX#16 68.1R010.20D
11
LX#11

2
7 IN 10 PX PX PX DY
LX#10

2
8 IN PC8612
PWR_11D5V_B2T SCD1U25V2KX--L-GP
BST 20

SC22U6D3V5MX--L3-GP

SC22U6D3V5MX--L3-GP

SC22U6D3V5MX--L3-GP
9 IN

SCD1U25V2KX-GP
2

1
PR8623 PG8609
95K3R2F-GP
PX GAP--CLOSE--PWR--6--GP
PWR_1D5V_VFB
FB 5
1

1
PC8619 PC8621 PC8628 PC8629 1 2 PWR_1D5V_TON 6 TON
PC8618 PX PX PX PX
SC10U25V5KX--L-GP

SC10U25V5KX--L-GP

SC10U25V5KX--L-GP

SC10U25V5KX--L-GP

SCD1U50V3KX--L-GP PX PWR_1D5V_PG 1 PGOOD AGND 4

2

DY PWR_1D5V_VFB_A
PWR_1D5V_EN 2 EN 19
PGND

ch
PGND 14
PWR_1D5V_PFM 3 13
PFM# PGND
PGND 12
PWR_1D5V_SS 22 15
SS PGND R8623
R1 PC8624
1

66K5R2F-GP
2 1

SC220P50V2KX--3GP
PR8626 AOZ2260QII--10-GP PX DY
100KR2F-L1-GP
PX
2

PX PC8627
2 1

SCD01U50V2KX--L-GP
2

B B
PX
1
1

R8622
75KR2F-GP R2 Vo=0.8x(1+R1/R2)
PX

ni
=0.8x(66.5+75/75)
2

Add For Discharge Circuit 20151123 3D3V_S0 =1.509

1

Q8606 PR8622
PX 10KR2J--3-GP PWR_1D5V_EN 10KR2J--3-GP
3D3V_VGA_S0 R8624 1 2 G
PX
2
1

D 1D35V_EN#

ca
C8620 PC8631
SC1KP50V2KX-1GP

SCD22U10V2KX--L1-GP DY S PX
2

Notice:ZZ.2N702.J3101
PX 2N7002K--2-GP
84.2N702.J31
2ND = 84.2N702.031
3rd =84.2N702.W31

3D3V_S5
1

PR8624
100KR2J--1-GP
PX

l
2

PWR_1D5V_PG

A A

Eletro-XTechnical Eletro-XTechnical
<Core Desiiign>

Wistron Corporation
21F, 88, Sec...1, Hsiiin Tai W u Rd.,,,Hsiiichih,
Taipei Hsiiien 221, Taiwan, R...O...C...

Title
GPU Discrete Power
Siize Document Number Rev
A1 LV115 SKL-U -1
Date: Monday,,, Apriiilll 25, 2016 Sheet 86 offf 102

5 4 3 2 1
 5 4 3 2 1

Eletro-XTechnical

D D

16 XDP_PREQ# 1 TP9911
TPAD14--OP-GP
16 XDP_PRDY# 1 TP9901
TPAD14--OP-GP

1 TP9915
6 CFG3 TPAD14--OP-GP

1 TP9938
6 ITP_PMODE TPAD14--OP-GP

1 TP9904
TPAD14--OP-GP
4 PROC_TCK 1 TP9902
TPAD14--OP-GP

El
1 TP9908 TPAD14--OP-GP
4 PROC_TDI 1 TP9903
TPAD14--OP-GP

1 TP9937 TPAD14--OP-GP
4 PROC_TMS 1 TP9905
TPAD14--OP-GP
1 TP9939
TPAD14--OP-GP
4 PROC_TRST# 1 TP9906
TPAD14--OP-GP

et
1 TP9940
TPAD14--OP-GP
1 TP9936
4 PCH_JTAG_TDO TPAD14--OP-GP

4 PCH_JTAG_TCK 1 TP9907 TPAD14--OP-GP

C C

ro
-X
Te
ch
B B

ni
ca
l
A A

<Corrre Desiiign>

Wistron Corporation
21F,,, 88, Sec...1, HsiiinTai W u Rd...,,,Hsiiichih,

Eletro-XTechnical Eletro-XTechnical
Taiiipeiii Hsiiien 221,,, Taiiiwan,,, R.O.C...

Title

Reserved
Siiize Document Number Rev
A2
LV115 SKL-U -1
Date: Monday,,, Aprrriill25, 2016 Sheet 99 off 102
5 4 3 2 1
 5 4 3 2 1

Main Func = CPU

UNSLICED GT
+VCCGT
VCCIO
Eletro-XTechnical
+VCCIO

+VCCIO(ICCMAX.=2.73A)
1

1
C1147 C1148 C1149 C1150 1U

1
C1136 C1138 0402 x 6
SC18P50V2JN--1-GP

DY
2

1
C1151 C1152 C1153 C1154
SC1U10V2KX--1GP

SC1U10V2KX--1GP

SC18P50V2JN--1-GP

SC1U10V2KX--1GP

SC18P50V2JN--1-GP

21

2
SC1U10V2KX--1GP

SC1U10V2KX--1GP

SC1U10V2KX--1GP

SC1U10V2KX--1GP
D D
DY DY

GTUS 20141114 Alden

PCH DERIVED RAILS +VCCGT
+V_VCCGTUS_VR can merge to +VCCGT

+VCCPGPPA(ICCMAX.=0.05A)

+V1.8A +VCCPGPPA

R1111

1 DY 2

1
PC1104 PC1105 PC1106 PC1107
3D3V_S5 0R3J--0-U--GP

El
SC22U6D3V5MX--L3-GP SC22U6D3V5MX--L3-GP SC22U6D3V5MX--L3-GP SC22U6D3V5MX--L3-GP
23e 23e 23e 23e

2
1 R1109 2

0R0603-PAD

et
C C
3D3V_S5 +VCCPAZIO

ro
L1101
1 2
BLM15EG221SN1D--GP
68.00084.C21

1D0V_S5 +VCCAPLL_1P0

-X
L1102
1 2
BLM15EG221SN1D--GP
68.00084.C21

Te
ch
1D0V_S5

1D0V_S5 +VCCAMPHYPLL_1P0
1

1
C1174 C1182 C1104 C1105 1 R1102 2
B B
0R0603-PAD
2

2
SC1U10V2KX-1GP

SC18P50V2JN--1-GP

SC1U10V2KX--1GP

SC1U10V2KX-1GP
C1181
SC22U6D3V5MX--L3-GP C1172

2 1

2 1
SC1U10V2KX-1GP

ni
DY DY DY

ca
l
VCC_CORE

3D3V_S5 +VCCPGPPD_TCH

1 R1108 2
1
1

C1101 C1102 C1103 C1116 C1117

1U 0402 x 5 0R0603-PAD
21

21

+V1.8A
SC1U10V2KX--1GP

SC1U10V2KX--1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP

A R1129 A
1 DY 2 0R3J--0--U-
GP

+VCCPGPPD_TCH
<Corrre Desiiign>
U-line 23e 28W
IccMax current-10ms max = 34 A C1183
Wistron Corporation
SC10U6D3V3MX-GP

21F,,, 88, Sec...1, HsiiinTai W u Rd...,,,Hsiiichih,

2 1

Eletro-XTechnical Eletro-XTechnical
Taiiipeiii Hsiiien 221,,, Taiiiwan,,, R.O.C...

Title

CPU_(Power CAP2)
Siiize Documenttt Numberr Rev
A2
LV115 SKL-U -1
Date: Monday,,, Aprrriill25, 2016 Sheet 11 off 102
5 4 3 2 1
 D

-1
Wistron Corporation

Rev

102
21F,,, 88, Sec...1, HsiiinTai W u Rd...,,,Hsiiichih,
Taiiipeiii Hsiiien 221,,, Taiiiwan,,, R.O.C...

off
CPU_(Power CAP1)

Sheet 10
Eletro-XTechnical

Eletro-XTechnical
LV115 SKL-U
1

1
Date: Monday,,, Aprrriill25, 2016
Siiize Documenttt Numberr
<Corrre Desiiign>

Title

A2
l
ca
2

2
ni
(#543016 PDG)

ch
Te
-X
3

3
ro
et
SC1U10V2KX--L1-GP
PC1064 SC22U6D3V5MX--L3-GP
1 2 1 2
PC1025 PC1026 PC1027

SC1U10V2KX--L1-GP
PC1063
2 1 SC22U6D3V5MX--L3-GP
PC1060 1 SC10U6D3V3MX--L-GP 2
SC1U10V2KX--L1-GP 1 2
El
PC1062
1 2
PC1059 1 SC10U6D3V3MX--L-GP 2 SC22U6D3V5MX--L3-GP
SC1U10V2KX--L1-GP
PC1061 1 2
21 SC22U6D3V5MX--L3-GP
PC1058 1 SC10U6D3V3MX--L-GP 2
1 2
1 2 SC22U6D3V5MX--L3-GP
PC1057 SC10U6D3V3MX--L-GP
1 2
1 2

PC1047 PC1048 PC1049 PC1050 PC1051 PC1052 PC1053

PC1056 SC10U6D3V3MX--L-GP SC22U6D3V5MX--L3-GP
1D2V_S3

1 2
1 2
PC1055 SC10U6D3V3MX--L-GP
SC22U6D3V5MX--L3-GP
1 2
4

4
SC22U6D3V5MX--L3-GP
1 2 SC22U6D3V5MX--L3-GP
1 2
SC22U6D3V5MX--L3-GP
SC22U6D3V5MX--L3-GP
1 2
1 2
SC22U6D3V5MX--L3-GP SC22U6D3V5MX--L3-GP

PC1044 PC1069 PC1070 PC1071 PC1072 PC1073 PC1074 PC1075 PC1076 PC1077 PC1078 PC1079 PC1080 PC1081
1 2 1 2
SC22U6D3V5MX--L3-GP
SC22U6D3V5MX--L3-GP
1 2
SC22U6D3V5MX--L3-GP 1 2

PC1045 PC1046
VCCSA
SC22U6D3V5MX--L3-GP
1 2 SC22U6D3V5MX--L3-GP
1 2
PC1010 PC1011 PC1012 PC1013 PC1014 PC1015 PC1016 PC1017 PC1018 PC1019 PC1020

1 2
SC22U6D3V5MX--L3-GP SC22U6D3V5MX--L3-GP SC22U6D3V5MX--L3-GP

PC1089 PC1090
SC22U6D3V5MX--L3-GP SC22U6D3V5MX--L3-GP

+VCCSA
1 2 1 2 1 2
1 2 1 2

Eletro-XTechnical
SC22U6D3V5MX--L3-GP SC22U6D3V5MX--L3-GP
PC1001 PC1002 PC1003 PC1004 PC1005 PC1006 PC1007 PC1008 PC1009

SC22U6D3V5MX--L3-GP SC22U6D3V5MX--L3-GP
1 2 2 1

SC1U10V2KX--L1-GP
1 2 1 2
SC22U6D3V5MX--L3-GP SC22U6D3V5MX--L3-GP
SC22U6D3V5MX--L3-GP SC22U6D3V5MX--L3-GP
1 2 1 2
1 2 1 2
SC22U6D3V5MX--L3-GP SC22U6D3V5MX--L3-GP

PC1028

DY
PC1031 PC1032 PC1033 PC1034 PC1041 PC1042 PC1043

PC1086 PC1087
SC22U6D3V5MX--L3-GP SC22U6D3V5MX--L3-GP SC22U6D3V5MX--L3-GP SC22U6D3V5MX--L3-GP

PC1038 PC1039
IccMax current-10ms max = 34 A

1 2 1 2

IccMax current-10ms max[A] = 67 A

1 2 1 2 1 2 1 2
SC22U6D3V5MX--L3-GP SC22U6D3V5MX--L3-GP
1 2 SC22U6D3V5MX--L3-GP SC22U6D3V5MX--L3-GP SC22U6D3V5MX--L3-GP

1D0V_S5
1 2 1 2 SC22U6D3V5MX--L3-GP

SLICED GT
1 2 1 2 1 2
SC22U6D3V5MX--L3-GP SC22U6D3V5MX--L3-GP SC18P50V2JN--1-GP

PC1085
1 2
SC22U6D3V5MX--L3-GP SC22U6D3V5MX--L3-GP SC22U6D3V5MX--L3-GP

PC1021 PC1022 PC1023 PC1024

1 2 1 2 1 2
Main Func = CPU

DY DY
1 2 1 2 1 2
5

5
SC22U6D3V5MX--L3-GP SC22U6D3V5MX--L3-GP SC18P50V2JN--1-GP

PC1084
U-line 23e 28W

DY
+VCCIO(ICCMAX.=2.73A)
SC22U6D3V5MX--L3-GP SC22U6D3V5MX--L3-GP SC22U6D3V5MX--L3-GP
1 2 1 2 1 2
CORE

U-line 23e 28W

1 2 1 2 1 2
SC22U6D3V5MX--L3-GP SC22U6D3V5MX--L3-GP SC22U6D3V5MX--L3-GP

PC1083
SC22U6D3V5MX--L3-GP SC22U6D3V5MX--L3-GP SC22U6D3V5MX--L3-GP
1 2 1 2 1 2
1 2 1 2 1 2
SC22U6D3V5MX--L3-GP SC22U6D3V5MX--L3-GP SC22U6D3V5MX--L3-GP

PC1082
SC22U6D3V5MX--L3-GP SC22U6D3V5MX--L3-GP SC22U6D3V5MX--L3-GP

PC1035 PC1036
1 2 1 2 21 SC22U6D3V5MX--L3-GP
1 2 1 2 1 2
1 2
SC22U6D3V5MX--L3-GP

VCC_CORE

+VCCIO

+VCCGT
1 2

DY
D

A
 5 4 3 2 1

Eletro-XTechnical

D D
H1 H2 H3 H4 H5
STF237R128H42-7-GP STF237R128H42-7-GP STF237R128H42-7-GP STF237R128H42-7-GP STF237R128H42-7-GP
SP1 SP2
H6 SPRIING--43--GP-U SPRIING--43--GP-U
STF236R128H93-GP 34.4WZ01.001 34.4WZ01.001 34.4WZ01.001 34.4WZ01.001 34.4WZ01.001

1
34.4LY03.201 34.15J03.001 34.15J03.001
PX PX

1
1

1
1ST = 34.4LY03.201
1ST = 34.4WZ01.001 1ST = 34.4WZ01.001 1ST = 34.4WZ01.001 1ST = 34.4WZ01.001 1ST = 34.4WZ01.001
2ND = 34.4LY03.101
2ND = 34.4WZ01.101 2ND = 34.4WZ01.101 2ND = 34.4WZ01.101 2ND = 34.4WZ01.101 2ND = 34.4WZ01.101

H18

El
HT6BE75R26-U--45-GP

ZZ..00PAD..EH1
H11
H8 H12 H13 H14 H15
HOLE237R103-GP HT9X9B9X9R31-S--GP HT9X9B9X9R31-S--GP HT9X9B9X9R31-S--GP HT9X9B9X9R31-S--GP H16 H19
ZZ..00PAD..EJ1 ZZ.00PAD..GG1 ZZ.00PAD..GG1 ZZ.00PAD..GG1 ZZ..00PAD.G. G1 HOLE237R103-GP HOLE237R103-GP

1
ZZ..00PAD..EJ1 ZZ.00PAD..EJ1

et
1

1
ZZ..00PAD..571

HOLE355X355R111-S1-GP

C C
DCBATOUT

ro
DCBATOUT
1

EC8601 EC8602 EC8603 EC8607 EC8608 EC8612 EC8621 EC8622

2

1
SCD1U50V3KX--L-GP

SCD1U50V3KX--L-GP

SCD1U50V3KX--L-GP

SCD1U50V3KX--L-GP

SCD1U50V3KX--L-GP

SCD1U50V3KX--L-GP

SCD1U50V3KX--L-GP

SCD1U50V3KX--L-GP

EC8604 EC8605 EC8606 EC8609 EC8610 EC8611

SC1U50V5ZY--1-GP--U

SC1U50V5ZY--1-GP--U

SC1U50V5ZY--1-GP--U

SC1U50V5ZY--1-GP--U

SC1U50V5ZY--1-GP--U
-X
2

2
SCD1U50V3KX--L-GP
Te
3D3V_S0
3D3V_S5 5V_S5 1D0V_S5 +VCCSA

ch
1

EC8616 EC8617
RFC8923 RFC8924 RFC8925 RFC8926 RFC8928
SCD1U25V2KX--L-GP

SCD1U25V2KX--L-GP

DY DY
2

DY DY DY DY DY
1

1
B EC8613 C8601 EC8614 EC8615 EC8618 EC8619 EC8620 B

SC8P50V2DN--1GP

SC8P50V2DN--1GP

SC8P50V2DN--1GP

SC8P50V2DN--1GP

SC8P50V2DN--1GP
2 1

2 1

21

21

21

DY DY DY DY DY DY
SCD1U25V2KX--L-GP

SC1U10V2KX--1GP

SCD1U25V2KX-L--GP

SCD1U25V2KX--L-GP

SCD1U25V2KX-L--GP

SCD1U25V2KX--L-GP

SCD1U25V2KX--L-GP
2

2
ni
ca
CL7 CL8
SPRIING--166--GP SPRIING--166--GP

34.41L50.001 34.41L50.001

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Wistron Corporation
21F,,, 88, Sec...1, HsiiinTai W u Rd...,,,Hsiiichih,

Eletro-XTechnical Eletro-XTechnical
Taiiipeiii Hsiiien 221,,, Taiiiwan,,, R.O.C...

Title

UNUSED PARTS/EMI Capacitors

Siiize Document Number Rev
A2
LV115 SKL-U -1
Date: Monday,,, Aprrriill25, 2016 Sheet 89 off 102
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