A 2.

4 GHz Fully Integrated Doherty Power Amplifier

Using Series Combining Transformer
Ercan Kaymaksüt, Patrick Reynaert
ESAT-MICAS, Katholieke Universiteit Leuven
Leuven, Belgium
[email protected] , [email protected]

Abstract—A 2.4 GHz fully integrated Doherty power amplifier is

fabricated in standard 90nm CMOS technology. The power
amplifier employs a series combining transformer to eliminate
bulky λ /4 transmission lines. An efficiency enhancement at
power back-off is measured. The two-stage Doherty PA has 16.6
dB small-signal gain and produces 20.5 dBm saturated output
power with a drain efficiency of 30.9% (PAE 26.7%) by using 2
V supply voltage. The PA is tested with 54 Mbps WLAN 802.11g
signal and the PA meets the stringent EVM and spectral mask
requirements at 12.9 dBm average output power with a drain
efficiency of 14.1% (PAE 11.5%).

I. INTRODUCTION
The growing demand on high data rate communication
systems leads to an increasing amount of amplitude
modulation in modulation schemes. Therefore, power
amplifiers have to operate at back-off to cover the required
dynamic range. Conventional linear power amplifiers operate
with high efficiency only at the vicinity of peak output power.
The Doherty architecture can be used to enhance the back-off Figure 1. Schematic of the Doherty Power Amplifier
efficiency of linear amplifiers. In this architecture an auxiliary
amplifier is employed to keep the main amplifier in saturation WLAN 802.11g standard. The power amplifier demonstrates
for a 6dB power range. In a conventional Doherty amplifier, high linearity and efficiency enhancement at power back-off
an impedance inverter ( λ /4 transmission line) is used to which are essential for high-data rate communication systems.
achieve active load modulation. However bulky impedance The design of the 2.4 GHz Doherty amplifier is presented
inverters limit the performance of fully integrated in Section II. In section III, measured large signal transfer
implementation of Doherty amplifier. Previous integrated characteristics and measurement results with 54 Mbps WLAN
CMOS Doherty amplifiers either suffer from low efficiency 802.11g signal are given. The paper is concluded with section
due to low quality passives [1-2] or use off-chip output IV.
matching circuitry [3].
In this paper, a series combining transformer is proposed II. DESIGN OF 2.4 GHZ DOHERTY PA
to function as Doherty combiner. The series combining A Doherty amplifier combines the output powers of two
transformer is an efficient way of power combining, amplifiers. One of the amplifier is biased in class AB mode
impedance matching and differential to single ended (main amplifier) and provides linear amplification for all the
conversion [4]. Employing independent windings for primary power range while the other amplifier is biased in class C
inductors increases the flexibility of the architecture. In this mode(auxiliary amplifier), only contributes to the output
way, efficiency enhancement at back-off can be obtained by power for the upper 6 dB power range. The auxiliary amplifier
changing the number of combined amplifiers [5]. In the starts to conduct current at the power level that the main
proposed architecture, a class AB amplifier is combined with a amplifier starts to saturate. As the delivered current from the
class C amplifier by using a series combining transformer. A auxiliary amplifier increases, the load impedance seen by the
2.4 GHz fully integrated Doherty amplifier is designed for main amplifier reduces. Therefore, active load modulation

978-1-4244-6664-1/10/$26.00 ©2010 IEEE 302

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 from the auxiliary amplifier keeps the main amplifier in VDD out VDD
saturation for a 6 dB power range. This brings the efficiency
enhancement at power back-off. In addition, combining the
output powers of class AB and class C amplifiers increases the
overall linearity of the amplifier since the auxiliary amplifier
shows gain extension behavior while the gain of the main in2
amplifier compresses. Therefore, linearized transfer function
in1
is obtained until the saturation of the auxiliary amplifier [6].
The schematic of the fully integrated Doherty power
amplifier is given in Fig.1. An input balun transforms the
single ended input to differential. Two differential drivers are Figure 2. Layout of the 2x1:1 Series Power Combining Transformer
used to drive the main and the auxiliary amplifiers unequally.
An additional matching inductor is used before the auxiliary 0.76
amplifier to compensate the phase and the gain mismatch
between the main and the auxiliary amplifiers. The series 0.74

combining transformer acts as an impedance inverter and 0.72

output balun.

Efficiency
0.7

A. Design of the Integrated Doherty Combiner 0.68

The Doherty combiner shapes the output waveforms of the 0.66

main and the auxiliary amplifiers while combining the output 0.64
powers. The load impedance seen by the amplifiers should be
adequate for highly efficient amplification and the load 0.62
0 0.2 0.4 0.6 0.8 1
impedance of the main amplifier should reduce with I Aux / I Main

increasing output power. Figure 3. Simulated Efficiency of Series Combining Transformer.with

In this design, a series combining transformer is optimized respect to the Ratio of the Auxiliary and the Main Amplifier Currents
for Doherty operation. Output impedance of the amplifiers
does not influence the combining efficiency of the transformer 50
Real ZL
while the input windings are driven by identical currents [4]. 45 Imag ZL
However, in the Doherty architecture, the ratio of the main 40 ZL tuned with shunt C
Impedance(ohms)

and the auxiliary amplifier currents changes with respect to the

35
output power. At low power region only the main amplifier
generates current; therefore, the efficiency of series combining 30

transformer should be optimized considering the output 25

impedance of the auxiliary amplifier. Simulations revealed 20
that capacitive impedance on the auxiliary winding reduces 15
the efficiency of the transformer for the low power region.
10
Therefore, the series combining transformer designed such 0 0.2 0.4 0.6 0.8 1
that the auxiliary amplifier does not require a capacitor to tune I Aux / I Main

the input impedance of the transformer. Figure 4. Simulated Load Impedance of the Main Amplifier with respect to
A single thick metal (3.2 um copper) is available in the the Ratio of the Auxiliary and the Main Amplifier Currents
process and therefore planar layout is used. In Fig. 2 the
symmetrical layout is adopted for the transformer to minimize The simulated combining efficiency of the transformer is
the load impedance mismatch between the differential given in Fig 3. with respect to the ratio of the auxiliary and the
transistors. This mismatch in differential load impedance is main amplifier currents. At the low power region where the
mainly caused by asymmetrical mutual and capacitive class C auxiliary amplifier does not generate current; some of
coupling. The secondary winding is interleaved to increase the the power generated by the main amplifier dissipated at the
coupling factor. The transformer is simulated using ADS non-operational auxiliary winding. Therefore efficiency of the
Momentum and the parameters are optimized to compromise transformer is degraded. Transformer efficiency peaks while
the efficiency at low power region and at high power region. both amplifier generates the same RF current and reaches
Combining efficiency of the transformer is defined by: 74%.
The simulated active load modulation in the series
Pout (1)
η= combining transformer is given in Fig.4. showing that the real
PMain + PAuxiliary part of the load impedance seen by the main amplifier

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 increases due to the active load modulation of the auxiliary
amplifier. However the real impedance obtained by tuning the
load impedance with a shunt capacitor reduces with the
increasing IAux. Therefore, considering the parasitic
capacitances of the main amplifier; the main amplifier can be
designed to deliver higher output power due to the active load
modulation of auxiliary amplifier.

B. Amplifier Design Considerations

Differential cascode configuration is adopted for the main
and the auxiliary amplifiers. The 90nm transistor is cascoded
with a high breakdown device (Lmin=0.25 um) to compromise
between the gain and the voltage swing.
Figure 5. Die Photo of the two stage Doherty Amplifier
The main amplifier supplies the linear amplification for the
whole power range. Therefore, the bias point of the common 25 110
source transistor is selected to maximize the linearity. The 22
Output Power(dBm)
Gain(dB) 100
VBIAS1 and the VDD (Fig.1) are selected as 1.5 V and 2 V 19
I Main
I Auxiliary 90

respectively to distribute the voltage stress on both transistors.

DC Current Consumption(mA)
Output Power(dBm), Gain(dB)
16 80

13 70
The input impedance of the transformer is tuned with a 10 60
1.2pF shunt capacitor at the main amplifier side. The main 7 50
amplifier is sized for producing maximum output power with 4 40
the load impedance when IAux=IMain(Fig.4) and preserving high 1 30

efficiency for varying load impedances. −2 20

−5 10
The auxiliary amplifier is biased for class C mode of −8 0
operation. The gate bias voltage of the common source −25 −20 −15 −10 −5
Input Power Power(dBm)
0 5 10

transistor for the auxiliary amplifier is selected as 0.2 V while

Figure 6. Single-tone Measurement results of Doherty Amplifier at 2.4 GHz
the threshold voltage for the low leakage transistor is 0.45 V.
The VBIAS2 is selected as 1.4 V to reduce the voltage stress on
the common source transistor. The auxiliary amplifier is sized III. MEASUREMENT RESULTS
to operate efficiently with the impedance seen by the The chip has been measured by using RF wafer probes.
transformer. Shunt capacitor is not used at the auxiliary The large signal transfer characteristic of the Doherty PA is
winding to avoid the loading of the transformer at the low given in Fig.6. for 2.4 GHz single tone measurements. The
power region.
amplifier has 16.6 dB small signal gain and the 1 dB gain
The drivers consist of a differential common source compression occurs at 17.5 dBm output power. The saturated
amplifier with an on-chip RF choke. The main and the power of the PA is measured as 20.5 dBm. Fig.5 indicates
auxiliary amplifiers deliver the same amount of power at the that the DC current consumption of the auxiliary amplifier
peak power level. Therefore, the driver of the auxiliary increases rapidly after -3 dBm input power. The auxiliary
amplifier is designed to have around 2 times more gain than amplifier only conducts current when high output power is
the driver of the main amplifier at peak power. An additional required.
matching network is used between the driver and the auxiliary Fig.7 demonstrates the efficiency enhancement behavior of
amplifier to compensate the phase and the gain mismatch the Doherty power amplifier at power back-off. The
between the main and the auxiliary amplifiers. The driver of measured peak drain efficiency of the Doherty PA is 30.9%
the main amplifier is designed for linearity while the driver of
(peak PAE 26.7%) and the drain efficiency at 5 dB power
the auxiliary amplifier is biased around the threshold voltage
back-off is 3.2% larger than the drain efficiency of ideal
as linearity is not required to drive a class C amplifier. The
supply voltage for the drivers (VD) is selected as 0.75 V. Class B PA with the same peak drain efficiency. The
efficiency enhancement compared to ideal class A PA is
The chip photo with a total die size of 1.2 mm x 1.6 mm is 10.8% at 5 dB back-off.
given in Fig.5. The compact layout leads a strong coupling The two tone test is performed on the PA at 2.4 GHz with
from the series combining transformer to the input balun, the a tone spacing of 5 MHz. The measured third order inter
drivers and the DC feed lines. The differential and common modulation products with respect to output power is plotted
mode feedback/feed forward is simulated and the layout is in Fig. 8. Due to the linearization behavior of the Doherty
optimized by using ADS Momentum EM simulator. PA, the third order products are lower than -30dBc at 16.4
dBm output power.

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 Measured PAE
30
Measured Drain Efficiency
Ideal Class B PA with same peak efficiency
Ideal Class A PA with same peak efficiency
25

20
Efficiency(%)

15

10

0
5 10 15 20
Output Power(dBm)

Figure 7. Measured Drain Efficiency and PAE at 2.4 GHz

Figure 10. Measured Output Spectrum of the PA at 12.9 dBm average output
power
−10
−15
−20 IV. CONCLUSION
−25
A fully integrated Doherty amplifier in standard 90 nm
IMP3(dBc)

−30
−35
CMOS technology is demonstrated. A series combining
−40 transformer is employed as an impedance inverter and balun.
−45 The Doherty PA meets the EVM and spectrum mask
−50 requirements of 2.4 GHz WLAN 802.11g standard at 12.9
−55 dBm average output power with a PAE of 11.5%.The
−60
−5 −2.5 0 2.5 5 7.5 10 12.5 15 17.5 20 proposed Doherty amplifier is suitable for SoC architectures.
Output Power(dBm)

Figure 8. Two-tone Measurement Results of the Doherty PA at 2.4 GHz ACKNOWLEDGMENT

with 5 MHz tone spacing
Authors wish to kindly acknowledge Rohde&Schwarz-
Belgium for their support during the measurement setup and
18
PAE(%)
−10
Infineon Technologies Austria-Villach to support this
15
Drain Efficiency(%)
EVM(dB) −15 research.
12 −20
Efficiency(%)

REFERENCES
EVM(dB)

9 −25
[1] M. Elmala, R. Bishop, “A 90nm CMOS Doherty Power Amplifier with
Integrated Hybrid Coupler and Impedance Transformer ”, IEEE Radio
6 −30
Frequency Integrated Circuits (RFIC) Symposium 2007, pp: 423 – 426,
3 −35
2007.
[2] Yang Li-Yuan, Chen Hsin-Shu, Chen Y.-J.E, “A 2.4 GHz Fully
0 −40 Integrated Cascode-Cascade CMOS Doherty Power Amplifier”, IEEE
−2 0 2 4 6 8 10 12 14 16
Output Power(dBm) Microwave and Wireless Components Letters, vol. 18. issue 3, pp197-
199, 2008.
Figure 9. Measured EVM and Efficiency with 54 Mbps WLAN 802.11g [3] N. Wongkomet, L. Tee, P.R. Gray, “A + 31.5 dBm CMOS RF Doherty
signal Power Amplifier for Wireless Communications”, IEEE Journal of
Solid-State Circuits, vol. 41, issue 12, pp 2852 – 2859, 2006.
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modulated signal. The EVM requirement for a 54 Mbps transformer-a new power-combining and impedance-transformation
technique”, IEEE Trans. Microwave Theory and Techniques, vol 50,
signal is -25dB and the output spectrum should satisfy the pp. 316 -331, Jan 2002.
spectrum mask. [5] D. Chowdhury, C. D. Hull, O. B. Degani, Y. Wang, A. M Niknejad, “A
Fig. 9. shows the measured efficiency and the EVM with Fully Integrated Dual-Mode Highly Linear 2.4 GHz CMOS Power
54 Mbps modulated signal. The power amplifier delivers 12.9 Amplifier for 4G WiMax Applications”, Journal of Solid-State Circuits,
dBm average output power with a drain efficiency of 14.1% pp. 3393 – 3402, Dec 2009.
(PAE 11.5%) while EVM is better than -25 dB. The output [6] Steve C. Cripps, “RF Power Amplifiers for Wireless Communications”,
Artech House Publishers, 1999.
spectrum of the PA for 12.9dBm average output power given
in Fig. 10. satisfies the spectrum mask requirement.

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