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Nano Ca2

This document discusses MOSFET scaling. It defines scaling as reducing the critical parameters of a MOS transistor to improve performance while maintaining basic operational characteristics. Scaling involves reducing device dimensions, increasing density and functional capacity. It allows more chips per wafer, reducing costs. However, scaling presents challenges like changes to electrical characteristics and difficulties in fabrication. The document discusses types of scaling, their effects on device performance, and concludes different scaling approaches are suitable depending on the application's requirements for power dissipation or switching speed.

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Somnath Mondal
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17 views

Nano Ca2

This document discusses MOSFET scaling. It defines scaling as reducing the critical parameters of a MOS transistor to improve performance while maintaining basic operational characteristics. Scaling involves reducing device dimensions, increasing density and functional capacity. It allows more chips per wafer, reducing costs. However, scaling presents challenges like changes to electrical characteristics and difficulties in fabrication. The document discusses types of scaling, their effects on device performance, and concludes different scaling approaches are suitable depending on the application's requirements for power dissipation or switching speed.

Uploaded by

Somnath Mondal
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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MOSFET SCALING

NAME: SOMNATH MONDAL


ROLL NO: 34900321012
SEM: 5TH
SUB: NANO ELECTRONICS

DEPARTMENT OF ELECTRONICS & COMMUNICATION


ENGINRREING
COOCH BEHAR GOVERNMENT ENGINEERING COLLEGE
Definition of MOSFET Scaling
Scaling of a MOS transistor means reducing the critical parameter of the device
in accordance with a given criterion in order to improve some performance
features such as Speed, Application, Power Dissipation, and so on while
keeping the basic operational characteristics unchanged.
Scaling of a MOS transistor is concerned with reducing the dimension of the
device. The size of a MOS transistor is reduced by a factor of 0.7 in each
technology generation [1]. Scaling results in the decrease of the dimensions of
a MOS device, and thus increases the device density and functional capacity of
the chip. More number of smaller MOS transistors is packed into a smaller chip
area, and thus increases the device density and functional capacity of the chip.
The cost of a VLSI chip depends upon the number of chips that can be
produced per wafer. Smaller MOS transistors reduce the chip area, and thus
allow more chips per wafer. This reduces the overall fabrication cost of the
chip. MOSFET capacitances are also reduced, which in turn reduces the output
switching time and switching power dissipation [1]. Despite some of the
advantages, scaling of MOS device presents a series of challenges to device
design. The electrical characteristics of a MOS transistor change with the
reduction in the device dimensions. Further reducing the size of MOS
transistors is restricted due to difficulties in device fabrication process and need
for low voltages. Lowering the supply voltage reduces the switching speed of a
MOS transistor. So, in order to maintain the same switching speed, its
threshold voltage should be reduced at the same rate as the supply voltage is
reduced. However, low threshold voltage MOS transistor results in increasing
the subthreshold leakage power dissipation [2-3]. Thus, the relationship
between power dissipation and switching speed is critical in obtaining optimal
scaled MOS device. The internal MOS transistor characteristic is changed with
the reduction in the dimension of MOS device, and thus the current flow
characteristics also changes [4-5]. MOSFET characteristics degrade with the
reduction in its physical dimension. Main characteristics are threshold voltage
and subthreshold swing. Threshold voltage decreases and subthreshold swing
increases because of two-dimensional (2-D) electrostatic charge sharing
between the gate and the source-drain regions [6-7]. Consequently, the on-to-
off current ratio is reduced substantially, which results in a significant increase
in standby power and compromised overall performance [7]. Weaker electrical
performance due to scaling of MOS transistor further necessitate for new
initiatives in improving the performance of the device.

Advantages of scaling in MOSFET:


• Packaging Density: The packing density of the device improves as a result of scaling
hence we can fit more transistors in the same space as before.
• Size Chip: As we can pack more number of transistors in the same space hence we can
decrease the overall area of the chip
• Multifunction of Chip: As transistor size is reduced we can make multifunctional chips
by reducing the area of chips.

Types of Scaling in MOSFETs-:


Scaling can be classified into three categories, which are detailed below.

• Constant Field Scaling or Full Scaling.


• Constant Voltage Scaling.
• Lateral Scaling.

Before scaling, the channel length and the channel width of the MOS transistor
are W and L respectively. After scaling by a factor S, the dimensions of the
scaled MOS device are W’=W/S and L’=L/S. The channel area of the MOS
transistor before scaling is A=WL, whereas the channel area of the MOS
transistor after scaling is A’= W’L’=A/S2 . Hence after scaling, the channel area
of a MOS device reduces significantly. Two different scaling options are
employed for scaling the MOS device. These different options are: constant
field scaling and constant voltage scaling [8]. Both types of scaling methods
have different effects on the performance characteristics of the MOS device.
Constant Field Scaling or Full Scaling-:
In this, all the parameter of the MOSFET is scaled to understand it in a better way we
will consider a case, suppose the scaling factor is “S” whos values greater than 1
(S>1) now consider all the parameters of MOSFET is scaled by scaling factor “S” then
its all parameter will get changed to a new value.

For example, if the original gate length is “L” then after scaling it will become L’ = L/S

In a similar way, all parameters of the MOSFET will get changed to their new value
hence this type of scaling is known as the Full Scaling.
Effects Of Constant Field Scaling On Mos Device Performance

The effects of constant field scaling on MOS device performance such as gate oxide
capacitance per unit area, transconductance, drain current, power dissipation, and
power dissipation density are shown from equations (1) – (6).

Gate oxide capacitance per unit area, C’ox = εox/t’ox = S. εox/tox = S. Cox (1)

Transconductance, k’n = µn.C’ox.W’/L’ = S. kn (2)

Drain current, I’D (lin) = k’n/2. [2.(V’GS-V’TH).V’DS – V’2DS]

= S. kn/2. 1/S2.[2.(VGS-VTH).VDS – V2DS]

Hence, I’D (lin) = ID (lin)/S (3)

I’D (sat) = k’n/2. (V’GS-V’TH)2

= S. kn/2. 1/S2. (VGS-VTH)2

Hence, I’D (sat) = ID (Sat)/S (4)

Power dissipation, P’= I’D . V’DS

= 1/S2. ID . VDS

Hence, P’= P/S2 …………(5)

Power dissipation density, P’d = P’/ (W’. L’) = Pd …………..(6)


Constant Voltage Scaling-:
In this only, the physical parameters of the MOSFET are Scaled-down such as
the Gate length of the MOSFET is decreased, and this result In a Short Channel
Effect which will directly affect the Drain Current, therefore the drain Current is
Inversely proportional to gate length. And electrical Parameters are kept
constant, such as the terminal voltage of the MOSFET is kept constant.

Effects Of Constant Voltage Scaling On Mos Device Performance


The effects of constant voltage scaling on MOS device performance such as
gate oxide capacitance per unit area, transconductance, drain current, power
dissipation, and power dissipation density are shown from
equations (7) – (12).
Gate oxide capacitance per unit area, C’ox = εox/t’ox = S. εox/tox = S. Cox ...(7)
Transconductance, k’n = µn.C’ox.W’/L’ = S. kn (8)
Drain current, I’D (lin) = k’n/2. [2.(V’GS-V’TH).V’DS – V’2DS]
= S. kn/2. [2.(VGS-VTH).VDS – V2DS]
Hence, I’D (lin) = S. ID (lin) …..(9)
I’D (sat) = k’n/2. (V’GS-V’TH)2
= S. kn/2. (VGS-VTH)2
Hence, I’D (sat) = S. ID (Sat) …..(10)
Power dissipation, P’= I’D . V’DS
= S. ID . VDS
Hence, P’= S. P ………. (11)
Power dissipation density, P’d = P’/ (W’. L’) = S3. Pd ……….(12)

Lateral Scaling-:
In this type of scaling only the width of the gate channel is scaled. It’s
commonly called a gate shrink. This type of scaling is used only in specific
applications. the disadvantage associate with this type is the high electric field
through the channel and hence it also causes a short channel effect.
Conclusion
Reducing the device dimensions allows higher density and higher logic
integration. As the device dimensions are systematically reduced through
constant field scaling or constant voltage scaling, various physical limitations
become increasingly more prominent, and ultimately restrict the amount of
feasible scaling for some device dimensions. In constant field scaling, power
dissipation decreases by S2 , while in constant voltage scaling, drain current
increases by S. Hence, constant field scaling can be used in low power
applications, while constant voltage scaling can be used in high switching speed
applications. The appropriate scaling approach in a MOSFET may be used
depending upon the applications.

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