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Hardware Engineer Profile

Ravi Kumar Saini is a hardware engineer seeking a career in the hardware domain. He has experience as a design verification engineer trainee where he gained experience writing RTL models in Verilog and verifying them using SystemVerilog and UVM testbenches. He has skills in digital system design, Verilog, SystemVerilog, analog electronics, and microcontrollers/processors. He has a Bachelor's degree in Electronics and Communication Engineering.

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sahil saini
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64 views2 pages

Hardware Engineer Profile

Ravi Kumar Saini is a hardware engineer seeking a career in the hardware domain. He has experience as a design verification engineer trainee where he gained experience writing RTL models in Verilog and verifying them using SystemVerilog and UVM testbenches. He has skills in digital system design, Verilog, SystemVerilog, analog electronics, and microcontrollers/processors. He has a Bachelor's degree in Electronics and Communication Engineering.

Uploaded by

sahil saini
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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RAVI KUMAR SAINI

HAR DWARE ENGINEER

ABOUT ME

CONTACT MEAT
I am hardworking Hardware engineer, I have good
knowledge of Digital System Design,Analog
Electronics,Memory,Microcontroller & Microprocessor,
Khetri, Rajasthan,India
Verilog,System Verilog and UVM. Seeking a career in
[email protected] Hardware domain where I can put my skills to help to grow
company and besides enhance my knowledge and skills.
+91 – 7240768992

https://www.linkedin.com/in
/ravi-saini-a483a3221/
WORK EXPERIENCE
Design Verification Engineer Trainee (FEB 2022 -SEP 2022)
Truechip Solutions , Noida

Good understanding of writing RTL models in Verilog and


SKILLS SUMMARY Verify Through System Verilog and UVM based
testbench Architecture.
Hands on experience in preparing Verification plans by Using
Digital System Design:
SV and UVM based testbench.
 Combinational Circuit:
 Logic Gates Advanced VLSI Training (AUG 2021-JAN 2022)
 K-map Truechip Solutions , Noida
 Half-Adder,Full-adder Better Understanding of Digital System Design,Verilog System
 Half-sub,Full-sub
Verilog,Universal Verification Methodology(UVM)
 Comparator
 Encoder & Decoder
 MUX & DEMUX EDUCATION Q U A L I F I C A T I ON
 Sequential Circuit:
Bachelor of Technology
 Latch & Flip-Flop
B K Birla Institute of Engineering & Technology (2021)
 Counter
Electronics and Communication Engineering (7.66CGPA)
 Shift Register
 FSM
Senior Secondary Education
Govt. Senior Secondary School (2017)
RBSE BOARD (63%)
Analog Electronics: PROJECTS

 Resistor ALU(Arithmetic Logic Unit) APRIL 2022


 Capacitor Project Description:
 Transistor Design RTL Model Using Verilog - HDL Verified
Using SV &UVM Based Testbench
 Diode
 BJT Dual Port RAM JULY 2022

 MOSFET Project Description:


Design RTL Model Using Verilog -HDL
 Inductor
Verified Through SV & UVM Based Testbench
 op-amp

Memory Devices: T E C H N I C AL S K I L L
 RAM
 ROM Product testing,debugging,validation
Microcontroller & Microprocessor Computer knowledge
Basic knowledge of Arduino uno
Programing Language: HDL : Verilog
 VERILOG HVL : System Verilog
 System Verilog Programming Language : Verilog,System Verilog,UVM
 UVM EDA Tool : QuestaSim, Xilinx,Modelsim

C O - C U R R I C U LA R A C T I V I TY
Regular Passed with first Division during college.

Participated in sports activities like football, cricket duringschool as


well as college.

Languages Known:

ENGLISH
HINDI DATE :
PALCE: RAVISAINI

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