MIPS processor architecture
and
Memory systems
1
References
●
Computer organization and design MIPS Edition, Henessey and
Patterson (H&P). 4th or 5th editions. – Ch 2, 4, 5
Do not use ARM edition and RISC-V editions
– 5th edition:
https://ict.iitk.ac.in/wp-content/uploads/CS422-Computer-Architectu
re-ComputerOrganizationAndDesign5thEdition2014.pdf
– 4th edition:
https://nsec.sjtu.edu.cn/data/MK.Computer.Organization.and.Desig
n.4th.Edition.Oct.2011.pdf
●
Do not refer to “Computer architecture- Quantitative approach by H&P
– it has more advanced content
●
Digital design and computer architecture, Harris and Harris- Ch 6, 7, 8
2
Turing lecture
●
The Turing Award is recognized as the "highest distinction in
computer science" and "Nobel Prize of Computing".
●
ACM has named John L. Hennessy, former President of
Stanford University, and David A. Patterson, retired Professor of
the University of California, Berkeley, recipients of the 2017
ACM A.M. Turing Award (Alan Mathison Turing) for pioneering
a systematic, quantitative approach to the design and
evaluation of computer architectures with enduring impact on
the microprocessor industry.
●
https://amturing.acm.org/
●
https://www.acm.org/hennessy-patterson-turing-lecture
3
Other video resources
●
MIT 6.004 Computation Structures Fall 2018
https://www.youtube.com/playlist?list=PLDSlqjcPpoL64CJ
dF0Qee5oWqGS6we_Yu
– Lec 11, 15, 16, 17, 18: Processor
– Lec 13, 14: Caches
●
Digital design and Computer Architecture- ETH Zurich
Spring 2020
– https://www.youtube.com/playlist?list=PL5Q2soXY2Zi_FRrloMa
2fUYWPGiZUBQo2
– https://safari.ethz.ch/digitaltechnik/spring2020/doku.php?id=sch
edule
– Lec 10 to 14: Processor
– Lec 21a, 21b: Caches 4
MIPS Architecture
32-bit RISC ISA - All instructions are 32-bits
●
32 32-bit Registers,$s0–$s7, $t0–$t9, $zero,
etc
●
Byte addressable memory
– Byte = 8bits
– Word = 4 bytes
– A 32-bit word contains four bytes
6
Registers
7
MIPS byte addressible memory
2^32 locations
●
MIPS addresses
each byte (8 bits)
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Instruction: 32bits
(4 bytes) must
start at addresses
that are multiples
of 4.
Instruction 2
PC + 4 address instruction
0x00000008
Instruction 1
0x00000004
PC 0x00000000 0x4FCB516B
Big endian notation
8
http://chortle.ccsu.edu/assemblytutorial
MIPS instructions
9
Taken from “Computer organization and architecture”, Hennessey and Patterson
..cont
Fill with 0’s
10
Taken from “Computer organization and architecture”, Hennessey and Patterson
MIPS Instruction Formats
●
R format - Uses three register operands
– Arithmetic and logical instructions
– And $s1,$s2,$s3
– Add $s1,$s2,$s3
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I format - Uses two register operands and an
address/immediate value
– Load and store instructions:
●
LW $s1, 16($s2)
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SW $s1, 16($s2)
– Arithmetic and logical instructions: addi $s1, $s2, 10
11
MIPS Instruction Formats
●
J format - Contains a jump address
– Jump instructions. JMP 1000
12
MIPS Program Examples
●
Assume g = h + A[4]. Compile this into MIPS
assembly
- Say g->$s1, h-->$s2
– Base of array A is found in $s3
– Use temporary register $t0 if needed
13
MIPS Program Examples
●
Assume g = h + A[4]. Compile this into MIPS
assembly
- Say g->$s1, h-->$s2
– Base of array A is found in $s3
– Use temporary register $t0 if needed for storing
intermediate value
Lw $t0,16($s3) # Temporary reg $t0 gets A[4]
Add $s1,$s2,$t0 # g = h + A[4]
14
Instruction codes
15
MIPS Instruction codes-
R-format
16
Computer organization and design, Hennessey and Patterson
MIPS Instruction Formats
32-bit Instruction Formats R, I and J
OP RS RT RD SHAMT FUNCTION
6 5 5 5 5 6
OP RS RT Address/Immediate
6 5 5 16
OP Jump Address
6 26
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MIPS instruction encoding
Role of function field??
18
Computer organization and design, Hennesey and Patterson
MIPS instruction encoding
R-format has same opcode
(0). To distinguish between Destination registers are
instructions, we have the different for these types of
function field instructions
19
Computer organization and design, Hennesey and Patterson
R-format- Add operation
20
Shift operation
21
Shift operation
Sign extend
What about SLA?
22
I format: Immediate addressing
Load upper immediate:
Lui $s0, 0x1000 : # $s0 0x10000000
23
BEQ
Branch target address = PC+4 + (immediate value * 4)
In other words:
Immediate field- gives the number of instructions between PC+4
and the target 24
J- format
●
Jump ( j ) instruction jumps directly to the
instruction at the specified label.
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Jump and link ( jal ) is similar to j but is used by
procedures
25
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J-type instruction does not have enough bits to
specify a full 32-bit Jump target address. Six bits
used for the opcode , so only 26 bits are left
●
How does the processor create a 32 bit address?
32 bit Jump Address
OP Jump Address
6 26
26
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JTA 1:0 , should always be 0, because instructions are word aligned. So,
we can ignore the least 2 bits of the JTA
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JTA 27:2 , are taken from the addr field of the instruction
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JTA 32:29 are ignored--> because we can only Jump to the location inside
the code segment. In other words, the (PC+4)’s 4 MSB bits and JTA’s 4
MSB bits will be same
– Limits the jump range
32 bit Jump Address
27:2 --> 26 bit address
OP Jump Address
6 26
27
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How do we form a 32 bit jump target address
from the instruction?
– Append 2 zeroes at the LSB
– Append 4 zeroes to the MSB
OP Jump Address
6 26
32 bit
0000 Jump Address 00
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Instruction in memory
Stored program concept
29
Byte addressing
0 AB
1 CD
2 EF
3 78
4 F2
5 F1
6 AC
7 07
8 01
9 EE
A 28
B 42
C 40
D F3
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MIPS memory map ●
Address space: 2^32 bytes = 4GB
●
Text space: Stores code: 256MB of
code. 4 MSB bits = 0: JMP can jump
to any instruction in the program
space
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Global data: saves global variables:
64kB
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Stack/Heap – 2GB: Save registers
during procedure call
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$sp initialised to topmost location
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Stack grows downwards – LIFO
●
Heap stores data allocated during
runtime (malloc)
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Reserved – by OS
Code
31
Code/text
segment
Data
segment
32
33
Poll
●
Which of these instructions write to the memory
– LW
– SW
– SLL
– BEQ
34
●
Which of these is an R-Format instruction
– LW
– SW
– BEQ
– Add
35
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[BEQ S1, S2, target] jumps to the target if:
– S1=S2
– S1 not equal to S2
– S1<S2
– S1>S2
36
●
SW S1, 8 (S2). How many registers are being
read in this instruction?
– One
– Two
37
●
Which of the following is true for a word aligned
memory or byte addressible memory in MIPS?
A)Instructions are 8 bits wide
B)PC should increment by PC+1
C)PC should increment by PC+4
D)Data is 32 bits wide
1)B,D
2)C,D
3)A,C,D
4)All are true 38
Convert this to instruction code – MIPS format
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A[200] = h + A[100]
– Say, $t1 has the base of the array A and $s1
corresponds to h
– $s0 to $s7 map --> registers 16 to 23
– $t0 to $t7 map --> registers 8 to 15
– Use $t0 as temporary register
39
Branch instruction
Output of Execution?
41
MIPS assembly
C equivalent of this code?
43
Acknowledgements
●
Diagrams taken from H&P 4th edition, Harris
and Harris Ch-6
45
