Lecture 6 -

Finite State Machines

(continuing)

ITEE, UQ 1
 Admin
-
§ This week’s practical – continuation of prac 3
(arithmetic circuits)
§ Get your oral assessments completed for prac 2 if
you have not done already. Late penalties apply only
on the report submission date.

ITEE, UQ 2
 Se
-

Finite State Machines

From last week:
a

crtnt 1] 0
inpub

⑧
~

1State ↳r
->
NS S
triage
fit
-

->

T ③
-
r

a ②
e

i ~Macra.
-
Mealy
ITEE, UQ 3
 Flip-Flops
! FLIP-FLOPs are trivial FSMs
! Use state diagrams to remember F-Fs functions

D K el T R
1 1 1 1

↑
S&R
D J T

D K T S&R
0 0 0 0
D
jaJ T S

D JK - T SR
-
ITEE, UQ 4
 B -- C-

Flip-Flops Timing ParametersDa-

D

I
-

~ --
A -
L

extend
§ Set-up
- time
§ Hold-time
~
1

# ⑰D
-
= Designe
13 B
*
&

§ Clock pulse duration

⑰
( ⑧
§ Clock-to-output delay
a

- --

-
Desi
-
=

§ Register metastability W

clk -
-
-

i
1
all

Sever
a a

clk
r IJT5
!
Y
a
- L

& v
-

Dinput -

·a
--

sIH- trt Sync

FFS
ITEE, UQ f 5
 - -

COB-S-D
FSM performance - ->

! Maximum frequency of operation is calculated as :

f max = T1mi n = Tnext st at e +
1
Tset up +Td
-

D1 Q1 o
in1 Next State 0 u Out1

"To
D2
1 t
Q1 Q2
Q2 e
Clk
-
TCPD
L

⑧
Tnextstate Tsetup Td Tout

ITEE, UQ
-
~*Ia
w
6
 FSM state assignment -encoding
-
scheme
by heuristics (educated guess)
§ How does the next state and output logic depend on
the codes assigned to the states ?
§ Can we optimise logic better if we assign state codes
in a smart way ?
§ What is the smart way to assign the state codes ?
§ Is it worth to try randomly and pick up the best code ?
§ What are the guidelines to assign good codes ?
§ When is it important to optimise the state codes ?
§ Different schemes: on-hot encoding, binary, gray code
- 00
T
00 0 I
§ CAD tools use different algorithms
000l id 1)
10
00 10
ITEE, UQ 0100 1000 ii) 7
 FSM state assignment
by heuristics (educated guess)
§ Number of possible state assignments :
-zm = number of states
⑧
- n = number of possible states ( n = 2^k )
-

n!
n m! = -------
m (n-m)!

8!
--------- = 6,720
(8- 5)! -

ITEE, UQ 8
 q
FSM state assignment
Golden Rules of good state encoding (for D FFs).
aakofat---
O 1. States with most incoming branches should be
-

assigned least '1's in their codes since they potentially

-a.
contribute most product terms.
03 -
⑧x②
⑰
⑧
S1

b↳
A
H S0 = 1000
-
-
↓ ↓
-
Q3+ = ... +A.S1 + b.S2 +
-> S0
S2 -> ⑧ H contributes
- -

C.S3 + d.S4 + H.S0 + ...

-I↑d
- M --

C
-

S3 A S4 = 0001
S4
contributes Q0+ = ... + A.S3
~

ITEE, UQ 9
 FSM state assignment
qGolden Rules of good state encoding (for D FFs).
0
2. States with common next state on the same input condition
should be assigned adjacent codes.
-

~ a

~O ⑧
S1 S2
+
Q3 = ... + b.S1 + b.S2 +
b contributes = ... + b.(S1 + S2) + ...
b

a
S3 -
-
S3 = 1000
-

as Qs

O
·
S1 = 1100
S2 = 0100
adjacent codes
contributes bm e
.( Q1. Q2. Q3 . Q4

= -
t
+ Q1.Q2.Q3.Q4)

b. Q2. Q3. Q4
ITEE, UQ 10
 ↑
als
FSM state assignment al
q Golden Rules of good state encoding (for D FFs).
ab
0 3. Next states of the same state should be assigned adjacent
codes according to adjacency of branch conditions.
-
l
Q3+ = a.b.S0 + a.b’.S0
a&b

~
S0 = a.S0
w
Q2+ = a.b.S0 + a’.b.S0
0 ⑧
a&b a&b a&b contributes
->
= b.S0
S1 D
S3 S2
adjacent codes Q0+ = a.b.S0 + a.b’.S0
~ &

+
S0 = 0001
a’.b.S0 + a’.b’.S0
T S1 = 1101 ↑ distre
dis
· S2 = 0101 2
8.
= S0 5
distre
-- a
2
S3 = 1001 -
ab
⑧
ITEE, UQ 11
 FSM state assignment
q Golden Rules of good state encoding (for D FFs).
4. States that form a chain on the same branch condition should
be assigned adjacent codes.
-

H
Q2+ = H’.S0 + H.S1 + H’.S1 + H.S2
= H’.(S0 + S1) + H(S1 + S2)
S0
= H’.Q1’.Q2 + H.Q0.Q2
↓
contributes
H
Q1+ = H’.S1 + H.S2
S1
= H’.Q0.Q1’.Q2 + H.Q0.Q1.Q2
S0 = 001
I Q0+ = H.S0 + H’.S0 + H.S1+H’.S1 + H.S2
b
H
S1 = 101
H
S2 = 111 o = (S0 + S1) + H.S2
= Q1’.Q2 + H.Q0.Q1.Q2
S2
adjacent codes
H
ITEE, UQ 12
 VHDL Examples
library IEEE;
signal D, LE, Q: bit ; use IEEE.std_logic_1164.all;
...

I
entity LATCHES is
b1 : process (D, LE)
port (D1, -D2, LE: in std_logic;
begin -
~
Q : out std_logic);
-

if (LE = ’1’) then

~

end LATCHES;
Q <= D;
-

end if ; ? architecture EG of LATCHES is

begin -
end process
S
; process (D1, D2, LE)
begin
I if (LE = '1') then
Q <= D1 xor D2; E

Implement end if ; --

end process;
end EG;

- ~

-
-
-
ITEE, UQ 13
 VHDL Examples
library IEEE;
use IEEE.std_logic_1164.all;

entity FLIPFLOP is

port (D1, D2, clk: in std_logic;

Q : out std_logic);
end FLIPFLOP;

architecture EG of FLIPFLOP is ~
begin u
process (clk)
begin -

~ -
if (clk’event and clk='1') then
Q <= D1 xor D2; -
w a
end if ;
end process;
end EG;

ITEE, UQ 14
 VHDL Examples
signal D, Q, clk, reset : bit ;
... ade

I
process (clk, reset)
positure
triggend
begin
if (reset = ’1’) then
I Q <= ’0’ ;
-

elsif (clk’event and clk = ’1’) then

--

Q <= D ;
-- Et
end if ;
-- D
end process ; P with
I asyehre
wis
DFF..--- active
reset
ITEE, UQ 15
 VHDL Examples
library IEEE;
use IEEE.std_logic_1164.all;

entity FLIPFLOP is
~

port (D1, D2, reset, clk: in

-

std_logic;
Q ~
: out std_logic);
0
end FLIPFLOP; L

L
architecture EG of FLIPFLOP is
begin
process (clk) -
-
begin ~
~
if (clk'event and clk='1') then
↳ if reset = '1' then
-

P
active wish
Q <= '0' ;
else -
Q <= D1 xor D2;
end if ; reset.
end if; Sync.
end process;
end EG;
ITEE, UQ 16
 VHDL Examples

r
- It
I
I DQ
>
ClK
s

-
~
-
↑Resatur

ITEE, UQ 17
 VHDL Examples
VHDL Ne
parameterised
->
L
N-bit
register
low
-
0 active
-
with
Wese f
asque. cluck
positive
tringend
- o..
=- sits.
a

compart. 32
a ,
=

-
ambewhey a (N
N
as MA

instrutted
chased GENERICMAP.
-
-

*
a

PORT ~

ITEE, UQ 18
 w

11 mux.
=
g
ITEE, UQ 19
 VHDL Examples

M
-
paratel Lond
=>

~ ~

seme
shift t al3) GlY G(Y II ITD
->A
~-
Tifaco)

ITEE, UQ 20
 VHDL Examples
N bit s Lift weg

-
Wit parallel
Lord
AL=
mut
. -
Loop-

For Rece
sequenti
--

to
⑰
-
use state.
-

-
↳

~
W aset
assignment
of - -

Genente
- a
set
I sequ
concurrent
procee
---
For
2

<
ene
assis ~ ↳ assist

ITEE, UQ 21
 VHDL Examples

ITEE, UQ 22
 VHDL Examples

ITEE, UQ 23
 VHDL Examples
entity count23 is
port ( clk, input1 : in std_logic; begin
output1 : out std_logic ); case present_state is

I
end count23;
-

when s0 =>
-

present_state <= S1;

architecture EG of count23
-w is when s1 => -

if (input1 = ‘0') then

-type -h
state_type is (s0, s1, s2) ;

-
- -
signal present_state: state_type; present_state <= s0 ;
-
else -

begin present_state <= s2;

process (clk) end if; -

begin when s2 =>

if clk'event and clk = '1' present_state <= s0
then w end case ;
end if;
end process ;
output1 <= ‘1’
when present_state = s0 else ‘0’;
NOTE: Can’t have “when” end EG ;
statement inside process

ITEE, UQ 24
 VHDL Examples
entity count23 is
port ( clk, reset, input1 : in begin
std_logic; case present_state is
output1 : out std_logic ); when s0 =>
end count23; present_state <= S1;
when s1 =>
architecture EG of count23 is if (input1 = ‘0') then
type state_type is (s0, s1, s2) ; present_state <= s0 ;
signal present_state: state_type; else
present_state <= s2;
begin end if;
process (clk, reset) when s2 =>
begin present_state <= s0
if reset = ‘1’ then end case ;
end if;
present_state <= s0;
end process ;
elsif clk'event and clk = '1'
output1 <= ‘1’
then
when present_state = s0 else ‘0’;
end EG ;

ITEE, UQ 25
 VHDL Examples
entity three is
port ( clk, input1 : in std_logic; begin
output1 : out std_logic ); case p_s is
end three; when 0 =>
00 if (input1=‘0')then p_s <= 0 ;
architecture EG of three is ol else p_s <= 1; end if;
-

; when 1 =>
- 10
⑧
signal p_s:
integer range 0 to 3 := 0;
:
if (input1=‘0')then p_s <= 2 ;
else p_s <= 3; end if;
when 2 =>-

begin if (input1=‘0')then p_s <= 0;

process (clk) else p_s <= 1; end if;
begin when 3 => -

if clk'event and clk = '1' if (input1=‘0')then p_s <= 3;

then else p_s <= 3; end if;
end case ; -

end if;
end process ;
output1 <= ‘1’
A when ((p_s=0) and (input1 = ‘0’))
or ((p_s=3) and (input1 = ‘1’))
else‘0’;
end EG ;
ITEE, UQ 26
 -

-
- -

v-
-

⑰
/
v ---

~
=

I
-
-
-
-

~
I State
Frau

---- F
oLP:
=

E -
1 op.
ITEE, UQ 27
 State Minimisation -

q In a complex FSM, if the number of states can be

reduced, the overall complexity can be reduced
q When there are many states, some states can be
equivalent
O 0
-

I
q Two states Si and Sj are said the be equivalent if and
only if for every possible input sequence, the same
-

output sequence will be produced, regardless of

whether Si or Sj is the initial state
-
u

q There are many algorithms to find equivalent states

in an FSM. We will look at one simple method; based
-

on state partitioning
e

q The idea is to partition the states and eliminate the

ITEE, UQ states that are not equivalent 28
 So,SI,S2---. S7
State Minimisation k
[00,01,10,13
=

q Some definitions:
-such
Di
– 0-successor, 1-successor and k-successor of a state Si
A - -
-

⑮ ·Su
"

0 Si- Sj
-

O-successer
" – A partition within the FSM consists of one or more
K 5 set of input combinati
=

⑲
- -
-

blocks, where each block contains a subset of states that

-
may be equivalent, but the states within a given block
succes are definitely not equivalent to the states in other blocks.
-

1- ~
L
-
~P=(S0,51,55) (S2,55,56) (S4)
ITEE, UQ - At 29
Pr= ( So,,, ---
S1)
Pit Pitt
)State Minimisation
P2 (-)) C
-
=
-
-
--
Method: L
q
4
①– Assume all states are equivalent initially. Thus, we have an
initial partition P1 containing all states within a single block
-

– From P1, obtain a new partition P2 such that the states

⑧ w
within each block in P2 generate the same output. Note
that states that generate different outputs cannot be
equivalent and thus are in different blocks within P2
– Continue to form new partitions by checking whether the k-

I
e
successors of the states in each block are contained in one
-

block. Those states in Pi whose k-successors are in m

- - 1

different blocks cannot be in one block in Pi+1

-– New blocks are formed in the new partition Pi+1 based on
this rule. The process stops when Pi+1 =Pi
ITEE, UQ -
-
30
 State Minimisation
Present Next State Output P, (A,
=
B, C, D, E, F, G)
State
·
w=0 w=1 ⑧

A B C 1 ·P2 =

(A,B,x)(EFG) E
B D F 1 -

0xX I 01 *A
C F E 0
W D B G 1 (B,x,B) CCFGS (FFE) (E)
P3 (A Bx) (EG) (F)
E F C 0
=

- F E D - 0
-

of I
G F G 0
Lo I
7 State FSM
↓
(BCSB) (E2) (FFF) (E(a)
(B) (CEC) (F)
4 StartsESM. PG=

(A x)
PS (AX) (B) (cE(a)
ITEE, UQ STOP- - = CF) 31
 FSM Example – Add/Shift Multiplier
A

ITEE, UQ 32
 Multiple/Interacting FSMs
*

ITEE, UQ 33
ITEE, UQ 34
ITEE, UQ 35