DESIGNWARE IP DATASHEET

MIPI D-PHY IP

Highlights Overview
• Compliant with the MIPI D-PHY Synopsys’ DesignWare D-PHY IP enables high-performance, low-power interface
specification, v1.2 to SoCs, application processors, baseband processors, and peripheral devices
• Fully integrated hard macro for mobile, automotive, artificial intelligence (AI), and IoT applications. The PHY,
for mainstream and FinFET processes, is compliant with the D-PHY specification,
• Up to 2.5 Gbps per lane
operating at 10Gb/s aggregate data rate in 4 lanes. Supporting low-power state
• Aggregate throughput up to 10 Gbps in 4 modes allows the IP to deliver low-power consumption at the maximum speed
data lanes to address energy requirements of battery-operated devices. The DesignWare
• Supports PHY Protocol Interface (PPI) D-PHY IP interoperates with Synopsys’ CSI-2 and DSI/DSI-2 controllers which
• Low-power escape modes and ultra low- support key features of the latest MIPI display and camera specifications. The
power state modes DesignWare MIPI D-PHY IP is ASIL B Ready ISO 26262 certified, meeting the
stringent requirements of automotive ADAS and Infotainment applications.
• Shutdown mode
• SCAN and loopback BIST modes
• Extensive access to internal
programmability registers Bias PLL
• Master, slave, TX- and RX-only
configurations
Digital TX
• Attachable PLL for master applications
configuration and glue logic

HS
• Flexible input clock reference LP-TX Data
data serializer
• 50% DDR output clock duty cycle lane 1
PPI interface

TX
• Silicon-proven, robust design available in LS TX
HS-TX
escape mode
advanced process technologies
• ASIL B Ready ISO 26262 certified for
HS HS-RX RT Clock
Grade 1 and Grade 2 automotive design RX lane
data recovery

Target Applications LS RX LP-RX

• CSI-2 Host escape detect

• DSI Host CD Data

LP-CD
control logic lane 0
• CSI-2 Device CD
• DSI Device Digital RX

Technology Figure 1: DesignWare MIPI D-PHY IP block diagram

• Available in 65-nm, 40-nm, 28-nm, 22-nm,
and 16-nm, 12-nm, 7-nm FinFET

synopsys.com/designware
Key Features
• Compliant with the MIPI D-PHY specification
• Fully verified hard macro
• Up to 2.5 Gb/s per lane
• Aggregate throughput up to 10 Gb/s in 4 data lanes
• Support for the PHY Protocol Interface (PPI)
• Low-power escape modes and ultra- low-power modes
• Shutdown mode
• SCAN and Loopback BIST modes
• Extensive access to internal programmability registers

Deliverables
• Databook
• Behavioral model
• LEF file
• .LIB file
• GDSII Layout Database

IP Accelerated Initiative
The Synopsys IP Accelerated initiative augments Synopsys’ established, broad portfolio of silicon-proven DesignWare IP with new
DesignWare IP Prototyping Kits, DesignWare IP Virtual Development Kits, and customized IP subsystems to accelerate prototyping,
software development, and integration of IP into SoCs.

For hardware engineers, the IP Prototyping Kits provide a validated IP configuration that can be easily modified to explore design
tradeoffs for the target application. Software developers can use either the IP Virtual Development Kits or the IP Prototyping Kits as
proven targets for early software development, bring-up, debug and test.

About DesignWare IP
Synopsys is a leading provider of high-quality, silicon-proven IP solutions for SoC designs. The broad DesignWare IP
portfolio includes logic libraries, embedded memories, embedded test, analog IP, wired interface IP, wireless interface IP,
security IP, embedded processors, and subsystems. To accelerate prototyping, software development and integration of IP
into SoCs, Synopsys’ IP Accelerated initiative offers IP Prototyping Kits, IP Virtualizer Development Kit and IP subsystems.
Synopsys’ extensive investment in IP quality, comprehensive technical support and robust IP development methodology
enables designers to reduce integration risk and accelerate time-to-market.

For more information on DesignWare IP, visit synopsys.com/designware .

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06/30/20.CS12062_MIPI_D-PHY_DS.