5 4 3 2 1

D D

LCFC Confidential
C S350 Renoir M/B Schematics Document C

om
AMD FP6 Renoir with DDR4

.c
2020-01-06

ix
af
REV:1.0

in
//v
s:
tp
B
ht B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/02/27 Deciphered Date 2020/02/27 Cover Page
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
S350 ARE 1.0

Date: Sunday, January 19, 2020 Sheet 1 of 45

5 4 3 2 1
 A B C D E

Memory BUS (DDR4)

PCI-Express Channel A DDR4-SO-DIMM X1
NGFF SSD1
4x Gen3
PEIe GPP[3:0]
Page 22 1.2V DDR4 2400MT/s UP TO 16G x 1 Page 14

HDMI Conn. HDMI x4 Lane Port1 Memory BUS (DDR4) 1

Channel B DDR4 DRAM DOWN

Page 19

1.2V DDR4 2400MT/s 4pcs x16 Page 15

eDP Conn
Int. Camera USB Left Port2 Lower
USB 2.0 Port2 eDP x2 Lane port0 USB 3.0 1x
USB 2.0 1x USB 2.0 Port4
Int. DMIC Conn. USB 3.0 Port4 Page 20

Page 17 AMD FP6 APU

USB Left Port1 Upper
Renoir USB 3.0 1x
SATA HDD SATA Gen3 USB 2.0 1x USB 2.0 Port1
SATA Port2 USB 3.0 Port1
Page 30 UMA Page 20

2 NGFF Card PCIe 1x 2

WLAN&BT
Key E USB2.0 1x
USB 2.0 1x USB2.0 Conn

om
PCIe Port4
USB 2.0 Port6 Page 27 USB 2.0 Port0
Page 21
USB 2.0 1x

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ix
Finger Print

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USB 2.0 1x
I2C BUS
USB 2.0 Port7 Page 32 Touch Pad

in
Page 32

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Touch Screen USB 2.0 1x
USB 2.0 Port3 Page 17

s:
SPI BUS SPI ROM
W25Q128JWSIQ_SO8

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16MB Page 08
ht
3 3
SD/MMC Conn.
Codec & C/R USB2.0 x1
TPM (Reserved)
ST33HTPH2E32AHB4
SPK Conn. HD Audio
Realtek RTS5119 Page 29

HP&Mic Combo Conn.

USB2.0 Port5

EC SMBUS
Battery
IO Board
IT8227E-CX_LQFP128 Page 38
Page 31
SMBUS

Charger
Page 39

Int.KBD Thermistor Hall sensor

AH9247
Page 32 Page 25 Page 32
Thermal Sensor
4
F75303M_MSOP10 4

Page 25

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/15 Deciphered Date 2013/08/15 Block Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
S350 ARE 1.0

Date: Sunday, January 19, 2020 Sheet 2 of 44

A B C D E
 A B C D E

Voltage Rails ( O --> Means ON , X --> Means OFF ) STATE

SIGNAL
SLP_S3# SLP_S5# +VALW +V +VS Clock

+5VS S0 (Full ON) HIGH HIGH ON ON ON ON

+3VS
S1 (Power On Suspend) HIGH HIGH ON ON ON LOW
+1.8VS
power +0.75VS S3 (Suspend to RAM) LOW HIGH ON ON OFF OFF
plane B+
1 (+20VSB) +5VALW +0.6VS 1
+2.5V S4 (Suspend to Disk) LOW LOW ON OFF OFF OFF
+3VL +3VALW
(+3VALW_APU) +1.2V
+5VLP +VDDC_VDD S5 (Soft OFF) LOW LOW ON OFF OFF OFF
+1.8VALW
+VDDCR_SOC
+0.75VALW
BOM Structure Table
State BOM Structure BTO Item
Port List @ Not stuff
SOURCE Device
ME@ Connector
HSIO Port Device
EMC@ EMC Part
TP_I2C3_SCL APU Touch Pad
0 EMC_NS@ EMC reserve Part
TP_I2C3_SDA +3VALW +3VS
1 RF@ RF Part
2 TPM@
S0 O O O O GFX 3
TPM part
APU I2C address N/A HDT@ HDT Debug part
Device Address
4 REDRV@ Redriver part
S3
O O O X Elan：SA469D-22HA 69x104x1.0 ?
5 17@ 17' HDD Redriver part
2
Synaptics：TM-P3255-008 69x104x1.0 ?
6 NO17@ 17' HDD Redriver reserve part
2

7
S5 S4/AC O O X X 0
TS@ Touch Screen Part
NOTS@ Touch Screen reserve Part
1 FP@ Finger print Part
SSD
S5 S4/ Battery only
O X X X 2 NOFP@ Finger print reserve Part
3

om
4 WLAN
S5 S4/AC & Battery
don't exist X X X X 5
GPP
6 N/A

.c
SMBUS Control Table 7
8 HDD

ix
SOURCE GPU BATT IT8227 SODIMM WLAN Thermal APU Charger PMIC
9

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Sensor 10 N/A
11

in
EC_SMB_CK1 0 N/A
IT8227
X V X X X X V X

//v
3 3
EC_SMB_DA1 +3VL
USB3.0
1 USB 3.0 Port1 Upper
4 USB 3.0 Port2 Lower
5

s:
EC_SMB_CK2 N/A
EC_SMB_DA2
IT8227
+3VS X X X X V V X X 0 USB2.0
+3VS SIC/SID

tp
1 USB 3.0 Port1 Upper
EC_SMB_CK3 ht 2 Camera
EC_SMB_DA3
IT8227
+3VL X X X X X X X V 3 Touch Screen
USB2.0
4 USB 3.0 Lower
5 Cardreader
APU_SCLK0
APU_SDATA0
APU
X X X X X X X X 6 BT
7 Finger Print

EC SM Bus0 address EC SM Bus1 address EC SM Bus2 address

Device Address Device Address Device Address
4 4
PD Charger 0b00010010 APU SB-TSI releate to F3x1E4[SbiAddr] or
Address Select Pins setting
PMIC 0X34 Battery ?
Thermal Sensor 10011011b(read) 10011010b(write)

EC SM Bus3 address Security Classification LC Future Center Secret Data Title

Device Address
Issued Date 2013/08/15 Deciphered Date 2013/08/15 Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Expand IT8013 0100,A2,A1,A0 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S350 ARE
Date: Sunday, January 19, 2020 Sheet 3 of 45
A B C D E
 5 4 3 2 1

D D

UC1A

G13 F4
F13 P_GFX_RXP0 P_GFX_TXP0 F2
P_GFX_RXN0 P_GFX_TXN0
J14 F3
H14 P_GFX_RXP1 P_GFX_TXP1 E4
P_GFX_RXN1 P_GFX_TXN1
G15 E1
F15 P_GFX_RXP2 P_GFX_TXP2 C1
P_GFX_RXN2 P_GFX_TXN2
J15 D5
K15 P_GFX_RXP3 P_GFX_TXP3 E6
P_GFX_RXN3 P_GFX_TXN3
H16 C6
J16 P_GFX_RXP4 P_GFX_TXP4 D6
P_GFX_RXN4 P_GFX_TXN4
F18 B6
G18 P_GFX_RXP5 P_GFX_TXP5 C7
P_GFX_RXN5 P_GFX_TXN5
J18 D8
K18 P_GFX_RXP6 P_GFX_TXP6 B8
P_GFX_RXN6 P_GFX_TXN6
C C
H19 C8
G19 P_GFX_RXP7 P_GFX_TXP7 A8
P_GFX_RXN7 P_GFX_TXN7

om
PCIE_PRX_DTX_P0 G11 L3 PCIE_PTX_DRX_P0 0.22U_0201_6.3V6-K 1 2 CC9 PCIE_PTX_C_DRX_P0
22 PCIE_PRX_DTX_P0 PCIE_PRX_DTX_N0 P_GPP_RXP0 P_GPP_TXP0 PCIE_PTX_DRX_N0 0.22U_0201_6.3V6-K 1 PCIE_PTX_C_DRX_N0 PCIE_PTX_C_DRX_P0 22
F11 L1 2 CC10
22 PCIE_PRX_DTX_N0 P_GPP_RXN0 P_GPP_TXN0 PCIE_PTX_C_DRX_N0 22
PCIE_PRX_DTX_P1 J10 L4 PCIE_PTX_DRX_P1 0.22U_0201_6.3V6-K 1 2 CC11 PCIE_PTX_C_DRX_P1
22 PCIE_PRX_DTX_P1 P_GPP_RXP1 P_GPP_TXP1 PCIE_PTX_C_DRX_P1 22

.c
PCIE_PRX_DTX_N1 H10 L2 PCIE_PTX_DRX_N1 0.22U_0201_6.3V6-K 1 2 CC12 PCIE_PTX_C_DRX_N1
M.2 SSD1 22 PCIE_PRX_DTX_N1 P_GPP_RXN1 P_GPP_TXN1 PCIE_PTX_C_DRX_N1 22
PCIE_PRX_DTX_P2 PCIE_PTX_DRX_P2 0.22U_0201_6.3V6-K 1 PCIE_PTX_C_DRX_P2
M.2 SSD1
G8 M4 2 CC13
22 PCIE_PRX_DTX_P2 PCIE_PRX_DTX_N2 P_GPP_RXP2/SATA0_RXP P_GPP_TXP2/SATA0_TXP PCIE_PTX_DRX_N2 0.22U_0201_6.3V6-K 1 PCIE_PTX_C_DRX_N2 PCIE_PTX_C_DRX_P2 22
F8 M2 2 CC14

ix
22 PCIE_PRX_DTX_N2 P_GPP_RXN2/SATA0_RXN P_GPP_TXN2/SATA0_TXN PCIE_PTX_C_DRX_N2 22
PCIE_PRX_DTX_P3 G6 N3 PCIE_PTX_DRX_P3 0.22U_0201_6.3V6-K 1 2 CC15 PCIE_PTX_C_DRX_P3
22 PCIE_PRX_DTX_P3 PCIE_PRX_DTX_N3 F7 P_GPP_RXP3/SATA1_RXP P_GPP_TXP3/SATA1_TXP N1 PCIE_PTX_DRX_N3 0.22U_0201_6.3V6-K 1 2 PCIE_PTX_C_DRX_N3 PCIE_PTX_C_DRX_P3 22
CC16

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22 PCIE_PRX_DTX_N3 P_GPP_RXN3/SATA1_RXN P_GPP_TXN3/SATA1_TXN PCIE_PTX_C_DRX_N3 22

in
PCIE_PRX_DTX_P4 M9 T2 PCIE_PTX_DRX_P4 0.1U_0201_6.3V6-K 1 2 CC17 PCIE_PTX_C_DRX_P4
WLAN 27 PCIE_PRX_DTX_P4 PCIE_PRX_DTX_N4 P_GPP_RXP4 P_GPP_TXP4 PCIE_PTX_DRX_N4 0.1U_0201_6.3V6-K PCIE_PTX_C_DRX_N4 PCIE_PTX_C_DRX_P4 27 WLAN
M8 T4 1 2 CC18
27 PCIE_PRX_DTX_N4 P_GPP_RXN4 P_GPP_TXN4 PCIE_PTX_C_DRX_N4 27
L7 R1

//v
L6 P_GPP_RXP5 P_GPP_TXP5 R3
P_GPP_RXN5 P_GPP_TXN5
K7 P2
K8 P_GPP_RXP6 P_GPP_TXP6 P4
P_GPP_RXN6 P_GPP_TXN6

s:
H6 N2
H7 P_GPP_RXP7 P_GPP_TXP7 N4
P_GPP_RXN7 P_GPP_TXN7

tp
SATA_PRX_DTX_P0 L9 K2 SATA_PTX_DRX_P0
30 SATA_PRX_DTX_P0 SATA_PRX_DTX_N0 P_GPP_RXP8/SATA2_RXP ht P_GPP_TXP8/SATA2_TXP SATA_PTX_DRX_N0 SATA_PTX_DRX_P0 30
HDD L10 K4 HDD
30 SATA_PRX_DTX_N0 P_GPP_RXN8/SATA2_RXN P_GPP_TXN8/SATA2_TXN SATA_PTX_DRX_N0 30
K11 J4
B
J11 P_GPP_RXP9/SATA3_RXP P_GPP_TXP9/SATA3_TXP J2 B
P_GPP_RXN9/SATA3_RXN P_GPP_TXN9/SATA3_TXN
J12 H3
H12 P_GPP_RXP10 P_GPP_TXP10 H1
P_GPP_RXN10 P_GPP_TXN10
J13 H4
K13 P_GPP_RXP11 P_GPP_TXP11 H2
P_GPP_RXN11 P_GPP_TXN11
FP6 REV0.92
PART 2/13

AMD-RENOIR-FP6_BGA1140
@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/15 Deciphered Date 2013/08/15 FP6 (PCIE SATA I/F)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
S350 ARE 1.0

Date: Sunday, January 19, 2020 Sheet 4 of 45

5 4 3 2 1
 5 4 3 2 1

DDRA_MA_DM[0..7] 14
DDRA_MB_DM[0..7] 15
UC1B DDR_A_DQS#[0..7] 14
UC1C DDR_B_DQS#[0..7] 15
DDR_A_DQS[0..7] 14
DDR_A_MA0 DDR_B_DQS[0..7] 15
AK26
DDR_A_MA1 MA_ADD0/RSVD DDR_A_D0 DDR_A_D[0..63] 14 DDR_B_MA0
AG24 K27 AM29
DDR_A_MA2 MA_ADD1/RSVD MA_DATA0/MAA_DATA8 DDR_A_D1 DDR_B_MA1 MB_ADD0/RSVD DDR_B_D0 DDR_B_D[0..63] 15
AG23 L26 AH31 C27
DDR_A_MA3 MA_ADD2/MAB_CA0 MA_DATA1/MAA_DATA9 DDR_A_D2 DDR_A_MA[0..13] 14 DDR_B_MA2 MB_ADD1/RSVD MB_DATA0/MBA_DATA8 DDR_B_D1
AG26 N26 AJ30 A28
DDR_A_MA4 MA_ADD3/MAA_CA4 MA_DATA2/MAA_DATA13 DDR_A_D3 DDR_B_MA3 MB_ADD2/MBB_CA0 MB_DATA1/MBA_DATA9 DDR_B_D2 DDR_B_MA[0..13] 15
AG27 N27 AH29 F29
DDR_A_MA5 AF21 MA_ADD4/MAA_CA5 MA_DATA3/MAA_DATA12 G27 DDR_A_D4 DDR_B_MA4 AG32 MB_ADD3/MBA_CA4 MB_DATA2/MBA_DATA13 F31 DDR_B_D3
DDR_A_MA6 AF22 MA_ADD5/MAA_CA3 MA_DATA4/MAA_DATA11 H27 DDR_A_D5 DDR_B_MA5 AG30 MB_ADD4/MBA_CA5 MB_DATA3/MBA_DATA12 B27 DDR_B_D4
DDR_A_MA7 AF25 MA_ADD6/MAA_CA2 MA_DATA5/MAA_DATA10 M27 DDR_A_D6 DDR_B_MA6 AG31 MB_ADD5/MBA_CA3 MB_DATA4/MBA_DATA11 D27 DDR_B_D5
DDR_A_MA8 AF24 MA_ADD7/RSVD MA_DATA6/MAA_DATA15 N24 DDR_A_D7 DDR_B_MA7 AF30 MB_ADD6/MBA_CA2 MB_DATA5/MBA_DATA10 E32 DDR_B_D6
D DDR_A_MA9 AE21 MA_ADD8/RSVD MA_DATA7/MAA_DATA14 DDR_B_MA8 AG29 MB_ADD7/RSVD MB_DATA6/MBA_DATA15 F30 DDR_B_D7 D
DDR_A_MA10 AL21 MA_ADD9/RSVD L23 DDR_A_D8 DDR_B_MA9 AF29 MB_ADD8/RSVD MB_DATA7/MBA_DATA14
DDR_A_MA11 AF27 MA_ADD10/MAB_CS_L1 MA_DATA8/MAA_DATA0 N21 DDR_A_D9 DDR_B_MA10 AM30 MB_ADD9/RSVD H31 DDR_B_D8
DDR_A_MA12 AE23 MA_ADD11/MAA_CKE1 MA_DATA9/MAA_DATA1 T21 DDR_A_D10 DDR_B_MA11 AF31 MB_ADD10/MBB_CS_L1 MB_DATA8/MBA_DATA0 H30 DDR_B_D9
DDR_A_MA13 AM23 MA_ADD12/MAA_CKE0 MA_DATA10/MAA_DATA5 T22 DDR_A_D11 DDR_B_MA12 AE32 MB_ADD11/MBA_CKE1 MB_DATA9/MBA_DATA1 K31 DDR_B_D10
DDR_A_W E# AM21 MA_ADD13_BANK2/RSVD MA_DATA11/MAA_DATA4 M22 DDR_A_D12 DDR_B_MA13 AP30 MB_ADD12/MBA_CKE0 MB_DATA10/MBA_DATA5 L30 DDR_B_D11
14 DDR_A_W E# DDR_A_CAS# MA_WE_L_ADD14/MAB_CKE1 MA_DATA12/MAA_DATA7 DDR_A_D13 DDR_B_W E# MB_ADD13_BANK2/RSVD MB_DATA11/MBA_DATA4 DDR_B_D12
AL27 L24 AP31 G30
14 DDR_A_CAS# DDR_A_RAS# MA_CAS_L_ADD15/RSVD MA_DATA13/MAA_DATA6 DDR_A_D14 15 DDR_B_W E# DDR_B_CAS# MB_WE_L_ADD14/MBB_CKE1 MB_DATA12/MBA_DATA7 DDR_B_D13
AL24 R21 AP29 H29
14 DDR_A_RAS# MA_RAS_L_ADD16/MAB_CKE0 MA_DATA14/MAA_DATA2 DDR_A_D15 15 DDR_B_CAS# DDR_B_RAS# MB_CAS_L_ADD15/RSVD MB_DATA13/MBA_DATA6 DDR_B_D14
R23 AN29 K30
MA_DATA15/MAA_DATA3 15 DDR_B_RAS# MB_RAS_L_ADD16/MBB_CKE0 MB_DATA14/MBA_DATA2 DDR_B_D15
K29
DDR_A_BA0 AL22 P24 DDR_A_D16 MB_DATA15/MBA_DATA3
14 DDR_A_BA0 DDR_A_BA1 MA_BANK0/MAB_CS_L0 MA_DATA16/MAA_DATA17 DDR_A_D17 DDR_B_BA0 DDR_B_D16
AK27 R26 AN31 N32
14 DDR_A_BA1 MA_BANK1/MAB_CA1 MA_DATA17/MAA_DATA16 DDR_A_D18 15 DDR_B_BA0 DDR_B_BA1 MB_BANK0/MBB_CS_L0 MB_DATA16/MBA_DATA21 DDR_B_D17
T27 AM32 N29
DDR_A_BG0 MA_DATA18/MAA_DATA21 DDR_A_D19 15 DDR_B_BA1 MB_BANK1/MBB_CA1 MB_DATA17/MBA_DATA22 DDR_B_D18
AE27 V27 P30
14 DDR_A_BG0 DDR_A_BG1 MA_BG0/MAA_CS_L1 MA_DATA19/MAA_DATA20 DDR_A_D20 DDR_B_BG0 MB_DATA18/MBA_DATA20 DDR_B_D19
AE26 P25 AD29 L32
14 DDR_A_BG1 MA_BG1/MAA_CS_L0 MA_DATA20/MAA_DATA19 DDR_A_D21 15 DDR_B_BG0 DDR_B_BG1 MB_BG0/MBA_CS_L1 MB_DATA19/MBA_DATA19 DDR_B_D20
P27 AD31 L31
DDR_A_ACT_N MA_DATA21/MAA_DATA18 DDR_A_D22 15 DDR_B_BG1 MB_BG1/MBA_CS_L0 MB_DATA20/MBA_DATA17 DDR_B_D21
AD22 V23 M30
14 DDR_A_ACT_N MA_ACT_L/RSVD MA_DATA22/MAA_DATA23 DDR_A_D23 DDR_B_ACT_N MB_DATA21/MBA_DATA16 DDR_B_D22
T25 AD30 L29
DDRA_MA_DM0 MA_DATA23/MAA_DATA22 15 DDR_B_ACT_N MB_ACT_L/RSVD MB_DATA22/MBA_DATA18 DDR_B_D23
L27 N31
DDRA_MA_DM1 N23 MA_DM0/MAA_DM1 W22 DDR_A_D24 DDRA_MB_DM0 C30 MB_DATA23/MBA_DATA23
DDRA_MA_DM2 R27 MA_DM1/MAA_DM0 MA_DATA24/MAA_DATA30 Y23 DDR_A_D25 DDRA_MB_DM1 H32 MB_DM0/MBA_DM1 R30 DDR_B_D24
DDRA_MA_DM3 Y24 MA_DM2/MAA_DM2 MA_DATA25/MAA_DATA31 AC24 DDR_A_D26 DDRA_MB_DM2 M29 MB_DM1/MBA_DM0 MB_DATA24/MBA_DATA30 R32 DDR_B_D25
DDRA_MA_DM4 AP27 MA_DM3/MAA_DM3 MA_DATA26/MAA_DATA26 AC23 DDR_A_D27 DDRA_MB_DM3 T29 MB_DM2/MBA_DM2 MB_DATA25/MBA_DATA31 V30 DDR_B_D26
DDRA_MA_DM5 AW23 MA_DM4/MAB_DM2 MA_DATA27/MAA_DATA27 V21 DDR_A_D28 DDRA_MB_DM4 AU30 MB_DM3/MBA_DM3 MB_DATA26/MBA_DATA26 V32 DDR_B_D27
DDRA_MA_DM6 AT21 MA_DM5/MAB_DM3 MA_DATA28/MAA_DATA28 W21 DDR_A_D29 DDRA_MB_DM5 BD28 MB_DM4/MBB_DM2 MB_DATA27/MBA_DATA27 P29 DDR_B_D28
DDRA_MA_DM7 AV18 MA_DM6/MAB_DM1 MA_DATA29/MAA_DATA29 AA24 DDR_A_D30 DDRA_MB_DM6 BB23 MB_DM5/MBB_DM3 MB_DATA28/MBA_DATA28 P31 DDR_B_D29
W24 MA_DM7/MAB_DM0 MA_DATA30/MAA_DATA24 AA22 DDR_A_D31 DDRA_MB_DM7 BD20 MB_DM6/MBB_DM1 MB_DATA29/MBA_DATA29 U31 DDR_B_D30
MA_DM8/RSVD_52 MA_DATA31/MAA_DATA25 W31 MB_DM7/MBB_DM0 MB_DATA30/MBA_DATA25 U29 DDR_B_D31
DDR_A_DQS0 M25 AP26 DDR_A_D32 MB_DM8/RSVD_57 MB_DATA31/MBA_DATA24
DDR_A_DQS#0 M24 MA_DQS_H0/MAA_DQS_H1 MA_DATA32/MAB_DATA17 AN24 DDR_A_D33 DDR_B_DQS0 E29 AT29 DDR_B_D32
DDR_A_DQS1 P22 MA_DQS_L0/MAA_DQS_L1 MA_DATA33/MAB_DATA16 AR25 DDR_A_D34 DDR_B_DQS#0 D28 MB_DQS_H0/MBA_DQS_H1 MB_DATA32/MBB_DATA16 AU32 DDR_B_D33
DDR_A_DQS#1 P21 MA_DQS_H1/MAA_DQS_H0 MA_DATA34/MAB_DATA21 AU26 DDR_A_D35 DDR_B_DQS1 J31 MB_DQS_L0/MBA_DQS_L1 MB_DATA33/MBB_DATA17 AW31 DDR_B_D34
DDR_A_DQS2 T24 MA_DQS_L1/MAA_DQS_L0 MA_DATA35/MAB_DATA20 AN25 DDR_A_D36 DDR_B_DQS#1 J29 MB_DQS_H1/MBA_DQS_H0 MB_DATA34/MBB_DATA21 AW30 DDR_B_D35
DDR_A_DQS#2 R24 MA_DQS_H2/MAA_DQS_H2 MA_DATA36/MAB_DATA19 AN27 DDR_A_D37 DDR_B_DQS2 N30 MB_DQS_L1/MBA_DQS_L0 MB_DATA35/MBB_DATA20 AR30 DDR_B_D36
DDR_A_DQS3 AA21 MA_DQS_L2/MAA_DQS_L2 MA_DATA37/MAB_DATA18 AR27 DDR_A_D38 DDR_B_DQS#2 M31 MB_DQS_H2/MBA_DQS_H2 MB_DATA36/MBB_DATA19 AT31 DDR_B_D37
C DDR_A_DQS#3 Y21 MA_DQS_H3/MAA_DQS_H3 MA_DATA38/MAB_DATA23 AU27 DDR_A_D39 DDR_B_DQS3 T30 MB_DQS_L2/MBA_DQS_L2 MB_DATA37/MBB_DATA18 AV30 DDR_B_D38 C
DDR_A_DQS4 AP23 MA_DQS_L3/MAA_DQS_L3 MA_DATA39/MAB_DATA22 DDR_B_DQS#3 T31 MB_DQS_H3/MBA_DQS_H3 MB_DATA38/MBB_DATA23 AW29 DDR_B_D39
DDR_A_DQS#4 AP24 MA_DQS_H4/MAB_DQS_H2 AV25 DDR_A_D40 DDR_B_DQS4 AU29 MB_DQS_L3/MBA_DQS_L3 MB_DATA39/MBB_DATA22
DDR_A_DQS5 AW22 MA_DQS_L4/MAB_DQS_L2 MA_DATA40/MAB_DATA30 AW25 DDR_A_D41 DDR_B_DQS#4 AU31 MB_DQS_H4/MBB_DQS_H2 AY29 DDR_B_D40
DDR_A_DQS#5 AV22 MA_DQS_H5/MAB_DQS_H3 MA_DATA41/MAB_DATA31 AV20 DDR_A_D42 DDR_B_DQS5 BA27 MB_DQS_L4/MBB_DQS_L2 MB_DATA40/MBB_DATA29 AY32 DDR_B_D41
DDR_A_DQS6 AT20 MA_DQS_L5/MAB_DQS_L3 MA_DATA42/MAB_DATA26 AW20 DDR_A_D43 DDR_B_DQS#5 BB27 MB_DQS_H5/MBB_DQS_H3 MB_DATA41/MBB_DATA28 BC27 DDR_B_D42
DDR_A_DQS#6 AR20 MA_DQS_H6/MAB_DQS_H1 MA_DATA43/MAB_DATA27 AV27 DDR_A_D44 DDR_B_DQS6 BC23 MB_DQS_L5/MBB_DQS_L3 MB_DATA42/MBB_DATA24 BB26 DDR_B_D43
DDR_A_DQS7 AR18 MA_DQS_L6/MAB_DQS_L1 MA_DATA44/MAB_DATA28 AW26 DDR_A_D45 DDR_B_DQS#6 BA23 MB_DQS_H6/MBB_DQS_H1 MB_DATA43/MBB_DATA25 BC25 DDR_B_D44
DDR_A_DQS#7 AT18 MA_DQS_H7/MAB_DQS_H0 MA_DATA45/MAB_DATA29 AU21 DDR_A_D46 DDR_B_DQS7 BC20 MB_DQS_L6/MBB_DQS_L1 MB_DATA44/MBB_DATA27 BA25 DDR_B_D45
Y26 MA_DQS_L7/MAB_DQS_L0 MA_DATA46/MAB_DATA24 AW21 DDR_A_D47 DDR_B_DQS#7 BA20 MB_DQS_H7/MBB_DQS_H0 MB_DATA45/MBB_DATA26 BB30 DDR_B_D46
Y27 MA_DQS_H8/RSVD_58 MA_DATA47/MAB_DATA25 Y32 MB_DQS_L7/MBB_DQS_L0 MB_DATA46/MBB_DATA30 BA28 DDR_B_D47
MA_DQS_L8/RSVD_59 AT22 DDR_A_D48 Y30 MB_DQS_H8/RSVD_61 MB_DATA47/MBB_DATA31
SA_CLK_DDR0 AJ25 MA_DATA48/MAB_DATA11 AP21 DDR_A_D49 MB_DQS_L8/RSVD_60 BA24 DDR_B_D48
14 SA_CLK_DDR0 SA_CLK_DDR#0 MA_CLK_H0/MAA_CKT MA_DATA49/MAB_DATA10 DDR_A_D50 SB_CLK_DDR0 MB_DATA48/MBB_DATA11 DDR_B_D49
AJ24 AN19 AJ31 BC24
14 SA_CLK_DDR#0 SA_CLK_DDR1 MA_CLK_L0/MAA_CKC MA_DATA50/MAB_DATA14 DDR_A_D51 15 SB_CLK_DDR0 SB_CLK_DDR#0 MB_CLK_H0/MBA_CKT MB_DATA49/MBB_DATA10 DDR_B_D50
AJ22 AN18 AK30 BC22
14 SA_CLK_DDR1 SA_CLK_DDR#1 MA_CLK_H1/MAB_CKT MA_DATA51/MAB_DATA15 DDR_A_D52 15 SB_CLK_DDR#0 MB_CLK_L0/MBA_CKC MB_DATA50/MBB_DATA14 DDR_B_D51
AJ21 AU23 AK32 BA22

om
14 SA_CLK_DDR#1 MA_CLK_L1/MAB_CKC MA_DATA52/MAB_DATA12 DDR_A_D53 MB_CLK_H1/MBB_CKT MB_DATA51/MBB_DATA15 DDR_B_D52
AR22 AL31 BB25
MA_DATA53/MAB_DATA13 AN20 DDR_A_D54 MB_CLK_L1/MBB_CKC MB_DATA52/MBB_DATA12 BD25 DDR_B_D53
MA_DATA54/MAB_DATA9 AP19 DDR_A_D55 MB_DATA53/MBB_DATA13 BB22 DDR_B_D54
MA_DATA55/MAB_DATA8 MB_DATA54/MBB_DATA9 BD22 DDR_B_D55
AT19 DDR_A_D56 MB_DATA55/MBB_DATA8
DDR_A_CS0# AL25 MA_DATA56/MAB_DATA6 AW18 DDR_A_D57 BA21 DDR_B_D56
14 DDR_A_CS0# DDR_A_CS1# MA_CS_L0/MAB_CA2 MA_DATA57/MAB_DATA7 DDR_A_D58 DDR_B_CS0# MB_DATA56/MBB_DATA4 DDR_B_D57
AM26 AU16 AN30 BC21

.c
14 DDR_A_CS1# MA_CS_L1/MAB_CA5 MA_DATA58/MAB_DATA2 DDR_A_D59 15 DDR_B_CS0# MB_CS_L0/MBB_CA2 MB_DATA57/MBB_DATA5 DDR_B_D58
AW16 AR31 BC18
MA_DATA59/MAB_DATA3 AW19 DDR_A_D60 MB_CS_L1/MBB_CA5 MB_DATA58/MBB_DATA2 BB18 DDR_B_D59
MA_DATA60/MAB_DATA4 AU19 DDR_A_D61 MB_DATA59/MBB_DATA3 BB20 DDR_B_D60
MA_DATA61/MAB_DATA5 MB_DATA60/MBB_DATA6

ix
AP16 DDR_A_D62 BB21 DDR_B_D61
MA_DATA62/MAB_DATA1 AT16 DDR_A_D63 MB_DATA61/MBB_DATA7 BB19 DDR_B_D62
DDR_A_CKE0 AD24 MA_DATA63/MAB_DATA0 MB_DATA62/MBB_DATA1 BA18 DDR_B_D63
14 DDR_A_CKE0 DDR_A_CKE1 MA_CKE0/MAA_CA1 DDR_B_CKE0 MB_DATA63/MBB_DATA0
AD25 W27 AC31

af
14 DDR_A_CKE1 MA_CKE1/MAA_CA0 MA_CHECK0/RSVD_54 15 DDR_B_CKE0 MB_CKE0/MBA_CA1
W25 AC29 W30
MA_CHECK1/RSVD_53 AC26 MB_CKE1/MBA_CA0 MB_CHECK0/RSVD_56 W29
MA_CHECK2/RSVD_68 AC27 MB_CHECK1/RSVD_55 AA30
DDR_A_ODT0 AM24 MA_CHECK3/RSVD_69 V26 MB_CHECK2/RSVD_65 AB29

in
14 DDR_A_ODT0 DDR_A_ODT1 MA_ODT0/MAB_CA3 MA_CHECK4/RSVD_49 DDR_B_ODT0 MB_CHECK3/RSVD_67
B AM27 V24 AP32 V29 B
14 DDR_A_ODT1 MA_ODT1/MAB_CA4 MA_CHECK5/RSVD_48 15 DDR_B_ODT0 MB_ODT0/MBB_CA3 MB_CHECK4/RSVD_50
AA27 AR29 V31
MA_CHECK6/RSVD_63 AA25 MB_ODT1/MBB_CA4 MB_CHECK5/RSVD_51 AA29
MA_CHECK7/RSVD_62 MB_CHECK6/RSVD_64 AA31

//v
DDR_A_ALERT_N AE24 +1.2V +1.2V MB_CHECK7/RSVD_66
14 DDR_A_ALERT_N MA_ALERT_L/TEST31A DDR_A_PARITY DDR_B_ALERT_N
AK24 DDR_A_PARITY 14 15 DDR_B_ALERT_N AE30
DDR_A_EVENT# AK23 MA_PAROUT/RSVD DRAM@ MB_ALERT_L/TEST31B AM31 DDR_B_PARITY
14 DDR_A_EVENT# DDR4_A_DRAMRST# MA_EVENT_L DDR_B_EVENT# MB_PAROUT/RSVD DDR_B_PARITY 15
AD27 AN21 RC151 1 2 1K_0402_5% AL30
14 DDR4_A_DRAMRST# MA_RESET_L M_DDR4 DDR4_B_DRAMRST# MB_EVENT_L
FP6 REV0.92 AN22 AC32 FP6 REV0.92

s:
PART 1/13 M_LPDDR4 15 DDR4_B_DRAMRST# MB_RESET_L PART 9/13

AMD-RENOIR-FP6_BGA1140 AMD-RENOIR-FP6_BGA1140

tp
@ @

+1.2V ht
RC150 1 2 1K_0402_5% DDR_A_EVENT#

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/15 Deciphered Date 2013/08/15 FP6 (MEM)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document
Size DocumentNumber
Number Rev
Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
S350 ARE 1.0

Date:
Date: Sunday, January 19, 2020 Sheet
Sheet 5 of 45
5 4 3 2 1
 5 4 3 2 1

+3VS
RPC6 +1.8VS +1.8VS
UC1D DP_BLON=>VDD18 S0 APU_HDMI_DDC_CLK 1 4
APU_HDMI_DDC_DATA 2 3

2
APU_EDP_TX0+ D11 A22 DP_ENBKL PD FOR CUSTOMER
17 APU_EDP_TX0+ APU_EDP_TX0- B11 DP0_TXP0 DP_BLON D23 DP_ENVDD PU FOR INTERNAL
RC52 RC49
+1.8VALW 17 APU_EDP_TX0- DP0_TXN0 DP_DIGON C23 DP_EDP_PWM 2.2K_0404_4P2R_5%
eDP APU_EDP_TX1+ C11 DP_VARY_BL APU_EDP_HPD RC53 1 2 100K_0402_5%
39.2_0402_1%
@
1K_0402_5%
17 APU_EDP_TX1+ APU_EDP_TX1- A11 DP0_TXP1 D12 APU_EDP_AUX

APU_TEST31
17 APU_EDP_TX1- DP0_TXN1 DP0_AUXP APU_EDP_AUX 17

1
1

B12 APU_EDP_AUX# APU_TEST31 DP_STEREOSYNC

RC50 D10 DP0_AUXN C12 APU_EDP_HPD APU_EDP_AUX# 17 eDP M_TEST CONNECTION TBD
DP0_TXP2 DP0_HPD APU_EDP_HPD 17

2
4.7K_0402_5% B10 +1.8VS
DP0_TXN2 J20 APU_HDMI_DDC_CLK RC54 RC51
D9 DP1_AUXP K20 APU_HDMI_DDC_DATA APU_HDMI_DDC_CLK 19
DP0_TXP3 DP1_AUXN APU_HDMI_DDC_DATA 19 HDMI 39.2_0402_1% 1K_0402_5%
2

APU_RST# B9 L21 APU_HDMI_HPD @ @

DP0_TXN3 DP1_HPD APU_HDMI_HPD 19 RPC7

1
D APU_HDMI_TX2+ APU_TEST17 D
PLACE CC30 CAPS CLOSE TO APU,CRB reserve 27pf G23 L19 4 5
19 APU_HDMI_TX2+ APU_HDMI_TX2- H23 DP1_TXP0 DP2_AUXP M19 APU_TEST14 3 6
1 19 APU_HDMI_TX2- DP1_TXN0 DP2_AUXN M20 APU_TEST16 2 7
CC30 APU_HDMI_TX1+ F22 DP2_HPD APU_TEST15 1 8
56P_0201_50V8-J 19 APU_HDMI_TX1+ APU_HDMI_TX1- G22 DP1_TXP1 M14 check with AMD ,Follow CRB ,USE PU, 07/29
2 19 APU_HDMI_TX1- DP1_TXN1 DP3_AUXP L14
@
HDMI APU_HDMI_TX0+ G21 DP3_AUXN L16
10K_0804_8P4R_5%
19 APU_HDMI_TX0+ DP1_TXP2 DP3_HPD @
APU_HDMI_TX0- H21
19 APU_HDMI_TX0- DP1_TXN2 B23 DP_STEREOSYNC
APU_HDMI_CLK+ F20 DP_STEREOSYNC
+1.8VS +1.8VALW 19 APU_HDMI_CLK+ APU_HDMI_CLK- G20 DP1_TXP3
19 APU_HDMI_CLK- DP1_TXN3 To EDP panel +3VS
1

1
PU FOR INTERNAL
RC55
RC416 4.7K_0402_5% PD FOR CUSTOMER +3VALW RC56
300_0402_5% 4.7K_0402_5%
@
2

2
APU_PWROK RC147
10K_0402_5%
PCH_EDP_PWM 17
PLACE CC31 CAPS CLOSE TO APU,CRB reserve 27pf
1 BB6 TEST4 1 @ TC4
TEST4

3
BD5 TEST5 1 @ TC5 QC1B
CC31 TEST5

D2
56P_0201_50V8-J AG12 5
2 @ TEST6 G2
G25 APU_TEST14

S2
TEST14

6
K25 APU_TEST15
APU_TEST15
QC1A
TEST15 F25 APU_TEST16

D1
TEST16

4
F26 APU_TEST17
APU_TEST17 DP_EDP_PWM 2 PJT7838_SOT363-6
TEST17 G1
+3VS H26 APU_TEST311 @ TC7

S1
TEST31

1
RC58
RPC8 PJT7838_SOT363-6

1
AK9 1 @ TC8 100K_0402_5%
8 1 APU_SID TEST41
7 2 APU_SIC APU_TDI AP3 AK21
TDI ANALOGIO_0

2
6 3 APU_PROCHOT#_R APU_TDO AU1 AG21
C 5 4 ALERT# APU_TCK AR2 TDO ANALOGIO_1 C
APU_TMS AU3 TCK
APU_TRST# AR4 TMS
1/16W_1K_5%_8P4R_0804 APU_DBREQ# AT2 TRST_L
DBREQ_L +0.75VS

om
APU_RST# AW3 P3 SMU_ZVDDP RC60 1 2 196_0402_1%
APU_PWROK AW4 RESET_L SMU_ZVDD
43 APU_PWROK PWROK
@
RC62 2 1 0_0402_5% APU_SIC B22
+3VS_APU 25,31 EC_SMB_CK2 1 0_0402_5% APU_SID SIC DP_ENVDD
25,31 EC_SMB_DA2 RC63 2 @ D22 RC72 2 @ 1 0_0402_5%
ALERT# C22 SID AK7 VDDP_S5_SENSE 1 @ PCH_ENVDD 17
TC25
APU_THERMTRIP# AN9 ALERT_L VDDP_S5_SENSE AK12 APU_VDDP_RUN_FB_H 1 @

.c
TC11
31 APU_THERMTRIP# THERMTRIP_L VDDP_SENSE

1
RC66 2 @ 1 0_0402_5% APU_PROCHOT#_R B25 J23 VDDCR_SOC_VCC_SENSE
31,41
2 1K_0402_1% APU_THERMTRIP# H_PROCHOT# PROCHOT_L VDDCR_SOC_SENSE VDDCR_VCC_SENSE VDDCR_SOC_VCC_SENSE 43
RC67 1 K22 RC71
VDDCR_SENSE J21 VDDCR_VCC_SENSE 43
100K_0402_5%
VDDIO_MEM_S3_SENSE

ix
RC68 2 @ 1 0_0402_5% APU_SVC_RA D25
43 APU_SVC 1 0_0402_5% APU_SVD_RA SVC0 VDDCR_VSS_SENSE
RC69 2 @ C25 J22
43 APU_SVD SVD0 VSS_SENSE_A VDDCR_VSS_SENSE 43

2
RC70 2 @ 1 0_0402_5% APU_SVT_RA A25 FP6 REV0.92 AJ12 VSS_SENSEB 1 @ TC12
43 APU_SVT SVT0 PART 3/13 VSS_SENSE_B
LCD Power IC can change for PCH_ENVDD for cost down

af
AMD-RENOIR-FP6_BGA1140 VDDCR_SOC_VCC_SENSE 1 @ TC13
APU_SVC APU_SVD APU_SVT VDDCR_VCC_SENSE 1 @ TC14
@
VDDCR_VSS_SENSE 1 @

in
27P_25V_J_NPO_0201

27P_25V_J_NPO_0201

27P_25V_J_NPO_0201

TC15
1 1 1
CC34 CC35 CC36
@

//v
2 2 2
DP_ENBKL RC81 2 @ 1 0_0402_5%
PCH_ENBKL 17

s:

1
RC80
100K_0402_5%
@

tp

2
B
ht B

New HDT conn +1.8VALW +1.8VALW

JHDT1 +1.8VALW
1 1/16W_1K_5%_8P4R_0804
1 2
2 3 APU_TCK 8 1
3
2

4 APU_TMS 7 2 RC74
4 5 APU_TDI 6 3 1K_0402_5%
5 6 APU_TDO 1 HDT@ 2 APU_DBREQ# 5 4 HDT@
6 7 APU_PWROK RC78
7 8 APU_RST# 33_0402_5%
8 RPC9
1

9 APU_DBREQ#_R
9 10 APU_TRST#_R RC79 1 HDT@ 2 33_0402_5% HDT@ APU_TRST#
13 10 11
GND1 11 1
14 12 CC38
GND2 12 0.01U_6.3V_K_X7R_0201
HIGHS_FC1AF121-1151H HDT@
2
ME@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/15 Deciphered Date 2013/08/15 FP6 (DP/JTAG/SIV2/MISC)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OFSize
R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
S350 ARE 1.0

Date: Sunday, January 19, 2020 Sheet 6 of 45

5 4 3 2 1
 5 4 3 2 1

Mirror code: Platform allows RSMRST# = 0 to SPI tri-state

add reserved QC11,RC3268 For mirror 07/31 +1.8VALW +3VALW_APU

1
1 RC6

1
10K_0402_5% 0_0402_5%
RC4 CC21 @ PCIE_WAKE#_RA RC5 1 2 EC_PCIE_WAKE# 27,31
10K_0402_5% 10U 6.3V M X5R 0402 DC2
2 SYS_RESET# 1 2 SYS_PWRGD_R @

2
2
RC3 1 @ 2 0_0402_5% RSMRST#_R RC8 1 @ 2 0_0402_5% SYS_PWRGD_R RB751V-40_SOD323-2
31 EC_RSMRST# 31 EC_SYS_PWRGD
1 1 @
1
CC22 CC24 CC23
+3VL 0.1U_0201_6.3V6-K 0.1U_0201_6.3V6-K @ 0.1U_0201_6.3V6-K
2 2
2

1
RC3268
@ 10K_0402_5%
RC9 1 PCIE_RST0#_R
2 33_0402_5%
22,27,29 PLT_RST#

6
D D D

2
2 QC11A

1
G 2N7002KDWH_SOT363-6 1
@ RC10 CC148
S 100K_0402_5% 150P_25V_J_NPO_0402

1
3
D @
2 RPC1
5 QC11B

2
G 2N7002KDWH_SOT363-6 EGPIO145 1 4
@ EGPIO146 2 3
S

4
UC1E 10K_0404_4P2R_5%
AM3
SFH_IPIO271 AT4
SFH_IPIO272 AM1 EGPIO147 RC211 1 2 10K_0402_5%
SFH_IPIO273 AJ8
SFH_IPIO274 AW7
SFH_IPIO39 AU2
PCIE_RST0#_R AP6 SFH_IPIO41
PCIE_RST1#_R AT13 PCIE_RST0_L/EGPIO26 AP14 EGPIO145 If unused, enable internal pull up or pull down by software.
RSMRST#_R AR8 PCIE_RST1_L/EGPIO27 I2C0_SCL/EGPIO145 AN14 EGPIO146
PM_SLP_S3# CC146 @1 2 2200P_25V_K_X7R_0201 RSMRST_L I2C0_SDA/EGPIO146
PM_SLP_S5# CC147 @1 2 2200P_25V_K_X7R_0201 PBTN_OUT# RC11 1 @ 2 0_0402_5% PWRBTN#_R AT12 AP2 EGPIO147
31 PBTN_OUT# SYS_PWRGD_R PWR_BTN_L/AGPIO0 I2C1_SCL/EGPIO147 BOARD_ID4
AW2 AN3 E14 is ID3 +1.8VS
SYS_RESET# AL2 PWR_GOOD I2C1_SDA/EGPIO148
13 SYS_RESET# PCIE_WAKE#_RA SYS_RESET_L/AGPIO1
AW12 AN12 I2C2_SCL_APU RC501 2 @ 1 0_0402_5%
WAKE_L/AGPIO2 I2C2_SCL/EGPIO113/SMBUS0_I2C_SCL AP12 I2C2_SDA_APU RC500 2 @ 1 0_0402_5%
APU_SMB_CLK 14 SO-DIMM
PM_SLP_S3# PM_SLP_S3#_R I2C2_SDA/EGPIO114/SMBUS0_I2C_SDA APU_SMB_DATA 14
RC14 2 @ 1 0_0402_5% AT11
31 PM_SLP_S3# PM_SLP_S5# PM_SLP_S5#_R SLP_S3_L TP_I2C3_SCL_R
RC15 2 @ 1 0_0402_5% AV11 AM9
13,31 PM_SLP_S5# SLP_S5_L I2C3_SCL/AGPIO19/SMBUS1_I2C_SCL AM10 TP_I2C3_SDA_R TP_I2C3_SCL_R 13,32 Touch Pad
I2C3_SDA/AGPIO20/SMBUS1_I2C_SDA TP_I2C3_SDA_R 13,32
AW13
S0A3_GPIO/AGPIO10 D24
AC_PRESENT BA8 SFH1_SCL B24
31 AC_PRESENT AC_PRES/AGPIO23 SFH1_SDA
+3VALW_APU RC16 1 2 10K_0402_5% BATLOW# AV6
LLB_L/AGPIO12
BB7 BOARD_ID8
AW8 AGPIO3 BA6
EGPIO42 AGPIO4/SATAE_IFDET SSD_SATA_PCIE_DET1# 22
+3VS_APU
AK10 USBDEBUG OD,Pull high 3VALW?
AGPIO5/DEVSLP0 SATA_DEVSLP1 USBDEBUG 20
Follow E14 07/30 BC6 RPC2
AGPIO6/DEVSLP1 BOARD_ID0 SATA_DEVSLP1 22 I2C2_SCL_APU
AW15 3 2
SATA_ACT_L/AGPIO130 Follow E1415 Wait for define Board ID 07/27 I2C2_SDA_APU 4 1
AG6 AU4 PCH_TP_INT1#
AG7 ACP_WOV_CLK AGPIO9 AP7 APU_SSD_RST# PCH_TP_INT1# 32 2.2K_0404_4P2R_5%
AJ6 ACP_WOV_MIC0_MIC1_DATA AGPIO40 AV13 BOARD_ID2 APU_SSD_RST# 22
ACP_WOV_MIC2_MIC3_DATA AGPIO69 BB12 EC_SMI# +3VS_APU
C HDA_BITCLK AGPIO86/SPI_CLK2 EC_SMI# 31 C
AN6
RC19 1 @ 2 0_0402_5% HDA_SDIN0_R AL6 AZ_BITCLK/TDM_BCLK_MIC
28 HDA_SDIN0 HDA_SDIN1 AZ_SDIN0/CODEC_GPI INTRUDER_ALERT EC_SMI#
TC1 @ 1 AM7 AU7 RC20 2 @ 1 20M_0402_5% VCCRTC RC21 1 2 2.2K_0402_5%
TC2 @ 1 HDA_SDIN2 AJ9 AZ_SDIN1/SW_DATA1B/TDM_BCLK_PLAYBACK INTRUDER_ALERT AR11 PCH_TP_INT# RC22 1 2 10K_0402_5%
HDA_RST# AZ_SDIN2/SW_DATA2/TDM_DATA_PLAYBACK/ACP_WOV_MIC4_MIC5_DATA SPKR/AGPIO91 PCH_BEEP 28
AM6 AW11 BLINK
AZ_RST_L/SW_DATA1A/SW_DATA3/TDM_DATA_MIC BLINK/AGPIO11

om
HDA_SYNC AN8
HDA_SDOUT AK6 AZ_SYNC/TDM_FRM_MIC AV15 PCH_TP_INT#
AZ_SDOUT/TDM_FRM_PLAYBACK GENINT1_L/AGPIO89 BOARD_ID9 PCH_TP_INT# 32
AU14 +3VALW_APU
AM4 GENINT2_L/AGPIO90
AL3 SW_MCLK/TDM_BCLK_BT
BOARD_ID7 AM2 SW_DATA0/TDM_DOUT_BT AT10 PCH_WLAN_OFF# RPC3
Board ID Description Stuff R AGPIO7/FCH_ACP_I2S_SDIN_BT FANIN0/AGPIO84 PCH_WLAN_OFF# 27
BOARD_ID6 AL4 FP6 REV0.92 AU10 PCH_BT_OFF# TP_I2C3_SDA_R 3 2
AGPIO8/FCH_ACP_I2S_LRCLK_BT PART 4/13 FANOUT0/AGPIO85 PCH_BT_OFF# 27 TP_I2C3_SCL_R

.c
4 1
00 14 RC35 RC36
AMD-RENOIR-FP6_BGA1140 2.2K_0404_4P2R_5%
@
01 15 RC35 RC43 +3VS_APU +3VALW_APU

ix
Board_ID[0,1] RPC4
PBTN_OUT# 1 8
RPC59 PCIE_WAKE#_RA
10 17 RC42 RC36 2 7

af
PCH_WLAN_OFF# 1 4 AC_PRESENT 3 6
PCH_BT_OFF# 2 3 4 5
11 Reserved RC42 RC43
10K_0404_4P2R_5% 10K_0804_8P4R_5%
RPC5

in
0000 Hynix 8Gb RC44 RC41 RC45 RC46 BLINK RC24 1 @ 2 10K_0402_5%
TC3 @ 1 HDA_RST_AUDIO# 1 8 HDA_RST# PM_SLP_S3# RC25 1 @ 2 2.2K_0402_5%
2 7 HDA_SYNC PM_SLP_S5# RC26 1 @ 2 2.2K_0402_5%
28 HDA_SYNC_AUDIO HDA_BITCLK APU_SSD_RST#
0001 Micron 8Gb RC44 RC41 RC45 RC39 3 6 RC27 1 @ 2 10K_0402_5%

//v
28 HDA_BITCLK_AUDIO HDA_SDOUT
4 5
28 HDA_SDOUT_AUDIO SATA_DEVSLP1 RC415 1 @ 2 10K_0402_5%
0010 DIMM_ONLY RC44 RC41 RC38 RC46 1/16W_33_5%_8P4R_0804
Board_ID[2,3,4,5] +3VS_APU +3VALW_APU PCH_TP_INT1# RC437 1 TP_W@ 2 10K_0402_5%

s:
0011 Samsung 8Gb RC44 RC41 RC38 RC39
PCH_TP_INT# RC28 1 @ 2 10K_0402_5%
2

RSMRST#_R RC32 1 @ 2 100K_0402_5%

0100 Reserved RC44 RC48 RC45 RC46 RC174 RC172 SYS_PWRGD_R RC33 1 2 100K_0402_5%

tp
10K_0402_5% 10K_0402_5%
@ S350ARE@ PCIE_RST1#_R RC34 1 2 10K_0402_5%
0101 Reserved RC44 RC48 RC45 RC39 @
1

BOARD_ID8

B Board_ID6
0 NON-TS RC426 BOARD_ID9
ht B

1 TS RC424
1

RC175 RC173
0 NON-FP RC171 2K_0402_5% 2K_0402_5%
Board_ID7 @ S145API@
For EMI
HDA_BITCLK
1 FP RC170 1
2

+3VALW_APU
+1.8VS +3VS_APU CC27
0 S145API RC173 56P_50V_J_NPO_0201
2 EMC@
Board_ID8
1 S350ARE RC172 Close to PCH
1

0 Reserved RC175
2

Board_ID9 RC424 RC170 RC38

2K_0402_5% 2K_0402_5% 10K_0402_5% RC39
1 Reserved RC174 TS@ FP@ @ 10K_0402_5%
EGPIO148 ID4 +1.8VS @
2

AGPIO85 ID5 +3.3VS

1

BOARD_ID4
BOARD_ID5
8 BOARD_ID5 BOARD_ID6
AGPIO8 ID6 +3.3VALW BOARD_ID7

AGPIO7 ID7 +3.3VALW

2

RC45 RC46
2

RC426 RC171 10K_0402_5% 2K_0402_5%

10K_0402_5% 10K_0402_5% @ @
NOTS@ NOFP@
ADD BOARD ID6~7 07/31
1

+3VS_APU
1

1
2

RC42 RC43 RC48

10K_0402_5% 10K_0402_5% RC37 10K_0402_5%
@ @ 2K_0402_5% @
A A
@
1

BOARD_ID0
AGPIO130 ID0
BOARD_ID1 EGPIO142 ID1
8 BOARD_ID1 BOARD_ID2 AGPIO69 ID2
BOARD_ID3
8 BOARD_ID3 ID0~2 Follw E14, ID4 is Change E14 ID3
1

RC44
RC35 RC36 10K_0402_5% RC41
2K_0402_5% 2K_0402_5% @ 2K_0402_5% Title
@ @ @ Security Classification LC Future Center Secret Data
Issued Date 2013/08/15 Deciphered Date 2013/08/15 FP6 AZ/I2C/ACPI/GPIO
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S350 ARE
Date: Sunday, January 19, 2020 Sheet 7 of 45
5 4 3 2 1
 5 4 3 2 1

LPCCLK0 PCH_SPI_CLK

2
RC82 1 2 33_0402_5% LPC_RST#_R
13,31 APU_LPC_RST#
RC83
1 0_0201_5% RC90
CC41 EMC_NS@ 10_0402_5%
150P_25V_J_NPO_0402 EMC_NS@

1
2
1 1
CC42 CC43
22P_0201_25V8 10P_0201_25V8G
EMC_NS@ EMC_NS@
+3VS_APU 2 2
RPC11
SSD_CLKREQ#
EMC EMC
D 1 4 D
2 3 WLAN_CLKREQ# UC1F

10K_0404_4P2R_5%

SSD_CLKREQ# AR13
22 SSD_CLKREQ# WLAN_CLKREQ# CLK_REQ0_L/SATA_IS0_L/SATA_ZP0_L/AGPIO92
AP10
27 WLAN_CLKREQ# CLK_REQ1_L/AGPIO115
AR15
BOARD_ID3 AT14 CLK_REQ2_L/AGPIO116
7 BOARD_ID3 BOARD_ID5 AN11 CLK_REQ3_L/SATA_IS1_L/SATA_ZP1_L/EGPIO131
7 BOARD_ID5 AN13 CLK_REQ4_L/OSCIN/EGPIO132
AN15 CLK_REQ5_L/EGPIO120
CLK_REQ6_L/EGPIO121 +3VS_APU
AW14 FPR_RESETN APU-->FP RESET(common design)
EGPIO70 FPR_RESETN 32
BB13 LPCPD# LPCPD# 13
CLK_PCIE_SSD RC84 2 @ 1 0_0402_5% CLK_PCIE_SSD_R AF11 LPC_PD_L/AGPIO21 BA16 LAD0 RC85 1 2 10_0402_5% LPC_FRAME# RC94 1 @ 2 10K_0402_5%
22 CLK_PCIE_SSD CLK_PCIE_SSD# GPP_CLK0P LAD0/ESPI1_DATA0/EGPIO104 LPC_AD0 31
PCIE CLK0 SSD1 RC86 2 @ 1 0_0402_5% CLK_PCIE_SSD#_R AF12 BA15 LAD1 RC87 1 2 10_0402_5%
22 CLK_PCIE_SSD# GPP_CLK0N LAD1/ESPI1_DATA1/EGPIO105 LPC_AD1 31
BC13 LAD2 RC88 1 2 10_0402_5% LPC_AD2 31 KBRST# RC96 1 2 10K_0402_5%
CLK_PCIE_WLAN RC89 2 @ 1 0_0402_5% CLK_PCIE_WLAN_R AG4 LAD2/ESPI1_DATA2/EGPIO106 BB14 LAD3 RC91 1 2 10_0402_5%
27 CLK_PCIE_WLAN GPP_CLK1P LAD3/ESPI1_DATA3/EGPIO107 LPC_AD3 31
CLK_PCIE_WLAN# RC92 2 @ 1 0_0402_5% CLK_PCIE_WLAN#_R AG2 BB15 LPCCLK0 RC93 2 1 3.3_0402_1% LDRQ0#_R RC322 1 2 10K_0402_5%
PCIE CLK1 WLAN 27 CLK_PCIE_WLAN# GPP_CLK1N LPCCLK0/EGPIO74 LPC_CLKRUN#_R RC417 CLK_PCI_EC 31
BD13 1 @ 2 0_0402_5%
LPC_CLKRUN_L/AGPIO88 LPC_CLKRUN# 13
AG3 BA12 EGPIO75
AG1 GPP_CLK2P LPCCLK1/EGPIO75 BC15 +3VALW_APU
GPP_CLK2N SERIRQ/AGPIO87 SERIRQ 13,31
BA13
AF2 LFRAME_L/EGPIO109 LPC_FRAME# 31 EC_SCI# 1 2 10K_0402_5%
RC100 @
AF4 GPP_CLK3P BC12 LPC_RST#_R
Follow CRB 0Ω resistor pull down GPP_CLK3N LPC_RST_L/AGPIO32 AU12 1 TC32@
AH2 AGPIO68 AP4 EC_SCI# Follow E14 07/31
GPP_CLK4P LPC_PME_L/AGPIO22 EC_SCI# 31
RC98 1 @ 2 0_0402_5% XGBECLK0 AH4
RC99 1 @ 2 0_0402_5% XGBECLK1 GPP_CLK4N
AJ2 @
AJ4 GPP_CLK5P BA11 AGPIO30 10K_0402_5% 1 2 RC116
GPP_CLK5N SPI_ROM_REQ/EGPIO67 BB11
AF8 SPI_ROM_GNT/EGPIO76
AF9 GPP_CLK6P/WIFIBT_CLKP AT15 KBRST# EGPIO75 10K_0402_5% 1 @ 2 RC117
GPP_CLK6N/WIFIBT_CLKN ESPI_RESET_L/KBRST_L/AGPIO129 LDRQ0#_R RC101 KBRST# 31
BC11 1 LPC@ 2 0_0402_5% LDRQ0# LDRQ0# 13
TC16 @ 1 48M_OSC AK1 ESPI_ALERT_L/LDRQ0_L/EGPIO108
X48M_OSC BC10 SPI_CLK RC102 1 2 10_0402_5% PCH_SPI_CLKM
C SPI_CLK/ESPI_CLK C
BA10 SPI_D1 RC103 2 @ 1 0_0402_5% PCH_SPI_D1_R
X48M_X1 BB3 SPI_DI/ESPI_DATA BB8 SPI_D0 RC104 2 @ 1 0_0402_5% PCH_SPI_D0_R
X48M_X1 SPI_DO BA9 SPI_D2 RC105 2 @ 1 0_0402_5% PCH_SPI_D2
SPI_WP_L/ESPI_DAT2 BC8 SPI_D3 RC106 2 @ 1 0_0402_5% PCH_SPI_D3
SPI_HOLD_L/ESPI_DAT3 BD11 SPI_CS1# RC107 2 @ 1 0_0402_5% PCH_SPI_CS1#
SPI_CS1_L

om
X48M_X2 BA5 BC9 AGPIO30
X48M_X2 SPI_CS2_L/ESPI_CS_L/AGPIO30 BB10 PCH_SPI_PIRQ#_R RC418 1 TPM@ 2 0_0402_5%
SPI_CS3_L/AGPIO31 SPI_CS#_TPM PCH_SPI_PIRQ# 29
BD8
SPI_TPM_CS_L/AGPIO29 SPI_CS#_TPM 29 +3VS_APU

XGBECLK0 AG10
RSVD_71

.c
XGBECLK1 AG9
RSVD_70

1 RC108 2

1 RC109 2

1 RC111 2
1K_0402_1%

1K_0402_1%

1K_0402_1%
AW10

ix
22,27 SUSCLK RTCCLK

X32K_X1 AY1 BA17 APU_UART0_RXD

@ @ @

af
X32K_X1 EGPIO141/UART0_RXD BC16 APU_UART0_TXD
EGPIO143/UART0_TXD BD15 BOARD_ID1
EGPIO142/UART0_RTS_L/UART1_RXD APU_UART0_CTS# BOARD_ID1 7
BC17 BOARD ID2 Follow E14 3.3_SO Power 07/31
RC113 X32K_X2 AY4 EGPIO140/UART0_CTS_L/UART1_TXD BB16

in
1 2 X32K_X2 AGPIO144/SHUTDOWN_L/UART0_INTR
20M_0402_5% FP6 REV0.92
YC1 PART 5/13

//v
1 2
AMD-RENOIR-FP6_BGA1140
32.768KHZ_12.5PF_202740-PG14 @ ADD QC7 For Mirror required 07/31

1 1

s:
+3VALW_APU

48MHz/10pF Crystal X48M_X1

CC44
9P_50V_B_NPO_0402
CC45
9P_50V_B_NPO_0402
2 2

tp
X48M_X2 11/30 CC44,CC45 Change from 10pF , 12pF to 9pF

2
B ht B
RC115 1 2 1M_0402_5%
Kevin H: change YC1 PN change to SJ10000MQ00,manual modify PN to SJ10000MQ00 PCH_SPI_CLKM 3 1 PCH_SPI_CLK_R
PCH_SPI_CLK_R 13
YC2

1 4 +1.8V_SPI +1.8VALW QC7

OSC1 NC2 UC3 LSI1012XT1G_SC-89-3
PCH_SPI_CS1# +1.8V_SPI
0.085 A
2 3 1 8 RC118 1 @ 2 0_0402_5% RC3269 1 2 0_0402_5%
NC1 OSC2 /CS VCC
PCH_SPI_D1 2 7 PCH_SPI_D3 @
1 1 DO /RESET 1
48MHZ_10PF_7V48000017
CC46 SJ10000VD00 CC47 PCH_SPI_D2 3 6 PCH_SPI_CLK CC48
6P_0402_50V8D 6P_0402_50V8D /WP CLK 0.1U_0201_6.3V6-K
2 2 4 5 PCH_SPI_D0 2 PCH_SPI_CLK_R RC159 2 @ 1 0_0402_5% PCH_SPI_CLK
GND DI
Need change to ±10ppm
RC160 1 @ 2 0_0402_5%
EC_SPI_CLK 31
W25Q128JWSIQ_SO8 RC161 1 TPM@ 2 0_0402_5%
16MB(128Mb) TPM_SPI_CLK 29
11/30 CC46,CC47 Change from 8pF to 6pF
PCH_SPI_CS1# RC162 2 @ 1 0_0402_5% EC_SPI_CS1#
EC_SPI_CS1# 31

PCH_SPI_D0_R RC163 2 @ 1 0_0402_5% PCH_SPI_D0

+1.8V_SPI
RC164 1 @ 2 0_0402_5%
PCH_SPI_CS1# EC_SPI_SI 31
RC119 1 2 10K_0402_5%
RC120 1 2 10K_0402_5% PCH_SPI_D1 RC165 1 TPM@ 2 0_0402_5%
PCH_SPI_D2 TPM_SPI_MOSI 29
RC121 1 @ 2 10K_0402_5%
RC122 1 @ 2 10K_0402_5% PCH_SPI_D3

PCH_SPI_D1_R RC166 2 @ 1 0_0402_5% PCH_SPI_D1

RC167 1 @ 2 0_0402_5%
EC_SPI_SO 31
A RC168 1 TPM@ 2 0_0402_5% A
TPM_SPI_MISO 29

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/15 Deciphered Date 2013/08/15 FP6 CLK/LPC/SD/EMMC/UART

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
S350 ARE 1.0

Date: Sunday, January 19, 2020 Sheet 8 of 45

5 4 3 2 Date: 1 Sheet
 5 4 3 2 1

UC1G

N7 P8
R7 AGPIO256/WIFIBT_BT_DATA EGPIO267/RFIC_SPI_CLK R9
N6 AGPIO257/WIFIBT_BT_VALID EGPIO268/RFIC_SPI_SS R6
T6 AGPIO258/WIFIBT_BT_SYNC AGPIO269/RFIC_SPI_DATA
AGPIO259/WIFIBT_BT_CLK

D R10 P9 D
T12 AGPIO260/WIFIBT_QSPI_DATA0
AGPIO270/WIFIBT_RFIC_WAKEUP T9
P12 AGPIO261/WIFIBT_QSPI_DATA1 EGPIO271/WIFIBT_BUCKEN T8
P11 AGPIO262/WIFIBT_QSPI_DATA2 EGPIO266/WIFIBT_FLOW
T11 AGPIO263/WIFIBT_QSPI_DATA3
P6 AGPIO264/WIFIBT_QSPI_CLK
AGPIO265/WIFIBT_QSPI_SS V7
WIFIBT_DATA_RXP V6
WIFIBT_DATA_RXN
V9
WIFIBT_DATA_TXP V10
WIFIBT_DATA_TXN
FP6 REV0.92
PART 12/13

AMD-RENOIR-FP6_BGA1140
@

UC1H

For USB 2.0 port USB20_P0 AC6 AA1

21 USB20_P0 USB20_N0 USBC0_DP/USB0_DP USBC0_TX1P/USB0_TXP/DP2_TXP2
USB P0 AC7 AA3
21 USB20_N0 USBC0_DN/USB0_DN USBC0_TX1N/USB0_TXN/DP2_TXN2
USB20_P1 AA8 AA2
20 USB20_P1 USB1_DP USBC0_RX1P/USB0_RXP/DP2_TXP3
USB3.0 port1 upper USB20_N1 AA9 AA4
20 USB20_N1 USB1_DN USBC0_RX1N/USB0_RXN/DP2_TXN3
USB P1
USB20_P2 Y10 AC2
17 USB20_P2 USB20_N2 USB2_DP USBC0_TX2P/DP2_TXP1
For camera 17 USB20_N2 Y9 AC4
USB P2 USB2_DN USBC0_TX2N/DP2_TXN1
USB20_P3 Y7 AC1
17 USB20_P3 USB20_N3 USB3_DP USBC0_RX2P/DP2_TXP0
Touch Screen 17 USB20_N3 Y6 AC3
USB P3 USB3_DN USBC0_RX2N/DP2_TXN0
AE1 USB30_TX_P1
USB1_TXP USB30_TX_N1 USB30_TX_P1 20
AE3
USB20_P4 USB1_TXN USB30_TX_N1 20
AC9
20 USB20_P4 USB20_N4 USBC4_DP/USB4_DP USB30_RX_P1
USB3.0 port2 lower 20 USB20_N4 AC10 AD8 USB30_RX_P1 20 USB3.0 Port1 upper
USB P4 USBC4_DN/USB4_DN USB1_RXP AD9 USB30_RX_N1
USB20_P5 USB1_RXN USB30_RX_N1 20
C IO Board for Card reader AA11 C
28 USB20_P5 USB20_N5 USB5_DP
USB P5 28 USB20_N5 AA12
USB5_DN
BT USB20_P6 W8
27 USB20_P6 USB20_N6 USB6_DP USB30_TX_P4
USB P6 27 USB20_N6 W9 V3
USB6_DN USBC4_TX1P/USB4_TXP/DP3_TXP2 USB30_TX_N4 USB30_TX_P4 20
V1
USB20_P7 USBC4_TX1N/USB4_TXN/DP3_TXN2 USB30_TX_N4 20
Finger print W11
32 USB20_P7 USB20_N7 USB7_DP USB30_RX_P4
USB P7 32 USB20_N7 W12 U4 USB30_RX_P4 20 USB3.0 port2 lower
+1.8VALW USB7_DN USBC4_RX1P/USB4_RXP/DP3_TXP3 U2 USB30_RX_N4
USBC4_RX1N/USB4_RXN/DP3_TXN3 USB30_RX_N4 20
RPC57
1 4 USBC_I2C_SCL AL9 W2
2 3 USBC_I2C_SCL USBC4_TX2P/DP3_TXP1 W4
@ USBC_I2C_SDA AL8 USBC4_TX2N/DP3_TXN1
4.7K_0404_4P2R_5% USBC_I2C_SDA W1
USBC4_RX2P/DP3_TXP0 W3
USB_OC0# USBC4_RX2N/DP3_TXN0

om
21 USB_OC0# AE9
USB_OC1# AE10 USB_OC0_L/AGPIO16 AD2
20 USB_OC1# USB_OC1_L/AGPIO17 USB5_TXP
USB_OC2# AE6 AD4
20 USB_OC2# USB_OC2_L/AGPIO18 USB5_TXN
AE7
USB_OC3_L/AGPIO24 AD12
USB5_RXP AD11
USB5_RXN

.c
FP6 REV0.92
PART 10/13

AMD-RENOIR-FP6_BGA1140
@

ix
af
in
//v
+3VALW_APU

B RPC58 B
USB_OC0# 1 8

s:
USB_OC1# 2 7
USB_OC2# 3 6
4 5

10K_0804_8P4R_5%

tp
ht

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/15 Deciphered Date 2013/08/15 FP6 USB/WIFI

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Size
D Document Number Rev 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S350 ARE
Date: Sunday, January 19, 2020 Sheet 9 of 45
5 4 3 2 Date: 1 Sheet
 5 4 3 2 1

D D

UC1I

D21 A18
A20 CAM0_CSI2_CLOCKP CAM0_CLK
CAM0_CSI2_CLOCKN C18
D18 CAM0_I2C_SCL B17
B18 CAM0_CSI2_DATAP0 CAM0_I2C_SDA
C C
CAM0_CSI2_DATAN0 D17
C19 CAM0_SHUTDOWN
D20 CAM0_CSI2_DATAP1

om
CAM0_CSI2_DATAN1
C21
B21 CAM0_CSI2_DATAP2
CAM0_CSI2_DATAN2
C20
B20 CAM0_CSI2_DATAP3
CAM0_CSI2_DATAN3

.c
C15 A13
A15 CAM1_CSI2_CLOCKP CAM1_CLK
CAM1_CSI2_CLOCKN B13

ix
D16 CAM1_I2C_SCL D13
B16 CAM1_CSI2_DATAP0 CAM1_I2C_SDA
CAM1_CSI2_DATAN0 C14

af
D15 CAM1_SHUTDOWN
B15 CAM1_CSI2_DATAP1 C16
CAM1_CSI2_DATAN1 FP6 REV0.92 CAM_PRIV_LED C13
CAM_IR_ILLU

in
PART 13/13

AMD-RENOIR-FP6_BGA1140

//v
@

s:
tp
B
ht B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/15 Deciphered Date 2013/08/15 FP6 CAM

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
S350 ARE 1.0

Date: Sunday, January 19, 2020 Sheet 10 of 45

5 4 3 2 1
 5 4 3 2 1

+VDDC_VDD
+VDDCR_SOC +VDDC_VDD
UC1J
15A N16 G7 44A
N18 VDDCR_SOC_1 VDDCR_1 G10
N20 VDDCR_SOC_2 VDDCR_2 G12

180P_50V_J_NPO_0402
P17 VDDCR_SOC_3 VDDCR_3 G14
P19 VDDCR_SOC_4 VDDCR_4 H8
VDDCR_SOC_5 VDDCR_5 1
R18 H11

CC60
R20 VDDCR_SOC_6 VDDCR_6 H15
T19 VDDCR_SOC_7 VDDCR_7 K6
U18 VDDCR_SOC_8 VDDCR_8 K12 2
U20 VDDCR_SOC_9 VDDCR_9 K14
D D
V19 VDDCR_SOC_10 VDDCR_10 L8
W18 VDDCR_SOC_11 VDDCR_11 M7
W20 VDDCR_SOC_12 VDDCR_12 M10
Y19 VDDCR_SOC_13 VDDCR_13 N14
VDDCR_SOC_14 VDDCR_14 P7
VDDCR_15 P10
+1.2V VDDCR_16 P13
VDDCR_17 P15
6A AC20 VDDCR_18 R8
AC28 VDDIO_MEM_S3_1 VDDCR_19 R14
AD23 VDDIO_MEM_S3_2 VDDCR_20 R16
AD26 VDDIO_MEM_S3_3 VDDCR_21 T7 +VDDCR_SOC
VDDIO_MEM_S3_4 VDDCR_22

22UC_6.3VC_MC_X5RC_0603
AD28 T10
AD32 VDDIO_MEM_S3_5 VDDCR_23 T13
+3VS_APU AE20 VDDIO_MEM_S3_6 VDDCR_24 T15
+3VS AE22 VDDIO_MEM_S3_7 VDDCR_25 T17

180P_50V_J_NPO_0402
AE25 VDDIO_MEM_S3_8 VDDCR_26 U14

1U_0402_6.3V6K
AE28 VDDIO_MEM_S3_9 VDDCR_27 U16

22UC_6.3VC_MC_X5RC_0603
1 1

1U_0402_6.3V6K

1U_0402_6.3V6K
RC125 1 @ 2 0_0402_5%1 AF23 VDDIO_MEM_S3_10 VDDCR_28 V13

CC76

CC77
1 1 1 VDDIO_MEM_S3_11 VDDCR_29
AF26 V15

CC141
CC66

CC67

CC68
VDDIO_MEM_S3_12 VDDCR_30
22UC_6.3VC_MC_X5RC_0603

AF28 V17
@ AF32 VDDIO_MEM_S3_13 VDDCR_31 W7 2 2
2 2 2 2 AG20 VDDIO_MEM_S3_14 VDDCR_32 W10
AG22 VDDIO_MEM_S3_15 VDDCR_33 W14
+1.8VS BO BU AG25 VDDIO_MEM_S3_16 VDDCR_34 W16
AG28 VDDIO_MEM_S3_17 VDDCR_35 Y8
1U_0402_6.3V6K

1U_0402_6.3V6K

AJ20 VDDIO_MEM_S3_18 VDDCR_36 Y13

1 1 1 VDDIO_MEM_S3_19 VDDCR_37
AJ23 Y15
CC78

CC79

CC80

AJ26 VDDIO_MEM_S3_20 VDDCR_38 Y17

@ AJ28 VDDIO_MEM_S3_21 VDDCR_39 AA7
2 2 2 AJ32 VDDIO_MEM_S3_22 VDDCR_40 AA10
+1.8VS +1.8VALW VDDIO_MEM_S3_23 VDDCR_41
22UC_6.3VC_MC_X5RC_0603

AK22 AA14
BO BU AK25 VDDIO_MEM_S3_24 VDDCR_42 AA16
AK28 VDDIO_MEM_S3_25 VDDCR_43 AA18
+1.8VALW AL23 VDDIO_MEM_S3_26 VDDCR_44 AB13
VDDIO_MEM_S3_27 VDDCR_45

2
AL26 AB15
1U_0402_6.3V6K

1U_0402_6.3V6K

RC126 RC127 AL28 VDDIO_MEM_S3_28 VDDCR_46 AB17 +1.2V

1 1 VDDIO_MEM_S3_29 VDDCR_47
1 0_0402_5% 0_0402_5% AL32 AB19
CC82

CC83

AM22 VDDIO_MEM_S3_30 VDDCR_48 AC14

CC81

@ @ @ +VDD_AUD_ALW AM25 VDDIO_MEM_S3_31 VDDCR_49 AC16

2 2 VDDIO_MEM_S3_32 VDDCR_50

1
AM28 AC18

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

180P_50V_J_NPO_0402
0.22U_0201_6.3V6-K
2 VDDIO_MEM_S3_33 VDDCR_51
22UC_6.3VC_MC_X5RC_0603

AN28 AD7

1U_0402_6.3V6K

1U_0402_6.3V6K
1U_0402_6.3V6K
BO BU AN32 VDDIO_MEM_S3_34 VDDCR_52 AD10
1 1 1 VDDIO_MEM_S3_35 VDDCR_53 1 1 1 1 1 1 1 1 1
AP28 AD13

CC88

CC89

CC90

CC91

CC93

CC95

CC96

CC97

CC98
CC84

CC85

CC86
C +3VALW_APU AR32 VDDIO_MEM_S3_36 VDDCR_54 AD15 C
@ @ VDDIO_MEM_S3_37 VDDCR_55 AD17 @ @ @ @ @
1A
1U_0402_6.3V6K

1U_0402_6.3V6K

2 2 2 AC21 VDDCR_56 AD19 2 2 2 2 2 2 2 2 2

1 1 VDDIO_VPH_1 VDDCR_57
1 AD21 AE8
CC100

CC101

BO BU VDDIO_VPH_2 VDDCR_58 AE14

0.2A
CC99

VDDCR_59

om
@ AP9 AE16
2 2 VDDIO_AUDIO VDDCR_60 AE18
2 0.25A VDDCR_61
22UC_6.3VC_MC_X5RC_0603

AL18 AF7
BO BU AM17 VDD_33_1 VDDCR_62 AF10
VDD_33_2 VDDCR_63 AF13
+0.75VALW 2.5A AL20 VDDCR_64 AF15
ALL BU(on bottom side under SOC)
AM19 VDD_18_1 VDDCR_65 AF17
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

VDD_18_2 VDDCR_66

.c
AF19
1
1 1 1 1A AL19 VDDCR_67 AG14
CC103

CC104

CC105

AM18 VDD_18_S5_1 VDDCR_68 AG16

CC102

@ VDD_18_S5_2 VDDCR_69 AG18

2 2 2 0.25A AL17 VDDCR_70 AH13 +1.2V

ix
2 AM16 VDD_33_S5_1 VDDCR_71 AH15
VDD_33_S5_2 VDDCR_72 AH17
2A VDDCR_73
22UC_6.3VC_MC_X5RC_0603

BO
22UC_6.3VC_MC_X5RC_0603

BU AL11 AH19
+0.75VS VDDP_S5_1 VDDCR_74

af
AL12 AJ7
AM12 VDDP_S5_2 VDDCR_75 AJ10

180P_50V_J_NPO_0402

180P_50V_J_NPO_0402
180P_50V_J_NPO_0402

VDDP_S5_3 VDDCR_76 AJ14

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K
2A
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

M15 VDDCR_77 AJ16

1 1 1 1 1 1 1 1 1 1 1 VDDP_1 VDDCR_78 1 1 1 1 1 1
M16 AJ18

CC117

CC118

CC119

CC120

CC121

CC122
in
CC106

CC107

CC108

CC109

CC110

CC111

CC112

CC113

CC114

CC115

CC116

M18 VDDP_2 VDDCR_79 AK13

VDDP_3 VDDCR_80 AK15 @
2 2 2 2 2 2 2 2 2 2 2 VDDCR_81 AK17 2 2 2 2 2 2
VDDCR_82 AK19

//v
AJ11 VDDCR_83
BO(Bottom side outside SOC) BU VDDBT_RTC_G FP6 REV0.92
PART 6/13
JCMOS1
@ AMD-RENOIR-FP6_BGA1140
Decoupling between processor and DIMMs
VCCRTC +RTCBATT_APU Across vddio and vss split

s:
@
1

1 2
RC128 1K_0402_5%
0.22U_0201_6.3V6-K

tp
+1.2V
1U_0402_6.3V6K

1 1
CC123

CC124

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
2 2
ht

0.22U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K
B 1 1 1 1 1 1 B
1

CC125

CC127

CC128

CC129

CC133

CC134
RC130
470_0603_5%
@ 2 2 2 2 2 2
12

D QC4
2 EC_RTCRST#_ON
EC_RTCRST#_ON 31
G @ @ @ @ @ @
2

S L2N7002KWT1G_SOT323-3 RC131
3

@ 10K_0402_5%
@
Reserved for debug
1

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/15 Deciphered Date 2013/08/15 FP6 POWER

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S350 ARE
Date: Sunday, January 19, 2020 Sheet 11 of 45
5 4 3 2 1
 5 4 3 2 1

D D

UC1K UC1L UC1M

AM20 K28 AR14 BD19 V5 AE13

A3 VSS_310 VSS_60 K32 AR16 VSS_246 VSS_305 BD21 V8 VSS_122 VSS_184 AE15
A5 VSS_1 VSS_61 L5 AR19 VSS_247 VSS_306 BD23 V11 VSS_123 VSS_185 AE17
A7 VSS_2 VSS_62 L13 AR21 VSS_248 VSS_307 BD26 V14 VSS_124 VSS_186 AE19
A10 VSS_3 VSS_63 L15 AR26 VSS_249 VSS_308 BD30 V16 VSS_125 VSS_187 AF1
A12 VSS_4 VSS_64 L18 AR28 VSS_250 VSS_309 V18 VSS_126 VSS_188 AF3
A14 VSS_5 VSS_65 L20 AT23 VSS_251 V20 VSS_127 VSS_189 AF5
A16 VSS_6 VSS_66 L25 AU5 VSS_252 V22 VSS_128 VSS_190 AF14
A19 VSS_7 VSS_67 L28 AU8 VSS_253 V25 VSS_129 VSS_191 AF16
A21 VSS_8 VSS_68 M1 AU11 VSS_254 V28 VSS_130 VSS_192 AF18
A23 VSS_9 VSS_69 M3 AU13 VSS_255 W5 VSS_131 VSS_193 AF20
A26 VSS_10 VSS_70 M5 AU15 VSS_256 W13 VSS_132 VSS_194 AG5
A30 VSS_11 VSS_71 M21 AU18 VSS_257 AV8 W15 VSS_133 VSS_195 AG8
C3 VSS_12 VSS_72 M23 AU20 VSS_258 RSVD_46 BD18 W17 VSS_134 VSS_196 AG11
C10 VSS_13 VSS_73 M26 AU22 VSS_259 RSVD_47 AV3 W19 VSS_135 VSS_197 AG13
C32 VSS_14 VSS_74 M28 AU25 VSS_260 RSVD_45 AU6 W23 VSS_136 VSS_198 AG15
E7 VSS_15 VSS_75 M32 AU28 VSS_261 RSVD_44 AR6 W26 VSS_137 VSS_199 AG17
E8 VSS_16 VSS_76 N5 AV1 VSS_262 RSVD_43 AR3 W28 VSS_138 VSS_200 AG19
E10 VSS_17 VSS_77 N8 AV5 VSS_263 RSVD_42 AP1 W32 VSS_139 VSS_201 AH14
E11 VSS_18 VSS_78 N11 AV7 VSS_264 RSVD_41 AN16 Y1 VSS_140 VSS_202 AH16
E12 VSS_19 VSS_79 N13 AV10 VSS_265 RSVD_40 AN4 Y3 VSS_141 VSS_203 AH18
E13 VSS_20 VSS_80 N15 AV12 VSS_266 RSVD_39 AN2 Y5 VSS_142 VSS_204 AH20
E14 VSS_21 VSS_81 N17 AV14 VSS_267 RSVD_38 AM14 Y11 VSS_143 VSS_205 AJ1
C C
E15 VSS_22 VSS_82 N22 AV16 VSS_268 RSVD_37 AM13 Y14 VSS_144 VSS_206 AJ3
E16 VSS_23 VSS_83 N25 AV19 VSS_269 RSVD_36 AL29 Y16 VSS_145 VSS_207 AJ5
E18 VSS_24 VSS_84 N28 AV21 VSS_270 RSVD_35 AL15 Y18 VSS_146 VSS_208 AJ13

om
E19 VSS_25 VSS_85 P1 AV23 VSS_271 RSVD_34 AL14 Y20 VSS_147 VSS_209 AJ15
E20 VSS_26 VSS_86 P5 AV26 VSS_272 RSVD_33 AL13 Y22 VSS_148 VSS_210 AJ17
E21 VSS_27 VSS_87 P14 AV28 VSS_273 RSVD_32 AK3 Y25 VSS_149 VSS_211 AJ19
E22 VSS_28 VSS_88 P16 AV32 VSS_274 RSVD_31 AJ29 Y28 VSS_150 VSS_212 AK5
E23 VSS_29 VSS_89 P18 AW5 VSS_275 RSVD_30 AJ27 AA5 VSS_151 VSS_213 AK8
E25 VSS_30 VSS_90 P20 AW28 VSS_276 RSVD_29 AF6 AA13 VSS_152 VSS_214 AK11
VSS_31 VSS_91 VSS_277 RSVD_28 VSS_153 VSS_215

.c
E26 P23 AY6 AE12 AA15 AK14
E27 VSS_32 VSS_92 P26 AY7 VSS_278 RSVD_27 AD6 AA17 VSS_154 VSS_216 AK16
F5 VSS_33 VSS_93 P28 AY8 VSS_279 RSVD_26 AD3 AA19 VSS_155 VSS_217 AK18
F19 VSS_34 VSS_94 P32 AY10 VSS_280 RSVD_25 AC30 AA23 VSS_156 VSS_218 AK20

ix
F21 VSS_35 VSS_95 R5 AY11 VSS_281 RSVD_24 AC12 AA26 VSS_157 VSS_219 AL1
F23 VSS_36 VSS_96 R11 AY12 VSS_282 RSVD_23 AB31 AA28 VSS_158 VSS_220 AL5
F28 VSS_37 VSS_97 R13 AY13 VSS_283 RSVD_22 AA20 AA32 VSS_159 VSS_221 AL7

af
G1 VSS_38 VSS_98 R15 AY14 VSS_284 RSVD_21 AA6 AB2 VSS_160 VSS_222 AL10
G3 VSS_39 VSS_99 R17 AY15 VSS_285 RSVD_20 Y12 AB4 VSS_161 VSS_223 AL16
G5 VSS_40 VSS_100 R19 AY16 VSS_286 RSVD_19 W6 AB14 VSS_162 VSS_224 AM5
VSS_41 VSS_101 VSS_287 RSVD_18 VSS_163 VSS_225

in
G16 R22 AY18 V12 AB16 AM8
G26 VSS_42 VSS_102 R25 AY19 VSS_288 RSVD_17 R12 AB18 VSS_164 VSS_226 AM11
G28 VSS_43 VSS_103 R28 AY20 VSS_289 RSVD_16 N19 AB20 VSS_165 VSS_227 AM15
G32 VSS_44 VSS_104 T1 AY21 VSS_290 RSVD_15 N12 AC5 VSS_166 VSS_228 AN1

//v
H5 VSS_45 VSS_105 T3 AY22 VSS_291 RSVD_14 N10 AC8 VSS_167 VSS_229 AN5
H13 VSS_46 VSS_106 T5 AY23 VSS_292 RSVD_13 N9 AC11 VSS_168 VSS_230 AN7
H18 VSS_47 VSS_107 T14 AY25 VSS_293 RSVD_12 M13 AC13 VSS_169 VSS_231 AN10
H20 VSS_48 VSS_108 T16 AY26 VSS_294 RSVD_11 M12 AC15 VSS_170 VSS_232 AN23
VSS_49 VSS_109 VSS_295 RSVD_10 VSS_171 VSS_233

s:
H22 T18 AY27 M11 AC17 AN26
H25 VSS_50 VSS_110 T20 BB1 VSS_296 RSVD_9 M6 AC19 VSS_172 VSS_234 AP5
H28 VSS_51 VSS_111 T23 BB32 VSS_297 RSVD_8 L12 AC22 VSS_173 VSS_235 AP8
J19 VSS_52 VSS_112 T26 BD3 VSS_298 RSVD_7 K19 AC25 VSS_174 VSS_236 AP13

tp
K1 VSS_53 VSS_113 T28 BD7 VSS_299 RSVD_6 F16 AD1 VSS_175 VSS_237 AP15
K3 VSS_54 VSS_114 T32 BD10 VSS_300 RSVD_5 F14 AD5 VSS_176 VSS_238 AP18
K5 VSS_55 VSS_115 U13 BD12 VSS_301 RSVD_4 F12 AD14 VSS_177 VSS_239 AP20
K16 VSS_56 VSS_116 U15
htBD14 VSS_302 RSVD_3 F10 AD16 VSS_178 VSS_240 AP25
K21 VSS_57 VSS_117 U17 BD16 VSS_303 RSVD_2 C26 AD18 VSS_179 VSS_241 AR1
K26 VSS_58 VSS_118 U19 VSS_304 RSVD_1 AD20 VSS_180 VSS_242 AR5
B VSS_59 VSS_119 V2 AE5 VSS_181 VSS_243 AR7 B
VSS_120 V4 FP6 REV0.92 AE11 VSS_182 VSS_244 AR12
FP6 REV0.92 VSS_121 PART 11/13 VSS_183 VSS_245
PART 7/13 FP6 REV0.92
AMD-RENOIR-FP6_BGA1140 AMD-RENOIR-FP6_BGA1140 PART 8/13
@ @ AMD-RENOIR-FP6_BGA1140
@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/15 Deciphered Date 2013/08/15 FP6 GND

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
S350 ARE 1.0

Date: Sunday, January 19, 2020 Sheet 12 of 45

5 4 3 2 1
 5 4 3 2 1

+1.8VS +1.8VALW +3VALW_APU

1
RC132 RC133 RC134
10K_0402_5% 10K_0402_5% 10K_0402_5%
@

2
D D
PCH_SPI_CLK_R
8 PCH_SPI_CLK_R 7 SYS_RESET#

1
RC135 RC136
2K_0402_5% 2K_0402_5%
@ @

2
STRAP PINS SYS_RESET#
1:USE 48MHZ CRYSTAL CLOCK AND
GENERATE BOTH INTERNAL AND EXTERNAL CLOCKS(DEFAULT)
PCH_SPI_CLK 0:USE 100MHZ PCIE CLOCK AS REFERENCE CLOCK AND
GENERATE INTERNAL CLOCKS ONLY
C C

1:NORMAL RESET MODE(DEFAULT)

SYS_RESET#

om
0:SHORT RESET MODE

.c
ix
af
in
//v
LPC ROM EMULATOR HEADER

s:
+3VALW_APU +3VS_APU

tp
PIN4 should be removed as a Key
2

RC138 RC139

LPC@
0_0402_5% 0_0402_5%
LPC@
ht DAISY CHAIN ROUTING FOR LPC SIGNALS
1

B B

APU_LPC_RST# RC140 1 LPC@ 2 0_0402_5%

8,31 APU_LPC_RST# LPC_RST#_H 1 @ IT1 IT2 @ 1 RC141 1 @ 2 0_0402_5% PM_SLP_S5#
PM_SLP_S5# 7,31
LPCRUNPWR 1 @ IT3

RC142 1 LPC@ 2 0_0402_5% I2C3_SCL_LPC 1 @ IT5 IT4 @ 1 I2C3_SDA_LPC RC143 1 LPC@ 2 0_0402_5%
7,32 TP_I2C3_SCL_R TP_I2C3_SDA_R 7,32
1 @ IT7 IT6 @ 1 SERIRQ
SERIRQ 8,31
IT8 @ 1 LDRQ0#
LDRQ0# 8
2 2
CC142 CC143
0.1U_6.3V_K_X5R_0201 0.1U_6.3V_K_X5R_0201
LPC@ 1 1 LPC@

CC142 CC143 should be put on APU side to reduce stub when MP

+3VS_APU

RC144 1 @ 2 10K_0402_5% LPCPD# LPCPD# 8

RC145 1 @ 2 10K_0402_5% LPC_CLKRUN#

LPC_CLKRUN# 8

+3VALW_APU
A A

RC323 1 LPC@ 2 10K_0402_5% LPCPD#

RC146 1 2 100K_0402_5% APU_LPC_RST#

CC138 1 @ 2 150P_0402_50V8-J

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/15 Deciphered Date 2013/08/15 FP6 Straps

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document
Size DocumentNumber
Number Rev
Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
S350 ARE AMD UMA 1.0

Date:
Date: Sunday, January 19, 2020 Sheet
Sheet 13 of 45
5 4 3 2 1
 5 4 3 2 1

DDR_A_D[0..63]
DDR_A_D[0..63] 5
DDR_A_DQS[0..7]
DDR_A_DQS[0..7] 5
DDR_A_DQS#[0..7]
DDR_A_DQS#[0..7] 5
DDR_A_MA[0..13]
+1.2V +1.2V DDR_A_MA[0..13] 5
update JDDR1 symbol 1129 DDRA_MA_DM[0..7]
DDRA_MA_DM[0..7] 5
JDDR1A JDDR1B
Swap Table
1 2 DDR_A_MA3 131 132 DDR_A_MA2
DDR_A_D14 3 VSS_1 VSS_2 4 DDR_A_D12 DDR_A_MA1 133 A3 A2 134 DDR_A_EVENT#
DQ5 DQ4 A1 EVENT_n DDR_A_EVENT# 5 Pin Name Net Name
5 6 135 136
DDR_A_D13 7 VSS_3 VSS_4 8 DDR_A_D9 SA_CLK_DDR0 137 VDD_9 VDD_10 138 SA_CLK_DDR1
DQ1 DQ0 5 SA_CLK_DDR0 CK0_t CK1_t SA_CLK_DDR1 5 DQ0 DDRA_DQ6
9 10 SA_CLK_DDR#0 139 140 SA_CLK_DDR#1
D
DDR_A_DQS#1 VSS_5 VSS_6 DDRA_MA_DM1 5 SA_CLK_DDR#0 CK0_c CK1_c SA_CLK_DDR#1 5 DQ1 DDRA_DQ5 D
11 12 141 142
DDR_A_DQS1 13 DQS0_C DM0_n/DBIO_n/NC 14 DDR_A_PARITY 143 VDD_11 VDD_12 144 DDR_A_MA0 DQ2 DDRA_DQ2
DQS0_t VSS_7 DDR_A_D8 5 DDR_A_PARITY Parity A0 DQ3 DDRA_DQ3
15 16
DDR_A_D11 17 VSS_8 DQ6 18 DQ4 DDRA_DQ4
19 DQ7 VSS_9 20 DDR_A_D10 DDR_A_BA1 145 146 DDR_A_MA10 DQ5 DDRA_DQ0
DDR_A_D15 VSS_10 DQ2 5 DDR_A_BA1 BA1 A10/AP
21 22 147 148 DQ6 DDRA_DQ1
23 DQ3 VSS_11 24 DDR_A_D2 DDR_A_CS0# 149 VDD_13 VDD_14 150 DDR_A_BA0
DDR_A_D0 25 VSS_12 DQ12 26 5 DDR_A_CS0# DDR_A_WE# 151 CS0_n BA0 152 DDR_A_RAS# DDR_A_BA0 5 DQ7 DDRA_DQ7
27 DQ13 VSS_13 28 DDR_A_D4 5 DDR_A_WE#
153 WE_n/A14 RAS_n/A16 154 DDR_A_RAS# 5 DQS#0 DDRA_DQS#0
DDR_A_D5 29 VSS_14 DQ8 30 DDR_A_ODT0 155 VDD_15 VDD_16 156 DDR_A_CAS# DQS0 DDRA_DQS0
31 DQ9 VSS_15 32 DDR_A_DQS#0 5 DDR_A_ODT0 DDR_A_CS1# 157 ODT0 CAS_n/A15 158 DDR_A_MA13 DDR_A_CAS# 5
DDRA_MA_DM0 VSS_16 DQS1_c DDR_A_DQS0 5 DDR_A_CS1# CS1_n A13
33 34 159 160 DQ8 DDRA_DQ13
35 DM1_n/DBl1_n/NC DQS1_t 36 DDR_A_ODT1 161 VDD_17 VDD_18 162 +VREF_CA
DDR_A_D3 VSS_17 VSS_18 DDR_A_D1 5 DDR_A_ODT1 ODT1 C0/CS2_n/NC DQ9 DDRA_DQ9
37 38 163 164
39 DQ15 DQ14 40 165 VDD_19 VREFCA 166 DDRA0_SA2 DQ10 DDRA_DQ14
DDR_A_D7 41 VSS_19 VSS_20 42 DDR_A_D6 167 C1/CS3_n/NC SA2 168 DQ11 DDRA_DQ10
43 DQ10 DQ11 44 DDR_A_D33 169 VSS_53 VSS_54 170 DDR_A_D37 DQ12 DDRA_DQ12
DDR_A_D16 45 VSS_21 VSS_22 46 DDR_A_D21 171 DQ37 DQ36 172 DQ13 DDRA_DQ8
47 DQ21 DQ20 48 DDR_A_D32 173 VSS_55 VSS_56 174 DDR_A_D36
VSS_23 VSS_24 DQ33 DQ32 DQ14 DDRA_DQ15
DDR_A_D20 49 50 DDR_A_D17 175 176
51 DQ17 DQ16 52 DDR_A_DQS#4 177 VSS_57 VSS_58 178 DDRA_MA_DM4 DQ15 DDRA_DQ11
DDR_A_DQS#2 53 VSS_25 VSS_26 54 DDRA_MA_DM2 DDR_A_DQS4 179 DQS4_c DM4_n/DBl4_n/NC 180 DQS#1 DDRA_DQS#1
DDR_A_DQS2 55 DQS2_c DM2_n/DBl2_n/NC 56 181 DQS4_t VSS_59 182 DDR_A_D38 DQS1 DDRA_DQS1
57 DQS2_t VSS_27 58 DDR_A_D18 DDR_A_D35 183 VSS_60 DQ39 184
DDR_A_D19 59 VSS_28 DQ22 60 185 DQ38 VSS_61 186 DDR_A_D39
DQ23 VSS_29 VSS_62 DQ35
DQ16 DDRA_DQ20
61 62 DDR_A_D22 DDR_A_D34 187 188
DDR_A_D23 VSS_30 DQ18 DQ34 VSS_63 DDR_A_D45
DQ17 DDRA_DQ21
63 64 189 190
65 DQ19 VSS_31 66 DDR_A_D28 DDR_A_D40 191 VSS_64 DQ45 192 DQ18 DDRA_DQ22
DDR_A_D29 67 VSS_32 DQ28 68 193 DQ44 VSS_65 194 DDR_A_D44 DQ19 DDRA_DQ19
69 DQ29 VSS_33 70 DDR_A_D24 DDR_A_D41 195 VSS_66 DQ41 196 DQ20 DDRA_DQ16
DDR_A_D25 71 VSS_34 DQ24 72 197 DQ40 VSS_67 198 DDR_A_DQS#5 DQ21 DDRA_DQ17
73 DQ25 VSS_35 74 DDR_A_DQS#3 DDRA_MA_DM5 199 VSS_68 DQS5_c 200 DDR_A_DQS5
VSS_36 DQS3_c DM5_n/DBl5_n/NC DQS5_t DQ22 DDRA_DQ23
DDRA_MA_DM3 75 76 DDR_A_DQS3 201 202
77 DM3_n/DBl3_n/NC DQS3_t 78 DDR_A_D42 203 VSS_69 VSS_70 204 DDR_A_D47 DQ23 DDRA_DQ18
DDR_A_D31 79 VSS_37 VSS_38 80 DDR_A_D26 205 DQ46 DQ47 206 DQS#2 DDRA_DQS#2
81 DQ30 DQ31 82 DDR_A_D43 207 VSS_71 VSS_72 208 DDR_A_D46 DQS2 DDRA_DQS2
DDR_A_D30 83 VSS_39 VSS_40 84 DDR_A_D27 209 DQ42 DQ43 210
C DQ26 DQ27 VSS_73 VSS_74 C
85 86 DDR_A_D48 211 212 DDR_A_D53 DQ24 DDRA_DQ28
87 VSS_41 VSS_42 88 213 DQ52 DQ53 214
CB5/NC CB4/NC DDR_A_D49 VSS_75 VSS_76 DDR_A_D52
DQ25 DDRA_DQ29
89 90 215 216
DQ26 DDRA_DQ31

om
+1.2V +1.2V 91 VSS_43 VSS_44 92 +1.2V 217 DQ49 DQ48 218
93 CB1/NC CB0/NC 94 DDR_A_DQS#6 219 VSS_77 VSS_78 220 DDRA_MA_DM6 DQ27 DDRA_DQ27
RD273 1 @ 2 240_0402_1% 95 VSS_45 VSS_46 96 DDR_A_DQS6 221 DQS6_c DM6_n/DBl6_n/NC 222 DQ28 DDRA_DQ24
RD274 1 @ 2 240_0402_1% 97 DQS8_c DM8_n/DBI8_n/NC 98 223 DQS6_t VSS_79 224 DDR_A_D54 DQ29 DDRA_DQ25
99 DQS8_t VSS_47 100 DDR_A_D50 225 VSS_80 DQ54 226
VSS_48 CB6/NC DQ55 VSS_81 DQ30 DDRA_DQ30
101 102 227 228 DDR_A_D55
for MEM_MB_RST# overshoot issue DQ31 DDRA_DQ26

.c
103 CB2/NC VSS_49 104 DDR_A_D51 229 VSS_82 DQ50 230
105 VSS_50 CB7/NC 106 231 DQ51 VSS_83 232 DDR_A_D57 DQS#3 DDRA_DQS#3
107 CB3/NC VSS_51 108 DDR4_A_DRAMRST#_R DDR_A_D61 233 VSS_84 DQ60 234 DQS3 DDRA_DQS3
VSS_52 RESET_n DQ61 VSS_85

ix
DDR_A_CKE0 109 110 DDR_A_CKE1 235 236 DDR_A_D60
5 DDR_A_CKE0 CKE0 CKE1 DDR_A_CKE1 5 DDR_A_D56 VSS_86 DQ57
111 112 237 238 DQ32 DDRA_DQ33

0.1U_0201_6.3V6-K
DDR_A_BG1 113 VDD_1 VDD_2 114 DDR_A_ACT_N 239 DQ56 VSS_87 240 DDR_A_DQS#7
5 DDR_A_BG1 DDR_A_BG0 BG1 ACT_n DDR_A_ALERT_N DDR_A_ACT_N 5 1
DDRA_MA_DM7 VSS_88 DQS7_c DDR_A_DQS7
DQ33 DDRA_DQ37

af
115 116 241 242
5 DDR_A_BG0
117 BG0 ALERT_n 118
DDR_A_ALERT_N 5
243 DM7_n/DBl7_n/NC DQS7_t 244 DQ34 DDRA_DQ34
DDR_A_MA12 119 VDD_3 VDD_4 120 DDR_A_MA11 DDR_A_D63 245 VSS_89 VSS_90 246 DDR_A_D59 DQ35 DDRA_DQ38
CD120
DDR_A_MA9 121 A12 A11 122 DDR_A_MA7 2 247 DQ62 DQ63 248 DQ36 DDRA_DQ32

in
123 A9 A7 124 @ DDR_A_D58 249 VSS_91 VSS_92 250 DDR_A_D62 DQ37 DDRA_DQ36
DDR_A_MA8 125 VDD_5 VDD_6 126 DDR_A_MA5 251 DQ58 DQ59 252
A8 A5 +VDDSPD VSS_93 VSS_94 DQ38 DDRA_DQ35
DDR_A_MA6 127 128 DDR_A_MA4 APU_SMB_CLK 253 254 APU_SMB_DATA
A6 A4 7 APU_SMB_CLK SCL SDA APU_SMB_DATA 7 DQ39 DDRA_DQ39

//v
129 130 255 256 DDRA0_SA0
VDD_7 VDD_8 257 VDDSPD SA0 258 DQS#4 DDRA_DQS#4
+2.5V VPP_1 VTT DDRA0_SA1 +0.6VS DQS4 DDRA_DQS4
1 1 259 260
CD28 CD29 VPP_2 SA1
1
ARGOS_D4AR0-26001-1P40 1U_0402_6.3V6K 0.1U_0201_6.3V6-K CD121 261 262 DQ40 DDRA_DQ44

s:
22P_0402_50V8-J GND_1 GND_2
ME@
2 2 ARGOS_D4AR0-26001-1P40
DQ41 DDRA_DQ40
RF RF_NS@
2 DQ42 DDRA_DQ47
ME@
DQ43 DDRA_DQ43

tp
5 DDR4_A_DRAMRST#
DDR4_A_DRAMRST# RD288 1 @ 2 0_0402_5% DDR4_A_DRAMRST#_R DQ44 DDRA_DQ41
DQ45 DDRA_DQ45
+3VS +VDDSPD
ht DQ46 DDRA_DQ46
DQ47 DDRA_DQ42
RD271 1 @ 2 0_0402_5%
+2.5VS DQS#5 DDRA_DQS#5
B B
+1.2V DQS5 DDRA_DQS5
+1.2V RD272 1 @ 2 0_0402_5%
+2.5V +2.5VS DQ48 DDRA_DQ48
1

DQ49 DDRA_DQ49
1

RD10 3 1

D
RD258 +VREF_CA QD1
DQ50 DDRA_DQ55
1K_0402_1%
1K_0402_1% LP2301ALT1G_SOT23-3 DQ51 DDRA_DQ50
DQ52 DDRA_DQ52
15mil Layout Note: Place near JDDR1

G
2

2
@
@
DQ53 DDRA_DQ53
2

DQ54 DDRA_DQ54
1000P 25V K X7R 0201
0.1U_0201_6.3V6-K
1

DDR_A_ALERT_N
DQ55 DDRA_DQ51
1U_0402_6.3V6K

19,33 SUSP
RD11 1 1 1
1K_0402_1% +0.6VS +1.2V DQS#6 DDRA_DQS#6
DQS6 DDRA_DQS6
follow CRB 1pcs 4.7uf + 1pcs 0.1uf follow CRB 6pcs 0.1uf
CD262

CD116

CD117
2

2 2 2 DQ56 DDRA_DQ60

180P_50V_J_NPO_0402
0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

27P 25V J NPO 0201

0.1U_0201_6.3V6-K

27P 25V J NPO 0201

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K
DQ57 DDRA_DQ56
0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

4.7U_0402_6.3V6M

1 1 1 1 1 1 1 1 1 1 1 1 1 DQ58 DDRA_DQ63
1 1 1 1 CD16 CD17 CD18 CD20 CD21 CD22 CD23 CD58 CD59 CD60 CD61 CD62 CC211
CD249 CD251 CD250 CD248 @ EMC_NS@ @ EMC_NS@ @ @ DQ59 DDRA_DQ59
@ @ DQ60 DDRA_DQ61
2 2 2 2 2 2 2 2 2 2 2 2 2 DQ61 DDRA_DQ57
2 2 2 2
DQ62 DDRA_DQ58
DQ63 DDRA_DQ62
+3VS +3VS +3VS DQS#7 DDRA_DQS#7
DQS7 DDRA_DQS7
1

RD26 RD269 RD270 +2.5V +1.2V

10K_0402_5% 10K_0402_5% 10K_0402_5% follow CRB 1pcs 1uf + 2pcs 0.1uf + 1pcs 180pf
22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

@ @ @
2

DDRA0_SA0 DDRA0_SA1 DDRA0_SA2

180P_50V_J_NPO_0402

10U_0603_6.3V6M

10U_0603_6.3V6M
1U_0402_6.3V6K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

1 1 1 1 1 1 1 1 1
1

1 1 1 1 CD261 CD63 CD66 CD67 CD19 CD260 CD12 CD348 CD349

A RD268 RD28 RD29 CD122 CD123 CD124 CC206 @ @ 22P_0402_50V8-J 22P_0402_50V8-J 22P_0402_50V8-J 22P_0402_50V8-J 22P_0402_50V8-J A
0_0402_5% 0_0402_5% 0_0402_5% RF_NS@ RF_NS@ RF_NS@ RF_NS@ RF_NS@
2 2 2 2 2 2 2 2 2
2 2 2 2
RF
2

@ @ @

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/15 Deciphered Date 2013/08/15 DDRIV SO-DIMM A
SPD Address = A0H THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document
Document Number
Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
S350 ARE 1.0

Date:
Date: Sunday, January 19, 2020 Sheet
Sheet 14 of 44
5 4 3 2 1
 5 4 3 2 1

DDR_B_D[0..63]
DDR_B_D[0..63] 5
DDP@ DDR_B_DQS[0..7]
DRAM_DDRB_BG1 DDR_B_BG1 DDR_B_DQS[0..7] 5
RD238 2 1 0_0201_5%
DDR_B_BG1 5 DDR_B_DQS#[0..7]
DDR_B_DQS#[0..7] 5
UD1 UD2
DDR_B_MA[0..13]
DDR_B_MA[0..13] 5

1
DDR_B_MA0 P3 G2 DDR_B_D3 DDR_B_MA0 P3 G2 DDR_B_D18
DDR_B_MA1 P7 A0 DQL0 F7 DDR_B_D7 DDR_B_MA1 P7 A0 DQL0 F7 DDR_B_D16 RD234 DDRA_MB_DM[0..7]
DDR_B_MA2 A1 DQL1 DDR_B_D6 DDR_B_MA2 A1 DQL1 DDR_B_D17 DDRA_MB_DM[0..7] 5
R3 H3 R3 H3 SDP@ 0_0201_5%
DDR_B_MA3 N7 A2 DQL2 H7 DDR_B_D0 DDR_B_MA3 N7 A2 DQL2 H7 DDR_B_D19
DDR_B_MA4 N3 A3 DQL3 H2 DDR_B_D2 DDR_B_MA4 N3 A3 DQL3 H2 DDR_B_D23
A4 DQL4 A4 DQL4

2
DDR_B_MA5 P8 H8 DDR_B_D1 DDR_B_MA5 P8 H8 DDR_B_D22
DDR_B_MA6 P2 A5 DQL5 J3 DDR_B_D5 DDR_B_MA6 P2 A5 DQL5 J3 DDR_B_D21
DDR_B_MA7 R8 A6 DQL6 J7 DDR_B_D4 DDR_B_MA7 R8 A6 DQL6 J7 DDR_B_D20
DDR_B_MA8 A7 DQL7 DDR_B_D10 DDR_B_MA8 A7 DQL7 DDR_B_D27 +1.2V
DDR_B_MA9
R2
R7 A8 DQU0
A3
B8 DDR_B_D8 DDR_B_MA9
R2
R7 A8 DQU0
A3
B8 DDR_B_D25 3/18 CD163 change from SE00000VX00 to SE102104K0J
DDR_B_MA10 M3 A9 DQU1 C3 DDR_B_D11 DDR_B_MA10 M3 A9 DQU1 C3 DDR_B_D30 DRAM@
DDR_B_MA11 T2 A10/AP DQU2 C7 DDR_B_D9 DDR_B_MA11 T2 A10/AP DQU2 C7 DDR_B_D28 UD1_DDRB_UZQ SB_CLK_DDR#0 RD122 1 DRAM@ 2 1/20W _39_+-5%_0201 CD163 1 2 0.1U_0402_10V7K
DDR_B_MA12 M7 A11 DQU3 C2 DDR_B_D14 DDR_B_MA12 M7 A11 DQU3 C2 DDR_B_D26 SB_CLK_DDR0 RD123 1 DRAM@ 2 1/20W _39_+-5%_0201
DDR_B_MA13 T8 A12/BC_N DQU4 C8 DDR_B_D15 DDR_B_MA13 T8 A12/BC_N DQU4 C8 DDR_B_D29
D D
A13 DQU5 D3 DDR_B_D13 A13 DQU5 D3 DDR_B_D31 UD2_DDRB_UZQ
DDR_B_W E# L2 DQU6 D7 DDR_B_D12 DDR_B_W E# L2 DQU6 D7 DDR_B_D24 +0.6VS
5 DDR_B_W E# DDR_B_CAS# WE_N/A14 DQU7 DDR_B_CAS# WE_N/A14 DQU7
M8 M8
5 DDR_B_CAS# DDR_B_RAS# CAS_N/A15 +1.2V DDR_B_RAS# CAS_N/A15 +1.2V UD3_DDRB_UZQ
L8 L8
5 DDR_B_RAS# RAS_N/A16 RAS_N/A16
D1 D1
SB_CLK_DDR#0 K8 VDD1 J1 SB_CLK_DDR#0 K8 VDD1 J1 DDR_B_MA0 RD148 1 DRAM@ 2 1/20W _39_+-5%_0201
5 SB_CLK_DDR#0 SB_CLK_DDR0 CK_C VDD2 SB_CLK_DDR0 CK_C VDD2 UD4_DDRB_UZQ DDR_B_MA1
5 SB_CLK_DDR0
K7 L1 K7 L1 RD149 1 DRAM@ 2 1/20W _39_+-5%_0201
CK_T VDD3 R1 CK_T VDD3 R1 DDR_B_MA2 RD124 1 DRAM@ 2 1/20W _39_+-5%_0201
DDR_B_CKE0 K2 VDD4 B3 DDR_B_CKE0 K2 VDD4 B3 DDR_B_MA3 RD125 1 DRAM@ 2 1/20W _39_+-5%_0201
5 DDR_B_CKE0 CKE VDD5 CKE VDD5 DDR_B_MA4
G7 G7 RD126 1 DRAM@ 2 1/20W _39_+-5%_0201
VDD6 VDD6

1
DDR_B_DQS#0 F3 B9 DDR_B_DQS#2 F3 B9 DDR_B_MA5 RD127 1 DRAM@ 2 1/20W _39_+-5%_0201

240_0402_1%

240_0402_1%

240_0402_1%

240_0402_1%
DDR_B_DQS0 G3 DQSL_C VDD7 J9 DDR_B_DQS2 G3 DQSL_C VDD7 J9 DDR_B_MA6 RD128 1 DRAM@ 2 1/20W _39_+-5%_0201

RD233

RD232

RD231

RD228
DDR_B_DQS#1 A7 DQSL_T VDD8 L9 DDR_B_DQS#3 A7 DQSL_T VDD8 L9 DDR_B_MA7 RD129 1 DRAM@ 2 1/20W _39_+-5%_0201
DDR_B_DQS1 B7 DQSU_C VDD9 T9 DDR_B_DQS3 B7 DQSU_C VDD9 T9 DDR_B_MA8 RD130 1 DRAM@ 2 1/20W _39_+-5%_0201
DQSU_T VDD10 DQSU_T VDD10 DDR_B_MA9 RD131 1 DRAM@ 2 1/20W _39_+-5%_0201

2
DDRA_MB_DM1 E2 A1 DDRA_MB_DM3 E2 A1 DDR_B_MA10 RD132 1 DRAM@ 2 1/20W _39_+-5%_0201
DDRA_MB_DM0 E7 NF/UDM_N/UDBI_N VDDQ1 C1 DDRA_MB_DM2 E7 NF/UDM_N/UDBI_N VDDQ1 C1 DDR_B_MA11 RD133 1 DRAM@ 2 1/20W _39_+-5%_0201
NF/LDM_N/LDBI_N VDDQ2 G1 NF/LDM_N/LDBI_N VDDQ2 G1 @ @ @ @ DDR_B_MA12 RD134 1 DRAM@ 2 1/20W _39_+-5%_0201
DDR_B_BA0 N2 VDDQ3 F2 DDR_B_BA0 N2 VDDQ3 F2 DDR_B_MA13 RD135 1 DRAM@ 2 1/20W _39_+-5%_0201
5 DDR_B_BA0 DDR_B_BA1 BA0 VDDQ4 DDR_B_BA1 BA0 VDDQ4
RF 5 DDR_B_BA1 N8
BA1 VDDQ5
J2 N8
BA1 VDDQ5
J2
DDR_B_W E#
F8 F8 RD138 1 DRAM@ 2 1/20W _39_+-5%_0201
DDR_B_ACT_N L3 VDDQ6 J8 DDR_B_ACT_N L3 VDDQ6 J8 DDR_B_CAS# RD139 1 DRAM@ 2 1/20W _39_+-5%_0201
5 DDR_B_ACT_N DDR_B_CS0# ACT_N VDDQ7 DDR_B_CS0# ACT_N VDDQ7 DDR_B_RAS#
L7 A9 L7 A9 RD140 1 DRAM@ 2 1/20W _39_+-5%_0201
5 DDR_B_CS0# DDR_B_ALERT_N CS_N VDDQ8 DDR_B_ALERT_N CS_N VDDQ8
P9 D9 P9 D9
5 DDR_B_ALERT_N ALERT_N VDDQ9 G9 +2.5V ALERT_N VDDQ9 G9 +2.5V RD233 RD232 RD231 RD228 will install different DDR_B_ACT_N RD144 1 DRAM@ 2 1/20W _39_+-5%_0201
5 DDR_B_BG0
DDR_B_BG0 M2
BG0
VDDQ10 DDR_B_BG0 M2
BG0
VDDQ10 value base on SDP or DDP.control by Virtual symbol Swap Table
B1 B1 DDR_B_ODT0 RD147 1 DRAM@ 2 1/20W _39_+-5%_0201
DDR_B_ODT0 K3 VPP1 R9 DDR_B_ODT0 K3 VPP1 R9 DDR_B_CS0# 1 DRAM@ 2
5 DDR_B_ODT0 ODT VPP2 ODT VPP2 DDR_B_CKE0
RD145 1/20W _39_+-5%_0201 Pin Name Net Name
+VREF_CA_MD +VREF_CA_MD RD141 1 DRAM@ 2 1/20W _39_+-5%_0201
DDR_B_PARITY T3 M1 DDR_B_PARITY T3 M1 DQ0 DDRB_DQ3
5 DDR_B_PARITY PAR VREFCA PAR VREFCA +1.2V

1U_0402_6.3V6K

1U_0402_6.3V6K
DRAM_DDRB_BG1 1 DDP@ 2

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K
1 1 1 1 RD229 1/20W _39_+-5%_0201 DQ1 DDRB_DQ6
10K_0402_5%1 DRAM@ 2 RD251 TEN1 N9 E1 10K_0402_5% 1 DRAM@ 2 RD253 TEN2 N9 E1
DQ2 DDRB_DQ2

CD202

CD203

CD232

CD233
TEN VSS1 K1 TEN VSS1 K1

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K
1000P 25V K X7R 0201

1000P 25V K X7R 0201

VSS2 1 1 VSS2 1 1 DQ3 DDRB_DQ0

1
DDR4_B_DRAMRST#_R P1 N1 DDR4_B_DRAMRST#_R P1 N1 DDR_B_BA0 RD142 1 DRAM@ 2 1/20W _39_+-5%_0201

CD189

CD188

CD230

CD231
RESET_N VSS3 T1 DRAM@ 2 2
DRAM@ RESET_N VSS3 T1 DRAM@2 2 RD276 DDR_B_BA1 RD143 1 DRAM@ 2 1/20W _39_+-5%_0201 DQ4 DDRB_DQ7
F1 VSS4 B2 F1 VSS4 B2 +VREF_CA_MD DQ5 DDRB_DQ5
0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K
DRAM@ 1K_0402_1%
H1 VSSQ1 VSS5 G8 2 DRAM@2 H1 VSSQ1 VSS5 G8 2 2
1 VSSQ2 VSS6
DRAM@ 1 VSSQ2 VSS6
DRAM@ DRAM@ DQ6 DDRB_DQ4
A2 K9 A2 K9 DRAM@
15mil DQ7 DDRB_DQ1
CD132

CD160
VSSQ3 VSS8 VSSQ3 VSS8

2
D2 R10170 D2 R10171 DDR_B_BG0 RD146 1 DRAM@ 2 1/20W _39_+-5%_0201
E3 VSSQ4 T7 1 2 E3 VSSQ4 T7 1 2 DDR_B_PARITY RD275 1 DRAM@ 2 1/20W _39_+-5%_0201
DQS#0 DDRB_DQS#0
2 VSSQ5 VSS7 2 VSSQ5 VSS7 DQS0 DDRB_DQS0

1
A8 A8

0.1U_0201_6.3V6-K
@ DDP@ 0_0402_5% @ DDP@ 0_0402_5%
UD1

1000P 25V K X7R 0201

VSSQ6 VSSQ6

1U_0402_6.3V6K
D8 D8 RD277 1 1 1
E8 VSSQ7 M9 DRAM_DDRB_BG1 E8 VSSQ7 M9 DRAM_DDRB_BG1 1K_0402_1% DQ8 DDRB_DQ9

DRAM@

DRAM@

DRAM@
C9 VSSQ8 VSS9 C9 VSSQ8 VSS9 DRAM@ +1.2V
DQ9 DDRB_DQ11

CD357

CD358

CD359
C
H9 VSSQ9 E9 UD1_DDRB_UZQ H9 VSSQ9 E9 UD2_DDRB_UZQ C
VSSQ10 VSS10 VSSQ10 VSS10 DQ10 DDRB_DQ12

2
F9 F9 2 2 2
ZQ ZQ DDR_B_ALERT_N RD86 1 DRAM@ 2 1/20W _1K_1%_0201 DQ11 DDRB_DQ8
DQ12 DDRB_DQ15
1

1
RD116 RD117 DQ13 DDRB_DQ13
K4AAG165W A-BCW E_FBGA96 240_0402_1% K4AAG165W A-BCW E_FBGA96 240_0402_1% DQ14 DDRB_DQ14
Layout Note: Place near DRAM
DRAM@ DRAM@ DQ15 DDRB_DQ10
@ @
DQS#1 DDRB_DQS#1
2

2
[email protected] DQS1 DDRB_DQS1
+1.2V
+1.2V
UD1
DQ16 DDRB_DQ7
DQ17 DDRB_DQ3
follow SCL 20pcs 0.22uf DQ18 DDRB_DQ4
DQ19 DDRB_DQ0
DQ20 DDRB_DQ6

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K
CD266 1 CD267 1 CD268 1 CD269 1 CD270 1 CD271 1 CD272 1 CD273 1 CD274 1 CD275 1 CD276 1 CD277 1
DQ21 DDRB_DQ5

47P_0201_25V8-J

27P 25V J NPO 0201

27P 25V J NPO 0201

27P 25V J NPO 0201

27P 25V J NPO 0201

27P 25V J NPO 0201

27P 25V J NPO 0201

47P_0201_25V8-J

27P 25V J NPO 0201

47P_0201_25V8-J

47P_0201_25V8-J

27P 25V J NPO 0201

1 1 1 1 1 1 1 1 1 1

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@
CD154 CD155 CD142 CD127 CD141 CD152 CD150 CD158 CD143 CD137 DQ22 DDRB_DQ2
2 2 2 2 2 2 2 2 2 2 2 2 DQ23 DDRB_DQ1
DQS#2 DDRB_DQS#2

om
2 2 2 2 2 2 2 2 2 2
DQS2 DDRB_DQS2
UD3 UD2
UD4 DQ24 DDRB_DQ15
DDR_B_MA0 P3 G2 DDR_B_D35 DRAM@ DRAM@ DRAM@ DRAM@ DRAM@ DRAM@ DRAM@ DRAM@ DRAM@ DRAM@
DDR_B_MA1 A0 DQL0 DDR_B_D38 DDR_B_MA0 DDR_B_D62
DQ25 DDRB_DQ11
P7 F7 P3 G2 [email protected]
DDR_B_MA2 R3 A1 DQL1 H3 DDR_B_D34 DDR_B_MA1 P7 A0 DQL0 F7 DDR_B_D57 DQ26 DDRB_DQ12
DDR_B_MA3 N7 A2 DQL2 H7 DDR_B_D37 DDR_B_MA2 R3 A1 DQL1 H3 DDR_B_D58 DQ27 DDRB_DQ8
DDR_B_MA4 N3 A3 DQL3 H2 DDR_B_D39 DDR_B_MA3 N7 A2 DQL2 H7 DDR_B_D56 +1.2V DQ28 DDRB_DQ13

.c
DDR_B_MA5 P8 A4 DQL4 H8 DDR_B_D36 DDR_B_MA4 N3 A3 DQL3 H2 DDR_B_D59 DQ29 DDRB_DQ9
DDR_B_MA6 P2 A5 DQL5 J3 DDR_B_D32 DDR_B_MA5 P8 A4 DQL4 H8 DDR_B_D60
DDR_B_MA7 A6 DQL6 DDR_B_D33 DDR_B_MA6 A5 DQL5 DDR_B_D63 +1.2V +0.6VS
DQ30 DDRB_DQ14
R8 J7 P2 J3 DQ31 DDRB_DQ10
DDR_B_MA8 R2 A7 DQL7 A3 DDR_B_D42 DDR_B_MA7 R8 A6 DQL6 J7 DDR_B_D61
DDR_B_MA9 R7 A8 DQU0 B8 DDR_B_D40 DDR_B_MA8 R2 A7 DQL7 A3 DDR_B_D50 DQS#3 DDRB_DQS#3

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K
ix
DDR_B_MA10 M3 A9 DQU1 C3 DDR_B_D45 DDR_B_MA9 R7 A8 DQU0 B8 DDR_B_D49 DQS3 DDRB_DQS3
DDR_B_MA11 T2 A10/AP
A11
DQU2
DQU3
C7 DDR_B_D46 DDR_B_MA10 M3 A9
A10/AP
DQU1
DQU2
C3 DDR_B_D51 CD362 1 2 0.22U_0201_6.3V6-K CD174
1
CD173
1
CD169
1
CD165
1
CD167
1
CD172
1
CD171
1
CD175
1
CD168
1
CD166
1
UD2
DDR_B_MA12 M7 C2 DDR_B_D43 DDR_B_MA11 T2 C7 DDR_B_D53 @ DQ32 DDRB_DQ6
DDR_B_MA13 T8 A12/BC_N DQU4 C8 DDR_B_D41 DDR_B_MA12 M7 A11 DQU3 C2 DDR_B_D54 CD363 1 2 0.22U_0201_6.3V6-K
A13 DQU5 DDR_B_D44 DDR_B_MA13 A12/BC_N DQU4 DDR_B_D48 2 2 2 2 2 2 2 2 2 2 DQ33 DDRB_DQ7

af
D3 T8 C8 @
DDR_B_W E# L2 DQU6 D7 DDR_B_D47 A13 DQU5 D3 DDR_B_D55 CD364 1 2 0.22U_0201_6.3V6-K
DQ34 DDRB_DQ2
DDR_B_CAS# M8 WE_N/A14 DQU7 DDR_B_W E# L2 DQU6 D7 DDR_B_D52 DRAM@ DQ35 DDRB_DQ1
DDR_B_RAS# L8 CAS_N/A15 +1.2V DDR_B_CAS# M8 WE_N/A14 DQU7 DQ36 DDRB_DQ5
RAS_N/A16 D1 DDR_B_RAS# L8 CAS_N/A15 +1.2V DRAM@ DRAM@ DRAM@ DRAM@ DRAM@ DRAM@ DRAM@ DRAM@ DRAM@ DRAM@ DQ37 DDRB_DQ3
SB_CLK_DDR#0 K8 VDD1 J1 RAS_N/A16 D1 DQ38 DDRB_DQ4

in
B B
SB_CLK_DDR0 K7 CK_C VDD2 L1 SB_CLK_DDR#0 K8 VDD1 J1 +1.2V
CK_T VDD3 SB_CLK_DDR0 CK_C VDD2 +1.2V DQ39 DDRB_DQ0
R1 K7 L1
DDR_B_CKE0 K2 VDD4 B3 CK_T VDD3 R1 DQS#4 DDRB_DQS#4
CKE VDD5 G7 DDR_B_CKE0 K2 VDD4 B3 DQS4 DDRB_DQS4
DDR_B_DQS#4 F3 VDD6 B9 CKE VDD5 G7 UD3
S145API EMC request for 1.2V

//v
DDR_B_DQS4 G3 DQSL_C VDD7 J9 DDR_B_DQS#7 F3 VDD6 B9

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K
DQSL_T VDD8 DQSL_C VDD7
DQ40 DDRB_DQ9
DDR_B_DQS#5 DDR_B_DQS7
DDR_B_DQS5
A7
B7 DQSU_C
DQSU_T
VDD9
VDD10
L9
T9 DDR_B_DQS#6
DDR_B_DQS6
G3
A7 DQSL_T
DQSU_C
VDD8
VDD9
J9
L9 plane edge EMI CD215
1
CD218
1
CD212
1
CD211
1
1 1
DQ41
DQ42
DDRB_DQ15
DDRB_DQ12
B7 T9 @ @ @ @ CD133 CD153
DDRA_MB_DM5 E2 A1 DQSU_T VDD10 +1.2V 22P_0402_50V8-J 22P_0402_50V8-J DQ43 DDRB_DQ14
DDRA_MB_DM4 E7 NF/UDM_N/UDBI_N VDDQ1 C1 DDRA_MB_DM6 E2 A1 2 2 2 2 RF_NS@ RF_NS@ DQ44 DDRB_DQ11
NF/LDM_N/LDBI_N VDDQ2 NF/UDM_N/UDBI_N VDDQ1 2 2

s:
G1 DDRA_MB_DM7 E7 C1 DQ45 DDRB_DQ13
DDR_B_BA0 N2 VDDQ3 F2 NF/LDM_N/LDBI_N VDDQ2 G1
DDR_B_BA1 BA0 VDDQ4 DDR_B_BA0 VDDQ3
DQ46 DDRB_DQ10
N8 J2 N2 F2 DQ47 DDRB_DQ8
BA1 VDDQ5 F8 DDR_B_BA1 N8 BA0 VDDQ4 J2
DDR_B_ACT_N L3 VDDQ6 J8 BA1 VDDQ5 F8
DQS#5 DDRB_DQS#5

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K
ACT_N VDDQ7 VDDQ6 DQS5 DDRB_DQS5

tp
DDR_B_CS0# L7 A9 DDR_B_ACT_N L3 J8 CD352 1 CD353 1 CD354 1 CD355 1 CD356 1
DDR_B_ALERT_N P9 CS_N
ALERT_N
VDDQ8
VDDQ9
D9
+2.5V
DDR_B_CS0#
DDR_B_ALERT_N
L7 ACT_N
CS_N
VDDQ7
VDDQ8
A9
+0.6VS
UD3
G9 P9 D9

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@
DDR_B_BG0 VDDQ10 ALERT_N VDDQ9 +2.5V
DQ48 DDRB_DQ11
M2 G9 DQ49 DDRB_DQ13
BG0 DDR_B_BG0 VDDQ10 2 2 2 2 2
DDR_B_ODT0 K3 VPP1
B1
R9 ht M2
BG0 B1 follow SCL 10pcs 0.22uf DQ50 DDRB_DQ8
ODT VPP2 +VREF_CA_MD DDR_B_ODT0 K3 VPP1 R9 DQ51 DDRB_DQ14
DDR_B_PARITY T3 M1 ODT VPP2 +VREF_CA_MD DQ52 DDRB_DQ9

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K
PAR VREFCA DDR_B_PARITY
1U_0402_6.3V6K

T3 M1 DQ53 DDRB_DQ15
0.1U_0201_6.3V6-K

1 1 PAR VREFCA 1 1 1 1 1 1 1 1 1 1

1U_0402_6.3V6K
0.1U_0201_6.3V6-K
10K_0402_5%1 DRAM@ 2 RD255 TEN3 N9 E1 1 1 CD146 CD148 CD139 CD138 CD201 CD245 CD246 CD244 CD243 CD242 DQ54 DDRB_DQ12
CD236

CD237

TEN VSS1 K1 10K_0402_5%1 DRAM@ 2 RD257 N9 E1

0.1U_0201_6.3V6-K

TEN4
1000P 25V K X7R 0201

1 1 DQ55 DDRB_DQ10

CD240

CD241
DDR4_B_DRAMRST#_R P1 VSS2 N1 TEN VSS1 K1

0.1U_0201_6.3V6-K
1000P 25V K X7R 0201
1 1
CD234

CD235

RESET_N VSS3 T1 2 2 DDR4_B_DRAMRST#_R P1 VSS2 N1 2 2 2 2 2 2 2 2 2 2 DQS#6 DDRB_DQS#7

CD238

CD239
F1 VSS4 B2 DRAM@ RESET_N VSS3 T1 2 DRAM@ 2 DQS6 DDRB_DQS7
0.1U_0201_6.3V6-K

VSSQ1 VSS5 2 2 DRAM@ VSS4 DRAM@ UD4

0.1U_0201_6.3V6-K

1 H1 G8 F1 B2
A2 VSSQ2 VSS6 K9 H1 VSSQ1 VSS5 G8 2 2
DRAM@ 1 DQ56 DDRB_DQ5
CD161

D2 VSSQ3 VSS8 DRAM@ A2 VSSQ2 VSS6 K9 DRAM@ DRAM@ DRAM@ DRAM@ DRAM@ DRAM@ DRAM@ DRAM@ DRAM@ DRAM@ DRAM@
S145API Place near UD1
R10172 DRAM@ DQ57 DDRB_DQ1
CD162

E3 VSSQ4 T7 1 2 D2 VSSQ3 VSS8 R10173

@ 2 A8 VSSQ5 VSS7 DDP@ 0_0402_5% E3 VSSQ4 T7 1 2 DQ58 DDRB_DQ2
D8 VSSQ6 @ 2 A8 VSSQ5 VSS7 DDP@ 0_0402_5% +1.2V +0.6VS +0.6VS DQ59 DDRB_DQ0
E8 VSSQ7 M9 DRAM_DDRB_BG1 D8 VSSQ6 +2.5V DQ60 DDRB_DQ7
C9 VSSQ8 VSS9 E8 VSSQ7 M9 DRAM_DDRB_BG1 DQ61 DDRB_DQ3
H9 VSSQ9 E9 UD3_DDRB_UZQ C9 VSSQ8 VSS9
VSSQ10 VSS10 VSSQ9 UD4_DDRB_UZQ
DQ62 DDRB_DQ6
F9 H9 E9

180P_50V_J_NPO_0402
ZQ VSSQ10 VSS10 DQ63 DDRB_DQ4
F9

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K
ZQ 1 1 DQS#7 DDRB_DQS#6
1 1 1 1 1 1 CD265

CC205
DQS7 DDRB_DQS6
1

CD350 CD351 CD259 CD252 CD263 CD264 22P_0402_50V8-J

K4AAG165W A-BCW E_FBGA96 RD118 RD119 @ @ 22P_0402_50V8-J 22P_0402_50V8-J RF_NS@ UD4
A @ 2 2 A

DRAM@

DRAM@
240_0402_1% K4AAG165W A-BCW E_FBGA96 240_0402_1% RF_NS@ RF_NS@
@ 2 2 2 2 2 2
DRAM@ @ DRAM@
2

DDR4_B_DRAMRST# Security Classification LC Future Center Secret Data Title

5 DDR4_B_DRAMRST# RD502 1 @ 2 0_0402_5% DDR4_B_DRAMRST#_R
Issued Date 2013/08/15 Deciphered Date 2013/08/15 DDRVI MD
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S350 ARE
Date: Sunday, January 19, 2020 Sheet 15 of 44
Date: Sheet
5 4 3 2 1
 5 4 3 2 1

D D

C C

om
.c
ix
af
in
//v
s:
B B

tp
ht

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2016/08/16 Deciphered Date 2017/08/15 Blank
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
B
S350 ARE 1.0

Date: Sunday, January 19, 2020 Sheet 16 of 44

5 4 3 2 1
 5 4 3 2 1

LCD POWER CIRCUIT B+ to +LEDVDD POWER

+LCDVDD_CON
+3VS +3VS
W=40 mils V20B+
U9 +3VS_CMOS +LEDVDD
5 1 W=60mils F3 0.5A_32V_ERBRD0R50X F2
IN OUT 1 2 2A 80 mil
2 1 2
1U_0402_6.3V6K

RF_NS@

0.1U_0201_6.3V6-K
1 GND

10U_0603_6.3V6M

0.1U_0201_6.3V6-K

4.7U_0805_25V6-K
C1

C25

33P_0402_50V8J
4.7U_0402_6.3V6M
PCH_ENVDD 4 3 @1
EN OCB 1 1 1 1 1 1
C1321 C3 3A_32V_0497003PKRHF C23
2 0.1U_0402_25V6
D SY6288C20AAC_SOT23-5 @ @ C23 0.1u for G HSW panel blink issue D
2 2 2 2 2 2 2

C2

C122

C123
PCH_ENVDD
6 PCH_ENVDD For RF

JEDP1
1
+LEDVDD 1
2
3 2
4 3
5 4
APU_EDP_TX0+ C19 2 1 0.1U_0201_6.3V6-K EDP_TX0+ 6 5
APU output enable Voh min is 1.8V-0.45V=1.35V 6 APU_EDP_TX0+ APU_EDP_TX0- C16 EDP_TX0- 6
2 1 0.1U_0201_6.3V6-K 7
6 APU_EDP_TX0- 8 7
APU_EDP_TX1+ C17 2 1 0.1U_0201_6.3V6-K EDP_TX1+ 9 8
6 APU_EDP_TX1+ APU_EDP_TX1- C18 2 1 0.1U_0201_6.3V6-K EDP_TX1- 10 9
6 APU_EDP_TX1- 11 10
APU_EDP_AUX C20 2 1 0.1U_0201_6.3V6-K EDP_AUX 12 11
6 APU_EDP_AUX APU_EDP_AUX# C21 2 1 0.1U_0201_6.3V6-K EDP_AUX# 13 12
6 APU_EDP_AUX# 14 13
PCH_EDP_PWM R19 2 1 0_0402_5% INVT_PWM DISPOFF# 15 14
6 PCH_EDP_PWM
@ AUX don't pull high and pull low for eDP panel INVT_PWM 16 15
17 16
6 APU_EDP_HPD 17
1

18
+LCDVDD_CON 18
R20 W=60mils 19
100K_0402_5% 20 19
@ 21 20
C 22 21 C
28 DMIC_CLK 22
2

23
28 DMIC_DATA 23
24
+3VS_CMOS 24

om
W=40mils 25
26 25
27 26
R182 2 @ 1 0_0402_5% USB20_P2_R 28 27

+3VS
CMOS Camera 9
9
USB20_P2
USB20_N2
R183 2 @ 1 0_0402_5% USB20_N2_R 29
30
28
29 GND1
31
32

.c
30 GND2

HIGHS_FC5AF301-3181H
2

ix
R10 ME@
4.7K_0402_5% L12 EMC_NS@

af
@ USB20_N2 1 2 USB20_N2_R
1 2
1

USB20_P2 USB20_P2_R

in
R12 2 @ 1 0_0402_5% DISPOFF# 4 3
31 BKOFF# 4 3
EXC24CH900U_4P

//v
R14 2 @ 1 0_0402_5% ENBKL
6 PCH_ENBKL ENBKL 31
1

R16 DMIC_CLK DISPOFF# INVT_PWM DMIC_DATA

s:
470P_0201_50V7-K

470P_0201_50V7-K
100K_0402_5%
33P_0402_50V8J

33P_0402_50V8J
EMC_NS@ EMC_NS@ EMC_NS@ EMC_NS@
C12

C13
1 1 1 1

tp
2

C11

C57
2 ht 2 2 2

B B

EMC

+3VS

Touch Screen RTS1 1 @ 2 0_0402_5%

+5VS +3VS_TS

USB20_P3_CONN
RTS2 1 @ 2 0_0402_5%
L15 USB20_N3_CONN JTS1
1
USB20_P3 1 2 USB20_P3_CONN CTS1 1
1 2 1
3

+3VS_TS 0.1u_0201_10V6K RTS3 1 @ 2 0_0402_5% TS_RS 2

31 EC_TS_ON 3 2
TS@
USB20_N3 4 3 USB20_N3_CONN 2 RTS4 1 @ 2 0_0402_5% USB20_N3_CONN 4 3
4 3 9 USB20_N3 4
1

D2 RTS5 1 @ 2 0_0402_5% USB20_P3_CONN 5

9 USB20_P3 6 5
EXC24CH900U_4P
1

6 7
EMC_NS@ GND1 8
D757 GND2
AZC199-02S.R7G_SOT23-3 HIGHS_WS83061-S0171-HF
For EMI
2

EMC_NS@ ME@
A AZ5725-01F.R7GR_DFN1006P2X2 A
2

EMC_NS@ change symbol to SP021412291 by amy 0620

1

For ESD

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 eDP/CMOS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S350 ARE
Date: Sunday, January 19, 2020 Sheet 17 of 44
5 4 3 2 1
 5 4 3 2 1

D D

C C

om
.c
ix
af
in
//v
s:
tp
B
ht B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2016/08/16 Deciphered Date 2017/08/15 Blank

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
S350 ARE 1.0

Date: Sunday, January 19, 2020 Sheet 18 of 44

5 4 3 2 1
 5 4 3 2 1

7/29 S145API EMC request for HDMI

1
HDMI_CLK-_CON
R300 +3VS
270_0402_1%
HDMI_CLK+_CON
EMC_270@

2
D D

D3

5
G
Q1B HDMI_DET 1 1 10 9 HDMI_DET

1
HDMI_TX0-_CON
R301 HDMICLK_R 2 2 9 8 HDMICLK_R
270_0402_1% APU_HDMI_DDC_CLK 4 3 HDMICLK_R

S
HDMI_TX0+_CON 6 APU_HDMI_DDC_CLK HDMIDAT_R HDMIDAT_R
4 4 7 7

D
EMC_270@ 2N7002KDWH_SOT363-6

2
+5VS_HDMI 5 5 6 6 +5VS_HDMI

G
Q1A
3 3

1
HDMI_TX1-_CON
R302 APU_HDMI_DDC_DATA 1 6 HDMIDAT_R 8

S
6 APU_HDMI_DDC_DATA
270_0402_1%

D
HDMI_TX1+_CON 2N7002KDWH_SOT363-6
EMC_270@ AZ1045-04F_DFN2510P10E-10-9

2
EMC_NS@

EMC

1
HDMI_TX2-_CON
R303
270_0402_1%
HDMI_TX2+_CON
EMC_270@

2
+5VS +5VS_HDMI_F +5VS_HDMI

+3VS F1
1 2
C C
1.1A_8V_1206L110THYR
HDMI_CLK-_CON R29 1 2 499_0402_1%
Follow Zx05 and beema

1
HDMI_CLK+_CON R30 1 2 499_0402_1% C LP2301ALT1G_SOT23-3 1 2
Q43 2 R202 1 2 150K_0402_5% HDMI_DET C34 CC1279
HDMI_TX0-_CON R31 1 2 499_0402_1% B 1 3 Q22 0.1u_0201_10V6K 10U 6.3V M X5R 0402

2
1
E MMBT3904WH_SOT323-3 @

om
2 1

3
HDMI_TX0+_CON R32 1 2 499_0402_1% RP2
6 APU_HDMI_HPD

1
2.2K_0404_4P2R_5%

G
2
1
HDMI_TX1-_CON R33 1 2 499_0402_1% R257
R910 100K_0402_5%
14,33 SUSP

3
4
HDMI_TX1+_CON R34 1 2 499_0402_1% 100K_0402_5%

.c
2
HDMI_TX2-_CON R37 1 2 499_0402_1%

2
+5VS_HDMI
HDMI_TX2+_CON R38 1 2 499_0402_1% JHDMI1 ME@

ix
18 15 HDMICLK_R
+5V_Power SCL 16 HDMIDAT_R

af
SDA
1

D
2 Q13 APU_HDMI_TX0+ C38 2 1 0.1U_0201_6.3V6-K HDMI_TX0+_CON 7
+3VS 6 APU_HDMI_TX0+ TMDS_Data0+
G L2N7002KWT1G_SOT323-3 APU_HDMI_TX0- C37 2 1 0.1U_0201_6.3V6-K HDMI_TX0-_CON 9 13
6 APU_HDMI_TX0-

in
APU_HDMI_TX1+ C40 2 1 0.1U_0201_6.3V6-K HDMI_TX1+_CON 4 TMDS_Data0- CEC 17
6 APU_HDMI_TX1+ APU_HDMI_TX1- HDMI_TX1-_CON TMDS_Data1+ DDC/CEC_Ground HDMI_DET
S C39 2 1 0.1U_0201_6.3V6-K 6 19
6 APU_HDMI_TX1- TMDS_Data1- Hot_Plug_Detect
3

APU_HDMI_TX2+ C42 2 1 0.1U_0201_6.3V6-K HDMI_TX2+_CON 1

6 APU_HDMI_TX2+ TMDS_Data2+

//v
R42 1 @ 2 APU_HDMI_TX2- C41 2 1 0.1U_0201_6.3V6-K HDMI_TX2-_CON 3
6 APU_HDMI_TX2- TMDS_Data2-
100K_0402_5% 8 14
5 TMDS_Data0_Shield Utility
2 TMDS_Data1_Shield

s:
TMDS_Data2_Shield
B 20 B
11 GND1 21

tp
APU_HDMI_CLK+ C36 2 1 0.1U_0201_6.3V6-K HDMI_CLK+_CON 10 TMDS_Clock_Shield GND2 22
6 APU_HDMI_CLK+ APU_HDMI_CLK- HDMI_CLK-_CON TMDS_Clock+ GND3
C35 2 1 0.1U_0201_6.3V6-K 12 23
6 APU_HDMI_CLK- TMDS_Clock- GND4
ht
ALLTO_C128AF-K1935-L

D6 D7
HDMI_CLK+_CON 1 1 10 9 HDMI_CLK+_CON HDMI_TX1-_CON 1 1 10 9 HDMI_TX1-_CON

HDMI_CLK-_CON 2 2 9 8 HDMI_CLK-_CON HDMI_TX1+_CON 2 2 9 8 HDMI_TX1+_CON

HDMI_TX0+_CON 4 4 7 7 HDMI_TX0+_CON HDMI_TX2-_CON 4 4 7 7 HDMI_TX2-_CON

HDMI_TX0-_CON 5 5 6 6 HDMI_TX0-_CON HDMI_TX2+_CON 5 5 6 6 HDMI_TX2+_CON

3 3 3 3

8 8

AZ1045-04F_DFN2510P10E-10-9 AZ1045-04F_DFN2510P10E-10-9
EMC_NS@ EMC_NS@

EMC
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/15 Deciphered Date 2013/08/15 HDMI_CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S350 ARE
Date: Sunday, January 19, 2020 Sheet 19 of 44
5 4 3 2 1
 A B C D E

+USB_VCCA

C8815 1 2 100U_1206_6.3V6M

LEFT SIDE USB3.0 PORT x2 C8806 1 2 150U_B2_6.3VM_R35M

+
USB30_TX_P1 C126 1 2 0.22U_6.3V_K_X5R_0402 USB30_TX_C_P1 C125 1@ 2 1U_0402_10V6K
9 USB30_TX_P1
@
+5VALW +USB_VCCA USB30_TX_N1 C124 1 2 0.22U_6.3V_K_X5R_0402 USB30_TX_C_N1 C127 1 2 1U_0402_10V6K
9 USB30_TX_N1
U2 @
5 1
IN OUT JUSB1 ME@
1
C128 2
1U_0402_10V6K GND R95 1 @ 2 0_0402_5% USB30_TX_R_P1 9
4 3 USB_OC1# 1 StdA_SSTX+
2 20,21,31 USB_ON# ENB OCB USB_OC1# 9 R96 1 @ 2 0_0402_5% USB30_TX_R_N1 8 VBUS
SY6288D20AAC_SOT23-5 USB20_P1 R97 1 @ 2 0_0402_5% USB20_P1_R 3 StdA_SSTX-
1 9 USB20_P1 D+
1 C140 7 1
1000P_0201_50V7-K USB20_N1 R93 1 @ 2 0_0402_5% USB20_N1_R 2 GND_DRAIN 10
9 USB20_N1 USB30_RX_R_P1 D- GND_2
EMC_NS@ R94 1 @ 2 0_0402_5% 6 11
Low Active 2A 2 4 StdA_SSRX+ GND_3 12
R98 1 @ 2 0_0402_5% USB30_RX_R_N1 5 GND_1 GND_4 13
StdA_SSRX- GND_5

USB30_RX_P1 C8787 1 USB30_RX_C_P1 ALLTO_C19043-10905-L

2 0.33U 10V K X5R 0402
9 USB30_RX_P1
USB30_RX_N1 C8788 1 2 0.33U 10V K X5R 0402 USB30_RX_C_N1
9 USB30_RX_N1

L13 EMC_NS@
USB30_RX_C_N1 1 2 USB30_RX_R_N1
1 2

USB30_RX_C_P1 4 3 USB30_RX_R_P1
4 3
EXC24CH900U_4P USB20_P1_R
+USB_VCCA
USB20_N1_R D12 EMC@
L16 EMC_NS@ USB30_RX_R_N1 10 1 USB30_RX_R_N1
USB30_TX_C_N1 1 2 USB30_TX_R_N1 NC1 Line-1

AZ5725-01F.R7GR_DFN1006P2X2
1 2

2
D11 USB30_RX_R_P1 9 2 USB30_RX_R_P1
D13 NC2 Line-2

1
USB30_TX_C_P1 4 3 USB30_TX_R_P1 AZC199-02S.R7G_SOT23-3 USB30_TX_R_N1 7 4 USB30_TX_R_N1
4 3 EMC@ NC3 Line-3
EXC24CH900U_4P USB30_TX_R_P1 6 5 USB30_TX_R_P1
NC4 Line-4
3

2
EMC_NS@ GND1

2
L8 EMC@ 8
USB20_N1 1 2 USB20_N1_R GND2
1 2 AZ1143-04F-R7G_DFN2510P10E10

1
USB20_P1 4 3 USB20_P1_R
4 3
EXC24CH900U_4P
EMC
EMC

2 USB3.0 PORT 2

+5VALW +USB_VCCB
U25

om
5 1
IN OUT
1
C8813 2
L30 EMC_NS@ 1U_0402_10V6K GND
USB30_RX_C_N4 1 2 USB30_RX_R_N4 USB_ON# 4 3 USB_OC2#
1 2 20,21,31 2 USB_ON# ENB OCB USB_OC2# 9
SY6288D20AAC_SOT23-5
USB30_RX_C_P4 4 3 USB30_RX_R_P4
4 3

.c
1
EXC24CH900U_4P Low Active 2A C8814
1000P_0201_50V7-K
EMC_NS@
L29 EMC_NS@ 2

ix
USB30_TX_C_N4 1 2 USB30_TX_R_N4
1 2 +USB_VCCB

USB30_TX_C_P4 4 3 USB30_TX_R_P4
4 3

af
EXC24CH900U_4P
C8816 1 2 100U_1206_6.3V6M

L17 EMC@

in
USB20_N4_S 1 2 USB20_N4_R C8817 1 2 150U_B2_6.3VM_R35M

+
1 2
USB30_TX_P4 C2058 1 USB30_TX_C_P4
2 0.22U_6.3V_K_X5R_0402 C2060 1@ 2 1U_0402_10V6K
USB20_P4_S USB20_P4_R 9 USB30_TX_P4
4 3 @
4 3 USB30_TX_N4 C2057 1 USB30_TX_C_N4
2 0.22U_6.3V_K_X5R_0402 C2059 1 2 1U_0402_10V6K

//v
9 USB30_TX_N4
EXC24CH900U_4P @
JUSB2 ME@

R3119 1 @ 2 0_0402_5% USB30_TX_R_P4 9

1 StdA_SSTX+

s:
R3116 1 @ 2 0_0402_5% USB30_TX_R_N4 8 VBUS
USB20_P4_S R3103 1 @ 2 0_0402_5% USB20_P4_R 3 StdA_SSTX-

For USB Debug Function USB20_N4_S R942 1

R3117 1
@
@
2 0_0402_5%
2 0_0402_5%
UARTA_P80_EN
USB20_N4_R
USB30_RX_R_P4
7
2
6
D+
GND_DRAIN
D- GND_2
10
11

tp
4 StdA_SSRX+ GND_3 12
R3114 1 @ 2 0_0402_5% USB30_RX_R_N4 5 GND_1 GND_4 13
StdA_SSRX- GND_5

3
7 USBDEBUG
R531
2 Debug@ 1
0_0402_5%
USB_UART_SEL 9

9
USB30_RX_P4

USB30_RX_N4
USB30_RX_P4 C8789 1

USB30_RX_N4 C8790 1
ht
2 0.33U 10V K X5R 0402USB30_RX_C_P4

2 0.33U 10V K X5R 0402USB30_RX_C_N4

ALLTO_C19043-10905-L
3

1
R538
2

2 Debug@
R537

100K_0402_5%
U129
0_0402_5%
D45 EMC@
USB30_RX_R_N4 10 1 USB30_RX_R_N4
NC1 Line-1
1

R533 2 Debug@ 1 0_0402_5% EC_TX_C 1 10 R11 2 Debug@ 1 0_0402_5%

+3VALW
27,31 EC_TX 1D+ VCC @ USB30_RX_R_P4 USB30_RX_R_P4
9 2
R536 2 Debug@ 1 0_0402_5% EC_RX_C 2 9 USB_UART_SEL NC2 Line-2
27,31 EC_RX 1D- S USB30_TX_R_N4 USB30_TX_R_N4
7 4
3 8 USB20_P4_S NC3 Line-3
9 USB20_P4 2D+ D+ USB30_TX_R_P4 USB30_TX_R_P4
NCY3958Y 6 5
4 7 USB20_N4_S NC4 Line-4
9 USB20_N4 2D- D- 3
5 6 GND1
GND1 OE# 8
11 GND2
GND2 AZ1143-04F-R7G_DFN2510P10E10

NCT3958Y_DFN10_3X3
Debug@
FOR ESD Close to Connector
USB20_P4_R +USB_VCCB

USB20_N4_R
3

USB20_P4 R539 1 @ 2 0_0402_5% USB20_P4_S D43

AZ5725-01F.R7GR_DFN1006P2X2

AZC199-02S.R7G_SOT23-3
1

EMC@
USB20_N4 R541 1 @ 2 0_0402_5% USB20_N4_S D34
1

USBDEBUG Kernel debug EMC_NS@

Set input Set input

2

Set output Low ENABLE

2
1

+3VALW

4
UARTA_P80_EN POST 80 4
1

Set input DISABLE R547

Debug@ 10K_0402_5%
Set output Low ENABLE
2

USB_UART_SEL
1

D
UARTA_P80_EN 2
OE# S FUNCTION G L2N7002KWT1G_SOT323-3
Q56
H X DISABLE S Debug@
3

Security Classification LC Future Center Secret Data Title

L L D(+/-) to 1D(+/-)

L H D(+/-) to 2D(+/-) Issued Date 2016/08/16 Deciphered Date 2017/08/15 USB3.0 PORT (LEFT)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S350 ARE
Date: Sunday, January 19, 2020 Sheet 20 of 44
A B C D E
 5 4 3 2 1

D D

Follow S145WHL
+5VALW +USB_VCCD +USB_VCCD
U132
5 1
IN OUT
1
C8808 2
1U_0402_10V6K GND
USB_ON# 4 3 USB_OC0#
20,31
2 USB_ON# ENB OCB USB_OC0# 9
SY6288D20AAC_SOT23-5 1 C8810 1 2 100U_1206_6.3V6M
C8809
1000P_0201_50V7-K
Low Active 2A EMC_NS@ C8804 1 2 150U_B2_6.3VM_R35M

+
2
C8811 1@ 2 1U_0402_10V6K
@
C8812 1 2 1U_0402_10V6K
@
JUSB3
1
USB20_N0 R4713 1 @ 2 0_0402_5% USB20_N0_R 2 VBUS
9 USB20_N0 USB20_P0 USB20_P0_R D-
R4714 1 @ 2 0_0402_5% 3
9 USB20_P0 4 D+ 5
GND GND1 6
C C
GND2 7
GND3 8
GND4

om
ALLTO_C107G1-10803-L
ME@

12/30 Update USBConn

.c
FOR ESD Close to Connector
USB20_P0_R +USB_VCCD

ix
USB20_N0_R

af
3

2
D755

AZ5725-01F.R7GR_DFN1006P2X2
AZC199-02S.R7G_SOT23-3

1
in
EMC@
D756

1
L34 EMC@
USB20_P0 4 3 USB20_P0_R EMC_NS@

//v
4 3

USB20_N0 1 2 USB20_N0_R

2
1 2

2
s:
EXC24CH900U_4P

1
tp
B
ht B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2016/08/16 Deciphered Date 2017/08/15 USB2.0

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
S350 ARE 1.0

Date: Sunday, January 19, 2020 Sheet 21 of 44

5 4 3 2 1
 5 4 3 2 1

+3VS Need short +3VS_SSD1

J8 @ Min 3A
1 2
1 2

10U 6.3V M X5R 0402

4.7U_0402_6.3V6M
C5
JUMP_43X79

0.1U_0201_6.3V6-K
C2037
1 1 1 1 1

10U 6.3V M X5R 0402

C2093

C2094

C2095
@

10U_0603_6.3V6M
D 2 2 2 2 2 D

CD@ CD@

+3VS_SSD1

JSSD1
76
GND15
1 2
3 GND1 3.3V_1 4
5 GND2 3.3V_2 6
4 PCIE_PRX_DTX_N0 PERn3 N/C_2
7 8
4 PCIE_PRX_DTX_P0 9 PERp3 N/C_3 10
PCIE_PTX_C_DRX_N0 11 GND3 DAS/DSS#(I/O)/LED1#(I)(0/3.3V) 12
4 PCIE_PTX_C_DRX_N0 PCIE_PTX_C_DRX_P0 PETn3 3.3V_3
4 PCIE_PTX_C_DRX_P0 13 14
15 PETp3 3.3V_4 16
4 PCIE_PRX_DTX_N1 17 GND4 3.3V_5 18
19 PERn2 3.3V_6 20
4 PCIE_PRX_DTX_P1 21 PERp2 N/C_4 22 +3VS_SSD1
PCIE_PTX_C_DRX_N1 23 GND5 N/C_5 24
4 PCIE_PTX_C_DRX_N1 PCIE_PTX_C_DRX_P1 PETn2 N/C_6
25 26
4 PCIE_PTX_C_DRX_P1 PETp2 N/C_7

1
27 28
29 GND6 N/C_8 30 RF41
4 PCIE_PRX_DTX_N2 31 PERn1 N/C_9 32
4 PCIE_PRX_DTX_P2 PERp1 N/C_10 10K_0402_5%
33 34 @ RB521CM-30T2R_VMN2M-2 S550_ICL PULL UP TO +3VS_SSD
PCIE_PTX_C_DRX_N2 35 GND7 N/C_11 36 D29
4 PCIE_PTX_C_DRX_N2 PETn1 N/C_12

2
PCIE_PTX_C_DRX_P2 37 38 2 @1
4 PCIE_PTX_C_DRX_P2 PETp1 DEVSLP(O) SATA_DEVSLP1 7
39 40
41 GND8 N/C_13 42 RF14 10K_0402_5%
4 PCIE_PRX_DTX_P3 PERn0/SATA-B+ N/C_14
43 44 1 2
4 PCIE_PRX_DTX_N3 45 PERp0/SATA-B- N/C_15 46 @
PCIE_PTX_C_DRX_N3 47 GND9 N/C_16 48
4 PCIE_PTX_C_DRX_N3 PCIE_PTX_C_DRX_P3 PETn0/SATA-A- N/C_17 SSD_RST#
49 50
4 PCIE_PTX_C_DRX_P3 51 PETp0/SATA-A+ PERST#(O)(0/3.3V) or N/C 52 SSD_CLKREQ_Q# R223 1 @ 2 0_0402_5%
SSD_CLKREQ# 8
53 GND10 CLKREQ#(I/O)(0/3.3V) or N/C 54 1 @ TP265
C 8 CLK_PCIE_SSD# C
55 REFCLKn PEWAKE#(I/O)(0/3.3V) or N/C 56
8 CLK_PCIE_SSD REFCLKp N/C_18
57 58
GND11 N/C_19

om
R3 1 @ 2 0_0201_5%
SUSCLK_R 27
67 68 SUSCLK_SSD1
SSD_DET1 69 N/C_1 SUSCLK(32kHz)(O)(0/3.3) 70 R1 1 @ 2 0_0201_5%
71 PEDET(NC-PCIe/GND-SATA) 3.3V_7 72 SUSCLK 8,27
GND12 3.3V_8

.c
73 74 +3VS_SSD1
75 GND13 3.3V_9
GND14 77
GND16

ix
ARGOS_NASM0-S6705-TSH4

af
ME@

in
change JSSD to YOGA530 Connector 0619

//v
s:
tp
B
ht B
+3VALW_APU +3VS_SSD1
1

R9 R467
2.2K_0402_1% 100K_0402_5%
2

R219 2 @ 1 0_0402_5% SSD_DET1

7 SSD_SATA_PCIE_DET1#
1

10K_0402_5% @ SSD_DET# R2 +3VS

@
R15 0--SATA 1 2 0_0402_5%

1--PCIE
2

+3VS

2
R25
@ 10K_0402_5%

5
U3

1
VCC
PLT_RST# 1
7,27,29 PLT_RST# IN1 SSD_RST#
4
APU_SSD_RST# 2 OUT
7 APU_SSD_RST#
GND
IN2
AND Gate:
MC74VHC1G08DFT2G_SC70-5 PLT_RST# APU_SSD_RST# SSD_RST#
3

L L L
1

L H L
A R8 H L L A
10K_0402_5% H H H
2

R232
@
1 2 0_0402_5%

Security Classification LC Future Center Secret Data Title

Issued Date 2016/08/16 Deciphered Date 2017/08/15 M.2 SSD

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document
Size DocumentNumber
Number Rev
Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
S350 ARE 1.0

Date:
Date: Sunday, January 19, 2020 Sheet
Sheet 22 of 44
5 4 3 2 1
 5 4 3 2 1

D D

C C

om
.c
ix
af
in
//v
s:
B B

tp
ht

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/15 Deciphered Date 2013/08/15 Blank
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
B
S350 ARE 1.0

Date: Sunday, January 19, 2020 Sheet 23 of 44

5 4 3 2 1
 5 4 3 2 1

D D

C C

om
.c
ix
af
in
//v
s:
tp
B B

ht

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 Blank

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
S350 ARE 1.0

Date: Sunday, January 19, 2020 Sheet 24 of 44

5 4 3 2 1
 5 4 3 2 1

Thermal Sensor
placed nearby SO-DIMM +3VALW
Near Air outlet
US1
+3VS

1
RS1 1 @ 2 +3VS_THU1 1 10 RS2 1 @ 2 0_0402_5% RS5
D VCC SCL EC_SMB_CK2 6,31 D
13.7K_0402_1%
0_0402_5% REMOTE1+ 2 9 RS3 1 @ 2 0_0402_5%
DP1 SDA EC_SMB_DA2 6,31
1

2
CS1 REMOTE1- 3 8 NTC_V2
DN1 ALERT#

1
0.1U_6.3V_K_X5R_0402 REMOTE2+ 4 7 F75303M_THERM# RS4 1 @ 2 10K_0402_5%
2 DP2 THERM# +3VS
RS6
REMOTE2- 5 6 100K_0402_1%_NCP15WF104F03RC
DN2 GND

2
F75303M_MSOP10

2
Address 1001_101xb RS48
0_0402_5%
RS49
0_0402_5%
Internal pull up 1.2K to 1.5V @

R for initial thermal shutdown temp

1
@

REMOTE2+/-: EC_AGND

Trace width/space:10/10 mil

C
Trace length:<8" C

Close APU
REMOTE1+ REMOTE2+

om
REMOTE1+ REMOTE2+

1
C

1
1 1 1 2 QS2 C
CS4 @ B MMBT3904WH_SOT323-3 1 2 QS1

.c
CS2 CS3 E CS5 B MMBT3904WH_SOT323-3

3
2200P_25V_K_X7R_0201 2200P_25V_K_X7R_0201 100P_0402_50V8J @ E

3
2 2 2

ix
100P_0402_50V8J
2
REMOTE1- REMOTE2- REMOTE1-

af
REMOTE2-

in
//v
over temperature threshold:
RSET=3*RTMH
92+/-30C

s:
B B

Hysteresis temperature threshold.

tp
RHYST=(RSET*RTML)/(3*RTML-RSET)
+5VLP +5VLP
+3VL
+5VLP 56+/-30C ht
HW thermal sensor
2

2
1
CS6 RS8 RS9
0.1u_0201_10V6K

@ 21.5K_0402_1%
2

21.5K_0402_1%
@ @
RS7 2
1

1
@ 10K_0402_5%
US2 @
1 8 TMSNS1
1

VCC TMSNS1
2 7 PHYST1 RS10 1 @ 2 10K_0402_5%
GND RHYST1
3 6 TMSNS2 RS12 1 @ 2 0_0402_5% NTC_V2
40 EC_ON_R OT1 TMSNS2 NTC_V2 31
4 5 PHYST2 RS11 1 @ 2 10K_0402_5%
Open-Drain Active Low over-temperature output for sensor OT2 RHYST2
A G718TM1U_SOT23-8 A

Security Classification LC Future Center Secret Data Title

Issued Date Deciphered Date THERMAL SENSOR

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
B
S350 ARE 1.0

Date: Sunday, January 19, 2020 Sheet 25 of 44

5 4 3 2 1
 5 4 3 2 1

D D

FAN Conn
JFAN1
+5VS 1
31 EC_FAN_PWM1 1
C 31 EC_FAN_SPEED1 2 C
3 2
3

om
R4682 1 @ 2 0_0603_SP +5VS_FAN 4
4
5

.c
6 GND1
1 1 2 GND2
C2080 C2081 @ @ C2083

ix
10U_0603_10V6K 0.1u_0201_10V6K 10U 6.3V M X5R 0402

af
2 2 1 HIGHS_WS33040-S0351-HF

in
ME@

//v
s:
tp
ht
B B

A
Security Classification LC Future Center Secret Data Title A

Issued Date 2013/08/08 Deciphered Date 2013/08/05 FAN CONN

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
A 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S350 ARE
Date: Sunday, January 19, 2020 Sheet 26 of 44
5 4 3 2 1
 A B C D E

Mini-Express Card(WLAN/WiMAX)

22UC_6.3VC_MC_X5RC_0603
+3VS_W LAN
+3VS Need short
J2 @
1 2

1500P_50V_K_X7R_0402

0.1U_0201_6.3V6-K
1 2

10U 6.3V M X5R 0402

JUMP_43X79 1 1 1 1

C7

C6
C8797
1 1

C53
@ 2 2 @2 @ 2

+3VS +3VS_W LAN

U131 @
5 1
IN OUT
2 +3VS_W LAN
GND
3V_W LAN_EN 4 3
31 3V_W LAN_EN EN OCB

SY6288C20AAC_SOT23-5
JW LAN1
1 2
3 GND1 3.3V-2 4
9 USB20_P6 USB_D+ 3.3V-4
5 6 1 @ T7
9 USB20_N6 USB_D- LED1#
7 8
9 GND2 PCM_CLK/12S SCK 10
11 SDIO_CLK PCM_SYNC/12S WS 12
13 SDIO_CMD PCM_OUT/12S SD_OUT 14
15 SDIO_DAT0 PCM_IN/12S SD_IN 16 1 @ T6
17 SDIO_DAT1 LED2# 18
19 SDIO_DAT2 GND11 20
21 SDIO_DAT3 UART WAKE# 22
23 SDIO_WAKE# UART TXD
2 SDIO_RESET# 2

om
25 KEY E 24
27 PIN24~PIN31 NC PIN 26
29 28
31 30

.c
33 32
35 GND3 UART RXD 34

ix
4 PCIE_PTX_C_DRX_P4 PERP0 UART RTS
37 36
4 PCIE_PTX_C_DRX_N4 PERN0 UART CTS
39 38
GND4 RSRVD4

af
41 40
4 PCIE_PRX_DTX_P4 PETP0 RSRVD3
43 42
4 PCIE_PRX_DTX_N4 PETN0 RSRVD2
45 44
GND5 COEX3

in
47 46
8 CLK_PCIE_W LAN REFCLKP0 COEX2
49 48
8 CLK_PCIE_W LAN# REFCLKN0 COEX1 SUSCLK_R
51 50 R55 1 @ 2 0_0402_5%
GND6 SUSCLK SUSCLK 8,22

//v
R61 1 @ 2 0_0402_5% W LAN_CLKREQ_Q# 53 52 PLT_RST#
8 W LAN_CLKREQ# CLKREQ0# PERSTO# PLT_RST# 7,22,29
R262 1 @ 2 0_0402_5% PCIE_W AKE#_W LAN 55 54 BT_OFF# R53 1 2 1K_0402_5%
7,31 EC_PCIE_W AKE# PEWAKE0# W_DISABLE2# W LAN_OFF# PCH_BT_OFF# 7
57 56 R56 1 @ 2 0_0402_5%
GND7 W_DISABLE1# PCH_W LAN_OFF# 7
R317 1 @ 2 0_0402_5%

s:
31 W LAN_W AKE#
R90 1 @ 2 0_0402_5%
59 58 EC_RX_R R88 1 @ 2 0_0402_5%
RESERVED/PERP1 I2C_DATA EC_TX_R EC_RX 20,31
61 60 R89 1 @ 2 0_0402_5%

tp
RESERVED/PERN1 I2C_CLK EC_TX 20,31
63 62
65 GND8 ALERT# 64 R91 1 @ 2 0_0402_5%
RESERVED/PETP1 RSRVD1

1
67 ht 66
69 RESERVED/PETN1 UIM_SWP/PERST1# 68 +3VS_W LAN R186
71 GND9 UIM_POWER_SNK/CLKREQ1# 70 100K_0402_5%
3 73 RESERVED/REFCLKP1 UIM_POWER_SRC/GPIO1/PEWAKE1# 72 3
75 RESERVED/REFCLKN1 3.3V-72 74
GND10 3.3V-74

2
77 76 EC_RX
GND13 GND12 +3VS
1
ARGOS_NASE0-S6701-TSH4 C8818
ME@ 0.1U_0201_6.3V6-K @
2
1
change JWLAN to YOGA530 Connector 0619 C8793
0.1U_0201_6.3V6-K
@
2
U130
5 1
Vcc OE
2 SUSCLK
IN_A
SUSCLK_R 4 3
22 SUSCLK_R OUT_Y GND

M74VHC1GT125DF2G_SC70-5
@

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 NGFF WLAN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
Size Document
Document Number
Number Rev
Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S350 ARE
Date:
Date: Sunday, January 19, 2020 Sheet
Sheet 27 of 44
A B C D E
 5 4 3 2 1

IO Connector
@ @
RA3025 1 2 1K_0402_5% CA41 1 2
0.1U_0201_6.3V6-K S145API EMC request for
HDA_BITCLK_AUDIO
D D
DA1
2
31 EC_BEEP
1 PC_BEEP1 RA211 1 2 1K_0402_5% CA40 1 2 PC_BEEP HDA_BITCLK_AUDIO
3 0.1U_0201_6.3V6-K
7 PCH_BEEP

33P_0402_50V8J
LBAT54CWT1G_SOT323-3 RA14 1 EMC_NS@
10K_0402_5%

CA42
@
@

2
RA30261 @ 2 0_0402_5% 2

Place near J1

C C
+5VS +5VS
+3VL +3VS JIO1 JIO2
1 1
2 1 2 1
PC_BEEP 3 2 PC_BEEP 3 2
4 3 4 3

om
4 +3VS
5 5 4
5 +3VL
NOVO_BTN# 6 NOVO_BTN# 6 5
6 32 NOVO_BTN#
EC_MUTE# 7 EC_MUTE# 7 6
8 7 31 EC_MUTE# 8 7

.c
USB20_N5 9 8 USB20_N5 9 8
USB20_P5 10 9 9 USB20_N5 USB20_P5 10 9
10 9 USB20_P5 11 10

ix
11
DMIC_CLK 12 11 DMIC_CLK 12 11
DMIC_DATA 13 12 17 DMIC_CLK DMIC_DATA 13 12

af
13 17 DMIC_DATA
14 14 13
HDA_BITCLK_AUDIO 15 14 HDA_BITCLK_AUDIO 15 14
7 HDA_BITCLK_AUDIO

in
HDA_SDOUT_AUDIO 16 15 HDA_SDOUT_AUDIO 16 15
16 7 HDA_SDOUT_AUDIO
HDA_SDIN0 17 HDA_SDIN0 17 16
HDA_SYNC_AUDIO 18 17 7 HDA_SDIN0 HDA_SYNC_AUDIO 18 17

//v
18 7 HDA_SYNC_AUDIO
+1.8VALW 19 +1.8VALW 19 18
20 19 20 19
+1.8VS 20 +1.8VS
ON/OFFBTN# 21 25 ON/OFFBTN# 21 20

s:
B 28,32 ON/OFFBTN# 28,32 ON/OFFBTN# B
22 21 GND1 26 22 21
28,31 PWR_LED1# 22 GND2 28,31 PWR_LED1#
23 23 22
28,31 PWR_LED2# 23 28,31 PWR_LED2#
24 23

tp
+3VALW 24 +3VALW
24 25 24
ht HIGHSTAR_FC5AF241-2931H 26 25
+1.8VS
ME@ 27 26
28 27
+3VS
29 28 32
30 29 GND2 31
+5VS 30 GND1

HIGHS_FC5AF301-2931H

24Pin CONN ME@

change SP01001IF00 to SP01001YP00(30pin)0619

30Pin CONN

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2016/08/16 Deciphered Date 2017/08/15 IO CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
B
S350 ARE 1.0

Date: Sunday, January 19, 2020 Sheet 28 of 44

5 4 3 2 1
 5 4 3 2 1

+1.8VS
+1.8V_TPM
1A
RTPM17 2 @ 1 0_0402_5%
+1.8VALW

RTPM18 2 TPM@1 0_0402_5%

+3VALW +1.8V_TPM
D D

2
RTPM14 RTPM28
TPM@ @ RTPM28 stuff for NationZ
+1.8VS +1.8V_TPM 0_0603_5% 0_0603_5%
+1.8V_TPM

1
1

1
RTPM34 RTPM33
TPM@ TPM@
10K_0402_5% 10K_0402_5%
D754

2
2 1 1 1 1 2
2 1 TPM_SPI_PIRQ# CTPM1 CTPM2 CTPM3 CTPM4 CTPM5 CTPM6
8 PCH_SPI_PIRQ#
@ TPM@ 0.1U_0201_6.3V6-K 0.1U_0201_6.3V6-K TPM@ @
TPM@ 10U_0603_6.3V6M 4.7U_0402_6.3V6M TPM@ TPM@ 1U_0402_6.3V6K 10U_0603_6.3V6M
RB751V-40_SOD323-2 1 2 2 2 2 1
SCS00008K00

UTPM1

22

1
TPM@

NiC2

NiC1
VPS
C C
TPM_SPI_PIRQ# 18
SPI_PIRQ 3 TPM_GP2 RTPM26 2 TPM@ 1 10K_0402_5%
NiC6 +1.8V_TPM
4 TPM_PIN4 RTPM24 2 @ 1 0_0402_5%
NiC7 +1.8V_TPM
TPM_SPI_MOSI RTPM20 2 TPM@1 0_0402_5% TPM_SPI_MOSI_R 21 5
8 TPM_SPI_MOSI MOSI NiC8
TPM_SPI_MISO RTPM21 2 TPM@1 0_0402_5% TPM_SPI_MISO_R 24 10
8 TPM_SPI_MISO MISO NiC9 11
NiC10 12
NiC11 13
SPI_CS_R# 20 NiC12 14
SPI_CS NiC13 +1.8V_TPM
15

om
TPM_SPI_CLK RTPM22 2 TPM@1 0_0402_5% TPM_SPI_CLK_R 19 NiC14 16
8 TPM_SPI_CLK SPI_CLK NiC15 25
TPM_PLT_RST# 17 NiC16 26
+1.8V_TPM SPI_RST NiC17 27 TPM_PIN27 1
RTPM25 @ 2 10K_0402_5%
NiC18

.c
6 28
GPIO NiC19 31
NiC20
1

7
PP

ix
RTPM23
TPM@
10K_0402_5% 29 TPM_PIN29 PIN29 reserve for TPM MS low power mode

af
NiC21

1
30
NiC22
2

RTPM30

GND1

GND2
NiC3

NiC4

NiC5
TPM_PLT_RST#

in
@
B +5VALW 10K_0402_5% B

//v
2

23

32

33
ST33HTPH2E32AHB4_VQFN32_5X5 +1.8V_TPM
1

1TPM_PIN2
RTPM35
10K_0402_5%

s:

1
TPM@
RTPM32
2

RTPM36 0_0402_5%
@

tp
D
2 QTPM1A 10K_0402_5%
G DTPM1
2N7002KDWH_SOT363-6

2
TPM@
ht TPM_PIN29 2 1 PLT_RST#
S
1

2
3

D @
7,22,27 PLT_RST# 5 QTPM1B RB751V-40_SOD323-2
G 2N7002KDWH_SOT363-6 TPM@ SCS00008K00
TPM@
S
4

+1.8VALW +1.8V_TPM
2

A A
RTPM37 RTPM27
10K_0402_5% @
TPM@ 10K_0402_5%
Security Classification LC Future Center Secret Data Title
1

RTPM19 2 TPM@ 1 0_0402_5% SPI_CS_R#

8 SPI_CS#_TPM
Issued Date 2016/08/16 Deciphered Date 2017/08/15 TPM
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Size Document
Document Number
Number Rev
Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S350 ARE
Date:
Date: Sunday, January 19, 2020 Sheet
Sheet 29 of 44
5 4 3 2 1
 A B C D E F G H

SATA HDD Conn.

JHDD1 ME@
+5VS_HDD
10 11
R332 NO17@1 2 0_0201_5% SATA_PTX_R_DRX_P0 C66 NO17@1 2 0.01U_6.3V_K_X7R_0201 SATA_PTX_C_DRX_P0_CON 9 10 GND1
4 SATA_PTX_DRX_P0 9
R333 NO17@1 2 0_0201_5% SATA_PTX_R_DRX_N0 C67 NO17@1 2 0.01U_6.3V_K_X7R_0201 SATA_PTX_C_DRX_N0_CON 8 12
4 SATA_PTX_DRX_N0 8 GND2
7 1 1 1 1 1
R334 NO17@1 2 0_0201_5% SATA_PRX_R_DTX_N0 C68 NO17@1 2 0.01U_6.3V_K_X7R_0201 SATA_PRX_C_DTX_N0_CON 6 7 C74 C75 C76 C77 C78
1 4 SATA_PRX_DTX_N0 R335 NO17@1 2 0_0201_5% SATA_PRX_R_DTX_P0 C69 NO17@1 2 0.01U_6.3V_K_X7R_0201 SATA_PRX_C_DTX_P0_CON 5 6 1000P_0201_50V7-K 0.1u_0201_10V6K 33P_0402_50V8J 10U_0603_10V6K 33P_0402_50V8J
1
4 SATA_PRX_DTX_P0 4 5 EMC_NS@ RF_NS@ RF_NS@
3 4 2 2 2 2 2
2 3
1 2
1
EMC
HIGHS_FC5AF101-2931H
Need short +5VS_HDD
J3 @
1 2
+5VS 1 2
JUMP_43X79

SATA HDD Redriver(NEW ADD 20190614 ) +3VS

+3VS_SATA

R109 1 @ 2 0_0402_5%

+3VS_SATA

+3VS_SATA

2
RF1
2 17@ 2
1/20W_4.7K_5%_0201

Close APU U133

1
7 10
EN VDD1 20
SATA_PTX_DRX_P0 CF1 17@1 2 0.01U_6.3V_K_X7R_0201 SATA_PTX_C_DRX_P0 1 VDD2

om
SATA_PTX_DRX_N0 CF2 17@1 2 0.01U_6.3V_K_X7R_0201 SATA_PTX_C_DRX_N0 2 A_INP 6 REXT RF2 1 17@ 2 4.99K_0402_1%
A_INN REXT 16 DEW
SATA_PRX_DTX_P0 CF3 17@1 2 0.01U_6.3V_K_X7R_0201 SATA_PRX_C_DTX_P0 5 DEW
SATA_PRX_DTX_N0 CF4 17@1 2 0.01U_6.3V_K_X7R_0201 SATA_PRX_C_DTX_N0 4 B_OUTP 9 A_DE
B_OUTN A_DE 8 B_DE
A_EQ1 17 B_DE

.c
A_EQ2 18 A_EQ1 15 SATA_PTX_U_DRX_P0 CF5 17@1 2 0.01U_6.3V_K_X7R_0201 SATA_PTX_C_DRX_P0_CON
B_EQ1 19 A_EQ2 A_OUTP 14 SATA_PTX_U_DRX_N0 CF6 17@1 2 0.01U_6.3V_K_X7R_0201 SATA_PTX_C_DRX_N0_CON
B_EQ2 13 B_EQ1 A_OUTN

ix
B_EQ2 11 SATA_PRX_U_DTX_P0 CF7 17@1 2 0.01U_6.3V_K_X7R_0201 SATA_PRX_C_DTX_P0_CON
3 B_INP 12 SATA_PRX_U_DTX_N0 CF8 17@1 2 0.01U_6.3V_K_X7R_0201 SATA_PRX_C_DTX_N0_CON
21 GND1 B_INN

af
EPAD
PS8527C_TQFN20_4X4
17@

in
//v
s:
+3VS_SATA +3VS_SATA +3VS_SATA +3VS_SATA +3VS_SATA +3VS_SATA +3VS_SATA

tp
3 +3VS_SATA 3
2

2
R41
17@ 1/20W_4.7K_5%_0201
R43
17@ 1/20W_4.7K_5%_0201 17@
R47
1/20W_4.7K_5%_0201 @
R54
1/20W_4.7K_5%_0201 @
R57
1/20W_4.7K_5%_0201
ht @
R79
1/20W_4.7K_5%_0201 @
R36
1/20W_4.7K_5%_0201
1

1
A_EQ1 A_EQ2 B_EQ1 B_EQ2 A_DE B_DE DEW
1 1 1
2

2
17@ CF11 17@ CF9 17@ CF10
R44 R45 R46 R60 R78 R80 R81 0.01U_25V_K_X5R_0201 0.1U_25V_K_X5R_0201 0.1U_25V_K_X5R_0201
@ @ 17@ 1/20W_4.7K_5%_0201 17@ 1/20W_4.7K_5%_0201 @ @ @ 2 2 2
1/20W_4.7K_5%_0201 1/20W_4.7K_5%_0201 1/20W_4.7K_5%_0201 1/20W_4.7K_5%_0201 1/20W_4.7K_5%_0201
1

Close to pin 10. Close to pin 20.

Equalization level setting for Channel x(x=A/B), De-emphasis level setting for Channel x(x=A/B), De-emphasis widith adjustment,
internally tied to VDD/2 internally tied to VDD/2 internally pulled down
[x_EQ2, x_EQ1] == [x_DE] == [DEW] ==
L/M: for channel loss up to 2.4dB M: -3.5dB (default) M: for SATA3(default)
L/L: for channel loss up to 7.4dB L: 0dB L: for SATA3
L/H: for channel loss up to 14.4dB H: -6dB H: for SATA2
M/M: for channel loss up to 12.2dB (default)
M/L: for channel loss up to 9.4dB
M/H: for channel loss up to 13.3dB
H/M: for channel loss up to 6.2dB
H/L: for channel loss up to 11.2dB
H/H: for channel loss up to 5dB

Follow Vendor suggest

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 HDD CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S350 ARE
Date: Sunday, January 19, 2020 Sheet 30 of 44
A B C D E F G H
 5 4 3 2 1

+5VALW

RE1 1 @ 2 0_0603_SP
+3VL USB_ON# RE15 1 2 10K_0402_5%

+3VL_EC +3VL_EC_R +3VL_EC RE3 1 @ 2 1/10W_0_+-5%_0603

+3VALW +3VS
1 2 0_0603_SP
LE1 @
All capacitors close to EC +3VL_EC RPE5
EC_SMB_CK2 4 1 2.2K_0404_4P2R_5%

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K
CD@

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201
1 1
CE4 CE5 @1 @1 EC_SMB_DA2 3 2
1 1 1 1
0.1U_6.3V_K_X5R_0201 1000P 25V K X7R 0201
@
2 2
LE2 1 @ 2 0_0603_SP EC_AGND 2 2 2 2 2 2 AMD request SIC/SID pull high 1K

CE11
+3VL_EC_R
+3VL_EC

CE10
CE6

CE7

CE8

CE9
+1.8VALW
EC_AGND EC_SMB_CK1 RPE7 4 1 2.2K_0404_4P2R_5%
D follow L340 API EC_SMB_DA1 3 2 D

2
+3VS RE4371 1 @ 2 0_0603_SP RE4372
@ 0_0603_SP EC_SMB_CK3 RPE8 4 1 2.2K_0404_4P2R_5%
VCC:power supply of LPC EC_SMB_DA3 3 2
VSTBY_FSPI: power supply of SPI flash

1
UE1 +3VS

114
121

106

127
IT8227E-CX_LQFP128_16X16

11
26
50
92

74
ENBKL RE4324 1@ 2 100K_0402_5%
RE1000 1 @ 2 0_0402_5% EC_LPC_AD0 10 87 IT10 1 @ SERIRQ RE4354 1@ 2 10K_0402_5%
8 LPC_AD0

VSTBY(PLL)
AVCC
VCC

VFSPI
VSTBY1
VSTBY2
VSTBY3
VSTBY4
VSTBY5
EC to APU/LPC RE1001 1 @ 2 0_0402_5% EC_LPC_AD1 9 EIO0/LAD0/GPM0(3) SMCLK0/GPF2 88 IT11 1 @ EC_FAN_PWM1 RE4327 1@ 2 10K_0402_5%
8 LPC_AD1 EC_LPC_AD2 EIO1/LAD1/GPM1(3) SMDAT0/GPF3 EC_SMB_CK1 EC_FAN_SPEED1
RE1002 1 2 0_0402_5% 8 115 1 2 10K_0402_5%
8
8
LPC_AD2
LPC_AD3 RE1003 1
@
@ 2 0_0402_5% EC_LPC_AD3 7 EIO2/LAD2/GPM2(3)
EIO3/LAD3/GPM3(3)
SM BUS SMCLK1/GPC1
SMDAT1/GPC2
116 EC_SMB_DA1 EC_SMB_CK1
EC_SMB_DA1
38,39
38,39
Charger IC, Battery RE4328

APU_LPC_RST# 22 117 EC_SMB_CK2 EC_TP_OFF# 1@ 2 10K_0402_5%

APU,Thermal sensor
GPD2 must be pulled down.(HW strapping) RE4358
8,13 APU_LPC_RST# CLK_PCI_EC_R ERST#/LPCRST#/GPD2 PECI/SMCLK2/GPF6(3) EC_SMB_DA2 EC_SMB_CK2 6,25
LPC CLK 33M RE31 1 @ 2 0_0402_5% 13 118
8 CLK_PCI_EC LPC_FRAME#_R ESCK/LPCCLK/GPM4(3) SMDAT2/PECIRQT#/GPF7(3) EC_SMB_DA2 6,25
cycle start RE32 1 @ 2 0_0402_5% 6
+3VL_EC 8 LPC_FRAME# ECS#/LFRAME#/GPM5(3)
+3VALW

DE2 @1 2 P_APU_OCPL_10 126

43 P_APU_OCPL_10 GA20/GPB5(3) USM_EN_5V_R RE336 2
Interrupt request signal SERIRQ 5 85 @ 1 0_0402_5%
8,13 SERIRQ EC_SMI# ALERT#/SERIRQ/GPM6(3) PS2CLK0/CEC/TMB0/GPF0 PBTN_OUT# USM_EN_5V 40 EC_PCIE_WAKE#
System Management Interrupt 15 LPC 86 RE4331 1@ 2 10K_0402_5%
RB751V-40_SOD323-2 7 EC_SMI# EC_SCI# PLTRST#/ECSMI#/GPD4(3) PS2DAT0/TMB1/GPF1 FPR_GPIO_SCL_EC PBTN_OUT# 7 WLAN_WAKE#
System Control Interrupt 23 PS/2 89 Sqe: EC to APU Start-up trigger signal RE4332 1@ 2 10K_0402_5%
8 EC_SCI# ECSCI#/GPD3 PS2CLK2/GPF4 FPR_GPIO_SCL_EC 32
RE8 1 2 100K_0402_5% WRST# 14 90 ENBKL EC to APU PCIE wake up
WRST# PS2DAT2/GPF5 ENBKL 17 +3VL_EC

IT8227E-CX
KBRST# 4 APU to EC Enable Backlight
KB Reset Signal(SWUC)
8 KBRST# KBRST#/GPB6(3)
1
GPG2 RE4351 1 2 100K_0402_5%
CE12 24 PW R_LED_WIT# Sink 16/actual 5mA white

LQFP128
1U_0402_6.3V6K PW M0/GPA0 25 PW R_LED1# PW R_LED_WIT# 32 Sink 16/actual 5mA white LID_SW# 1 2 100K_0402_5%
RE4323
2 PW M1/GPA1 28 PW R_LED2# PW R_LED1# 28
FP Green LED L/ON H/OFF
113 PW M2/GPA2 29 EC_BEEP PW R_LED2# 28
EC_BEEP 28 SUSP# RE18 1 @ 2 100K_0402_5%
EC_MUTE# 123 CRX0/GPC0 PW M3/GPA3 30 BATT_CHG_LED#
28 EC_MUTE# CTX0/TMA0/GPB2(3) CIR SMCLK5/PWM4/GPA4 BATT_LOW _LED# BATT_CHG_LED# 32
Speaker sound
Sink 8/actual 5mA white EC_ON_5V
31 RE72 1 2 100K_0402_5%
Mute Audio codec speaker out SMDAT5/PWM5/GPA5 BATT_LOW _LED# 32 Sink 8/actual 5mA amber
CAPS_LED# RE73 1 2 100K_0402_5%
H_PROCHOT#_EC
PWM @
underclocking EC to APU 80
RE342 @1 2 0_0402_5% 119 DAC4/DCD0#/GPJ4(3) 47 EC_FAN_SPEED1 FAN Speed detection NUM_LED# RE74 1 @ 2 100K_0402_5%
11 EC_RTCRST#_ON EC_VR_ON DSR0#/GPG6 TACH0A/GPD6(3) EC_TS_ON EC_FAN_SPEED1 26
C 33 48 Touch screen ON C
43 EC_VR_ON GINT/CTS0#/GPD5 TACH1A/TMA1/GPD7(3) EC_TS_ON 17 PIMC_PW R_EN RE4370 1
EC control RTC reset 2 100K_0402_5%
Sqe: Vcore PMIC(RT3662) EN 0_75VALW _EN 81 120 WLAN_WAKE#_R RE330 2 @ 1 0_0402_5% WLAN WAKE to EC
41 0_75VALW _EN DAC5/RIG0#/GPJ5(3) TMRI0/GPC4(3) WLAN_WAKE# 27 EC_TP_EN#
124 SUSP# RE4374 1 TP_W@ 2 100K_0402_5%
EC_TX TMRI1/GPC6(3) SUSP# 33,41,42 EC --> LV5028 EN VTT/0.9VS
EC to USB Debug/Debug card 17 Sqe: EN S0 POWER
20,27 EC_TX EC_RX TXD/SOUT0/LPCPD#/GPE6 EC --> LV5083 EN 3/5VS
16
20,27 EC_RX

om
RXD/SIN0/PWUREQ#/BBO/SMCLK2ALT/GPC7(3)
ADC:Adapter Current Output ADP_I 71 107 EC_ON_5V_R RE335 2 @ 1 0_0402_5% Sqe: System PMIC&5VALW Power EN 0_75VALW _EN RE4363 1 2 100K_0402_5%
Sqe: System PMIC(LV5028) +2.5V ENABLE 2_5VEN RE4353391 ADP_I
@ 2 0_0402_5% 72 ADC5/DCD1#/GPI5(3) GPE4 18 PM_SLP_S3# EC_ON_5V 40
41 2_5VEN ADC6/DSR1#/GPI6(3) UART port WAKE UP RI1#/GPD0(3) EC_ON_3V_R PM_SLP_S3# 7 Sqe: APU-->EC S3 POWER ON
USM_EN_5V
ADC:Total System power PSYS 73 21 RE4315 2 @ 1 0_0402_5% Sqe: 3VALW Power EN RE4366 1 @ 2 100K_0402_5%
39 PSYS USB_ON# ADC7/CTS1#/GPI7(3) RI2#/GPD1 EC_ON_3V#
USB Power switch SY6288D20AAC EN (L Active) 35
20,21 USB_ON# EC_TP_OFF# RTS1#/GPE5 USM_EN_3V
LID Close event (Active Low) 34 RE4362 1 @ 2 100K_0402_5%
32 EC_TP_OFF# PW M7/RIG1#/GPA7 USM_EN_3V_R
Sqe: EN +1.2V SYSON 122 112 RE331 2 @ 1 0_0402_5%
USM_EN_3V 40

.c
EC_SMB_DA3 95 DTR1#/SBUSY/GPG1/ID7 RING#/PW RFAIL#/CK32KOUT/LPCRST#/GPB7 110 ON/OFF_R RE326 2 1 0_0402_5% 2_5VEN 1 2 100K_0402_5%
PMIC 41
41
EC_SMB_DA3
EC_SMB_CK3
EC_SMB_CK3 94 CTX1/SOUT1/GPH2/SMDAT3/ID2
CRX1/SIN1/SMCLK3/GPH1/ID1
PW RSW/GPB3
GPB4
111 APU_THERMTRIP#_R RE328 2
@
@ 1 0_0402_5%
ON/OFF 32
APU_THERMTRIP# 6
Sqe: power button to EC start-up signal
thermal protection
RE4357

109 LID_SW# LID Switch output -->EC

EC_SPI_CLK GPB1 LID_SW# 32
Serial Flash Clock(Mirror code) 105 108 ACPRN Sqe: AC IN -->EC
8 EC_SPI_CLK

ix
Serial Flash Chip Enable(Mirror code) EC_SPI_CS1# 101 FSCK GPB0 GPG2 RE4355 1 @ 2 100K_0402_5%
8 EC_SPI_CS1# EC_SPI_SI FSCE#
Serial Flash In(Mirror code) 102 EXTERNAL SERIAL FLASH
8 EC_SPI_SI EC_SPI_SO FMOSI FPR_DELINK_EC 3V_WLAN_EN
Serial Flash Out(Mirror code) 103 66 ADC: Reserver thermal sensor RE4330 1 @ 2 10K_0402_5%
8 EC_SPI_SO FMISO ADC0/GPI0(3) BATT_TEMP FPR_DELINK_EC 32
KSO[0..17] 67

af
32 KSO[0..17] BATT_TEMP 38,39 BATT IN -->EC
KSO16 56 ADC1/GPI1(3) 68 NTC_V2 BKOFF# RE4334 1 2 10K_0402_5%
NTC_V2 25 ADC: NTC Near Air outlet
KSO17 57 KSO16/SMOSI/GPC3(3) ADC2/GPI2(3) 69
FAN Speed Contrl EC_FAN_PWM1 32 KSO17/SMISO/GPC5(3) ADC3/GPI3(3) 70 IDCHG_R RE4361 2 @ 1 0_0402_5% EC_VR_ON RE4336 1 2 100K_0402_5%
26 EC_FAN_PWM1 IDCHG 39 ADC:Buffered discharge current.
PW M6/SSCK/GPA6 ADC4/GPI4(3)

in
GPG2 100 PIMC_PWR_EN EC_RSMRST# 1 2 100K_0402_5%
GPG2 must be pulled up.(HW strapping)
SSCE0#/GPG2 A/D D/A PIMC_PW R_EN 41 WLAN P/ SW SY6288C20AAC EN (H Active) RE4339 @
GPG0 reserved test point(HuiH) @ 1IT9 125 SPI ENABLE
SSCE1#/GPG0 76 EC_TP_EN#_R RE4373 2 TP_W@ 1 0_0402_5% SUSP# RE4337 1 2 100K_0402_5%
TACH2A/GPJ0 EC_TP_EN# 32 Sys PMIC LV5028 '+0.9VS power OK-->EC
SYSON RE99 2 @ 1 0_0402_5% KSO0 36 77 PM_SLP_S5# SYSON RE4338 1 2 100K_0402_5%

//v
1_2VEN 41 KSO0/PD0 TACH2B/GPJ1 PM_SLP_S5# 7,13 Sqe: APU-->EC S5 POWER ON
KSO1 37 78 VR_PWRGD Sqe: VDDCR/SOC(RT3662) Core PWR OK -->EC
KSO1/PD1 DAC2/TACH0B/GPJ2(3) VR_PWRGD 43
KSO2 38 79 CE29 2 1 0.1U_6.3V_K_X5R_0201
KSO3 39 KSO2/PD2 DAC3/TACH1B/GPJ3(3) APU3VALW _EN 33
KSO3/PD3 EC -->DCDC(SY8386) '+3VALW disable
KSO4 40
KSO4/PD4 For EMC EMC_NS@
KSO5 41

s:
KSO6 42 KSO5/PD5 follow L340 API
KSO7 43 KSO6/PD6
KSO8 44 KSO7/PD7
S350ADA 0~17 KSO9 45 KSO8/ACK#

tp
KSO10 46 KSO9/BUSY EMC_NS@ EMC_NS@
KSO11 51 KSO10/PE 2 APUALW_PWRGD CLK_PCI_EC RE103 1 2 10_0402_5% CE48 1 2 10P_0201_25V8G
KSO11/ERR# GPJ7 AC_PRESENT APUALW_PWRGD 41
KSO12 52 CLOCK 128
KSO12/SLCT GPJ6 AC_PRESENT 7
KSO13 53 ht
B RE324 1 @ 2 0_0402_5% KSO14 54 KSO13 APU_LPC_RST# CE49 EMC_NS@ 1 2 220P_25V_K_X7R_0201 B
39 VR_HOT# H_PROCHOT# 6,41 KSO14
KSO15 55 84 NUM_LED#
KSO15 KBMX EGCLK/GPE3 EC_APU_ALWEN_R NUM_LED# 32 Sink 16/actual 12mA
KSI[0..7] 83 RE11 2 @ 1 0_0402_5% Sqe: System PMIC LV5028 0.9VS/1.8VALW EN
EGCS#/GPE2
2

H_PROCHOT#_EC RE325 1 @ 2 0_0402_5% 32 KSI[0..7] 82 EC_PCIE_WAKE# EC_APU_ALWEN 41 BATT_TEMP CE31 1 @ 2 100P_50V_J_NPO_0201

1 EGAD/GPE1 EC_PCIE_WAKE# 7,27
KSI0 58 EC-->FP SYS PWR Status
RE323 CE43 KSI1 59 KSI0/STB# APU_THERMTRIP# CE44 1 @ 2 100P_50V_J_NPO_0201
100_0402_5% 47P_25V_J_NPO_0201 KSI2 60 KSI1/AFD# 19 FPR_GPIO_AL0_EC
2 KSI2/INIT# SMCLK4/L80HLAT/BAO/GPE0 FPR_GPIO_AL0_EC 32 Power key shielding L/enable H/disable KEY
@ EMC_NS@ KSI3 61 20 FPR_PWR_EN
KSI3/SLIN# SMDAT4/L80LLAT/GPE7 FPR_PWR_EN 32
1 1

KSI4 62 GPIO @
D KSI5 63 KSI4 3 3V_WLAN_EN_R
2 @
RE4308 1 0_0402_5% VR_PWRGD CE46 1 2 0.01U_6.3V_K_X7R_0201
KSI5 GPH7 3V_WLAN_EN 27 mcu out pin
H_PROCHOT#_EC 2 @ KSI6 64 99 NOVO#
KSI6 ID6/GPH6 NOVO# 32 NOVO botton to EC ，start up
G QE3 KSI7 65 98 BKOFF# EC control backlight on/off APUALW_PWRGD CE50 1 @ 2 0.1U_6.3V_K_X5R_0201
KSI7 ID5/GPH5 CAPS_LED# BKOFF# 17
L2N7002KWT1G_SOT323-3 97 Sink 16/actual 12mA
ID4/GPH4 EC_SYS_PWRGD CAPS_LED# 32
S 96 Sqe: EC-->APU ALL POWER OK ON/OFF CE57 1 @ 2 0.1U_6.3V_K_X5R_0201
VCORE
ID3/GPH3 EC_SYS_PWRGD 7
3

93
AVSS
VSS1
VSS2
VSS3
VSS4
VSS5

CLKRUN#/ID0/GPH0 EC_RSMRST#_R RE4350 1 @ 2 0_0402_5%

EC_RSMRST# 7
Sqe: Standby Power Supply Voltage Good Signal
1
27
49
91
104

75

12
VCOREVCC

+3VALW
RPE9
AC IN +3VL_EC

1 4 KSO1 EC_AGND 2
Close EC ACPRN RE25 1 2 100K_0402_5%
2 3 KSO2 RE26 1 @ 2 0_0402_5%
ACIN 39
CE3
0.1U_6.3V_K_X5R_0201 DE1 22 11 @ RB751VM-40TE-17_UMD2M2
10K_0404_4P2R_5% 1
@
+5VALW 1 2 CE14 100P_50V_J_NPO_0201
+3VL_EC +3VALW
RPE9 Reserve for vender suggest 5/30
@
1

2
+3VL RE101
100K_0402_5% RE4340
100K_0201_5% @ RE4346
1

100K_0402_5%
2

RE100 EC_ON_3V 40

1
SSM3K15AMFV_2-1L1B

100K_0402_5%
1

@ 1 IT12 KSI6 EC_APU_ALWEN

2

2
A @ 1 IT13 KSI7 A

1M_0402_1%
QE4

EC_ON_3V# 2

RE4368
Place Bot @ RE4345
100K_0402_5%
3

1
@
Reserve SMBUS Debug
RE102 1 2 0_0402_5%

Security Classification LC Future Center Secret Data Title

Issued Date 2016/08/16 Deciphered Date 2017/08/15 EC ITE8227 LQFP128
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S350 ARE
Date: Sunday, January 19, 2020 Sheet 31 of 44
5 4 3 2 1
 5 4 3 2 1

ON/OFF switch
+3VL

2
R82
100K_0402_5%

1
NOVO_BTN# R261 2 @ 1 0_0402_5% NOVO#
28 NOVO_BTN# NOVO# 31

D D

+3VL

LID switch

2
R114
100K_0402_5%

1
ON/OFFBTN# R119 2 @ 1 0_0402_5% ON/OFF 1@
28 ON/OFFBTN# ON/OFF 31
C1104
U14 100P_0201_25V8J
from IO/B connector J5 1 2 @ 1
GND 2
1
SHORT PADS C1105 3 LID_SW#
OUTPUT LID_SW# 31
0.01U_6.3V_K_X7R_0201 @
J6 1 2 @
+3VL R264 2 @ 1 0_0402_5% 2 +VCC_LID 2
SHORT PADS VCC
AH9247-W-7_SC59-3

POWER LED
K/B Connector KSI[0..7]
KSI[0..7] 31 31 BATT_LOW_LED#
BATT_LOW_LED# LED2 1 2 R143 1 2 470_0402_5% +3VALW
KSO[0..17] KSI1 R319 1S350KB@ 2 0_0402_5% L-C192JFCT-LCFC_SUPER_AMBER
KSO[0..17] 31

1
KSO15 R320 1S350KB@ 2 0_0402_5%
D18

1
AZ5725-01F.R7GR_DFN1006P2X2
EMC_NS@ KSO15_R R341 1 S145KB@2 0_0402_5% JKB1 ME@ EMC_NS@
PWR_CAPS_LED C133 1 2 100P_0201_25V8J ON/OFFBTN# R304 1 S145KB@2 0_0402_5% KSI1_R 1
PWR_LED_WIT# R274 1 S145KB@2 200_0402_1% KSO15_R 2 1
AZ5123-01F.R7GR_DFN1006P2X2

PWR_LED#_R 3 2

2
NUM_LED# NUM_LED#_R 3
1

D25 R279 1 2 200_0402_1% 4

31 NUM_LED# 4

2
KSO17 R281 2 @ 1 0_0402_5% KSO17_R 5
1

KSO16 R280 2 @ 1 0_0402_5% KSO16_R 6 5

KSI1 7 6
11/30 Common MB for 14/15 KSI7 8 7 BATT_CHG_LED# LED3 1 2 R144 1 2 470_0402_5%
8 31 BATT_CHG_LED# +3VALW
KSI6 9
KSO9 10 9
2

EMC_NS@ L-C192WDT-LCFC_WHITE
CAPS_LED# C117 1 2 100P_0201_25V8J S145KB@ KSI4 11 10
11
2

1
KSI5 12
C NUM_LED#_R C118 1 2 100P_0201_25V8J KSO0 13 12 D19 C

1
KSI2 14 13 AZ5725-01F.R7GR_DFN1006P2X2
EMC_15_NS@ KSI3 15 14 EMC_NS@
KSO5 16 15
KSO1 17 16
17

om
KSI0 18

2
KSO2 19 18
19

2
CAPS_LED#_R NUM_LED#_R PWR_LED#_R KSO4 20
KSO7 21 20 PWR_LED_WIT#
KSO8 22 21
KSO6 23 22
KSO3 24 23 PWR_LED_WIT# LED4 1 2 R4672 1 2 470_0402_5%
24 31 PWR_LED_WIT# +3VALW
1

1
KSO12 25
25

.c
D22 D23 D46 KSO13 26 L-C192WDT-LCFC_WHITE D16
1

1
AZ5123-01F.R7GR_DFN1006P2X2 AZ5123-01F.R7GR_DFN1006P2X2 AZ5123-01F.R7GR_DFN1006P2X2 KSO14 27 26 AZ5725-01F.R7GR_DFN1006P2X2
EMC@ EMC_15@ EMC_NS@ KSO11 28 27 EMC_NS@
KSO10 29 28
KSO15 30 29

ix
R275 1 2 200_0402_1% CAPS_LED#_R 31 30 34
2

2
31 CAPS_LED# PWR_CAPS_LED 32 31 GND2 33
+3VALW R84 1 @ 2 0_0402_5%
32 GND1
2

2
HIGHS_FC8AR321-3160-1H

af
For EMC
11/30 EMC request Change to stuff at SIT

in
Finger Print Connector +3VL +3VALW FP_PWR
+3VS TP_PWR
TP/B Connector

//v
R306 2 @ 1 0_0402_5% R141 1 2 0_0402_5%

R305 2 @ 1 0_0402_5%
Support PTP
1
+3VL JTP2

s:
+3VALW LP2301ALT1G_SOT23-3 EC_TP_OFF#_R 1

C114
0.1U_0201_6.3V6-K
ME@
LP2301ALT1G_SOT23-3 TP_INT# 2 1
2 2
1

Q24 3 1 TP_W@ 3

D
R344 Q160 3 1 R346 1 @ 2 0_0603_SP 4 3
S

0.01U_0201_10V6K
1/20W_200K_5%_0201 FP@ 5

tp
1 1 1 5
TP_I2C3_SDA
1

FP@ C134 C135 C185 6

TP_W@
G
6

2
FP@ 0.1U_0201_6.3V6-K 0.1u_0201_10V6K TP_I2C3_SCL 7
G

7
2

0.047U_0402_16V_X7R_0402 @ TP_W@ 8
2 2 2 TP_PWR 8
2

C186
1 @ 2 1 @ 2 FPR_PWR_EN ht EC_TP_EN# R148 1 TP_W@ 2 9
31 EC_TP_EN# 10 GND1
R435 100K_0402_5%
GND2
1

R348 0_0402_5% 1 1
0_0402_5% 1 C187 C188
B
FP@ R347 C132 FP_PWR 0.01U_0201_25V6-K 0.1u_0201_10V6K HIGHS_FC5AF081-2931H
B

100K_0402_5% 0.1U_0201_6.3V6-K TP_W@ TP_W@

@ 2 2
2 8 Pin Connector
2

FPR_PWR_EN#
1

R415
330_0402_1%
1

Q161 FP_PWR TP_PWR

SSM3K15AMFV_2-1L1B
2

FPR_PWR_EN 1 @ 2 2 FP@
31 FPR_PWR_EN
1

R343 Q192 JTP1

3

0_0402_5% R313 2 @ 1 0_0402_5% EC_TP_OFF#_R 1 ME@

31 EC_TP_OFF# TP_INT# 1
2

FP@ R342 1 R314 1 2 0_0402_5% 2

7 PCH_TP_INT#
10K_0201_5%

100K_0402_5% 2 3 2
R149

TP_I2C3_SDA_R TP_I2C3_SDA 3
2

C2061 FP@ R4681 1 @ 2 0_0402_5% 4

TP_W@

4
2

SSM3K15AMFV_2-1L1B 0.1U_0201_6.3V6-K TP_I2C3_SCL_R R4680 1 @ 2 0_0402_5% TP_I2C3_SCL 5

2 5
3

6
TP_PWR 6
1

R311 2 @ 1 0_0402_5%

100P_0201_25V8J

100P_0201_25V8J
JFP2 TP_INT# 3 1PCH_TP_INT1# 7
PCH_TP_INT1# 7 1 1 GND1
10 8
S

ME@
L4310 9 GND2 GND2
TP_W@ EMC_NS@ EMC_NS@
USB20_N7 1 2 GND1 Q25
9 USB20_N7 HIGHS_FC5AF061-2931H
1 2 8 L2N7002KWT1G_SOT323-3 2 2

C115

C116
USB20_N7_CONN 7 8
USB20_P7 4 3 USB20_P7_CONN 6 7
9 USB20_P7 4 3 5 6
FPR_DELINK_EC R307 1 @ 2 0_0201_5% FPR_DELINK_R 4 5 TP_I2C3_SCL
EXC24CH900U_4P 31 FPR_DELINK_EC FPR_GPIO_AL0_EC R308 1 @ 2 0_0201_5% FPR_GPIO_AL0_R 3 4 TP_I2C3_SDA Colay S145API non PTP
31 FPR_GPIO_AL0_EC FPR_RESETN FPR_RESETN_R 2 3
EMC_NS@ 8 FPR_RESETN R309 1 @ 2 0_0201_5%
FPR_GPIO_SCL_EC FPR_GPIO_SCL_R 2
3

R312 2 @ 1 0_0402_5% R310 1 @ 2 0_0201_5% 1

31 FPR_GPIO_SCL_EC 1 D100
FPR_DELINK_R FPR_GPIO_AL0_R HIGHS_FC5AF081-2931H
EMC_NS@
1

TP_PWR
R345 TP_PWR
1

100K_0201_5%
@ R412

2
1
1/20W_47K_1%_0201
2

FP@ RPC20
2.2K_0404_4P2R_5%
2

AZC199-02S.R7G_SOT23-3
1

5
for EMC TP issue 1112

3
4
TP_I2C3_SDA_R R315 2 @ 1 0_0402_5% 3 4 TP_I2C3_SDA
7,13 TP_I2C3_SDA_R

S
D
+3VS Q159B

2
2N7002KDWH_SOT363-6

G
A R413 @ USB20_N7_CONN FP_EMC@ D5106 A
1 2FPR_DELINK_R FPR_DELINK_R 10 1 FPR_DELINK_R
NC1 Line-1
FP_PWR 1/20W_2.2K_5%_0201 USB20_P7_CONN FPR_GPIO_AL0_R 9 2 FPR_GPIO_AL0_R TP_I2C3_SCL_R R316 2 @ 1 0_0402_5% 6 1 TP_I2C3_SCL
NC2 Line-2 7,13 TP_I2C3_SCL_R
S
D

FPR_RESETN_R 7 4 FPR_RESETN_R Q159A

R329 NC3 Line-3
1

D14 2N7002KDWH_SOT363-6
2 1 FPR_RESETN_R FPR_GPIO_SCL_R 6 5 FPR_GPIO_SCL_R
NC4 Line-4
3
1/20W_4.7K_5%_0201 GND1
2

@ 8
R331 GND2
1/20W_4.7K_5%_0201 @ AZ1143-04F-R7G_DFN2510P10E10
3

FP_EMC@
AZ5515-02FPR7GR_DFN1006P3X
1

Security Classification LC Future Center Secret Data Title

Issued Date 2016/08/16 Deciphered Date 2017/08/15 KBD/PWR/IO/LED/TP Conn.

SDV Reserved THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Size Document
Document Number
Number Rev
Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S350 ARE
Date:
Date: Sunday, January 19, 2020 Sheet
Sheet 32 of 44
5 4 3 2 1
 A B C D E

Load Switch +3VS, C173 --> 2.74ms

+5VLP +5VALW
+5VALW To +5VS +5VS, C176 --> 2.03ms
+3VALW To +3VS VIN 5V and 3.3V (VBIAS=5V), IMAX(per channel)=6A, Rds=16mohm

1
U13 Need Short
R156 R157 15
100K_0402_5% 100K_0402_5% +5VALW Thermal Pad +5VS
@ 7 8 J12 @
R64 1 @ 2 0_0402_5% 3VSON 6 IN2_2 OUT2_1 9 +5VS_LS 1 2
IN2_1 OUT2_2 1 2

2
1 1
SUSP 1 1 5VSON 5 10 C176 1 2 1000P_0201_50V7-K JUMP_43X79 1 1
14,19 SUSP EN2 CT2
C177 C3916 C174 C3917
1U_0402_6.3V6K .01U_0402_16V7-K 4 11 0.1u_0201_10V6K 0.01U_0201_10V6K
+5VALW VBIAS GND
@ @ @ @
SUSP# R27 1 @ 2 0_0402_5% 5VSON +3VALW 2 2 3VSON 3 12 C173 1 2 2200P_0402_25V7-K 2 2 +3VS
EN1 CT1

1
D J11 @
SUSP# 2 QX5 2 13 +3VS_LS 1 2
31,41,42 SUSP# IN1_2 OUT1_1 14 1 2
G L2N7002KWT1G_SOT323-3 1 1 1
IN1_1 OUT1_2 JUMP_43X79
1 1
S C180 C179 C178 G2898KD1U_TDFN14P_2X3 C175

3
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K Need Short 0.1u_0201_10V6K
2 2 @ @
2 2
Change the main source to SA000067600 (GMT) 7/16

+3VALW +3VALW_APU
For DisCharge
+3VALW to +3VALW_APU
CS34
+3VS +5VS @
R340 1 @ 2 0_0603_SP +5VS 1 2 +3VS

2
+3VL 0.1u_0201_10V6K 2

LP2301ALT1G_SOT23-3

1
@
Q29 3 1 1 2 R940 R941 +5VS

D
1

R339 470_0603_5% 470_0603_5%

1/2W_0.01_+-1%_0603_50PPM/C @ 1
@ R337 CS24

G
2

2
100K_0402_5% @ 0.1u_0201_10V6K
@ @
R158
2

@ 2

om
1 2 APU3VALW_EN

1
D @ D
1

1 4.7K_0402_5% Q158 2 SUSP Q165 2 SUSP

Q17 C131 2N7002KW_SOT323-3 G 2N7002KW_SOT323-3 G
SSM3K15AMFV_2-1L1B 0.1U_0201_6.3V6-K
APU3VALW_EN 1 2 2

.c
31 APU3VALW_EN @ @ @ S S

3
2 +3VALW
@
R336
3
1

ix
0_0402_5% 1
CS43
@ R164 @ 0.1U_0201_6.3V6-K

af
100K_0402_5%
2
2

in
//v
3 3

s:
AONS32314

tp
VDS=30V VGS=20V, ID=32A,
+0.75VALW QX3 +0.75VS +/- 5% 1.5A Rds=8.7mohm @ VGS=10V
+/- 2% AON6324_DFN8-5
VGS(th)=2.25V Max ht
1
2 1 1
0.01U_6.3V_K_X7R_0201

1 5 3 CX5
CX3 CX4 1U_0402_6.3V6K
10U_0603_6.3V6M 10U_0603_6.3V6M
2 2
1

@ 1 1
4

2 CX6 CX7 RX11

0.1U_0201_6.3V6-K 470_0603_5%
@ @ @
2 2
+5VALW
2

RX12 RX13 RX14

+0.75VS_GATE_R 2 @ 1 2 @ 1 0.75VS_GATE1 2 10K_0402_5%

0_0402_5% 0_0402_5%
1

4 D D 4
1
CX8 RX15 2 QX2 SUSP 2 QX4
0.01U_0201_25V6-K 1M_0402_5% G L2N7002KWT1G_SOT323-3 G L2N7002KWT1G_SOT323-3
@
2 S S
2

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/15 Deciphered Date 2013/08/15 DC V TO VS INTERFACE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S350 ARE
Date: Sunday, January 19, 2020 Sheet 33 of 44
A B C D E
 5 4 3 2 1

Hole
PCB Fedical Mark PAD
H2 SO-DIMM Shielding
HOLEA
FD4901 FD4902 FD4903 FD4904 FD4905 FD4906

SH1 SH2 SH5 SH6

1
SHIELDING_SUL-35A2M_9P2X3P3_1P

1
SHIELDING_SUL-35A2M_9P2X3P3_1P SHIELDING_SUL-35A2M_9P2X3P3_1P SHIELDING_SUL-35A2M_9P2X3P3_1P

PAD_C10P0D8P0

D D

1
1

1
H4 H6 H7 H8
HOLEA HOLEA HOLEA HOLEA
1

1
SH8
SHIELDING_SUL-35A2M_9P2X3P3_1P
PAD_CT7P0B6P0D3P2 PAD_CT7P0B6P0D3P2 PAD_CT7P0B6P0D3P2 PAD_CT7P0B6P0D3P2

H9 H10

1
HOLEA HOLEA

1
1

PAD_C7P0D4P0 PAD_C7P0D4P0
H17 H18
HOLEA HOLEA

H11 H12 H13

HOLEA HOLEA HOLEA

1
C PAD_O2P5X3P0D2P5X3P0N PAD_O2P5X3P0D2P5X3P0N Memory Down Shielding C
1

om
PAD_C7P0D2P8 PAD_C7P0D2P8 PAD_C7P0D2P8
SH9 SH10 SH11 SH12
SHIELDING_SUL-35A2M_9P2X3P3_1P SHIELDING_SUL-35A2M_9P2X3P3_1P SHIELDING_SUL-35A2M_9P2X3P3_1P SHIELDING_SUL-35A2M_9P2X3P3_1P
H14
HOLEA

.c
1

ix
1

1
PAD_C7P0D2P4

1
af
H15 H16

in
HOLEA HOLEA

//v
1

PAD_CT7P0B10P0D4P0 PAD_CT7P0B10P0D4P0

s:
tp
B
ht B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 Hole

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
S350 ARE 1.0

Date: Sunday, January 19, 2020 Sheet 34 of 44

5 4 3 2 1
 5 4 3 2 1

UC1 UC1 UC1

RC35 14MB@ RC36 14MB@

4700U 4500U
4300U
2K_0402_5% 2K_0402_5%
RYZEN 7 100-000000083-00 2G
R7@
RYZEN 5 100-000000084-00 2.375G
R5@
RYZEN 3 100-000000085-00 2.7G
R3@ check ok
SD02820018J SD02820018J SA0000AHU20 SA0000AHX20 SA0000AHW20
D
APU type D
N N
14' Mainboard N N N

RC35 15MB@ RC43 15MB@ ZZZ9 DRAM_S4G@ ZZZ2 DRAM_M4G@ ZZZ7 DRAM_H4G@

2K_0402_5% 10K_0402_5% Samsung Micron Hynix check ok

SD02820018J SD02810028J X7649312001 X7649312002 X7649412001
DRAM X76 BOM
N N
15' Mainboard N N N

RC42 17MB@ RC36 17MB@ UD1 MD_H8Gb@ UD2 MD_H8Gb@ UD3 MD_H8Gb@ UD4 MD_H8Gb@ RC44 MD_H8Gb@ RC41 MD_H8Gb@ RC45 MD_H8Gb@ RC46 MD_H8Gb@

10K_0402_5%
SD02810028J
2K_0402_5%
SD02820018J check ok H5AN8G6NCJR-XNC
SA0000AC710
H5AN8G6NCJR-XNC
SA0000AC710
H5AN8G6NCJR-XNC
SA0000AC710
H5AN8G6NCJR-XNC
SA0000AC710
10K_0402_5%
SD02810028J
2K_0402_5%
SD02820018J
10K_0402_5%
SD02810028J
2K_0402_5%
SD02820018J
N N
17' Mainboard N N N N
memory particles
N
matched resistance
N N
DRAM_Hynix
N
4G check ok

UD1 MD_M8Gb@ UD2 MD_M8Gb@ UD3 MD_M8Gb@ UD4 MD_M8Gb@ RC44 MD_M8Gb@ RC41 MD_M8Gb@ RC45 MD_M8Gb@ RC39 MD_M8Gb@

MT40A512M16TB-062E:J MT40A512M16TB-062E:J MT40A512M16TB-062E:J MT40A512M16TB-062E:J 10K_0402_5% 2K_0402_5% 10K_0402_5% 10K_0402_5%

SA00009R510 SA00009R510 SA00009R510 SA00009R510 SD02810028J SD02820018J SD02810028J SD02810028J
C N N N N
memory particles
N
matched resistance
N N
DRAM_Micron
N
4G check ok C

om
RC44 DIMM_ONLY@ RC41 DIMM_ONLY@ RC38 DIMM_ONLY@ RC46 DIMM_ONLY@

.c
10K_0402_5% 2K_0402_5% 10K_0402_5% 2K_0402_5%
SD02810028J SD02820018J SD02810028J SD02820018J
N N N
DIMM ONLY
N
check ok

ix
af
UD1 MD_S8Gb@ UD2 MD_S8Gb@ UD3 MD_S8Gb@ UD4 MD_S8Gb@ RC44 MD_S8Gb@ RC41 MD_S8Gb@ RC38 MD_S8Gb@ RC39 MD_S8Gb@

in
K4A8G165WC-BCWE K4A8G165WC-BCWE K4A8G165WC-BCWE K4A8G165WC-BCWE 10K_0402_5% 2K_0402_5% 10K_0402_5% 10K_0402_5%
SA0000AC810 SA0000AC810 SA0000AC810 SA0000AC810 SD02810028J SD02820018J SD02810028J SD02810028J

//v
N N N N
memory particles
N
matched resistance
N N
DRAM_Samsung
N
4G check ok

s:
tp
B
ht B

PRTC1 RTC@ ZZZ13 ZZZ14 HDMI@

GS451 DAZ1JQ00100
GS551 DAZ1JR00100
GS751 DAZ1JT00100

BATT CR2032 3V 220MAH PCB PN HDMI PN

X7647H12001 DAZ1JQ00100 RO00000040J
RTC N
PCB_MB N
check ok HDMI N

RD233 SDP@ RD232 SDP@ RD231 SDP@ RD228 SDP@ RD233 DDP@ RD232 DDP@ RD231 DDP@ RD228 DDP@

0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 240_0402_1% 240_0402_1% 240_0402_1% 240_0402_1%

SD02800008J SD02800008J SD02800008J SD02800008J SD000009T8J SD000009T8J SD000009T8J SD000009T8J
N N N N N N N N
A SDP DDP check ok A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 Virtual symbol

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S350 ARE
Date: Monday, February 10, 2020 Sheet 35 of 44
5 4 3 2 1
 5 4 3 2 1

D D

C C

om
.c
ix
B B

af
in
//v
s:
tp
ht
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/15 Deciphered Date 2013/08/15 Power sequence Block

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S350 ARE
Date: Sunday, January 19, 2020 Sheet 36 of 44
5 4 3 2 1
 5 4 3 2 1

B+ Richtek +1.8VS/2A
Silergy +5VALW
+5VALW/8A RT8068AZQW
SY8288CRAC Convertor
QFN20_3X3 FOR +1.8VALW
Adaptor Converter +5VLP/ 100mA SUSP# EN
D
EC_ON_3V EN FOR SYSTEM PGOOD D

NA

Silergy +3VLP/ 100mA

SY8386BRHC
QFN16_2P5X2P5
Converter +3VALW/ 6A
EC_ON_5V EN
FOR SYSTEM PGOOD
NA

TI
BQ24780SRUYR
C
Battery Charger C

Switch Mode
LCFC +1.2V/6A

om
LV5028
1.2VEN S5 PMIC +0.6VS/1A
SUSP# S3
FOR SYS

.c
POK_VDDQ
SMBus

ix
+5VALW
+0.75VALW/6A

af
0_75VALW_EN EN
PGOOD APUALW_PWRGD

in
+5VALW +1.8VALW/3A

//v
Battery EC_APU_ALWEN EN PGOOD APUALW_PWRGD

Li-ion

s:
3S1P +3.3VALW

tp
+2.5V/1A
B B
2.5VEN EN
ht

Richtek VDDC_VDD/44A
RT3663BCGQW
controller VDDCR_SOC/13A
APU_SVI2 VIDs FOR CPU CORE&SOC
EC_VR_ON EN VR_APU_PWRGD
PGOOD

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/15 Deciphered Date 2013/08/15 Power Diagram

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
S350 ARE 1.0

Date: Sunday, January 19, 2020 Sheet 37 of 44

5 4 3 2 1
 5 4 3 2 1

PL101 EMC_NS@
HCB2012KF-121T50_0805
1 2 VIN BATIN BATT+
PL103 EMC@
D PL102 EMC@ HCB2012KF-121T50_0805 D
HCB2012KF-121T50_0805 1 2
1 2

PJ101 @ PL104 EMC@

JDCIN1 PF101 JUMP_43X79 HCB2012KF-121T50_0805
1 APDIN 1 2 APDIN1 1 2 1 2
1 1 2 JBATT1
2
GND1 3 7A_24VDC_429007.WRML 1 BATIN
GND2 1

1
4 2 PC106 PC107
GND3 5 9 2 3 EC_SMCA 1000P_0402_50V7K 0.01U_0402_25V7K

1000P_0402_50V7K

1000P_0402_50V7K
100P_0402_50V8J

100P_0402_50V8J
GND4 6 10 GND1 3 4 EC_SMDA
EMC@ EMC@

PC101EMC@

PC102EMC@

PC103EMC@

PC104EMC@
GND5 GND2 4

2
1

1
7 5 AZC199-02S.R7G_SOT23-3
GND6 5 6 PD103
6

2
ME@ 7
7

2
8
8

1
HIGHS_PJSS0026-8B01H

100_0402_1%

100_0402_1%
ME@

PR106

PR105
SUYIN_125022HB008M202ZL

2
EMC_NS@

1
C JBATT2 ME@ EC_SMB_CK1 31,39
C

1 BATIN
1 2 BATIN
2 EC_SMB_DA1 31,39
3 EC_SMCA
GND 9 3 4 EC_SMDA 100K_0402_1%
GND 10 GND1 4 5 BATT_TEMP_IN PR107
GND2 5 6 1 2

om
6 7 GND +3VALW
7 8 GND
8
BATT_TEMP_IN 1 2
BATT_TEMP 31,39

.c
HIGHSTAR_WS33081-S120S-1H PR108 A/D
10K_0402_1%

ix
ONLY for 17'

af
RTC_VCC
VCCRTC +3VL PR109 1 @ 2 0_0402_5%
RTC_VCC

in
//v
Just reserved for RTC integrated into Battery
PD101
2

s:
B
1 JRTC1 B
3 2 1 1
2 1

tp
PR104 3 2
1U_0402_10V6K

2 LBAT54CWT1G_SOT323-3 GND1
1K_0603_1% 4
PC105

GND2 ht
@
1 HIGHS_WS33020-S0351-HF
ME@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/15 Deciphered Date 2013/08/15 DCIN / RTC

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S350 ARE
Date: Sunday, January 19, 2020 Sheet 38 of 44
5 4 3 2 1
 5 4 3 2 1

V20B+
PQ201 PQ202

@
AONS32314_DFN8-5 AONR32340C_DFN8-5 PJ201 PR201
D
P2 P3 JUMP_43X79 0.01_1206_1% D
1 1
2 2 S1 5 2 1 1 4
5 3 3 S2 D 2 1
VIN S3 2 3

220P_0402_50V7K

470P_0402_50V7K

680P_0402_50V7K

4700P_0402_50V7-K

6800P_0402_25V7-K

220P_0402_50V7K

4700P_0402_50V7-K

6800P_0402_25V7-K
10U_25V_M_X5R_0603

10U_25V_M_X5R_0603

0.01U_50V_K_X7R_0402

0.01U_50V_K_X7R_0402
PQ203

EMC_NS@

EMC_NS@
1 1

4
1 4

5
AON6324_DFN8-5
For 2cell battery system shutdown issue

PC329

PC330

PC331

PC332

PC333

PC334

PC335

PC338

PC339

PC340
1 1

470P_0402_50V7K

0.022U_0402_25V7K
4.7_0603_5%
1

1
PC201

PR202
2 2

2
PD202 @

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@
PC202

PC203

PC204
2 2
SDT10A45P5-13_POWERDI5-3

2
780s_BATDRV 4

0.01U_0402_25V7K
499K_0402_1%

3
1

3
2
1
1
780s_ACDRV_R

PR203

PC208
2
2
1 2
VIN VIN BATT+
PC205
0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6
LBAT54CWT1G_SOT323-3
1

1
4.02K_0603_1%

4.02K_0603_1%

1
PR206

PR207

PC206

PC207
2

2
V20B+

PD201
2

43K_0402_1%
1

PR208

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603
EMC_NS@
1 1

0.1U_0402_25V6
2

1
BQ24780S_VDD

PC209
1

ACN
ACP

PC211

PC212
PR209

0.01U_0402_25V7K
2 2

2
10_1206_5%

7.15K_0402_1%
2
2

1
PC215

PR210
C C

2
2.2U_10V_K_X5R_0603

ACN
ACP

5
PC213 PC214
1 1 2 780s_VCC 28 24 1 2 PQ205
VCC REGN

1
AON7380_DFN8-5
1U_0603_25V6K 780s_ACDET 6
ACDET 2.2_0603_5% 0.047U_0603_16V7K

om
25 780s_BS 1 2 2 1 4
BTST
PR211 PC216
780s_CMSRC 3 26 780s_HG
CMSRC HIDRV PR213

3
2
1
780s_ACDRV 4 0.01_1206_1%
ACDRV PL201
780s_LX

.c
27 1 2 1 4
ACOK_10k pull high +3VL of open drain output at EC 780s_ACOK
PHASE 2.2UH_PCMB063T-2R2MS_8A_20% BATT+
PR215 2 1 0_0402_5% 5

BQ24780SRUYR_QFN28_4X4
@ PQ206 2 3

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
ACOK

1
31 ACIN

1
PR217 2 @ 1 0_0402_5% 780s_SDA 11 PR216

ix

PC221

PC218

PC217

PC230
31,38 EC_SMB_DA1 SDA

AON7380_DFN8-5
23 780s_LG 4.7_0805_5%
SMBUS_10k pull high +3VL_EC of open drain output at EC LODRV
EMC_NS@

PU201

2
PR218 2 @ 1 0_0402_5% 780s_SCL 12 22 1 2
31,38 EC_SMB_CK1 SCL GND

2
af
4
PC228

0.1U_0402_25V6

0.1U_0402_25V6
1
PR219 2 @ 1 0_0402_5% 780s_IADP 7 29 PC222 0.1U_0402_25V6
31 ADP_I IADP PAD

1
1000P_0402_50V9-J

PC223

PC224
PR220 1 2 0_0402_5% 780s_IDCHG 8 18 780s_BATDRV
EMC_NS@
@

in
31 IDCHG IDCHG BATDRV

3
2
1

2
10_0603_5%

2
PR221 2 @ 1 0_0402_5% 780s_PMON 9 PR222
31 PSYS PMON 780s_BATSRC 780s_BATSRC_R
17 1 2
BATSRC

//v
20 780s_SRP 1 2 780s_SRP_R
780s_VR_HOT 10 SRP
PROCHOT# PR224 charge：
100P_0402_50V8J

100P_0402_50V8J

100P_0402_50V8J

PR231
13
CMPIN
10_0603_5%
max current=3.75A

BATPRES#
1

s:
volatge=3S

TB_STAT#
20K_0402_1% 14
PC225

PC226

PC227

CMPOUT 19 780s_SRN 1 2 780s_SRN_R

SRN
780s_ILIM 21
fsw=800K/REG0x12[9:8] = 01
@

ILIM
2

PR225

tp
10_0603_5%

16

15
1

B PR226 ht B
31 VR_HOT# PR232 2 @ 1 0_0402_5% 0_0402_5%
@ 780s_TB#

VR_HOT_10k pull high +3VS_APU of open drain output at APU

2

1 2 780s_ILIM_R 1 2
+3VALW BATT_TEMP 31,38
PR227 PR228
143K_0402_1% 32.4K_0402_1%
100K_0402_1%
0.1U_0402_25V6

Charge current limit 7A

1

PC229

PR230

discharge current 10A limit during turbo

2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 CHARGER

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S350 ARE
Date: Sunday, January 19, 2020 Sheet 39 of 44
5 4 3 2 1
 5 4 3 2 1

+3VALW
D D

1
PR1101
@
100K_0402_5%

V20B+

2
PJ1101 PU1101

@
2 1 +3VALW_VIN 2 7 +3VALW_PG

0.1U_0402_25V6

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603
2 1 3 IN1 PG 1 +3VALW_BST 1 2

EMC_NS@
1 1 IN2 BS

1
JUMP_43X79 4 PC1104

PC1101
IN3 0.1U_0603_25V7K

SY8386BRHC_QFN16_2P5X2P5
PC1102

PC1103
5
2 2 LX1 PL1101

2
6 15 PJ1102

@
14 GND1 LX2 16 +3VALW_LX 1 2 +3VALW_P 2 1
GND2 LX3 2 1 +3VALW

1
17
GND3 PR1102 1.5UH_PCMB063T-1R5MS_10A_20%

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
JUMP_43X79
2.2_0805_5%

150U_B2_6.3VM_R35M
PR1112 2 @ 1 0_0402_5% 9 11 +3VALW_P
31 EC_ON_3V +3VALW_VIN 1 2 8 EN1 OUT EMC_NS@ 1 1 1 1 1
@

PC1107

PC1108

PC1109

PC1110
EN2

1 2
10 +3VALW_FB +

PC1105
PR1103

0.1U_0402_25V6
FF
10K_0402_5% 2 2 2 2

1
12
100mA PC1111

PC1106
TEST 2

1
13 1000P_0402_50V7K
LDO +3VLP 3VALW:

2
EMC_NS@

2
TDC=6A
PR1111

1M_0402_5%
1
34.8K_0402_1%

PR1107
OCP=8A
PC1112

1 2

2
4.7U_0603_6.3V6K

SSM3K15AMFV_2-1L1B
2 1 2 1 2
OVP=120%
PC1113 PR1108
Fsw=600KHz

PQ1101
2 1000P_0402_25V7-K 1K_0402_1%
31 USM_EN_3V PJ1103

@
1 2 1
+3VLP 2 1 +3VL

3
PR1113
100K_0402_5% JUMP_43X39
2

C C

+3VALW

om
1
PR1601
@

.c
100K_0402_5%

V20B+

2
PU1601
PJ1601
@

ix
2 1 +5VALW_VIN 2 7 ALW_PWRGD
0.1U_0402_25V6

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603
2 1 3 IN1 PG 1 +5VALW_BST 1 2
EMC_NS@

1 1 IN2 BS +5VALW
1

JUMP_43X79 4 PC1603
PC1604

IN3 PL1601

af
0.1U_0603_25V7K PJ1602
8A

@
SY8388CRHC_QFN16_2P5X2P5
PC1601

PC1602

5 +5VALW_LX 1 2 +5VALW_P 2 1
2 2 LX1 2 1
2

1
15 2.2UH_PCME063T-2R2MS_10A_20%
LX2 16 PR1602

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
JUMP_43X79

150U_B2_6.3VM_R35M
6 LX3 2.2_0805_5%

in
GND1 1
14 EMC_NS@ 1 1 1 1 @
17 GND2 +

PC1608

PC1605

PC1606

PC1609

PC1607
GND3

1 2
11 +5VALW_P
PR1603 OUT

//v
0_0402_5% 10 PC1610 2 2 2 2 2
2 @ 1 +5VALW_EN 9
EN1
FF 1000P_0402_50V7K 5VALW:

2
31 EC_ON_5V +5VALW_VIN 1
TDC=8A
2 8 12 EMC_NS@
EN2 LDO +5VLP
1

PR1604
100mA OCP=12A
1 2 10K_0402_5% 13 +5VVCC 1
25 EC_ON_R VCC

s:
PR1605

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
OVP=120%
1

0_0402_5% 68K_0402_1%
@

PC1613
1
0.1U_0402_25V6

PR1608 @
SSM3K15AMFV_2-1L1B

Fsw=600KHz
2
2

PC425
1M_0402_5%
PC1611

PC1612
tp
470P_0402_50V7K
PR1606

2
1

+5VALW_FB 2 1 1 2
2

PR1607
PQ1601

B 2 ht 1K_0402_1% B
31 USM_EN_5V
3
1

PR1609
100K_0402_5%
2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 PWR_3VALW/5VALW

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S350 ARE
Date: Sunday, January 19, 2020 Sheet 40 of 44
5 4 3 2 1
 5 4 3 2 1

PR1902 2 @ 1 0_0402_5% LV5075_VDDQ_EN

31 1_2VEN
SYSON-1_2VEN
PC1909 2 1 0.1U_0402_10V6-K

@
SUSP# PR1904 2 @ 1 0_0402_5% LV5075_VTT_EN
31,33,42 SUSP#

PC1908 2 1 0.1U_0402_10V6-K

@
D D
EC_APU_ALWEN PR1908 2 @ 1 0_0402_5% LV5075_1P8VA_EN
31 EC_APU_ALWEN
100k pull high for support 1.8V SPI mirror code
LV5075_VCC
PC1906 2 1 0.1U_0402_10V6-K
10_0603_5%

@
PR1907
0_75VALW_EN PR1910 2 @ 1 0_0402_5% LV5075_0.75ALW_EN 1 2 PR1901 2 @ 1 0_0402_5%
31 0_75VALW_EN +5VLP PIMC_PWR_EN 31

need 100K pull down at EE side 2 1 1 2

PC1905 2 1 0.1U_0402_10V6-K

@
PC1902 PC1903
@ 2.2U_10V_K_X5R_0603 0.1U_0402_10V6-K

PR1911 2 @ 1 0_0402_5% LV5075_2.5V_EN PR1909

31 2_5VEN

LV5075_PMIC_EN
1 2
EC-2_5VEN +1.2V_B+

LV5075_VSYS
10_0402_5%
PC1904 2 1 0.1U_0402_10V6-K 1 2
@

PC1901
1U_0402_25V6-K

28

27

41
9
VCC

GND
PMIC_EN
VSYS
PR1923 1 210K_0402_5% 29 25 LV5075_EC_SMB_DA3 PR1925 2 @ 1 0_0402_5%
EN_LDO1 SDA EC_SMB_DA3 31
LV5075_2.5V_EN 1 26 LV5075_EC_SMB_CK3 PR1926 2 @ 1 0_0402_5%
EN_LDO2 SCL EC_SMB_CK3 31

LV5075_LX_0.75VALW
LV5075_0.75ALW_EN 11 24 LV5075_ALERT# PR1912 1 2 0_0402_5%

@
EN_V1P0A OT H_PROCHOT# 6,31

22UC_6.3VC_MC_X5RC_0603
LV5075_1P8VA_EN 16 22 APUALW_PWRGD PR1927 2 1 100K_0402_5%

LV5075_LX_1P8
EN_V1P8A PG_V1P0A +3VALW
LV5075_VDDQ_EN 31 21
EN_VDDQ PG_V1P8A APUALW_PWRGD 31
PJ1901 LV5075_VTT_EN 36 23

@
1 2 LV5075_0.75VALW_VIN EN_VTT PG_VDDQ

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
+5VALW 1 2 PL1901
PJ1902

EMC_NS@

@
0.1U_0402_25V6
JUMP_43X39 12 LV5075_LX_0.75VALW 1 2 +0.75VALW_P 2 1
1 LX_V1P0A1 2 1 +0.75VALW

2
7 13

EMC_NS@

EMC_NS@
PC1910

PC1911

4.7_0603_5%

4.7_0603_5%
C
8 VIN_V1P0A1 LX_V1P0A2 14 0.47UH_PCMB063T-R47MS_18A_20% JUMP_43X79
C
VIN_V1P0A2 LX_V1P0A3 1 1 1 1 1 1 0.75VALW:

22UC_6.3VC_MC_X5RC_0603
15
TDC=6A

PC1912

PC1913

PC1914

PC1915

PC1916

PC1917

PR1918

PR1919
2 LX_V1P0A4

2
PJ1903
@ 10 OCP=10A
VO_V1P0A 2 2 2 2 2 2 OVP=120%

1
1 2 LV5075_V1P8_VIN

@
+5VALW 1 2
Fsw=1M

EMC_NS@
1

0.1U_0402_25V6

om
1
JUMP_43X39 17 LV5075_LX_1P8 PL1902 PJ1904

@
PC1918

PC1919
19 LX_V1P8A1 18 1 2 +1.8VA_P 2 1
+1.8VALW

680P_0402_50V7K

680P_0402_50V7K
VIN_V1P8A LX_V1P8A2 1UH_PH041H-1R0MS_3.8A_20% 2 1

EMC_NS@

EMC_NS@
2

1
20 JUMP_43X79
1.8VALW:

PC1930

PC1931
VO_V1P8A

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
+1.2V_P APU_VDD18=2A(TDC)
+1.2V_P 1 1
TDC=3A

2
33 LV5075_UG_1.2V
→ 38

PC1920

PC1921
2 UGATE_VDDQ
OCP=6A

.c
PR1916 PC1925
PC1924 VIN_VTT 32 LV5075_BST_1.2V 1 @ 2 1 2
BS_VDDQ 2 2 OVP=120%
← 39
10U_0603_6.3V6M
1 Fsw=1M

22UC_6.3VC_MC_X5RC_0603
0_0603_SP 0.1U_0603_25V7K
VTT 34 LV5075_LX_1.2V

ix
PJ1905 LX_VDDQ
@

2 1 +0.6VSP 40 35 LV5075_LG_1.2V
+0.6VS 2 1 VSNS_VTT LGATE_VDDQ

af
JUMP_43X39 1 PR1917 37 +1.2V_P
1 2 LV5075_CS 30 VSNS_VDDQ
PC1926

CS_VDDQ
33K_0402_1%
2

in
5 6
VIN_LDO1 LDO1

//v
PJ1910

@
PJ1909 3 +2.5V_P 1 2
@

1 2 LV5075_2.5V_VIN 4 LDO2 1 2 +2.5V

+3VALW

24.9K_0402_1%
1 2 VIN_LDO2

1
2 JUMP_43X39
FB_LDO2
10U 6.3V M X5R 0402

s:
JUMP_43X39
2.5V:

PR1920
2
1
PC1935 TDC=1A
PC1934

PU1901
1
10U_0603_6.3V6M FB=0.75V

2
LV5028RPC_QFN40_5X5

tp
2 +2.5V_FB

B
ht B

10.5K_0402_1%
PR1921
2
+1.2V_B+
PJ1908

@
+1.2V_B+ 1 2
1 2 V20B+
JUMP_43X39

0.1U_0402_25V6
EMC_NS@

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603
1
5

PC1929
1 1
PQ1901

D
AONR32340C_DFN8-5

PC1932

PC1933
2
2 2
LV5075_UG_1.2V 4
G
+1.2V_P

S3
S2
S1
0.47UH_PCMB063T-R47MS_18A_20% @
PL1903 PJ1911

3
2
1
LV5075_LX_1.2V 1 2 +1.2V_P 2 1
2 1 +1.2V
5

2
JUMP_43X118
PR1922

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
1.2V:

AON7380_DFN8-5
4.7_0805_5%
EMC_NS@ TDC=10A

PQ1902
1 1 1 1 1 1 OCP=20A

1
LV5075_LG_1.2V 4
OVP=120%

PC1937

PC1938

PC1939

PC1940

@PC1941

PC1942
Fsw=1M

1
PC1943
680P_0402_50V7K 2 2 2 2 2 2

@
EMC_NS@
3
2
1

2
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/02/20 Deciphered Date 2014/02/20 System PMIC

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S350 ARE
Date: Sunday, January 19, 2020 Sheet 41 of 44
5 4 3 2 1
 A B C D

1 1

+3VALW

100K_0402_1%
2
PL2101
PJ2101 1UH_PH041H-1R0MS_3.8A_20% PJ2102

PR2101
+1.8VS
2 2

2 1 +1.8VS_VIN +1.8VS_LX 1 2 +1.8VS_P 2 1

+5VALW 2 1
@
2 1
@

EMC_NS@ EMC_NS@
680P_0402_50V7K 4.7_0603_5%
10U_0603_6.3V6M

10U_0603_6.3V6M

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
JUMP_43X39 @ JUMP_43X79

PR2102
2 2

2200P_25V_K_X7R_0402
1/16W_102K_1%_0402
PC2101

PC2102

0.1U_0402_25V6
4

EMC_NS@

EMC_NS@
1

68P_0402_50V8J
1

1
10 1

PC2109

PC2108
1 1

PG
PVIN2 LX1

1 1
1 1

1
PR2103

PC2104

PC2105

PC2106
om
9 2

PC2103
PVIN1 LX2

2
2

2
8 3 2 2
SVIN1 LX3

2
PR2105
+1.8VS_EN +1.8VS_FB

.c
31,33,41 SUSP# 1 2 5 6

GND
EN FB

NC
0.47U_0402_25V6K

1/16W_51K_1%_0402
1/16W_16K_1%_0402 PU2101

ix
11

7
2

1
RT8068AZQW_W DFN10_3X3

1M_0402_1%
1

PR2106

PC2107

PR2104
af
2

2
in
//v
s:
tp
3 3

ht

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/15 Deciphered Date 2013/08/15 PWR_1.8VS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
S350 ARE 1.0

Date: Sunday, January 19, 2020 Sheet 42 of 44

A B C D
 5 4 3 2 1

V20B+

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603
0.1U_25V_K_X5R_0402

22U_B2_25VM_R100M

22U_B2_25VM_R100M
@

EMC@
1 1 1 1 @ 1

PC5623

PC5624

PC5625
+ +

PC5626

PC5627
5
2 2 2

AON6380_DFN8-5
2 2
D D

PQ5601
P_VDDC_VDD_UG1_30 4

3
2
1
PL5601
0.15UH_CMME063T-R15MS0R905_38A_20%
P_VDDC_VDD_PH1_30 1 2
+VDDC_VDD
@ @

2
0_0805_5%
PJ5601 PJ5602 Base on 25W config

PR5656
AON6324_DFN8-5
JUMPER JUMPER
APU_VDDCR

1
FSW=400KHz

PQ5602
P_VDDC_VDD_LG1_30

2
4
Slew rate:12.5mv/us

1
1000P_0402_50V7K
PR5657 TDC=44A EDC=70A
2K_0402_1% OCP=105A

1
OVP=VID+300mV

PC5628
3
2
1
1.RT3663BH change to RT3663BM PC5629 Load Line=0.7mohm

2
2.VDD chock change to DCR 5% PN

2
3.PWR_OK sequency confirm
1 2 Ripple:+/-20mv
VOTFC missing issue change to MAX AC: VID_VDDC +95mv
0.1U_25V_K_X5R_0402
RT3663BM ES 09/27 MP 10/15 MIN AC: VID_VDDC -80mv
P_VDDC_VDD_ISEN1P_10
PU5601
100K_0402_1% 1/16W_2.2_1%_0402
+P_APU_VCC_20 PR5633 PR5632
P_APU_TONSET_10 1 2 2 1
PR5602 1 2 10_0603_5% 28 4
V20B+
+5VALW VCC TONSET Fsw_Max 413K 1
PC5601 2 1 2.2U_10V_K_X5R_0402 PC5611
0.1U_25V_K_X5R_0402
PR5601 1 2 2.2_0603_5% P_APU_PVCC_20 50 PR5635 PC5612 2
+5VALW PVCC 46 P_VDDC_VDD_BOOT1_30 2 1 2 1 P_VDDC_VDD_PH1_30 P_VDDC_VDD_ISEN1N_10
PC5602 2 1 2.2U_10V_K_X5R_0402 BOOT1
PR5603 47 P_VDDC_VDD_UG1_30 2.2_0603_5% 0.22U_0603_25V7K
1 2 PR5604 2 1 100K_0402_1%P_APU_TONSETA_10 40 UGATE1
V20B+ Fsw_Max 411K TONSETA 48 P_VDDC_VDD_PH1_30
1 PHASE1
1/16W_2.2_1%_0402 PC5603
0.1U_25V_K_X5R_0402 V20B+

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603
0.1U_25V_K_X5R_0402
2
P_VDDCR_SOC_PH1_30 1 2 1 2 P_VDDCR_SOC_BOOT1_30 42 49 P_VDDC_VDD_LG1_30
BOOTA1 LGATE1
P_VDDCR_SOC_UG1_30 1 1 1
43

EMC@
PC5604 PR5605

PC5630

PC5631

PC5632
0.22U_0603_25V7K 2.2_0603_5% UGATEA1
P_VDDCR_SOC_PH1_30

5
44
PHASEA1 8 P_VDDC_VDD_ISEN1P_10 2 2 2

AON6380_DFN8-5
ISEN1P
7 P_VDDC_VDD_ISNE1N_R_10 PR5636 2 1 1/16W_732_1%_0402 P_VDDC_VDD_ISEN1N_10
ISEN1N

PQ5603
1 P_VDDC_VDD_UG2_30
PC5613 4
P_VDDCR_SOC_LG1_30 45 0.1U_25V_K_X5R_0402
LGATEA1
PR5637 PC5614 2
2 P_VDDC_VDD_BOOT2_30 2 1 2 1 P_VDDC_VDD_PH2_30
P_VDDCR_SOC_ISEN1P_10 BOOT2

3
2
1
36 PL5602
ISENA1P 1 P_VDDC_VDD_UG2_30 2.2_0603_5% 0.22U_0603_25V7K 0.15UH_CMME063T-R15MS0R905_38A_20%
P_VDDCR_SOC_ISEN1N_10 1 2 P_VDDCR_SOC_ISNE1N_R_10 35 UGATE2 P_VDDC_VDD_PH2_30 1 2
+VDDC_VDD
0.1U_25V_K_X5R_0402

ISENA1N 52 P_VDDC_VDD_PH2_30
PHASE2
1 PR5606 @ @

2
1/16W_732_1%_0402

0_0805_5%
PC5605

PJ5603 PJ5604

PR5659
AON6324_DFN8-5
51 P_VDDC_VDD_LG2_30
C JUMPER JUMPER C
2 LGATE2

1
PQ5604
P_VDDC_VDD_LG2_30

2
4
P_VDDC_VDD_ISEN2P_10

1
5

1000P_0402_50V7K
41 ISEN2P PR5660
PWMA2 6 P_VDDC_VDD_ISNE2N_R_10 PR5638 2 1 1/16W_732_1%_0402 P_VDDC_VDD_ISEN2N_10 2K_0402_1%
ISEN2N

PC5633
1

3
2
1
PC5615
PC5634

2
0.1U_25V_K_X5R_0402

2
1 2
10K_0402_1% 2
PR5671 0.1U_25V_K_X5R_0402
1 2 33
+5VALW ISENA2P 3 P_VDDC_VDD_PWM3_10
NOT USE,Connect to 5VALW PWM3 P_VDDC_VDD_ISEN2P_10
34
ISENA2N
330P_0402_50V7K 56P_50V_J_NPO_0402
PC5606 PC5607

om
1 2 1 2 P_SOC_COMP_10

30
10K_0402_1% 47.5K_0402_1% COMPA 9 P_VDDC_VDD_ISEN3P_10
PR5631 1 2 1/16W_10_1%_0402 1 PR5607 2 1 PR5608 2 ISEN3P
6 VDDCR_SOC_VCC_SENSE P_VDDC_VDD_ISNE3N_R_10 P_VDDC_VDD_ISEN3N_10 P_VDDC_VDD_ISEN2N_10
10 PR5639 2 1 1/16W_732_1%_0402
ISEN3N
VDDCR_SOC_VSS_SENSE merge with VDDCR_VSS_SENSE P_VDDCR_SOC_FB_10 1
31 PC5616
FBA 0.1U_25V_K_X5R_0402

2
+VDDCR_SOC PR5630 1 2 100_0402_1% 32 PC5617 PC5618

.c
VSENA 13 P_VDDC_VDD_COMP_10 1 2 1 2
COMP
56P_50V_J_NPO_0402 220P_0402_50V7K V20B+
VDD/DOC offset 0mV PR5640 PR5641

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603
PR5610 2 @ 1 10K_0402_1% 1 2 1 2
+P_APU_VCC_20

0.1U_25V_K_X5R_0402
PR5612 1 2 10K_0402_1% P_VDDCR_SOC_OFS_10 24 34.8K_0402_1% 10K_0402_1%

ix
OFSA P_VDDC_VDD_FB_10 1 1 1
12

EMC@
PC5636

PC5637
PR5611 2 1 10K_0402_1% P_VDDCR_CPU_OFS_10 23 FB
+P_APU_VCC_20 @

PC5635
OFS

5
PR5613 1 2 10K_0402_1% 2 2 2

AON6380_DFN8-5
PR5677 1 2 40.2_0402_1%
OPR SET VDD/SOC: PR5614 2 1 124K_0402_1% PR5616 2 1 1K_0402_1% P_APU_SET1_10 +VDDC_VDD
+P_APU_VCC_20

af
PR5618 2 1 20.5K_0402_1% PR5620 2 1 200_0402_1% 25 11 PR5676 1 2 1/16W_10_1%_0402

PQ5605
OCP_TDC≠OCP_SPIKE SET1 VSEN VDDCR_VCC_SENSE 6
PR5665 4
VID up compensate LL 18mv 1 60.4_0402_1% P_APU_SET2_10

2
PR5615 1 2 33.2K_0402_1% PR5617 2 26 2.2_0603_5%
Ramp 100%/QRTH 39mV +P_APU_VCC_20 PR5621 1 2 110_0402_1% PR5619 1 2 1/16W_8.45K_1%_0402 SET2 PC5620 1 2 Driver_VCC PR5666 PC5641
1000P_0402_50V7K
+5VALW 4 2 1 1 2
Offset disable BOOT

1
PC5640 2 1 1U_0402_10V6K 8
OCP trigger delay 10ms VCC

3
2
1
53 14 P_APU_RGND_10 PR5675 1 2 1/16W_10_1%_0402 3 2.2_0603_5% 0.22U_25V_K_X5R_0402 P_VDDC_VDD_UG3_30 PL5603
GND RGND UGATE

in
VDDCR_VSS_SENSE 6 P_VDDC_VDD_PWM3_10 5 0.15UH_CMME063T-R15MS0R905_38A_20%
PR5674 1 2 PWM 2 P_VDDC_VDD_PH3_30 1 2
100K（>1%）*20uA=2V, for internal analog circuits 40.2_0402_1%
PR5622 1 P_APU_IBIAS_10 2 100K_0402_1% PR5644 2 @ 1 0_0402_5%
EC_VR_ON 31
Driver_VCC PR5667 2 @ 1 0_0402_5% 1
EN
PHASE
7 P_VDDC_VDD_LG3_30
+VDDC_VDD
P_APU_EN_10
Connect to output Cap GND LGATE @ @

2
Pull up with +1.8VALW follow CRB 29 37 PC5621 1 2 0.1U_10V_K_X5R_0402 6

0_0805_5%
PR5623 1 2 2.2_0603_5% IBIAS EN GND1 9 PJ5605 PJ5606

PR5662
+1.8VALW

AON6324_DFN8-5
2 1 P_APU_VDDIO_20 GND2
PC5610 1U_0402_6.3V6K
→ 18 PH5602 PR5650 JUMPER JUMPER

//v
VDDIO

1
2 1 2 1 PU5602
Pull up with +1.8VALW follow CRB 1/16W_23.2K_1%_0402 RT9610CGQW_WDFN8_2X2

PQ5606

2
6 APU_PWROK
PR5673 2 @ 1 0_0402_5%
→ 19 PWROK P_VDDCR_SOC_IMON_10
PR5649 100K_0402_1%_NCP15WF104F03RC 6.49K_0402_1% 4

1
17 2 1 PR5648 2 1 20K_0402_1%

1000P_0402_50V7K
20 IMONA PR5663
6 APU_SVC SVC

1
PC5647 1 2 @ 0.1U_25V_K_X5R_0402 PH5601 PR5647 2K_0402_1%

PC5638
21 15 P_VDDC_VDD_IMON_10 2 1 2 1 2 1
6 APU_SVD SVD IMON

3
2
1
PC5648 1 2 @ 0.1U_25V_K_X5R_0402
PC5639

2
22 PR5646 100K_0402_1%_NCP15WF104F03RC 12.4K_0402_1%
6 APU_SVT SVT

s:
PC5649 1 2 @ 0.1U_25V_K_X5R_0402 7.32K_0402_1% PR5645 2 1 14K_0402_1% 1 2
38
B PR5628 2 1 PGOODA B
+3VS 10K_0402_1% POR,Vdiv=2150mV:current gain ratio 25% 0.1U_25V_K_X5R_0402

31 VR_PWRGD ← 39 PGOOD
P_APU_V064_20
after POR,V064 clamp voltage =0.64V
P_VDDC_VDD_ISEN3P_10
PR5629 1 @ 2 10K_0402_1% 27 16 2 1 2 1
+1.8VS OCP_L V064/SET3 +P_APU_VCC_20

tp
PR5672 1 @ 2 0_0402_5% PR5651 PR5652
31 P_APU_OCPL_10
RT3663BMGQW_WQFN52_6X6 330_0402_1% 26.1K_0402_1%

19.6K_0402_1%
1

2
PR5653

PR5654
0_0402_5%

2
ht P_VDDC_VDD_ISEN3N_10

1
0.022U_0402_25V7K

1/16W_340_1%_0402
2

PC5622

PR5655
1

1
V20B+

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603
0.1U_25V_K_X5R_0402
1 1 1

PC5643

PC5644
EMC@
PC5642
5
2 2 2

AON6380_DFN8-5
PQ5607
P_VDDCR_SOC_UG1_30 4

3
2
1
PL5604
0.36UH_PCMB063T-R36MS3R205_20A_20%
P_VDDCR_SOC_PH1_30 1 2
+VDDCR_SOC
@ @

2
0_0805_5%
PJ5607 PJ5608

AON6324_DFN8-5

PR5668
JUMPER JUMPER

1
PQ5608

2
P_VDDCR_SOC_LG1_30 4

4.75K_0402_1%
1
VDDCR_SOC

1000P_0402_50V7K

PR5669
FSW=300KHz

PC5646
Slew rate :12.5mv/us

3
2
1
PC5645
TDC=13A EDC=17A

2
1 2 OCP=26A
OVP=VID+300mA
0.1U_25V_K_X5R_0402
Loadline=2.1mohm
PR5678 Ripple:+/-20mv
P_VDDCR_SOC_ISEN1P_10 1 2 MAX AC: VID_VDDCR_SOC +70mv
1/16W_1.87K_1%_0402 MIN AC: VID_VDDCR_SOC -40mv

A A

P_VDDCR_SOC_ISEN1N_10

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/15 Deciphered Date 2013/08/15 PWR_VDD/SOC

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
S350 ARE 1.0

Date: Sunday, January 19, 2020 Sheet 43 of 44

5 4 3 2 1
 A
B
C
D

5
5

2
1
PC5731
22UC_6.3VC_MC_X5RC_0603

2
1
+VDDC_VDD

PC5732
22UC_6.3VC_MC_X5RC_0603

2
1
PC5733
22UC_6.3VC_MC_X5RC_0603

4
4

2
1
PC5734
22UC_6.3VC_MC_X5RC_0603

2
1
2
1

PC5735 PC5719
22UC_6.3VC_MC_X5RC_0603 22UC_6.3VC_MC_X5RC_0603

2
1
2
1

PC5736 PC5720
22UC_6.3VC_MC_X5RC_0603 22UC_6.3VC_MC_X5RC_0603

2
1
2
1

PC5737 PC5721
22UC_6.3VC_MC_X5RC_0603
2 22UC_6.3VC_MC_X5RC_0603
1
2
1

PC5738 PC5722
22UC_6.3VC_MC_X5RC_0603 22UC_6.3VC_MC_X5RC_0603
+

2
1

2
1
2
1

PC5770
@

PC5739 PC5723 330U_2.5V_M_B2_ESR9M_H1.9

22UC_6.3VC_MC_X5RC_0603 22UC_6.3VC_MC_X5RC_0603
+

2
1
2
1
2
1

PC5740 PC5724 2 1 PC5701

22UC_6.3VC_MC_X5RC_0603 22UC_6.3VC_MC_X5RC_0603 330U_D2_2V_Y
PC5705
2
1
2
1
2
1
+

0.1U_0402_25V6
@

PC5741 PC5725 EMC_NS@ PC5702

22UC_6.3VC_MC_X5RC_0603 22UC_6.3VC_MC_X5RC_0603 2 1 330U_2.5V_M_B2_ESR9M_H1.9
2
1
2
1

PC5706
@
2
1
+

PC5742 PC5726 0.1U_0402_25V6

22UC_6.3VC_MC_X5RC_0603 22UC_6.3VC_MC_X5RC_0603 EMC_NS@ PC5703
ht
2 1 330U_2.5V_M_B2_ESR9M_H1.9
2
1
2
1

@
2
1
+

PC5743 PC5727 PC5707

tp
@

22UC_6.3VC_MC_X5RC_0603 22UC_6.3VC_MC_X5RC_0603 0.1U_0402_25V6 PC5704

EMC_NS@ 330U_2.5V_M_B2_ESR9M_H1.9
2
1
2
1

2 1
@
2
1
+

PC5744 PC5728
@

22UC_6.3VC_MC_X5RC_0603 22UC_6.3VC_MC_X5RC_0603 PC5708 PC5768

s:
@

0.1U_0402_25V6 330U_D2_2V_Y
2
1
2
1

PC5745 PC5729
EMC_NS@
22UC_6.3VC_MC_X5RC_0603 22UC_6.3VC_MC_X5RC_0603
//v

3
3

2
1
2
1

PC5746 PC5730
in
22UC_6.3VC_MC_X5RC_0603 22UC_6.3VC_MC_X5RC_0603
af
ix
.c
om

Issued Date
2
1
+VDDCR_SOC

PC5747
Security Classification
22UC_6.3VC_MC_X5RC_0603
2
1

PC5748
22UC_6.3VC_MC_X5RC_0603
2
1
2
1
2
1
+

PC5749 PC5754 PC5767

22UC_6.3VC_MC_X5RC_0603 22UC_6.3VC_MC_X5RC_0603 470U_D2_2VM_R4.5M
2
1
2
1
2
1
+

PC5750 PC5755
2013/08/15

22UC_6.3VC_MC_X5RC_0603 22UC_6.3VC_MC_X5RC_0603 PC5769

330U_D2_2V_Y
2
1
2
1

2
2

PC5751 PC5756
22UC_6.3VC_MC_X5RC_0603 22UC_6.3VC_MC_X5RC_0603
2
1
2
1

PC5752 PC5757
22UC_6.3VC_MC_X5RC_0603 22UC_6.3VC_MC_X5RC_0603
2
1
2
1

PC5753 PC5758
22UC_6.3VC_MC_X5RC_0603 22UC_6.3VC_MC_X5RC_0603
2
1

PC5759
Deciphered Date

22UC_6.3VC_MC_X5RC_0603
2
1

PC5760
22UC_6.3VC_MC_X5RC_0603
LC Future Center Secret Data

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
2013/08/15

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

Date:
Custom
Title

Size Document Number

1
1

Sunday, January 19, 2020

PWR_VDD/SOC decoupling cap

Sheet
S350 ARE
44
of
44
Rev
1.0
A
B
C
D