t

R
ie

V
INPUT

Vt
Vcb
c VOUT

-io
Vee
--.I Tp I OUT- O U
TI PUT PUT
Ti . RISE TIME V
e
VLOW VHIGH
TZ ,e SATURATION DELAY
T3 = FALL TIME

SATURATED MODE
I

V15
vc, eig
a VT Vcc
" Re RL
V
NONSATURATED MOOE

asVe<.1i
VT Vcc
+ Vbb + Vbb
TIME

FIG. 1-Response time with storage delay FIG. 2-Back-clamping technique giving
(middle curve) and no delay (lower curve) FIG. 3-Bistable saturated circuit is less
voltage gain along with good efficiency efficient at low output power

BOOSTING TRANSISTOR
By RICHARD H. BAKER
Staff Member
Massachusetts Institute of Technology
Lincoln Laboratory, Cambridge, Mass.

UMMARY Transistor properties affecting response time in switching

circuits are summarized and basic circuits given for obtaining maximum
energy conversion efficiency. Combined use of pnp and npn transistors gives
circuit symmetry that Utilizes inherent advantages of transistors. Other cir-
cuits include saturated and nonsaturated current -demand flip-flops with
single or double triggering, designed for maximum reliability despite normal
variations in circuit constants and input pulses

THE NORMAL three -region junc- that of hole storage or saturation tions. In all modes of operation,
tion transistor (excluding delay. however, the transistor switching
graded -base or drift types) is a time is dependent on the constants
slow device when compared to a Response Times
of the device and the amount of
vacuum -tube triode. In a tube, the There may be as many as three overdrive supplied at the input.
movement of electrons from cath-. separate response times, depending The single most important factor
ode to plate is aided by strong upon the mode of operation, as- affecting the switching time is the
electric fields, whereas in a tran- sociated with a single -stage tran- frequency response of the device it-
sistor the transport of carriers sistor network. These are rise self. Also, minimum response time
(electrons or holes) is only by dif- time, storage or saturation dellay occurs when current gain ay is 1.
fusion. and fall time, all shown in Fig. 1. There is promise of obtaining
In designing transistor circuits If RL, R Vee and VT are chosen high -frequency transistors by us-
for high-speed switching, the de- so that the voltage polarity across ing graded -base structures and
signer must consider normal inte- the collector junction maintains the other configurations. However, the
grative effects due :o shunt ca- collector junction under reverse interim solution of transistor
pacitances as well as the delay or bias at the peak of the output pulse, manufacturers has been to build
carrier transit time between emitter the saturation delay vanishes. transistors with very narrow base
s

and collector. When the transistor The magnitudes of response widths to increase the frequency
is operated in the saturated mode, times Ti, Ts and T. are different response. This approach is fruit-
there exists an additional effect, for each of the three basic connec- ful to a degree, but there is an op -
190
March 1, 1957 - ELECTRONICS
 30 -Vbb -Vbb
-Vbb I -Vbb 1

-6.5 V -65V
-6.5V -65V -TRIGGER WIDTH
-RV FRED= IOCPS
Feb .
-Vee Rb Cbb=0.002
4.TK Rb Rb 4.7K
2N99 2N99 STAYS
6.BK .B

6K
CONSTANT
TO 7100
µSEC

OUT- CIN CIN OUT-

Cbb 0.01 0.01 15
PUT 0.02 PUT

RESET SET RIN IZ SET RESET TIME-

e omega
b 0.022
RL +Vee +Vee R CM

Vet

4JD 4JD 10K

IA22 OK
RbI Cc Cc R. I422 00 510µµF +Vee
510µµF
510µµF 5+VeelOµµF 2 3 +Vbb
47K 4.7K +Vbb K=X1,000 I

Vbb +V TIME IN µSEC +65V +6.5V

1+5V
+65V +6.5V

FIG. 4-Saturated current -demand single - FIG. 5-Characteristics of single -trigger- FIG. 6-Saturated current -demand flip-flop
triggering circuit with 1 -mc transistors ing circuit of Fig. 4 double -triggering with 1 -mc transistors

SWITCHING SPEED

timum base width that yields mini- two inherent opposing effects. As compared with the transistor off -on
mum switching time for practical the signal level increases (total uncertainty region, which is about
switching circuits. This optimum swing), the amount of energy dis- 0.2 volt for germanium transistors
base width is generally different sipated in charging and discharg- and about 1 volt for silicon tran-
for each of the three basic connec- ing capacitance increases. This ef- sistors.
tions. fect indicates that the signal level
Energy Conversion Efficiency
In transistor circuits the transit should be low. On the other hand,
time of the carrier across the base for convenience of circuit design Fundamentally the transistor,
region imposes an absolute mini- the signal level should be large like the vacuum tube, has gain
mum input pulse width. This in by virtue of dissipation changes.
turn sets rather large minimum ca- Unlike the vacuum tube, the input
pacitance values in a given circuit, 12- Ir -SET-RESET TIME impedance is much lower than the
creating recovery time problems output impedance. In the design
that may be more serious than
IO
of realistic transistor systems,
rTRIGG ER WIDTH
actual rise time considerations. FOR 10-µ SEC SET -RESET TIME then, a serious problem arises in
6 the available power to drive suc-
Signal Levels STAYS CONSTANT AT 5V._
ceeding stages. This situation is
Because transistors are ex- STAYS CONSTANT AT 4V%
aggravated still further in the de-
tremely efficient voltagewise, the 8 12 16
sign of high-speed systems, since
system levels are usually set by a TIME IN µSEC it is necessary in the transient
combination of system and tran- state to overdrive the stages to ob-
sistor considerations. FIG. 7-Characteristics of double -trigger- tain fast switching. This fact,
The low voltage limit is auto- ing circuit of Fig. 6 more than any other, accounts for
matically set if the transistors are the large number of transistors re-
allowed to saturate, this being pri- quired to build transistor systems
200µµ F
marily determined by speed con-
/TRIGGER WIDTH
FOR l0' -µSEC
CIN `
Cc 200µµF
compared with equivalent vacuum-
-¡ SET-RESET TIME
tube systems.
siderations. Cbb = 0.022

The upper voltage limit is set by L = 500µ H These considerations indicate

the total power consumption of the \\ SET-RESET
TIME
DECREASES TO
3 5V AT 10 µSEC-,
1

that circuitry should be designed

system and by the punch -through t to deliver maximum output power
and that a high percentage of the
ánd avalanche phenomena in the
transistor. 2
TIME IN µSEC
3 available output power should be
The signal voltage swing in an available to drive other transistors.
all-transistor system is usually FIG. 8-Characteristics of double -trigger-
Further, since currently available
chosen as a compromise between ing circuit using 5-mc transistors high -frequency transistors are ex-
191
ELECTRONICS-March 1, 1957
 unity (this must be true if there that nl is about 24. Power
supply
exists a minimum power level to drain is 50 mw + 2.5 mw,
so that
process intelligence). n, is about 0.95.
In most present transistor cir- Two of the circuits of Fig. 2
cuit designs, a high percentage of may be coupled together, with
only
useful output power from the tran- slight modification, to form
the bi-
sistor is dissipated in the load re- stable circuit of Fig. 3.
This
sistors. This is especially true for several drawbacks, however. has
direct -coupled logic. Therefore, the low -voltage level is not fixed, The
value of n2 may be increased sig- dependent on loo and
being
other factors.
nificantly by removing the stand- The power dissipated
in internal
by power dissipated in this area. load resistor RL (in shunt with the
The circuit design techniques in actual load) may
be an appreciable
the following sections show how percentage, particularly
the values of ni and n2 may be in- put power levels. For
at low out-
creased to give minimum power time (when the transistor
fast fall
is turned
dissipation, maximum speed and off) , RL must be made
FIG. 9-Nonsaturated current -demand sin- small.
minimum sensitivity to component
gle -triggering flip-flop and transistor drift circuits. Current -Demand Circuit
Maximum -Efficiency Circuits A circuit that circumvents these
disadvantages is shown in Fig. 4.
Aside from eliminating the Here essentially all of the
power dissipated in load resistors, current (collector current)
output
is avail-
an additional gain in system power able to drive load RL.
efficiency may be obtained by using Standby power is low; when
circuits that draw power from the there is no load, the power
supplies according to the power and from the supplies is approximately taken
demand at the output. This proc- equal to the dissipation
2 I,,'R,
ess always involves feedback. Cath- in the base resistors.
Both the
ode -follower and emitter -follower high and low
voltages are clamped
(grounded -collector) circuits do (the transistors saturate).
this, but unfortunately have no The
voltage gain.
A transistor circuit involving
voltage gain, along with an ability i

to convert d -c power into signal

power as required by the load, is
/ ,330 -OHM COLLECTOR LOAD
SHUNTED BY 220µµF

shown in Fig. 2. The transistor

FIG. 10-High-speed nonsaturated cur- dissipation is low and the output
rent -demand double -triggering flip-flop '----330-OHM RESISTIVE
power is high for collector currents COLLECTOR LOAD

less than the maximum output cur-

tremely low-power devices (on the rent. The major portion of the 0.2 0.4
TRIGGER WIDTH IN µSEC
0.6
order of 0.5 me-watt as a figure power drawn from the supplies is
of merit for SBT-100 at 50 me and available at the output for dissipa- ..aGGER WIDTH
10 mw), circuitry should be de- tion in the load resistor, so that n2
signed to give highest possible approaches 1 and the circuit draws
energy conversion efficiency. The from the supplies only the power 0.2 -µSEC 0.5 -µSEC/
ratio n, of useful signal output dissipated in RL and R, (neglecting - TRIGGER TRIGGER/
WIDTH
power to transistor dissipation transistor dissipation). The only WIDTH-

should therefore approach infinity.

,

transistor parameter of importance 4 a 6 1.2

MINIMUM SET-RESET TIMEIN µSEC
For optimum circuit design of a in the conducting state is the mini-
minimum-power -drain system, the mum base -to -collector current gain FIG. 11-Triggering characteristics of flip-
ratio n2 of useful signal output ßv. flop of Fig. 10
power to power supply drain should To illustrate the design of this
approach 1. circuit, assume that ßN is 20, input
The product of n, and n2 should d -c voltage V, is 5 volts, transistor =-++-_
be made as large as possible. The saturated base resistance r, is 50 ---
SILICON
-SILICON
ratio represented by nl can be made
large by allowing the transistor to
ohms, V is 10 volts, R, is 10,000 KNEE--
0.7 V
ohms and RL is 1,000 ohms. Then GERMANIUM
saturate or by controlling the volt- I, is about 0.5 ma, I, ,,, is 10 ma IMA
age from collector to base through and I, is the sum of these or 10.5 --GERMANIUM KNEE
AT MA' 0.2V
I

the use of clamping diodes. How- ma. Useful signal output power is
ever, minimum -power systems can V I, or 50 mw and transistor
be built only by making n, close to dissipation is 10.5 X 0.2 mw, so FIG. 12-Diode characteristic curves

192
March 1, 7957 - ELECTRONICS
 signing the circuits to operate in VT

the nonsaturating mode is de- TJL (CLOCK PULSE)

.I I.
creased switching time. Figure 9 Iol Re
W

shows a typical design using the

vc2 T
nonsaturated configuration with
Vcl
11c
single triggering. Figure 10 shows
a higher -speed version using double
triggering, and Fig. 11 gives trig-
I I

Vbbº Vbbt
gering conditions for the circuit. EiI
The diode characteristics in Fig. 12 =-Vcc
show why these back-clamped cir-
cuits do not allow the transistors Vb

to be saturated.
If silicon transistors are used,
INPUT
CLOCK

i II

IERE+RBII-a)
VL-;
L'
p `Ì
--
the nonsaturated circuits do not re- [

.ilA
FIG. 13- - Family of collector curves for 17
silicon transistor quire the four silicon diodes. This VbbItVL I
' `ZCE
I

I I

may be seen from the silicon col- UNCERTAINTY; I

RE O N
I

-
I I

GATING
II

lector curves in Fig. 13. The basic

I

WAVE-
FORM -21-A
-Vbb -Vbb
circuit using silicon transistors is I REFERENCE
I T`RsCc

-Vee Rib
Si Si
shown in Fig. 14.
I
Rib (Vbbl)
I

Rb Rb UUU

The salient features of the satur-

ated back-clamping current -de- FIG. 15-Circuit and waveforms of pulse -
mand technique are low transistor level gating circuit
dissipation, high conversion effi-
ciency, insensitivity to component
and transistor parameters (stand- Fig. 15 along with its gating wave-
by load resistors not needed), in- forms.
+vbb +Vbb
sensitivity to voltage supply drift, Conclusions
FIG. 14-Basic silicon transistor circuit for maximum system efficiency (power
nonsaturated current -demand flip-flop drawn from supplies according to The reliability of transistor
needs of load), fast rise and fall switching systems is closely related
tolerance on all resistors may be time (inherent overdrive) and loop to the design of circuits. The cir-
large (on the order of 50 percent). delay (caused by saturation time). cuit designer must consider the
Circuit operation is substantially Nonsaturated circuits give in- drift of operating points caused by
independent of transistor para- creased operating speed because aging and ambient self-generated
meters. The stability of the con- they have no saturation delay, but temperature changes. For high-
figuration is insensitive to supply are otherwise identical. speed networks, due to the lack of
voltages. The configuration leads to high-speed transistors, overdrive
fast rise and fall time since large Gating Circuits must be used to speed up the cir-
transistor overdrive is inherent. cuit response.
The last three advantages accrue The design of maximum -reliabil- Transistors are inherently effi-
because the configuration allows ity switching systems depends cient devices (both voltagewise and
the transistors to set their own heavily upon the reliability of the powerwise). This, along with the
levels. Some of the operating char- voltage -pulse voltage -level gate. fact that two types of transistors
acteristics of the circuit are shown To assure maximum system reli- are available (npn and imp), al-
in Fig. 5. ability (assure positive action and lows circuit design that is ex-
One difficulty with the circuit of suppress superfluous triggering), tremely efficient in terms of power
Fig. 4 is that there is an appreci- the gate circuits should be inde- supply drain for a given signal
able delay around the loop because pendent of pulse width, pulse am- power output.
the conducting transistors are plitude, pulse repetition frequency The transistor, being an efficient,
saturated. This difficulty may be and pulse level (within given reliable and small device, may be
minimized by double triggering limits), and should have fast re- soldered into systems much as are
(triggering all four transistors sponse to pulse and level changes. ordinary resistors and capacitors.
simultaneously) . The current-de- The circuit design should also be in- This, plus the fact that it is basic-
mand flip-flop circuit of Fig. 6, em- sensitive to component values and ally a three -terminal passive device
ploying this feature, gives the char- transistor parameters, require min- which can produce power gain,
acteristics shown in Fig. 7. By imum standby power, have high makes its use attractive in net-
using 5 -mc transistors in this output power, present a constant works where feedback techniques
circuit and changing all 510-14 load to the pulse source (driver) are widely employed.
capacitors to 200 µµf, the charac- and deliver standardized output The research work herein de-
teristics of Fig. 8 can be obtained. pulse and level amplitudes. scribed was supported jointly by
The circuit techniques described A circuit configuration that ful- the Army, Navy and Air Force
may be extended to nonsaturating fills to a high degree the above re- under contract with Massachusetts
circuits. The primary gairl in de- liability characteristics is shown in Institute of Technology.

ELECTRONICS - March 1, 1957

193