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Edge Detection Canny Algorithm Using Adaptive Threshold Technique

Chapter · January 2021

DOI: 10.1007/978-981-15-5679-1_45

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 EDGE DETECTION CANNY ALGORITHM USING ADAPTIVETHRESHOLD
TECHNIQUE
R N Ojashwini, R Gangadhar Reddy, R N Rani, B Pruthvija

ABSTRACT— Detection of edge is most basic operations 3. Irregularities according to the properties of the
which is needed in processing of objects in image processing material.
identification. Hence edge detection is the most likely
operation for the processing of image in real time applications 4. Illumination according to the image sequences.
with optimized results which is accurate and architecture with
less complexity results in less latency. Hence edge detection One of the standard detection algorithms for the
with adaptive threshold technique plays a vital role in present detecting of the edges is the canny algorithm where the
day edge detection techniques. The computation is carried threshold values are physically given, where calculations are
with threshold values which are automatically adopted done according to the image specifications according to the
according to the image specification which helps to reduce the size, color and orientation of the image sequences.
memory and computations along with decision making will
take less time. Hence delay gets reduced with improved The point that need to be considered in edge detection
detection performance along with increased efficiency. The techniques, the object that has to be detected should separate
proposed architecture is implemented using Xilinx system from the background then edge detection process is applied for
generator tool on Spartan6ATLYS board. the detection to get the outline of the object, hence edge
Keywords—Canny edge algorithm, adaptive threshold detection become important thing in visioning and processing
technique, system generator, Xilinx ISE 14.5 tool, parallel of image.
processing.
In the original canny detection is based on the frame
level statistics that is complete image is considered as single
1.0 INTRODUCTION frame and the threshold value is depend on the specifications of
Detection of edges are the set of mathematical calculations the image according to the mathematical calculations of the
with different methods that are adopted according to the canny algorithm. Hence computations has to take place for each
specification of the image, the value of the pixel has more image sequence, hence canny algorithm has more computations
discontinuity at the edges as compared with the remaining part and has more complexity with higher latency which results in
of the image. Hence only the detection of edgesneeds different less efficient and less computational performance.
mathematical calculations that are adopted to get efficient
results. The contour of the image is helpful to identify the image The another technique has been introduced for the
as an object for edge detection. Edge detection will gives the edge detection process which is block based statistics that is
outline of the image which is pre- processed according to the each image sequence will divide into block and each block get
specified image calculations with adaptive threshold technique. processed and detection of the will take place and each block
has processed and pipelined to get the edge of the processed
The edge detection techniques will have the different image.
orientations:
2.0 LITERATURE SURVEY:
For the particular image sequences different adaptive In [1]–[3], The filter Deriche has been derived from thecriteria
thresholds are adopted for the image depending on:
of Canny and has been implemented on the ASIC platforms
1. Depth variations.
which is base for the configuration, consists of minimum of
four transputers that can easily detect the edgesof 256*256
2. Variations in the image sequences according to the
with minimum time of 6seconds for the configuration of real
orientation.
time applications.

1
In [4]–[6], these three papers explains about the Canny edge GAUSSIAN FILTER:
detection algorithm which is FPGA- based block level It is one of the two dimensional operator applied for
platforms. There are two types of implementations in [4] and convolution which is adopted to reduce the noise in the input
[5] Which directs and explains about the software design that image. The matrix that represents the kernel of the system that
is VHDL or Verilog has been directly [6] converted according is in Gaussian shape with bell shaped representation.
to its hardware design tools which are of system-level that
The matrix represented as below:
results in decreased performances according to its given time.

In [7] , the paper explains about the adaptive threshold

technique for the canny algorithm which is proposed for the (1)
system of robot that is automatically adapted, the algorithm Where, d0 to d8 are the 3x3 image sub-matrix pixel values.
based on the high and low thresholds according to its fore The given image which is consolidate into blocks and each
consolidated blocks get divided into 3*3 matrix along with the
ground and back ground images based on the input image for
standard deviation value, increase in the standard deviation
implementation which is based on the Altera Cyclone FPGA. value the blurring of image is more, hence with the determined
standard deviation value along with the Gaussian filter co-
In [8] [9] [10], the General Purpose Graphic Processing Unit efficient the convolution will takes place which results in the
(GPGPU) has emerged for the parallel processing of the image smoothing of the image.
for multiple applications with different input image
specifications with double thresholding, non-maximum The representation of the image is as follows:
suppression, hysteresis the above paper explains about theeach
step analysis and according to it specification which is adopted
dynamically.

3.0 SYSTEM ARCHITECTURE

Fig 2: Gaussian graphical representation

Gaussian kernel 2D definition is as follows:

(2)
Where is the Standard Deviation.

The moving window architecture to implement 3x3 image

sub-matrix is shown
Fig 1: Proposed Diagram of adaptive threshold Canny Edge
Algorithm

PRE-PROCESSING:
This is the first step in adaptive threshold technique of canny
edge algorithm is to resize the input image into suitable size
(256 * 256) and the resized image get converted into a grey
level for the purpose of hardware optimization.

2
 FINDING GRADIENTS:
The Modified Canny operator uses two 3x3 kernel matrix one
is horizontal gradient and one is vertical gradient. They are as
follows:

(4)

Fig 3: Moving window architecture (3x3 pixel generation)

In the moving window architecture or in 3x3 pixel generation

block nine shift registers and two FIFO structures are used. The (5)
architecture of the shift register is as follows The convolution of the image is according to horizontal and
vertical directions according to its gradient. And the magnitude
is calculated from the below ,

(6)
From the moving window architecture pixel values are taken
and the convolution of the image is according to horizontal and
vertical directions according to its gradient. The hardware
Fig 4: Shift register block diagram structure is implemented by using only shifters and
To access 3x3 pixel the above architecture is used shift register adders/subtractors.
is part of this architecture. Here in the shift register if the clock
is high the data will move to the output variable or else the input
variable is assigned with the previous data. ADAPTIVE THRESHOLD:
The architecture of the FIFO is as follows:
This is the step where canny algorithm get differentiated from
the adaptive threshold technique for the detection of the edge.

In the originally canny threshold values are manually given ,as

a result the computations will get increase but in the adaptive
threshold technique the threshold values are automatically
adjusted according to the image specifications.

To calculate adaptive thresholding value the equation is as

follows

(3)
Fig 5: FIFO block diagram Where S is the summation, N dimension of the input image
(N=256x256) and A1, A2…AN are the intensity values of the
FIFO is the part of the 3x3 pixel generation block. After image pixel.
convolution with the Gaussian kernel noiseless image is found.
Three modes of suppression needed for the final edge detection
which as low in magnitude, medium dark edges and the sure
shot edges.

3
NON MAXIMUM SUPPRESSION: Edge pixels weaker than the low threshold are suppressed and
edge pixels between the two thresholds are marked as weak.
The non- maximum values are removed in this process in the
given image based on the threshold values. It is used to suppress EDGE TRACKING BY HYSTERESIS:
the low in magnitude edges.
This mode of suppression is mainly used for medium intensity
There are many steps: images. Here the comparison of the each pixel with the
corresponding eight pixel values in all corresponding
1. Let us consider the single pixel value θ and round the directions. According to the threshold values by comparing the
gradient direction into corresponding nearest value to larger value pixel will remain and the remaining lower pixel
the 450 according to its eight connected neighbor values get suppressed.
values that is the remaining direction pixel value get
4.0 SYSTEM DESIGN:
suppressed because the lesser in the threshold value.

System generator is instrument created from Xilinx

2. Here the comparison of the current and corresponding
that enable usage of Simulink design environment for FPGA
edges, that is according to its gradient direction. If the plan. Designs are captured as block-set in Simulink modelling
direction of the gradient is north (θ=900).Hence the environment and all FPGA implementation steps are performed
comparison will takes place bothin north and south without human intervention to produce FPGA programming
direction according to its thresholdvalues. files.
More than 80 DSP blocks are delivered in XilinxDSP
block set for Simulink such as registers, multipliers, adders. It
also offers combination platform for design of FPGA that allow
3. The edge gradient direction considered as, RTL, Simulink components to come organized in single
Del+={(1,0) (1,1) (0,1) (-1,1)} simulation and employment environment.
Del-= {(-1,0) (-1,-1) (0,-1) (1,1)}
IMAGE PROCESSING:
Let us consider for the each pixel value (i,j):
When image pre-processing is done using mat lab, it delivers
4. The direction of the gradient is normal to the edge inputs to FPGA as vectors which is appropriate for bit stream
D=(Dir(i,j)+ )mod gathering by system generator. Following functions are done
for image processing.
5. If the magnitude is smaller
than any one of its neighbour, along the gradient PRE-PROCESSING PROCEDURE:
direction d then In(i,j)=0 otherwise
1. Data form alteration: it alters image to unnamed integer
In(i,j)=magnitude(i,j)
setup.
6. If
2. Buffer: changes scalar illustrations to frame output. It’s
magnitude(i,j)<magnitude(i,j)+Del+(d) then In(i.j)=0 done at low sampling level.
else if magnitude(i,j)<magnitude(i,j)+Del-(d) then 3. 2D to 1D converter: it alters 1 dimensional image to 2
In(i,j)=0 which results in thinned edge image or else dimension image matrix.
In=magnitude(i,j).

DOUBLE THRESHOLDING:

This mode is used to suppress the shot edges. The thresholding

is takes place between the background and foreground
threshold value.

Low threshold corresponds to the back ground = 0.66* mean

value of the pixel.

High threshold corresponds to the foreground = 1.33*mean Fig 6: Image pre processing
value of the pixel.

4
POST-PROCESSING PROCEDURE: 5.0 RESULTS:

1. Data form alteration: it alters image to unnamed integer

setup.
2. Buffer: changes scalar illustrations to frame output. Its
done at low sampling level.
3. 1D to 2D converter: it alters 1 dimensional image to 2
dimension image matrix.

Fig 7: Image post processing

Fig 9: Edge detected by adaptive threshold technique

Fig 8: System model

Fig 10: Device utilization summary

5
 Pacific IFIP Int. Conf. Very Large Scale Integr., 1995, pp. 811–
Device Utilization 816.
[3] F. G. Lorcaaa,, L. Kessalaa,,, and D. Demignyaa,,,
Logic Utilization Used Available Utilization ‘Efficient ASIC and FPGA implementation of IIR filters for
No of Slice Registers 533 69120 0% real time edge detection,’ in Proc. IEEE ICIP, vol. 2. Oct. 1997,
pp. 406–409.
No of Slice LUTs 5478 69120 7% [4] D. V. Raao and M. Venkatesanan, ‘An efficient
reconfigurable architecture and implementation of edge
No of fully used detection algorithm using handle-C,’ in Proc... IEEE Conf.
373 5638 6%
LUT-FF pairs ITCC, vol. 2. Apr. 2004, pp. 843–847.
[5] H. Neoha and A. Hazanachucka,.. ‘Adaptive edge
No of bonded IOBs 28 640 4% detection for real-time video processing using FPGAs,’ Altera
No of Corp..., San Jose, CA, USA, Application Note, 2005.
4 32 12% [6] C. Gentsos,. C. Sotiropoulou,.. S. Nikolaidis,. and N.
BUFG/BUFGCTRLs Vassiliadis, “Realtime canny edge detection parallel
No of DSP48Es 1 64 1% implementation for FPGAs,” in Proc. IEEE ICECS, Dec. 2010,
pp. 499–502.
[7] W. Hea and K. Yuana,,, ‘An improved canny edge
Fig 11: Availability of devices and its utilization summary detector and its realization on FPGA,’ in Proc... IEEE 7th
WCICA, Jun. 2008, pp. 6561–6564.
Results analysis explains about the detection of efficient edge [8] I. K. Paraka, N. Singhala,, M. H. Leea,, S. Choa,,. and C.
analysis by adaptive threshold technique, where the W. Kim, ‘Design and performance evaluation of image
implementation of parallel processing , which results in the less processing algorithms on GPUs,’ IEEE Trans. Parallel Distrib.
computations because the each frame get divided into blocks as Syst..., vol. 22, no. 1, pp. 91–104, Jan. 2011.
a result delay will be less due to parallelprogramming and the [9] J. D. Oweansa et al…,, ‘A survey of general-purpose
memory utilization will be less. computation on graphics hardware,’ Comput. Graph Forum,
vol. 26, no. 1, pp. 80–113, 2007.

6.0 CONCLUSION AND FUTURE WORKS

The thesis describes the “Implementation of Canny Edge
Detection using adaptive technique” that used to detect the edge
of any image as a complete image with dividing it into blocks.
The proposed Block level Canny Edge detector has overcome
the limitation of existing edge detection algorithms by reducing
the delay and area.

The design of Block Level Canny Edge Detector is coded in

VHDL language. The simulation and synthesis of the design is
carried out using Xilinx ISE 14.5 tool.

The proposed method takes less area and less computational

time result of this decreases latency and increases throughput.
In Future, it can be possible to propose dynamic based edge
detection algorithm which can adapt for different variations of
lighting conditions in image and also can be extended to video
processing in detection of real time edges required for
broadcasting.

REFERENCES:

[1] R. Derichee,,,‘Using canny criteria to derive a recursively

implemented optimal edge detector’, Int... J. Computer. Vis.,
vol. 1, no. 2, pp,… 167–187, 1987.
[2] L. Torres, M. Robert,.., E. Bourennaneae, and M.
Paindavoineae, ‘Implementation of a recursive real time edge
detector using retiming technique,’. in Proc.... Asia South

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