DIGITAL

TECHNIQUES

Student Workbook

RcviscdBy: LeeAnneFarr
Educarional MediaDesigner

EB^aOl.41
595.35KX
Digital Tcchnlques, Fourth Edltton
Copyright e 1993.1990.1985. 1978 by HMÙICompuiy. Bcnton
Haxbor. Midugan 49021 AHrights icsCTvcd. Printed in the Uxutcd
Suucs of Amcrica. Exccpi as penniued under the Uniud Siatcs
Copyright Aci of 1976. no pan of (his publication mvy bc
Teproduocd or discributed in «nyftnm or by «nymcuu. clecBxmic
or rocciDnuciiI. mctading phoiooopyins, Tccoriing. norage in a
database or rericval syttnn, or otherwise. widiout thc prior
pennBsion of thc publishcr.
Not offîliaïed with D.C. Heath, ïnc.

ISBN 0-87119.222-5
 Dlgltal Technlques j3

Contents
Intioduction.....................................................J

Pansljst........................................................6

Experiments
Expcriment 1—BipolarTransistorSwitdi...........................11
Experiment 2—Logic Invcitcr ....................................17
"Expemneat 3 — Diode Logic Gatcs.............................. ..^7
Expcrimcat 4—TransistorLogic Gatc ..............................35
Expeumeat 5 —- TILLogic Gates. .................................39
Expcrimcnt 6—CMOS Logic Gates................................47
Bqpcnmcnt 7—ApplyingNAND andNOR Gaies. .................. .^5
Esqpeximau 8—Tlc Wred-AND ComiccrioiL........................65
Experimutt 9—Sct-Rcset Flip-Rops ...............................75
Eiiperiment 10—D FUp-Rops and Rcgisters..........................79
Expcrimcnt 11 —JK RUp-Hops. ....................................85
Experimait 12—Biiiary Coiimcis. ..................................91
Expcrimcnt 13—TheBCD Countcr ................................1(;2
Experimcnt 14—Counter AppUcarions. .............................107
Expeiùneml5—ShiftRegisters...................................113
Expemaest 16—ShiftRegisterAppIications........................ .121
Eiqieriment 17—Qocks and One-Shocs.............................131
E3q»eriment 18—Dccodcrs...................................... .139
Expcriment 19—7-Segment Decoder-Driverand Display ...............145
Eiqperiment 20—Miltiplexers................................... .151
Experimcm 21 —Exchisive-OR/NOR.............................. .161
Expcriment 22—Exchisive-OR/NOR Applicarions ....................169
E3qperimcnt23—ScnuconductorMemories..........................183
Expeximeat 24 —DigitaI-to-AxialogConvcrsicm. ......................191
Expcrimcnt 25—Aiulog-to-Digital Converrim. ..................... J2G3
Eîiperimcnt26—PracticalDigital Troublcshooting ...................2Ï3
4 ISTUDENTWORKBOOK

Unit Exammations
Unit I Examuurion- "fatroductionto Digital Techmques ............. ^25
Unit 2Examinatimi- ScnuconductorDeviccs for Digital Qrcuits ...... ^27
Unit SExamination- "DigitalLogic Orcuits ..................... ..^31
Umt 4Examinatioa- "Digital Integratcd Circuits.....................235
Ifeit 5Exanunatkm- "BoolcanAlgebra........................ ...^41
Unit 6E3Eaminati<M»- -FBp-FIops and Registcrs ..................... ^47
Unit 7Examination- "Sequcntial Logic Grcuits .....................251
Unit 8 Examuiation- "Combinational Logic Circuits..................255
Umt çExaBMnatiCTi' "SemioonductorMemorics.................... J26Ï
Unit 10 Examination " "Digital Appiications......................... ^67
Unit 11 Exammatiai " "Digital Troubleshootmg...................... J73

Appendu A
IC Pin Assigmneni Diagrams A-I
 Dlgltal Technlques J5

Introduction
"nris Woricbook comains 26
practical aqicrimcats that iUustraae many of Ac
comxpts prescated in the tcxt. WIrilc thesc cxpcrimcats arc intended to use a
" Hcatlridt Digftal Traincr, faeycan bc unplemcntcd m othcrways. The foUowing
componaats are required;
" PowcrSupplies
+ 12V at 100mA
- 12V at 100mA
+5Vat500mA
" PulseGcDeratorwithTTLcompatiUeouqnitsof:
1 Hz. 60 Hz (Une). I UIz aad 100 kHz.
" Fourtogic switdies
" Two "dcbouaced" swiiches
" FcxnrLEDaidicaiors
" Soldedess breadboarding Uodc tihat will hold up to ei^u. Ï6-pm
duaI-in-IincICs.

Thc fifllowmg sdiedulc is suggcsicd for pcrfomung thc csqnrimcnts.

Eiqperimcntl aftcrUnit2
Expcrinicutt 2,3, uul 4 aftcrUnit3
Expcdincnts 5 and 6 aftcrUnit4
E^crimcnts 7 and 8 aftcrUnitS
Eîqpeiùncnts9,10, aad 11 aftcrUnit6
Experimcnts 12.13.14,15.16. and 17 afterUnit?
Experimcnts 18,19,20,21, and 22 afterUnitS
E3q)Ctunent23 afterUmtP
Expnunous 24 and 25 aftcrUmt 10
Eiçunncnt26 afterUnitll

An cxammation for cadi urit is also indudcd m tius Workbook.

A pin assigmncnt diagram for cach IC used in this coursc is comamcd in Appcn-
dix A atfhe cnd offliis Woikbodc.
6l STUDENT WORKBOOK

Parts List
This is a list ofalloftfac parts uscd in ciqperimaus wfaidi you wfll pcrfpnn with
dns coune. Thc key number in titus pans list coxresponds to the numbers m thc
pans picioriaL Some parts are padcaged in cnvdopcs. Excqrt for ttus uritial pans
chedc, fccqp tfaesc parts in thdr cnvdopes until they are caUed for m the
caperimenL A containcris provided so fhat you can kcep thc smaU pans together
uitaicplaoe.

KEY HEATO QTy. DESCRIPTION

No. PartNo.

Reslstor(5%)
A1 &.102.12 2 1000Q(bro»ifrbtoek^d)
A1 M72-12 2 47DOQ(yritow<Ka<«4«t)
A1 6.103.12 2 10k0(b(owfrbtod(.owit»e)
A1 M73-12 1 471(Q(yBBoiwiiol»fromn(»e)
A1 W24.Î2 1 220k0(mdwtyrttow)
A1 M61.12 1 5600(fln»frbhi»t)ro*m)
1M11 1 SUICSonttol
10412 2 lOI(QCo(tfrol

Capacltore

Ceramte
A2 21-1B2 1 0.1ftF(100

EtectrolyUc
A3 2M75 2 1000»iF
 Digital Technlques j 7

KEY HEATH QTY. DESCRIPTION

No, PartNo.
NOTE: MEATM PART NUMBERS
ARE STAMPED ON MOST DIODES.
Diode-Led Dlsplay Transistors
A4 56-56 2 1N4149stCcondode
A4 56-59 1 1 N52308 4.7 V2ener
A5 411-885 1 7segmentRDdisplay
A6 417-801 2 MPSA20 transistor

NOTE: Transistors and integrated circuits are marked <or

klentiffcation in one of the (ollbwing ways:

1. Partnumber.
2. Type number.
3. Part number and type number.
4. Pan number with a type number other than the one
listed.

Integrated Clrcults
A7 442-21 1 1458
A7 442-751 1 1408
A7 443^80 1 7495
A7 443-694 1 8368 or
443-1802 1 14495.1
A7 443-695 1 4001
A7 443-728 1 74LSOO
A7 443-745 1 74LS03
A7 443-755 1 74LS04
A7 443-764 1 2114
A7 443-778 1 74LS02
A7 443-780 1 74LS06
A7 443-781 1 74LS75
A7 443-7B8 1 74LS20
A7 443-807 1 74LS42
A7 443^13 1 74LS90
A7 443^15 2 74LS193
A7 443-829cr 2 74LS76
443-1755
A7 443^78 1 74LS151
A7 443^91 1 74LS86
A7 443.942 1 74LS123

Miscellaneous
26&W2 1 SmaB pans contaioer
344.52 10' Redwire
490-111 1 10 pulter ^^
8l STUDENT WORKBOOK

CAUTION

1. Bc ture that aU powcnd cquqaneot is mnff»*h*rf 10 thc same powcr

aouroc. Tlris wfll estaUisfa a cooanon reference and picvcnt ground loops.
2. Make surc you do NOT nudvenenuy uBcn a ground itao die drcirit
under tut This ooaM occcr, for ^vnp^. if your tett cquipincnt icfcrence
(pound) lead is carth grouadcd.
Uae an (rtmuneter, "ettoRxI.toseciftIictest equipmaa refcreaoc Ie«I
is cartb grounded. Measinc bctwcen refennce lead and die ccnaer prong
on die powcr jdug. If tiae reading is zero. your cquipmcnt is carth
gnxunded. Ifit is earth grouaded. aU measureacnts MUSTbe referenced
lOgrouDd.

3. The 9ocai9cy of your cxperimetds may vaty slighfly with thosc of odier
aandents w examjAes givcn in tbe tcst This is bccausc ofoomponent pan
toletuccs, mcter cdibaation. md fite indwiduri inictpolation of tfae
metcr's nadiqg.
 Dlgltal Technlques | 9

Experiments
10 ISTUDENTWORKBOOK
 Dlgltal Technlques | 11

Experiment 1
Bipolar Transistor Switch
Objective
To demonstrate the operation. characteristics and design ofa saturated bipolar
transistor switch.

Materials Requîred
Votancter (vom or TWSM)
Hcathkit Digital Trainer (Refcr to tbc Trainer xiianual for operations details and
breadboardiqg proocdures.)

1 -NFN transistorMPSA20 (417-801)

l-560Qrenstor
1 -1 U2 resistor
l~4.7kftffcsis(or
I-lOltfïresisior
I-220kQresistor

Procedure
1. Consmxct the drcuit shown m Hgure El-1 (m the solderiess breadboaid-
iag Uock. Thc drcuit rcceivcs fts iiqnit from data switch SW1. You will
monitor the ouçutat tt»coUcctor with a voltmcter. Sce Rgure El-2 for
transisior basc details.

45V

DATA

^^RB-^O
INPUT—»-—W^
V|

FigureEl.2
FigureEl-1 Lead connections
Inveitcr circuit for Stqï 1 . for 417-801 transistor.
12l STUDENT WORKBOOK
Set SWI to thc down (LO) position and measurc the DC output voltage
CVo) widl nspect to ground. Rccord below.
Vo= volts.

The inpat voltage at this timc is

Vj = _ vdts.

3. Sct SWI to the np (HD position aad measure the circuit DC input voltage
(VI) witfa respect to ground. Rccord bdow.
Vj s= _ volts.

Ncxt. measure fbe followiag tnansistor junctiai voltagcs base-to-emitter

0^) basc-tD-coUcctor (Vag). and coBcctor-to^Duner (Vag). Rccoid your
valucs in Table I using thc Rg = 220 k0 row. Be siire to note thc polarity
of cach voltage so that you can detennine whcthcr tbe junctions arc for-
ward or revcise-Uascd.,

TABLEI
R» VK Va, VCE=VO Is thc iransistor satnratcd?

220 kû

4.7 kQ

4. Mcasure thc voltagc drop aciioss dic 220 ku basc resistor (Vf^ anr? thc
voltagc across Ae coBct tor resistor ÇV^ç)and reconl m Table II in th;; Rg
c 220 IcQ column. Using thcsc voltagcs and assodatcd rcsistor valucs,
calcûlatcflie basc cuncnt (Ig) and colleciorcurrent CIc) vsmE Ohm's law.
^VM
IB=
RB~

'c^
 Dlgltal Technlques j 13

Rccoid yourvalues m Table II. Also calculatF; tfac rario Ic/Ig aad rccond m
TaUeIL

TABLEH
RB«=220kû RB«=4.7kQ

VKB

V«c

k
Ic

IC^B

5. UsingthccriterionttiatstatesatraDsistorissaouatedifthcI(/lB<hpgand
thc data in Table II, dctenninc the coDdition ofthe transisior assuEauag b^
=100.
Is thc transistor saturated?

6. RcpIaccthc220kr2bascresisiorRBwitha4.7kûrcsistor.

7. Rqicat Step 3. Mcasure Vgg, Vcg, and VQ and recotd m Tablc I. Study
youricsults.
8. Rqîcat Stqï 4 itcording your data in Tablc II.

9. RqpcatStepS.Isthctraiisistorsaturatcd?, _

Discussion
Jn Step 1 you consnuctcd a bipolar transistor switcfa. In Slep 2 with the ngrot
&om SW1 (LO or ground), thc E-B junction is not forwaid-biascd, thcrcfore tbc
transistor is cut ofF and the output voltagc you measured was Vçc = +5 volts as
sccn through the 1 kûcollector rcsistor.
14 JSTUDENTWORKBOOK

In Step 3 you applicd forwaid-bias to thc cmittcr-base junction of uic transistor

fium thc +5 volt logic Icvcl ouîput ofSWl througii tbc 220 ki2 basc resistor. Thc
tnmsistor coxiducts. This is indicated by thc jimction voltagcs. You should havc
measured a Vgg in thc 0.6 to 0.8 volts rangc with the base posirivc with rcspect
to thc cnuûer. Vçy should havc beca coc volt or so with thc coUector posirivc
witb respect to thc basc. Thc coUcctor-uxmittcr voltagc Vcg should havc bccn 1
to 4 volts with tbc coUector fhc most posirivc dcmcnL Tbe cmitxcr-basc junction
is fonvari-biased îund thc basc-coUector junction is revcne-biascd. Scc Figure
E1-3A for a sununaiy ofthc transistorjunctioo vohagc polaritics for a properiy
biascd transistor. With this arrangcmcnt, thc tiaasistor conducts but is not
saturatcd. The traiisistoris opcrating somcwhcre m its liocar rcgion.

's
Bccause wc do not laiow the cxact valuc of t^. your voltagcs for Vcg aad Vc^
may not be cxactly cqual lo tbosc givcn abovc but thcy should be closc.

*
VCB» UV^- VCBsO^V,

VCEs2V -^îl- 0.1V

VBEsO.TV^ . VBE=C.TVV .

FigureEl-3
NPNTransistor
Junction bias polarirics.
In StqïS 4 and 5 you dctemuncd thc coUcctor and basc cu"1cats by mcasumig thc
voltagc drops across the base and collcctor resistors thcn dividing by thc rcspec-
tivc resistor valucs. Tbcn you dctcimincd if thc rado ïç/ï^ was cqual to, lcss
than. or grcatcr than thc assumcd b^ valuc of 100. If Icfl^ < hra Acn uxt vw'
sistor is saturatcdL In this stcp you should bavc found ^ to bc hi^r than hpg.
Obviously. tfae transistor is aot samratcd. What you calculaied wbcn you dividcd
by IB was tfac tiuc gain or hpg of thc transiscor. It should havc been greatcr
thanIOO.
In Stcp 6. you rcplaced thc 220 kT2 basc resistor with a 4.7 kO resismr. This pro-
vidcs more basc'drivc currcnt In Stq) 7 with +5 volts appUcd 10 the input, the
tranastor c<Sducts. but this omc much faarder. Tïsc juocdon voltagcs should_be
=0.6 vol^ VCE = 0;1 V01L >nlc
^roximatdy as fdlows: Vgg = 0.7 volt, VCB
kn bascrKistor^vCB^S
^îarirics of Vgg and Va arc'as bcforc. But with the 4.7 'niis indicatcs that the
sucb tfaat thc basc is more positivc than tfac colkctor.
basc<oUcaorjunction is forward-biascd wbcrcas, with tfac 220 kt2 basc resistor.
it was icvcise-biased. With both the anicer-base and basc-coUcctor junaions
fbrwaid-biascd, thc transistor is saturatcd. Thc ouiput voltagc VQ or Vag »s tbe
diffciencc bctwccn V^ and V^. Sce Rgurc E1-3B.

In Stcps 8 and 9, you again dctcnniDcd Ic, Ig, aod ï^y. In this casc. you should
havc found Ic/Ig to bc less than a Dominal hpg of 100. Thcreforc. thc transisior is
saturated.
 Dlgltal Technlques 117

Experiment 2
Logic Inverter
Objectîve
To demonstraïe the operafion and characteristics qftypicaî discrete componenï
wid integrated circuit hgic inverters.

Materials Required
HcadddtDigitaITraincr
DC Volnnctcr

2 - MPSA20 tranristor (417-801)

2-IkÛresisior
2-4.7kQreastor
1 - 74LS04 TII- bex invcner intcgraicd circuit (443-755)

Procedure
1. Wre the cireuit shown to Rgure E2-1. "nic uqmt is dcrivcd uom data
switch SWI. You wffl measure the output statc with your voltmcter and
obsuvc itonIJED indicsuorLL

BATA 4.71(0
swncH —<"
swn V|

FigureE2-l
18 ISTUDENTWORKBOOK

Mcasuxe the mvcner ispvt and oiiqnit voltagcs Vj aiid VQ with rcspcct to
grouui for both positions of daia switch SW1. Rccord your data m TaUe
L

TABLEI
SW1 V, Vo
rosmoN
DOWN

UP

From thc data in Tablc I, answer the following quesrioas.

a. Does thc rircuit perform logic invcision?
b. What are the two ouqnit logic voltage lcvds assuming positivc logic?
binaiyO
binaiy l
c. Malcc a tnrtfa tabie fiom the data in Table L Use posidve logic and
assume thc circirit input is A.

4. Discomiect the 4.7 kûbasc resistor from input SW1 and Ict it hanig frec.
Measure the ouçwtvoltagc. VQ s= _. Wuh an ppen
mpai, thc ouqnit is binaiy_. An open input has the
samc cffcct as a binary_ inpuL CUsc posirivc logic.)

5. Connecttheficccndofthe4.7kubascresistortotheCLKoucutand8et
die dock ficquency to IHz. Connect LED indicators to dic cirouit ùçnits
and ouçutsas shown in Figure E2-2. Observe thc operarioo of thc circuit
by watcfaing ihe I.ED indicator states and their rclationship to oxic another.
The circuit output is always thc , of the input.

45V

T, LED
-—Ti
1HZ
OK RB-<:7kO

LED ^,
LZ

FigureE2.2
 DlgltalTechnlques J19
6. Modify your circuit as shown in Figure E2-3. Herc you arc cascading two
inveiter drcuits. You wOl monitor the input on LED indicator L2 and thc
output of thc secoad invener on LED Ll. Observe the wpat and oucut
statcs as the 1 Hz dock operatcs the drcuiL

îf the iiiput to the cucuit in Figurc E2-3 is binaiy 1, the putput wiU be bi-
nary _. Ifthe output is binaiy 0. the vspvtt. must be bmaiy

^5V

;1k0
! 1k O
l£D
L1

-^

MPSA20
417401

Rgure E2-3

Discussion
to Steps 2 and 3 you demonstratcd invcncr acrion. With input Vj cqual to zcro
volts, (SW1 <Iown), the cmitter-base fimction is not forward-biased so the tran-
sistor docs not conduct. The ouiput VQ is +5 volts as sccn through the 1 kQ col-
Icctor resistor. Widi +5 volts iicut (SWI up), thc transistor is saturatcd and tfie
ouçut voltagc is about 0.1 volts. Invcrsion is perfonncd. The posiave logic lcv-
ds are binary O = 0.1 volts and binaiy I = +5 volts. Tlie logic truth tablc you
consnucted for this drcuit slrould appear as shown in Tablc II below.

TABLEH
INPUT OUTPUT

A T
o 1
1 o
20 1 STUDENT WORKBOOK

The itput and ouçwtare cooaplemcntary.

ta Stq»4 you disoomiected the invener iqput and lcft it opca. Wid»tfais coodi-
tion, no fbrward-bias is applied to thc transisior so it does not conduct Tbe out-
put vottage at thc collector is +5 volts or tnnaiy 1. Thercfore, an open ucut pro-
duocs tbe tamc efifect as a binaiy O inpuL

ïn Siqp 5 you furtfaer demonsûatcd logic invcner actiOT. The 1 Hz dock was
used to drive tbe invcrtcr. You obscrvcd thc uyut and ovspat states on flic LED
indicators. Y<Mt rihould have found that thc ucwt aad ouqwt statcs werc always
thc pppositc ofonc anotfaer or comidcmcntaiy as indicatcd by LED's Ll and L2
wbiàbatematdy swiidi <m and ofîat a I Hz rate.

to Stqp 6 you cascadcd two invcner circuits and obsenrcd their opcrarion. You
shmild havc found that tfae outputofflie second mvcncris the same as the wpaL
(toc invcrtcr cancds the effisct ofdie otber. Thc output statc is thc samc as thc
iapat statc wheai an even munber of inveners is cascadcd.

Integrated Circuit Hex Invener

In the steps to follow, ymi wiU bc using a typicai TTL (cransistor-transistor
logic) mtcgrated circirit (IÇ)to demonstratc invcncr acrion. This 1C and all oth.
crs supplied m dus program are housed in a idastic dual in-lmc package (DIrO as
shown m Rgure E2-4. Both 14- and 16-pin versions are availablc. Notc thc way
in ^rich dw pms are numbered. A notch or dot (mdcntations. ctc.) is uscd to
^rd^niit^ Ac location of pin 1.

"ff^^-o,
is /^iiy5
i< ji^^-ï^^iiy4
la y ^^.^UIU3
l2 IJZ
1 1
FigureE2-4
Typical .14- and 16-pin DIP ICs
showinig pin numbering schcmcs.
 DlgltalTechnlques i 21

Rgurc E2-5 shows thc logic diagram and pbysical pin connections (pin out) oa
tbc 74LS04 hcx inveitcr IC. This IC coiitains sa idcntical aitd indepCDdeDt lo^c
inverters. Tlie ùyutsaxid ouçutsare idcntificd by pm number. In the diagrams
used in tfaese cxpcrimcitts the padageoutlme wOl not bc shown. Instead, aily
tbc invcrtcr symbol widi pin number labding wfll be given. Sec tfae cxamplcin
Rgure E2-6. In an expcriment, ifno pin numbCTs arc givoi you caa use any to-
vcncr you wam. Not all of thc invcneis in flic IC wffl be uscd in cvciy cxpcu-
mem. Simpty ignons thosc tiot used.

vS»A m
r-®-@-®-S-&tflA- ll'^Â - "«3l's^î2

'~4-^r4^WW~t^ ^-
FigureEZ-6
FïgureE2-5
Top view of74LS04 hex invcrter
IC showing pin assignments.
22 I STUDENT WORKBOOK
The traincr's breadboaid is designedto readQy accommodate ICs. Thc bread-
boaid blodk contains two rows of soldcriess comiectors sq»aratcd by a nanow
cemer groovc. Ttris Uodc isdesigned so Aat a dual-m-line IÇpadcage can be
uucrticd astridc tfac caiter groove n*idi results in fbiu- conncction pcnnts bdng
avaHaMc for eadi pin. TsigaxeE2-7 fllustrata a breadboandcd DIP IC. AU pins
should bc seated finnly. Tbc pias are dclicatc, so bc carcful when installing and
ranoving the IC.

-^i—Jg^--.-

INSET

FïgureE2-7

Aftertbe IC is instalkd, comiect the power (yy) and ground lcads. The supply
voltage for thc 74LS04 TTL IC is +5 volts and is applied at pin 14. Gnound
(GND) is comiected to pin 7. Chcck thc powcr and ground pin assignmcms for
eadi IC you use as they vaiy fiom one type to anothcr.
 DlgltaITechnlques | 23

Procedure (cont.)
7. Mount a 74LS04 hcx invcner IC (pan number 443-755) on the brcad-
boaiding block and comiect inn 14 to +5 volts and pm 7 to ground (GND).

8. Conaect one of the invencrs as shown in Figurc E2-8. The wput will come
fiiom data switch SW1 and the outpvst will bc displaycd on indicator I.T7D
Ll.

1/6 74LS04

DATA
SWTTCH
SW1
+t>it lED
L1

Figure E2-8

9. Appîy the logic voltagcs to the input as shown ùiTablc 10 and mcasure
thc conespCTiding ouçutvoltagcs. Rccoid m TaUe m.

Does the circuit invcrt?

What are thc output vokagc lcvds for positivc logic?
bixiaiy O = _ volts
binary l =_volts

TABLEm
A x
ov
+5V
24l STUDENTWORKBOOK
10. Rcmove the conncctioa bctwecn inn 1 ofthc IC and SW1 so fliat tbc in-
vcner iapat is opcn. Mcasure thc output voltage. Wifli the icput open fte
output vdtagc is ^ volts, or forpositive logic, a binaiy
_. Tlus aacans &at aa qpen icput has tfac same cffect as
abinaiy_input

11. WiretbccucuitsbownmRgiucE2-9.Howmanyiawrtcisaxccascadcd?

«"Ttiao*

DATA 10

rn-
awn»< LED
<W1 11 u
i.^...
tB>
u
FigurcE2-9

12. SctSWltolrinatyOtiuîobînaiylDOtmgdieoutputstatefDrcachuçuL

13. ModiIyyourcircusttocoDnectfheLSuyutoftbcLEDindicatoriopinS
oftheIC.
How many invencrs are cascaded?

14. ApiriybinaiyOaDdbmaiyltolhedicuitwithSWl.agamnotiDgthccor-
respoading ouçutstaie.

Whcn an odd numbcrofinvencrs are cascaded. ti»ompat is:

a. fliesamcastticnçiut.
b. oppositc dac ispot.

When an evcn number ofinveneis are cascadcd, Ae output is:

a. thesamcasfliençut.
b. ppposite thc UÇUL

Discussion
In Stqis 7.8, and 9 you coimected an imegratcd cireuit invcner and evaluated its
pperatkm. Widi zero volts (bmaiy 0) in you should bavc measured about +35
vote ouçut (binajy 1). With +5 volts input (binary 1) you shouU have measured
âbout '+O^? volts ouq»ut (binaiy 0). Even with unequal iigiut and oucut voltggcs,
flie circuit stffl pcrfonns logic uivcisioa.
 Dlgltal Technlques J 25
In Step 10 you detcnnincd thc cffect of an opcn inpuL Wth no mpul conacction,
dic output is +0^ volts or bmary 0. Since the input and output of a logic invcncr
are always complcmentary, the open ugiut miist be acring like a binaiy 1.

In Siep 11 you cascaded 5 invenets. You should havc found m Stcp 12 that thc
fmtpat was the complcmcnt of the mpat. Ncxt, m Step 13. you monitored the
ouqxit of thc founh invcncr in tiie diain. In Step 14 you dcmonstratcd that thc
wpat and ouqnit wcre the samc. Rom fliis data, you can concludc tiiat m a chain
of invcrtcis an odd number pioduccs a complcmcntaiy iiqîut and output; whilc
witfa an cvcn numbcr of inveners. flie ugnit and oucut wiU be thc same.
26 1 STUDENT WORKBOOK
 DlgltalTechnlques | 27

Experiment 3
DiodeLogic Gates
Objective
To demonstrate the operation and characteristics ofdiode AND and OR gates.

Materials Required
HcatUdt Digital Trainer
DCVoluncter

2 - 1N4149 smcon diodcs («5fr-56)

1-lkûresistor
1 -10 kûresistor

Procedure
1. Wre tfac drcuat shown in Figurc E3-I. faputs A and B comc firom data
switches SW1 and SW2. You wfll measure thc output voltagc C with re-
spect to ground.
*5V

llltû
1N«14»
wpur DIOOE8
OATA OVTPUT
swncH 4- -4<- ">"
SW1
WPUT
OATA B
SWTTCH -»" -^-
swz

FigureE3-l
28 I STUDENT WORKBOOK
2. Usit^g data switdics SW1 and SW2. apFiy thc iqiut voltagcs indicatcd m
Tabte I to Ûielogic gatc. R)r each set of inputs, monitor thc ouqxit voltagc
andrecoriinTableL

3. Using posirivc lopc assigmncnts, oonven tbc volugc lcvds in Tatde I into
binary I's and O's and transfer to TaUc IL

TABLEI TABLEH TABLEffl

A B c A B c A B c
ov ov
ov +5V

+5V ov
+5V +5V

4. Study TaUe II and drtmmiTN* dic lopc iunction bcing perfonncd. Logic
Fimction

5. CoDvnt fl»volta^e levds in TaUc I into 1's aod O's using ncgarive logic
"ssignincots OT<Ï transfcrto TaUc DL

6. Study TaUe m and detcrauDc ftc lopc function bcing pcrfbimcd. Logic
Rmctic»

7. Modyyyoarcîq»erimentcucuittodiatitappcarsasshownmRgureE3-2.
One logic ixyut wiD comc from SW1. Thc other logic ùçutwill oomc
fixxn logic switcfa A. You wffl mooitor the gatc oucut witfaLED indicator
Ll andAelogicswitcfaAouÇïatroLZ.
-SV

1 IkO

OUTPUT
OATA
swncH -N- -S-"
swï
wvre
-N-
LB3
12

FigureE3-2
 DlgltalTechnlques|29

8. Set SW1 to bmary O (down). Press logic switch A sevcral timcs, noting
Ac ouçuton LED Ll. T'iica. set SW1 to binaiy 1 (up). Agaia. press logic
swiich A sevcral times wfaïïe noting tbc ouiput on LED Ll. Explain your
nssults.
SWl=O.OutputC=.
SWl=1.0utputC=.

What logic ftmction is the gatc pcrfoiming?

9. Conscruct the logic gate shown in Rgure E3-3. Agam. data switdies SW1
aiid SW2 wffl sappîy fte togic aspats D and E, and you wffl measurc thc
ouçmtvoltagc atFwithaDCvolnncter.

DATA
SWTTCH -rt-
SW1
mpurs
DATA OUTPUT
SVOTTCH -^- -»"
F
SW2

ICkO

FigureE3-3

10. Appïy the logic voltagc levéls indicated m Table rv 10 thc circiriL Meas-
uic thc ouiput voltage for each set of uqnns aad recoid in TaUe IV.

TABLEIV TABLEV TABLEVI

D E F D E F D E F

ov ov
ov +5V

+5V ov
+5V +5V
30 1 STUDENTWORKBOOK
11. Using positive logic asagmnuus. convert tbe voltage levds iD Talflc TV
uuo binary 1 's and 0*s and transfertoTabIc V.

12. Study Table V and detennioe thc logic fimcrioa being perfonncd. Logic
RmctiOT .

13. Usingncgadvclogicassignmcnts.conventhedatainTablcrVhnobiDaiy
0*s aad 1's aad tnmsferto TaUc VL

14. Study TaUc VI and dctennine wfaat logic ftmction is bcuig perfonncd.
Logic FimctioD _ .

15. Modify your cxperimental circuh so that it qipears as shown in Figure

t. ODC uqiut is fiom togic switch A. Tbc odicr input is a I Hz dock
signal you wiU momtor witfa LED indicator Ll. You wiU observc tfae
dock ouçniton I-IÏTÎ indicator L2.

uxacswnrcH
A —^-

iwt/rs
CLK LED
(IH^
-^ Ll

lOkO

LEO
t2

FigureE3-4

16. Wifli the logic switdh tn thc X posirion. the logic ispat to the gate is tri-
naiy _ (positivc logic). Obscrve tbe gate ouqwt (LED
Ll) and dock (LED L2) rignals. When ûieclock ïapat is a binuy 1, ûic
gate ougnit is binaiy _. When thc ctodc input is a bi-
naxy 0, tfae gate ouiput is buiaiy^ .

17. Hold Ac logic switdi Sthc A poation whHe obsenring thc gate oucut
(LED Ll). Wth the logic switch in this position, thc logic inputto tte gate
istnnaty_and tbc gate ouçutis binaiy_.
Rdcasctteswitch.

18. What logic funcrion is tf»gatc pcrfonnuig?

 DlgltalTechnlques| 31

Discussion
In this oqïeriment you cvaluated two basic typcs of diode logic gatcs. You detcr-
miDcd thdr ekctrical pcrfonnance by applyiag logic voltage inputs aiul measin*-
ing thc conesponding outputs. Tliea, using both posirive and negarive logic Icvd
assignments, you detennined thc logic fimcdons bemg perfbimed. You also
dcmonstrated scvcral practical qpplicarions ofthcse basic logic gatcs.

to Steps 1 througb 6. you Otpcrimented widi uie gatc in Rgure E3-1. Your data
in Tatfle I, II, and Rshould appear as sbown in Tablcs VII, VID, and DC.

TABLEVD TABLEVm TABLEDC

A B c A B c A B c
ov ov 40.TV o o o 1 1 I
+5V ov +0.7V o I o 1 o 1

ov +5V 40.TV 1 .o o o 1 1
+5V +5V +5V I I 1 o o o

From Tablc VII. you can scc how thc gatc fimcuons dcctrically. With cither or
both iiçuts at ground or ZCID volts, citfaer one or both diodcs conduct The out-
put, therefore, is the fonvaid diode voltage drop ofabout 0.7 volts. Whcn boui
.iiqxtts aie +5 vota. neither dipde amducts. Ihe oyqnit is +5 yoilts as seço
4hroughthcl kûresistor.

Wtfa positive lopc assignmaus of the voltagc lcvds m Table VII (+5 volîs a tri-
naiy 1, 0V or +0.7V = binaiy 0), tfae gatc perfonns the AND fimction as you
should havc deduccd fiiom TaUc vm. The ouçutis a binaiy 1 oriy îf aU (both)
ïapvas arc binary 1. For àU other iqnit conditions. tfae ouqnit is binaxy 0. Tlris is
thcANDfùnction.

Next, you cvaluaied the gate using negative lopc assignments (+5 V s= binaiy 0,
0V or +0.7V s= binaiy 1). From Tablc DC, you should see that thc OR ftmction is
being performed. Tbe oucnit is iMnary I (0V) if cither one or bofli inputs arc bi-
naryKOV).
32 I STUDENTWORKBOOK
llic logic gatc in Rgure E3-1 can perfbnn both AND and OR operations, de-
peoding upon the logic levd assignmcnts. It is a positivc AND/aegarivc OR gatc.
The logic symbols vcpieseaung thesc fimctioxis are mdicatedin Figure E3-5.

A.

B. ^' :=o—
POSmVEANO tCûA'nVEOR

FigureE3-5

In Steps 7 and 8, you demonstrated a common application of a logic gatc. Huc,

dic gate acts as a connol elemenL Tlns comrol is handled by oncof thc iqputs,
SW1 in dris case. The second wpat, logic switdi A, is allowcd to pass or is in-
hibited by thc actfon ofthe finst uçmt.Wtfi the SWI input binary 0, the gsue out-
pnt is binaiy 0. Thc logic switch A pulses are mlubited and do not qîpear at dic
output. I.RD indicator Ll sbould have been off, indicaring this condition. LED
mdicator L2 mamtors logic switdi A. so it should foBow thc pulsations.

WWi SW1 set to binary 1, the gate is cnabted and thc ncnit is allowed lo pass
itomeb to fte OUÇULLED indicators Ll and L2 shoidd foBow onc another.
Cleariy, fte AND logic ftmction is being peribmied. This typc of connol gating
is vay widdy used in digital circuits.

In Steps 9 Ihrouj^i 14 you demonstrated flie logic gate m Rgure E3-3. Yoa ap-
piied 0V and +5V ncut levds and measured fl»eoutput for cadi comtrinarimi to
detcnninc its dectrical cfaancterisrics. Your results m TaUcs rv. V, and VI
should bc as shown in Tabtes X, XI, and XII bdow.

TABLEX TABLEXI TABLEXD

D E F D E F D E F
ov ov -0.7V o o o 1 1 1
ov +5V 443V o I 1 1 o o
+5V ov +4JV 1 o 1 o I o
+5V +5V +4JV I 1 I o o o
 DlgltalTechnlques|33

Wîth both iqntts at zcro volts. both diodcs conduct and the outpat is thc fowand
diodc voltage drop of-0.7 volts. If cithcr one or both diodes cooduct the outpit
is ûieiapat logic lcvel (+5 volts) less the forwaid drop of tiie conducting diodc
or qïproximatdy +4.3 volts.

Transfcmng dns dcctrical data into binary I's and O's. you complcted Tablcs V
and VI. Studynig Tatdes XI and XII, you can sce that wiA poarivc logic assigo-
mcms (+4.3V or +5V s binaiy 1,0V or -0.7V = binary 0), the drcuit pcrfonns
the OR logic ftmction since the oucnxt is binaiy 1 if cithcr or both inputs is bi-
aary î. With negarivc logic assigmncnts (+4.3V or +5V a binaiy 0.0V or -O.TV
= bùuuy 1), the gate perfonns the AND fanction. TTus gate is a posirive OR/
negativc AND. The togic symbols represcnting thcsc gate ftmctions are shown m
Fifiurc

POSmVEOR NEGATOEAND

FigureE3-6

Again. you dcmoastrated the dual nature of a logic gatc. Any logic gate can
perfonn cither thc AND or OR fimcrion dcpending upon the logic Icvd
assignincnts.

Rnally, you demonstratcd a useful application of an OR logic gate. In Rgiuc

E3-4, two togic mputs, A andthe 1 Hz dock, drivc UK gate. With tha togic
switch in thc A positioo. its oucut is hinary 0. The gate ouqxit follows dic dodc
ÙÇUL With tbe logic switcfa in die A position, its ouqntt is binaiy L This tums on
thcoidputindicatorandkeqBitonasIoagastbcswitdiisheIddowa Whenthe
dock mput is binaiy 1, thc output is binaiy 1. Whea A is binaiy 1. tfac oucut is
binaiy 1. The gatc is perfbnning the OR functiSi.
34( STUDENTWORKBOOK
 DlgltalTechnlques]35

Experiment 4
Transistor Logic Gate
Objectjve
To demonstrate the operation emd characterisrics of a typical discrete compo-
nent transistor logic gate.

Materials Required
Heaflddt Digital Tramcr
DC Volttaicter

1 - MPSA20 transistor (417-801)

1-lUïresistor
2-4.7kQrcsistors

Procedure
1. ConstructthccucuitshownuingurcE4-l.TheinputsAandB wmcomc
&CTD data switchcs SW1 and SW2. You wiU monitor the output on LED
logicindicatorLl.

+SV

uo
c
""—L1
4.7k O
SW1
INPUT
MPSA20
A
417^01
SW2.
INPUT
B
4.7k O
1
FigureE4-l
36| STUDENT WORKBOOK

2. Apply thc finu- input coatanarions givcn in TaUc I and mcasixni the om-
putvoltagc at Cforeach. Recori yourresults indie C column inTaUe I.

TABLEI
A B c
ov ov
ov +5V

+5V ov
+5V +5V

3. Usiflg poarivc logic levd assigmncnts. convcn the data m TaUc I nuio a
mxûitaïale usi^g binaiy O's and 1's. Use TaUe DL

TAB1£D
A B c

4. Study TaUc II and detcmunc die logic fimctioo bdng pcrfonned. Logic
fùnctioD
 DIgltaI Tcchnlqyes J 37
5. Usu®negarive logic lcvel assignacms, convcrt thc voltages in TaUc I
iniD binaiy l*s and O's and complctcTablc IR.

TABLEm
A B c

Study TaUc III and detenninc the logic ftmcrion bdng pcxfonned. Logic
fimctioa

Discussion
Tbc logic dreuit in Figune E4-I is callcd a rensior-tranauaor togic (RTL) gate. tt
is idcndcal to a sunirie oansistor invCTier. but with two mpat basc resistore. A
positivc voltage Icvcl qiplied to cithcr or bodi ofthc nçutswffl satunue dte nan-
sisior and cause dx; ouq>ut to go tow. Widiboth iicuts ncarzero volts orground,
flie transistor wfll bc cut ofif and tte aatpat wffl be the sicply voltagc as secn
througfa the coDector resistor. This «yentionis OMaplctdy defined by your nuth
tàtflc fTàUeI) and diould sppcw as Aown in Taldc IV bdow.

TABLEIV
A B c
ov ov +5V

ov +5V 40.1V

45V ov 40.1V

+5V +5V 40.IV

38 ISTUDENTWORKBOOK

Using positivc logic. your truth table CTable II) should be as iadicated in TaUe
V.

TABLEV
A B c
o o 1

o I o
1 o o
1 I o

TOs defines the NOR lunction. Thc RTL gate acts as an OR gatc foUowcd by an
invcncr.

Using xiegativc logic, your outh tablc CTaUc III) should appcar as idiown in
TaUeVL

TABLEVI
A B c
I 1 o
1 o 1

o I 1

o o I

This is thc NAND funcrion. Tbs gate pcrforans thc samc function as aa AND
gatc followcd by an mvcner for negativc logic.
Tbas drcuit cm be used to implement any of the basic logic fimcrions by com-
bimng a number of gates. Additional basc resistore can be added as more iapstts
are requucd. By parallding uipits or using a singlc inpiu, the circuit is nodring
more than a simplc invcner.

Tïàstype of logic gaic was widely xiscd in discrctc componcm digital sysacms
and a modificd vcrsion of it is availablc in intcgrated circuit fonn.
 Dlgltal Tcchnlques | 39

Experiment 5
TTL Logic Gates
Objective
To demonsxraïe the operation and characteristics cf aTTL ïogic gate and to
shcw haw it can be used to perform any cfthe three basic logicfimctions.

Materials Requlred
Hcaflddt Digital TTainer
DC Voluncter or togic prube.

I - 74LSOO TTL quad two-mput NAND gatc IC (443-728)

Procedure
1. Moum die 74LSOO TTL intcgratcd cucuit on tiic brcadboanling block. Be
sure ftat it is scated finnly, sttaddling the xiolch fa tfac sodket and that
BMC ofthc pms are baiL QMmcct pin 14 to +5 volts and pin 7 to GND.
Rguic E5-1 diows the pin coimcctfoas.

YCC
r-TO-IïîUî^-R-F^-fîUTl-i

r^n(Di
l~tiJ"ïll~tJLn±]~lit~liMzJ~~'
OND
7<taao
OUWTWMNPUriWO

FigureES-1
Pin conncctions for 74LSOO TTL IC
40 I STUDENTWORKBOOK

Note:

In Fîgure E5-2, wc show a dashed line around thc IC gate symbol. This repre-
sents tfac IC paduigc. The numbcr C74LSOO. 74LS20, 74LS02, ctc.) iden-
tifies tfae typK of IC. Accompanying the IC designarion number you will scc
1/2, 3/4, or ofter fractions. TOs is a mcthod of indicating how many of the
gates ia the IC are uscd. For examplc, m a 74LSOO IC fliere are four 2-iqntt
NANDs. In Rgure E5-2, only one of Ac fbur gaies is uscd; therefore, we in-
dicate dris with thc designation 1/4-74LSOO. In Rgure E5-4. two of dïe four
gates are used. so the designation is 2/4.74LSOO. This temunology wffl bc
used ûuoufîiouttfac program.

Connect (mc of fltc four gates in thc IC as shown in Figure E5-2. Tbe iqmt
wffl ccane froin data swittdi SWI. You wiU monitor dic ucmt and output
states with toeLl and L2LED indicators and yourDCvoInneter.

1M.74UOO

V|
«Wl -»-t2

T
u
>

FtewtES-î

3. Sct SW1 to tte down porition. Measure the DC input Cpins 1 and 2) aad
ouqput Qrin 3) voltagcs. Set SWI tt) the up posirion and measure dic uspat
and oucut voliagcs again. Recoid your data m Table I. Also, notc thc
I.FD indicator input/output states.

TABLEI
INPUTS OUTPUT

I 2 3
 DlflltaJTechnlques J 41
4. Assuming posirive logic, the output logic levels are:
binary O = _ volts.
binaiy I = _ volts.

5. Study Table L What logic fimction is being perfonncd?

6. Wire thc circuit shown in Rgure E5-3. The 'mpwts comc from data
switchcs SW1 (A) and SW2 CB). You wffl mcasure output voltagc C at pin
3ofthe74LSOOIC

W.74LSOO

SWt
iNpurs
SW2

Figure E5-3

7. With SW1 and SW2, apply the input voltages givcn in TaUc II. Mcasure
and record the owpat voltage for cach set of inputs.

TABLEH
JNPUTS OUTPUT
A(SWI) B(SW2) c
ov ov
ov +5V
+5V ov
+5V +5V
42l STUDENTWORKBOOK
'S
8. Using positive logic conven your dectrical ouA tablc in Table U into I
andO'sinTabIeIIL

TABLEffl
A B c

9. Study TaUe HL What logic ftuicrion is being perfbrmcd?

10. UsiDgncgativeIogic.conventhcdatainTabkIIuBol'sand O'sandre-
coniinTaUlcIV.

TABLEIV
A B c

11. Study TaUe FV. What logic fimction is bcing perfonned?

 Dlflltal Technlques J 43
12. Wre thc dreuit shown ia Rgure E5-4. Wth SW1 (A) and SW2 (B). apply
thc states shown in TaUe V. Record the ouçùtstatc for cach set of iiqwts.
Observc LED iDdicatois Ll, L2, and L3 to obtain your uçutand ouçut
data. Usc positfve logic Oiinaiy ls=on,binary0=ofl).

u »4-74t.SOO
"w———~~.i

sm -S-UL c
"»—
u
awa >-

u J--P.-
<5V

FigunES-4

TABLEV
A B c
o o
o 1

1 o
1 1

13. StudythccucuitinFigureE5-4andthcdatainTahlcV.Whatlogicfûnc-
tianistïdngpctfimned?/ _.
14. Connect tfac drcuit shown m Rgure E5-5. Monitor flie icputs and (naput
oa LED indicatoxs Ll, L2. and L3. With SW1 (A) and SWZ (B), apply the
nçutshown in Tatdc VL Recoid die ouçutstate concspondmg to cach sct
of nçuts.Use positiw logic.
a».741800
»"""—""<
an JL-@]>^: c
"^- u
nw2<

t2
{:0-r 10
>"-

FigurcES.5
44 f STUDENT WORKBOOK
15. Study Rgure E5-5 and TaUc VI. What logic function is being pcrfonDcd?

TABLEVI
A B c
o o
o 1
1 o
1 I

16. Modify your cucuit in Rguuc E5-5 by adding u»c fouith gsuc in thc
74LSOO to flie oniput as dtown in Rgiuc E5-6. Only dic output change is
shown. llte rest offhc dreuit stays as m Rgure E5-5.
741.800

r-22T 11 -S-L3
^w tî >

FigunES^

17. Uang SWl (A) and SW2 (B) data switches and monitoring LED in-
dicatois Ll. L2 aad L3, spply the aates daown in Tablc VH. Recoid thc
ouçutstatc for cadi sct ofnçntfs.

TABLEVH
A B c
o o
o 1

1 o
1 1

18. Study TaUe VIL What togic ftmction is being pcrfonncd? .

 Dlgltal Technlques | 45

Discussion
In Steps 1 through 5 you demonstiated how onc of tfie four gate circuits in the
74LSOO IC could bc uscd as an inverter. The two iDputs are ricd togctherto fonn
a single inpw. line. With this aiTangcment, ftc gatc peribnns as a TTL logic in-
vcrtcr where the iiq»utaxxl oucut arc complemcntary.

In Step 3 you mcasured tfac iiçutand ouqmt voltages. Whcn thc DC hyut at pns
1 and 2 isO volts, dic ouqiut at pin 3 is qpproximaiely 4J volts. When thc DC
iqnit at pins 1 and 2 is5 volts, thc ouqnrt atpm 3 is O volts. Thc gate is perfonn-
ing fte NOT ftmcdon.

to Steps 6,7,8, and 9 you demoastratcd the basic logic ftmction oftbe TTL gate.
Using poritive logic it perfonns thc NAND fimcdon. In Steps 10 aad 11 you
should havc found that flie baric TTL gate perfonns uie NOR fimcdon with
negativçlogic.

You danonstrated howTTL gates could bc conneacd 10 pcrfonn the basic AND
function in Stqïs 12 aad 13. în Rgurc E5-4 gatc 1 is a NAND wbale gate 2 is
connected as BD invcner to complcmcnt the NAND oucnit to producc the AND
OUÇUL

You comncctcd TTL gases as an OR circuit and demoxistrated its funcrion in

Steps 14 and 15. In Stqps 16 and 17 you addcd an invcner to the ouqxit of tfae
OR to ptodiice tfac poritivc NOR fimction. Thc AND and OR drcuits are ccnn-
moriy uscd with tfac TII- gate. Howcvcr. the NOR vcision is rarely usc<L A
sqMratc positive NOR TII. lopc demcnt is availablc C74LS02) to climinaTe fhe
.Bccd to imcrconncct a 74LSOO as wc did hcre.
46l STUDENT WORKBOOK
 DlgItalTechnlques j 47

Experiment 6
CMOS Logîc Gates
Objective
To àemonstrate the aperatwn and characteristics cfa CMOS logic gaïe ond to
shaw how itcanbe used toperform emyofAe three basic hgicfunctions.

Materials Required
HeaûddtDijptal Trainer
DC Voloncter or logic probc

1 - 4001 CMOS quad two-iaput NOR gatc IC (443-695)

Procedure
1. Mount thc 4001 CMOS mtcgrated circuit on thc breadboarding UocL Bc
suic flut ft is seated finnly, stFaddIing the notdi m thc sodoct. and that
nmtc ofAe pins are bem. Qmaect pin 14 lo +5 vdts and pin 7 to GND.
Rgure E6-I diows tbe pn coxmectioDS.

vS_ _ _ _
r-fR-Iial-FîUïïUîol-fîUïl-i

'-tinînii-tii-unsnir'
4001
NOR
CU06 QtWD WO«»Vr

FïgureEfrl
Pin coimcctfons for 4001 CMOS IC
48| S7UDENT WORKBOOK

Conaect one of thc four gates in the IC as shown in Rgurc E6-2. At thc
samc time, conncct the other six gate inputs (pins 5, 6,8,9,12, and 13) to
+5 volts. The iiput to thc gatc wiU comc from data switch SW1. You wm
measure die iiçutand thc mtpat states with your DC volnneter.

Note: Although CMOS has good noisc unmumty charactcristics, its noise
immunity is dcgradcd by any open iicnits. For cxamplc, thc CMOS gate
cucuit you just wired might not woA if you didn't conncct aU of the in-
puts to the otfier gatcs to a spcdfic logic JevcL As a geacral nde. it is best
to use a Logic hi^i voltage level, rathcr than a logic low voltStge levcL

SW1

TïgureE6-2

3. Sct SW1 first to tfie down position thcn the up position. Mcasure the DC
iffpttt (pms 1 and 2) and oucnit voltage (pui 3) for cach position. Rccortl
yourdatainTableI.

TABLEI
INPUTS OUTPOT

1 2 3

Assuming positive logic, tte output logic lcvcls are:

binaiy O = __ volts.
binary l s= _ volts.

Study Tablc I. What logic fimction is being perfonned?

 DIgltaITechnlques {49

6. Wire thc drcuit shown in Rgure E6-3. Tbe inputs comc from SW1 and
SW2. You wUl measMrc thc output voluge C at pin 3 of the 4001IC.

SW2

Figure E6-3

7. Wifli SW1 and SW2. spply the iiqiui voltages given in TaUe IL Measurc
and recoid the ouqiut voltage for each set of inputs.

TABLED
INPUTS OUTPUT
A(SWI) B(SW2) c
ov ov
ov +5V
+5V ov
+5V +5V

's
8. Using positivc logic, convcn your dectrical truth table in Table U into 1
andO'smTablcUL

TABLEm
A B c
50 I STUDENT WORKBOOK
9. Sudy Tablc m. What lopc fimcrion is beiDg peifonncd?.

10. Vsss Ncgarivc logic, conven thc data ni Tablc II uuo 1's and O's aad re-
cordinTaUcrV.

TABLEIV
A B c

11. StudyTabIerV.WhatIogicfunctionisbeiDgpufonncd?

12. Wirc the dreuit shown in Figwc Eo^t. Rcmembcr to removc +5 votts
fixxn pms 5 and 6. WiA SWI (A) aad SW2 (B). apply thc iapat states
shown in Tatflc V. Record tfac oinput state for cadi sct ofnqnns. Use posi-
tivc logic (binaiy I *= on, binaiy 0«=ofl).

2M-4001

SW1.
u
"—
SW2. ~B-

FigunEfr4
 D(gltalTechnlques|51

TABLEV
A B c
o o
o 1

1 o
1 1

13. StudythedrcuitmRgureE6-4andflicdatainTaUcV.Whatlogicfimc-
tion is beàasperfbnned? _.

14. Connect thc cireuit shown m Hgure E6-5. Rcmcmbcr to rcmovc +5 volts
fiun pns 8 and 9. With SW1 (A) and SW2 (B), apply ÛKnçiutsshown in
TaUc VL Record ftc ovspat state (O concspcmding to cach setofixqnns.
Usc posirive togic.

W-4COÏ

SW1
A

B
SW2

FîgureE6-5

TABLEVI
A B c
o o
o 1

I o
I 1
52 ISTUDENTWORKBOOK

15. Study Rgure E6-5 and TaUe VI. What lopc function is being perfonned?

16. Modify your cucirit m Rgure E6*5 by adding Ûicfoiudi gate in thc 4001
to thc output as dwwD m Rgure E6^. Ocly U*c ouqxrt changc is shown.
Tbc rest of thc cireuh stays as m Figure E6-5. Rcmember to icmove +5
volts ftom pins I2and 13.

4001

TîgureEM

17. Using data switches SW1 (A) and SW2 CB) appty flic states shown in
Tablc VII. Record tfae ouqnit state (O for cach set of ncnits.

TABLEVD
A B c
o o
o 1

1 o
1 1

18. Study Table VIL What togic ftmctioa is being perfonned?.

 DlgltalTechnlques | 53

Discussion
In Steps 3 through 5 you dcmonstrated how one of the four gate circuits in the
4001 IC could be uscd as an invcncr. Tbe two inputs are ticd together to fonn a
single iapat line. With this anangement, thc gate perfonns as a logic mvcner
whcre the input and ouiput are complcmentary.

Tbs input from SW1 is O and +5 volts. Thc approximate output levels should
havc been tunary O = +0.1 volts aitd binary 1 s= +5 volts.

In Stqps 7,8 and 9 you dcmonstrated fte basic logic funcrion of the CMOS gate.
Using poritivc logic it pcrfomis thc NOR fimction. In Steps 10 and 11 you
should havc found that the basic CMOS gate perfonns the NAND funcdon with
ncgative logic.

You demonstratcd tfiat thc CMOS gate can be connectcd to perfonn the basic
OR ftmctiCTi in Steps 12 and 13. In Rgure E6-4 gatc 1 is a posiuvc NOR
(ncgativc NAND) and gate 2 is connected as an invcncr to complemcnt the NOR
aad pnoducc an OR oucxtt.

You Dcxt connccted CMQS gatcs as an AND cunrit and dcmonstrated its fimc-
rion in Stqps 14 and 15. In Stq» 16.17 and 18 you addcd an mvcitcr to the out-
put of the AND to producc thc positive NAND ftmcdon. The AND and OR dr-
cuits arc commoiriy unplcmcnted with CMOS NOR gatcs. However. the NAND
verdon shown herc is raidy uscd. A scparaic positivc CMOS NAND logic elc-
mcnt is avaflablc (4011) to climmate the nccd to intcrconnect a 4001 as wc did
hcre.
54 [ STUDEhTT WORKBOOK
 DlgltaITechnlques 155

Experiment 7
Applying NAND and NOR Gates
Objective
To shmv haw TTL cmd CMOS, NAND, and NOR gates are used to mplement wy
logic functions and to danonsvrate ihe value cfBoolean algebra w reaucing
ïogic circuiïs to iheirminaman corfiguratwn.

Materials Required
Hcaflddt Digital Trainer
1 ~ 74LSOO TTL quad two-input NAND gate IC (443-728)
1 - 74LS20 TTL dual four-mput NAND gatc IC (443-798)
1 - 74LS02 TIÏ- quad two-input NOR gatc IC (443-779)
1 ~ 4001 CMOS quad two-input NOR gate IC (443-695)

Procedure
1. Writc thc ouqxtt cxpresaon of d»e circuit shown in Rgurc E7-1.
F=

A.
c. >

)n
>

B.

D. >

Figure E7-1
56 I STUDENTWORKBOOK

Figure E7-2 shows tbc NAND gate implemcntation of tfie circuit m Rguxc
E7.1. Rcmember, ifyou NOT thc iiyuts and the output of an AND gatc, it
fùnctiousUlSan OR gate. Wxc d»cucirit shown m Rgure E7-2. Thc pin
connections for the 74LSOO and 74LS20 IC are givcn in Fîgure E7-3. Be
sure to coanect pin 14 to+5 volts and pin 7 to GNDon cadi IC.
741.900

swa

8W

Figure E7-2

vcc
'-tLTisniMininsj-Q-'
74SUO
OUAOn»tMNPUrNAND
Y»
r4ï2UÏ3Uî5Uïîl-N45Uîï-i
^iu-isreniniHiî-iu--'
OND
74LS2B
DUAI. FOWMNPUT N»WD

l-tLJ~W~t.lJ~lâl~l£TB"~'
74tSOa
QUAOTWtMNPUTNOfl
I!1gureE7.3
ICPinConnecrions.
 Dlgltal Technlques | 57

3. Apply the iiçuts A. B. C, and Din Table I to the circuit with data
switches SWI through SW4. Monitor the ouqput on LED Ll and recori
the state for cach set of inputs m thc left-hand F (Figurc E7-2) column in
TableL

TABLEI
INPUTS OUTPUTS

A(SW4) B(SW3) C(SW2) D(SWI) F(L1) F(L1)

Fig.E7.2 Fig.E7-4

o o o o
o o o 1

o o 1 o
o o 1 1

o I o o
o 1 o 1

o 1 1 o
o I 1 1

I o o o
1 o o 1

I o 1 o
I o 1 1

1 1 o o
1 1 o 1

1 1 1 o
I 1 1 1
58 ISTUDENTWORKBOOK

4. UaQg Boolean algebra, reducc fltt ouçnitcquarion obtamed m sfq> 1. Tbc

ynmtfnJTp^ ciqMCSSion is:

5. CoDsmictdiccircuitshownmRgureE7-4.

FîgureE7-4

Write thc oatpat equarion of the drcuit m Figure E7-4. Cpmpare it to tbc
oqncsaor you derivcd in Step 4. Rcmcmbcr, if you NOT thc iicxrts and
flic output ofanOR gate, it ftmctions likc an AND gatc.

7. ApplytIasinputsshownmTaUeIandxccoidtheoutputStatem&eri^u-
hand F (Hgure E7-4) column.
8. Conqïare thc two F oaçwt columns in Tablc I. What condurion can you
readi reganling thc cucuits in Rgure E7-2 aod E7.4?

Discussion
In tfiis pan ofdie oqxrimeot you demonstrated bow TIL NAND and NOR gates
are uscd to implement logic fimctions aad how Boolcan algcbra isuscful in min-
inuzing flïe cquatioii.
 Dlgltal Technlques | 59

First we illustrated a standard logic circuit (Rgure E7-1). aad you wrote its out-
put cquaoon.
F=AC+AD+BC+BD

Then we fllustrated how fliis drcuit could be implcmentcd with TTL NAND
gatcs (Rgure E7-2). It took four 2-input gates from dtc 74LSOO IC and onc 4 in-
put gate fiom the 74LS20, or two IC packages. Ncn you devdoped a truth tablc
for this drcuit

In Stq> 4 you minimiTcd thc original cquatiai with Boolcan algcbra. Your solu-
tion should took Ukc this:
F=AC+AD+BC+BD
Factor out A, factar out B
F=A(C+D)+B(C+D)
Factorout(C+D)
Fs(C+D)(A+B)

Thcn m Step 5 y<m consttucted a drcuit ORgurc E7-4) madc with a 74LS02 TRL
NOR gatc Aat implemcnts flie abovc icduccd cquanon. te output cxpression is F
=(A + B) (C+ D). To verify hs opcration. you dcvdopcd a nuth table. By com-
paring the output rcsulîs ofdie circuits m Rgure E7-2 and E7-4 m TaUc I. you
shoidd find tfaem idcnticaL Obviously, the simplcr drcuit in Rgurc E7-4 is pre-
fencd because it wfll takc up lcss spacc and will consinnc less powcr.

Procedure (cont.)
In dte foUowing stq»s you wfll bc givcn a Boolean cqiiatfon to implement with
CMOS NOR gatcs. You wfll nnpleinent the original cxpression and test it Thcn
you wOl îninimiri!- thc uipicssion and implemem uic reduccd vcrrion. Rnally,
you wiU compare the logical opcration offlienro circuits.
60 ISTUDENTWORKBOOK

9. Draw fte AND and OR gate lopc diagram of tiic cxpression

X*=C[K(K+L)+M]

10. RedrawthccircuitusmgpositivcNORgates.

11. Implancnt your ciicuft m Stq» 10 with a 4001 CMOS quad two-iqput
NOR gate IC. Usc SW2. SW3 aid SW4 lo apply the K, L, andM inputs.
MoanitoryourouQïutoaLl.TbepmcoDnectioDsforflie4001 ICaregivcn
in Rgure E7-5. Oonnect +5 volts to pin 14 and ground to pin 7. Rcmember
to conncct aU unuscd inputs to+5 vplts.

l~îirtînîniTunsnzj~J
OND

FigunE7.S
Pin Qnmections for4001 CMOS IC
 DlflltalTechnlques| 61

12. Develop a truth table for tte circirit by recordmg your output in thc left
hand X column (Step 12) ofTaUc EL

TABLED
INPUTS OUTPUTS

K(SW2) L(SW3) M(SW4) X (STEP 12) X(STEP16)

o o o
o o 1

o 1 o
o I I

I o o
I o I

1 1 o
1 1 I

13. Rcduce tiac cxpicssion m Step 9 using Boolcan algcbra. Tt»c nuiiimizcd
cquaûonis.

Xs

14. Draw die logic diagram of tlus cucuit uang AND aad OR gatcs.

15. Implemcnt the drcuh dcvdoped in Stcp 14 wift CMOS NOR gates.

16. Wrc the minixmzcd drcuit. Apply iqputs K, L, and M with daaa switdtes
SW2, SW3 and SW4. Monitorthc ouçuton Ll. Use thc right-hand X col-
UDMI (Stq> 16) in Tablc II to record your tmth table data.

17. Compare tfae two X ouc»utcolumns in Tablc IL What condusions can you
draw? What cuarit muumizatiai was really accwnplidicd?
62 1 STUDENTWORKBOOK
Discussion
Your logic diagram for thc origixial cxpnsrion m Stcp 9 should appear as m Fig-
ure E7-6. Rcdrawing tfae circuit using poritivc NOR gatcs should havc givcD you
the drouit in Rgure E7-7. Your vraui tablc should appear as m Table m.

Figure E7-6

FigureE7-7

TABLEm
INPUTS OUTPUT

K L M x
o o o o
o o 1 1

o 1 o o
o 1 1 o
1 o o o
1 o 1 1

1 1 o o
1 1 1 o
 DlgItaITechnlques J 63
Ncxt, you minimizcd the original cxpression by using Boolcan algcbra. Your re-
duction should appear like this:
X=E[ÎC(K+L)+M]
X=L(KK+ÎCL+M)
X=LKK+LKL+Ùtf
X^LÎA

A logic circuit for this is shown in Rgure E7-8. TIiis reduccd cxprcssion is rcad-
Uy unplcmciucd with positive NOR gates. as shown in Figure E7-9. Tbs K input
has absolutdy no cfifect on the dreuit as this reduoed cxpression indicatcs. The
rcduccd drcuit will producc the samc logic fimctfoD as dic origiaal morc com-
plex cucuit as your truth taUe should indicate.

M.
iX-UUI

FigureE7-8

XcDN

r»gureE7-9

Tlic imponam pouu to get fiom this cxercisc is that Boolcan algcbra accom-
plished a drcuit muumization fiom 4 gates (Rgurc E7-7) to 2 gates CRgure
E7-9). Thc type 4001 CMOS IC contains four 2-iiçutNOR gatcs. It can be used
to implcmcnt the original drcuit (Rgure E7-7).It is also iised to imiflemcat ftc
reduced drcuit (Rgiue E7-9). Bui only two gatcs are used. The iinused gates
could possiUy be uscd dscwhere.

Procedure (cont.)
18. Write the truA taUc for a 3-iiçut AND gate and sketch thc appropriatc
logic symboL

19. Sbow how to implcmcnt a threc-input AND gate with a quad 2-taput
NAND f74LSOO). Draw thc drcuit. implcmcni it on your TtaiDer and
vcrify its operadon witfa a truth taUc.
64J STUDENT WORKBOOK
Discussion
The truth table for a three-input AND gate is givcn m Table IV. The logic dia-
gram is shown in Figure E7-10.

A.
B. "D-ABC
c.

Fïgure E7.10

A 3-mpat AND gatc unplememed wiûia 74LSOO IC is shown in Figurc E7-1I.

înpists B and C are NANDed in gate 1. Gatc 2 is connected as an mvener to pro-
ducc BC. BC is tfaen NANDcd with A in gate 3 (o producc A(BO. Gatc 4, con-
nccted as an invcner, givcs D s= A (BC) whidh by thc Law of Associarion is the
sameasD=ABC.
741SOO

A(BC)
'):>-C[^_>T- D=A(BC)cABC

B ")3&£^
1 7)0-JBC
c

FigureE7-ll

TABLEIV
INPUTS OUTPUT

A B c D

o o o o
o o 1 o
o 1 o o
o 1 1 o
1 o o o
I o 1 o
I 1 o o
1 I 1 1
 DlgltalTechnlquesJ 65

Experiment 8
The Wired-AND Connection
Objective
To uivestigote the wired-AND connection tifan open-coUector TTL loyc gate
and determine its logic function.

Introduction
Wth ccnain types of logic gatcs, connectiog their ouQMts togethcr as shown in
Hgurc E8-1A. fonns an additioiul logic fimction at thc common connection.
This logic fimction slwwn in Figure E8-1B is refcncd to as an implicd. dot, or
wired-AND. NOR and AND functions can bc achicvcd by simifly tyiag gate out-
puts togcther to a conunon-coUcctor puU-up reristor. Tliis wired-AND function
is aduevcd by using opc»M»UectorTTL gates.

A.
B. >1
c.
D. y
FigureES-lA

COtMOH
WrERCONNECnON
MOOE

VIL
TÏZ>
VIL
T=D-
Figure E8-1B
66 f STUDENT WORKBOOK
Somc logic fa**T«1i»s,wfaen wired togcther as shown m Rgurc E8-1A, pnxluce a
wucd-OR condition. An cxanirie wauld bc Ac ECL togic gate. Thcre are two
types of gates dhat wiU pnducc some vuy undcsiraUc results wbcn thdT ouçuts
are connected togcdier. These ue logic drcuits using activc pun-up transisiors
sudi as tbe standaid totan-pole TTL and CMOS.
V .aen gate outputs are connccttd together, tbc output oansistor of cadi gate is
conneotcd in paralld. Wth opciM»UectorTTL gatc circirits. a single extcmal
pull-up resiaor is added as shown in Rgure E8-2. Whcn cither one or bofli of d»e
shunt ouçuttransistois is conducting, the ouçutwm bc low.

1+Vcc

: 1 ? -L
L..—
oinpuTt
FîgureES-2

In this ciqxrimcnt, you wffl bc mvcstigating the cfFecis of thc wired-AND OM»-
necrion using an opciw»UcctorTTL gate.

Materials Required
Heattkit Digital Trainer

I -74LS03 TTL quad two-iaput NAND gate with opcn-coUcctor output IC

(443-745)
1 - 74LS04 TTL hcx invuter IC (443-755)
I - 74LSOO TTL qxiad two-mput NAND gate IC (443-728)
1 - 74LS08 TTL quad two-input AND gatc IC (443-780)
1 -1 lûCÎrenstor
 Dlgltal Technlques j 67

Procedures
1. Mount thc 74LS03 IC on the breadboanL Connect the dffarit showo in
Rgure E8-3A. Thc pin connectioas for the 74LS03 are shown m Figure
E8-3B. Comicct +5 volts to pin 14 and tlu; I kQ resistor. Pin 7 is con-
nccted to GND. The inputs A and B mn come fixnn data switches SW1
and SW2. Thc ouqnn is displayed on LED indicator Ll. Ll lights to in-
dicatc a hi^i oucnit at C.

2. Apply thc uputs as indicatcd in Table L Use positive logic. Rccoid tfac
concspODding ouqmts in column 1 ofTaUe L

3. Study your results in Tablc L What logic function is bdng performed?

4. Write flie output cxpression of tiiis circuit fiom TaUc I usang flieprocc-
dure described m this unit

5. Uang DcMoxgan's thcorem, changc its fonn.

6. Draw thc cquivàlau logic diagrams for Ae cxprcssions you dcrived m

stqïs 4 and 5 above. Show thc uqwts and ouipucs.

<w
2«.74tS03
f»««W^

SW1

SW2

FigureE8-3A

'-iininin.ii-iâniniT"
OND

FîgureE8-3B
Pin conncctions for 74LS03
intcgratcd circuiL
68 ( STUDENTWORKBOOK

7. Wire the circirit shown in Rgure E8.4A. 'Tbs pin coxincctions for thc
74LS08 and 74LS04 are shown in Rgutc E8-4B and C. Conncct +5 volts
to pin 14 and GND topin 7 for bofli ICs.

8. ApplythcnyatsAandBftomdaoswitchesSWlitndSW2asshownm
TaUe L Usc posirivc logic. Kecotd die correspondmg ouqnits m column 2
ofTabtcL

9. Compaic columns I and 2 ofTaUc L Are thcy the samc?

Why?

You can rcadUy sce flut tfae AND ftmction is bcing perfonncd ly thc out-
put AND gate in Rgure E8-4A. What is causing die ANI>ing m Rgure
E8-3A?_

What advantagc does the circuit of Rgiuc E8-3A have coinpared to thc
cucuit ofRgure E8-4A?

^.^-tâK., ,.JA-.?<tâSg^.
SW1—&

r-KÀFUUU^l-S-,

l-liJ~t£Tliï~Ën£J~liî~lzt~J
iA tB iY»* n av awo
74LS08
OUWnKMNfVrANO

YË?AS. JE; A £.A .Î2.

r-F3Uî3Uî5UîîUî5t4ïUïl-,

k>3l>'l{^:
l-tiï-tâi-tânir-isj-isj~l2,}~^
^^^
IA 1Y a* tï *A av 0x0
74US04
HEXWVBnER

FigureEM
 DlgltalTechnlques | 69

TABLEI
WPVTS OUTPUT OOTPUT

Columnl Cokunn2
ACSWI) B(SW2) ccu) C(U)

o o
o I

I o
I 1

10. WJrethecucuitshownmRgureE8-5.

11. ^pplythe iiçutsA, B, C. and D from data switches SW1. SW2, SW3, aad
SW4 as indicated in TaUe D. Use positive logic. Rccord the pucut state at
Ll in outiwt column 1 ofTabIc II.

12. Study your results in TaUc IL Noticc that the outpat is a logic O wrihcn
boA iaputs A and B are a logic I or, both inpuis C and D arc logic 1 or;
wbeai all inputs arelogic 1.

13. From tbe data in Tablc H, writc thc Boolcan cxpnsssion for thc togic O
outputs.

14. Using Bookan algebra, reducc the cquarion to its sunplcst fonn. F »
_. Note: Because your cquaoon is derivcd firom the logic
O outputs CF). a vinculum should be placcd ovcr thc cnrire sunplificd cx-
picssionCF).
*sv
a4.74LSC3
110
SWt

SW2

SW3

SW4

FigureES-S
70 1 STUDENT WORKBOOK
15. Draw thc equivalcnt circuit(s) for tfae cucuit ofRgure E8.5 using standaid
TTL ICs. Show all iqxits and ouqxits.

16. 'WMcthecquivàlcDtcircuitofFigureE8-5asshownmFîgureE8-6A.The
pin connections for die 74LSOO are shown in Rgure E8-6B.
17. Appiy thc itputs indicated in TaUe IL Rccoxd thc coiTesponding ouqnits
in ouçutcolumn2 ofTaUe IL
Docolumns I and2match? Why?

What arc thc advantages of the opeo-coiUector cireuit ofFigure E8-5 com-
pared to tfae standaid m, gate drcuit ofRgure E8^A?

1M.MLM8

FigunES^SA

^]nE>i
l~iLnîn2niTiânîTUTd
7-UOO OND
<xjwmo«purK»ND
FigureES^iB
 DIgltaI Technlques i 71

TABLEH
INPUTS OUTPOT1 OUTPUT2

OPEN EQUIVALENT
SW1 SW2 SW3 SW4 COLLECTOR CIRCUTT
A c D E F

o o o o
o o o 1

o o I o
o o 1 1

o 1 o o
o 1 o T
o 1 1 o
o 1 I I

1 o o T
1 o o I

1 o 1 o
1 o 1 1

1 I o o
1 1 o I

I I 1 o
1 1 I 1
72l STUDENTWORKBOOK
Discussjon
to stqp 1. you ctBmcctcd two of the gatcs in fhe 74LS03 as mvcitcrs wdth thefcr
oaiputs cCTniccted together throu^i a I ku pull-up rcsistor. In step 2. you ptotted
a tnrih taUe forthe cirouitto scc how it worics. Tbeaby studying the truth taUe,
ywi should havc conduded that tfic drcuit pexfbnns the negadvc AND (Positivc
NOR) fimcrion sincc thc oucut is 1 oaly whsn bodi ofthc 'vapats are lopc 0. The
ovttpat equatfon Aen is C «= ÀS.In step 5. you used DeMoigan's tbeorem to
changc its foim. You found that C =^S *= A+B. In siep 6, you drew thc equuva-
lent circuits for these CTpressioas. Thcy should appcar as shown m Figures
E8-7A&B.

In step 7, you wired d»equivalcnt cireuit in Rgure E8-4A. la stq> 8, you ap-
plied flic iqnits according to TaUe L You recorded the concsponding ouqiuts in
column 2 ofTaUc L to stq) 9. you found tfiat oucnit colwnns 1 and 2 were the
same. Tbis shows that the drcuits m Rguics E8-4A and E8-3A are pcrfonning
the same function. It is apparent that thc AND ftmction is bcmg perfbnned by
the ouiput AND gate in Uie cquivalem negarive AND drcuit of Rgurc E8-4A.
How is this being donc in Rgure E8-3A?

Tbc two opcn-coUector NAND gatcs in Rgure E8-3A are conncctcd as inveneRS.
Howcver, invencre of thcmsdves can not pcrform ANDing ftmctionsi. Thc only
cooduaon is flîat the ANDiag is bciag donc at thc common coimcction point
Tlus is fliejuHction ofoucuts 3 and 6 ofdic NAND invcnens and thc 1 kQ puU-
upicsistor.

To fiuûier verify thc wired-AND ccHmectiai, you wired thc circuil in Rgure
E8-5. bt step 11. you qiplicd uqnits accorduig to Table II. You recordcd cw-
nqxmding ouçutsin cohunn 1 ofTaUc IL Li saqp 13. you wroie the ouqnit cx-
picssion Ffor tbc O ougwts.
JFaXBCD + ABCD + ABCD + AB^ + ABCD + ABCD + ABCD.

Wth flie use of Boolcan algcbra, you nsduce thc cxpresaocL Your reduction
ShouM be sùnilarto thc following:

Thc first step is to iise the Laws of Commutadon to regroup tcims and factors.

ÂCTC+XCDB+ACDB+ACDB + AB^ + ABCD + ABCS

 DlgltalTechnlques | 73

Next, factor out the conunon Tpintcnns. ACD in the first two tenxis; ACD m
tcnns 3 & 4. ABC in tenns 5 & 6. Igaore tcnn 7 for now.
%CD(5+B) + ACD<5 + B) + ABW+D) + ABCS

By thc Laws of Complemmts, this becomcs:

ÀCDO)+ ACDQ) + ABCO) + ABCS

By the Law of Intcrscctioii, this bccomcs:

ACD+ACT + ABC + ABR)

Ncxt, factor out canmon mintcrms; CD in thc first two tcrms. AB in tbc last two
tcnns.

CT»(X+A)+AB(C+CD)

Next. use thc Law of Complcments oo the first cxpresson and the Law of Ab-
soxi»ionm the sccond. 'nie resuU bccomcs:

CDO)+AB(5+D)

Using the Law of Inicrscction on the fiist cxprcssion and DcMoigan's thcoicm
on fte second. you bavc:

CD+AB(CD)

Using the Law of Absoipdon again, you havc:

CD+AB

Using thc Law of Commutation, you havc:

AB+CD

Bccausc fte original cxpression was derived from the logic Ooutputs, you must
place a vinculum ovcr thc final cxpression. The final cxpression becomes:
F=AB+CD
74l STUDENT WORKBOOK

In step 15, you drew tfie equivalent circuits for the open-coUcctor circuit of Rg-
urc E8-5. 'Iliese drcuits usc the standanl TTL ICs. Thcy shoiud appear as shown
in Rgures E8-7C and D. Widi thc ncuts shown, uss ouiput of cach cquivatent
circuit matdies thc final result offtc simpUficd cqncssion (AB + CD).

fa stcp 16. you wired tfac circuit ofFigure E8-6A to lurflicr venfy tiiat a standari
TTL cuarit must haw an acttial oaxpat AND gate to accomplish the samc logic
lùncrionas thc opcn-coBector wucd-AND.

ATÎ

CT
B. > ffB)(5B)sÀ"ï+"co
c.
CT >
>

Â
AB
B
JTBTETD
ÇD
5

FigureE8-7
Standaid TTL Equivalcnt Orcuits.

In step 17, you ^ppUcd tfae inputs in^cated m TaUle U. You recordcd the cor-
reqxmding outputs in colunm 2 ofTaUc IL A comparisoa of columns 1 & 2 in-
dicates that bodi circuits funcrion flte same logically. "niey are cquivalcnt twt.
thc open-coUector circuit of Figure E8-5 requires only ODC IC. die 74LS03. Thc
obvious reason is that flie conunon conaection on the outpat is perfonnutg thc
AND ftmction. In the standard TTL cucuit an additional AND IC must be used
on tiae ovxpaL Becausc fewcr ICs are required in the opeiM»Ucctor drcirit, it
uses less powcrto accomplish (hc samc nsult.
 Dlflltal Technlques | 75

Experiment 9
Set-Reset FIîp-FIops
Objective
To demonstrate the operation and characteristics ofa set-reset (latch)flip-flop.

Materials Required
Hcadddt Digital Trainer

1 - 74LSOO TTL quad two-input NAND gate IC (443-728)

1 - 74LS02 TTL quad two-mput NOR gate IC (443-779)

Procedure
1. Wire the latch circuit shown m Rgurc E9-1. The set (S) and rcsct (R) in-
puts to thc latdi will comc fium the  and B oucuts offlie two logic
switches. Tbc A togic switch is the set iiyut. the B logic switdi is the reset
iapoL Thc latch ouqnits, Cand £,wm bc displaycd on LED indicators Ll
and L2 respectivdy. Be sure to apply power to thc IC by conacctiflg pin
14 to +5 volts and pin 7 to GND.

1C.74LSOO

"-L1

"-L2

Figure E9-1

With ûiclogic switches in thcir Àand B positions. what is the state of the
S and R inputs?.
76 I STUDENTWORKBOOK
Apply power to thc Trainer and note the state of 'he latch by obscrving
LED iiuficatorLl. Ll = binaiy_.

Using fte logic switches, apply flic logic levds dcsignaied in Table I to
tf»eS and R iqputs ofthc latch. Obscrvc thc ouqnit conditions on the tED
indicau)rs for eadi set of iicwi states. Record your ouqwt statcs in Tablc I.

TABLEI
INPUTS OU1TUTS
S(A) ROB) C(LI) C(L2) STATE

1 I

1 o
o 1

o o

In fhc coluian maited STATE u»Tablc I, writc a singlc word dcsignating the
state tcprescnted by eachset ofoucnits.

To get a fcd for how Ac circuit operates, play with thc inpuis w^ile obscrving
fhc ouçuts. By repeatedly putting the latch into thc sct, reset and ambiguous
states you wfll understand it beuer.

3. CoDStroct ttc cucuit d»wnta Rgure E9-2. Thc set and resct input signals
comc fipom logic switches A (set) and B (reset). With thc togic switches in
ÛieirA and B positions, wfaat Is thc state ofthe S and R inputs?

a»-74tao2
B—»
"-L1

"-U
A—

Fïgure E9-2
 Dlflltal Technlques J 77
4. Apply powcr to the circuiL Noie the statc of tite latch by obscrving Ll.
Ll = binary" . Tben apply tbe ùçutsgivcn m TaUe Q.
Observc the ouçuis for cach set of inputs and complcte the D and D
columns.

TABLEH
INPUTS OUTPUTS

S(A) RCB) D 5 STATC

o o
o 1

I o
1 1

In fte column labélcdSTATE, m TaUc II, writc a woid thu designates thc
statc of thc latch as indicated by cach of the output indicatioiis.

5. Comparc thc data in Tablcs I and II and notc thc simUaritfes and dififcr-
cnces in opcrarion bctwecn the NAND and NOR gate latchcs.

Discussion
In Swps 1 and 2. you constructcd a NAND gatc latch usmg a 74LSOO IC. Tbe
iiçutswens obtained fiom fte logic switdies. The À and B ouçutsof these logiç
switches were uscd to suRfly thc sct and reset inputs respectively. Tïie A and B
ouçutsare noimâUylu^ Whcn ûieswitch is dcpreScdrthcAor5 ouçwt goes
low. With boûiswitehes in flicir nonnal or npn^Icpresscd state, thc S and R in-
puts to dac lateh are binary 1. Tbcnsfore. thcy baye no cffcct on thc statc of tbe
latcfa.

Wben powcr is applied the laudi can go iato cithcr statc. The C puqwit could bc
cither O or l as indicated by LED mdicator Ll. Rjegardless of the imdal state. C
and C should be concilcmanary.

When logic switdi B is actuatcd. a low lcvd is appBcd to the resct input Tl»C
output (Ll) shouM go low and the C (L2) output high. Whcn switch B is
relcased. the flip-flpp wm remain resct thcreby storing a binaiy 0. Actuating
logic switch A supplies a low to thc set input Tbe C output (L) goes high and thc
çouqnn (L2) low. Whcn switch A is rcleased. the flip-nop remams set storing a
binaiyl.
78l STUDENT WORKBOOK
When bofl»Ipgic swftches arc actuated to apply a low to boûiset and resct inputs,
both C and C oucuts go hi^L This is tfac ambiguous state.

In Stqps 3 and 4 you constmcted and tested a NOR gatc latch. The set and resct
uçatsare supplied by &e nonnal ouçuts (A and B) ofthe two logic switches tm
ymir Trainer. The A and B ouqwits are aomiaUy low when the switcbcs are tut
acouucd. A low iapat to a NOR gatc latdi docs noi diaagc its statc as it does in
tbe NAND gate latch. Therefore, witfa botfi vapats low, thc latdi can be cither set
orreset dcpendiqg upaithe aibinsuysateitcomesupin wfaenpowcris appUed.

When the B logic switcfa is actuated. the B output goes high applying a Uigh or
binary l levd to the reset input Tliis forccs flie D oucut low and tfae 5 outpat
higfa thcreby indicaring that a binaiy O has been stored. Vpon rdcasing tfac B
swiich, ftc latch retams thc reset state.

When you depress thc A logic switch, you apply a high levcl to the sct mpai. The
D output goes high and the D output goes low. The flip-flop remains m thc sct
stittc wfaea the switch is released.

If you apply baaaiy 1 *s to both set and resct iiyuts at tfie samc tixne by simxil-
taneously actuating thc A and B tofiic switcbes, flic latch gocs imo dic ambigu-
oixs state. Bodi outputs go low.

In compariqg tbe NAND andNOR gatclatches wc cansay in summary:

1. Eitbertypeflip-flopwillstoreorobitofdata.withtbestateoftheoutputs
indicating ti»value of thc bit stored. The two oucuts are complcmcntaiy.

2. Thc NAND latdi requresa low-Icvcl on eithcr iapat to sct or reset it.
"nie NOR gate latch requires a hi|ft-level at fee apprppriate uyut to
gate
changc its state. .

3. When ao changc in state is dcsired, tfic latch icputs should rnnain in OTC
state c" Ae odier Origh or Ipw) Aepending upon d»type ofgate used. For
a NAN?> gate latdi, &e mpats nomuOIy rest in die hi^i state. ThcNOR
gatc latdi anputs are nonnaUy both low.
4. Botfa types of latches havc an ambiguous state. In thc NAND gate latdi
bofl»ovtpaxs are hi^L In the NOR gate latch. bpth oucuts are low.
 Dlgltel Technlques J 79

Experiment 10
D FIip-FIops And Registers
Objective
To demonstrme the operation cfa Dflip-Jlop and a storage register

Materials Required
HcatMdt ragitàlTrainer

1 - 74LSOO TTL quad two-input NAND gate IC (443-728)

1 -4001 CMOS quad two-input NOR gate IC (443.695)
1 - 74LS75 TTL four-bit bistaUc latch IC (443-781)

Procedure
1. Wre fte circuit shownin Rgure E10-1. Usc a typc 74LSOO IC. Bccausc
of the laigc numbw of caancctions requinsd, takc your time to avoid mak-
ing a wiring mistake. DouUe chccl!: your conncctions bcforc you pcrfbnn
the csqwrimeut. Don't foigct to coanect pin 14 to +5 volts and pin 7 to
GND. The D and T ucwts wffl be supplicd by daxa switchcs SW1 and
SW2. The flip-flop ouqwits will bc monitoicd on LED indicators Ll and
L2.

_74tSOD
SW1.

> "u
>

J^ "u
12 >
"'TT
JO >"
<"""—»—<

swn

Fieure E10-1
80 I STUDENT WORKBOOK
Set input data switdies (SW1 and SW2) to trinary O and tum the Trainer
on. What is die state of the flip-flpp ouçut? Q = binary _.

Leaving d>e T inpot (SW2) at binary 0, îwitch thc D iiqiut (SWI) between
binary O and buuny 1. Docs ttc flip-flop ouqput (Q) change? _.

Set thc T uput to bmaiy 1, switdi ttie D uyut betwccn binaiy O and U-
nay 1. Does &e flip-flop output change?_.

For a more graphic indicarion ofcxacuy wfaat takcs place. replacc tbe data
switdi on ûieD wput witfa a logic dock signal. Set thc clock frcquency to
1 Hz. Set flie T iqxtt fiist to Irinary 1 and obsenrc thc flip-flop outputs fbr
a hricfperiod. Note the xdationship between the dock staic and thc Q out-
pat. Set the T iiçutto binaiy O and again obsttvc the ouqwts.
4. Ccmstroct thc cucuit showh in Rgure E10-2. Use a 4001 CMOS NOR IC.
Usc data switches for thc D andT ixyuts and LFP indicators for Ac
ouçxns.

-<0flni_
wn- -B

3Z>

ï>- =s~>
"u

t,....

niB
T-T 114

*5V

FipireElO-2

5. Set iiçutdata switches (SW1 and SW2) to lanary O and tum ûteTraincr
00. Wbat is tfae state of the flip-ûopouiput? Q = binary _.

Lcaving ÛKÏT ncut (SW2) at tunaiy 0. switch tbc D uyut (SW1) bctwccn
binnyOaid binaiy LDoes the flip-flop ouuput (Q) change?_.

Set the T iapttt vo binaiy I, switch thc D inpat betwccn binary O and In-
naiy 1. Does tte ffip-flop outpw change? _.

6. Repeat Step 3 for the NOR D fiip-flop.

 DlflItalTechnlques J 81
7. Comparcyounesultsinstcps2aad5andinstq)s3and6.

8. Wire the dreuit shown in Rgurc EIO-3. 'Ilic 74LS75 IC cdttauis four
TTL D flip-flops similar in pperation tp tfae NAND D flip-flops discussed
cailier. Rgure E10-4 shows the intemal scucturc and pin conaecdons for
this dcvice. Notc that +5 volts is coiinccted to pin 5 and GND is caanccted
to pin 12. The dau switcfaes on the Trainer are uscd as a swtch icgistcr.
The switch outputs are used as a sowcc of data for a four-bit repstcr niadc
Irom the flip Dops in the 74LS75. You wfll monitor thc rcgister ouqmt on
the LED logic mdicatore.

Logic switch A is used as the LOAD, or strobe. signal which transfers in-
put data ixuo thc registcr.
74LS75
NS8 16
SWt D G u

r o

SW2 î Q
15 u
_î r Q

SW3 _( > o 10 u
" o

1 u
J
» o
SW4
L88 5, 45V
_4 o
!2_

+ LOAO 1
FigureElO-3
82 ISTUDENTWORKBOOK

r4wt-FSUïïl-R3lJ^-FTUî5Uîl-,

'-lij-tij-laj-tiny-tsninju-1
«cc
74tS»«
roURW B«ST*a£tATCH

FifiureElO-4
Tpp view of74LS75 TEL IC
(quad D flip-flops).

9. Apply powcr to Ac circuit and ncoid thc numbcr in tbe register. Indicator
L4 mmitots the LSB.

10. Sct all of flic data switches to lunaiy O. Then momentarily dçpress ûicA
logic switdtL Recoidthe bùiaxynumberin&e register.

11. Set aB the data switches to Irinaiy 1. Deprcss the A logic switch aad note
CStVOStttttSL

12. Load the suiteen lanaiy numbus 0000 througb 1111 uno flic register onc
t a time by seuing the data switches, then actuaring thc A logic switdi.
Vcrify flut dic iqwt does load by comparing tfae LED indicator states with
flic data swiuA settiog afnsr tbe A logic switch is dqncssed.

Discussion
In Stq» l you cansûucteda D ffip-flop wiûiTII- NAND gates. When you ap-
plied power in Stcp 2. thc fBp-ftop could havc assumed cither the sct or resct
state.

IfttieTiiçutisbinaiyO.dic flip-flopsiateis dctennmcd by tfac previous iapaxs.

Switdring thc D nqiut bctwccn O aad 1, wfaile T is binaiy 0, will not ajffect tfae
state of Ae flip-flop. With Ae T uqnit set to buuuy 1. you can switdi ûieD uçut
betwcen Irinaiy O and 1 and watdi tte nonaal oirtput foDow it.

In Stq) 3 you ap(riicd Ac 1 Hz dock sgnal to thc D ncut and observcd tiie op-
eratian oftite flip-flq). Wdi T set to binaiy O, tfac dock signal at tfac D ùçutis
igaored. Bm witti T set to binary 1, tfae flip-ÛopouçatfoUows the 1 Hz D nçut
 Dlgltal Technlques | 83

to Stcp 4 you asscmUcd a D flip.flop finDm CMOS NOR gates. In Sttps 5 and 6
you cvaluated its operation. BasicaIIy you should havc foimd that its operafion
wasidauicaltottiatoftheNANDDflip-flopwithtbcotcqptionofthe siateof
ïfac T iigmt. On tfac NOR D fly-flop. thc T iiçutaust be low in onter for the D
inpvtt to be recogmzed. With the T iiqnit low, flic nonnal ouqmt follows or tradcs
tbe DiicmL Whcn theTinput is hi^h. the D input wffl have no cffcct on tbe state
offlieflip-flop.

fa Stcp 8 you asscmUcd a 4-bit storagc registcr iising thc four D flip-flops m a
74LS75 TTL MSI IC. The operarion of the flip-flops m this devicc is sunilar to
theNANDD flip-flopyou sudied eadicr.The dataswitcbesonthcTrainerwere
uscd as a switdi register.Thc A logic switch is used as a manual LOAD controL
Tlte A output is nonnaUy low thereby teeping thc T iicuts to all four re^stcr
flip-flops tow. Thc iaputs from thc switdi registcr are ignored. Wbcn the A
switch is acaiated, AeA output goes higfa causing tfae data from Ac switch regis-
ter to be loaded imo fec ngister.
Whcn you first applica power, thc contaas of thc w^ster could havc bcen any-
thing. Whcn pcwer is appUed to a flip-flop it can comc up m cithcr thc set or
reset condition. Ncxt, you reset thc register by loading aU binaiy 0*s. Thcn. you
loadcd 1111. These two operarions cfacck to sec that aU foxu- flip-flops woik. m
botfastates.

RnaUy. you sequcntiaUy loadcd the numbcrs 0000 tiirou^i 1111. This givcs you
an opponunity to become famfliar with setring txinary numbcrs on thc switch reg-
istexs and practicc in reading binaiy numbers fiom thc I.ED indicaton;. An im-
ponaat point you shoifld have graspcd is that the input word can bc different
from thc register contcnts. Wth dic LOAD ircnit low, Ae D inputs to the flip-
flop arc ignored. Whcn LOAD is made iBnary 1, howcver, dic register ouqiut jbe-
comcs cqual to thc inpuis.
84 ISTUDENTWORKBOOK
 Dlflltal Technlques J 85

Experiment 11
JK Flip-Flops
Objective
To demonstrate the operadon and characteristics cfaJKflip-flop.

Materials Required
HcatUatDigitantainer

1 - 74LS76 TIL dual JK fly-flqp IC (443^29)

Procedure
1. Ooonect fl»edrcirit shown in Figurc EI 1-1. Usc data switdies for tbc J, K.
S, and C uqauts. Utc logic switch A for thc dock T input CoDncct LED
indicatOBs to c»di output TbcfHn coniicctioas for thc 74LS76 dual JK
fly-flop are shown fe Rgure EI 1-2. Thcac arc two idcnrical JK flip-flops
inflic74LS76 IQ but wc wffl use ordy onc. CODDCCT+5 volts to pin 5 and
GNDtopinlS.

»M

,IP.:7A53?4?..

svn 1ÎL u
<t 0
A T
SW2 W! u_ 1.2
K Q

<w
-î A^

[3
13_ ONO

SW4

Figure Ell-I
86 f STUDENT WORKBOOK

GND
r=@-@-@Uî3yî3I-F?-®-fîl-i

'iit-ïii-iirunir-t^nznj^-1
«cc
RgunEll-2
Pin connectioas for dual TTL JK
flip-flop74LS76.

2. F5rstyouwiUchedctheasynchronousoperationoftbeJKflip-fiop.SctJ=
K*=l withSWlandSW2.ApplyttielevdsmdicatedinTaUeItothcS
and C iicuts. Notc the oucut statcs and recoid them m TaUc I. Repcat
tfais step with J s K e 0. Recoid the results in Tablc L

Do the JK ùçutsaffect thc asyachronous pperation?, .

TABLEI
J«K»1 J.=K»0
INPUTS OUTPUTS OUTPUTS

s c Q ç Q ç
1 1

o I

I o
o o
 Dlgltal Technlques | 87

3. Ncxt, vcrily the syndmmous opcration oftteJK flip-flop. Remove thc

WÙCmmwying dic Q OUCltt to ï CTÎ indîcator L2. Setthc S and C iqnits
to Unaiy 1. Tbcn apfty dic logic levds iadicatcd m Tablc ILNote tiie nor-
màl output statc bcfore (Q) ax»dafter [Q (t+1)] Ac appUcation ofa singlc
doclc pidse from flic A togic switdi. Aficr you bavc completcd TaUe II,
repcat d»ciapass gwcn and togglc the dodf. ÇDiapat scvcral timcs wifli
thc A logic switch for cach set of iiqïuts. Note flic results on tfae LED logic
indicators.

TABLED
INPUTS oumrrs
J K Q Q(t+l)

o o
o 1

1 o
1 1

NOTE: Q (t+1) xneaas flic statc oftfae Q ouqiut aftcrtihc q»plication of onc
dodc pulse witfa tte ghm nçnus.

4. SetthcJaiidKuçutslobmaryl.fflidûicSandCuçutstobinatylwith
the logic switches. Rcmovc tfac A logic switdi fiom the T iaput and con-
nect a l Hz dock (CLK) signal to iL Also coancct a spare LED logic in-
dicator to monitor tte CLK rignal. Observc thc GLK ispat and Q oulput
oa fte T.RT) mdicators. What is thc relationship betwcen ùçutand oucut
fitqucndes?
88| STUDENT WORKBOOK

5. ConstructfliecixciritdiownmRgureEll-S.'niccircuitwiUbe drivcn
fiom the 1 Hz CLK rignaL nc A and B logic switches wffl conuol the
cuctrit You wffl obscnw the ouc»atstatts on LED indicators L3 and L4,
and tbe CLK input on LED indicatorLl.

NCyiE: Tbs Iflgic Icvd of the JK flip-ftop's Q oucut is not saxïDg cnou^i
to drivc bofli tfae next flip-flop and an LED. Tliensfore. you wOl usc a
74LSW bex inverter on tbe Q ouqxrt to drivc tbc LED.

7?*'?7'.-.-__J2_._ ~IB '~»7

L1 18l U
y—«~»——^—«——ï^—^«s.——.^.s———.«^»—

:l^^§:î]:t1
FRt

48V

A-»-
-£=^J 1<i
«av-
y "»"""<"""—<""»—"—"fr*«»i "I u

Figure Ell-3

Obsave the idationsinp bctwcen flie vaput (Ll) aad oxiqwt (L3 and L4)
wavcfoxms. You can do diis by coiStitigthe mimber of input and oucwt
^'f^tcft 9 tiTn'nfr diagrana iUustraring uris relationship.

Wbnc Ûïccircuit is opcrating. dqpress and hold tfac B logic switch. What
efiect docs das have on flic ciicuit? (Note Ae ouqput statcs). Rdeasc tfae B
switch. Rqpeattfais stiq) scvcral times.

Depnss and bold Ac A logic switcb wlrile thc cucuit is opcraring. Note
the cflTcct oa thc ouqxtts. Rdease dic A switdL Repcat scvcnl tnncs.

NOTE: ffyou havc an osdlloscope, sct tbc CLK frequcncy to I KHz or 100
KHz and obscrvc CLK. FF1 and FR2 noting thcir fipcqucncy relationship.
 Dlflltal Technlques | 89

Discussion
In Stcps 1 and 2. you wrified the opcration of tfae JK flip-flop m tfac
asynChrcaous mode. "nus refas to dic use oftiic sct CS) and clear (O or nsct in-
puts to connol thc state of the flip-flop. From dic data you recoidcd in TaUe I,
you should havc found that the JK flip-flop fimcdwis just Ukc a NAND latdi
wben tfic S and C iicuts we used. With boui nqwts binaiy 1, the flip-flop can be
in cither state. Whcn Cis low and S is Iri^i. the flip-fiop is icset Wth C hi^i
and S Iow,fbc flip-flpp is SCL IfboA S and C arclow, thc amtriguous aate (Q=
IQ = I) OCCUFS.

to stqïs 3 and 4, you verificd thc synchronous opcration of ftc JK flip-ûop.Thc

most imponant poixds to note are:

1. ItisnotthcJKùçniisflMtcauscthestatcoftfacflip-floptochangc.Itis
tfacT nçnit l to O traosidon tbat causes tiic statc cfaangc. Thc J andK in-
puts do ddcnnme the statc to vdrich tfac flip-flop gocs but not wton ft
dianges.

2. llïc Qsp-ûtfptoggles or complemcias cach timc a 1 to O changc occurs <m

tfac T iiçutwitti J = K = 1;

3. Theflip-flopdoesDOttogglcwhenack>c]cpul»occiusifJ=K*sO.TIris
makes tiae SK iapuxs uscfiil as a togglc inlubit coDtroL

4. To resctlhc JK ffip-flop. s^y a O to tbc Jic^ and a I to tfac K^

thcn <ç)plya dodc pulse.

5. TosctfheJKflip-flop.applyaltothcJnçutaDdaOtoAcKhgïut.flten
sp^y a dodc pulsc.

6. ForeveiytwolMnaiylixçiutpulscsonT.oDcbinarylpulKoccuisatthe
Q ouçmtThis inditftft's a two-to^nc ficqucncy diviapn.
90 1 STUDENT WORKBOOK
In Stq> 5 you cascaded two JK flip-Sops and in Stq> 6 you detcmuned the
input-ouqout relationships. By observiag thc IT?D indicators you should have
found tbat for cvciy four binaiy 1 dod: iiçutpulses thcre were two pulses fnnn
FF1 and taic pulse fiom FE2. This itxUcates thatcadi flip-flop divides die nput
frequcndes by 2. The overaU cucut, boai fly-flops togcther, divides by 4. 'nic
uçwtis 1 Hz. Thcouçut ofFFl is J Hz aadfltc ouçutofFR2 is JS5 Hz. Your
nçïut-outputwavefonas should sppcw as diown m Rgure El 1-4.

M) (1) CtK r~lJ~U-LJ~LJ~lJ~1-J

1SEC

(U) ^ O I 1

tl^) FR o j
FifiureEll-4

to Step 7 you used tfac B logic switdi to control flic JK nyuts to FFI. WiA UB
switch in its nomul poatfon, thc 5 ouiput is binaiy l. Tbetefon, tbs JK iqwns
are buuiy 1 and the^fBp-ftop togglcs with cach dodc pulse. Wben you dqne'*s
thc B togic switcfa, 6 gocs tow. This inhilrite FF1. Thc dock pdses will not af-
fect it with JsK*=O.It wffl rimply retain the state to which it wasset ty the last
dodc pulsc prior to Ac JK taputs bccommg low. Sincc EFI does not togglc, FR2
wffl not togglc. Tlc nçuttoFR2 comcs ftom FFl.As a result, whcn thc JK in-
pias <»Hrl go low, die dodc pulsc has no effect and the fiUp-flop states can bc
ituyUtdOlg.

Whcn you dqnness tbc A lopc switcfa you resct botb flip-flpps. Wiûithe A logic
swîtch in its tionnal position. tbe Àouqiut is taff^ This puts a bmary 1 on bofli C
icpuas. This_wffl not affcct flie fl4>-flop jnates. When you dqancss die A togic
switch, flic A ouQîut goes tow. This resets both flip-flqis unmediately. Regaid-
less oftbe staies ofthc ffip-flops, wben you dqpress A, both wffl bc put uuo thc
binaiy O condition. You wfll notc Aat this reset statc ovemdes dic doclc signaL
With the C iBputs low. thc dodc mput has xio .cfiecL In a JK flip-fliy, tfac
asynchronous inputs always takc precedcncc ovcr die synchronous iqnits.
 Dlgltal Technlques 1 91

Experiment12
Binary Counters
Objective
To demonstrme the opera&onand characteristics ofa binary counter.

Materials Required
HeathUt Digital TTaiaer
DC Volcncter

2 - 74LS76 TTL dlial JK flip.flop IC (443-829)

I - 74LS193 TTL synchronous upAtown tnnaiy oountcr IC (443-815)
1 - 74LS04 TTL hex invcncr IC (443-755)

Procedure
1. On your Traincr, oonsurua flic four iMt Innary countcr circuit shown m
Rgurc E12-1. Tbc pin coanecdons for flic 74LS76 ICs are given in Rgure
E12-2. Tate care m wiriag the drcuit to avoid cnois. Bc sure to comicct
pin 5 to .t-5 volts and inn 13 to ground (GND) n»cadi 74LS76 IC. and pin
14 to+5 volts and (rin 7 to ground on dic 74LS04 IC. You wffl monitor thc
coumer ouqputs on tt*e TK" indicators. You will stq> thc coumer with thc
A logic switcfa.

Study ûuicountcr cucuit m Hgure E12-1.

Whattypcofcounterisflus?^ _.
92 I STUDENT WORKBOOK

u t3 L2 L1
4c
<sv 45V <5V +5V +5V +SV +5V
74LS76
^
-s
-r-T
ts^l»..A7^ 4 2t ll5 _l8__j7__741
"fr——fr
^""""—!>""""
741S76
""""<!"<"""""

s
J 0 7so 11
J O 7sa :11

A-»
_!6
K_ss K O K 0
^B c_
~y ^_
5W1 u
f3 114 12
u
h
is""Tiors -
1
11 (16 tt't 12 ,-!&I
TJ-
4SV <5V 4SV +5V 4SV

:14
-o^ ~{>>J
45V

1-L
3^.741504

ReureEU-l
Esqperimental circuit for cvaluating
thc opcration of a binaxy countcr.

~tLTi2Minii~tu~t£nzj~isJ~^
VGC

FigureE12-2
Pin comiection for
dual JK flip-flop 74LS76.
 Dlgltal Technlques j 93

2. Set the switch SWI to the high or up posidon. Apply power to thc cucuit.
Notc fec statcs of the I.ED indicatois. Rccord the binary numbcr siored in
the coumcr. Note: A (L4) = LSB. D(L1) = MSB

DCTA=
Depress the B lo^c switch. Note the states of the LEDs. Rccord the value
ofthe binary wonlstoxcd m the countcr.

DCBA=

Docs the changc tfiat takcs place in die ouqiuts occur on the Icading or
cailtog cdge of ftc B signal?_.

4. Reoord the imtial coumer stateobiained in Step 3 in the first (0) position
ofTable L Usmgflic A logicswitch. stcp thc counter. Each timeypu ac-
luate thc A logic switch, observc dic Tï?r» ouçutsand reconl the cpunter
comcntsinTaUeL

Docs dic coimtcrstatt change'whenyou eicpress or relcase the A lopc

switch? _. What does diis tdl you?

Observe your data m Tabte L What kind of counter did you consttuct?
_. Docs this data coxifum ypur answcr givcn m Stq»
l? When thc countcr contcnt is DCBA s 1111. wtut hicpcns when you
dq)icss tbe A togic switcfa? The counier ouqnit becomcs wfaat?

DCBA=

6. Rcmovc thc coumcr iaput finpm thc A output and connect it to ûieCLK
ouçiut.Sct tfac dock ficqucnçyto 1 Hz. Dqpress die B logic switch and
bold it Obscrvc die LED indicatois. Tbea, idcase the B logic switch and
let fl»countcr counL As it counis slowly. verify its ouqnits against your
data in Tablc L Let the counter nm untfl you ftiUy uiidcistand the count
sequaice.

7. As thc cpuntcr is countidg, sct data switd»SW1 to the low or down posa-
tion and obscive the result. Rqïeat several times to be sure you imderstand
what bappeas. What cfifect docs SW1 have? _.
Depress the B logic switdi wlule uic counter is counuog. What happcns?
. Rctum thc countcr inpul to thc A output ofthc
logic switch.
94| STUDENT WORKBOOK

Discussion
In Stqï l you ctmstructed a four-bit binaiy countcr using JK flip-flops. This is a
binaiy up countcr of thc asyochnmous or ripplc type since thc nonnal oucnit of
ooe flip-flop is connected to flie toggle CT) nyut oftfie next flip-flop.

When you apfity powcr to d»ccircuit, fhc flip-flops can come up in anyjandom
state. In Step 3 you uscd tfae B logic switch lo reset the counter. The B output
nonnally rests hi^i so that it has no cffcct on thc asynchnmous dcar inputs (Q
of Ae flip-flops. When Uie switdi isdq»resscd,5 gocs low uwreby putting dB
flip-flpps into the binajy O state. Thc countcr resets on tiic leading edgc of the B
signaL

Ncatt. you stepped tbe counter wiui (bc A Icgic switch, noted the pucut states on
tfae LED indicators and icconied them in Tablc I. Thecounter is stepped or m-
cnancnted on Ae uaning ed£C of die A iaput sigaaL The couqt nçut&om A is
nonnafly tow. Wbra you depress the A lofiic switch, A goes high and a lcading
edgc is geaerated. Whea you nelease die A logic switch, A goes low and a oaH-
ing edge is generated. Thus, ftc coumer is incremented. By scudyiag dic data in
TaUe I you can scc that the countergcnerates tte purc 8421 binaiy codc.

An imponam obsenrarion you made in Stq»5 was the recydmg of the counter
ftian state 1111 to 0000 ^icc tfae 16th input pulsc wasappUed.

Next, in Step 6 you Ict fte 1 Hz dodc rignal step thc coinuer autpmatically. The
staies diaage slpw cnpugb for you tp sec each onc, and thus bccomc familiar
wfth tfris vuy comaioa couxit sequenccand tbe recyding stqp.

You sbould havc ftnmd in Stcp 7 flut you coidd siop the countcr fiom coinuing
in two ways. Finst. by sctdng data switdi SW1 tp thc banaiy O ppsition. tfac
countcr stops. Whsî yw did was to make ttie J and K UCUES of tfae A fiip-flop
binary O aod tfacreby inhibit its pperation. Smce thc CQUDier is uie ripplc type,
naturaUy ifA doesn't toggle, neiflicr wiU any offlie other flip-flops. Thc counier
simply retains d»last state it was m pxipr tp maldng fte JK mpass low. Puning
SW1 backindietMnaiy I state sunply causes u»ecoumer to resumc counting.

You can also stpp flie ooumer by resetting it When you dcpresscd thc B logic
switeh, flic counter deated. Asloug as flie B switdi is actuated, fltc clock pulscs
havc no cfiect. Thc asynchronous Clcaruyuts! ovemde thc cffcct pfutt dock.
 Dlgltal Technlques j 95

TABLEI
D c B A

o
1
2

6
7

8 .1
9
10

II

12

13

14

15
96 I STUD6NT WORKBOOK
Procedure (cont.)
8. ModaydiccountcrtoconfonntothccireuitmRgiucEl2-3.BccarcfùIin
making your wiiuig changes to avoid CTrors.

Study tfac coumcr rireuit you bavc just wired. Wbat Idnd of counier is il?

U U L2 L1
+A ^B iC 4o
«sv <W 45V 1 *SV ^SV »5V 45V
7«S
"^iis.^?...^.î«.......^ j l»-j7-74u
.iç...lî..j.7..74lsw
"...^4^....{,2....(,iç., *«*|>rN»»4»»»»w»;

±-
"» Q IF^—MI L-|7^]J
s' I :'
"I
s
O
w
A-» T
J& KCB KAS liol K .0
^. ^
«wn y
'T5Is u
"-&"
1« Ï1Ï2"
<w
-TsJ-

«w
'""+"6

«8V
[3 li4i Ï2

«5V
r"1
<»sv

Figure E12-3
Experimcntal Qrcuit for Steps 8, 9. and 10.

9. Apfly power and note thc countcr output statc.

DCBAs

Now momeatarily dqncss thc B logic swiudi. Rccoid fbe

comttcr ouqxit state bdow.

DCBAs

Whatfaappcnedhere?!

10. RecotdthccounterstatcobtainedmthelattcrpanofStcp9uithcfirstpo-
sitim ofTable II. Usc the A logic switch and siep the coumer. In TaUc II.
reconi &e coumer staie after cach actuation of switch A. Continue stq>-
png dic counter unta you fill Table II.
 Dlgltal Technlques J 97
11. Conven the Unary iiumbers you recorded ui TaUe II uuo dieir decimal
cquivalcnts and ncord thcm in thc far ri^tt hand column ofTable IL

12. Observe your data in Table H. What Idnd of countcr is dus?

. Docs this confinn your answcr in Stqp 8?
13. Connect the countcr ùçnttto ihe CLK output (l Hz) as you did m Stqp 6.
Lct thc circuit coum. As you do, observc the oinput staies and compare
them to your data m Tatfle H. Let tbe countcr nm for a whïïe untfl you sec
the couxit pattcmor scqucncc.

TABLEH
D c B A Dccimal
98 ISTUDENTWORKBOOK

14. While fbe counter is stq)ptag, set the SW1 logic switch to binary 0. Note
dtc tcsult Next, wfailc tisc csmaaer is stepping, dqncss the B logic switch.
Whathappens in cadi case?

Discussion
In Stq» 8 you consttucted a Unaiy down counter. Thc oomplcment oucut of
each flip-flop is connccted to the T input of tfac next in sequence. As iqiut pulses
are sppKed. Ae couater is decremeated. Eadh iapat pulsc decicascs the number
in tise coumer by one. Whcn tfie count is reduced to 0000, it wffl recydc to its
maîdmum coum (1111) when tfae next dodk pulsc is îçplied.
You should havc found in Step 14 flut flris down counter drcuit responds to the
B topc switch (reset) and SW1 data switch cxacdy like the binary up coumcr.

Procedure (cont.)
15. Wre thc coumcr drcuit shown in Rgure EI2-4. Usc a 74LS193 IC
(443-815). Bc sore to connect +5 volts to pm 16 and ground to pn 8. TT*c
pia connections for the 74LS193 IC are shown in Rgure E12-5. You wffl
stq> tbe ooumer widi thc A logic switch and reset it with tfac B logic
switch. The data switcbes SWI throu^h SW4 scrvc as a paraUd daia
sourcc for presccing the counter.

14 L3 12 U

1111

,r y'7q--r»^
CLEAR

B 4W SW4 SW3 SW2 SW1

FigureE12-4
Counter cuaut uang a 74LS193 IC
 Dlgltal Technlques J 99
INPUTS OUIPUTC wnns

] I < 1 1

*-tL}~i£j~tininin£MineTJ
j.<~T'i^'~T
OUIn"s
J,ourpuTSÏSns'
wtsin
SVNtanOMCXIS UnDOWN BttMtY COUWTH»

Figure E12-5
Pin connccûonsfor 74LS193 IC
tnnary up/down countcr.

16. ^iply power to thc circuiL Ifthe stateoftbc counter is other than 0000,
reset it wiûithe B lugic switch. Step tbK countcr 16 times wiA ûicA logic
switch. Note thc output states on the TT7n indicators after cach stqp. Com-
pareûiestatestofliose you recordcd inTableL
What type ofcount scqucnce docs this IC counter gcncrate?

17. Reversc tfie wires at pins 4 and 5 ofthc IC. Resct the counter wifli the B
lo^c swftch. Apply 16 pulscs witfa Itoc A lopc switch and observe fhe
couDtcr ouqput states. Compare fliem to thc data you recorded in TaUe II.
Whatkmd ofcount scqucncc is generated? ,^

18. Rcmovethewiresconnectedtopins4 and5oftheIC. CoDnectirin4to

+5V and pn 5 to GLK. Bc surc the dock; frequeocy is set to 1 Hz. Con-
nect a DC volonetcr bewccn GND and pin 12 of tfac IC. Set the meter for
a rcading in tbe O to+5 volt range.
1001 STUDENT WORKBOOK

19. Notc tfac votaneter reading as flic counier is stqipcd by the clock- Rccord
bdow. At somc pomt in the coum cyde, thc voltage at pm 12 will change
momcntarily. Whcn it does, notc thc itew oucut voltagc and Ae bmary
statc of dic oounter dunng the duagc. Rccori bdow.

Voltagc atpin 12 bcfore thc cfaaigc volts.

(duriqg counting)
Voltagc at pn 12 after the chac^gc volts.
(motnuaataïy)
BinaiyCodcDCBA! . (during momcntary dtiange)

20. Rcvencfliewiresatpns4aad5ofdicIC.CoanectAevoltmctertopin
13. Repcat stcp 19. Recori thc data bdow.

Voltajgc at irin 13 befoxc changc volts.

(during ooumine)
Voltagc atinn 13 afterchangc volts.
(aioincntaiy)
Binary Codc DCBA < . (during momciitajy chaiigc)

21. Rcmove thc wires at pias 4 and 5 ofthc IC. Coancct pm 4 to +5V and pin
5 to tbe A oucut oflogic switdi A. Removc thc wirc bctwccn B and pin
14 aa flie IC. Cannect pin 14 to ground. Coancct B to pm 11. Thc DC
volttnctcr can also be removcd at flus timc.

22. Set aU of the data switcbcs (SW1-SW4) (o binary 1. Dqncss the B logic
gwitch. Note flie oug»utstatc ofAe counter.

DGBAs

Nexx, set all data switches to binary 0. Dcpress dic B logic switch and ob-
scrve thc 1JcfD indicators.

DCBA
 Dlgltal Technlques 1101

Set fte data swnches to die woids as follows. AIter cadi word is sct into
thc switches. dq»ressthc B lopc switdi and notc thc couffler oate ofttac
LED indicatois. Comparc dus siatc to flic daci switch scttings.

SWI SW2 SW3 SW4

0101
1 O 1 O
1 O O 1
O l 1 O

What oondusioa can you draw fiom this stqï? What ftmcdon is talang
plaoe? __ __ _.
23. LcavcdicdataswitcticsscttoOllO.DqïressthcBlogiçswitch.Notcthe
counter state. Tbcn start stqipiog thc countcr with thc A logic switdi.

Whathanpais?.

Discussion
TIic 74LS193 is a TTL MSI up/down countcr. It opcrates synchronously and can
be preset QMiraUd loadcd) &om an cxtemal 4 bit data sounx. ID Stq> 15 you
wired ttris IC as an up counter. Tlic counter is deared wben B switcbcs fiom low
to hig}L Thc couiitcr is mcrcmcotcd wùmflic A logic switdi is actuatcd. Tbc
state changc ocaus on the binaiy O to binary 1 Ocading cdge) o-aisition oftheA
sipiàL As you detcnnined by obscrving flic ouçuts. thc 74LS193 counts in
thc pure Unaiy codc. Tbc oucnits should be identical to thosc you reconled in
TaUcL

In Stq> 17 you applied tbc logic switdi A ooum pulse to tiic down coimt uciut
With flris ccumection thc counter is decremented cacfa timc you press the lopc
switch. Your count scqucncc shCTild bavc becn idcmicaL to Û» scquoacc you re-
cordedinTabIcJL

In Steps 18.19 and 20, you detemuncd thc ppcrarion ofdie cany and boirow out-
puts. The coumcr was stqppcd by thc 1 Hz clock and you momtored thc oulputs
witb a DC volnnetcr. During thc up count scqucncc in Stcp 19, thc cany ouciut
should havc becn high (aboul +3J5 volts). Whcn tiac 1111 statc occius. thc casry
ouçutshould go low (about +0.1 vote) mwncntarily. The cany ouq»utindicaies
thaiAc maximum coumcrvaluc has bccn reacbcd.
1021 STUDENT WORKBOOK

In ifae down couat scquencc in Step 20. you monitorcd tfac bonow ouqwt at pin
13 wiûithc voltmeter. This auapm shouU also bc M^i during tfac OOUOL But
wtvm the 0000 state is nadied, flie bonow ouqiut goes low momentarily. Tbe
bonow aatpat detects tfac mmiiTiipn coumer value. To cascadc 74LS193
counteB, thc cany «ndboirow owpssts of onc comuer arc coaaccted to tfae up
and downcouDtixqxasicspectivdyoftfaciicxtcouDtcrmscquence.
In Stqïs 21,22 and 23 you demonsttated how the counter could bc preset Thc
data switcbes SCTved as your 4-bit paraUd sourcc, and you wired tbc B logic
switch to thc load hcut COTÛDI(pin II). You should have fomid that thc counier
statc bccamc the samc as tfae data switeh state wben thc B logic switch was
éepsesaed. Ymi partUd loaded the data switch won! imo the countcr. Thc fiast
mçxmant point to ranember is tiut tfae coimter assumcd thc state oftfae parallel
iapaas nçgaxdlcss of its prcvious coiueats. In other woids, you did not havc U)
leaet ttae coaneri»iortopnesttting it Second. flie loadhtg occius when Uic load
japat tjnn II goes tow.
Rnàlly,in Step 23 ymx stqiped Ac coumer aftcr presetring it to 0110. Fflch ac-
tuation of &c A logic switdi diould havc incrememed the couraer. This iUus-
tnues ûatflic count tcquencc simply stans at thc preset point and continucs m
the nonnal lanaiy sequenoc. The same app^es for down couiiring.
Ranemberthcsc operatiag deuuls offlie 74LS193 cxnmter as you wiU usc it later
in dcinousoïtn^g wmT(T tipFtications.
 Dlflltal Tcchnlques J 103

Experiment 13
The BCD Counter
Objective
To àemonstratethe operaûonofan integrated circuit BCD counter.

Materials Required
HcatUdt Diptal Traincr

1 - 74LS90 TTL dccade coumcrIC (443^13)

Procedure:
1. WrefliccwcuitshowninRgureE13-l.youwiUusca74LS90TTLMSI
dccadc countcr. You wiD step flie countcr firom togic swiuA A. Tbc
coumer wffl be resct by usmg data switch SW1. You wSl dcmonstnac tfae
presct lo nine operarioo using data switch SW2. Thc coinucr statcs will be
shown oa the LJED mdicauns.Be sure to coancct +5 volts to pm 5 and
ground to pin 10 on&e IC Tt»pm oonnectioas for tfais dcvicc are shown
inRgureElS-l

14 U U t1
«WNC OA oo aSOB oc
r"UioU«UT]
112
-ï- IB 111
IB —D
BC

PRESETTOB

swz
FigureEl^l IïgureE13-2
CSicuit for BCD countcr Piûconnccrionsfor thc
dcmoxistration. 74LS90couatcr.
104l STUDENTWORKBOOK
Bc siuc the data switches SW1 and SW2 are m fhe binary O position.
Next. appïy powerto fte dreuiL Observc and record the states on ÛVKLED
uidicatois.

DCBAs

Momcmarily movc SW110 the binary 1 posirion and then backto binauy
0. Recoid the ncw countcr aate.

DCBA=

to fl»cfirst posirion ofTaUe III, record the counter state dut you observed
aftcr actuaring SWI in Stq> 2 abovc. Thcn step thc countcr with tfae A
logic switch. After cach actuation of logic switch A, note tbc LED in-
dicator states and iccoxd than in Table DI. Apply a total of tcn mpat
pulscs with tte A logic switch aad complcte TaUc m. Notc paiticulady
thc couxuer state changc Drticn the 10A input pidsc is appUcd.

4. Convcrt tfac binary numbus you recordcd to Tablc m into thcu- dcdmal
equivalent and write them imo thc spaces providcd in Table m. 'nicn, ob-
acmog thc data in TaUc m, verily thc opeiarion of thc coumcr. What
type of counring funcrion docs Ais IC perfonn?

TABLEm
D c B A DEOMAL
 Dlgltal Technlques j 105

5. Momcntarilymove SW1 to tuaaiy 1 position and retum it unmcdiaicly lo

binary 0. Observc and record the siates on thc LED ixidicaiois.

DCBAs
"nien, set SW2 to
tfae buuuy 1 position momcntarily and dien reonn it to
binaiy 0. Rccoid thc new coumer statc.

DCBA=

AUemateIy setSWl then SW2to Unay 1 and badc to O scvcral timcs to

bc sure tfaat you ase what cfiEat flut these two ùqnitshave.

Rcmpvc Ae wucconnecting pin 14 of the IClo the oucmt offlic A Ippc

switch. CoDnect pm 14 tp thc ÇLKougwL Set die clp<A ficqucncy to 1
Hz. Let flie dodc acp ^ (anuuer. Obseiw dic counter stq»and foUow
flic sequence by refenuig tp te states you obtauined and reconlcd m Table
IIL Let dic comder tydc fpravdiile to be suic that you see and xmdastand
fte CCTatt scquSccAat it produces.

7. Ranove tihe connations fmm flie counter to LÏÎD indicatois L2, L3, and
L4. OrilymdicatorLI sh(niMbe«nmec^ttdic^rc^
remoying flxw conoeçticms. tesuic to n^^
1 and 12 onte IC ThcLl mdicaiw is
moaitoring flic moa agnificaat Nt of flic coimter. Rcmpvc thc ooianection
bctwecn irin W <m ifae IC and te CUK oi^^ û^^
ouçuttcnninal oflogic smtdi A.

8. Momcmarily sct SW1 lo ttc tnnary 1 position. Then. sppïy Iqgic çount
ptdses to fltc coumer by actuadng thc A togic switcfa. Count the Dumber of
pulscs flut you spfiy to tbe circuit Wtrik you are doing this, monitor Ae
ouçutstate ofLl. Radi tunc thatLI tums on and ûieno£F,udiçatcits oc-
cuncDoc ïiy maridng a I in flie maigin oftfic pagc. At that tune also note
ftc number of ngxit pulses tiut have been applicd to tine couDter up lo that
point. Each ùmeLl tums on and fhen off. stan tfae uyut coimt ovcr again.
Howmanyiqnitpulsesoccurforcadi siitglc ouçutpulsc?_.
106l STUDENT WORKBOOK

Discussion
In this cxpcrimcnt you demonstrated thc operation of the 74LS90 TTL MSI BCD
comiter. As you should have discovered finom cvaluating the count scqucncc you
recorded in TaUe ffl, tfais drcuit couras m the standard 8421 BCD codc. When
the ciicuit rcaches its maximum count of9 (1001) thc ncxt uspat pulsc causcs thc
coumer to recyclc to 0000. Tbe states 1010 through 1111 arc invaUd m a BCD
counter.

You used data switch SW1 to reset the coumer to 0. Wben powcr is first applicd
to îhe counter it can come q> in any statc. By momcntarily puttmg SW1 in the
binaiy l posirion, the counter should reset to 0.

You demonsûatedhow data switch SW2 could be iised to pnsset the counter to 9.
When SW2 is momcntarily moved to the binaiy I position, Ae coumer is preset
to 9 (1001), Thc preset to 9 ojperation is hot a widdy used countcr function.
Howcvcr, it is uscd m some appUcations w*cre cenain arithmeric opcrarioas
with BCD numbers arc canied out with the couater.

In Stqis 7 and 8 you demonstrated that the fincquency counter diyidcs by 10.
Such a cpumer is gcnerally rcferred to as a dccadc counter. Thc dividc by 10 ac-
tum is danonstBated by thc &ct Aat you shpuld havc recoided a cfaange m the Ll
output indicator for cvcry 10 iapw. pulses. Widi thc countcr stairing at binary 0,
the Ll indicator whid»mmutors the D fiip-flpp oucmt remains reset for tbc first
7 iqwt pulses. On thc <à0sûiinput pu . Ll switches on indiçatuig that thc D
flip-flop has bccn set Upon appUcatio {the 10th input pulsc, flK Ll indicator
switches ofi. As you can see from thc troth tablc you dcvdoped m Table III, fcc
D ffip-ftop isset fortwo counts. Thc D flyp-flppscts andthen resets cvery 10 in-
putpulses.
 Dlgltal Technlques J 107

Experiment 14
Counter Applications
Objective
To demonstratéseveral pracâcàlappUcaûoiisfor binary and BCD counters.

Materials Required
Hcathkit Digital Tïainer

1 - 74LSOO TTL quad two-ncut NAND gatc IC (443.728)

2 - 74LS76 TTL dual JK fly-flop IC (443-829)
1 - 74LS90 TIL dccade countcr IC (443-813)
1 - 74LS193 TTL synchronous up/down binaiy countcr IC (443-815)
1 - 74LS04 TTL hcx mvotcr IC (443-755)

Procedure
1. Refcr to the ciqperimcatal cireuit m Figure E14-1. TUis is a scalcr circuit
using couinus. Study the dxcuit and dctcniunc thc ratio ty wtuch it
dhddcs tfae iqput fiequauy. ID tfac spaccs provided bclow, recoid thc iiyut
frequençy and fhc ficqucndcs at points X, Y.and Z in the cucuit. Rcfer
back to fte qapropriatc sections in ifae umt or prcvious cxpcrimeius if ncc-
cssary to dctennine how fce drcuit operatcs.

Frequencyat: INPUT Hz
x Hz
Y Hz
z Hz
108l STUDENT WORKBOOK

L3 L4

'ï
^z
UNE
SOURCE
1/B-74LS04
45V
^""""^
~s~
1.15.J
+5V ^SV
"<--A <5V
155.
1/2-74LS76
^~ 11 s
1t J Q -1J O J O

di w_
K
_c_
0
rtlc0 t<
_c_
Q

^
A
'12
à
19 18
B C D
^"-1?"
*5V 45V
>·<1—···^····<·<
6li2"'y8""|{
!
4SV +5V 4SV
["""""""<*»«w^»»»<
1l6"'"y3"1S"1Ï3"
+5V 4SV45V -
J4| 74LS90

pj^lY <SV
r^. :4
:14 +5V
»"—»»""""»»
-î:
Î!6"-'74-LSOÏ

FigureE14-l
Scalcr drcuit for Stëps1,2, and 3.

Coiistruct tbc circuit shown m Rgure E14-1 (on the ET-1000 Trauier, thc
iiqiut is taken finom thc squarc wavc gcncrator set 10 60 Hz.) As before,
takc your timc to bc sure tbat d»ccircuit is wired conccdy. As thc evperi-
ments bccomc more sqriusticatcd, thc numbcr of ixuegrated circuits to be
iDacrooanectcd increascs. Tlus also mcrcases thc chanccs of your making a
wuing mistake. If flic cucuit does not peifonn properiy, tbe JBist tiung to
ttottCSc. is your circuit wiring. Be sure that you have connected +5 volts and
ground to eadi ofthc integrated drcants in thecxpertcnaual circuiL
3. To vcilfy the operation of die drcuit, apply powcr and otecrvc the outpuis
Y and Z on LED indicatois L3 and L4 respcctivdy. 'n»ficquency oftfic
ouQïut pulses at Z wffl bc stow cnou^h for you to coum them. Count the
numbcrofpulscs at Z thax occur in one hatfminute using thc second hand
OD your watch as a timing indicator. Recoid thc numbcr of pulscs occur-
ring in a halfminute. , .
What is the ovcraU frequency division ratio of this circuit?
What is the basic funcrion of this circuit?
 Dlgltal Technlques j 109

4. Rcfcr to the drcuit shown m Rgurc E14-2A. Study tfais cucuit carefuUy,
noting the lùnctionofcach lopc dcmcnt m tbc drcuit. Analyzc the opera-
tion of the circuiL To do this, assume that the 74LS193 counter is uritiaUy
resct AIso assume that the latch madc up of gates 1 and 2 is also initiaBy
rcset so thai the ouqmt at pn 6 of gate 2 is binary 0. Assume that the op-
crarion of the drcuit is staned by accuadng flie B logic switch a single
tirne. Assiune that the data switches arc set so that SW4 = 1, SW3 = 0,
SW2 = I. and SW1 = 0. Sketch the output ofgate 4.

y r-i SW4 SW3 SW2 SW1 <5V 2/4-74LSOO

2M-74USOO
f'
Ul1"!
L»d
11

74LS193
110
LXSB
19
\s_
A-» ;12,
G>¬D5y
1310—!
COUNT
OOWN
A B C D

LOAD yTTÏ_l216_17
ourpurs
B

Figure E14-2A
Expcrimcntal circuit for Stcps 4 and 5.

Cionsiruct the arcuh diown in Figure E14-2A. The circuit will bc driven
by logic switch A. You will obscrvc thc ouqnit of the circuit on LED iD-
dicator Ll. Set the data switches as indicated in Sticp 4.

Apply powcr to fhc cireuiL Ll sbould be ofifat this timc. To start the op-
cradon of thc drcut, dcpress logic switch B onoc. Thcn. whUe obsemng
tfac Ll ouQîiu, depress thc logic switch A scveral tuncs. Count dic mnnber
ofpulses that occur on Ll. Keep depnessing logic switch A unffl Ll stops
pulang. How many ouqnit pulscs occur bcfore Ll remains ofi?
Setthe data switches so thatSW4 s 0, SW3 s o, SW2 s= 1. andSWl ss 1.
Rccoid below the tanaiy and decimal numbcrs represemed by Ais word.
Momcntarily dcpress logic switch B. Dcpress logic switch A a number of
times, again counring how many pulses occur at Ll before the arciut
stqps.

Binaiynumber =
Decimal numbcr =
PulsesatLl =
110| STUDENT WORKBOOK

7. Udng the infonnatitn that you coUectcd m Stq» 6 abovc, compare thc
cuniber ofouçutpulses occuning on Ll wifli die dedmal value of thc U-
naty number loaded into dic 74LSI93 counicr. How are fliey idated?
What is tfae basic fùnctionoftiris circuit?

Discussion
The circuit shown in Figure EI4-1 is a divide-by-60 scaler. It acccpts the 60 Hz
wavefonn firom the lu»nnucc oucuton the Tramer and dividcs it by 60. Tlie
Z ougwt is gy ofthe iipit firequency, or 1 Hz.
Tbe mvener (74LS04) coanected between die Unc sourcc and u»mpat to thc
74LS90 tcrves only to buflfer die ET-IOOO Tiainer's square wavc generator out-
jxtt. Ifyni are using any odier trainer, flic iiivcner is not nquired.
Oose analyas of Itus circtrit wffl show flut die oucwt at point X is 1/10 oftihc
ngnt fiequcncy, or 6 Hz. Tlie 74LS90 dccade counter is uscd as a dhridc by 10
drcuit
Thc first 74LS76 IC in the circuit is connected as a divide-by-3 (modulo 3)
oomaer. The output at ponit Y thun is 1/3 of the frequcncy at point X or 6 "*" 3 = 2
Hz. This agnal is appued to oae of dic JK flip-Opps in tbc odicr 74LS76 IC. It
divides ttie ficqucncy of poutt Y by 2 to producc an ouçnrt fiSquencyof 1 Hz.
Thc agnal at Z is a 1 Hz squaic waw wifli a 50 percent duty cycte.
Sinoc Ac linc source in te Tramcr is derived fiom die 60 Hz power line. the in-
put fteyaeacy is vuy accunte. Tlic ficquency of the powcr line voltagc bas an
cnor tyiacaUy Icss dun 0.1 pCToent Fbr tfaat reason thc output ficquency at Z is
a voy accuntc 1 tecmd souroe. Wifli a 50 peffocnt duty cyde at thc output. LED
indicator L4 remains <n for (me-half «ecmidaad ften off" another half second.
When you couued thc number of ooçut pulses on L4 occuning in one-half
niinute, you diould bave iccorded a value of 30. Onc-talf minute, of coune. is
cqual to 30 scconds and a 1 Hz rignal wffl causc 30 piriscs to occur during that
pcriodoftime.
 Dlgltal Technlques J111

Thc cireuit in Rgure E14-2A is dcsigncd 10 generate a fixcd numbcr of output

pulscs upon command and then stop automatically. Tbe numbcr ofoutputpulscs
to be gencrated by the drcuit is detcmuned by the binaiy numbcr input sct mto
the data switches. For cxample, you set in the binaiy number 0101 whicfa is the
binauy cquivalcnt oftfac decunal numbcr 5. When the B logic switch is actuated
and the A logic switdi is pulscd. the drcuit will generate 5 output pulscs and
tbcn stop. Thesc ouqnit pulscs occur at the rate lopc switch A is pulsed. You ob-
servcd thunon LED indicaior Ll. The wavefonns produccd by this circuitare
fflustrated in Figurc EI4-2B.

B ~L
OUTPUT
GATE2 -J T_
ourpur
GATE4
(Ll)
rL-Tu~Ln
BORROW
LJ
Figure EI4.2B
Wavefonns for the circuit in Figurc E14-2A.

Hcrc's how the circuit opcratcs.

Assumc that thc 74LS193 binaiy counter is uiirially rescL Note that it is wircd as
a down coumcr since the count pulses arc applied to ihe down count input at pin
4. Anothcr duc that tlus devioc is bcing used as a down coumer is flic use of thc
boirow ouqput. The bonow output is cffcctive only in the down counting mode.
Assumc also that the laudi circuit, madc up of gates I and 2, is also resct. This
mcans that the output of gatc 2 is low. This low output inhibits the AND gate,
madc up of gates 3 and4, in the 74LSOO IC. The pulses from logic switch A stcp
tfae coumer only when gate 3 is cnaUcd.

Thc signal from the B logic switch is used to uuriatc the drcuil operarion. When
thc B logic switch is depresscd. the B ouqxit goes low. This signal causes two
things to happen. FIISI, it forces the load input on die 74LS193 low thercby
presetting the counter to die binary numbcr sct on the daia switches. m this case.
0101. At thc same time. this signal sets the latch made up of gates 1 and 2. With
thc latch sct, the oucut of gate 2 is hi^i. Gate 3, thcreforc, is enablcd and pulses
pass ttarou^i gate 3 and gate 4 (which is connected as an invcitcr) and cause the
countcr to stcp. The counter counts down, stanmg at its preset numbcr 5. The
countcr contmues to stcp until the O condition is reached. At tfus time thc borrow
ouqput linc gocs low causing the latch to reset. As the latch rcsets. gate 3 is again
inhibitcd aiid tfae pulses no longer rcach the counter.
112J STUDENt WORKBOOK

DuriDg tfae time ftat flie counteris decianaiting, T-î?T> indicaior Ll mooitors thc
ptdses occuniag at dic output of invcrter 4. Sincc it takes fivc ptrises to dccre-
rncnt d>c countcrto 0, this LED mdicator wfll switdi ofl'and on iive times. Tlris
indicates thatfive outputpulses occurred. This concspcmds (o the Iwiary numbcr
ptcset aato Ae oountcr.
You again danonstrated flic opcration of flic dreuit by programming the oountcr
with the nnnber 1100 or 12. When thc B logic switch is actuaicd. thc circuit
gcnerates 12 ouçnit pulses bcfore it stops.
The xumber ofouqput pilses gencrated by this cucuit is Umited by the count ca-
paMity ofthe 74LS193 coinaer. te maximum coum is 1111 or 15. fa oider to
cxtend dus to laigcr values. additional 74LS193 coumers can bc cascadcd to ac-
ccamnodate the desired numbcr ofpulscs.
 DlgltalTechnlques J113

Experiment 15
Shift Registers
Objective
To demonstrafe the operation and characteristics cf bipolar wtegraied circiut
shyt registers.

Materials Required
Hcatfakit Digital Trainer

1 - 74LS04 TI1. hcx mvcrter IC (443-755)

2 - 74LS76 TTL dual JK fltp-flop IC (443-829)
1 - 7495 TTL four.bit shift registcr IC (443-680)

Procedure
1. Coiistruct the four bit shift ngistcr circuit shown m Rgurc E15-1. You
wûluse two 74LS76 dual JK flip-flops. Shift pulscs for thc circuit wiU be
deriived from togic swiich A. Logicswitch B is coxmcctcd to reset thc sliift
registcr via the asynduonous dear iiyuts <m tbc flip-flops. The scrial in-
put to thc shift rcgiacr wiU comc ftom data swuch SW1. Notc that onc of
the inveners in a 74LS04 IC is used to makc thc JK uqwts of thc fiBt
flip-flop complcmcntaiy. Thc sluft register outputs will be monitored on
thcLED uadicauns. Don't foiget to connect+5 volisand ground tp eadi
IC.

swn ". <»w u u «w u

?£s<M
>""""(
<
A
?«i5!s...415...4tJ2-15-
+"

JSîSS.. t?&.4..teJ

1^1. T
ni J O ^

Bfr
J O .^0

: T :2 Ji K_S ;1fl w K 5 K 0
K£B
-Tu-fy JC_ ~v -c_
4W -*- u (12- q. v
1s' ft' |f2
rlbîi
^-"

RESET

Figure E15-I
SIrift repstcr dcmonscaûoncircuit
114l STUDENT WORKBOOK

Apply powcr to fte circuiL Resct the shift registcr by actuaring thc B logic
switch. Set daia switdi SWI to the binaiy 1 posidoii. Then, using the A
logic switcfa. tpply 4 diift pdses. Observe the LED uidicators as you do.
Rcconi thc binary valt»of uss regisier contaits aftcr four shift pidses.

ABCDs

Ncxt. sct tbe SW1 switch to tBnaiy 0. Again aRriy four sbift pulses with
thc A lopc switch. Recoid the binaiy coments ofthe register.

ABCD^

3. Usaas thc SW1 data switch and tfie A logic swiudi, load tfac shift register
by usidg the stq> by step pnwedure givcn bclow.

SW1 a 1. dq»ressswitchA
SWï s= 0. dq»ressswitch A
SWI s 1, depress switA A
SWI s= 0. depress switdi A

After you havc loaded fl*c shift register, obscrvc thc LED indicatons aai in
die space bdow write the decinul cquivalent of the binary number ui the
shift nsgister.

Decimalnumbcrs

Discussîon
fa fliese steps you consttuctcd a four-Ut shift register with JK flip-flops. You
loaded data into thc shift register seriaUy using data switdh SW1 as your data
source. A siDgIe-bft of infonnation was entered into thc shift register with each
actuation of tfie A logic swftch. As the bits wcre entered into die A flip-fiop, thcy
wctc shified to the ri^it one-bit at a timc for cach shift pulse.
"nie 74LS04 invcner is uscd 10 conven tfie data fnwn SW1 uito two oomple-
mcntaiy rigiuls wduch are app]ied to the JK iicuts of the uqxrt (A) flip-flop. Thc
JK nçutsmust always bc çomplementary in a shîft rcgisteruang a JK flip-fkgï.
 Dlgltal Technlques J 115

In Stq> 2 you appUed a bmaiy 1 to the shift register ùçmt.Then, actuarinig thc A
lofiic switch four times, you gcneratcd finir shift pulses which loaded ftc shift
register with binsuy I's. As you generated thc shift pdses. you should havc
noted the cnuy ofthe finst buuuy 1-bit uuo tbc A flip-flop and with ttic second
shift pulsc.thc shifting ofthcdaia to thc right untU the register was fuU(1111).
Ncxt, you sct uic ncut tobmaiy O and thcsD loadcd fl>e refiisicr with bmaiy O's
wifhfoursluftpulscs (0000). Asflicbmaiy O's wercloaded, diebmary llnts m
thc ïe^sterwCTe shiftcd out

In Stq> 3 you loaded tfac binaiy number 0101 mto dic register a bit at a tunc by
sctting SW1 to the desired statc and flicn dqnpcsriag logic switch A to generate a
sbift pulsc. WhUe thc bit paacm in the shift register is casy to identily by simply
observaig thc T.FT) indicatORs, you cannot convett Uut bit pattcm inio its decimal
rounber equivatent unlcss you Imow ^rtudi Ut is theLSB. Since this infonnation
was not givcxi, your answcr coidd havc bccn cither 0101 a 5 or 1010 a 10.

In a tnnaiy counter thc lcast significant Irit is readily idcntificd sinoc it is dic
flip-flpp to wtuch tte iiyut or coum pirises are qïplicd. With uus mfimnatitm
you can always detcnninc die yaluc oftlic nannber in fl»c oountcr. Wîtti Ac duft
registcr, howcvcr, tfae u^ut flip-flop may npt neccssaiily be thc Icast agnificaat
bit Wc could tuso assiga thc ri^itmost or serial quciut fUp-flop as the least rig-
infîcant lat Tli& choice of wcifiîtt for thc input and ouçnrtflip-flops is np to the
designcr and will <tepcad upon thc qiplication. For a laigc pcrcentagc of applica-
tions. Ae icput flip-flop cotttains thc most sigmficant Ut wUlc thc oucut fiip-
ûopcontams thc teast rignificani bit In othcar wonls, dao is énterednuo tfae shift
tcgistcr bepinnng wifh flic Icast significant trit As data is slufkcd out of die drift
register thc lcast sigoificant bit is shifted out first. Unlcss otheiwisc stated. we
will usc fliat convemion heic. As ymi can see fintMn tiis demonstration aescabed
hcic, fltc diift regisier docs perfbna a serial to paraUd convcision. Daia is.cn·
tered seriaUy from fl» SW1 daia switch and then diqflayed m paraDd on ttie
LED indicators. Data can also bc cntered scriaHy with SW1 and read-out scriaBy
by siaqfly obscrving flic state ofL4.
118l STUDENTWORKBOOK

Procedure (cont.)
6. Modify yoar 7495 shift register circuit 10 confonn to Uie configuration
shown in ïîgurc EI5-3. Here you are oonnccting tbe paraUe! data mpifls
back around to ftc outputs in onler to pennit the shifi register to perfbraa
shift left operations. As before you wiU use dac A logic switdi to geacrate
shift pidses. Data swftdi SWI wfll bc used for a scrial data uyut fordiift
riffat ppetations. SW4 wffl be used as the data souree for shift lcft opera-
tions. Switch SW2 wm be uscd to conaol tfae modc of tfac circuit 'nie
mode control wffl sdect either shfcft right or shift left operations.

8BUM.INPUT
FWSHKT
moHT i

saiuu.iNPur
FORSHFrUEFT

FiguneElS-3
Shiftrigfat/dnftleft
circuitforStqxs 6,7,and 8.

Studyutg thc circuit in Rgure E15-3. detennine tiic bmaiy state of the
mode control uput to perfonn sluft lcft opcrations.
7. SetdataswttchesSWl,SW2,aDdSW4tothcbiDaiyOstate.Applypowcr
to d>e cucirit and depiess die A loigic swiicfa fourtuncs. Rccond ÛKsute of
fte I-ED iDdicatois.
ABCD
 Dlflttal Technlques J119

Ncxt. sct data switch SWl to thc binary I position. Dqpress tbc A logic
switch four limes. Note thc direcdon of shifiing as tfae shifi pidscs arc ap-
plied. Afterfourpulscs haw bccn qylicd, iccoid tbe state ofthc nsgister.
ABCD=

Sct SW1 to tmary O. Agam dqness thc A lopc switdi four timcs. Note
tiic direction in wfaidi the data shifts.

8. Set SW2 and SW4 to binary 1. Appiy four duft pulscs witfa thc A logic
switch. Again, DOte the directfon of shifting and rcconl the contcnts of flie
register.

ABCD=

Sct data swtch SW4 to tnnary O and apply two shift pulscs. Note the di-
recrion oftbc shifting and record the Ti!?n indicator staies.

ABCD:

Discussion
In tfacsc stcps you dcmonstratcd faow the 7495 IC shift regisicr can pcrfonn both
shift right and shift lcft operarioos. In Stcp 7 you shiftcd data to ttic right uang
SW1 as d»scrial wpat data sourec. fitst, you shiftcd in trinaiy O's lo ctear thc
repstcr thcn shifted in binaiy 1's. You thcn shiftcd out thc biaaiy 1's as binaiy
O's wcrc shifted m. Durixig dicsc shifdng opcrarions you should havc xioted that
d»cdata mavcd from Icft to right Tbc logic indicators wcrc wired to visually in*
dicate tfac direction of sMft. Dau moved fiom flip-flop A. 10 flip-ftop B.'to fiip-
flop C, to fl4>-flop D; or from logic indicator Ll. to L2. to L3, and funaUy lo L4.
AU Ûusoccuncd with flie modc connol m the binary O position.

When SW2 is placed in thc lunaiy 1 p(»ition. tbe rcgister win bc set up for shift
lcft opcrations. Thc 7495 IC is intetnally wired to perfonn shift ri^ht operatimis
auiomatically. By amply cnabling tbc modc control with a bmaxy O Uie sluft
right function is perfonncd. Howcvcr. thc shift lcfit opcratioa must be cxtcmany
wired if it is to occur. Thc shift left operarion is implcmcntcd by connecting tfae
appippriatc flip-floip outputs back to thc paraUel iicut liiies. Tbc paraBd uyut
Unes pcnnit the 7495 to bc cidicr preset ftom somc parancl souroc or camccted
for shift teft opeiafioos. Note m Rgmc E15-3 that flic D flip-flop outpui is con-
laected to thc C flip-flop inpiu. Thc C flip-flop oucut is oonncctcd to the B flip-
flop icpuL And finaBy. thc B flip-flop wiqwt is connected to tiic A flip-flop in-
put Tbe D flip-flop nceivcs its iaput Erom data switch SW4. This is tfac serial
iiçullinc for thc dufi xcgistcr whcn used for duft lcft opcrations. Now. as duft
pulscs arc applied, dao wiU move ftom SW4 to thc D flip-flop fhen to C. B, and
tbenA.
1201 STUDBn- WORKBOOK

You demooscated the sUft teft cffect by loading all lansuyl's into tfae register.
As you did you diould have "cco the UEDs Ujlit Énxnrijg^it to left in4îCTtin£a
left diift. You Aan qipUed two diift putoes witt»tbe SW4 switdi sct to trinary 0.
Tliis caused bioaiy O's to bc loaded into thc C and D flip-flpps. Tlac iMnary 1's
previously siored m those two fUp-ftops wcrcshiftcd totbc A and B flip-flops.
Thereftnc, ûicbiaary number stoxcd m thc register after thc two pulses wcre ap-
pliedwasllOO.
This completes your woA for Experiment 15. Do not disassembk your shift rei;-
istercucuftasitwiDbeuscdmflKmixtoqteriment
 Dl8(talTechnlques|121

Experiment 16
Shift Register Applications
Objective
To àemonstrcae several practicaî eypUcaÀons of wtegrated circuit shfft
regfsters.

Materials Required
HeaûfldtDigital Traincr
Wîred circuit fiom Êqwriment15 (Rgure E15-3)

1 - 74LS04 TIL hcx invcrtcr IC (443-755)

Procedure
1. Fbr this cxperiment you wffl use the 7495 diift icgistcr cucuit you con-
structcd in Eîqperiment 15. As you recall. the register was wucd for both
shift right anl sMft lcft opcradons. To pcrfom» tbc ncxt sicp you do INH
need to makc any fiuther modificarions to thc cucuit Thc circuit is re-
peated in Rgurc E16-1.
2. SetSW2tobinaiyl.SWlshouUbesctiobinaryO.SctSW4tobinaiyO
and apply powcr to die Tlaincr. Dq»ressAc A logic switdi 4 times. Tlie
registcr is set up for shift left opcrations and tfus stq) should dear the icg-
istertoO.

Ncxt, setSW4 to binaiy 1. Dq»ressthc A logic switeh two times. Record

ûie Unaiy numbcr stond m flic register. Assumc Aat the D flip-flop
(indatorl4)isthcLSB.
ABCDs
Dcciuial valuc

Now set SW4 to binaiy 0. Dqncss Ac A logic switch oncc and again note
Ac contents ofthe register. Rccoid it and its dccimal equivalcnt
ABCDa
Dccunal value i
1221 STUDENT WORKBOOK

Dçpress Ae A logic switch again. Record the binary and decimal ecpuva-
lcnt of thc register comcnts.
ABCD=
Decimal value =

SOUALINWT
TORSWFT
RtGHr
SW1-»

SBUALINPUT
POftSH»TLEFT

FigureElW
Shiftri^u/shiftlcft
circuitforSicps l tfarough5.

3. Study the data you obtained in Stcp 2 above. Dctcnmnc tte relarionsfaip
brtwcen thc numbers obtained wben thc regisicr was loadcd and as it was
shifted to the left. Wbat mathcmatical opcration was pcrfonned by thc
shift lcft pperation?

4. SetSW2andSW4tobinaiyO.'n»eSWlswitchshouldalsobeatOatthis
time. Ocar tfae rcgister by pressing thc A logic swiudi 4 timcs. Next, load
tfac registcr by foUowmg the stcp by siq) mstructions bdow.

SctSWl to 1, Dqncss thc Alogic switch

Sct SWI to 0, Dcpress the A logic switch
Sct SWI to 1, Depress tfac A logic switch
SctSWltoO
 Dlgltat Technlques j 123

Rcconl the binary contcnts of uus registcr and its dccimal value bdow.
Again use thc D flip-fiop fmdicator L4) as the LSB.
ABCD=
Dednial valuc s

Deprcss the A logic switch oncc. Rccord the binary value of the register
coatents and its decimal equivalent betow.
ABCDs
Dccimalvaluc=

5. Study tbc data Aat you obtauied by the shift right opcrarions you camed
out in Stq> 4. What mathcmatical operaaion is perfonned when a diift
n0st ppcratioD occuns? ______ ______

Discussion
to thcsc stcps you demonstratcd how a shift righVshift left circuit could be used
to pcrfonn muldplication and divisimi operations on binaiy nualbcis. In Stq»2
you toaded thc dcdmal inunbcrS into tbc shift registcr. Thcn you shiftcd it to tfac
Icft one acp. Eyaluatmg thc numbcrin tfie registcr you saw that it was 6. Shift-
uig thc number onc more lat position to dtc lcft produoed the binaiy number 12.
Y(wr condusim fiun ttis is that mth cach sluft lcft opcrarion tfae ruunber siored
in the registcr was multipUcd by 2. Here, you shified the number 3 two positioas
to flic left piodudng a total mulriplicatkm factor of22 »4.

Next, you set up thc shift re^ister for pioducuoga shift rigte opcrarion. You in-
itiaDy loaded the buuuy numbCT 1010 imo ttie registw. Of.cQtuse, this is the IM-
nary cquivatant ofthc dedmal number 10. You thcn appBcd a single shift pulse
and caused thc numbcr to bc strifted to thc right Evaluaring tfac ncw cumbcr you
found it to be 0101 or5. Here shifting a numberto thc ri^it causes diat number
to be dividcd by two for cach shift right The original numbcr iD tfte register is
dividcd by a number equal to 2N ^icrc N is tbc numbcr ofpositions dufted lo
thcright

A shift right/shift left, shift registcr is casy to use for scaling opcrarions. involv-
mg die mulriplication or division of a itumbcr by somc power of2.
124 I STUDENT WORKBOOK

Procedure (cont.)
6. Ncxt, you are goicig to demonstntc how u»edata in a shift register can be
redreulatcd by feedinig the scrial ouqwt badc to tbe serial UÇÏULThis pcr-
mits dic data to be shifted out tcrially for usc in somc cxtemal sourcc but
tfac data wm stffl be retaioed siocc it is recirculatcd.

Modify your 7495shifi register dnwit so that ft qïpearsas showa m Rg-

urc E16-2. Notc that the output fixMn thc D flip-flop is fcd ba(A to the sc-
rial iapat ofthc shift registcratjnn 1. You will usc tbe data switcfa SW1 as
die naodc coarol and SW4 wfll scrve as an additfonal serial inpaL Thc
topc coanol gatfng at thc iiyut to the A flip-flpp pennits cither of two
data sources to bc shifted uuo ttic register, tfaat ftDm pin 1 and that ftom
pn2.
7. Sct SWI to binaiy 1 and SW4 to bniajy 0. Depress tfae A logic switch four
times. Tlns should clearflie refiistcrand tbcLED indicaiors should be off.

Next, set SW4 to binsuy 1. Dqwss thc A logic switchtwo tuncs.In thc
spacc provided bdow. recoid flte binaiy numbcr stored in ÛKregistcr.

ABCDa
Next, set SWI to binaty 0. Tben dqncss thc A logic switda four times.
For cach duft pulse. note the position of the binaiy 1 bits on d»LED dis-
play. Recoid dw state of tfac xc;gister ctaitcnts aftcr four-shift pulscs havc
becn^iplied.

ABCDs

In Tabte I, nscord tfae statc of tfac staft icgister cwuents as indicatnl by Ac

I.BD indicators. Tben after cach dodk jxrisc. again record the four-bil reg-
ister stfSv, Ooinplctc uy taM? as in4i<*fltp4.
 Dlgltal Technlques J 125
SERIAL
oumrr

SW1

Figure EI6-2
Write/recirculateshiftrcgisttr
drcuit for Stcps 6 through 9.

8. Study thc infonnation you reicprded in TaUc I. From tbis infonnation dc-
tennme thc operatton of thc cireuiL Refcr back to Figure E16-2 if ncccs-
saiy to scc how the circuit operattts. Is thc data m the shift register lost or
retaincd as a result of $hiflting &e data? _.

TABLEI
A B c D
126 j STUDENT WORKBOOK

9. Set the SW1 mode control switch to binary I . Set SW4 to binary 0. Again
appïy four shift piilses with Ae A logic switch. Note the contenîs of thc
register after thc four shift pulses have becn appîied and record the rcgistcr
statebelow.

ABCD=

As a result oftte operation abovc, was data lost or retained?

Discussion
In thesc stq»syou demonstratcd tsow data can be rcdrculated in Ac shift register
in oidcr Aat the conteats be retauBcd cvcn whcn thc data must be shifted out
scriaBy to anoflicr source. This is done by connecring the oucut of die shift reg-
istcr fixnn the D flip-flop badc around to the serial input 10 the A flip-flop atpin
1. Wîth fl»modc caatrol set to thc binary O position, the shift registcrwill per-
fbnn a shift rigfat operation. As the shift ri^it operation is perfonncd, thc serial
data appcars a bit at a timc at tfac nonnal oucut of tfae D flip-flop. But at the
samc timc, this data is shiftcd back mtp thc shift register. It takcs four shift
pulses to cause a single four-bit binaiy woid to be shifted out Afccr four shift
pulses occur, thc data is also shiftcd badc mto thc registcrand is rcady to be used
agam.

When flie modc connol switch is set to binaiy 1. the serialdata input a»; pin 1 on
thc 7495 IC is disabledL In this case, the iqiut at pn 2 is recognized. This pcr-
mits an cxtcmal serial data source to fced data to the shift register. Jn flris casc
you used SW4 to provklc dflta to thc shift ffegister. With Ac modc control icput
at binary I, you can Joad a scrial woxd appeaxing at pn 2 imo thc registcr as tftift
pulscs are appiied.
An imponant poim to note is that with thc mode coiurol in tbc binaiy 1 statc thc
paraUd data iapws are cnalfle<L Tlie input to flip-flop A is used as the serial data
sourcc. But thc oAer mpats must be connccted to flip-flops A. B and C icspec-
tivdy in order for a shift n^u qxration to bc perfonned with the modc conaol
iigïutbigh.

In Siep 7, you sct the mode control to the binary 1 posiaon and the SW4 switdi
to bmary 0. This causcd data (0000) to bc loaded into the shift register ftom
SW4. Ncxt, you loaded two binaiy 1 's by setring SW4 to binaiy 1 and deiHCSs-
ing fltc A logic switcb twice. Tbis loaded the number 1100 mto the register.
 Dlgltal Technlques | 127

Ncxt, you set the mode Snirolinput to binary 0. This disatflcs the serial input
ftoSSW4 and causes the data to recuculate. As you apiflied four shift pulscs,
you should have obscrved thc data shifting right out of the D flip-flop mdthai
back around into the A mp-ftop. Aftcr four shatpulses.the data is shiftcd out of
thc registcr but it is also redrculatcd. Aftcr four shift pulses, the contents of the
registcr is stiU 1100. Your data in Table I shoidd appear as shown m Table IL

TABLEH
A B c D

1 1 o o
o 1 1 o RECYCLE
RJ

o o 1 1

I o o I
-^- DIRECnONOFSHIFT

Rxially, you set the mode control switch to binary 1. 'niis again cnables the serial
uyut fiom SW4. You thcn loadcd binary O's with four shifi pulscs. As you
loadcd these O's you noticed that the buiary number 1 100 was shiftcd out scriaBy
and lost as thc ncw numbcr 0000 was shiftcd in.

A slrift registcr, whcn connccted in flus way, fonns what is known as a load/
recu'culate register. The mode conaol iicut Une lcts you put in data ftom an cx-
tcmàl serial sourcc. In flie rcdrculatc modc it pcnnits dafca lo be shiftcd out and
used extemally but also icaiffculatcs it so diat it is retamcd for anouicr opcratiion.

Procedure (cont.)
10. Usmg the redreulate registcr shown in Rgurc E16-2. clcar thc registcr by
loading aU O's. If the register is already at O titen this opcration is not
nccessary. To clear the tegister. sct SW1 to binary 1 and SW4 to binary 0.
Thcn depress fte A logic switch 4 timcs.

11. Ncxt. sct SW4 to binary 1. Deprcss the A logic switch oncc. Sct ttie mode
conuol switdi SW1 to bmaiy 0. Thcn bcgin depressing thc A logic swiudL
Notc thc resulL Coiuinue dcprcssing the A logic switch a number of nmcs
untfl you arc fully aware of what the circuit is doing.
128l STUDENT WORKBOOK

Discussîon
to thesc steps you demonstrated thc operarion of Ae diift rcgistcr as a ring
countcr. You deared thc repster and loadcd a binaiy 1 imo the A flip-flop. You
thSsct tibc mode connol so that flte shift register would recirculate. Tbcn by
depfessSsy tiae A logic swiich you were aUe to cause the bmary 1-bit to move
finom onc flip-fiop position to Ac next and Aen redrculatc. Whcn used in tlris
nunner, tbe shift registcr is known as a hng countcr. TIris ring countermakcs an
cxoeUcnt sequcacing drcuit for driving digital circuits diat rcquire a timc se-
quenocofpulses.

Procedure (cont.)
12. ModîlytheshiftregisterdrcuitsothatitconfonnstothatshownmFigure
E16-3. Thc paraBeI data iapats wffl not bc used in this step. The mode
conool input Uas is amply conncctcd to ground. Tbc oucut ftom thc D
flip-flop is connected throu^i onc of flie invertCTS in a 74LS04 IC and thcn
fed back around to flie input ofthe shift registcr.

W:7M3M
2S -.^1 ;1

*w

Figure E16.3
SIuft regiaer circuit for Steps 12 throu^i 15.
 Dlgltal Technlques 1129

13. Study thc circuit m Figurc EI6-3 and answcr the following questioiis.

Tbc circuit is sci up to perfonn a shift (rigto, ïeSt),

opcration.

The shift register circuit conaected m this way is taipwn as a

counter.

14. Aspp\y powcr to the circuit Depnsssthe A shift uyutswitch uma fhesiaft
icgistcr contains àUO's. Record this state ui tbe first position ofTableDI.
Next.depncss tbc A logic switdhi and after cach actuatipniccoid the shift
register state in tfae scquemial locarions in TaUc III. Coatinue dqpresaag
thc A logic switch one at a time aaul recoixiing thc rcgistcr states imtïï
TaUc m is complete.

TABLEm
A B c D

15. DiscoimccttheshiftdockinputImesatpins8and9onthe7495ICftDm
tbe A logic switch outpat and conncct thcm to Uw (dock (OLK) output Set
thc dock ficqucncy to I Hz. Apply power to the circuit and obscrvc the
shift register ouçutstatcs. As soon as aU the LED indicaiors show <t»creg-
istcr coiucnt to bc 0000, monitor thc shift regisasr states aftcr cach dock
pulse aiȉverify thcm against the data you coUcctcd and recoricd in Table
m. Conrinue lo lct the shift regisicr circuit operaic wtute obscrving Tablc
m. Be suie that you let the circuit nm long cnou^i so that you understand
tbe operation that is taking placc.
1301 STUDENTWORKBOOK

Discussion
The cuarit you coaasttucted in Step 12 is a Johnson comuer. Sinoe uic mode con-
m»lagïut is set to bînary O by grouxufing it. die circuit will perfonn a shift rigitt
opexatixm. Tbe cireuit connecrian feeds thc nonnal ouçut of ÛKD flip-flop
tiuoufii»«ainvener md «pfaiesthc comidemem back around to tbe scrial iBput
ofthe drift register. Tlris is the cquivalent of comiecting Uie nonnal and comjde-
mcot ouspat oftbc shift r^ster oulput flip-flop. badc arouad to thc K and Jio-
puis of thc ncwt flip-flop on ashift re^ister as indicatcd previously in the unit
When wc do flris wc fbnn a switth taaorJohnson counter. Since tfae nonnal and
oomidemeat flip-flpp ouçxrtsof ûieJK nçnnsan; npt avaaaMe, flie ansingcmau
in Rgure E16-3 acopmplishes thc same cfifcct. EsseaMaaIly wc iovcrt tiie wxtpua of
the sMft regisicr and feed it badc to the serial inpufc Tlac result is a four-bit
Johason coantcr. Such a ooamerhas 2 " N discrete states wiicn N is flic number
offl^>-flops. Stocc we are using four flip-flops flus cireuit should have 8 discrete
statcs. You verificd this by stq3(riag Ae coimter aad reconiing thc flip-flop states
in TaUc m. You then verified this ppcration by Icuing tbc counter operate
aatomaricaUy fmm tfac 1 Hz ctock pulse. You should havc found thc shifi îeps-
ter states to be like diosc indicated m TaUc W.

TABUEIV
A B c D

o o o o
1 o o o
1 1 o o
1 1 1 o R]
I 1 1 1

o 1 1 1

o o 1 1

o o o 1
 Dlgltal Technlques 1131

Experiment 17
CIocks and One-Shots
Objective
To àemonstrate the operation tifseveral clock oscillator circuits and a retrig-
gerable one-shot multivibrator.

Materials Required
HeatUkitDigitalTramer

2 - MPSA20 transistois (417-801)

2-lkQresistors
2-4.7kQresistors
l-471ûQnssistor
2 -1000 pF dectrolytic capadtors
1 - 74LS04 TII-hcx invcncr IC (443-755)
1-74LS123 TTL tetrifigeraUe onc-shot (monostablc midrivibrator) IC
(443-942)

Procedure
1. Construa thc astaUc multivibrator circutt showi in Rgure E17-1. Take
yourtimc in wiring flie dreuit to bc sure that you do not makc any wiring
mistakes. You wffl obseivc thc opcration ofthis circuit on LED mdicators
LlandLl

*w

NW>2>.
(417^01)

FigureEH-l
AstaUe mulrivibrator oipcrimcmal drcuiL
132l STUDENT WORKBOOK

Using thc conippnRiTt v^w<c indicatcd in Rgure E17-1, computc tfae fic-
qucacy of osdllation of ûâsastabte mulrivibrator cireuit Rccord your an-
swcrbdow.

F» Hz

Ncxt, annputc tfae period ofosdUation for dris circuit.

Pcriod» accoads

Tbc duty cyde of tUs cucuit wifl be ,_.

Appïypowerioûiccuaritand obscrveLED indicatorsLl and L2. Use dic

second hand on your watch to measure dic pcriod of osdllatioa. Rccortl
yourmeasured value bdow and cmnpare to ute computed value youdctcr-
minedcariier.

Pcriod) scconds

Does thc actual opcration of flie dreuit concspond to Ae axiswcis you

gaw in Stqp 2 above? Account for any discnyancy that you migtit
observc.

4. Oonsnuct Ihe dodc osdBator droirit shown in Rgure E17-2. You wOl use
a 74LS04 TTL hex invener. Bc sure to comiect +5 wlts and grouxid to Ac
integrated circirit. You wm observc ttic circuit output on LED udicator
L4.

5. ^ïply powcr to tfae dicuiL Mcasure thc pcriod of osdUation uang the
Bccood hand on your waid» and recoid betow. To do this accuBatdy, it
nuy bc necessary to measure ten periods then dividc youT result by tcn.

Period' seconds
3.74LS04

[>
^-qp-
2
1000*!'F
u 14

ïo66(i.F
-4^
>10000 " 10000

Fifiure E17-2
IC dock osdUaior circuit
 DlflItaITechnlques 1133

DJscussion
In tfaesc siqas yai danousttated two çpesof dodc oscfflatore. Tïe discntc com-
paaent dock in Rpnc E17-1 is a sttadard astaUe multivibratOT. Thc drcirit
shouM switdi nspcatodly bctwcen ics two states as indicaed by LED indicatois
Ll and L2. Wbcn Ll is on L2 wfll bc ofiF and vicc-vCTBa.

Uring tte fonmda gwcn cadicr in tte unit.tfae ftequcacy of oscillation should be
about .154 Has. TOs nicans that tfac dreuit should have a pcriod (tune for oac
<yde) of ^ppnoximatdy l "*" .154 or about 6.6 seconds. Tîus means dut die cir-
cuit dioukl dunge aate cveiy 6.6 secaids. Each LED iodicator wiU remain on
ft»rapproxuuatdly 3J25 «econds.TUs vay tow fiequency of osdUatioo is caused
prinuufly by the veiy higb valuc of cigwdtffw used in dic cuaut ffi^ier fic-
queadcs can be obtamed by uang SDaaUer capadtorvalues.
Your measuicd pcriod nuy be soaewhat diflfocnt from your calnilatnl value.
The fonnula pvcn fw computing ttw ficquency is "n q»proximation to b^in
wiffi, but Ac most likdy cauc for tte diffCTencc between your computcd and
aeasund vahies is fl»e tolcrances of flie tifping nsiston md capacitors. Since
botb nçwcitore aic die saxne laid die base resistors are equal, dae duty cydc of
fliccucuitdiouldbc50penxnt.,

In Stqps 4 and 5 you demonsttated a dock wcillator dtxaut made from TIL m-
vertcns. As ixidicated eadierinifac unit. thc pcriod ofosciUation ofthe circuit is
qqnoxunately 2RC. Usinig die componcnt values shown m Figurc EI7-2, dic pe-
riod of osdEUatioa »hmW be spptojamatsly 2 scoonds. This rqncscas a fic-
queaçy ofJ5Hz.In other woids, the TJKT* indicator L4 should flash on and off
ODCC cveiy 2 seconds.
1341 STUDENT WORKBOOK

Procedure (cont.)
6. DisassemUe the dodc osciUator cucuits you ctmsttuctcd m tfae prevknis
steps. On tiae tecadboaiding sodcet of your 'ITaiaer, consmict tbc circiut
diown in Rgure E17-3. This circait uses ûie74LS123 dual ictriEgcraUe
OBie-shot. The circuit is wired so that the fint (ae-shot wiU be triggcred
frnn the A togic switcfa. TIris Sie.shotwill in tum triggcrthc sccond one-
thot an flie IC. Esaemal nsistors and cicadtois are uscd to set flie duratitm
of Ae pulses produccd ly each (ne-shot You wffl mroutor d»c one-diot
wttpats oa LED indicaiors LI aad L4. Notc fliat Ae logicswiich oucnt,
5. is coimected to thc reset (Ç)iBput of the fiist one-diot Don't fotgtt to
canncct +5 volts tOjMn 16and pound topin Soffbe IC.

+SV *5V

1000 uF
:4.7k0

74LS123 n
^
o

A-». ^d C 0
12

4(10
<5V <SV

FigunE17-3
Onc-shot ciqicnmcntal circuit

Tbe pin ctnmections for ihc 74LS123 IC ans shown m Fîgurc E17-4. The pulsc
duration produccd by this ouc-shot is a ftmction of thc cxtcmal componeot val-
ues R and C and can be computed witfa thc fbnnula bdow.

t=0.33RC

In ûasfbnnula fee resistance value R is in kJCi and tbc capadtancc valuc C is in

pF. Thc cyucutpulsc duration t wffl bc m mUIiscconds.
 Dlgltal Technlques | 135

1
^ i S o "g I s ^
JiiUîSUiîUîal-JïSUî'iUiol-R-i

t-îlî-@-Q-ïU-©-B-ll!~liJ~~J
?"-j|°-8jj'
-..8 ï
FigureEl?^
Pincomicctionsfor
74LS123 dual retriggçrablcone-shot

Using thc formula, compute thc pulsc duradon of pach onc shot m Figurc
EI7-3. Rccoid your putec durations bdow. Thc output pulse widthofthc
first one-shot is l, and thc oucut of thc second one-shot is t^.

^- ms
»2! ms

8. Study the drcuit shown in Rgure E17-3. Detcnninc the operatipn of Ae

circuiL Assumc that thc cucuit opcration is uiioated by actuadng the A
logic switch. Skctch the icput and oucut wavcfonns for the circuiL

Wffl fte rircuit bc triggcred when thc A logic switch is dqnessed or

idcased? _ _ _ .

9. Depress tfac A logic swtch and relcasc it Notc ihe LED indiqatoB to $ec
wfaat operation occurs. Usc flie second hand of your watch 0 time thc one
shot ouçniïdiuations by obscrving Ll and L4. Rcpeat the sequeiicc as of-
tcn as ncccssaiy to vcrify tfae operarion of the circuiL

Docs the actual operation of the circuit corrcspond to your rcsult in Stq>
8?

10. Momcntarily dcpress and rclcasc the A logic switch. Note LED indicator
Ll. Aftcr a sccond or two. depress the B logic switch while noting Ll and
L4.Whathappcas?
136 I STUDENTWORKBOOK

11. RcmovctheinputfiromlogicswitchAtopm2oftheICandcoiuttCtpin2
to thc clock output CLK. Set the clodc fiequency to 1 Hz and obscrvc the
Ll mdicator.

What is the statc ofLl? .

What does ûasstatc indicate?

Discussion
fa thesc stçps you demonsttatcd the opcrari<m of a retriggcrable Sie-shot.The
retriggeralfle fùncrionis not always used, and when it isn't, diis circuit pcrfonaas
Iflcc any other monostable multivitnator. The circuit you consnucted receivcs a
triggcr pulse fiom the A logic switch. Tbc A ovttpat nonnaUy rests in d»low
position. When thc swildi is depicssed, A goes hi^i and wheo it is relcased goes
low agaai. It is on d»clow to Irigfa transition that thc iapat onc-riiot is triggcred.
Whcn it is triggcred, LED indicator Ll wiU nun on. Tlus output wffl xcmain on
untfl thc pulsc duration spcdfied by dic cxtemal resistor and capacitor is com-
plcted. Accojding to tfac calculations uring fl»c formula givcn eariier, thc pulsc
ouçutdiuarion for this one-shot (t,) shouU bc 153 seconds.

Wben ûicinput onc-shot times out, fts output wiB swhch fiom hi^i to low. This
wUl triggcrthe sccond one-îtoot in the circiriL Its time constant is set 10 producc
an output pulsc (^) of 1^5 seconds. Therefore, as soon as Ll tums off, L4
should nun on for approximatdy U5 scconds aad then go OUL This scqucnce
can bc repeated by dqpressing thc A lofiic switdi again.

Thc B logic switdi is winsd to die dear input of Ae first one-diot IF you triggcr
the drcuit toto ppcration wife thc A logic switdi, tfac first onc-shot wfll remain
rai for about 15^ seconds. Howevcr, this tuning interval can bc teraunatod or cut
shon by applying a reset pulse widi logic switch B. Thc mmnem the B logic
switch is dcpressed. the one-shot oucut will switch off. LED Ll wiU go OUL
This wfll immediatcly triggcr the sccond one-sbot and causc L4 to ligbt for ap-
pro3uinatdy 1^5 scconds. Both operations oould bc tcnninated by conMCtuag
the B logic switch oucut to Ae dear mpat offhe sccond ow-shot as wcU.
 DlgltaITechnlques 1137

The one-shot circuit that you demonstratcd herc shows how a dclay fimction is
implemcntcd. Tbe first one-shot produces a dday of ovcr 15 scconds and the
sccOTid oiie-shot gencrates a single ouq»ut pulse lj5 seconds loag. The A logic
switch initiates die circuit operarion. but it is the ouqnit of the secoiid one-shot
that is gcncrally uscd to actuatc an cxtemal circuit Sce Figurc E17-5.

IjOGIC LOG1C
SWITCHA SWTTCHA
DEPRESSEO RELEASS)
n*UTB

X(L1)

Y(l4)
1—I1-S5S.
(L40N)

Figure E17-5
Wavefonns fllustrating the operarion
ofthe cxpcrimcntal one-shot drcuit.

Rnally, you coiinectcd the uput to thc drcuit to thc 1 Hz ouq)ut of your ctock.
Sinoc the dock: intuval is approumatcly one sccond, thc input onc-shot will be
repcatedly triggered. This wfll cause thc output of thc one-sbot to tum on. Bcfore
thc drcuit can rirnc oui, thc ispw. wiB be triggcred again. Therefore, thc oucut
ofthc fiist onc-shot will remaui on as long as the dod rignal is app&ed. When
thc pulsc duration of fce onc-shot is greatcr than the pcriod of thc ïnpat triggCT-
ing agaal, tte retriggcraUc fcaturc comes into operatiai and wiU kccp LED in-
dicatorLl tumcd on. T.ER indicatorL4 wOl rcmain offduring dus timc sincc thc
secmid one-shot will not be oiggcred.
1381 STUDENT WORKBOOK
 DlgltalTechnlqucs 1139

Experiment 18
Decoders
Objective
To demonstrase the operation ofa decoder.

Materials Required
Hcaflddt Digital Trainer

1 - 74LSOO TFL quad two-jicutNAND gate IC (443-728)

1 - 74LS04 TCL hcx invcrtcr IC (443-755)
1 - 74LS20 TTL dual four-input NAND gatc IC (443.798)
1 - 74LS42 TIL BCD-to^ecimal decoder IC (443.807)

Procedure
1. Consttuct fte decodcr cucuit shown in Rgurc E18-1. Tlic data switdies
SW1-SW4 wm providc ftc wput. LED indicator 1^4 is thc OUCUL Bc sure
to coamect +5 volts to pin 14 and ground to pin 7 ofthc two ICs.

SW1 ^.K.-J.iiSS0....... .Î<B;.?41S94.

SW2

""""'p-~p-'
SW3 '-'
+5V

sw*

FigureElM
Dccoder circuit for Sttps 1 and 2.
1401 STUDENT WORKBOOK

Apply thc 16 statts 0000 throu^i 1111 to thc curcuit and observc thc out-
put Record the binaiy icput statc wbere L4 ligius. ^ .

Assumc SW4 is flie LSB. The decimal equivaknt is: ^ .

3. Constroct tfac drcuit shown in Rgure EI8-2. Takc your timc in consouct-
ing diis drcirit to avoid wiring enons. Thc drcirit iicut wiU coae fiom
SW3 and SW4 (LSB). You wffl observc flic ouiputs on LED uidicatois Ll
titiroughL4.

What type of cucuit is tfris? _

w.:j.^sss,
>j^

SW3-^-i 11
^>o-N
"~n7
L4
13;
SW4-<-
^c^ "1U--J7-
^M-'ïSSSi'
4SV ~-~ +5V "='

FigureE18-2

4. WithSW3andSW4,applytheuqïUtsindicatcdinTableLRecordihecor-
rcqxnding oaxpat states ofLl, L2. L3, and L4 forcach ofnyut states.

TABLEI
INPUTS OUIPUTS (STCP4) OUTPUTS(STCP6)

SW3] SW4 LI L2 L3 L4 Ll L2 L3 L4

o o
o 1

1 o
1 1
 DlgltalTechnlques 1141

Which of the fbllowing cmditims did you obscrvc for cach set of iqputs?

a. AUouçwtsIow.
b. AU ouiputs hi^L
c. Oaeouçutlow.
d. Two ougxtts hi^
e. Two outpins low.
f. Oneouçuthi£?L

5. Removc ÛKconncctions betwccn tiic outpits of invcitcrs 1,2, 3, and 4

and Ll, L2. L3, and L4. Coimect Ll. L2, L3. and U to thc ouqnts ofthc
74U900 ÎC gates, pins 3, 6,8, and 11 respectivcly.

6. RcpeatStep4.^>plytheng)utsmTablcIaDdrecorithcouçmtstatesin
the appropriatc placcs.

Which of thc foUowing output conditioiis did you obscrvc for cach set of
uçmts?

a. AU ouqwts kw. "

b. AU ouçutshi^L
c. Oncoutputhifib.
d. Oneouçwtlow.
c. Two ouçnnstow.

7. Comp{ucyourresultsftomStqis4and6byobscrvingd»cdatainTaUcI.
Thcn removc the Gircirit fiom thc bicadboanling bkxA.
142l STUDENTWORKBOOK

8. Moum a 74LS42 IC on thc breadboarding btock. Comiect pin 16 to +5

volts and pm 8 to ground. Conncct the inputs to switches SW1 - SW4. Re-
fcr to Rgurc El 8-3 aiid El 8-4 for IC pin conncctions. You will monitor
tfae ovxpttts, onc at a timc with LED indicator L4.

74LS42
1
I! 2.
SW1 ^ o 3.
4_
_!S
SW2 l^
s 5
wures 5 ourpurs
SW3 14
i L *^.
î_
sw* ^—2Sk o
1
16.

+5V
n'
FigureElS-3
Experimcmal circuit
for stqps 8 and 9.

MPUTS ovrpins
YCC A B CD9 6 7
r-pBi-ra-ra-FsuîsyîïUioiJîi-,
ULnt^ 'B
CD

l-iii~w~u]~i±TW~i£nin£TJ
^01 2 3 45 C^ GND
oinpurs
FigureE18-4
Pin conncctions for 74LS42
TFL BO-to-dccixnaI decoder IC
 DlgltalTechnlques J143

9. Apply the mputs givcn in TaUc D. The LSB (A) is SW4. Observc thc 10
outputs. oiie at a timc, with L4 by connectmg it sequentially to pins 1,2.
3,4,5,6,7,9.10, and 11. Rccord your outputs in Tablc IL

a. 'Ilic 74LS42 is a BCD-to-dccimd dccodcr. What does Uiis mean m

tenns ofthc outputs you obscrved?

b. The 74LS42 does not recogmzc the six states 1010 tinough 1111.
a. Tme
b. Falsc

TABLEII
INPUTS OUIPUTS

D c B A o 1 2 3 4 5 6 7 8 9

o o o o
o o o I

o o 1 o
o o 1 1

o 1 o o
o I o 1

o 1 1 o
o 1 1 I

1 1 o o o
I o o 1

I o 1 o
I o 1 1

I I o o
1 1 o 1

1 I 1 o
1 I 1 1
144l STUDENTWORKBOOK

Dîscussion
In Stqïs 1 and 2, you «mstructcd and tested a simple decoder for a 4-bit input
wori. Tbe 74LS20 four-input NAND gate is convcned uuo an AND gate by in-
'mpats
vener 3 at its ouçrot. The are connected so that the staie 1100 (decimal
12) is dccoded. Whcn SW1 1, SW2 s 1. SW3 = 0. and SW4 = 0, the output
s
wffl go hi^i. For àUother iqnit codes ftc ouçïutwUl bc low.

In Stcp 3, you coiisaucted a one-of-four dccodcr circuit The 2-bit input codc
comcs from SW3 and SW4. You obscrved the four possible ouqwts on the LED
indicatoxs.

fa Stq»4. you should have found that for any set of input states, only one ouqmt
is high. AD othcis are low. This provcs thc onc-of-four theory. Your data m
Tablc I should indicatc the following:

00,L4on
Ol.LSon
lO.Uon
1 1. Ll on

Next, you runovcd thc invencrs ftom tbc outputs of thc NAND gates. Bidicaiors
L1-L4 momtor the NAND outputs direcfly with tlus modification. You should
havc found that onc oucut was low and the other threc high for any iaput states.
Thc deoodcr is sriD a onc-of.four drcuit, but the sdcctcd ouqiut is low instcad of
hi^L Thc data in Table I should iitdicate:

OO.Uofif
Ol.LSojff
10.L2ofF
ll.LIoff

In comparing the one-of-four dccodcr widï and wifhout thc output inveneis. thc
ouçut data of one should be thc complcment of the oAeras you would suspect
Boîh types of dccodcns are uscd dq»endingupon tfae q»plicarioti. Whcn thc cmc-
of-four output is higîi flic decodcr is said to have an actfve high ouciut. An activc
low ovstpat indicates tfaat the seleaed (dccoded) one-of-four is low.

In Steps 8 and 9, you evaluated the qxration of thc 74LS42 BCD-to^lccimal

decoder. As you should havc discovered. this circuit hasacrivc low ouqxits smce
NAND gates are used for the decoding. In TaUe II. your data should show thai
the sdected ouçnit gocs low. AU OUICTS remain high. This drcuit ignores thc
1010 ûirough 1111 statcssince it is an 8421 BCD (l-of-10) dccoder. Tliese six
states arc Olegal. This is indicalcd by the fact that whai one of the six states is
spplicd to Ûieinputs, none of tfae ouqniis go low.
 DlgltalTechnlques | 145

Experiment 19
7-SegmentDecoder-Driver
andDisplay
Objective
To demonstrate the opereuion cfan integrated circuit 7-segment decoder-driver
and a 7-segmemLED decimal display.

Materials Required
HeathUt Digital Traincr

I - 74LS90 TTL decade countcr IC (443-813)

1 - 74LS193 TTL synchronous up/down bmaiy counter IC (443-815)
1 - 9368 or 14495-1 decoder-drivcr IC (443-813 or 443-1802)
1 - 7-segment LED display
146l STUDENT WORKBOOK

Procedure

1. Consouct the drcuit shown in Figurc E19-1. This circuit consists of a

74LS90 BCD countcr, a 9368 BCD-to-7-segment decoder driver (or a
14495-1 as shown m thc inset drawing) and a 7-segment LED display. The
four BCD outputs ofthe 74LS90 counter drive LED indicators Ll through
L4 and the decoder-driver. The output ofthe decoder-driver is used to drive
fhe 7-segmcnt display. The pin conncctions to uie decoder-driver and the
7-segment I.ED display are givcn in Figurc E19-2. As before, use carc m
wiring the circuit to prevent wiring crrors. Don't foiget to connect +5 volts
and ground to each IC. 'Ilie decoder driver IC is a 7-segment decoder-driver.
It acccpts the four-bit latch register which can be used to stpre the four-
bit input The output ofthis larch is fed to the decoder circuit that converts
the BCD input iiuo thc 7-segment output code described earlier. Drivcr
transistors in the IC provide the currcnt necessary to operate the 7-segments
of the display. The four-bit latch is loaded or enabled by the EL input pm.

7-SECMENT
OISPLAV

10

^ 12 11 10 15 »4
"b c d » 16
a_A *5V
DECOOEfVDfllVER
SWI' B3W
A B C O ^

^-u
-^-l.3
-»-u
«»-u
12

BCOCOUNTER
14 74LS80

ï-f
<sv

Figure E19-1
Experimenial circuit fc
Steps l through 4.
 DlgltalTechnlques 1147

DECODER-DRJVER

"B
LJ-llMâJ--llMlK£MlI-tI}
CELRgoRBtO AGNO

r-4^AA4U5l-A-T^-4J}--i

DECODER-DRIVER
Fîgure E19-2
14495-1 (A) Pin connectioas for 9368 and 14495-1
decoder-drivcr ICs. CB) Pin connections
for type FND500 7-segment LED display.

2. Apply power to the drcuit Set data swiich SWI to binaiy .0. Step the BCD
counttr with fhe A logic switoh. As you do, notc the binaiy LED displays
Ll OMSB) through L4 CLSB) and the 7-scgmcDl display. Check to scc that
the binary tiumbcr shown is cquivalcnt to the decunal numbcr indicaicd.
Stcp the countcr through its ten states sevcral tuncs to sce that the circuit
is pcrfonning properiy.

3. Rcmcwe the lcad connecting pm 14 of the 74LS90 couiuer to the A logic

switch and connect it to the CLK output Set tfae clock frcquency to 1 Hz.
The dock will now automatically step the courucr and pennit you to observe
both ûieBCD and decimal outputs of the circuit auiomatically. "

4. Whcn the decunal display reads 7. quiddy set SW1 to the binaiy 1 posirion.
Continue to observe I.ED indicatois Ll through LA and the 7-segmcnt
display and note your rcsulL
1481 STUDENT WORKBOOK

5. Modify your experimental drcuits so that it appears as shown in Figure

£19-3.Rcmove the 74LS90 IC and in its place instaU the 74LS193 binaiy
coiutcr. You wm contmue to use the 1 Hz clock to step the counter. Data
switch SW2 wiB be used to reset the Suntcr.

OECOOEFMÏRIVER
SWt 144BS-1
A B C D

SW2

Fîgure E19-3
Experimental circuit for Stcps 5 aiid 6.

6. Sct data switch SW2 to the binary O posidon. Chcck to see that SW1 is
in the binary O porition. As before. the countcr should change states at a
1 Hz rate as indicated by the UED indicators Ll ûirough L4 and the 7-
scgment display. Whfle you arc obscrving thc LED diq>lays, note thc status
of the 7-segmcnt readout during thc 6 invalid codcs for BCD opcrarion.
 Dlgltal Tcchnlques | 149

Does tfae decoder-drivcr rccognize the six 4-bit binary codes nonnally
considered to be invalid m the BCD coding system?

îf your axiswcr to thc question above is yes, recoid the characters dis-
played by the 7-segmcnt readout during these six invalid states.
1010
1011
1100
1101
1110
1111

Discussion
In this cxperimcm you demonstrated the operation of a decoder-driver circuit that
acccpts a binary or BCD input codc and gcncrates the 7-scgment display signals
to produce the numbers O through 9 and other characters. In Stcps 1 through 5
you used a 74LS90 BCD counter to drive the decoder-drivcr and display. This
cucuit coimts in thc standaid 8421 BCD code. As you stepped the counter with
the A logic switch, you should have generatcd the four-bit BCD codcs as displayed
by LED indîcators Ll throu^i L4. At the same timc, the conrcspondiog decimal
digit should have bcen displayed on the 7-scgmcnt rcadout Using the 1 Hz dock
signal to nm the circuit peimitted you to observe the outputs whUe the circuit
steppcd autoniaticaUy.
In Stq> 4 you uscd data switch SW1 to sct theEL uiput to the bmaiy 1 state when
the decimal owpat was 7. You should havc found that thc 7-segmexit display
continued to indicate 7 whilc the dlodk continued to step the counicr and display
the scqucruial BCD statcs on LED mdicators Ll through L4. What you did when
you set SW1 to the binary 1 position was to store the number 0111 m thc latch
storage regisier of thc dccoder-drivcr. Thc 7-scgmcnt rcadout àispïays only the
bixiary or BCD number stored in that intemal register. By seamg the EL line high
you effectivdy inhibitcd fhe BCD mputs from the binary counter from funher
affecring the decodcr-drivcr. Of course the BCD countcr condnucd to sequcncc
through its nonnal states as indicatcd by the changing conditions on LI fhrough
L4. During tfaepreviouspanofthe cxperimcnt, you set SW1 tobmaiy O condition.
This eiiaUes the latchcs or D flip-flops in the storage rcgister and penaitted the
7-segment ouçuts to follow the BCD input
150 I STUDENTWORKBOOK

Rgure E19-4 shows a simpUfied block diagram ofthe 7-segmcnt decodcr-drivcr/

latch. The 4-bit inputs are applicd to the data inputs of latches that arc enablcd
by the ÊLline. The outputs of these four flip-flops arc fed through a decoder.
Thc decoder outpuis then drive a circuit that generates tbe 7-segment code
neccssary to display the digits O through 9 and lettcrs A through F. The output
devices are current drivm transistors that supply the proper currcnt to the
segmcnts in thc drivcr.

LATCH

*^0-^
.<8-{»—^
*WT
lATCH

c@-0°^

E^4>
Fîgure E19-4
Block diagram of (A) 9368 and (B) 14495-1
7-scgment decodcr driver ICs.

Rinally, you reidaced thc BCD coiuucr with a standaxd 4-bit binary coantcr. In
Stcp 6, you should have found that tbc decoder-driver does rccognizc the six
states nonnaUy considered to be invalid in the BCD codc. In these six statcs,
the decodcr-driver causcs the lettcrs A, B, C. I . E, and Fto be displayed on
the 7-segment display.
 DlgltalTechnlques | 151

Experiment 20
Multiplexers
Objective
To denwnstrate the operation cmd epplication ofdigiïal multiplexers.

Materials Required
Heathkit Digital Traincr

1 - 74LSOO TTL quad two-input NAND gatc IC (443-728)

1 - 74LS151 TTL data sdcctor/multiplcxcrIC (443-878)
1 - 74LS193 TTL synchronous up/down binary counter IC (443-815)

Procedure
1. Construct thc drcuit shown in Hgure E20-1. Use a 74LSOO IC. and bc
sure to connect +5 volts and ground to pins 14 and 7 respectively.

Study the circuit in Figurc E20-1 and answer the questions belpw.

a. What type of circuk is this?

b. Thc two signal sourccs are and
c. Tlic control input is

+5V
74LSOO J,,
14
CLK(IHt)
?
JO
SW1
112,
7^)ô4-^-"
113

>
SW4 'z"
Figure E20.1
Multiplexer circuit for Steps 1 and 2.
1521 STUDENT WORKBOOK

Apply power to the circuit Sct SW1 to the binary 1 position and nrte the
drcuit ouçnit on T.RD indicator Ll. Note the effcct of switdung SW4 off
thcnon.

The output is _ .

Set SWI to the binary O posirion. Note the cffect of svritchdng SW4 off
andon.

Thc output is _

Discussion
In siep I. you constructed a 2-ïapat mulriplcxcr or data sdcctor circuit. You
cvaluated thc operarion of dus circuilin step 2. The two input signal sources are
tfae l Hz dock signal (CLK) and thc signal fiom SW4. Data switch SW1 is used
as tfac conirol ucniL

Refer to Fîgure E20-1. Whaicvcr the SW1 switch is in the buaary 1 poation.
gate 3 wffl be enabted. The 1 Hz CLK sigaal wffl pass through to theoutput and
wiU causc LED mdicaior Ll to switdh offand on aia 1 Hz rate. At this time,
gate l (which is connccted as an invcner) inhibits gatc 2, thcreby prevcnring
SW4 fiom influcncing the oucut of thc drcuiL

When SW1 is placcd in thc binaxy O position, gatc 3 is mhibitcd. This causes tfic
output of nivener 1 to bc higfa, thereby cnaUing gate 2. At tliis time. the statc of
SW4 wffl be tRaiisfcrred to the output So. the circuit is cipablc of sdccting one
of two data sources and routing it tfuoueft to the single exucnit Switch SW1 con-
trols which data sourec is sdccted. This cireuit is a logical cquivalcDt for a sim-
ple single-pole douUe-fluow (SPDT) switch.
 DlgltalTechnlques 1153

Procedure (Cont.)
3. Constmct the dmiit shown in Rgure E20-2. This circuit uses an 8-iqwt
data selcctor TTL 74LS15I IC. Thc desircd ncut is sdected by a 3-bit
codc (ABÇ)whidï is derivcd ftmoa a 74LS193bmaiy counter. This 3-bit
codc is monitored <a LED indicators L2 ûuoush L4. Thc couatcr is
nqïped manuaUy by logic swftdi A.

4SV
±
116

|00
101
SW1-» [02
SW2-^ 103
_î9 04 741S151 Y -»-L1
J4J
SW3-<- J3l
|06
SW4-<- A2| 07

ïiT^o

""-12
-»-l3
-»-L4

B C—D 11.
16_ 45V
74LS183

CIJR_
-L
^L

FigureE20-2
Expcrimcatal circuit forStqis 3 throu^h 6.
1541 STUDENT WORKBOOK

Tlie inputs to the data sdcctor or multiplexcr arc derived ftum data switchcs
SW1 through SW4. TTie data sdector output wiU be monitorcd on LED indicator
Ll.
Thc jns connccrions for thc 74LS151 data selector are givcn in Figure E20-3.
The logic diagram for this drcuit is shown in Figwe E20-4.

DATAWPUTS DATASELECT
-6--^ 'AB"^'
VCCrT~Ï
-4Î6UT«Uï3}-fïUîl-fîot-fîl-

z 3:
-^niriininsnirLni!^
W^STROfiE GND
^3 0,^Y
DATA MPUTS OUTPIHS

FigureEZO-3
Pin comiections for74LS151 multiplexcr.

4. Rcfer to Rgure E20-4. Write the Boolcan ourput cquation for the multi-
plcxer circuit shown. Doing this will help you to undcrstand what thc cir-
cuitdoes.

YS

5. Apply power to your cxperimental circuiL Stqp the binaiy countcr with the
A logic switch untU the L2, L3, L4, states are 000. Observuig the cx-
perimcntal cireuit diagram in Rgure E20-2 and thc datajsclcctor logic dia-
gram in Rgure E20-4, detemunc which iiiput on the 74LS151 is cnabled
with this binaiy codc and recoid it m the MPX column of Table I. Tben
operate each of the data switches. SWI throiigh SW4. and detenaine
which onc affccts thc data sdector output. Rccoid this infonnation in thc
Data Source column ofTable I.

Iiicremcat thc binaiy counter with logic switch A so that the LED in-
dicatois L2 through L4 read 001. Again, detenninc which uaput (DO
througîi D7) of the 74LS151 multiplexcr is cnabled. Confinn this by ac-
tuaring SW1 througb SW4 untfl you detcnninc which switch causes a
diange in the output on indicator Ll. Rccord this infonnauon in Table I.
Qmtinuc incrcmcnting the countcr for all cight statcs and complcte the
table as indicatcd.
 DATA
OATAINPUTS SELECT(BINARy)
Â
STROSE(S) DS 06 D7

Çl ?15 ?U ?13 ?1:

ô
OUTPUTW

FigureEZtM
Lo^c (fiagram of74LS151 multiplcxer.
TABLEI
INPUT
COIffi MPX DATA
INPUT SOURR
c B A

o o o
o o I

o 1 o
o 1 1

1 o o
1 o 1

1 1 o
1 1 1
 »r<-'n^800K
——<.

Discussion
In these stqps you used a binary coumer to sdect oiie of cight inputs on tbc
74LS151 multiplexer. Tbc binary codc fiom thc counter is dccodcd within thc
muldjdcxcr and aiaUcs onc of the wg^ lincs (DO ûuougjh D7). The dedmal
valuc of tbc cnabled unput line correspoads to tbc equivalcnt bmaiy uyut oode.
For cxample, wi& fte ùçutcode 101, niultiplexer uçutD5 is cnahlcd.

Data swiûAesSW1 througfa SW4 are used as thc data souicc for tbc multitplexer
ngntts. Sincc tfaere are only four switchcs. eadi is wucd to two of Ac multiplcxcr
inputs. As you can sce éomRgure E20-2, SW1 drivcs DO and D2, SW2 drives
Dl and D3, SW3 drives D4 and D6 wfailc SW4 drivcs D5 and D7. Your data m
TaUc I (MPX ixqnit) should icucct fhis.

In pperatmg tfais drcuit you should havc discowrea that only onc of uic ei^st
inputs is enaUed at a time. This pemuts oDly ooc ncnit switch to cffcci fl»cout-
put Setting Ac switch altematdy to binaiy O and Irinaiy 1 should havc caused
UFîP indicator Ll to follow.

In Stq> 4 you aic askcd to write Uie Boolean cquation for thc 74LS151 multi-
idexer arcuit in Rgiuc E2ÏM. Your Boolcan equarion should îç»pcaras shown
bdow.

Y«=S(ASeDO+ABCDl+ABCD2+ABeD3+X6CD4+ABCD5+ABCD6+ABCD7)

Notc ftat cach of the iiqwts DO throu^i D7 is cnabted ty its own uniquc iaput
axte. Saobe input S is uscd to cnaUe or disable the coiire drcuit When the S
icpat lir»is low, all dght iaput gates a»enabled thereby pcmutting daia to pass
Ûirou^ïto tfae ouipuL Ifthe sûDbençwtis MÉÎI,aU ofthe gates arc ùihilBtcdand
no data wifl pass duough to the ouiput.

It is evidcnt Irom thc logic equation diat the muldplcxer is a sum-of-products

generator for sSl possftdc comlnnatioDS of Û» wpvas A. B, and C By selecting
the desired iiçnit lines. any Boolcan equation in thc sum-of-products fonn for
thnse variables A, B. and Ccan bc generaied. You will demonscratc this conccpt
inAcDcxtStcps.
 Dlgltal Technlques j 157

Procedure (Cont.)
6. Modify your cxperimcntal circuit to confonn to Rgiue E20-5. Removc thc
conncctions firom the multiplexcr inpuls to data switches SW1 through
SW4. Wire thc inputs ofthc multiplcxcr as shown in Rgiue E20-5. Con-
nccted in this way, the multiplcxcr bccomcs a serial data wonl gcncrator
or a Boolean ftmction generator.
+5V ~1
[16
<sv 100
IDI
102
|D3
-15] |04 74LS151 L1
14] !D5
_13i 06
J2| 07

T 11 |10 |9

L2
-»-L3
L4

—B
A C D 11
16_ +5V
74LS193

CLR
1Î 4.
FigureE20-5
Expcmncntal drcuit for Steps 6 through 10.
1581 STUDENT WORKBOOK

Apply power to fte circuit Step thc countcr with d»eA logic switdi inua
it is in thc 000 state as indicated by LEDs L2 throu^i L4. At tfais tune ob-
scrvc Ae multiplexcr output on LED indicatorLl. This is the first bit of
an n^it-trit woid to bc gencrated by the 74LS151 multiplcxer. Tuc state
you are obscrving at diis tin»is thcLSB ofthe cigbi-bit wonL
Next. stq? fte countcr wift thc A logic switch. At cach counter statc, note
thc multiplexer ouçxit by observing Ll. Incremcnt the counter unta the
last bit ofthc word (couaer state 111) is obtaincd. Reconl the binaiy word
devdoped and its equvalcnt decimal value.

Scrial ouaput binaiy word !

Dccinul eqirivaleitt a

8. Wtfaout changing thc cxperimental cucuit. assumc that it is bcing used as

a Boolean fùnaiongcncrator. Stq) thc coumer thnough its cight states and
agam note tte Ll output condition for cach ofthc countcr states. Usc tfais
data to completc dic truA taUc shown m Tablc II.

9. Usmg thc procedmc you leaxiied in a previous unit, writc ftc Boolcan
cquation (sum-of-products) fiom tbc truth taUc m TaUc II. Rccord yoxu-
Boolcan equarion bdow.

YS

TABLEH
INPUTS OUTPUT

c B A Y

o o o
o o 1

o I o
o 1 1

1 o o
1 o 1

1 I o
1 1 I
 DlgîtalTechnlques 1159

10. Otxserviog the cxperimcntal rircuit m Fîgurc E20-5 and using tfae midti-
plexcr logic diagram in Figure E20-4 for rcferencc, write thc output cqua-
tioa for tfae multiptexer. Note tte states of fhe multiptexcr uapwss. Combin-
ing flus infonnation with the Boolcan equation for the multi{flexcr you de-
veloped cariier. write the sum-of-products cxpicSionof the output Y for
the ncw muJtipIexcr inputs.

Compare tbe cquation developed bere with the cquation you pnxluced
fiom û»uufli tablc in Ac picviousstq).

Discussion
The drcuft you wircd in Stq) 6 pcraaits the mtddplcxer to be uscd as eithcr a se-
rial binaay woid generator or a Boolcan function gcneraior. In cach case the
statcs of thc multiplexcr iaputs detcmune the statcs of the outputs for cach of titie
cight possitde binary inpat codcs from thc countcr.

In Step 7 you used the drcuit lo gcnerate a scrial binaiy woid. The wori pn>-
duccd by this drcuit is 01100101. With thc counicr m state 000, flie muldjflcxer
was obscnring ihc LSB of this numbcr. This is the binary statc ax the DO input
As the countcr was incicmcntcd, eadi ncw bit in thc serial word was genaratcd
unril thc 7th coumcr state (111) was reached. This rcprcscnts fte most significant
bit ofthe word (D7). The decimal equivalent of this binary number is 101,0. An-
othcr way to look at this circuit is as a parallel-to-scrial conveiter. The paraUd
ùçutnumber 01100101 is convcncd to a serial fonnat by thc 74LS151 IC.

In Step 8 you uscd the samc circuit but uuetpreicd its ouqxit as a Boolcan fimc-
tion gcnerator. Assuming the inputs to the muhi{dcxcr are tte logic rignals A, B,
aad C, the circuit output Y is a funcrion ofthcse nyuts aiid the states oftbe mul-
tçlcxcruçwts DO throu^i D7. As you saw cariicr. the multiplcxer is cayùdeof
generating all cight product tenns spedficd by the three bit input By enabling or
disabling the various iicuis thcse tcmis can be added to ûïeoutput In this cir-
cuit, mulriplexer inputs DO. D2. D5. and D6 have becn cnablcd by a +5 volt ag-
nal. This mcans that the terans assodated wiui thcsc inputs will appear in tbc out-
put You vcrified this by ploning a uuth table for thc OUÇULYou shoifld havc
fDund that the arcuit produccd a binary 1 output whcn inpui states 000.010,101.
andllOoccimcd.
1601 STUDENTWORKBOOK

To detcnnine the Bootean oaqxit cquation, you obSCTved tbc troth taUc and
wroie down a producttenn dcvdoped fiom Ac icputstates whens a Unaiy 1 ap-
pcaxs in Ae output For cxanpte, an oucut tcpcars when ncut state ABC is
equal to 010. You would uitcn writc a product tcna equal vs XB?I AU of the
tams are Aen sununcd <ai the output cquatioan. Your equation should be:
Ys A5C+ABC+AgC + XBC
fa StBp 10 you aaalyzed the cSiaectioosto the 74LS151 multiplcxer and wrote
d»e Boolean equtdicn fiom flic dreuit camections. Rcfcrring to the Boolean
equatitm you wrotc for the multiplexer cucuit itsdf»you shouM have found your
Boolcan cquation to bc the samc as tiut dcvdopcd ftan thc tiuth tablc.
 DlgltalTechnlques 1161

Experiment 21
Exdusive-OR/NOR
Objective
To demonstraïe the operaûonof exclusive-OR and exclusiye-NORgates.

Materials Required
Hcadddt Digital Traincr

1 - 74LSOO TTL quad two-input NAND gatc IC (443-728)

1 - 74LS86 TTL quad two-mput exdusivc-OR gate IC (443-891)
1 - 4001 CMOS quad two.input NOR gate IC (443-695)

Procedure
1. Wire the circuit shown in Figurc E2I-1. You wffl use a 74LSOO IC. Thc
iiçuts to the rircuit, A and B, wiU oomc ftom data switches SW1 aad
SW2. Tbe ouqnn C wU be indicated on Ll. Bçsurc to ccnmect +5 volts to
pin 14 and ground toinn 7 on thc IC.

oinpur
"-L1

SW2

..^........^.

+5V

Figure E21-1
Experimental arcuit
for Steps 1 through 3.
162l STUDENT WORKBOOK

Apply powcr to tbe circuit Vsmg datâ switches SW1 and SW2. apply thc
fourseparate sets ofûqHttsindicatcd m Table I. Forcach set ofinputs, re-
coid tfae coiresponding output C and complete Table I.

3. From die tnrth tabk you complcted m Table I, writc thc output cquarion
fiîrthccircuiL

c=
From the oruth taUc and dic cquatiai you can see that the drcuit does per-
fbnn the ___ lopc ftmction.

TABLEI
A B c
o o
o 1

I o
1 I

4. Mount a 74LS86 IC oa the breadboaidii»g block. VTue ii as shown m Rg-

urc E21-2. Thc pin comiecrioixs for this IC are shown in Rgure E21-3. As
in ifac carlicr steps. data switches SW1 and SW2 wfll be uscd to supply the
iapats to thc circuit You wfll moiiitor the ouqnit on LED indicator Ll.

wur ,Î?.:7J"5?., oumrr

*5V

FigureE21-2
Eiqxrimental dreuit ftn- Stcps 4 and 5.
 DIgltal Technlques j 163

'cc
r-®-Jî3Uî5l-(îï]-N4?UîT-

'-uj-isrwhnininir'
FigureE21.3
Pin connections for 74LS86 IC

5. Appïy thc ùçutstates A and B as in<î»cflTç<!in Table II 10 thc expenmeasal

circaiL For cach setof ncxns, monitor thc ouqwt C and record tfae statc m
dic appiopnatc space in Tablc II.

Study thc trudi taUe and dctcmune v/bat fiuicdon uie circuit is perfonn-
ing.

TABLED
A B c
o o
o 1

I o
1 1
164) STUDENT WORKBOOK

6. Construct the circuit shown in Rgure E21-4. Tlie inputs will comc ftom
tbc data switches and you wUl observc thc ontputs on the LED indicators.
Switdi SW4 and LED indicator L4 can bc considcrcd to be Ae LSB of thc
four-bft binaiy word input and ouqnjL

SW1 1 "
3_ "u
^>
SW2
""-L2
£>
SW3
Jfi
12:
o " 13

SW4
LS8 St^> Y

*'-[i-i""'f7
11 "»-L4
ise

<5V T
FigureE21-4
Experimcntal circuit
for Stcps 6.7, and 8.

7. Sct aU ofthe input data switches to tfic bijaaiy O state. Obscrvc the ouqnit
statc and record youroulput valuc bdow aiid mTablc m.

IiyuisOOOO.Oucuts

Ncxt, dcpress flie A togic switch and hoM momentarily while observmg
Ûicouçutindicators. Rccoid the state presuucd below and in TaUc m.

înpat =0000, Oaput = __

R>r cadi ofthc iiqwt states recoided in Table m, reconl tfac ouqmt states
wifli the A logic switch in its nonnal position and in its dqircsscd position.
TABLEm
INPUTS OUTTUTS

ANORMAL ADEPRESSED
SW1 SW2 SW3 SW4
Ll L2 L3 L4 Ll L2 L3 ÏA

o o o o
1 1 I I

1 o 1 o
o o 1 1
 Dlgltal Technlques | 165

8. Study the rcsults in Table III. Using this infonnadon and thc drcuit in
Rgurc E21-4 plus the rcsults of your previous steps. deteraaine the fimc-
tionofthiscircuit.

Discussion
In Stq» l you consttuctcd an exduswe-OR circuit using a 74LSOO quad two-
input NAND gate. Applying thc inputs A and B indicatcd in Table I you should
havc fouiid tfut the output of the circuit was binary 1 whcn either (me but not
both of the inputs were binaiy 1. As long as the inputs were complementaiy thc
output was binaiy I. Fbr cqual value binaiy inputs, thc output was buuiy 0. This
is typical of the exdusive-OR ftmction. In wriring the Boolean cquation of tfris
cucuit fipom thêcnuth tablc you should havc found it to bc C = AB + AB.

In Step 4 you wired a drcuit using a 74LS86 IC. This is a quad exclusive-OR
gatc. Four complctc cxduavc-OR drcuits arc comained within this package.
With an MSI dcvicc such as ûàs,it is uancccssaiy 10 implcmcm cxclusive-OR
gates with gate packagcs as you did ui Stq> 1.
Applymg the inputs given in Table II you should havc found that the circuit in
the 74LS86 does mdeed perfonn the exdusive-OR ftmction. The results you ob-
tained in TaUc U should bc cquivalcnt to that you obtaincd m Table I,

The circuit you constniaed in Step 6 not only fllustratcs the operauon of an
exclusivc-OR gate, but also shows one practical applicauan. Here a four-bil bi-
nary word firom the data switchcs is qïplicd to the cxdusive-OR gatcs. You no-
riccd &om Rguns E2I-4 that onc input ofcach of the cxduriyc-QRs is canncctcd
togcther and wired to togic switch A. Widi kigic switdi A in the nonnal. ron-
dqncsscd statc, ouqnit A is binary O. Knowing thc ppcrMion Qf thc cxclusivc-OR
and the siate ofthc iiqwt data switchcs you should be ablc U) detcnnine what the
cxclusivc-OR gatc ouqBUts are. Rcfcmng to the uuth tabte for an exclusivc-OR
you can see that wlust Onc iiqïut to cach of flie cxdusivc-OR gatts is binaiy 0,
thc ouqwt of that cxdusivc-OR gatc will be cqual to the binaiy statc of the othcr
WpûL

When logic switch A is dcpresscd, a binaiy 1 is applied to all of thc cxdusivc-

OR gatcs. Looking at the truth taUe then you can sce that thc ouqnit of thc
cxdusive-OR will be the complemeni of its other inpuL The circuit m Figure
E21-4. therefore, is a binary complemcnter. Undcr thc connol ofthe A input, the
ouçut can be cqual to the input or its comiricment depending upon the siate of
thc A ininit to Tabte DI you îÇïpUcdfour different inputs and monitored the out-
puts with thc A logic switch in both the nonnal and the dcpressed states. With
tbe A logic switch in the nonnal position. tte LED indicators should indicate the
statc of die inputs. With thc A logic switch depressed. the LED indicators should
show the complemcni of the input states.
1661 STUDENT WORKBOOK

Procedure (Cont.)
9. OonstructdKdrcuitshowninRgureE2I-5.Youwinusea< l CMOS
quad NOR gsue IC. Ixspats A aad B wiU comc from data swr.^bcs SWI
aod SW2 as bcfore. You wffl obseive Ac ouçnttC on LED indicatorLl.

<5V

SW1
ourpyr
i—U

swz

F^ureE21-5
Expcrimental circuit
forStcps9.10,andll.

10. Sauly the circuit m Rguns E21-5. Write thc ouxpat cqpressioD C fbr thc
cucuit in tenns ofnç»atsA and B. Use Boolcan algebra and DeMoi^an's
thcorem to manipidatc thc oaxfwt cxpresaon into its sunplest fonn.
c»
11. Apply ths iqpnt «atesdiown in TaUc rv. Rccord thc output C for cach of
die ooncsponding input siaies. Study thc tablc and dcterauDe wfaat func-
tiai &e dicuit is perfbmiiDg.
Ennn TaUe TV, write ttie Boolean cquation cxpnsssing thc opcration of
thiscirouit

TABLEIV
A B c
o o
o 1

1 o
1 1
 Dlgltal Technlques 1167

12. Studying Ae results of your equadon, dctennine the funcrion of thc cir-
cuit This circuit is known as a _ _ or a ^"

Discussion
Tbe drcint you constructed in Stcp 9 is an cxclunvc-NOR gate. 'Ilic oucwt
cquation for thc circuit is C= AB + AB. This.ofcouree, is the Boolean cquation
for an cxdusive-NOR gaie. The cxdusive-NOR fiiccrion is tfac complcmaat of
tfae cxditave-OR fimctfoa.

You ptottcd a truA taUc to vcrily flie opcration of flus drcuit You should havc
fouod dut Ae cireuit ouQiut C was cqual to binaiy 1 wfacn tte two iicuts were
equal u»one anothcr. Whcn tfic uqnits wcrc complemcntaiy, flie ouqxits were 0.
Another namc for thc cxdusive-NOR is comparator or cquivalcDce drcuiL
1701 STUDENTWORKBOOK

Materials Required

HeatUdl Digital TTainer

DC Voltmeter or logic probe
1 - 74LSOO TTL quad two.input NAND gaxc IC (443.728)
1 - 74LS20 TIL dual fow-vspat NAND gate IC (443-798)
1 - 74LS04 TTL hcx invertcr IC (443.755)
1 - 74LS151 TTL data sdecttn/DaultipIexcr IC (443^78)
2 - 74LS76 TIL dual JK fly-flop IC (443-829)
1 - 74LS86 TTL quad two-ncut cxchisive-OR gate IC (443-891)
I - 74LSI93 TTL synchronous up/Uown binaiy counter IC (443-815)
1 - 7495 TIL fBur-Ut shift registcr IC (443-680)

Procedure

1. Cunscuct tfae cireuit rihown in Rgure E22-1. Tlus isa fbur bit parity gcn-
cntor cucuit made fixm flie 74LS86 quad cxdusivc-OR IC The iapatto
dic parity generalor drcuit wfll comc from the binaiy couirtcr 74LSI93.
You wffl acp the oounterttaoagh its rixtecn statcs and obscrve ihe parity
bat oaçutou your DC vdtaneter or logic probe.

14 U U L1 45V

74LS1931
UP
couwr
74LS86 .L..O
J4
lcu»
w 'J"
lï '—""""-J;-i3""~'p'i'""p
B tW SW1 4W '="

FigureE22-l
Parity generator cireuit
fi)rSttpsItiauougb5.

Study the circuit shown m Rgure E22-1. Assume SW1 is in tfac binary O
posirion. Wffl the parity output bitP bc odd orcven? ^.

Wth SW1 in thc binaiy 1 position, wm tbc paiity output bit P bc odd or
cven?
 Dlgltal Technlques | 171

3. ApplypowertotitecucuiLUselogicswitchBtoclcarthebiDarycountcr.
Sct SWI to binary O posirion. Connect your DC voltmeter to pin 11 oftibc
74LS86 IC. Rccord tbe bmary oucut statc of P with the ioput code 0000.
Usc dhc igïpropriate column m Tablc L CFbr TTL drcuits binaiy 1 s= +35
volts. binary O = +0.1 volts)

laciement thc binary couDtcr wiui Ae A logic switdL Obsnvc the countcr
statcs on Ae LED mdicauïis. For cach of thc sixtecn ixipat states, rccord
the concspondinig binaiy ouqiut siatc ofP m Table I.

TABLEI
D c B A P(SW1«0) P(SWI«=1)

o o o o
o o o 1

o o 1 o
o o 1 1

o 1 o o
o 1 o 1

o 1 1 o
o 1 I 1

1 o o o
1 o o 1

1 o 1 o
1 o 1 I

I 1 o o
I 1 o I

1 1 I o
1 1 I 1
1721 STUDENT WORKBOOK

Rcpeat Step 3 widi data switch SW1 in thc binaiy 1 posirion. Rccord your
output staies in d»appropnaxc column ofTable J.

Study your resiilts in Table I and detennmc wtuch position of SW1 pro-
duccs odd and cven parity.

What lùnctiondocs cxdusive.OR gate 4 in Rgurc E22-1 play in dcteimin-

ing Ihc namre offhc output parity bft? _ .

5. Assume tfaat the drcuit m Figure E22-I is a parity checkcr circuit raflicr
than a parity gcnerator. Exdusivc-OR gatcs 1 dirough 3 fonn the parity
gcncrator drcuit wtsle cxdusive-OR gatc 4 thcn becomcs thc comparator
to compare thc parity bit cansmiucd wiA the data (sunulated by SW1)
and tfac parity bit gcnerated by the word ftsdfthrough gates 1. 2, and 3.
Answcr the foltowing qucstions:

A. Smce this is a parity chcckcr circuit. what docs output bit P indicate?

B. Does the pariiy gcnerator circuit, madc up of gates 1, 2, and 3, gencr-

aic odd or cvcn parity?

Assumc that thc input word fttan the binary coumcr is 1010 and thc
uqnn parity Ut fiom SW1 is bmary 1. Docs a parity error cxist?

Discussion
Tbc cirarit you constructcd m Rgiuc E22-1 is a parity gcncrator. X-OR gates 1,
2, aad 3 fonn an cvcn parity generaior cinaut. X-OR gate 4 is tïsed as a com-
plementer to provide duier odd or cven parity output Whcn SW1 is in the bi-
iiaiy O posidon. thc ouqwt of X-OR gate 4 wfll be an cvcn pariiy bit Setting
SW1 (o the trinary 1 position causes thc evcn parity output circuit from X-OR
gate 3 to bccomc complcmcnted and thus produce an odd parity output.
 Dlgltal Technlques 1173

You used the 74LS193 binary coimtcr as a outh table generator for the circuit
Rather dian using the data switches as an input. you usc fhe binary counter smce
the four bit binaiy code is generatcd automaticaMy cach time you mcrcmeiit the
counter with logic switdi A. The iMnary counter makcs an excellent iruth tablc
gaierator for producmg aU possible combinarions of four logic signals to apply
to a combinational lopic drcuit for piuposes of dciennining its oucut statcs.
You rcconlcd in Tablc I bodi the odd and cvcn parity owput bits by semng SW1
to binaiy O aad then tbc binary 1 state. With SWI in the binary O porition, even
parity is produced. Evea parity means fliat the total number of ones in the binary
woni induding the parity bit is cven. Widi SW1 in thc bmaiy 1 position, odd
parity is gcncrated. Herc the total number of ones in the input woid including the
panty bit is odd. Note that the odd and cven parity output bits arc
complcmcntaiy.

Whcn using the circuit inRgure E22-I as a parity checker circuit, X.OR gates 1,
2, and 3 fonn an cvcn parity gcncrator drcuiL Tbe ouqput of X-OR gate 3 is the
cvcn parity bit which is qiplicd to one input of X-OR gate 4. This is compaied to
an cxtcnaally transmittcd parity bit vrfiich in this case is represemed by SW1.

If the binaiy input «xteis 1010, the cvcn parity gcncrator wiU produce fbe bi-
nary O output bit so that cvcn parity is produced. At the same rime, if SW1 icpre-
scnts a parity input bit which is binary 1. a parity eiror wiU be generatcd. The
parity cnor comparator or dctcctor is X-OR gate 4. A binary 1 output wfll be
produoed ifthe two inputs to this gate arc complemcniaiy. This indicatcs a parity
error. No parity crror is uidicatcd when the two bits are cqual or alike.
174 1 STUDENT WORKBOOK

Procedure (Cont)
6. Wire the circuit shown in Rgurc E22-2. You wffl again use tfae 74LS193
binaiy counier as a tnitfa taUc gcncrator. The binaiy code will be ap^ied
to tihe cuncuit made up fiom thc 74LS86 quad exduaive-ORIC You wOl
observe theouçuton Lt?n indicatois Ll throu^h L4. This is a codc con-
vener circuit fhat wffl chan®cthc binaiy code fiom titie 74LS193 counter
into another code. You wiD detuaaine that codc m thc next step.

A +5V
74LS18315 ^...l...£

+SV

FigureE22-2
Codc coiivcncr cuaut
forStcps6fluou^i8.

Apply power to tfac circuiL Dcpress thc B logic swiich momentarily to

dear the counter to zero. Rccord thc output oodc m the first spacc pio-
vided m TaUe D. iBcmnent the counter sixtcca timcs and at cach step rc-
cord the oudput code inTablc D.

8. Obscrvc the codc that you copied m Table JL What codc did thc codc con-
vener ciicuit gcDerate? _.
 DlgltalTechnlques J 175

TABLED
Ll u L3 ÏA
178 1 STUDENT WORKBOOK

Discussion
In these stcps you used cxclusivc-OR gatcs to construci code convciter circuits.
The cireuit in Rgure E22-2 is a binary to Gray code convcncr. Thc binary codc
generatcd by the 74LS193 binary countcr is applicd to Uie 74LS86 cxdusive-OR
drcuit wfaich gcncrates fhc Gray code oulput The codc you nscoidcd m Table U
thereforc is the Gray code. Check your icsults by refening back to the Gray codc
TaUc in the tcxtbook.
"nic circuit in Figure E22-3 is a
Gray to binary code coavertcr. You appUed the
Gray codc to thc input circirit with the data switches. 'Ilic circuit should havc
gcneratcd the coiresponding binaiy oucut codc. Check your results by rcfening
to thc tcxtbook.

Procedure (Cont.)
12. Construct thc drcuit shown in Figure E22-4. This is a four-bit comparator
circuit that monitons two four-bit ugnit words and generates an output sig-
nal that iiidicatcs when the two words are cquaL Thc two four-bit data
sources are the data switchcs SWI through SW4 and thc four-bit binaiy
output code fiom the 74LSI93 counier. The binary counier output is
monitored on LED indicators LI througft L4. Thc comparator circuit is
made up of the 74LS86. 74LS04. and 74LS20 ICs. Tbs output is
monitored on a DC volanctcr or logic probe.

Study the circuit in Figurc E22-4 and detenninî tbe nccd for the 74LS04
inveitcrs ai die oucut of thc cxdunvc-OR gates. What are thc purposes of
thesc invcrtcrs?

13. Apply powcr to the drcuit Depress logic switch B momcntarily U) resct
thc counier to 0000. Vcrify the operation of thc comparator circuit by set-
ting the number 0011 into the data switches (SW4 = LSB). Thcn, using
logic switch A, inaemcnt the 74LS193 countcr. Obscrve the DC voltagc
at the output As soon as the outpit voltage rises to the binary 1 level,
compare the LED indicaior display with the data switch state. They should
beequal.

Set different valucs of four-bit binary numbers into flic data switches and
again incrcment the coumer wiih togic switch A, noring when thc DC
volimctcr rcads the binary I voltagc lcvcl at the ouqiut For each sct of in-
put woids, comparc ihe LED indicaior staies to the data switch value when
the output gocs high.
 Dlgltal Technlques 1179

_74l.S86 ^.;.%LSÇ4....,
LSB :
-li—xr—^
SW4

SW3
ÏE^- M- .T.
^.;.%L».°..J.y 1/6-74L&M.

swz'

SW1-

FigureE22-4
Comparator circuit for Steps 12 and 13.

Discussion

fa tbese steps you consttuctcd a binary comparator drcuit and vcrified its opcra-
tioii. You compared thc four-bit trinary woid ftom flie data switches to a biiiaiy
number generated ty the 74LS193 couiuer- When thc two numbexs wetc cqual,
thc DC volancter output mdicated a binaiy 1 lcvcL

A binaiy comparacor circuit is consuucted by using an cxdusive-NOR gate for

cach pair of concsponding bits in dic words to be compared. Thecxdusive-NOR
gates are constructed in tlris rircuitby connecting inveners at tite outputs of the
cxdusive-OR gates in the 74LS86. Tlic outputs from the 74LS04 uivcners are
thcn ANDed in thc 74LS20 NAND gate. The 74LS04 invcner at the ouiput of
the 74LS20 makes the arcut produce the AND funcrion. The output is a binaiy
1 when the two four-bit input words are identical.
1801 STUDENTWORKBOOK

Procedure (Cont.)
14. Consnict ftc circirit sbown m Figure E22-5. This is a complex circirit so
bc careful in putting it togeAer. Thonc are six intcgratcd circuits uivolved
and many wiiiag CTimecttons. Be sutc to conncct +5 volts and ground to
cachIC.

Tlris circuit is a serial biaary adder. Two 4-bit serial binaiy ronnbers are
fcd into a fuU adder circirit One ofuienumbeis to be added (tbc addcnd)
is stored in tbc 7495 4-bît shift rcgister. The othcr 4-Irit numbcr (the
augend) is storcd in the data switctoes and convencd to serial fonn by thc
74LS151 multiplexer. Tlie adder is made up oftfae 74LS86 cxdusive-OR
and the 74LSOO quad 2-iicut NAND gate. The two numbcis ans added a
bit at a timc and flic sum is shifted back: uuo tfac 7495 and displaycd on
LED mdicators Ll tbrough L4. Onc of the JK flip-flops in d»e74LS76 IC
is used as a memoiy for tfac cany bit (Co) gencrated by thc adder. Tlie A
logic switch is uscd to gcnerate flic clock or shift pulscs. Thc B logic
switch is used to reset the dreuit

15. Apply powcr to flie drcuit Sct thc buiary number 0111 into fl»c data
switchcs. Connect a wire fiiom pin 6 ofdic 7495 shift rcgister to +5 volts.
Tlus is the modc control mput to flie 7495 riMft registcr. It dctcrouncs
whether the device is parand loadcd or produces a shift right operarioDL In
this stqï, you wOl load flie registcr ftom tiic data switches. This will hap.
pen whsn tte modc connol input linc is high. Dcpress the A logic switdi
onoc to load thc data imo thc registcis. Thc I.ED indicators shoidd thcn
read the samc as thc data switches, 0111.

Movc tfae wire fiom pin 6 on fl»c7495 to ground. Set tbe data switcbes to
0101. Dcpress flie B logic switch to resct flie 2-Ut binaty counter driving
tfac 74LS151 multiplexer and tbe cany fl4>-ftop.

16. Dqpress thc A logic switch four tunes. F.adi tiine you dq»ressit, you wffl
note a change in flie ff^ display as the cinaut gaaeratcs u»e sum and
shifts îi ioto the 7495 repstcr. Oiicc four shift ptdscs havc becn generatcd,
note tte LBD oucwt display and ncoxd thc number.

Sum'

17. Rqïcat stçp 15 sevcral times. but use different binaiy numbcrs cach tinae.
Rcmanbcr thai. sincc the 7495 has a maMmuna cmiicnt of four bits, thc
sum must be 15 (1111) or kss if it is to appear coirecuy in tte regisier.
Rqxat thc operation sevcral times to bc sure that thc circuit does pcifonn
properiy.
 Dlgltal Technlques J 181
SUM_

U 12 U L«
ADDENO ,.1ff.-..74l^6.......J.Î4...J7...
h3 h2 hi hc
—CD^
INA B
14
d cuc +SV
+5V

I s^ MOOE
7485
-L 74LSOO

1 SW1-»
swz^.
SW3-^
SW4-»
2_ 3^ +5V T
03 02 D1 00
+5V AUSBID
741S151 Y

Jk B C
z rtT 10
T
,?A§%..... ^
Î2-
+5V. _4 J A ^54 lSfj—Bl21t^- 4SV
a.ocK
J2 F
""^""""à'
+5V. K A K B
ii3_
—*—t«-——'
B-<- ^
RESET

FigureE22-S
Serial binary addcr
drcuit for Steps 14 through 17.
1821 STUDENT WORKBOOK

Discussjon
Thc proccdure for operating this addcr circuit is to fust load the 7495 shift
rcgistcr. You did tfais by sening the modc control at pm 6 to binaiy 1 to pennit
presctting of thc registcr ftom the data switches. You dqiresscd thc A logic
switch to gcncrate the dock pulse that loads the 7495 Tegister witb the numbcr
0111. You thcn retumcd thc modc connol to bixiary O so that thc rcgistcr would
shiftright.

Next. you set the numbcr 0101 uuo the data switches. Thc 74LS151 mxilriplcxer
convens this paraUd woid into a scrial wotd as ii is sequcaced by the two-bit bi-
nary counter madc up of a 74LS76 dual JK flip-flop IC

Next, you used the A logic switch togcucrate shift pulscs diat causc the addition
to occur. Thc numbcr in the 7495 shift registcr is shifted out nuo thc addcr.
Thesc samc pulses mcrement the binaiy countcr and scquencc thc multiplcxcr.
Thc sum is stored m ftc 7495. Thc coirect sum should havc becn 1100.

Tbc Innary addcr in this circuit operates just Ukc the fuU addcr ciicuit discusscd
previouriy in the unit Thc only differencc is the addition of a JK flip-flop fiom a
74LS76 ICto use as a carry mcmoiy. Sincc wc areadding a singlc bit at a umc.
some means must bc provided for remcmbering thc occuireace of a cany so that
it can be addcd to the ncxt most significant bits in scquence.

Thc JK flip-ftop stores this cany. Note that the output of one gatc in thc 74LSOO
IC is labded cany-out (Co). This is applied to thc JK inputs. Assume that the
LSBs of &e numbers to bc added are applicd to the adder. The cany output Ime
at this timc wul havc on it a binaty state that indicates the prcscncc ofacany bit
if the states of the input bit are such that it produccs a cany. Assuming that a
cany is produced, this caxry signal will be loaded into the JK flip-flop whcn the
first dock pulse ocaus. At Ae samc tiac. the addcr is gcncrating the propcr bi-
naiy suSof thc two LSBs. Tlus is appUed to the scrial input ofihe 7495 riuft
rcgister. Therefore, when thc first dock pvSse ocaus, dte first sum bit is loaded
intD Ac 7495 shift registcr and the cany statc is stored m thc JK flip-flop.

Thc lcast significam bits have now becn added and lost. The ncxt most signifi-
cant bits now appcar at thc adder inputs. The propcr sum is gcnerated aad ap-
pears at the scrial iqput of thc 7495 shift registcr. At the same timc. thc cany
state fiom flic prcvious two bits stored in tfie JK flip-flop is aiqîlied to thc cany
input (Cj) of thc adder. This cnsures that thc previously gcnerated cany is added
to thc next two most significam bits. Tbc propcr sum then is gcnerated and is
loaded into the shift registcr when the ncxt dock pulse occurs. Also during thc
next dodc pulse time thc cany staie of thc prescndy moniiorcd bits is stored in
thc JK cany flip-flop. This acrion is cononucd unril aB four bits havc bccn
addcd. At this time Ac propcr sum is in die 7495 shift nsgisttr.
 Appendlx I A-1

Appendix A
IC Pin Assignment Diagrams
VGC 48 4A 4Y 38 3A 3Y
wi-rauiîLJt iLJia-i "u "

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«*"«¥«A tV »A SV OND 741S42
74tSO« Bco.nM)EOM<u. OEcooen
HEXINVEmïS
A-2 lAppendbc

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VCC
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vcc
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 Appendix j A-3

INPUTS ourpurs INPUTS

81-1171-116M15MMM13M12M11M10

6U15{-(M{-«3W»2U"1-(«OM8

II

@ 11111
U1 '-Q-ïiMïnin^-tsnzn^nir'
S S 2 3
2114
s < 3 IS

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1Kx4<(TCTATICR*M

°
^T'ljls^T
OUTPUTS
'^2^' otnnjrs
<wvr vcc
741S1B3
8VNCHRONOUS UROOWN 8WMW COIWTER r-R-}ï3l-p2l-FUîot4?Uïl-

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CMOS aUAD TWCMNPUT NOR

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OR 14495-1

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A-4