STATIC TIMING ANALYSIS
Topic – Analysis of Different timing paths
Basic Terminologies Combinational logic
Input D Q Combo D Q
ck Launch Flop ck Capture Flop Out
clock
Setup Time – It is the minimum time required for the input data that must be stable before the
Capture edge arrives.
positive Launch edge
Positive Capture edge
Setup time
Required Time – It is the Time required for the input data must be available before the setup
Time.
positive Launch edge
clk
Time period positive Capture Edge
clk
Required time setup time
Required Time = Time period of clock + T(clock →ck) – setup time.
Arrival time - It is the time taken by the data input to travel through sequential and
combinational block and end at input pin of capture flop.
positive Launch edge
clk
T(C2Q+combo)
Arrival Time positive Capture edge
clk
Setup time
Arrival time = T(clock → ck) + T(ck →Q) + combo(combinational delay).
Setup Slack :- It is the difference of Required time and the arrival time.
Setup slack = Required time – Arrival time
positive Launch edge
clk
T(C2Q+combo)
Arrival Time positive Capture edge
clk
Setup time
Required Time
Setup slack
Launch flop :- It is the flop flip at which the input data will be launched with respect to
launch edge of clock.
Capture flop :- It is the flop flip at which the input data will be catured with respect to
capture edge of clock.
Single cycle path :- The path at which data arrives one T(time period) time after the launch
edge
positive Launch edge
clock
positive Capture edge
Single cycle path (T)
In single cycle path required time = Capture clock delay + T - setuptime
Multi cycle path :- The path at which data arrives greater than oneT(time period) time after
the launch edge
positive Launch edge
clock
positive Capture edge
Multi cycle path (2T)
In Multi cycle path required time = Capture clock delay +2T - setuptime
Half cycle path :- The path at which data arrives T/2(time period) time after the launch edge
positive Launch edge
clock
Negative Capture edge
Half cycle path (T/2)
Different Timing Paths in STA
1.Input to Register
2.register to register
3.register to output
4.input to output
Design A
In to R
IN1 R to R path
D Q
R to Out path
r1
A1 Y out1
Ck D Q
clk1 A2 U2 ck r3
AAAAA
in to R path
In2
D Q A Y
clk2 R to R Path
Ck r2 U1
clk3
In3 A Y out2
U3 In to out path
As we can see the various timing path in the (Design A) Named as,
1.In to R(In1 to r1, In2 to r2) which is shown in Orange colour.
2.R to R (r1 to r3, r2 to r3) which is shown in Blue colour.
3.R to out (r3 to out1) which is shown in Green colour.
4.In to out(In3 to out2) which is shown in Black colour.
*In to R
As of now we are analysing only (in1 to r1 path)
positive Launch edge Arrival Time
clk1
clk1 to in1 + in1 to D(r1) positive Capture edge
clk1
clk1 to CLK Setup slack Setup time
Required Time
Time period(clk1)
Arrival Time = (clk1 to in1)delay + (in1 to D(r1))delay
Required Time = (clk1 to CLK)delay + T(clk1) – Setup Time
2. R to R path(r1 to r3 and r2 to r3)
As of now we are analysing only r1 to r3 timing path.
positive Launch edge Arrival Time
CLK1
Clk1 to CLK + combo delay positive Capture edge
CLK3
Clk3 to CLK Setup slack Setup time
Required Time
Time period(clk3)
Arrival Time = (clk1 to CLK)delay + (Clk to Q)delay + Combinational delay
Required Time = (clk3 to CLK)delay + T(clk3) – Setup Time
3. R to out (R3 to out1)
There is only one R to out timing path exits.
positive Launch edge Arrival Time
Clk3
Clk3 to CLK+ CLK to Q + Q to out1 positive Capture edge
Clk3
Clk3 to CLK
Output External Delay
Required Time Time period(clk3)
-ve Setup slack
Arrival Time = (clk3 to CLK)delay + (CLK to Q(u2))delay + (Q(u2) to out1)delay
Required Time = (clk3 to out1)delay + T(clk3) – output external delay
4. Input to output path(In3 to out2)
There is only one Input to Output timing path exits.
Arrival time = CLK(Source clock) to IN3 + In3 to Y(u3) + Y(u3) to out2
Required time = Time period(CLK) – (CLK to out2)delay
positive Launch edge Arrival Time
CLK
CLK to IN3+ IN3 to Y + Y to out1 positive Capture edge
CLK
CLK to out2
Required Time Time period(clk)
-ve Setup slack
