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STRUCTURE Silicon Monolithic Integrated Circuit

NAME OF PRODUCT DC-AC Inverter Control IC

TYPE ＢＤ９８９６ＦＶ
FUNCTION ・2ch control with Push-Pull
・Lamp current and voltage sense feed back control
・Sequencing easily achieved with Soft Start Control
・Circuit protection with Timer Latch
・Under Voltage Lock Out
・Over Voltage Protection
・Mode-selectable the operating or stand-by mode by stand-by pin
・BURST mode controlled by PWM and DC input
・Output linear Controllable Analog dimming by external DC voltage
・Synchronous operating the other several BD9896FV IC’s

○Absolute Maximum Ratings（Ta = 25℃）

Parameter Symbol Limits Unit
Supply Voltage VCC 15 V
Operating Temperature Range Topr -40～+90 ℃
Storage Temperature Range Tstg -55～+150 ℃
Power Dissipation Pd 1062* mW
Maximum Junction Temperature Tjmax +150 ℃
*
Pd derated at 8.5mW/℃ for temperature above Ta = 25℃ (When mounted on a PCB 70.0mm×70.0mm×1.6mm)

〇Recommended operating condition

Parameter Symbol Limits Unit
Supply voltage VCC 6.0～14.0 V
Output oscillation frequency fout 25～90 kHz
BCT oscillation frequency fBCT 0.05～1.00 kHz

Status of this document

The Japanese version of this document is the official specification.
Please use the translation version of this document as a reference to expedite understanding of the official version.
If these are any uncertainty in translation version of this document, official version takes priority.

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○Electric Characteristics（Ta=25℃，VCC=7V）
Limits
Parameter Symbol Unit Conditions
MIN. TYP. MAX.
（（WHOLE DEVICE） ）
Operating current Icc1 － － 17.0 mA CT_SYNC_IN=Low
Stand-by current Icc2 － － 10 μA CT_SYNC_IN=OPEN
（（OVER VOLTAGE DETECT））
FB over voltage detect voltage Vovf 2.20 2.40 2.60 V
（（STAND BY CONTROL））
Stand-by voltage L VstL -0.3 － 0.8 V
Input voltage range of Slave setting VstH1 1.8 - 2.25 V
Input voltage range of Master setting VstH2 2.55 - VCC V
（（TIMER LATCH））
Timer Latch voltage Vcp 1.9 2.0 2.1 V
Timer Latch current Icp 0.5 1.0 1.5 μA
（（BURST MODE））
BOSC Max voltage VburH 1.94 2.0 2.06 V fBCT=0.3kHz
BOSC Min Voltage VburL 0.4 0.5 0.6 V fBCT=0.3kHz
BOSC constant current IBCT 1.35/BRT 1.5/BRT 1.65/BRT A
BOSC frequency fBCT 292.5 300 307.5 Hz BRT=36kΩ BCT=0.048μF
（（OSC BLOCK））
MAX DUTY MAXDUTY 44 46.5 49 % fout=60kHz
Soft start current Iss 1.0 2.0 3.0 μA
IS COMP detect Voltage Visc 0.45 0.50 0.55 V
SS COMP detect voltage Vssc 2.0 2.2 2.4 V
SRT ON resistance RSRT － 200 400 Ω
（（UVLO BLOCK））
Detect voltage (VCC_UVLO) Vcc_vuvlo 5.100 5.300 5.500 V
Hysteresis width (VCC_UVLO) ⊿Vcc_vuvlo 0.150 0.200 0.250 V
Operating voltage (UVLO) Vuvlo 2.260 2.340 2.420 V
Hysteresis width (UVLO) ⊿Vuvlo 0.075 0.100 0.125 V
（（REG BLOCK））
REG output voltage VREG 3.038 3.100 3.162 V
REG source current IREG 5.0 － － mA
（（FEED BACK BLOCK））
IS threshold voltage ① Vis① 1.225 1.250 1.275 V VREF pin:OPEN,REG is shorted

IS threshold voltage ② Vis② － VREFIN VIS① V VREF pin is supplied

VS threshold voltage Vvs 1.220 1.250 1.280 V

IS source current 1 Iis1 － － 1.5 μA DUTY=2.2V
IS source current 2 Iis2 13.0 20.0 27.0 μA DUTY=0V、IS=0.5V
VS source current Ivs － － 1.0 μA
Over 1.25V is not
VREF input voltage range VREF IN 0.6 － 1.6 V
effective
（（OUTPUT BLOCK） ）
NBｃｈ output voltage Ｈ VoutNBH VCC-0.3 VCC-0.1 － V
NAｃｈ output voltageＨ VoutNAH VCC-0.3 VCC-0.1 － V
NBｃｈ output voltage L VoutNBL － 0.1 0.3 V
NAｃｈ output voltage L VoutNAL － 0.1 0.3 V
NBｃｈ output sink resistance RsinkNB － 5 10 Ω Isink = 10mA
NBｃｈ output source resistance RsourceNB － 8 16 Ω Isource = 10mA
NAｃｈ output sink resistance RsinkNA － 5 10 Ω Isink = 10mA
NAｃｈ output source resistance RsourceNA － 8 16 Ω Isource = 10mA
Drive output frequency fOUT 57.9 60.0 62.1 KHz RT=15.94kΩ
（（COMP BLOCK））
Overr voltage detect VCOMPH 2.4 2.5 2.6 V
Hysteresis width (COMP) ⊿VCOMPH 0.040 0.060 0.080 V
（（PROTECT CLOCK））
FAIL-pin On resistor value R_FAIL － 200 400 Ω
（（ SYNCRO BLOCK））
CT_SYNC_IN_High input Voltage Range VCT_SYNC_IN_H 2.0 － VCC*0.8 V
CT_SYNC_IN_Low input Voltage Range VCT_SYNC_IN_L -0.3 － 1.5 V
CT_SYNC_IN Pull-up resistor RCT_SYNC_IN_pull_up 500 － － kΩ
CT_SYNC_IN Self-oscillation voltage VCT_SYNC_IN VCC＊0.9 － VCC V
CT_SYNC_OUT sink resistor value RCT_SYNC_OUT＿sink － 150 300 Ω
CT_SYNC_OUT source resistor value RCT_SYNC_OUT＿source － 370 740 Ω
CT_SYNC_OUT_High output Voltage Range VCT_SYNC_OUT _H 2.8 3.1 3.4 V
CT_SYNC_OUT_Low output Voltage Range VCT_SYNC_OUT_L － － 0.5 V
SRT SYNC Exchange detect Voltage Vsrtc 0.5 0.8 1.1 V
（This product is not designed for normal operation with in a radio active environment.）

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〇Package Dimensions

Device Mark

BD9896FV

Lot No.

SSOP-B28 (Unit:mm)

〇Block Diagram 〇Pin Description

VCC REG CT_SYNC_IN CT_SYNC_OUT RT BRT BCT DUTY

端子番号 端子名 機 能
REG DUTY
Block
OSC BOSC
Block 1 NA1 FET driver for 1ch
SYSTEM ON/OFF 2 NB1 FET driver for 1ch
STB
STB Block Master/Slave CT External capacitor from CP to GND for
UVLO VCC 3 CP
Block UVLO
Timer Latch
SS
4 REG Internal regulator output
FB1 VCC
5 FAIL Protect clock output
IS1 F/B LOGIC OUTPUT NA1
PWM
VS1 Block ①
SS
Block ① Block Block ① NB1 6 VREF Reference voltage
CT ①
7 CT_SYNC_OUT Output pin of CT synchronous signal
FB2 VCC
8 CT_SYNC_IN Input pin of CT synchronous signal
IS2 F/B LOGIC NA2
PWM OUTPUT
Block ② SS
Block ② Block Block ② External resistor from SRT to RT for
VS2
CT
NB2 9 RT
VREF
adjusting the triangle oscillator
PGND
External resistor from SRT to RT for
GND 10 SRT
PROTECT
FAIL
adjusting the triangle oscillator
Block
11 GND GROUND
External capacitor from BCT to GND for
12 BCT
COMP CP SRT adjusting the BURST triangle oscillator
External resistor from BRT to GND for
13 BRT
adjusting the BURST triangle oscillator
14 DUTY Control PWM mode and BURST mode
15 STB Stand-by switch, Master/Slave selection
16 VS2 Error amplifier input④
17 IS2 Error amplifier input③
18 FB2 Error amplifier output②
19 VS1 Error amplifier input②
20 IS1 Error amplifier input①
21 FB1 Error amplifier output①
External capacitor from SS to GND for
22 SS
Soft Start Control
23 COMP Over voltage detector
24 VCC Supply voltage input
25 UVLO External Under Voltage Lock OUT
26 NB2 FET driver for 2ch
27 NA2 FET driver for 2ch
28 PGND Ground for FET drivers

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〇NOTE FOR USE

１． When designing the external circuit, including adequate margins for variation between external devices and the IC.Use

adequate margins for steady state and transient characteristics.

２． Recommended Operating Range

The circuit functionality is guaranteed within of ambient temperature operation range as long as it is within recommended

operating range. The standard electrical characteristic values cannot be guaranteed at other voltages in the operating

ranges, however, the variation will be small.

３． Mounting Failures

Mounting failures, such as misdirection or miscounts, may harm the device.

４． Electromagnetic Fields

A strong electromagnetic field may cause the IC to malfunction.

５. The GND pin should be the location within ±0.3V compared with the PGND pin

６． BD9896FV has the short circuit protection with Thermal Shut Down System. When STB or Vcc pin re-supplied, They enables

to cancel the latch. If It rise the temperature of the chip more than 170℃(TYP), It make the external FET OFF

７． Absolute maximum ratings are those values that, if exceeded, may cause the life of a device to become significantly

shortened. Moreover, the exact failure mode caused by short or open is not defined. Physical countermeasures, such

as a fuse, need to be considered when using a device beyond its maximum ratings.

８． About the external FET, the parasitic Capacitor may cause the gate voltage to change, when the drain voltage is switching.

Make sure to leave adequate margin for this IC variation.

９． On operating Slow Start Control (SS is less than 2.2V), It does not operate Timer Latch.

１０． By STB voltage, BD9896FV is changed to 3 states. Therefore, do not input STB pin voltage between one state and the

other state (0.8～1.8, 2.25～2.55).

１１．The pin connected a connector need to connect to the resistor for electrical surge destruction.
１２．This IC is a monolithic IC which (as shown is Fig-1)has P+ substrate and between the various pins. A P-N junction
is formed from this P layer of each pin. For example, the relation between each potential is as follows,
○(When GND > PinB and GND > PinA, the P-N junction operates as a parasitic diode.)

○(When PinB > GND > PinA, the P-N junction operates as a parasitic transistor.)

Parasitic diodes can occur inevitably in the structure of the IC. The operation of parasitic diodes can result in mutual

interference among circuits as well as operation faults and physical damage. Accordingly you must not use methods by

which parasitic diodes operate, such as applying a voltage that is lower than the GND(P substrate)voltage to an input
Resistance Transistor (NPN)
pin.
(PinA) B
(PinB)
C E
Ｃ
GND
N
P＋ P P＋
N
Ｎ N N
P substrate Ｎ P substrate
GND GND
Parasitic diode Parasitic diode

(PinB)
(PinA)
B CＣ
Ｂ
Parasitic diode EＥ
GND
GND
Other adjacent components Parasitic diode

Fig-1 Simplified structure of a Bipolar IC

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