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TL061, TL061A, TL061B

TL062, TL062A, TL062B, TL064, TL064A, TL064B
SLOS078L – NOVEMBER 1978 – REVISED MAY 2015

TL06xx Low-Power JFET-Input Operational Amplifiers

1 Features 2 Applications
•
1 Very Low Power Consumption • Tablets
• Typical Supply Current: 200 μA (Per Amplifier) • White goods
• Wide Common-Mode and Differential Voltage • Personal electronics
Ranges • Computers
• Low Input Bias and Offset Currents
• Common-Mode Input Voltage Range 3 Description
Includes VCC+ The JFET-input operational amplifiers of the TL06x
• Output Short-Circuit Protection series are designed as low-power versions of the
TL08x series amplifiers. They feature high input
• High Input Impedance: JFET-Input Stage impedance, wide bandwidth, high slew rate, and low
• Internal Frequency Compensation input offset and input bias currents. The TL06x series
• Latch-Up-Free Operation features the same terminal assignments as the TL07x
and TL08x series.
• High Slew Rate: 3.5 V/μs Typical
• On Products Compliant to MIL-PRF-38535, Device Information(1)
All Parameters Are Tested Unless Otherwise PART NUMBER PACKAGE BODY SIZE (NOM)
Noted. On All Other Products, Production TL06xxD SOIC (14) 8.65 mm × 3.91 mm
Processing Does Not Necessarily Include Testing
TL06xxJ CDIP (14) 19.56 mm × 6.92 mm
of All Parameters.
TL06xxN PDIP (14) 19.30 mm × 6.35 mm
TL06xxNS SO (14) 10.30 mm × 5.30 mm
TL06xxPW TSSOP (14) 5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.

Schematic Symbol

IN+ +
OUT
IN− −

OFFSET N1 OFFSET N2
Offset Null/Compensation
TL061 Only

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TL061, TL061A, TL061B
TL062, TL062A, TL062B, TL064, TL064A, TL064B
SLOS078L – NOVEMBER 1978 – REVISED MAY 2015 www.ti.com

Table of Contents
1 Features .................................................................. 1 8.2 Functional Block Diagram ....................................... 14
2 Applications ........................................................... 1 8.3 Feature Description................................................. 14
3 Description ............................................................. 1 8.4 Device Functional Modes........................................ 15
4 Revision History..................................................... 2 9 Applications and Implementation ...................... 16
9.1 Application Information............................................ 16
5 Pin Configuration and Functions ......................... 3
9.2 Typical Applications ................................................ 16
6 Specifications......................................................... 4
9.3 System Examples ................................................... 17
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 5 10 Power Supply Recommendations ..................... 19
6.3 Recommended Operating Conditions....................... 5 11 Layout................................................................... 20
6.4 Thermal Information - 8 Pins..................................... 5 11.1 Layout Guidelines ................................................. 20
6.5 Thermal Information - 14 Pins................................... 5 11.2 Layout Examples................................................... 20
6.6 Thermal Information - 20 Pins................................... 6 12 Device and Documentation Support ................. 21
6.7 Electrical Characteristics for TL06xC and TL06xxC . 6 12.1 Documentation Support ........................................ 21
6.8 Electrical Characteristics for TL06xxC and TL06xI ... 7 12.2 Related Links ........................................................ 21
6.9 Electrical Characteristics for TL06xM and TL064M .. 7 12.3 Community Resources.......................................... 21
6.10 Operating Characteristics........................................ 8 12.4 Trademarks ........................................................... 21
6.11 Typical Characteristics ............................................ 9 12.5 Electrostatic Discharge Caution ............................ 21
7 Parameter Measurement Information ................ 13 12.6 Glossary ................................................................ 21
8 Detailed Description ............................................ 14 13 Mechanical, Packaging, and Orderable
8.1 Overview ................................................................. 14
Information ........................................................... 21

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision K (January 2014) to Revision L Page

• Added Applications ................................................................................................................................................................. 1

• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1

Changes from Revision J (September 2004) to Revision K Page

• Updated document to new TI data sheet format - no specification changes. ........................................................................ 1

• Deleted Ordering Information table. ....................................................................................................................................... 1
• Updated Features with Military Disclaimer. ............................................................................................................................ 1

2 Submit Documentation Feedback Copyright © 1978–2015, Texas Instruments Incorporated

Product Folder Links: TL061 TL061A TL061B TL062 TL062A TL062B TL064 TL064A TL064B
 TL061, TL061A, TL061B
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5 Pin Configuration and Functions

TL061x D, P, and PS Package

8-Pin SOIC, PDIP, and SO TL062 FK Package
Top View 20-Pin LCCC
Top View

1OUT

VCC+
OFFSET N1 1 8 NC

NC

NC

NC
IN− 2 7 VCC+
IN+ 3 6 OUT
VCC− 4 5 OFFSET N2 3 2 1 20 19
NC 4 18 NC
1IN− 5 17 2OUT
NC 6 16 NC
TL062x D, JG, P, PS, and PW Package 1IN+ 7 15 2IN−
8-Pin SOIC, CDIP, PDIP, SO, and TSSOP
Top View NC 8 14 NC
9 10 11 12 13

1OUT 1 8 VCC+

VCC−

2IN+
NC

NC

NC
1IN− 2 7 2OUT
1IN+ 3 6 2IN−
VCC− 4 5 2IN+
TL064 FK Package
20-Pin LCCC
Top View
TL064x D, J, N, NS, PW, and W Package

1OUT

4OUT
1IN−

4IN−
14-Pin SOIC, CDIP, PDIP, SO, TSSOP and CFP

NC
Top View

1OUT 1 14 4OUT 3 2 1 20 19
1IN+ 4 18 4IN+
1IN− 2 13 4IN− NC
NC 5 17
1IN+ 3 12 4IN+ VCC−
VCC+ 6 16
VCC+ 4 11 VCC− NC
NC 7 15
2IN+ 5 10 3IN+ 3IN+
2IN+ 8 14
2IN− 6 9 3IN− 9 10 11 12 13
2OUT 7 8 3OUT
2IN−

3IN−
2OUT
NC
3OUT

Pin Functions
PIN
TL061 TL062 TL064
TYPE DESCRIPTION
NAME D, JG, P, D, J, N, NS,
D, P, PS FK FK
PS, PW PW, W
1IN– — 2 5 2 3 I Negative input
1IN+ — 3 7 3 4 I Positive input
1OUT — 1 2 1 2 O Output
2IN– — 6 15 6 9 I Negative input
2IN+ — 5 12 5 8 I Positive input
2OUT — 7 17 7 10 O Output
3IN– — — — 9 13 I Negative input
3IN+ — — — 10 14 I Positive input
3OUT — — — 8 12 O Output
4IN– — — — 13 19 I Negative input
4IN+ — — — 12 18 I Positive input
4OUT — — — 14 20 O Output
IN– 2 — — — — I Negative input

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Pin Functions (continued)

PIN
TL061 TL062 TL064
TYPE DESCRIPTION
NAME D, JG, P, D, J, N, NS,
D, P, PS FK FK
PS, PW PW, W
IN+ 3 — — — — I Positive input
1
1
3
4
5
6
8
7
9
NC 8 — — — Do not connect
11
11
13
14
15
16
18
17
19
OFFSET N1 1 — — — — — Input offset adjustment
OFFSET N2 5 — — — — — Input offset adjustment
OUT 6 — — — — O Output
VCC– 4 4 10 11 16 — Power supply
VCC+ 7 8 20 4 6 — Power supply

6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VCC+ 18
Supply voltage (2) V
VCC– –18
VID Differential input voltage (3) ±30 V
VI Input voltage (2) (4) ±15 V
Duration of output short circuit (5) Unlimited
TJ Operating virtual junction temperature 150 °C
Case temperature for 60 seconds FK package 260 °C
Lead temperature 1.6 mm (1/16 inch) from
J, JG, U, or W package 300 °C
case for 60 seconds
Lead temperature 1.6 mm (1/16 inch) from
D, N, NS, P, PS, or PW package 260 °C
case for 10 seconds
Tstg Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential voltages, are with respect to the midpoint between VCC+ and VCC−.
(3) Differential voltages are at IN+, with respect to IN−.
(4) The magnitude of the input voltage must never exceed the magnitude of the supply voltage or 15 V, whichever is less.
(5) The output may be shorted to ground or to either supply. Temperature and/or supply voltages must be limited to ensure that the
dissipation rating is not exceeded.

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 TL061, TL061A, TL061B
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www.ti.com SLOS078L – NOVEMBER 1978 – REVISED MAY 2015

6.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) 2000
V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22- V
2000
C101 (2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCC+ Supply voltage 5 15 V
VCC– Supply voltage –5 –15 V
VCM Common-mode voltage VCC– + 4 VCC+ – 4 V
TL06xM –55 125
TL06xQ –40 125
TA Ambient temperature °C
TL06xI –40 85
TL06xC 0 70

6.4 Thermal Information - 8 Pins

TL06xx
THERMAL METRIC (1) D (SOIC) P (PDIP) PS (SO) PW (TSSOP) JG (CDIP) UNIT
8 PINS 8 PINS 8 PINS 8 PINS 8 PINS
RθJ Junction-to-ambient thermal
97 85 95 149 — °C/W
A resistance (2) (3)
RθJ
Junction-to-case (top) thermal
— — — — 14.5 °C/W
C(to resistance (4) (5)
p)

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(2) Maximum power dissipation is a function of TJ(max), RθJA, and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) – TA)/RθJA. Operating at the absolute maximum TJ of 150°C can affect reliability.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.
(4) Maximum power dissipation is a function of TJ(max), RθJC, and TC. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) – TC) / RθJC. Operating at the absolute maximum TJ of 150°C can affect reliability.
(5) The package thermal impedance is calculated in accordance with MIL-STD-883.

6.5 Thermal Information - 14 Pins

TL06xx
D (SOIC) N (PDIP) NS (SO) PS (SO) PW J (CDIP) W (CFP)
THERMAL METRIC (1) UNIT
(TSSOP)
14 PINS 14 PINS 14 PINS 8 PINS 14 PINS 14 PINS 14 PINS
RθJ Junction-to-ambient thermal 113
86 80 76 95 — — °C/W
A resistance (2) (3)
RθJ
Junction-to-case (top) thermal
— — — — — 15.05 14.65 °C/W
C(to resistance (2) (3)
p)

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(2) Maximum power dissipation is a function of TJ(max), RθJC, and TC. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) – TC) / RθJC. Operating at the absolute maximum TJ of 150°C can affect reliability.
(3) The package thermal impedance is calculated in accordance with MIL-STD-883.

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Product Folder Links: TL061 TL061A TL061B TL062 TL062A TL062B TL064 TL064A TL064B
TL061, TL061A, TL061B
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6.6 Thermal Information - 20 Pins

TL06xx
THERMAL METRIC (1) FK (LCCC) UNIT
20 PINS
RθJA Junction-to-ambient thermal resistance (2) (3) — °C/W
(4) (5)
RθJC(top) Junction-to-case (top) thermal resistance 5.61 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(2) Maximum power dissipation is a function of TJ(max), RθJA, and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) – TA)/RθJA. Operating at the absolute maximum TJ of 150°C can affect reliability.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.
(4) Maximum power dissipation is a function of TJ(max), RθJC, and TC. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) – TC) / RθJC. Operating at the absolute maximum TJ of 150°C can affect reliability.
(5) The package thermal impedance is calculated in accordance with MIL-STD-883.

6.7 Electrical Characteristics for TL06xC and TL06xxC

VCC± = ±15 V (unless otherwise noted)
TL061AC, TL062AC,
TL061C, TL062C, TL064C
PARAMETER TEST CONDITIONS (1) TL064AC UNIT
MIN TYP MAX MIN TYP MAX
TA = 25°C 3 15 3 6
VIO Input offset voltage VO = 0, RS = 50 Ω mV
TA = Full range 20 7.5
Temperature coefficient
αVIO VO = 0, RS = 50 Ω, TA = Full range 10 10 μV/°C
of input offset voltage
TA = 25°C 5 200 5 100 pA
IIO Input offset current VO = 0
TA = Full range 5 3 nA
TA = 25°C 30 400 30 200 pA
IIB Input bias current (2) VO = 0
TA = Full range 10 7 nA
–12 –12
Common-mode input
VICR TA = 25°C ±11 to ±11 to V
voltage range
15 15

Maximum peak output RL = 10 kΩ, TA = 25°C ±10 ±13.5 ±10 ±13.5

VOM V
voltage swing RL ≥ 10 kΩ, TA = Full range ±10 ±10

Large-signal differential VO = ±10 V, TA = 25°C 3 6 4 6

AVD V/mV
voltage amplification RL ≥ 2 kΩ TA = Full range 3 4
B1 Unity-gain bandwidth RL = 10 kΩ, TA = 25°C 1 1 MHz
ri Input resistance TA = 25°C 1012 1012 Ω
Common-mode VIC = VICRmin,
CMRR 70 86 80 86 dB
rejection ratio VO = 0, RS = 50 Ω, TA = 25°C
Supply-voltage
VCC = ±9 V to ±15 V,
kSVR rejection ratio 70 95 80 95 dB
VO = 0, RS = 50 Ω, TA = 25°C
(ΔVCC±/ΔVIO)
Total power dissipation
PD VO = 0, No load, TA = 25°C 6 7.5 6 7.5 mW
(each amplifier)
Supply current
ICC VO = 0, No load, TA = 25°C 200 250 200 250 µA
(each amplifier)
VO1/VO2 Crosstalk attenuation AVD = 100, TA = 25°C 120 120 dB

(1) All characteristics are measured under open-loop conditions with zero common-mode input voltage unless otherwise specified. Full
range for TA is 0°C to 70°C for TL06xC, TL06xAC, and TL06xBC and –40°C to 85°C for TL06xI.
(2) Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as
shown in Figure 12. Pulse techniques are used to maintain the junction temperature as close to the ambient temperature as possible.

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 TL061, TL061A, TL061B
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6.8 Electrical Characteristics for TL06xxC and TL06xI

VCC± = ±15 V (unless otherwise noted)
TL061BC, TL062BC,
TL061I, TL062I, TL064I
PARAMETER TEST CONDITIONS (1) TL064BC UNIT
MIN TYP MAX MIN TYP MAX
TA = 25°C 2 3 3 6
VIO Input offset voltage VO = 0, RS = 50 Ω mV
TA = Full range 5 9
Temperature coefficient
αVIO VO = 0, RS = 50 Ω, TA = Full range 10 10 μV/°C
of input offset voltage
TA = 25°C 5 100 5 100 pA
IIO Input offset current VO = 0
TA = Full range 3 10 nA
TA = 25°C 30 200 30 200 pA
IIB Input bias current (2) VO = 0
TA = Full range 7 20 nA
–12 –12
Common-mode input
VICR TA = 25°C ±11 to ±11 to V
voltage range
15 15

Maximum peak output RL = 10 kΩ, TA = 25°C ±10 ±13.5 ±10 ±13.5

VOM V
voltage swing RL ≥ 10 kΩ, TA = Full range ±10 ±10

Large-signal differential VO = ±10 V, TA = 25°C 4 6 4 6

AVD V/mV
voltage amplification RL ≥ 2 kΩ TA = Full range 4 4
B1 Unity-gain bandwidth RL = 10 kΩ, TA = 25°C 1 1 MHz
ri Input resistance TA = 25°C 1012 1012 Ω
Common-mode VIC = VICRmin,
CMRR 80 86 80 86 dB
rejection ratio VO = 0, RS = 50 Ω, TA = 25°C
Supply-voltage
VCC = ±9 V to ±15 V,
kSVR rejection ratio 80 95 80 95 dB
VO = 0, RS = 50 Ω, TA = 25°C
(ΔVCC±/ΔVIO)
Total power dissipation
PD VO = 0, No load, TA = 25°C 6 7.5 6 7.5 mW
(each amplifier)
Supply current
ICC VO = 0, No load, TA = 25°C 200 250 200 250 µA
(each amplifier)
VO1/VO2 Crosstalk attenuation AVD = 100, TA = 25°C 120 120 dB

(1) All characteristics are measured under open-loop conditions with zero common-mode input voltage, unless otherwise specified. Full
range for TA is 0°C to 70°C for TL06xC, TL06xAC, and TL06xBC and –40°C to 85°C for TL06xI.
(2) Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as
shown in Figure 12. Pulse techniques are used to maintain the junction temperature as close to the ambient temperature as possible.

6.9 Electrical Characteristics for TL06xM and TL064M

VCC± = ±15 V (unless otherwise noted)
TL061M, TL062M TL064M
PARAMETER TEST CONDITIONS (1) UNIT
MIN TYP MAX MIN TYP MAX
TA = 25°C 3 6 3 9
VIO Input offset voltage VO = 0, RS = 50 Ω TA = –55°C to mV
9 15
125°C
Temperature coefficient VO = 0, RS = 50 Ω,
αVIO 10 10 μV/°C
of input offset voltage TA = –55°C to 125°C
TA = 25°C 5 100 5 100 pA
IIO Input offset current VO = 0 TA = –55°C 20 (2) 20 (2)
nA
TA = 125°C 20 20
TA = 25°C 30 200 30 200 pA
IIB Input bias current (3) VO = 0 TA = –55°C 50 (2) 50 (2)
nA
TA = 125°C 50 50
–12 –12
Common-mode input
VICR TA = 25°C ±11 to ±11 to V
voltage range
15 15

(1) All characteristics are measured under open-loop conditions, with zero common-mode voltage, unless otherwise specified.
(2) This parameter is not production tested.
(3) Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as
shown in Figure 12. Pulse techniques are used to maintain the junction temperature as close to the ambient temperature as possible.
Copyright © 1978–2015, Texas Instruments Incorporated Submit Documentation Feedback 7
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Electrical Characteristics for TL06xM and TL064M (continued)

VCC± = ±15 V (unless otherwise noted)
TL061M, TL062M TL064M
PARAMETER TEST CONDITIONS (1) UNIT
MIN TYP MAX MIN TYP MAX

Maximum peak output RL = 10 kΩ, TA = 25°C ±10 ±13.5 ±10 ±13.5

VOM V
voltage swing RL ≥ 10 kΩ, TA = –55°C to 125°C ±10 ±10
TA = 25°C 4 6 4 6
Large-signal differential VO = ±10 V,
AVD TA = –55°C to V/mV
voltage amplification RL ≥ 2 kΩ 4 4
125°C
B1 Unity-gain bandwidth RL = 10 kΩ, TA = 25°C MHz
ri Input resistance TA = 25°C 12 12 Ω
10 10
Common-mode VIC = VICRmin,
CMRR 80 86 80 86 dB
rejection ratio VO = 0, RS = 50 Ω, TA = 25°C
Supply-voltage
VCC = ±9 V to ±15 V,
kSVR rejection ratio 80 95 80 95 dB
VO = 0, RS = 50 Ω, TA = 25°C
(ΔVCC±/ΔVIO)
Total power dissipation
PD VO = 0, No load, TA = 25°C 6 7.5 6 7.5 mW
(each amplifier)
Supply current
ICC VO = 0, No load, TA = 25°C 200 250 200 250 µA
(each amplifier)
VO1/VO2 Crosstalk attenuation AVD = 100, TA = 25°C 120 120 dB

6.10 Operating Characteristics

VCC± = ±15 V, TA= 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VI = 10 V, CL = 100 pF,
SR Slew rate at unity gain (1) 1.5 3.5 V/μs
RL = 10 kΩ, see Figure 16
tr Rise-time VI = 20 V, CL = 100 pF, 0.2 μs
Overshoot factor RL = 10 kΩ, see Figure 16 10%
Vn Equivalent input noise voltage RS = 20 Ω f = 1 kHz 42 nV/√Hz

(1) Slew rate at –55°C to 125°C is 0.7 V/μs min.

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6.11 Typical Characteristics

Data at high and low temperatures are applicable only within the specified operating free-air temperature ranges of the
various devices.
Table 1. Table of Graphs
FIGURE
Maximum peak output voltage versus Supply voltage Figure 1
Maximum peak output voltage versus Free-air temperature Figure 2
Maximum peak output voltage versus Load resistance Figure 3
Maximum peak output voltage versus Frequency Figure 4
Differential voltage amplification versus Free-air temperature Figure 5
Large-signal differential voltage amplification versus Frequency Figure 6
Phase shift versus Frequency Figure 6
Supply current versus Supply voltage Figure 7
Supply current versus Free-air temperature Figure 8
Total power dissipation versus Free-air temperature Figure 9
Common-mode rejection ratio versus Free-air temperature Figure 10
Normalized unity-gain bandwidth versus Free-air temperature Figure 11
Normalized slew rate versus Free-air temperature Figure 11
Normalized phase shift versus Free-air temperature Figure 11
Input bias current versus Free-air temperature Figure 12
Voltage-follower large-signal pulse response versus Time Figure 13
Output voltage versus Elapsed time Figure 14
Equivalent input noise voltage versus Frequency Figure 15

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±15 ±15

VOM − Maximum Peak Output Voltage − V

VOM − Maximum Peak Output Voltage − V

RL = 10 kΩ
±12.5 TA = 25°C ±12.5
See Figure 2

±10 ±10

±7.5 ±7.5

±5 ±5

±2.5 ±2.5
VCC± = ±15 V
RL = 10 kΩ
See Figure 2
0 0
0 2 4 6 8 10 12 14 16 −75 −50 −25 0 25 50 75 100 125
|VCC±| − Supply Voltage − V TA − Free-Air Temperature − °C
Figure 1. Maximum Peak Output Voltage vs Supply Voltage Figure 2. Maximum Peak Output Voltage vs Free-Air
Temperature
±15
VCC± = ±15 V VCC± = ±15 V
RL = 10 kΩ
VOM − Maximum Peak Output Voltage − V

VOM − Maximum Peak Output Voltage − V

TA = 25°C TA = 25°C
±12.5 See Figure 2 ±12.5 See Figure 2
VCC± = ±12 V
±10 ±10

±7.5 ±7.5

±5 ±5
VCC± = ±5 V

±2.5 ±2.5

0 0
100 200 400 700 1 k 2k 4k 7 k 10 k 1k 10 k 100 k 1M 10 M
RL − Load Resistance − Ω f − Frequency − Hz

Figure 3. Maximum Peak Output Voltage vs Load Figure 4. Maximum Peak Output Voltage vs Frequency
Resistance
10 100
VCC± = ±15 V
AVD − Differential Voltage Amplification − V/mV

VCC± = ±15 V
RL = 10 kΩ
7 Rext = 0
10 RL = 10 kΩ 0°
AVD − Large-Signal Differential
Voltage Amplification − V/mV

TA = 25°C

Phase Shift
4 1 Phase Shift 45°
(right scale)

0.1 90°

2
AVD
(left scale) 135°
0.01

1 0.001 180°
−75 −50 −25 0 25 50 75 100 125 1 10 100 1k 10 k 100 k 1M 10 M
TA − Free-Air Temperature − °C f − Frequency − Hz
Figure 5. Differential Voltage Amplification vs Free-Air Figure 6. Large-Signal Differential Voltage Amplification and
Temperature Phase Shift vs Frequency

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250 250
TA = 25°C
No Signal
No Load
200 200
ICC − Supply Current − µA

ICC − Supply Current − µA

150 150

100 100
I CC±

I CC±
50 50
VCC± = ±15 V
No Signal
No Load
0 0
0 2 4 6 8 10 12 14 16 −75
|VCC±| − Supply Voltage − V TA − Free-Air Temperature − °C

Figure 7. Supply Current vs Supply Voltage Figure 8. Supply Current vs Free-Air Temperature
30 87
VCC± = ±15 V

CMRR − Common-Mode Rejection Ratio − dB

RL = 10 kΩ
86
D − Total Power Dissipation − mW

25
TL064
VCC± = ±15 V
No Signal
20 No Load 85

15 84

TL062
10 83

TL061
PD

82
P

0 81
−75 −50 −25 0 25 50 75 100 125 −75 −50 −25 0 25 50 75 100 125
TA − Free-Air Temperature − °C TA − Free-Air Temperature − °C
Figure 9. Total Power Dissipation vs Free-Air Temperature Figure 10. All Except TL06_C Common-Mode Rejection
Ratio vs Free-Air Temperature
1.3 1.03 100
Normalized Unity-Gain Bandwidth and Slew Rate

VCC± = ±15 V
40
Unity-Gain Bandwidth 1.02
1.2
(left scale)
Phase Shift
IIB − Input Bias Current − nA

(right scale) 10
4
Normalized Phase Shift

1.1 1.01

Slew Rate
1 1 1
(left scale)
0.4
0.9 0.99
IIB

0.1

0.8 VCC± = ±15 V 0.98 0.04

RL = 10 kΩ
f = B1 for Phase Shift
0.7 0.97 0.01
−75 −50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TA − Free-Air Temperature − °C TA − Free-Air Temperature − °C

Figure 11. Normalized Unity-Gain Bandwidth, Slew Rate, Figure 12. Input Bias Current vs Free-Air Temperature
and Phase Shift vs Free-Air Temperature

Copyright © 1978–2015, Texas Instruments Incorporated Submit Documentation Feedback 11

Product Folder Links: TL061 TL061A TL061B TL062 TL062A TL062B TL064 TL064A TL064B
TL061, TL061A, TL061B
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SLOS078L – NOVEMBER 1978 – REVISED MAY 2015 www.ti.com

6 28
Input
24
4 Overshoot
Input and Output Voltages − V

20

VO − Output Voltage − mV
2
16

0 12
Output
8
−2
VCC± = ±15 V 4
RL = 10 kΩ 10%
−4 VCC± = ±15 V
CL = 100 pF 0 RL = 10 kΩ
TA = 25°C tr TA = 25°C
−4
−6
0 2 4 6 8 10 0 0.2 0.4 0.6 0.8 1 1.2 1.4
t − Time − µs t − Elapsed Time − µs
Figure 13. Voltage-Follower Large-Signal Pulse Response Figure 14. Output Voltage vs Elapsed Time
vs Time
100
VCC± = ±15 V
V n − Equivalent Input Noise Voltage − nV/ Hz

90 RS = 20 Ω
TA = 25°C
80

70

60

50

40

30

20

10

0
10 40 100 400 1 k 4 k 10 k 40 k 100 k
f − Frequency − Hz
Figure 15. Equivalent Input Noise Voltage vs Frequency

12 Submit Documentation Feedback Copyright © 1978–2015, Texas Instruments Incorporated

Product Folder Links: TL061 TL061A TL061B TL062 TL062A TL062B TL064 TL064A TL064B
 TL061, TL061A, TL061B
TL062, TL062A, TL062B, TL064, TL064A, TL064B
www.ti.com SLOS078L – NOVEMBER 1978 – REVISED MAY 2015

7 Parameter Measurement Information

OUT
VI +

CL = 100 pF RL = 2 kΩ

Figure 16. Unity-Gain Amplifier

10 kΩ

1 kΩ −
VI
OUT
+
RL CL = 100 pF

Figure 17. Gain-of-10 Inverting Amplifier

IN−
−

TL061 OUT
IN+
+ N2
N1
100 kΩ

1.5 kΩ

VCC−
Figure 18. Input Offset-Voltage Null Circuit

Copyright © 1978–2015, Texas Instruments Incorporated Submit Documentation Feedback 13

Product Folder Links: TL061 TL061A TL061B TL062 TL062A TL062B TL064 TL064A TL064B
TL061, TL061A, TL061B
TL062, TL062A, TL062B, TL064, TL064A, TL064B
SLOS078L – NOVEMBER 1978 – REVISED MAY 2015 www.ti.com

8 Detailed Description

8.1 Overview
The JFET-input operational amplifiers of the TL06x series are designed as low-power versions of the TL08x
series amplifiers. They feature high input impedance, wide bandwidth, high slew rate, and low input offset and
input bias currents. The TL06x series features the same terminal assignments as the TL07x and TL08x series.
Each of these JFET-input operational amplifiers incorporates well-matched, high-voltage JFET and bipolar
transistors in an integrated circuit.
The C-suffix devices are characterized for operation from 0°C to 70°C. The I-suffix devices are characterized for
operation from −40°C to 85°C, and the M-suffix devices are characterized for operation over the full military
temperature range of −55°C to 125°C.

8.2 Functional Block Diagram

VCC+

IN+

50 Ω
IN−

100 Ω

C1

OFFSET N1 OFFSET N2 OUT VCC−

TL061 Only
C1 = 10 pF on TL061, TL062, and TL064
Component values shown are nominal.

8.3 Feature Description

8.3.1 Common-Mode Rejection Ratio
The common-mode rejection ratio (CMRR) of an amplifier is a measure of how well the device rejects unwanted
input signals common to both input leads. It is found by taking the ratio of the change in input offset voltage to
the change in the input voltage and converting to decibels. Ideally the CMRR is infinite, but in practice, amplifiers
are designed to have it as high as possible. The CMRR of this device is 86 dB.

8.3.2 Slew Rate

The slew rate is the rate at which an operational amplifier can change its output when there is a change on the
input. These devices have a 3.5-V/μs slew rate.

14 Submit Documentation Feedback Copyright © 1978–2015, Texas Instruments Incorporated

Product Folder Links: TL061 TL061A TL061B TL062 TL062A TL062B TL064 TL064A TL064B
 TL061, TL061A, TL061B
TL062, TL062A, TL062B, TL064, TL064A, TL064B
www.ti.com SLOS078L – NOVEMBER 1978 – REVISED MAY 2015

8.4 Device Functional Modes

These devices are powered on when the supply is connected. This device can be operated as a single supply
operational amplifier or dual supply amplifier depending on the application.

Copyright © 1978–2015, Texas Instruments Incorporated Submit Documentation Feedback 15

Product Folder Links: TL061 TL061A TL061B TL062 TL062A TL062B TL064 TL064A TL064B
TL061, TL061A, TL061B
TL062, TL062A, TL062B, TL064, TL064A, TL064B
SLOS078L – NOVEMBER 1978 – REVISED MAY 2015 www.ti.com

9 Applications and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

9.1 Application Information

The TL06x series of operational amplifiers can be used in countless applications. The few applications in this
section show principles used in all applications of these parts.

9.2 Typical Applications

9.2.1 Inverting Amplifier Application
A typical application for an operational amplifier in an inverting amplifier. This amplifier takes a positive voltage
on the input, and makes it a negative voltage of the same magnitude. In the same manner, it also makes
negative voltages positive.
RF

RI Vsup+

VOUT
+
VIN
Vsup-

Figure 19. Schematic for Inverting Amplifier Application

9.2.1.1 Design Requirements

The supply voltage must be chosen such that it is larger than the input voltage range and output range. For
instance, this application will scale a signal of ±0.5 V to ±1.8 V. Setting the supply at ±12 V is sufficient to
accommodate this application.

9.2.1.2 Detailed Design Procedure

Determine the gain required by the inverting amplifier:

(1)

(2)
Once the desired gain is determined, choose a value for RI or RF. Choosing a value in the kilohm range is
desirable because the amplifier circuit will use currents in the milliamp range. This ensures the part will not draw
too much current. This example will choose 10 kΩ for RI which means 36 kΩ will be used for RF. This was
determined by Equation 3.

(3)

16 Submit Documentation Feedback Copyright © 1978–2015, Texas Instruments Incorporated

Product Folder Links: TL061 TL061A TL061B TL062 TL062A TL062B TL064 TL064A TL064B
 TL061, TL061A, TL061B
TL062, TL062A, TL062B, TL064, TL064A, TL064B
www.ti.com SLOS078L – NOVEMBER 1978 – REVISED MAY 2015

Typical Applications (continued)

9.2.1.3 Application Curve
2
VIN
1.5
VOUT
1

0.5

Volts
0

-0.5

-1

-1.5

-2
0 0.5 1 1.5 2
Time (ms)

Figure 20. Input and Output Voltages of the Inverting Amplifier

9.3 System Examples

9.3.1 General Applications
VCC+ RF = 100 kΩ
− 10 kΩ 10 kΩ
0.1% 0.1%
100 kΩ +
TL064 15 V
Input A VCC+ 3.3 kΩ − Output
VCC− −

Output
TL061
TL064
100 kΩ +
CF = 3.3 µF 1 kΩ
+
VCC+ VCC+ 1 MΩ
VCC− −15 V
Input B + −
100 kΩ
TL064 TL064 100 kΩ
−
10 kΩ 10 kΩ + 3.3 kΩ
0.1% 0.1%
1 9.1 kΩ
VCC− VCC− f=
2π ´ RF ´ CF

Figure 21. Instrumentation Amplifier Figure 22. 0.5-Hz Square-Wave Oscillator

VCC+ − VCC+
1 MΩ
− TL064 Output A
VCC+ +

R1 TL061 −
+
Input Output 1 µF TL064 − VCC+
R2 Input
+
Output B
C3 VCC−
TL064
100 kΩ
+

100 kΩ
VCC+
VCC+
R1 = R2 = 2 ´ R3 = 1.5 MΩ −
R3 100 µF 100 kΩ
Output C
C1 C2 C3 TL064
C1 = C2 = = 110 pF +
2
1
fO = = 1 kHz
2π ´ R1´ C1
Figure 23. High-Q Notch Filter Figure 24. Audio-Distribution Amplifier

Copyright © 1978–2015, Texas Instruments Incorporated Submit Documentation Feedback 17

Product Folder Links: TL061 TL061A TL061B TL062 TL062A TL062B TL064 TL064A TL064B
TL061, TL061A, TL061B
TL062, TL062A, TL062B, TL064, TL064A, TL064B
SLOS078L – NOVEMBER 1978 – REVISED MAY 2015 www.ti.com

System Examples (continued)

15 V VCC+

10 kΩ 10 kΩ
0.1 µF
10 kΩ 10 kΩ
+
10 kΩ 1 MΩ
TIL601 100 pF Output
−
TL061
10 kΩ − TL061 Output
50 Ω
10 kΩ +
10 kΩ N2
5 kΩ N1
0.1 µF 10 kΩ
250 kΩ
−15 V

Figure 25. Low-Level Light Detector Preamplifier Figure 26. AC Amplifier

10 kΩ 100 kΩ 1 kΩ

IN+ +
0.1 µF 0.06 µF 0.06 µF
+ 1 µF TL062 Output
TL061
47 kΩ − 10 kΩ −
1.2 MΩ 100 kΩ 0.002 µF 50 kΩ 100 kΩ
2.7 kΩ

100 kΩ 10 kΩ
100 kΩ 270 Ω 0.003 µF 0.001 µF

+
50 kΩ 0.02 µF
20 µF
1 kΩ
1 kΩ

100 kΩ
−
TL062
IN− +

Figure 27. Microphone Preamplifier With Tone Figure 28. Instrumentation Amplifier
Control

18 Submit Documentation Feedback Copyright © 1978–2015, Texas Instruments Incorporated

Product Folder Links: TL061 TL061A TL061B TL062 TL062A TL062B TL064 TL064A TL064B
 TL061, TL061A, TL061B
TL062, TL062A, TL062B, TL064, TL064A, TL064B
www.ti.com SLOS078L – NOVEMBER 1978 – REVISED MAY 2015

System Examples (continued)

IC PREAMPLIFIER RESPONSE CHARACTERISTICS
25
Max Bass
20 Max
Treble
VCC± = ±15 V
15
TA = 25°C

Voltage Amplification − dB
10

−5

−10

−15

−20 Min
Min Bass Treble
−25
20 40 100 200 400 1k 2k 4k 10 k 20 k
f − Frequency − Hz
220 kΩ

0.00375 µF 0.003 µF
10 kΩ
0.03 µF
0.01 µF 27 kΩ
MIN MIN
100 kΩ 100 kΩ
VCC+ Bass Treble VCC+
MAX 10 kΩ 3.3 kΩ MAX
+ +
100 Ω
1 µF TL062 0.03 µF TL062 Output
Input − −

VCC− 0.003 µF VCC−

100 Ω 10 kΩ
Balance
10 pF 10 pF
75 µF 5 kΩ +
+ 47 kΩ
Gain 68 kΩ
50 pF 47 µF

Figure 29. IC Preamplifier

10 Power Supply Recommendations

CAUTION
Supply voltages larger than 36 V for a single supply, or outside the range of ±18 V for
a dual supply can permanently damage the device (see the Absolute Maximum
Ratings).

Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high
impedance power supplies. For more detailed information on bypass capacitor placement, refer to the Layout.

Copyright © 1978–2015, Texas Instruments Incorporated Submit Documentation Feedback 19

Product Folder Links: TL061 TL061A TL061B TL062 TL062A TL062B TL064 TL064A TL064B
TL061, TL061A, TL061B
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SLOS078L – NOVEMBER 1978 – REVISED MAY 2015 www.ti.com

11 Layout

11.1 Layout Guidelines

For best operational performance of the device, use good PCB layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole, as well as the
operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low impedance
power sources local to the analog circuitry.
– Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single
supply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds, paying attention to the flow of the ground current. For more detailed information, refer to
Circuit Board Layout Techniques, (SLOA089).
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If
it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as
opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible. Keeping RF and RG close to the inverting
input minimizes parasitic capacitance, as shown in Layout Examples.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.

11.2 Layout Examples

RIN
VIN +
VOUT
RG
RF

Figure 30. Operational Amplifier Schematic for Noninverting Configuration

Place components close to

device and to each other to
reduce parasitic errors
Run the input traces as far
away from the supply lines RF
as possible
NC NC VS+
Use low-ESR, ceramic
RG bypass capacitor
GND IN1í VCC+

VIN IN1+ OUT

RIN
VCCí NC GND
Only needed for
dual-supply
operation
GND VS-
(or GND for single supply) VOUT Ground (GND) plane on another layer

Figure 31. Operational Amplifier Board Layout for Noninverting Configuration

20 Submit Documentation Feedback Copyright © 1978–2015, Texas Instruments Incorporated

Product Folder Links: TL061 TL061A TL061B TL062 TL062A TL062B TL064 TL064A TL064B
 TL061, TL061A, TL061B
TL062, TL062A, TL062B, TL064, TL064A, TL064B
www.ti.com SLOS078L – NOVEMBER 1978 – REVISED MAY 2015

12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation
For related documentation, see the following:
Circuit Board Layout Techniques, SLOA089

12.2 Related Links

The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.

Table 2. Related Links

TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY
DOCUMENTS SOFTWARE COMMUNITY
TL061 Click here Click here Click here Click here Click here
TL061A Click here Click here Click here Click here Click here
TL061B Click here Click here Click here Click here Click here
TL062 Click here Click here Click here Click here Click here
TL062A Click here Click here Click here Click here Click here
TL062B Click here Click here Click here Click here Click here
TL064 Click here Click here Click here Click here Click here
TL064A Click here Click here Click here Click here Click here
TL064B Click here Click here Click here Click here Click here

12.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

12.4 Trademarks
E2E is a trademark of Texas Instruments.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.

Copyright © 1978–2015, Texas Instruments Incorporated Submit Documentation Feedback 21

Product Folder Links: TL061 TL061A TL061B TL062 TL062A TL062B TL064 TL064A TL064B
 PACKAGE OPTION ADDENDUM

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

81023022A ACTIVE LCCC FK 20 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 81023022A Samples
& Green TL062MFKB
8102302PA ACTIVE CDIP JG 8 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 8102302PA Samples
& Green TL062M
81023032A ACTIVE LCCC FK 20 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 81023032A Samples
& Green TL064MFKB
8102303CA ACTIVE CDIP J 14 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 8102303CA Samples
& Green TL064MJB
8102303DA ACTIVE CFP W 14 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 8102303DA Samples
& Green TL064MWB
TL061ACD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 061AC Samples

TL061ACDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 061AC Samples

TL061ACP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TL061ACP Samples

TL061BCP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TL061BCP Samples

TL061BCPE4 ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TL061BCP Samples

TL061CD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL061C Samples

TL061CDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL061C Samples

TL061CP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TL061CP Samples

TL061CPSR ACTIVE SO PS 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 T061 Samples

TL061ID ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TL061I Samples

TL061IDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TL061I Samples

TL061IDRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TL061I Samples

TL061IP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 TL061IP Samples

TL061IPE4 ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 TL061IP Samples

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 14-Oct-2022

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

TL062ACD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 062AC Samples

TL062ACDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 062AC Samples

TL062ACDRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 062AC Samples

TL062ACP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TL062ACP Samples

TL062ACPSR ACTIVE SO PS 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 T062A Samples

TL062BCD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 062BC Samples

TL062BCDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 062BC Samples

TL062BCP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TL062BCP Samples

TL062CD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL062C Samples

TL062CDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL062C Samples

TL062CDRE4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL062C Samples

TL062CDRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL062C Samples

TL062CP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TL062CP Samples

TL062CPE4 ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TL062CP Samples

TL062CPS ACTIVE SO PS 8 80 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 T062 Samples

TL062CPSR ACTIVE SO PS 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 T062 Samples

TL062CPW ACTIVE TSSOP PW 8 150 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 T062 Samples

TL062CPWR ACTIVE TSSOP PW 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 T062 Samples

TL062CPWRG4 ACTIVE TSSOP PW 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 T062 Samples

TL062ID ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TL062I Samples

TL062IDG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TL062I Samples

Addendum-Page 2
 PACKAGE OPTION ADDENDUM

www.ti.com 14-Oct-2022

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

TL062IDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TL062I Samples

TL062IDRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TL062I Samples

TL062IP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 TL062IP Samples

TL062IPWR ACTIVE TSSOP PW 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 Z062 Samples

TL062IPWRG4 ACTIVE TSSOP PW 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 Z062 Samples

TL062MFKB ACTIVE LCCC FK 20 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 81023022A Samples
& Green TL062MFKB
TL062MJG ACTIVE CDIP JG 8 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 TL062MJG Samples
& Green
TL062MJGB ACTIVE CDIP JG 8 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 8102302PA Samples
& Green TL062M
TL064ACD ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL064AC Samples

TL064ACDR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL064AC Samples

TL064ACN ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TL064ACN Samples

TL064BCD ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL064BC Samples

TL064BCDG4 ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL064BC Samples

TL064BCDR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL064BC Samples

TL064BCN ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TL064BCN Samples

TL064CD ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL064C Samples

TL064CDR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL064C Samples

TL064CN ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TL064CN Samples

TL064CNSR ACTIVE SO NS 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL064 Samples

TL064CPW ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 T064 Samples

Addendum-Page 3
 PACKAGE OPTION ADDENDUM

www.ti.com 14-Oct-2022

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

TL064CPWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 T064 Samples

TL064ID ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TL064I Samples

TL064IDG4 ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TL064I Samples

TL064IDR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 TL064I Samples

TL064IDRG4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TL064I Samples

TL064IN ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 TL064IN Samples

TL064INE4 ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 TL064IN Samples

TL064INS ACTIVE SO NS 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TL064I Samples

TL064INSR ACTIVE SO NS 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TL064I Samples

TL064IPWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 Z064 Samples

TL064MFKB ACTIVE LCCC FK 20 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 81023032A Samples
& Green TL064MFKB
TL064MJ ACTIVE CDIP J 14 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 TL064MJ Samples
& Green
TL064MJB ACTIVE CDIP J 14 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 8102303CA Samples
& Green TL064MJB
TL064MWB ACTIVE CFP W 14 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 8102303DA Samples
& Green TL064MWB

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Addendum-Page 4
 PACKAGE OPTION ADDENDUM

www.ti.com 14-Oct-2022

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TL062, TL062M, TL064, TL064M :

• Catalog : TL062, TL064

• Military : TL062M, TL064M

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

• Military - QML certified for Military and Defense Applications

Addendum-Page 5
 PACKAGE MATERIALS INFORMATION

www.ti.com 19-Mar-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TL061ACDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL061CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL061CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL061CPSR SO PS 8 2000 330.0 16.4 8.35 6.6 2.4 12.0 16.0 Q1
TL061IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL061IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL062ACDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL062ACPSR SO PS 8 2000 330.0 16.4 8.35 6.6 2.4 12.0 16.0 Q1
TL062BCDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL062CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL062CPSR SO PS 8 2000 330.0 16.4 8.35 6.6 2.4 12.0 16.0 Q1
TL062CPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
TL062CPWRG4 TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
TL062IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL062IPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
TL064ACDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 19-Mar-2023

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1

Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TL064BCDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
TL064CDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
TL064CNSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
TL064CPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
TL064IDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
TL064IDRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
TL064INSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
TL064IPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 19-Mar-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TL061ACDR SOIC D 8 2500 340.5 336.1 25.0
TL061CDR SOIC D 8 2500 340.5 336.1 25.0
TL061CDR SOIC D 8 2500 356.0 356.0 35.0
TL061CPSR SO PS 8 2000 356.0 356.0 35.0
TL061IDR SOIC D 8 2500 340.5 336.1 25.0
TL061IDR SOIC D 8 2500 356.0 356.0 35.0
TL062ACDR SOIC D 8 2500 340.5 336.1 25.0
TL062ACPSR SO PS 8 2000 356.0 356.0 35.0
TL062BCDR SOIC D 8 2500 340.5 336.1 25.0
TL062CDR SOIC D 8 2500 340.5 336.1 25.0
TL062CPSR SO PS 8 2000 356.0 356.0 35.0
TL062CPWR TSSOP PW 8 2000 356.0 356.0 35.0
TL062CPWRG4 TSSOP PW 8 2000 356.0 356.0 35.0
TL062IDR SOIC D 8 2500 340.5 336.1 25.0
TL062IPWR TSSOP PW 8 2000 356.0 356.0 35.0
TL064ACDR SOIC D 14 2500 356.0 356.0 35.0
TL064BCDR SOIC D 14 2500 356.0 356.0 35.0
TL064CDR SOIC D 14 2500 356.0 356.0 35.0

Pack Materials-Page 3
 PACKAGE MATERIALS INFORMATION

www.ti.com 19-Mar-2023

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TL064CNSR SO NS 14 2000 367.0 367.0 38.0
TL064CPWR TSSOP PW 14 2000 356.0 356.0 35.0
TL064IDR SOIC D 14 2500 356.0 356.0 35.0
TL064IDRG4 SOIC D 14 2500 356.0 356.0 35.0
TL064INSR SO NS 14 2000 356.0 356.0 35.0
TL064IPWR TSSOP PW 14 2000 356.0 356.0 35.0

Pack Materials-Page 4
 PACKAGE MATERIALS INFORMATION

www.ti.com 19-Mar-2023

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
81023022A FK LCCC 20 1 506.98 12.06 2030 NA
81023032A FK LCCC 20 1 506.98 12.06 2030 NA
8102303DA W CFP 14 1 506.98 26.16 6220 NA
TL061ACD D SOIC 8 75 507 8 3940 4.32
TL061ACP P PDIP 8 50 506 13.97 11230 4.32
TL061BCP P PDIP 8 50 506 13.97 11230 4.32
TL061BCPE4 P PDIP 8 50 506 13.97 11230 4.32
TL061CD D SOIC 8 75 507 8 3940 4.32
TL061CD D SOIC 8 75 506.6 8 3940 4.32
TL061CP P PDIP 8 50 506 13.97 11230 4.32
TL061ID D SOIC 8 75 506.6 8 3940 4.32
TL061ID D SOIC 8 75 507 8 3940 4.32
TL061IP P PDIP 8 50 506 13.97 11230 4.32
TL061IPE4 P PDIP 8 50 506 13.97 11230 4.32
TL062ACD D SOIC 8 75 507 8 3940 4.32
TL062ACP P PDIP 8 50 506 13.97 11230 4.32
TL062BCD D SOIC 8 75 507 8 3940 4.32
TL062BCP P PDIP 8 50 506 13.97 11230 4.32
TL062CD D SOIC 8 75 506.6 8 3940 4.32
TL062CD D SOIC 8 75 507 8 3940 4.32
TL062CP P PDIP 8 50 506 13.97 11230 4.32
TL062CPE4 P PDIP 8 50 506 13.97 11230 4.32
TL062CPS PS SOP 8 80 530 10.5 4000 4.1
TL062CPW PW TSSOP 8 150 530 10.2 3600 3.5
TL062ID D SOIC 8 75 506.6 8 3940 4.32
TL062ID D SOIC 8 75 507 8 3940 4.32
TL062IDG4 D SOIC 8 75 507 8 3940 4.32
TL062IDG4 D SOIC 8 75 506.6 8 3940 4.32
TL062IP P PDIP 8 50 506 13.97 11230 4.32

Pack Materials-Page 5
 PACKAGE MATERIALS INFORMATION

www.ti.com 19-Mar-2023

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
TL062MFKB FK LCCC 20 1 506.98 12.06 2030 NA
TL064ACD D SOIC 14 50 506.6 8 3940 4.32
TL064ACN N PDIP 14 25 506 13.97 11230 4.32
TL064BCD D SOIC 14 50 506.6 8 3940 4.32
TL064BCDG4 D SOIC 14 50 506.6 8 3940 4.32
TL064BCN N PDIP 14 25 506 13.97 11230 4.32
TL064CD D SOIC 14 50 506.6 8 3940 4.32
TL064CN N PDIP 14 25 506 13.97 11230 4.32
TL064CPW PW TSSOP 14 90 530 10.2 3600 3.5
TL064ID D SOIC 14 50 506.6 8 3940 4.32
TL064IDG4 D SOIC 14 50 506.6 8 3940 4.32
TL064IN N PDIP 14 25 506 13.97 11230 4.32
TL064INE4 N PDIP 14 25 506 13.97 11230 4.32
TL064INS NS SOP 14 50 530 10.5 4000 4.1
TL064MFKB FK LCCC 20 1 506.98 12.06 2030 NA
TL064MWB W CFP 14 1 506.98 26.16 6220 NA

Pack Materials-Page 6
 GENERIC PACKAGE VIEW
FK 20 LCCC - 2.03 mm max height
8.89 x 8.89, 1.27 mm pitch LEADLESS CERAMIC CHIP CARRIER

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4229370\/A\

www.ti.com
 PACKAGE OUTLINE
J0014A SCALE 0.900
CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE

PIN 1 ID A 4X .005 MIN

(OPTIONAL) [0.13] .015-.060 TYP
[0.38-1.52]

1
14
12X .100
[2.54] 14X .014-.026
14X .045-.065 [0.36-0.66]
[1.15-1.65]
.010 [0.25] C A B

.754-.785
[19.15-19.94]

7 8

B .245-.283 .2 MAX TYP .13 MIN TYP

[6.22-7.19] [5.08] [3.3]

C SEATING PLANE

.308-.314
[7.83-7.97]
AT GAGE PLANE

.015 GAGE PLANE

[0.38]

0 -15 14X .008-.014

TYP [0.2-0.36]

4214771/A 05/2017

NOTES:

1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for
reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermitically sealed with a ceramic lid using glass frit.
4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only.
5. Falls within MIL-STD-1835 and GDIP1-T14.

www.ti.com
 EXAMPLE BOARD LAYOUT
J0014A CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE

(.300 ) TYP
[7.62] SEE DETAIL B
SEE DETAIL A

1 14

12X (.100 )
[2.54]

SYMM

14X ( .039)
[1]

7 8

SYMM

LAND PATTERN EXAMPLE

NON-SOLDER MASK DEFINED
SCALE: 5X

.002 MAX (.063)

[0.05] [1.6]
ALL AROUND METAL
( .063)
SOLDER MASK [1.6]
OPENING

METAL

SOLDER MASK .002 MAX

(R.002 ) TYP [0.05]
OPENING
[0.05] ALL AROUND
DETAIL A DETAIL B
SCALE: 15X 13X, SCALE: 15X

4214771/A 05/2017

www.ti.com
 PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1

.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]

4X (0 -15 )

4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4

.005-.010 TYP
[0.13-0.25]

4X (0 -15 )

SEE DETAIL A
.010
[0.25]

.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.

www.ti.com
 EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X

SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK

EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55] SYMM

1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 MECHANICAL DATA

MCER001A – JANUARY 1995 – REVISED JANUARY 1997

JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE

0.400 (10,16)
0.355 (9,00)

8 5

0.280 (7,11)
0.245 (6,22)

1 4
0.065 (1,65)
0.045 (1,14)

0.063 (1,60) 0.310 (7,87)

0.020 (0,51) MIN
0.015 (0,38) 0.290 (7,37)

0.200 (5,08) MAX

Seating Plane

0.130 (3,30) MIN

0.023 (0,58)
0°–15°
0.015 (0,38)
0.100 (2,54) 0.014 (0,36)
0.008 (0,20)

4040107/C 08/96

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP1-T8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 PACKAGE OUTLINE
PW0008A SCALE 2.800
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

C
6.6 SEATING PLANE
TYP
6.2

A PIN 1 ID 0.1 C
AREA
6X 0.65
8
1

3.1 2X
2.9
NOTE 3 1.95

4
5
0.30
8X
0.19
4.5 1.2 MAX
B 0.1 C A B
4.3
NOTE 4

(0.15) TYP
SEE DETAIL A

0.25
GAGE PLANE

0.75 0.15
0 -8 0.05
0.50

DETAIL A
TYPICAL

4221848/A 02/2015

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153, variation AA.

www.ti.com
 EXAMPLE BOARD LAYOUT
PW0008A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

8X (1.5)
8X (0.45) SYMM
(R0.05)
1 TYP
8

SYMM

6X (0.65)
5
4

(5.8)

LAND PATTERN EXAMPLE

SCALE:10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL OPENING
OPENING SOLDER MASK

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

NOT TO SCALE

4221848/A 02/2015
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
PW0008A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

8X (1.5)
SYMM (R0.05) TYP
8X (0.45)
1
8

SYMM

6X (0.65)
5
4

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:10X

4221848/A 02/2015
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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