CRE Module IP

User Guide

FPGA-IPUG-02067-1.3

December 2022
CRE Module IP
User Guide

Disclaimers
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products for any particular purpose. All information herein is provided AS IS, with all faults and associated risk the responsibility entirely of the Buyer.
Buyer shall not rely on any data and performance specifications or parameters provided herein. Products sold by Lattice have been subject to limited
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products should be used in conjunction with mission- or safety-critical or any other application in which the failure of Lattice’s product could create a
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proprietary to Lattice Semiconductor, and Lattice reserves the right to make any changes to the information in this document or to any products at
any time without notice.

© 2020-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

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Contents
Acronyms in This Document ................................................................................................................................................. 5
1. Introduction .................................................................................................................................................................. 6
2. Functional Description .................................................................................................................................................. 7
2.1. Block Diagram ..................................................................................................................................................... 7
2.2. Security Functions and Features ......................................................................................................................... 7
2.2.1. Secure Hash Algorithm (SHA-256) .................................................................................................................. 7
2.2.2. Advance Encryption Standard (AES-128/256) ................................................................................................ 7
2.2.3. True Random Number Generation................................................................................................................. 7
2.2.4. Differential Power Analysis (DPA) Mitigation................................................................................................. 8
2.2.4.1. Clock Randomization.............................................................................................................................. 8
2.2.4.2. Random Noise Generation ..................................................................................................................... 8
2.3. Functional Overview ........................................................................................................................................... 8
2.3.1. LMMI Interface ............................................................................................................................................... 8
2.3.2. LMMI + FIFO Interface (Generic Interface) .................................................................................................... 8
2.3.3. AHB-Lite Interface .......................................................................................................................................... 8
2.3.4. APB Interface .................................................................................................................................................. 8
2.4. Signal Descriptions .............................................................................................................................................. 9
2.5. Attribute Summary............................................................................................................................................ 10
2.6. Register Map ..................................................................................................................................................... 11
2.7. CRE Function Access .......................................................................................................................................... 13
2.8. CRE Timing Diagrams ........................................................................................................................................ 20
2.9. Interface Limitations ......................................................................................................................................... 21
3. Getting Started ........................................................................................................................................................... 22
3.1. Generated Files and Top Level Directory Structure .......................................................................................... 23
3.2. Instantiating the Module .................................................................................................................................. 24
3.3. Running Functional Simulation ......................................................................................................................... 24
Appendix A. Resource Utilization ....................................................................................................................................... 29
References .......................................................................................................................................................................... 30
Technical Support Assistance ............................................................................................................................................. 31
Revision History .................................................................................................................................................................. 32

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Figures
Figure 2.1. CRE Module Block Diagram.................................................................................................................................7
Figure 2.2. SHA-256 Hash Done on Size N-Bytes Message .................................................................................................20
Figure 3.1. IP on Local, with CRE Selected Under Architecture ..........................................................................................22
Figure 3.2. Module / IP Block Wizard .................................................................................................................................22
Figure 3.3. IP Structure .......................................................................................................................................................23
Figure 3.4. IP Testbench Block Diagram..............................................................................................................................24
Figure 3.5. Adding the Simulation File ................................................................................................................................25
Figure 3.6. Simulation Wizard .............................................................................................................................................25
Figure 3.7. File List ..............................................................................................................................................................26
Figure 3.8. Parse HDL Files ..................................................................................................................................................26
Figure 3.9. Simulation Wizard Summary.............................................................................................................................27
Figure 3.10. Active-HDL Simulation Start ............................................................................................................................27
Figure 3.11. Active-HDL Simulation Finished ......................................................................................................................28

Tables
Table 2.1 CRE Module Ports..................................................................................................................................................9
Table 2.2. CRE Module Parameters ....................................................................................................................................10
Table 2.3. CRE Instruction Register Map.............................................................................................................................11
Table 2.4. CRE Data Register Map ......................................................................................................................................12
Table 2.5. SHA Message Generation Procedure (DATA_SOURCE = bus) ............................................................................13
Table 2.6. SHA Message Generation Procedure (DATA_SOURCE = FIFO)...........................................................................14
Table 2.7. HMAC-SHA Message Generation Procedure......................................................................................................14
Table 2.8. AES Encryption Procedure (DATA_SOURCE = bus).............................................................................................15
Table 2.9. AES Decryption Procedure (DATA_SOURCE = bus) ............................................................................................16
Table 2.10. AES Encryption Procedure (DATA_SOURCE = FIFO) .........................................................................................17
Table 2.11. AES Decryption Procedure (DATA_SOURCE = FIFO).........................................................................................18
Table 2.12. AES-Key Size Change (128-bit to 256-bit).........................................................................................................19
Table 2.13. True Random Number Generator Procedure ..................................................................................................19
Table 2.14. DPA Feature Access ..........................................................................................................................................19
Table 2.15. CRE Interface Limitations .................................................................................................................................21
Table 3.1 CRE Generated File Description ..........................................................................................................................23
Table A.1. Resource Utilization1 (LIFCL) ..............................................................................................................................29
Table A.2. Resource Utilization1 (LFD2NX) ..........................................................................................................................29
Table A.3. Resource Utilization1 (LFCPNX) ..........................................................................................................................29

© 2020-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
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Acronyms in This Document

A list of acronyms used in this document.
Acronym Definition
AES Advance Encryption Standard
AHB-L Advanced High Performance Bus - Lite
APB Advance Peripheral Bus
ECDSA Elliptic Curve Digital Signature Algorithm
ECIES Elliptic Curve Integrated Encryption Scheme
FIFO First-In, First-Out
HMAC Hash Based Message Authentication Code
CRE Cryptographic Engine
IP Intellectual Property
LMMI Lattice Memory Mapped Interface
LUT Lookup Table
SHA Secure Hash Algorithm
TRNG True Random Number Generation

© 2020-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

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1. Introduction
This document provides technical information about the CRE Module that is supported in Lattice FPGA devices built on the
Lattice Nexus™ platform. This aims to provide information essential for IP/System developers, Verification and Software
for integration, testing and validation. In general, design specification from RTL up to IP packaging, IP generation and
integration with Lattice Radiant software is covered in this document.
CRE stands for Cryptographic Engine. This module is based on the built-in Security Hard IP having the following features:
• Supports the following user mode security features
• High throughput Secure Hash Algorithm – 256 bits (SHA 256)
• Hash Based Message Authentication Code – HMAC-SHA
• High throughput Advance Encryption Standard – 128/256 bits (AES-128/256)
• Supports True Random Number Generation
• Supports multiple bus interfaces:
• Lattice Memory Mapped Interface (LMMI)
• LMMI + FIFO (High-speed SHA/AES)
• Advanced High Performance Bus (AHB) – Lite
• Advanced Peripheral Bus (APB)

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2. Functional Description

2.1. Block Diagram

Figure 2.1. CRE Module Block Diagram

Notes:
• The CLK and RST needs to be connected to the CRE Module. If user do not use the OSC primitive, the IP has the
option to automatically include the IP during generation to avoid encountering Synthesis Errors.
• The FIFO I/O only applies to FIFO control pins; the data pins are shared with the LMMI. The FIFO interface also
requires the information to be sent through the LMMI bus, hence the FIFO pins are only available if the LMMI
interface is also selected. More information would be discussed below.

2.2. Security Functions and Features

2.2.1. Secure Hash Algorithm (SHA-256)
The IP also features an high throughput SHA engine, for fast encryption of messages using the SHA function. The SHA
can be configured using an HMAC key with proper data for faster throughput, or through automatic handling of the
HMAC by the security engine.

2.2.2. Advance Encryption Standard (AES-128/256)

The IP can also process the encryption and decryption of messages based on the AES-128/256 standard using a
common key.

2.2.3. True Random Number Generation

The IP can also provide the true random number generator as a standalone feature for customer use cases, regardless
if related or not related to security functions.

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2.2.4. Differential Power Analysis (DPA) Mitigation

The IP includes an additional level of security to protect itself from several techniques involving power analysis. All
features can be turned on, or turned off independently.

2.2.4.1. Clock Randomization

The IP uses a 41b LFSR w/ random seed to make clock enable signal, thus effective clock frequency changes randomly.
Affects AES.

2.2.4.2. Random Noise Generation

The IP turns on random number generator, thus random noise hides the current pattern from internal operation.
Affects all operations

2.3. Functional Overview

The CRE Module can be configured using one of 4 different interfaces for maximum design flexibility.

2.3.1. LMMI Interface

The LMMI Interface is the native interface of the IP, and the most resource-efficient interface of the CRE Module. Using
this interface, user can directly use all of native IP features without using any fabric or additional control signals.

2.3.2. LMMI + FIFO Interface (Generic Interface)

The LMMI + FIFO interface is similar to the native LMMI interface with the addition of a FIFO control port. The FIFO
shares its input and output data connection with the LMMI’s input and output connection, hence user must design
additional circuitry to fully take advantage of this interface. The benefits of the FIFO data path are the increased
throughput for AES/SHA transactions. In this configuration, user can still utilize all the features of the IP while
minimizing resource utilization.
Important: The LMMI write and read data ports are shared with the FIFO interface. Proper care must be taken when
writing/sampling data to/from the IP using different clocks. This document assumes that the user have properly taken
care of any possible clock crossing issues which could arise from the use of asynchronous clocks.

2.3.3. AHB-Lite Interface

The CRE Module is designed to be fully compatible with the AHB-Lite standard. The bridge allows translation of signals
from the AHB-L bus into LMMI compatible signals, which can be directly interpreted by the core CRE security IP.

2.3.4. APB Interface

The CRE Module is designed to be fully compatible with the APB standard. The bridge allows translation of signals from
the APB bus into LMMI compatible signals, which can be directly interpreted by the core CRE Module.

© 2020-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
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2.4. Signal Descriptions

Table 2.1 CRE Module Ports
Pin Name Direction Width (Bits) Description
Core IP Signals
cfg_clk_i IN 1 Config Clock Signal (from OSC IP)
cre_clk_i IN 1 CRE Clock Signal (from OSC IP)
cre_rstn_i IN 1 CRE Engine Reset Signal
LMMI Slave Interface1
lmmi_clk_i IN 1 Clock Signal of the LMMI Interface
LMMI Reset Signal. Active LOW, LMMI interface is in reset when
lmmi_resetn_i IN 1
asserted.
Active HIGH signal, indicates that the master wants initiate a
lmmi_request_i IN 1
transaction when asserted.
Active HIGH signal, indicates a write transaction when the
lmmi_wr_rdn_i IN 1
asserted.
Offset address, the accessed location of the current active
lmmi_offset_i IN 18
transaction.
Input data, the data to be written in the offset address. (This port
lmmi_wdata_i IN 32
is shared with the FIFO data input.)
Output data, the data result from the previous transaction. (This
lmmi_rdata_o OUT 32
port is shared with the FIFO data output.)
lmmi_rdata_valid_o OUT 1 Active HIGH, indicates that the data is valid when asserted.
Active HIGH, indicates that the slave is ready to receive
lmmi_ready_o OUT 1
transactions when asserted.
FIFO Interface2
async_fifo_clk_i IN 1 Clock Signal of the FIFO Interface
FIFO Reset Signal, Active HIGH, indicates that the FIFO interface is
async_fifo_rst_i IN 1
reset when asserted
Active HIGH, indicates that an input data would be written to the
async_fifo_wr_en_i IN 1
FIFO if the FIFO is not full.
Active HIGH, indicates that an output data would be generated
async_fifo_rd_en_i IN 1
from the FIFO if the FIFO is not empty.
async_fifo_full_o OUT 1 Active HIGH, indicates that the FIFO is full.
async_fifo_empty_o OUT 1 Active HIGH, indicates that the FIFO is empty.
FIFO Interface2
async_fifo_clk_i IN 1 Clock Signal of the FIFO Interface
FIFO Reset Signal, Active HIGH, indicates that the FIFO interface is
async_fifo_rst_i IN 1
reset when asserted
Active HIGH, indicates that an input data would be written to the
async_fifo_wr_en_i IN 1
FIFO if the FIFO is not full.
Active HIGH, indicates that an output data would be generated
async_fifo_rd_en_i IN 1
from the FIFO if the FIFO is not empty.
async_fifo_full_o OUT 1 Active HIGH, indicates that the FIFO is full.
async_fifo_empty_o OUT 1 Active HIGH, indicates that the FIFO is empty.

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AHB-Lite Slave Interface3

ahbl_hclk_i IN 1 Clock Signal of the AHB-L Interface.
AHB-L reset signal. Active LOW, AHB-L interface is in reset when
ahbl_hresetn_i IN 1
asserted.
Active HIGH select signal. Allows the device to function when
ahbl_hsel_i IN 1
asserted.
When HIGH, this indicates that there are currently no transfers
ahbl_hready_i IN 1
being executed.
ahbl_haddr_i IN 32 Contains the address of the data to be written / read.
ahbl_hburst_i IN 3 Determines the type of burst used in the burst transfer.
ahbl_hsize_i IN 3 Indicates the size of the transfer.
ahbl_hmastlock_i IN 1 Indicates if the transfer is part of a locked sequence.
The protection control signals provide additional information
ahbl_hprot_i IN 4
about a bus access
Determines if the transfer is a single transfer or forms a part of
ahbl_htrans_i IN 2
the burst.
ahbl_hwrite_i IN 1 Indicates the transfer direction. (HIGH = write, LOW = read).
ahbl_hwdata_i IN 32 Input data for the CRE IP.
ahbl_hreadyout_o OUT 1 Indicates that the CRE IP is busy when pin is set LOW.
Indicates that an error has occurred in the transfer when asserted
ahbl_hresp_o OUT 1
to HIGH
ahbl_hrdata_o OUT 32 Output data for the CRE IP
APB Slave Interface 4
apb_pclk_i IN 1 Clock Signal of the APB interface
APB reset signal. Active LOW, APB interface is in reset when
apb_presetn_i IN 1
asserted.
Active HIGH select signal. Allows the device to function when
apb_psel_i IN 1
asserted.
apb_paddr_i IN 32 Contains the address of the data to be written / read.
apb_pwdata_i IN 32 Input data for the HSE IP.
apb_pwrite_i IN 1 Indicates the transfer direction. (HIGH = write, LOW = read).
apb_penable_i IN 1 Active HIGH, Initiates a transfer request when asserted.
Active HIGH, indicates that the slave is ready to receive
apb_pready_o OUT 1
transactions when asserted.
apb_prdata_o OUT 32 Output data for the HSE IP
Note:
1. LMMI interface is available when INTERFACE = “lmmi” or INTERFACE = “generic”
2. FIFO interface is available when INTERFACE = “generic”. The FIFO interface ports must by tied to 0, if unused or just set
INTERFACE = “lmmi”.
3. AHB-Lite interface is available when INTERFACE = “AHB-Lite”
4. APB interface is available when INTERFACE = “APB”

2.5. Attribute Summary

Table 2.2. CRE Module Parameters
Parameter Name Values Default Description
Instantiates the IP with the selected bus interface:
“generic”: LMMI + FIFO
“generic”, “lmmi”,
INTERFACE “generic” “lmmi: LMMI only
“AHB-Lite”, “APB”
“AHB-Lite”: AHB-L bus
“APB”: APB bus

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2.6. Register Map

The HSE Module contains several registers which control the different security functions of the IP. Some registers
change function depending on the current function that the IP is doing.
Table 2.3. CRE Instruction Register Map
APB / AHB-L
Name LMMI [17:0] Size R/W Description
[31:0]
Instruction register, writing to this register defines the
current function of the CRE Engine and automatically
starts the Engine:
0x00: Clears previous instruction
RI_CTRL1 0x2 000C 0x0000 080C 4B W/O
0x02: True Random Generation
0x05: Starts SHA256
0x06: Starts HMAC-SHA256
0x09: Starts AES Engine
Sets the size of the message to be encrypted / decrypted
RI_CTRL3 0x2 0014 0x0000 0814 4B W/O
HMAC-SHA [1980B max)
Sets the size of the key used in the encryption /
decryption process (AES)
AES_SIZE 0x2 0018 0x0000 0818 4B W/O
0x00: 128-bits (16B)
0x01: 256-bits (32B)
Shows the current status of the CRE Engine:
0x0B0: Engine is ready to accept instructions
RO_GP0 0x2 0020 0x0000 0820 4B R/O
0x0B1: Engine is busy
0x0B2: Engine has completed performing instructions
Writes the information controlling the Differential
Power Analysis features of the IP.
DPA_CON 0x2 0030 0x0000 0830 4B W
Bit[0] controls “Clock Randomization”
Bit[1] controls “Random Noise Addition”
Sets the data source for the SHA / AES engine:
0x00: Sets the AES engine data source to the bus
DATA_SRC 0x2 003C 0x0000 083C 4B W/O 0x02: Sets the SHA engine data source to the bus
0x03: Sets the SHA engine data source to the FIFO
0x04: Sets the AES engine data source to the FIFO
AES Control Register, sets the current function of the
AES engine to either encrypt or decrypt
AES_CON 0x2 2040 0x0000 2840 4B W/O
0x00: Encryption
0x01: Decryption
Shows the current status of the AES Engine:
AES_STAT[0] = 0: AES is busy expanding the key
AES_STAT 0x2 2044 0x0000 2844 4B R/O AES_STAT[0] = 1: AES key expansion ready
AES_STAT[1] = 0: AES is encrypting / decrypting
AES_STAT[1] = 1: AES process finished
Initializes the SHA engine, must be written with 0x01
SHA_INIT 0x2 3070 0x0000 3870 4B W/O
followed by 0x00

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Table 2.4. CRE Data Register Map

LMMI [17:0] APB / AHB-L [31:0] Description
HMAC-SHA:
0x1 F800 0x0000 0000 Generation:
INPUT (before process): HMAC-key (32B)

HMAC-SHA:
0x1 F820 0x0000 0020 Generation:
OUTPUT (after process): SHA message (32B)

HMAC-SHA:
0x1 F840 0x0000 0040 Generation:
INPUT (before process): message (n bytes depending on length)

TRNG:
0x1 F880 0x0000 0080
OUTPUT (after process): Q (32B), output of TRNG engine

AES:
0x2 2000 0x0000 2800
Input (before process): AES Key (32B) [Big Endian]
AES:
Encryption Mode:
• Input (before process): Private Message (16B) [Big Endian]. Total Message Size can
0x2 2020 0x0000 2820 be larger than 16B, but must be processed at 16B at a time.
Decryption Mode:
• Output (after process): Decrypted Message (16B) [Big Endian]. Total Message Size
can be larger than 16B, but must be processed at 16B at a time.
AES:
Encryption Mode:
• Output (after process): Encrypted Message (16B) [Big Endian]. Total Message Size
0x2 2030 0x0000 2830 can be larger than 16B, but must be processed at 16B at a time.
Decryption Mode:
• Input (before process): Encrypted Message (16B) [Big Endian]. Total Message Size
can be larger than 16B, but must be processed at 16B at a time.
SHA:
Input (before process): SHA data size (n bytes depending on message length) [Big
0x2 304C 0x0000 384C Endian]
1
Address does not increment, data must be written on the same address for every word
SHA:
0x2 3050 0x0000 3850
Output (after process): SHA message (32B)

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2.7. CRE Function Access

Note: When the transaction exceeds 4B of data, it is assumed that the user would automatically write or read at the
address position of the succeeding addresses in an incremental fashion in order to complete the entire data set, unless
otherwise indicated. Example, if 16B of data would need to be written at address 0x0000 0000, user would write four
4B data on addresses 0x0000 00000, 0x0000 0004, 0x0000 0008 and 0x0000 000C in four different transactions. This
applies to all bus interfaces: LMMI, AHB-L, and APB. All data are LITTLE ENDIAN unless otherwise specified.
Table 2.5. SHA Message Generation Procedure (DATA_SOURCE = bus)
Transaction AHB-L / APB LMMI Data Description
Read 0x0000 0820 0x2 0020 4B Poll if IP is Ready. [RO_GP0 == 0xB0]
[DATA_SRC ← 0x02]
Write 0x0000 083C 0x2 003C 4B Sets the SHA data source from the LMMI / AHB-L /
APB bus
[SHA_INIT ← 0x01]
Write 0x0000 3870 0x2 3070 4B
Initializes SHA (1st step)
[SHA_INIT ← 0x00]
Write 0x0000 3870 0x2 3070 4B
Initializes SHA (2nd step)
[RI_CTRL1 ← 0x05]
Write 0x0000 080C 0x2 000C 4B
Starts the SHA Engine
Message to be hashed. Written 1B at a time on the
same address on every write iteration, no increment
required. [BIG-ENDIAN] (The upper 3B must be
Write 0x0000 384C 0x2 304C 1B padded by 0, to fill the 32-bit word. The MSB of the
last word written must be 1). (that is, if the message
is 0x12345678, it must be written as 0x0000 0012,
0x0000 0034, 0x0000 0045 and 0x8000 0078)
Read 0x0000 0820 0x2 0020 4B Poll if transaction is done. [RO_GP0 == 0xB2]
Read 0x0000 3850 0x2 3050 32B SHA Message
[RI_CTRL1 ← 0x00]
Write 0x0000 080C 0x2 000C 4B Clears the previous transaction, and sets the IP ready
for the next.

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Table 2.6. SHA Message Generation Procedure (DATA_SOURCE = FIFO)

Transaction AHB-L / APB LMMI Data Description
Read 0x0000 0820 0x2 0020 4B Poll if IP is Ready. [RO_GP0 == 0xB0]
[DATA_SRC ← 0x03]
Write 0x0000 083C 0x2 003C 4B Sets the SHA data source from the LMMI / AHB-L /
APB bus
[SHA_INIT ← 0x01]
Write 0x0000 3870 0x2 3070 4B
Initializes SHA (1st step)
[SHA_INIT ← 0x00]
Write 0x0000 3870 0x2 3070 4B
Initializes SHA (2nd step)
[RI_CTRL1 ← 0x05]
Write 0x0000 080C 0x2 000C 4B
Starts the SHA Engine
Message to be hashed. Written 1B at a time as long
as the signal async_full_o is LOW. Hold the data
when the async_full_o is HIGH, this gives time for
the buffer to clear. Write the entire message first
lmmi_wrdata before reading hash output. [BIG-ENDIAN] (The
Write N/A N bytes
port upper 3B must be padded by 0, to fill the 32-bit
word. The MSB of the last word written must be 1).
(i.e. if the message is 0x12345678, it must be written
as 0x0000 0012, 0x0000 0034, 0x0000 0045 and
0x8000 0078)
SHA Message, start reading when the signal
lmmi_rddata
Read N/A 32B async_empty_o is LOW. Continue reading until the
port
async_empty_o signal is HIGH.1
[RI_CTRL1 ← 0x00]
Write 0x0000 080C 0x2 000C 4B Clears the previous transaction and sets the IP ready
for the next.
1. The FIFO interface is designed specifically for high throughput applications. The user must keep rd_en_i until async_empty_o
signal transitions from LOW to HIGH.
Table 2.7. HMAC-SHA Message Generation Procedure
Transaction AHB-L / APB LMMI Data Description
Read 0x0000 0820 0x2 0020 4B Poll if IP is Ready. [RO_GP0 == 0xB0]
[RI_CTRL3 ← <message size in bytes>]
Write 0x0000 2814 0x2 2014 4B
Size of message to be hashed
[DATA_SRC ← 0x02]
Write 0x0000 083C 0x2 003C 4B Sets the SHA data source from the LMMI / AHB-L /
APB bus
Write 0x0000 0000 0x1 F800 32B HMAC Key
Message to be hashed. If N is not divisible by 4B,
Write 0x0000 0040 0x1 F840 N bytes
pad the missing bytes on the last transaction with 0.
[RI_CTRL1 ← 0x06]
Write 0x0000 080C 0x2 000C 4B
Starts the HMAC-SHA Engine
Read 0x0000 0820 0x2 0020 4B Poll if transaction is done. [RO_GP0 == 0xB2]
Read 0x0000 0020 0x1 F820 32B SHA Message
[RI_CTRL1 ← 0x00]
Write 0x0000 080C 0x2 000C 4B Clears the previous transaction and sets the IP ready
for the next.

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14 FPGA-IPUG-02067-1.3
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Table 2.8. AES Encryption Procedure (DATA_SOURCE = bus)

Transaction AHB-L / APB LMMI Data Description
Read 0x0000 0820 0x2 0020 4B Poll if IP is Ready. [RO_GP0 == 0xB0]
[DATA_SRC ← 0x00]
Write 0x0000 083C 0x2 003C 4B Sets the AES data source from the LMMI / AHB-L /
APB bus
[AES_CON ← 0x00]
Write 0x0000 2840 0x2 2040 4B
Sets the AES mode to encryption
[AES_SIZE ← <size>]
Sets the AES key size for encryption.
Write 0x0000 0818 0x2 0018 4B
0x00: 128-bits (16B)
0x01: 256-bits (32B)
0x0000 2800 0x2 2000
Write 32B / 16B1 AES Key
0x0000 28101 0x2 20101
[AES_STAT[0] == 1]
Waits for the AES to finish key expansion
Read 0x0000 2844 0x2 2044 4B
AES_STAT[0] = 0: Busy
AES_STAT[0] = 1: Ready
[RI_CTRL1 ← 0x09]
Write 0x0000 080C 0x2 000C 4B
Starts the AES Engine
AES message to be encrypted. For larger data sizes:
user must write 16B → wait for encryption to finish
Write 0x0000 2820 0x2 2020 16B → read the output data (see succeeding
procedures); before continuing to the next set of
data. [BIG ENDIAN]
[ AES_STAT[1] == 1]
Waits for the AES to finish decryption
Read 0x0000 2844 0x2 2044 4B
AES_STAT[1] = 0: Busy
AES_STAT[1] = 1: Ready
Encrypted Message. For larger data sizes: user must
write 16B → wait for encryption to finish → read the
Read 0x0000 2830 0x2 2030 16B
output data (see preceding procedures); before
continuing to the next set of data. [BIG ENDIAN]
Read 0x0000 0820 0x2 0020 4B Poll if transaction is done. [RO_GP0 == 0xB2]
[RI_CTRL1 ← 0x00]
Write 0x0000 080C 0x2 000C 4B Clears the previous transaction and sets the IP ready
for the next.
1. if AES_SIZE is for 128-bits.

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FPGA-IPUG-02067-1.3 15
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Table 2.9. AES Decryption Procedure (DATA_SOURCE = bus)

Transaction AHB-L / APB LMMI Data Description
Read 0x0000 0820 0x2 0020 4B Poll if IP is Ready. [RO_GP0 == 0xB0]
[DATA_SRC ← 0x00]
Write 0x0000 083C 0x2 003C 4B Sets the AES data source from the LMMI / AHB-L /
APB bus
[AES_CON ← 0x01]
Write 0x0000 2840 0x2 2040 4B
Sets the AES mode to decryption
[AES_SIZE ← <size>]
Sets the AES key size for decryption.
Write 0x0000 0818 0x2 0018 4B
0x00: 128-bits (16B)
0x01: 256-bits (32B)
0x0000 2800 0x2 2000
Write 32B / 16B1 AES Key
0x0000 28101 0x2 20101
[AES_STAT[0] == 1]
Waits for the AES to finish key expansion
Read 0x0000 2844 0x2 2044 4B
AES_STAT[0] = 0: Busy
AES_STAT[0] = 1: Ready
[RI_CTRL1 ← 0x09]
Write 0x0000 080C 0x2 000C 4B
Starts the AES Engine
AES message to be decrypted. For larger data sizes:
user must write 16B → wait for encryption to finish
Write 0x0000 2820 0x2 2020 16B → read the output data (see succeeding
procedures); before continuing to the next set of
data. [BIG ENDIAN]
[ AES_STAT[1] == 1]
Waits for the AES to finish decryption
Read 0x0000 2844 0x2 2044 4B
AES_STAT[1] = 0: Busy
AES_STAT[1] = 1: Ready
Decrypted Message. For larger data sizes: user must
write 16B → wait for encryption to finish → read the
Read 0x0000 2830 0x2 2030 16B
output data (see preceding procedures); before
continuing to the next set of data. [BIG ENDIAN]
Read 0x0000 0820 0x2 0020 4B Poll if transaction is done. [RO_GP0 == 0xB2]
[RI_CTRL1 ← 0x00]
Write 0x0000 080C 0x2 000C 4B Clears the previous transaction and sets the IP ready
for the next.
1. if AES_SIZE is for 128-bits.

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16 FPGA-IPUG-02067-1.3
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Table 2.10. AES Encryption Procedure (DATA_SOURCE = FIFO)

Transaction AHB-L / APB LMMI Data Description
Read 0x0000 0820 0x2 0020 4B Poll if IP is Ready. [RO_GP0 == 0xB0]
[DATA_SRC ← 0x04]
Write 0x0000 083C 0x2 003C 4B
Sets the AES data source from the FIFO interface.
[AES_CON ← 0x00]
Write 0x0000 2840 0x2 2040 4B
Sets the AES mode to encryption
[AES_SIZE ← <size>]
Sets the AES key size for encryption.
Write 0x0000 0818 0x2 0018 4B
0x00: 128-bits (16B)
0x01: 256-bits (32B)
0x0000 2800 0x2 2000
Write 32B / 16B1 AES Key
0x0000 28101 0x2 20101
[ AES_STAT[0] == 1]
Waits for the AES to finish key expansion
Read 0x0000 2844 0x2 2044 4B
AES_STAT[0] = 0: Busy
AES_STAT[0] = 1: Ready
[RI_CTRL1 ← 0x09]
Write 0x0000 080C 0x2 000C 4B
Starts the AES Engine
Message to be encrypted. Written 4B at a time as
long as the signal async_full_o is LOW. Hold the data
lmmi_wrdata when the async_full_o is HIGH, this gives time for
Write N/A 32B
port the buffer to clear. Write the entire message first
before waiting for the async_empty_o to go LO.
[BIG-ENDIAN]
Encrypted message, start reading when the signal
async_empty_o is LOW. When the async_empty_o
lmmi_rddata goes HIGH, while there is still remaining data to be
Read N/A 32B
port read; wait for the signal to go LOW again before
reading.2 This gives the AES engine enough time to
process the input data.[BIG-ENDIAN]
Read 0x0000 0820 0x2 0020 4B Poll if transaction is done. [RO_GP0 == 0xB2]
[RI_CTRL1 ← 0x00]
Write 0x0000 080C 0x2 000C 4B Clears the previous transaction, and sets the IP ready
for the next.
Notes:
1. If AES_SIZE is for 128-bits
2. The FIFO interface is designed specifically for high throughput applications. The user must keep rd_en_i until async_empty_o
signal transitions from LOW to HIGH.

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FPGA-IPUG-02067-1.3 17
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Table 2.11. AES Decryption Procedure (DATA_SOURCE = FIFO)

Transaction AHB-L / APB LMMI Data Description
Read 0x0000 0820 0x2 0020 4B Poll if IP is Ready. [RO_GP0 == 0xB0]
[DATA_SRC ← 0x04]
Write 0x0000 083C 0x2 003C 4B
Sets the AES data source from the FIFO interface.
[AES_CON ← 0x01]
Write 0x0000 2840 0x2 2040 4B
Sets the AES mode to decryption
[AES_SIZE ← <size>]
Sets the AES key size for decryption.
Write 0x0000 0818 0x2 0018 4B
0x00: 128-bits (16B)
0x01: 256-bits (32B)
0x0000 2800 0x2 2000
Write 32B / 16B1 AES Key
0x0000 28101 0x2 20101
[ AES_STAT[0] == 1]
Waits for the AES to finish key expansion
Read 0x0000 2844 0x2 2044 4B
AES_STAT[0] = 0: Busy
AES_STAT[0] = 1: Ready
[RI_CTRL1 ← 0x09]
Write 0x0000 080C 0x2 000C 4B
Starts the AES Engine
Message to be decrypted. Written 4B at a time as
long as the signal async_full_o is LOW. Hold the data
lmmi_wrdata when the async_full_o is HIGH, this gives time for
Write N/A 16B
port the buffer to clear. Write the entire message first
before waiting for the async_empty_o to go LO.
[BIG-ENDIAN]
Decrypted message, start reading when the signal
async_empty_o is LOW. When the async_empty_o
lmmi_rddata goes HIGH, while there is still remaining data to be
Read N/A 16B
port read; wait for the signal to go LOW again before
reading.2 This gives the AES engine enough time to
process the input data.[BIG-ENDIAN]
Read 0x0000 0820 0x2 0020 4B Poll if transaction is done. [RO_GP0 == 0xB2]
[RI_CTRL1 ← 0x00]
Write 0x0000 080C 0x2 000C 4B Clears the previous transaction, and sets the IP ready
for the next.
Notes:
1. If AES_SIZE is for 128-bits
2. The FIFO interface is designed specifically for high throughput applications. The user must keep rd_en_i until async_empty_o
signal transitions from LOW to HIGH.

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18 FPGA-IPUG-02067-1.3
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Table 2.12. AES-Key Size Change (128-bit to 256-bit)

Transaction AHB-L / APB LMMI Data
Description
Read 0x0000 0820 0x2 0020 4B
Poll if IP is Ready. [RO_GP0 == 0xB0]
[RI_CTRL1 ← AES]
Write 0x0000 081C 0x2 001C 4B
Write AES old 128-bit key LSB [31:0].
1[ AES_STAT[0] == 1]

Waits for the AES to finish key expansion

Read 0x0000 2844 0x2 2044 4B
AES_STAT[0] = 0: Busy
AES_STAT[0] = 1: Ready
1[AES_SIZE ← <size>]
Write 0x0000 0818 0x2 0018 4B
Sets the AES key size to 0x01 for 256-bit selection.
1. Follow the instructions depending on the next AES transaction. Refer to Table 2.8, Table 2.9, Table 2.10, and Table 2.11 for the
protocols available related to AES.
Table 2.13. True Random Number Generator Procedure
Transaction AHB-L / APB LMMI Data Description
Read 0x0000 0820 0x2 0020 4B Poll if IP is Ready. [RO_GP0 == 0xB0]
[RI_CTRL1 ← 0x02]
Write 0x0000 080C 0x2 000C 4B
Starts the True Random Number Generation Process.
Read 0x0000 0820 0x2 0020 4B Poll if transaction is done. [RO_GP0 == 0xB2]
Read 0x0000 0080 0x1 F880 32B Random Generated Number output
[RI_CTRL1 ← 0x00]
Write 0x0000 080C 0x2 000C 4B Clears the previous transaction and sets the IP ready
for the next.

Table 2.14. DPA Feature Access

Transaction AHB-L / APB LMMI Data Description
Read 0x0000 0820 0x2 0020 4B Poll if IP is Ready. [RO_GP0 == 0xB0]
[DPA_CON ← <DPA setting>]
Write 0x0000 0830 0x2 0030 4B Bit [0] = Clock randomization
Bit [1] = Random Noise Addition
The steps below are for DPA_CON[0] = 1
[RI_CTRL1 ← 0x03]
Write 0x0000 080C 0x2 000C 4B API generates a random seed using TRNG, to be
loaded as a clock enable signal.
Read 0x0000 0820 0x2 0020 4B Poll if transaction is done. [RO_GP0 == 0xB2]
[RI_CTRL1 ← 0x00]
Write 0x0000 080C 0x2 000C 4B Clears the previous transaction and sets the IP ready
for the next.

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FPGA-IPUG-02067-1.3 19
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2.8. CRE Timing Diagrams

The CRE timing diagrams are compliant with the supported bus interfaces: LMMI, AHB-L and APB. The IP is designed to
support the protocols for this bus interface standard. A special case would be using the generic LMMI interface where
the IP configuration is fed through the LMMI bus, and data is processed using the FIFO interface.

Figure 2.2. SHA-256 Hash Done on Size N-Bytes Message

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20 FPGA-IPUG-02067-1.3
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2.9. Interface Limitations

Table 2.15. CRE Interface Limitations
Signal / Command Interface Description
The IP requires 500 clock cycles minimum in order to initialize the Security
“generic”, “lmmi”, Engine Core. This means that the user should wait 500 clock cycles before
RESET
“AHB-Lite”, “APB” initiating any bus access request. The 500 cycle measurement is taken from
the clock fed to cre_clk_i port.
The AHB-Lite interface cannot support byte / half-word transactions, and any
HSIZE “AHB-Lite”
AHB-Lite access should be limited with HSIZE[2:0] = 010.
Any write on a read-only register would cause an overwrite, if done on a
Write on Read-only “lmmi”, “AHB-Lite”,
register which contains process result. This command would overwrite the
register “APB”
result.
“lmmi”, “AHB-Lite”, Any read on a write register would return garbage data. The IP would still
Write on Read register
“APB” return an output as compliance to bus specifications.

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FPGA-IPUG-02067-1.3 21
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3. Getting Started
The Module/IP Block Wizard in Lattice Radiant Software allows the user to generate, create, or open modules for the
target device.
To generate the module:
1. From the Lattice Radiant Software, select the IP Catalog tab, and select IP on Local.

Figure 3.1. IP on Local, with CRE Selected Under Architecture

2. Double-click on CRE IP, to open the Module/IP Block Wizard. Provide a file name and click Next.

Figure 3.2. Module / IP Block Wizard

3. On the next screen, the Configuration mode for the module is displayed. The available user parameters are shown.
Use the default settings for now. Click Generate. After generation, the IP is automatically added on the active
project.

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22 FPGA-IPUG-02067-1.3
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Figure 3.3. IP Structure

3.1. Generated Files and Top Level Directory Structure

Table 3.1 shows the list of generated files and contains a short description of each file.
Table 3.1 CRE Generated File Description
File Sim Synthesis Description
Top Level RTL file with the selected configuration. The
<IP_name>.v Yes Yes
main IP file

testbench/dut_params Yes ― Top level parameters of the generated RTL file

Instantiated version of the <IP_name>.v file for

testbench/dut_inst Yes ―
simulation use

Test bench template, user can modify this to match the

specific needs. The tb_top contains a master module
testbench/tb_top.v Yes ―
and a checker module, which is automatically included
when the IP is simulated.

― ― This file contains the configuration options used to

<IP_name>.cfg
recreate or modify the core IP in the IP Platform.

― ― The IPX file holds references to all of the elements of an

IP or Module after it’s generated from the IP Platform
user interface. This file is used to bring in the
<IP_name>.ipx appropriate files during the design implementation and
analysis. It is also used to re-load parameter settings
into the IP Platform when the IP/Module is being re-
generated.

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FPGA-IPUG-02067-1.3 23
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3.2. Instantiating the Module

To instantiate the module, type the module name then instance name, following the Verilog format. Alternatively, a
sample instance can be seen in the testbench/dut_inst folder.

3.3. Running Functional Simulation

IP module generation includes a Verilog-based testbench to check for integrity of the generated IP. Testbench will
consume the parameters extracted from User configuration to match the IP. A high level block diagram showing the
testbench is shown below.

Figure 3.4. IP Testbench Block Diagram

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24 FPGA-IPUG-02067-1.3
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To run the testbench:

1. Add the testbench by right clicking the implementation name and selecting Add.
2. Add the simulation file. Select the testbench file from <ip_name>\testbench\ . The top level RTL is named tb_top.v

Figure 3.5. Adding the Simulation File

3. Once the simulation file is added, simulate the project. Click Tools > Simulation Wizard to open Lattice Radiant
Software’s simulation wizard.
4. The splash window opens. Configure the testbench and click Next.

Figure 3.6. Simulation Wizard

5. For this example, name the project “test”, using the Active-HDL simulator and RTL simulation only. Click Next.

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FPGA-IPUG-02067-1.3 25
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6. The list of files to be added appears. Make sure that at least two files are added: the generated IP and the top level
testbench. Click Next.

Figure 3.7. File List

7. Simulation Wizard does not parse the entire set of included RTL. In this section, make sure that the Simulation Top
Model is tb_top. Click Next.

Figure 3.8. Parse HDL Files

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26 FPGA-IPUG-02067-1.3
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8. Verify that the options Run simulator, Add top-level signals to waveform display, and Run simulation are checked.

Figure 3.9. Simulation Wizard Summary

9. Click Finish to automatically open Active-HDL and run the first 1 µs of the simulation.

Figure 3.10. Active-HDL Simulation Start

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10. Click Play to continue the simulation and view the rest of the waveform.

Figure 3.11. Active-HDL Simulation Finished

11. Once the simulation is completed, a list of all tests ran with their results, either data, pass, or fail are viewable. The
speed of the test is dependent on the configuration of the clocks and if the USE_OSC parameter is enabled or
disabled.

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28 FPGA-IPUG-02067-1.3
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Appendix A. Resource Utilization

Table A.1 shows configuration and resource utilization for LIFCL-40-9BG400I using Lattice LSE of Lattice Radiant
Software 3.1.
Table A.1. Resource Utilization1 (LIFCL)
Cryptographic Maximum
Interface Registers LUTs2 EBR
Block Frequency
LMMI 0 1 0 1 200 MHz
Generic (LMMI +
0 1 0 1 200 MHz
FIFO)
AHB-L 200 341 0 1 200 MHz
APB 3 19 0 1 200 MHz
Notes:
1. In all configurations, the oscillator clock and reset pins are connected externally to the CRE module.
2. The distributed RAM utilization is accounted for in the total LUT4s utilization. The actual LUT4 utilization is distribution among
logic, distributed RAM, and ripple logic.

Table A.2 shows configuration and resource utilization for LFD2NX-40-9BG256I using Lattice LSE of Lattice Radiant
Software 3.1.
Table A.2. Resource Utilization1 (LFD2NX)
Cryptographic Maximum
Interface Registers LUTs2 EBR
Block Frequency
LMMI 0 1 0 1 200 MHz
Generic (LMMI +
0 1 0 1 200 MHz
FIFO)
AHB-L 200 342 0 1 200 MHz
APB 3 19 0 1 200 MHz
Notes:
1. In all configurations, the oscillator clock and reset pins are connected externally to the CRE module.
2. The distributed RAM utilization is accounted for in the total LUT4s utilization. The actual LUT4 utilization is distribution among
logic, distributed RAM, and ripple logic.

Table A.3 shows configuration and resource utilization for LFCPNX-100-7LFG672I using Lattice LSE of Lattice Radiant
Software 2022.1.
Table A.3. Resource Utilization1 (LFCPNX)
Cryptographic Maximum
Interface Registers LUTs2 EBR
Block Frequency
LMMI 0 1 0 1 200 MHz
Generic (LMMI +
0 1 0 1 200 MHz
FIFO)
AHB-L 200 261 0 1 200 MHz
APB 3 14 0 1 200 MHz
Notes:
1. In all configurations, the oscillator clock and reset pins are connected externally to the CRE module.
2. The distributed RAM utilization is accounted for in the total LUT4s utilization. The actual LUT4 utilization is distribution among
logic, distributed RAM, and ripple logic.

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FPGA-IPUG-02067-1.3 29
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User Guide

References
• AMBA 3 AHB-Lite Protocol Specification

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30 FPGA-IPUG-02067-1.3
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Technical Support Assistance

Submit a technical support case through www.latticesemi.com/techsupport.
For frequently asked questions, refer to the Lattice Answer Database at
http://www.latticesemi.com/Support/AnswerDatabase.

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FPGA-IPUG-02067-1.3 31
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Revision History
Revision 1.3, December 2022
Section Change Summary
Appendix A. Resource Utilization Added Table A.3. Resource Utilization1 (LFCPNX).
Technical Support Assistance Added Lattice FAQ website link.

Revision 1.2, November 2021

Section Change Summary
Functional Overview Added footnote in Table 2.12. AES-Key Size Change (128-bit to 256-bit).
Appendix A. Resource Utilization General update to this section.

Revision 1.1, June 2021

Section Change Summary
— Changed document status from Preliminary to final.
Introduction • Replaced specific product names with Lattice FPGA devices built on the Lattice Nexus
platform.
• Revised statement to This module is based on the built-in Security Hard IP having the
following features.

Revision 1.0, August 2020

Section Change Summary
All Preliminary release

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