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Renesas I3C IP Data Sheet Overview

The I3C IP data sheet describes an I3C IP core that is compliant with the MIPI I3C Specification v1.0. The IP can operate as an I3C main/secondary master or slave and supports high data rates up to 33.4Mbps. It also supports legacy I2C functionality. The IP block diagram shows the main components including the bit rate controller, Tx/Rx control, FIFO buffers, and APB bus interface.

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54 views2 pages

Renesas I3C IP Data Sheet Overview

The I3C IP data sheet describes an I3C IP core that is compliant with the MIPI I3C Specification v1.0. The IP can operate as an I3C main/secondary master or slave and supports high data rates up to 33.4Mbps. It also supports legacy I2C functionality. The IP block diagram shows the main components including the bit rate controller, Tx/Rx control, FIFO buffers, and APB bus interface.

Uploaded by

Ahmed Eid
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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R06PM0076EJ0100

Rev.1.00
2019.11.18

I3C IP data sheet


I3C(Improved Inter Integrated Circuit） IP
Overview
The Renesas I3C IP is compliant with the “MIPI I3C Specification v1.0”. This IP operates the
I3C Main Master/Secondary Master mode and Slave mode. And the IP supports SDR, HDR-
DDR, HDR-TSL, HDR-TSP to perform high data rate (up to 33.4Mbps @HDR-TSP) and In-
Band Interrupt. The IP can also work as I2C master and slave.

General
•Compliant with “MIPI I3C Specification v1.0”

I3C features
•Master (Main Master/Secondary Master) mode and Slave mode
•SDR (I3C Single Data Rate) Mode
- Private Message
- Broadcast Message (Common Command Code)
- Direct Message (Common Command Code)
•HDR (I3C High Data Rate) Mode
- HDR-DDR (Dual Data Rate) Mode
- HDR-TSL (Ternary Symbol Legacy) Mode
- HDR-TSP (Ternary Symbol Pure-bus) Mode
•Legacy I2C Message
•Dynamic Address Assignment
•CCC(Common Command Code) support
•In-Band Interrupt
•Hot-Join Capability
•Synchronous/ Asynchronous Timing Control
•Error Detection
•Wake Up function support
•High Priority FIFO/Normal FIFO buffer transfer
•APB Bus interface

I2C features
•Master mode and Slave mode
•I2C Bus format
- Standard-mode (Sm)
- Fast-mode (Fm)
- Fast-mode Plus (Fm+)
- High-speed mode (Hs-mode)
•7bit/10bit address
• Wake Up function support
•APB Bus interface

Renesas Electronics Corporation


© 2019 Renesas Electronics Corporation. All rights reserved.
www.renesas.com
IP Block Diagram.

R-I3C ( I2C/I3C ) INT_ri3c_wu_n


Async Domain
PMU
(clock less) domain
TCLK, TRESETn
Bit Rate Ctrl Wake Up
SYSCON
PCLK, PRESETn

pt_scli_a
Ternary DNF
gen
Rx Ctrl
pt_sdai_a
DNF
Main FSM PORT
ri3c_sclo

Tx Ctrl
ri3c_sdao
& Ternary gen

Tx System FIFO Ctrl Rx System FIFO Ctrl


ri3c_elxxxx
Command Data Buf Response Status Buf
INT_ri3c_xxx_n
Status Ctrl
TX Data Buf RX Data Buf
SFR Receive Status Buf
icu_xxx_prhbt
ICU
/
Main Command Data Main Response ELC
Buf Status Buf

Main TX Data Buf Main RX Data Buf

Tx W/R Pointer Ctrl Rx W/R Pointer Ctrl

IBI Status Buf

APB Bus
SYSCON : System Controller DNF : Digital Noise Filter
PMU : Power Management Unit SFR : Special Function Register
ICU : Interrupt Control Unit FSM : Finite State Machine
ELC : Event Link Controller

Renesas Electronics Corporation


© 2019 Renesas Electronics Corporation. All rights reserved.
www.renesas.com

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