VHDL :

VHDL stands for very high-speed integrated circuit hardware description language. It is a
programming language used to model a digital system by dataflow, behavioral and structural
style of modeling. This language was first introduced in 1981 for the department of Defense
(DoD) under the VHSIC program.

Describing a Design

In VHDL an entity is used to describe a hardware module. An entity can be described using,

 Entity declaration
 Architecture
 Configuration
 Package declaration
 Package body
Let’s see what are these?

Entity Declaration

It defines the names, input output signals and modes of a hardware module.
Syntax −
entity entity_name is
Port declaration;
end entity_name;
An entity declaration should start with ‘entity’ and end with ‘end’ keywords. The direction
will be input, output or inout.

In Port can be read

Out Port can be written

Inout Port can be read and written

Buffer Port can be read and written, it can have only one source.

Architecture −
Architecture can be described using structural, dataflow, behavioral or mixed style.
Syntax −
architecture architecture_name of entity_name
architecture_declarative_part;

begin
Statements;
end architecture_name;
Here, we should specify the entity name for which we are writing the architecture body. The
architecture statements should be inside the ‘begin’ and ‘énd’ keyword. Architecture
declarative part may contain variables, constants, or component declaration.

Data Flow Modeling

In this modeling style, the flow of data through the entity is expressed using concurrent
(parallel) signal. The concurrent statements in VHDL are WHEN and GENERATE.
Besides them, assignments using only operators (AND, NOT, +, *, sll, etc.) can also be used
to construct code.
Finally, a special kind of assignment, called BLOCK, can also be employed in this kind of
code.
In concurrent code, the following can be used −

 Operators
 The WHEN statement (WHEN/ELSE or WITH/SELECT/WHEN);
 The GENERATE statement;
 The BLOCK statement

Behavioral Modeling

In this modeling style, the behavior of an entity as set of statements is executed sequentially
in the specified order. Only statements placed inside a PROCESS, FUNCTION, or
PROCEDURE are sequential.
PROCESSES, FUNCTIONS, and PROCEDURES are the only sections of code that are
executed sequentially.
However, as a whole, any of these blocks is still concurrent with any other statements placed
outside it.
One important aspect of behavior code is that it is not limited to sequential logic. Indeed,
with it, we can build sequential circuits as well as combinational circuits.
The behavior statements are IF, WAIT, CASE, and LOOP. VARIABLES are also restricted
and they are supposed to be used in sequential code only. VARIABLE can never be global,
so its value cannot be passed out directly.

Structural Modeling

In this modeling, an entity is described as a set of interconnected components. A component

instantiation statement is a concurrent statement. Therefore, the order of these statements is
not important. The structural style of modeling describes only an interconnection of
components (viewed as black boxes), without implying any behavior of the components
themselves nor of the entity that they collectively represent.
In Structural modeling, architecture body is composed of two parts − the declarative part
(before the keyword begin) and the statement part (after the keyword begin).
Half Adder ( HA )
The addition of 2 bits is done using a combination circuit called a
Half adder. The input variables are augend and addend bits and
output variables are sum & carry bits. A and B are the two input bits.

Data flow Half Adder:

library ieee;
use ieee.std_logic_1164.all;

entity half_adder is
port (a, b: in std_logic;
sum, carry_out: out std_logic);
end half_adder;

architecture dataflow of half_adder

is
begin
sum <= a xor b;
carry_out <= a and b;
end dataflow;
Behavioural Half Adder;
library ieee;
use ieee.std_logic_1164.all;

entity half_adder is
port (a, b: in std_logic;
sum, carry_out: out std_logic);
end half_adder;
Architecture behavioral of half_adder is
begin
process (a, b)
begin
if a = ‘1’ then
sum <= not b;
carry_out <= b;
else
sum <= b;
carry_out <= ‘0’;
end if;
end process;
end behavioral;
Structural Model

library ieee;
use ieee.std_logic_1164.all;

entity half_adder is
port (a, b: in std_logic;
sum, carry_out: out std_logic);
end half_adder;

architecture structure of half_adder is

component xor_gate
port (i1, i2: in std_logic;
o1: out std_logic);
end component;

component and_gate
port (i1, i2: in std_logic;
o1: out std_logic);
end component;

begin
u1: xor_gate port map (a, b, sum);
u2: and_gate port map (a, b, carry_out);
end structure;

Sub programs:
XOR GATE AND GATE
library ieee; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;

entity xorgate is entity andgate is

port (a, b: in std_logic; port (a, b: in std_logic;
s: out std_logic); s: out std_logic);
end xorgate; end andgate;

architecture dataflow of xorgate is architecture dataflow of andgate is

begin begin
s<=a xor b; s<=a and b;
end dataflow; end dataflow;
VHDL Code for Full Adder
The VHDL Code for full-adder circuit adds three one-bit binary numbers
(A B Cin) and outputs two one-bit binary numbers, a sum (S) and a carry
(Cout). Truth Table describes the functionality of full adder. sum(S) output is
High when odd number of inputs are High. Cout is High, when two or more
inputs are High. VHDL Code for full adder can also be constructed with 2 half
adder Port mapping in to full adder.

Full Adder Truth Table

DATA FLOW

Library ieee; architecture dataflow of fulladder is

Use ieee.std_logic_1164.all; begin
Entity fulladder is sum<= a xor b xor c;
port(a,b,c:in std_logic; carry<= ((a and (b xor c)) or (b and
sum,carry : out std_logic); c));
end fulladder; end dataflow;
 BEHAVIORAL FULL ADDER
Library ieee; sum<=’0’; carry<=’0’;
Use ieee.std_logic_1164.all; elsif s<=”001” then
sum<=’1’; carry<=’0’;
Entity fulladder is elsif s<=”010” then
port(a,b,c:in std_logic; sum<=’1’; carry<=’0’;
sum,carry : out std_logic); elsif s<=”011” then
end fulladder; sum<=’0’; carry<=’1’;
elsif s<=”100” then
Architecture behavioral of fulladder is sum<=’1’; carry<=’0’;
elsif s<=”101” then
begin sum<=’0’; carry<=’1’;
process(a,b,c) elsif s<=”110” then
begin sum<=’0’; carry<=’1’;
elsif s<=”111” then
variable s:std_logic_vector(2 sum<=’1’; carry<=’1’;
downto 0); end if;
s:=a&b&c; end process;
end behavioural;
if s<=”000” then

STRUCTURAL FULLADDER
Library ieee;
Use ieee.std_logic_1164.all; Component orgate
port (a, b: in std_logic;
Entity fulladder is s: out std_logic);
port(a,b,c:in std_logic; end component;
sum,carry : out std_logic);
end fulladder; begin
Architecture behavioral of fulladder is signal s0,s1.s2:in std_logic;
Component halfadder u1:half_adder portmap(a,b,s0,s1);
port (a, b: in std_logic; u2:half_adder portmap(c,s0,sum,s2);
sum, carry_out: out std_logic); u3:or_gate portmap(s1,s2,carry);
end component; end structural;

Sub Program:
OR GATE end or_gate;
library ieee; architecture dataflow of or_gate is
use ieee.std_logic_1164.all; begin
entity or_gate is s<=a or b;
port (a, b: in std_logic; end dataflow;
s: out std_logic);
Multiplexers in Digital Logic

It is a combinational circuit which have many data inputs and single output
depending on control or select inputs. For N input lines, log n (base2) selection
lines, or we can say that for 2n input lines, n selection lines are required.
Multiplexers are also known as “Data n selector, parallel to serial convertor,
many to one circuit, universal logic circuit”.. Multiplexers are mainly used to
increase amount of the data that can be sent over the network within certain
amount of time and bandwidth.

Y=S0’S1’S2’A0+S0S1’S2’A1+S0’S1S2’A2+S1S2S3’A3+S0’S1’S2A4
S0’S1’S2’A0+S0S1’S2’A1+S0’S1S2’A2+S1S2S3’A3+S0’S1’S2A4
+S1S2’S3A5+S0’S1S2A6+S0S1S2A7
DATAFLOW MODELING OF 8:1 MUX

library ieee;
use ieee.std_logic_1164.all;
entity MUX8_1 is
port (s0,s1,s2:in std_logic;
A: in std_logic_vector(7 downto 0);
Y : out std_logic );
end MUX8_1;
architecture dataflow of MUX8_1 is
signal s0bar,s1bar,s2lbar, s3bar,t1,t2,t3,t4,t5,t6,t7,t8: std_logic;
begin
s0bar<=not s0;
s1bar<=not s1;
s2bar<=not s2;
t1<=A(0) and sbar0 and sbar1 sbar2;
t2<=A(1) and s0 and s1bar and s2bar;
t3<=A(2) and s0bar and s1 and s2bar;
t4<=A(3) and s0 and s1 and s2bar;
t5<=A(4) and s0bar and s1bar and s2;
t6<=A(5) and s0 and s1bar and s2;
t7<=A(6) and s0bar and s1 and s2;
t8<=A(7) and s0 and s1 and s2;
Y<=t1 or t2 or t3 or t4 or t5 or t6 or t7;
end dataflow;

BEHAVIORAL METHOD Mux 8*1

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
use IEEE.STD_LOGIC_arith.ALL;

entity mux8_1 is
Port ( a : in STD_LOGIC_vector(7 downto 0);
e : in STD_LOGIC;
s : in STD_LOGIC_vector(2 downto 0);
y : out STD_LOGIC);
end mux8_1;
architecture Behavioral of mux8_1 is
begin
process(a,s,e)
begin
if(e='1') then
case s is
when "000"=>y<=a(0);
when "001"=>y<=a(1);
when "010"=>y<=a(2);
when "011"=>y<=a(3);
when "100"=>y<=a(4);
when "101"=>y<=a(5);
when "110"=>y<=a(6);
when "111"=>y<=a(7);
when others=>y<='Z';
end case;
else
x<='0';
end if ;
end process;
end Behavioral;

Mux32to1 USING 8*1

STRUCTURAL MODEL MUX 32*1 USING 8*1 MUX
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
use IEEE.STD_LOGIC_arith.ALL;

entity mux32to1 is
Port ( a : in STD_LOGIC_VECTOR (31 downto 0);
sl : in STD_LOGIC_VECTOR (4 downto 0);
en : in STD_LOGIC;
o : out STD_LOGIC);
end mux32to1;

architecture structural of mux32to1 is

component mux8_1
Port ( a : in STD_LOGIC_vector(7 downto 0);
e : in STD_LOGIC;
s : in STD_LOGIC_vector(2 downto 0);
y : out STD_LOGIC);
end component;

signal p1,p2,p3,p4:std_logic;
signal m:std_logic_vector(7 downto 0);
signal sin:std_logic_vector(2 downto 0);

begin
m<="0000"&p4 &p3 &p2 &p1;
sin<='0'&sl(4)&sl(3);

x1: mux8_1 port map(a(7 downto 0),en,sl(2 downto 0),p1);

x2: mux8_1 port map(a(15 downto 8),en,sl(2 downto 0),p2);
x3: mux8_1 port map(a(23 downto 16),en,sl(2 downto 0),p3);
x4: mux8_1 port map(a(31 downto 24),en,sl(2 downto 0),p4);
x5: mux8_1 port map(m,en,sin,o);

end structural;