Intel® Atom™ Processor E3800

Product Family
Datasheet

October 2013

Revision 1.0

Reference Number: 538136

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2 Datasheet
Contents
1 Introduction ............................................................................................................ 22
1.1 Terminology ..................................................................................................... 24
1.2 Feature Overview .............................................................................................. 25
2 Physical Interfaces .................................................................................................. 31
2.1 Pin States Through Reset ................................................................................... 33
2.2 System Memory Controller Interface Signals ......................................................... 34
2.3 PCI Express* 2.0 Interface Signals ...................................................................... 35
2.4 USB 2.0 Host (EHCI/xHCI) Interface Signals ......................................................... 36
2.5 USB 2.0 HSIC Interface Signals........................................................................... 36
2.6 USB 3.0 (xHCI) Host Interface Signals ................................................................. 36
2.7 USB 2.0 Device (ULPI) Interface Signals............................................................... 37
2.8 USB 3.0 Device Interface Signals......................................................................... 37
2.9 Serial ATA (SATA) 2.0 Interface Signals ............................................................... 38
2.10 Integrated Clock Interface Signals ....................................................................... 38
2.11 Display - Digital Display Interface (DDI) Signals .................................................... 38
2.12 Display - VGA Interface Signals ........................................................................... 39
2.13 MIPI Camera Serial Interface (CSI) & ISP Interface Signals..................................... 40
2.14 Intel® High Definition Audio Interface Signals ....................................................... 40
2.15 Low Power Engine (LPE) for Audio (I2S) Interface Signals ....................................... 41
2.16 Storage Control Cluster (eMMC, SDIO, SD) Interface Signals................................... 41
2.17 SIO - High Speed UART Interface Signals ............................................................. 42
2.18 SIO - I2C Interface Signals ................................................................................. 43
2.19 SIO - Serial Peripheral Interface (SPI) Signals....................................................... 43
2.20 PCU - iLB - Real Time Clock (RTC) Interface Signals ............................................... 44
2.21 PCU - iLB - Low Pin Count (LPC) Bridge Interface Signals ........................................ 44
2.22 PCU - Serial Peripheral Interface (SPI) Signals ...................................................... 44
2.23 PCU - System Management Bus (SMBus) Interface Signals ..................................... 45
2.24 PCU - Power Management Controller (PMC) Interface Signals .................................. 45
2.25 JTAG and Debug Interface Signals ....................................................................... 46
2.26 Miscellaneous Signals ........................................................................................ 46
2.27 GPIO Signals .................................................................................................... 47
2.28 Power And Ground Pins ...................................................................................... 51
2.29 Hardware Straps ............................................................................................... 53
2.30 Configurable IO: GPIO Muxing ............................................................................ 54
2.31 Reserved Pins ................................................................................................... 54
3 Register Access Methods ......................................................................................... 55
3.1 Fixed IO Register Access .................................................................................... 55
3.2 Fixed Memory Mapped Register Access................................................................. 55
3.3 IO Referenced Register Access ............................................................................ 55
3.4 Memory Referenced Register Access .................................................................... 56
3.5 PCI Configuration Register Access........................................................................ 56
3.6 Message Bus Register Access .............................................................................. 58
3.7 Register Field Access Types ................................................................................ 59
4 Mapping Address Spaces ......................................................................................... 61
4.1 Physical Address Space Mappings ........................................................................ 61
4.2 IO Address Space.............................................................................................. 67

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 4.3 PCI Configuration Space .....................................................................................68
5 Integrated Clock ......................................................................................................71
5.1 Features ...........................................................................................................72
6 Power Management .................................................................................................75
6.1 Power Management Features...............................................................................75
6.2 Power Management States Supported...................................................................75
6.3 Processor Core Power Management ......................................................................80
6.4 Memory Controller Power Management .................................................................86
6.5 PCIe* Power Management ..................................................................................89
7 Power Up and Reset Sequence .................................................................................90
7.1 SoC System States ............................................................................................90
7.2 Power Up Sequences ..........................................................................................90
7.3 Power Down Sequences ......................................................................................94
7.4 Reset Behavior ..................................................................................................98
8 Thermal Management ............................................................................................ 100
8.1 Overview ........................................................................................................ 100
8.2 CPU Thermal Management Registers ................................................................. 100
8.3 Thermal Sensors.............................................................................................. 100
8.4 Hardware Trips................................................................................................ 101
8.5 SoC Programmable Trips .................................................................................. 101
8.6 Platform Trips ................................................................................................. 102
8.7 Thermal Throttling Mechanisms ......................................................................... 102
8.8 Thermal Status................................................................................................ 102
9 Electrical Specifications ......................................................................................... 103
9.1 Thermal Specifications...................................................................................... 103
9.2 Storage Conditions........................................................................................... 104
9.3 Voltage and Current Specifications ..................................................................... 105
9.4 Crystal Specifications ....................................................................................... 116
9.5 DC Specifications ............................................................................................. 116
9.6 AC Specifications ............................................................................................. 138
10 Ballout and Package Information ........................................................................... 199
10.1 SoC Attributes................................................................................................. 199
10.2 Package Diagrams ........................................................................................... 200
10.3 Ball Name and Function by Location ................................................................... 202
10.4 Alphabetical Ball Name List ............................................................................... 249
11 Processor Core....................................................................................................... 258
11.1 Features ......................................................................................................... 258
11.2 Platform Identification and CPUID ...................................................................... 261
11.3 References...................................................................................................... 262
12 System Memory Controller ..................................................................................... 263
12.1 Signal Descriptions .......................................................................................... 263
12.2 Features ......................................................................................................... 267
13 SoC Transaction Router.......................................................................................... 270
13.1 Register Map................................................................................................... 271
13.2 Transaction Router A-Unit Message Bus Registers ................................................ 272
13.3 Transaction Router IO Registers......................................................................... 274

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 13.4 Transaction Router C-Unit PCI Configuration Registers ......................................... 276
14 Graphics, Video and Display .................................................................................. 280
14.1 Features ........................................................................................................ 280
14.2 SoC Graphics Display ....................................................................................... 281
14.3 Display Pipes .................................................................................................. 282
14.4 Display Physical Interfaces ............................................................................... 282
14.5 References ..................................................................................................... 288
14.6 3D Graphics and Video ..................................................................................... 288
14.7 Features ........................................................................................................ 289
14.8 VED (Video Encode/Decode) ............................................................................. 291
14.9 PCI Configuration Registers .............................................................................. 294
14.10 Memory Mapped Registers (1 of 2) .................................................................... 320
14.11 Memory Mapped Registers (2 of 2) .................................................................... 502
14.12 Memory Mapped Registers (Read Only) .............................................................. 862
14.13 Memory Mapped Registers (Write Only).............................................................. 868
15 MIPI-Camera Serial Interface (CSI) & ISP............................................................. 872
15.1 Signal Descriptions .......................................................................................... 872
15.2 Features ........................................................................................................ 874
15.3 Imaging Subsystem Integration ........................................................................ 877
15.4 Functional Description...................................................................................... 879
15.5 MIPI-CSI-2 Receiver ........................................................................................ 881
15.6 Register Map .................................................................................................. 884
15.7 Image Signal Processor PCI Configuration Registers ............................................. 885
15.8 Image Signal Processor Memory Mapped IO Registers .......................................... 911
16 Storage Control Cluster (eMMC, SDIO, SD Card) ...................................................1579
16.1 Signal Descriptions .........................................................................................1579
16.2 Features .......................................................................................................1581
16.3 References ....................................................................................................1583
16.4 Register Map .................................................................................................1585
16.5 eMMC PCI Configuration Registers ....................................................................1587
16.6 eMMC Memory Mapped IO Registers .................................................................1598
16.7 SDIO PCI Configuration Registers .....................................................................1631
16.8 SDIO Memory Mapped IO Registers ..................................................................1642
16.9 SD PCI Configuration Registers ........................................................................1675
16.10 SD Memory Mapped IO Registers......................................................................1686
16.11 eMMC 4.5 PCI Configuration Registers...............................................................1719
16.12 eMMC 4.5 Memory Mapped IO Registers ............................................................1731
17 Serial ATA (SATA).................................................................................................1764
17.1 Signal Descriptions .........................................................................................1764
17.2 Features .......................................................................................................1765
17.3 References ....................................................................................................1767
17.4 Register Map .................................................................................................1768
17.5 SATA PCI Configuration Registers .....................................................................1769
17.6 SATA Legacy IO Registers ...............................................................................1798
17.7 SATA Index Pair IO Registers ...........................................................................1803
17.8 SATA AHCI Memory Mapped IO Registers ..........................................................1805
17.9 SATA Primary Read Command IO Registers .......................................................1841
17.10 SATA Primary Write Command IO Registers .......................................................1846
17.11 SATA Primary Read Control IO Registers ...........................................................1848
17.12 SATA Primary Write Control IO Registers ...........................................................1849

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 17.13 SATA Secondary Read Command IO Registers ................................................... 1850
17.14 SATA Secondary Write Command IO Registers................................................... 1855
17.15 SATA Secondary Read Control IO Registers ....................................................... 1857
17.16 SATA Secondary Write Control IO Registers....................................................... 1858
17.17 SATA Lane 0 Electrical Register Address Map ..................................................... 1859
17.18 SATA Lane 0 Electrical Register Address Map ..................................................... 1889
17.19 SATA Lane 1 Electrical Register Address Map ..................................................... 1907
17.20 SATA Lane 1 Electrical Register Address Map ..................................................... 1937
18 USB Host Controller Interfaces (xHCI, EHCI) ....................................................... 1954
18.1 Signal Descriptions ........................................................................................ 1954
18.2 USB 3.0 xHCI (Extensible Host Controller Interface) ........................................... 1956
18.3 USB 2.0 Enhanced Host Controller Interface (EHCI)............................................ 1957
18.4 References.................................................................................................... 1958
18.5 Register Map................................................................................................. 1959
18.6 USB xHCI PCI Configuration Registers .............................................................. 1961
18.7 USB xHCI Memory Mapped I/O Registers .......................................................... 1997
18.8 USB EHCI PCI Configuration Registers .............................................................. 2164
18.9 USB EHCI Memory Mapped IO Registers ........................................................... 2182
19 USB Device Controller Interfaces (3.0, ULPI) ....................................................... 2218
19.1 USB Device Controller .................................................................................... 2220
19.2 References.................................................................................................... 2221
19.3 Register Map................................................................................................. 2222
19.4 USB 3.0 Device PCI Configuration Registers ...................................................... 2223
19.5 USB 3.0 Device PCI Configuration Registers ...................................................... 2232
19.6 USB 3.0 Device Memory Mapped I/O Registers .................................................. 2237
19.7 USB 3.0 Device Memory Mapped I/O Registers .................................................. 2430
20 Intel® High Definition Audio ................................................................................ 2450
20.1 Signal Descriptions ........................................................................................ 2451
20.2 Features ....................................................................................................... 2452
20.3 References.................................................................................................... 2452
20.4 Register Map................................................................................................. 2453
20.5 HD Audio PCI Configuration Registers ............................................................... 2455
20.6 HD Audio Memory Mapped I/O Registers ........................................................... 2486
21 Low Power Engine (LPE) for Audio (I2S) .............................................................. 2582
21.1 & 8.1 Signal Descriptions ............................................................................... 2582
21.2 Features ....................................................................................................... 2583
21.3 Detailed Block Level Description ...................................................................... 2584
21.4 Software Implementation Considerations .......................................................... 2587
21.5 Clocks .......................................................................................................... 2589
21.6 SSP (I2S) ..................................................................................................... 2592
21.7 Programming Model ....................................................................................... 2597
21.8 Register Map................................................................................................. 2602
21.9 Low Power Audio PCI Configuration Registers .................................................... 2603
21.10 pci_mem Address Map.................................................................................... 2611
21.11 Memory Mapped Shim Registers ...................................................................... 2622
21.12 Low Power Audio I2S0 Address Map.................................................................. 2649
21.13 Low Power Audio I2S0 Address Map.................................................................. 2669
21.14 Low Power Audio I2S0 Address Map.................................................................. 2689
21.15 Low Power Audio DMA0 Memory Mapped IO Registers ........................................ 2709
21.16 Low Power Audio DMA1 Memory Mapped IO Registers ........................................ 2822

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22 Intel® Trusted Execution Engine (Intel® TXE) ......................................................2935
22.1 Features .......................................................................................................2935
23 PCI Express* 2.0 ..................................................................................................2937
23.1 Signal Descriptions .........................................................................................2937
23.2 Features .......................................................................................................2938
23.3 References ....................................................................................................2941
23.4 Register Map .................................................................................................2941
23.5 PCI Configuration Registers .............................................................................2943
23.6 PCI Express* PCI Configuration Registers ..........................................................2944
23.7 PCI Express* Lane 0 Electrical Address Map .......................................................2987
23.8 PCI Express* Lane 0 Electrical Address Map .......................................................3017
23.9 PCI Express* Lane 1 Electrical Address Map .......................................................3035
23.10 PCI Express* Lane 1 Electrical Address Map .......................................................3065
23.11 PCI Express* Lane 2 Electrical Address Map .......................................................3083
23.12 PCI Express* Lane 2 Electrical Address Map .......................................................3113
23.13 PCI Express* Lane 3 Electrical Address Map .......................................................3131
23.14 PCI Express* Lane 3 Electrical Address Map .......................................................3161
24 Serial IO (SIO) Overview......................................................................................3178
24.1 Serial I/O (SIO) Register Map .........................................................................3178
24.2 SIO HSUART, PWM, and SPI DMA PCI Configuration Registers ..............................3179
24.3 SIO HSUART, PWM, and SPI DMA Memory Mapped I/O Registers ..........................3188
24.4 SIO I2C DMA PCI Configuration Registers ..........................................................3360
24.5 SIO I2C DMA Memory Mapped IO Registers........................................................3369
25 SIO - Serial Peripheral Interface (SPI) .................................................................3541
25.1 Signal Descriptions .........................................................................................3541
25.2 Features .......................................................................................................3542
25.3 Register Map .................................................................................................3545
25.4 SIO SPI PCI Configuration Registers..................................................................3546
25.5 SIO SPI Memory Mapped I/O Registers .............................................................3555
26 SIO - I2C Interface ...............................................................................................3571
26.1 Signal Descriptions .........................................................................................3571
26.2 Features .......................................................................................................3572
26.3 Use ..............................................................................................................3578
26.4 References ....................................................................................................3580
26.5 Register Map .................................................................................................3580
26.6 SIO I2C0 PCI Configuration Registers ................................................................3582
26.7 SIO I2C0 Memory Mapped I/O Registers ............................................................3591
26.8 SIO I2C1 PCI Configuration Registers ................................................................3630
26.9 SIO I2C1 Memory Mapped IO Registers .............................................................3639
26.10 SIO I2C2 PCI Configuration Registers ................................................................3678
26.11 SIO I2C2 Memory Mapped IO Registers .............................................................3687
26.12 SIO I2C3 PCI Configuration Registers ................................................................3726
26.13 SIO I2C3 Memory Mapped IO Registers .............................................................3735
26.14 SIO I2C4 PCI Configuration Registers ................................................................3774
26.15 SIO I2C4 Memory Mapped IO Registers .............................................................3783
26.16 SIO I2C5 PCI Configuration Registers ................................................................3822
26.17 SIO I2C5 Memory Mapped IO Registers .............................................................3831
26.18 SIO I2C6 PCI Configuration Registers ................................................................3870
26.19 SIO I2C6 Memory Mapped IO Registers .............................................................3879

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27 SIO - High Speed UART ........................................................................................ 3918
27.1 Signal Descriptions ........................................................................................ 3918
27.2 Features ....................................................................................................... 3919
27.3 Use.............................................................................................................. 3921
27.4 Register Map................................................................................................. 3922
27.5 SIO HSUART1 PCI Configuration Registers ........................................................ 3924
27.6 SIO HSUART1 Memory Mapped I/O Registers .................................................... 3933
27.7 SIO HSUART2 PCI Configuration Registers ........................................................ 3967
27.8 SIO HSUART2 Memory Mapped I/O Registers .................................................... 3976
28 SIO - Pulse Width Modulation (PWM)................................................................... 4010
28.1 Signal Descriptions ....................................................................................... 4010
28.2 Features ....................................................................................................... 4011
28.3 Use.............................................................................................................. 4012
28.4 Register Map................................................................................................. 4012
28.5 SIO PWM0 PCI Configuration Registers ............................................................. 4014
28.6 SIO PWM0 Memory Mapped IO Registers .......................................................... 4023
28.7 SIO PWM1 PCI Configuration Registers ............................................................. 4026
28.8 SIO PWM1 Memory Mapped IO Registers .......................................................... 4035
29 Platform Controller Unit (PCU) Overview ............................................................. 4038
29.1 Features ....................................................................................................... 4038
29.2 PCU iLB LPC Port 80h I/O Registers .................................................................. 4041
30 PCU - Power Management Controller (PMC) ......................................................... 4048
30.1 Signal Descriptions ........................................................................................ 4048
30.2 Features ....................................................................................................... 4050
30.3 USB Per-Port Register Write Control ................................................................. 4059
30.4 References.................................................................................................... 4059
30.5 Register Map................................................................................................. 4059
30.6 PCU PMC Memory Mapped I/O Registers ........................................................... 4060
30.7 PCU PMC IO Registers .................................................................................... 4094
30.8 PCU iLB PMC I/O Registers .............................................................................. 4097
31 PCU - Serial Peripheral Interface (SPI) ................................................................ 4114
31.1 Signal Descriptions ........................................................................................ 4114
31.2 Features ....................................................................................................... 4115
31.3 Use.............................................................................................................. 4128
31.4 Register Map................................................................................................. 4129
31.5 PCU SPI for Firmware Memory Mapped I/O Registers .......................................... 4130
32 PCU - Universal Asynchronous Receiver/Transmitter (UART)............................... 4163
32.1 Signal Descriptions ........................................................................................ 4163
32.2 Features ....................................................................................................... 4164
32.3 Use.............................................................................................................. 4166
32.4 UART Enable/Disable...................................................................................... 4166
32.5 IO Mapped Registers ...................................................................................... 4167
32.6 PCU iLB UART IO Registers.............................................................................. 4168
33 PCU - System Management Bus (SMBus).............................................................. 4177
33.1 Signal Descriptions ........................................................................................ 4177
33.2 Features ....................................................................................................... 4178
33.3 Use.............................................................................................................. 4187
33.4 References.................................................................................................... 4187

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 33.5 Register Map .................................................................................................4187
33.6 PCU SMBUS PCI Configuration Registers ............................................................4189
33.7 PCU SMBUS Memory Mapped I/O Registers........................................................4202
33.8 PCU SMBUS I/O Registers................................................................................4214
34 PCU - Intel Legacy Block (iLB) Overview ..............................................................4226
34.1 Signal Descriptions .........................................................................................4226
34.2 Features .......................................................................................................4227
34.3 PCU iLB Interrupt Decode and Route .................................................................4229
35 PCU - iLB - Low Pin Count (LPC) Bridge ................................................................4262
35.1 Signal Descriptions .........................................................................................4262
35.2 Features .......................................................................................................4263
35.3 Use ..............................................................................................................4268
35.4 References ....................................................................................................4269
35.5 Register Map .................................................................................................4270
35.6 PCU iLB Low Pin Count (LPC) Bridge PCI Configuration Registers...........................4272
35.7 PCU iLB LPC BIOS Control Memory Mapped I/O Registers ....................................4291
36 PCU - iLB - Real Time Clock (RTC).........................................................................4292
36.1 Signal Descriptions .........................................................................................4292
36.2 Features .......................................................................................................4293
36.3 Interrupts .....................................................................................................4294
36.4 References ....................................................................................................4296
36.5 Register Map .................................................................................................4296
36.6 IO Mapped Registers.......................................................................................4296
36.7 Indexed Registers ..........................................................................................4296
36.8 PCU iLB Real Time Clock (RTC) I/O Registers .....................................................4298
37 PCU - iLB - 8254 Timers ........................................................................................4300
37.1 Signal Descriptions .........................................................................................4300
37.2 Features .......................................................................................................4300
37.3 Use ..............................................................................................................4301
37.4 Register Map .................................................................................................4304
37.5 IO Mapped Registers.......................................................................................4304
37.6 PCU iLB 8254 Timers IO Registers ....................................................................4305
38 PCU - iLB - High Precision Event Timer (HPET) .....................................................4310
38.1 Features .......................................................................................................4310
38.2 References ....................................................................................................4312
38.3 Register Map .................................................................................................4312
38.4 Memory Mapped Registers...............................................................................4312
38.5 PCU iLB High Performance Event Timer (HPET) Memory Mapped IO Registers .........4313
39 PCU - iLB - GPIO ...................................................................................................4321
39.1 Signal Descriptions .........................................................................................4321
39.2 Features .......................................................................................................4321
39.3 Use ..............................................................................................................4322
39.4 Register Map .................................................................................................4322
39.5 GPIO Registers ..............................................................................................4323
39.6 PCU iLB GPIO CFIO_SCORE_IO Address Map......................................................4325
39.7 PCU iLB GPIO CFIO_SCORE Address Map ...........................................................4341
39.8 PCU iLB GPIO CFIO_SSUS_IO Address Map........................................................4800
39.9 PCU iLB GPIO CFIO_SSUS Address Map.............................................................4809

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40 PCU - iLB - Interrupt Decoding & Routing............................................................. 5024
40.1 Features ....................................................................................................... 5024
41 PCU - iLB - IO APIC .............................................................................................. 5026
41.1 Features ....................................................................................................... 5026
41.2 Use.............................................................................................................. 5028
41.3 References.................................................................................................... 5028
41.4 Memory Mapped Registers .............................................................................. 5029
41.5 Indirect I/O APIC Registers ............................................................................. 5029
41.6 PCU iLB IO APIC Memory Mapped I/O Registers ................................................. 5030
42 PCU - iLB - 8259 Programmable Interrupt Controllers (PIC) ................................ 5032
42.1 Features ....................................................................................................... 5032
42.2 IO Mapped Registers ...................................................................................... 5039
42.3 PCU iLB 8259 Interrupt Controller (PIC) I/O Registers......................................... 5041

Figures
Figure 1 SoC Block Diagram .................................................................................23
Figure 2 Signals (1 of 2) ......................................................................................31
Figure 3 Signals (2 of 2) ......................................................................................32
Figure 4 Physical Address Space - DRAM & MMIO ....................................................62
Figure 5 Physical Address Space - Low MMIO ..........................................................63
Figure 6 Physical Address Space - DOS DRAM .........................................................64
Figure 7 Physical Address Space - SMM and Non-Snoop Mappings .............................65
Figure 8 Bus 0 PCI Devices and Functions ..............................................................70
Figure 9 Clocking Example ...................................................................................72
Figure 10 Idle Power Management Breakdown of the Processor Cores ..........................82
Figure 11 Package C-state Entry and Exit .................................................................84
Figure 12 RTC Power Well Timing Diagrams..............................................................91
Figure 13 G3/S5 to S0 Cold Boot Sequence ..............................................................93
Figure 14 S0 to S4/S5 (Power Down) Sequence without S0ix......................................96
Figure 15 CORE_VCC_S3 and UNCORE_VCC_S3 SoC Loadline................................... 108
Figure 16 Definition of Differential Voltage and Differential Voltage Peak-to-Peak ........ 121
Figure 17 Definition of Pre-emphasis ..................................................................... 122
Figure 18 eMMC DC Bus signal level ...................................................................... 125
Figure 19 Definition of VHYS in Table 169 .............................................................. 137
Figure 20 Crystal Clock Timing ............................................................................. 140
Figure 21 SVID Timing Diagram............................................................................ 141
Figure 22 DDR3L DQ Setup/Hold Relationship to/from DQSP/DQSN (Read Operation) .. 144
Figure 23 DDR3L DQ and DM Valid before and after DQSP/DQSN (Write Operation) ..... 144
Figure 24 DDR3L Write Pre-amble Duration ............................................................ 144
Figure 25 DDR3L Write Post-amble Duration........................................................... 144
Figure 26 DDR3L Command Signals Valid before and after CK Rising Edge.................. 145
Figure 27 DDR3L CKE Valid before and after CK Rising Edge ..................................... 145
Figure 28 DDR3L CS# Valid before and after CK Rising Edge .................................... 145
Figure 29 DDR3L ODT Valid before CK Rising Edge .................................................. 146
Figure 30 DDR3L Clock Cycle Time ........................................................................ 146
Figure 31 DDR3L Skew between System Memory Differential Clock Pairs (CKP/CKN).... 146
Figure 32 DDR3L CK High Time............................................................................. 146

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 Figure 33 DDR3L CK Low Time ............................................................................. 147
Figure 34 DDR3L DQS Falling Edge Output Access Time to CK Rising Edge ................. 147
Figure 35 DDR3L DQS Falling Edge Output Access Time From CK Rising Edge ............. 147
Figure 36 DDR3L CK Rising Edge Output Access Time to the 1st DQS Rising Edge ....... 147
Figure 37 VGA_DDCDATA, and VGA_DDCCLK Timing Diagram .................................. 152
Figure 38 Input Glitch Rejection of Low-Power Receivers ......................................... 153
Figure 39 MIPI-CSI-2 Clock Definition ................................................................... 153
Figure 40 MIPI-CSI-2 Data to Clock Timing Definitions ............................................ 154
Figure 41 SD Card Timing Diagram (DDR50) .......................................................... 155
Figure 42 SD card Output Timing Diagram (SDR25) ................................................ 156
Figure 43 SD Card Input Timing Diagram (SDR12).................................................. 156
Figure 44 SD Card Input Timing Diagram (Default) ................................................. 157
Figure 45 SD card Output Timing Diagram (Default)................................................ 158
Figure 46 SD Card Input Timing Diagram (High Speed) ........................................... 159
Figure 47 SD card Output Timing Diagram (High Speed).......................................... 159
Figure 48 SDIO Timing Diagram (DDR50) .............................................................. 160
Figure 49 SDIO Output Timing Diagram (SDR25).................................................... 161
Figure 50 SDIO Output Timing Diagram (SDR12).................................................... 161
Figure 51 SDIO Input Timing Diagram (SDR12/25) ................................................. 162
Figure 52 eMMC* Output Timing Diagram (High Speed Mode) .................................. 163
Figure 53 eMMC* DDR Timings............................................................................. 163
Figure 55 eMMC Clock Signal Timing Diagram (HS200 Mode) ................................... 164
Figure 54 eMMC* Input Timing Diagram (High Speed Mode) .................................... 164
Figure 56 eMMC Input Timing Diagram (HS200 Mode) ............................................. 165
Figure 57 USB Rise and Fall Times ........................................................................ 169
Figure 58 USB Full Speed Load............................................................................. 170
Figure 59 USB Differential Data Jitter for Low/Full- Speed ........................................ 170
Figure 60 USB Differential-to-EOP Transition Skew and EOP Width for Low/Full-Speed . 170
Figure 61 USB 3.0 Signals AC Specification ............................................................ 171
Figure 62 ULPI Timing Diagram ............................................................................ 172
Figure 63 V/I Curves for HDA_SDO buffers ............................................................ 173
Figure 64 Maximum AC Waveforms for 1.5 V Signaling ............................................ 176
Figure 65 I2S Slave Port Timings in I2S Mode ......................................................... 178
Figure 66 I2S Slave Port Timings in PCM Short Frame Mode ..................................... 178
Figure 67 I2S Slave Port Timings in PCM Long Frame Mode ...................................... 179
Figure 68 PCI Express* Transmitter Eye ................................................................ 181
Figure 69 PCI Express* Receiver Eye .................................................................... 181
Figure 70 SPI Timing .......................................................................................... 184
Figure 71 SMBus Transaction ............................................................................... 186
Figure 72 SMBus Timeout .................................................................................... 186
Figure 73 Valid Delay from Rising Clock Edge ......................................................... 187
Figure 74 Output Enable Delay ............................................................................. 187
Figure 75 Float Delay .......................................................................................... 187
Figure 76 Setup and Hold Times ........................................................................... 188
Figure 77 Definition of Timing for F/S-Mode Devices on I2C Bus................................ 190
Figure 78 Definition of Timing for High Speed-Mode Devices on I2C Bus..................... 192
Figure 79 UART Timing Diagram ........................................................................... 193
Figure 80 JTAG Timing Diagram ........................................................................... 194
Figure 81 TAP Valid Delay Timing Waveform .......................................................... 195
Figure 82 Test Reset (TAP_TRST#), Async GTL Input and PROCHOT# Timing
Waveform ........................................................................................... 195
Figure 83 Clock Cycle Time .................................................................................. 196
Figure 84 Clock Timing........................................................................................ 196

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 Figure 85 Valid Delay from Rising Clock Edge ......................................................... 196
Figure 86 Setup and Hold Times ........................................................................... 196
Figure 87 Float Delay .......................................................................................... 197
Figure 88 Pulse Width.......................................................................................... 197
Figure 89 Output Enable Delay ............................................................................. 197
Figure 90 Differential Clock Waveform (Measured Single-ended) ............................... 198
Figure 91 Differential Clock Waveform (Using Differential Probe for Measurement)....... 198
Figure 92 Package Mechanical Drawing .................................................................. 200
Figure 93 Soc Transaction Router Register Map....................................................... 271
Figure 94 HDMI Overview .................................................................................... 286
Figure 95 DisplayPort* Overview........................................................................... 287
Figure 96 3D Graphics Block Diagram .................................................................... 289
Figure 97 Camera Connectivity ............................................................................. 874
Figure 98 Image Processing Components ............................................................... 877
Figure 99 MIPI-CSI Bus Block Diagram .................................................................. 881
Figure 100 MIPI CSI Register Map........................................................................... 884
Figure 101 SD Memory Card Bus Topology ............................................................. 1582
Figure 102 SDIO Device Bus Topology ................................................................... 1583
Figure 103 eMMC Interface .................................................................................. 1583
Figure 104 Storage Control Cluster Register Map .................................................... 1585
Figure 105 SATA Register Map ............................................................................. 1768
Figure 106 xHCI and EHCI Port Mapping ................................................................ 1956
Figure 107 USB Host Controller Register Map ......................................................... 1960
Figure 108 Intel® HD Audio Register Map .............................................................. 2453
Figure 109 Audio Cluster Block Diagram ................................................................ 2585
Figure 110 Memory Connections for LPE ............................................................... 2586
Figure 111 SSP CCLK Structure ............................................................................ 2590
Figure 112 Programmable Serial Protocol Format .................................................... 2596
Figure 113 Programmable Serial Protocol Format (Consecutive Transfers) .................. 2596
Figure 114 Low Power Engine for Audio Register Map .............................................. 2602
Figure 115 PCIe* 2.0 Lane 0 Signal Example.......................................................... 2938
Figure 116 Root Port Configuration Options ............................................................ 2939
Figure 117 PCI Express Register Map .................................................................... 2942
Figure 118 SPI Interface Signals........................................................................... 3541
Figure 119 Clock Phase and Polarity ...................................................................... 3543
Figure 120 SIO - SPI Register Map........................................................................ 3545
Figure 121 Data Transfer on the I2C Bus................................................................ 3573
Figure 122 START and STOP Conditions ................................................................. 3574
Figure 123 Seven-Bit Address Format.................................................................... 3575
Figure 124 Ten-Bit Address Format ....................................................................... 3575
Figure 125 Master Transmitter Protocol ................................................................. 3576
Figure 126 Master Receiver Protocol...................................................................... 3577
Figure 127 START Byte Transfer ........................................................................... 3578
Figure 128 SIO - I2C Register Map ........................................................................ 3581
Figure 129 UART Data Transfer Flow ..................................................................... 3919
Figure 130 SIO - HSUART Register Map ................................................................. 3923
Figure 131 PWM Signals ...................................................................................... 4010
Figure 132 PWM Block Diagram ............................................................................ 4011
Figure 133 SIO - PWM Register Map...................................................................... 4013
Figure 134 Flash Descriptor Sections ..................................................................... 4118
Figure 135 Dual Output Fast Read Timing .............................................................. 4125
Figure 136 PCU - SMBus Register Map ................................................................... 4188
Figure 137 LPC Interface Diagram......................................................................... 4264

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12 Datasheet
 Figure 138 PCU - iLB - LPC Register Map ................................................................4270
Figure 139 SIO - I2C Register Map.........................................................................4323
Figure 140 Detailed Block Diagram ........................................................................5027
Figure 141 MSI Address and Data .........................................................................5028

Tables
Table 1 Platform Power Well Definitions ................................................................ 33
Table 2 Default Buffer State Definitions ................................................................ 33
Table 3 DDR3L System Memory Signals................................................................ 34
Table 4 PCI Express* 2.0 Interface Signals ........................................................... 35
Table 5 USB 2.0 Interface Signals........................................................................ 36
Table 6 USB 2.0 HSIC Interface Signals................................................................ 36
Table 7 USB 3.0 Interface Signals........................................................................ 36
Table 8 USB 3.0 Device Interface Signals.............................................................. 37
Table 9 SATA 2.0 Interface Signals ...................................................................... 38
Table 10 Integrated Clock Interface Signals ............................................................ 38
Table 11 Digital Display Interface Signals ............................................................... 39
Table 12 VGA Interface Signals ............................................................................. 39
Table 13 MIPI CSI Interface Signals....................................................................... 40
Table 14 HD Audio Interface Signals ...................................................................... 41
Table 15 LPE Interface Signals .............................................................................. 41
Table 16 Storage Control Cluster (eMMC, SDIO, SD) Interface Signals........................ 41
Table 17 High Speed UART Interface Signals........................................................... 42
Table 18 SIO - I2C Interface Signals ...................................................................... 43
Table 19 SIO - Serial Peripheral Interface (SPI) Signals............................................ 43
Table 20 PCU - iLB - Real Time Clock (RTC) Interface Signals .................................... 44
Table 21 PCU - iLB - LPC Bridge Interface Signals .................................................... 44
Table 22 PCU - Serial Peripheral Interface (SPI) Signals ........................................... 45
Table 23 PCU - System Management Bus (SMBus) Interface Signals .......................... 45
Table 24 PCU - Power Management Controller (PMC) Interface Signals ....................... 45
Table 25 JTAG and Debug Interface Signals ............................................................ 46
Table 26 Miscellaneous Signals and Clocks.............................................................. 47
Table 27 GPIO Signals ......................................................................................... 47
Table 28 Power and Ground Pins ........................................................................... 52
Table 29 Straps .................................................................................................. 54
Table 30 Fixed IO Register Access Method Example (P80 Register) ............................ 55
Table 31 Fixed Memory Mapped Register Access Method Example (IDX Register) ......... 55
Table 32 Referenced IO Register Access Method Example (HSTS Register) .................. 56
Table 33 Memory Mapped Register Access Method Example (_MBAR Register)............. 56
Table 34 PCI Register Access Method Example (VID Register) ................................... 56
Table 35 PCI CONFIG_ADDRESS Register (IO PORT CF8h) Mapping ........................... 57
Table 36 PCI Configuration Memory Bar Mapping..................................................... 58
Table 37 MCR Description..................................................................................... 58
Table 38 MCRX Description ................................................................................... 59
Table 39 Register Access Types and Definitions ....................................................... 59
Table 40 Fixed Memory Ranges in the Platform Controller Unit (PCU) ......................... 66
Table 41 Fixed IO Ranges in the Platform Controller Unit (PCU) ................................. 67
Table 42 Movable IO Ranges Decoded by PCI Devices on the IO Fabric....................... 68
Table 43 PCI Devices and Functions....................................................................... 68
Table 44 SoC Clock Inputs.................................................................................... 73

Intel® Atom™ Processor E3800 Product Family

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 Table 45 SoC Clock Outputs ..................................................................................73
Table 46 SoC Sx-States to SLP_S*# ......................................................................76
Table 47 General Power States for System ..............................................................77
Table 48 ACPI PM State Transition Rules .................................................................77
Table 49 Processor Core/ States Support ................................................................78
Table 50 SoC Graphics Adapter State Control ..........................................................78
Table 51 Main Memory States................................................................................79
Table 52 PCIe* States ..........................................................................................79
Table 53 G, S and C State Combinations.................................................................79
Table 54 D, S and C State Combinations .................................................................80
Table 55 Coordination of Core/Module Power States at the Package Level....................84
Table 56 RTC Power Well Timing Parameters ...........................................................91
Table 57 S3/S4/S5 to S0 Cause of Wake Events ......................................................97
Table 58 Types of Resets ......................................................................................98
Table 59 Temperature Reading Based on DTS (If TJ-MAX =90oC) ............................ 100
Table 60 Intel® Atom™ Processor E3800 Product Family Thermal Specifications......... 103
Table 61 Storage Conditions Prior to Board Attach.................................................. 104
Table 62 VCC and VNN Currents .......................................................................... 107
Table 63 VCC and VNN DC Voltage Specifications ................................................... 107
Table 64 IMVP7.0 Voltage Identification Reference ................................................. 108
Table 65 ILB RTC Crystal Specification.................................................................. 116
Table 66 Integrated Clock Crystal Specification ...................................................... 116
Table 67 R,G,B/VGA DAC Display DC specification (Functional Operating Range) ........ 117
Table 68 VGA_DDCCLK, VGA_DDCDATA Signal DC Specification .............................. 118
Table 69 VGA_HSYNC and VGA_VSYNC DC Specification ......................................... 118
Table 70 DDI Main Transmitter DC specification ..................................................... 119
Table 71 DDI AUX Channel DC Specification .......................................................... 120
Table 72 DDI DDC Signal DC Specification (DDI[1:0]_DDCDATA, DDI[1:0]_DDCCLK) . 120
Table 73 DDI DDC Misc Signal DC Specification (DDI[1:0]_HPD, DDI[1:0]_BKLTCTL,
DDI[1:0]_VDDEN, DDI[1:0]_BKLTEN) ..................................................... 120
Table 74 PCI Express DC Receive Signal Characteristics .......................................... 122
Table 75 PCI Express DC Transmit Characteristics .................................................. 122
Table 76 PCI Express DC Clock Request Input Signal Characteristics......................... 123
Table 77 MIPI HS-RX/MIPI LP-RX Minimum, Nominal, and Maximum Voltage
Parameters .......................................................................................... 123
Table 78 SDIO DC Specification ........................................................................... 124
Table 79 SD Card DC Specification ....................................................................... 124
Table 80 eMMC 4.5 Signal DC Electrical Specifications ............................................ 125
Table 81 TAP Signal Group DC Specification (TAP_TCK, TAP_TRSRT#, TAP_TMS,
TAP_TDI)............................................................................................. 125
Table 82 TAP Signal Group DC Specification (TAP_TDO) .......................................... 126
Table 83 TAP Signal Group DC Specification (TAP_PRDY#, TAP_PREQ#).................... 126
Table 84 DDR3L-RS Signal Group DC Specifications................................................ 127
Table 85 HDA Signal Group DC Specifications ........................................................ 127
Table 86 SATA TX/RX Signal Group DC Specifications ............................................. 132
Table 87 LPC Signal Group DC Specification (LPC_V1P8V3P3_S = 1.8V
(ILB_LPC_AD][3:0], ILB_LPC_FRAME#, ILB_LPC_SERIRQ, ILB_LPC_CLKRUN#))
132
Table 88 LPC Signal Group DC Specification LPC_V1P8V3P3_S = 3.3V
(ILB_LPC_AD[3:0], ILB_LPC_FRAME#, ILB_LPC_CLKRUN#) ....................... 133
Table 89 SPI Signal Group DC Specification (PCU_SPI_MISO, PCU_SPI_CS[1:0]#,
PCU_SPI_MOSI, PCU_SPI_CLK) .............................................................. 133
Table 90 Power Management 1.8V Suspend Well Signal Group DC Specification ......... 134
Table 91 PMC_RSTBTN# 1.8V Core Well Signal Group DC Specification ..................... 135

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 Table 92 Power Management & RTC Well Signal Group DC Specification
(PMC_RSMRST#, PMC_CORE_PWROK, ILB_RTC_RST#)............................. 135
Table 93 iLB RTC Well DC Specification (ILB_RTC_TEST#) ...................................... 135
Table 94 ILB RTC Oscillator Optional DC Specification (ILB_RTC_X1) ........................ 135
Table 95 PROCHOT# Signal Group DC Specification ............................................... 136
Table 96 SVID Signal Group DC Specification (SVID_DATA, SVID_CLK,
SVID_ALERT#) .................................................................................... 136
Table 97 GPIO 1.8V Core Well Signal Group DC Specification (GPIO_S0_SC[101:0]) .. 137
Table 98 GPIO 1.8V Suspend Well Signal Group DC Specification (GPIO_S5[43:0]) .... 137
Table 99 I2C Signal Electrical Specifications .......................................................... 138
Table 100 Crystal Clock Timings............................................................................ 139
Table 101 19.2 MHz Platform Clock AC Specification ................................................ 140
Table 102 25 MHz Platform Clock AC Specification ................................................... 140
Table 103 SVID AC Specification ........................................................................... 141
Table 104 DDR3L Interface Timing Specification...................................................... 142
Table 105 DDI Main Transmitter AC specification..................................................... 148
Table 106 DDI AUX Channel AC Specification .......................................................... 149
Table 107 R,G,B / VGA DAC Display AC Specification ............................................... 150
Table 108 VGA_HSYNC and VGA_VSYNC AC Specification ......................................... 151
Table 109 VGA_DDCDATA, and VGA_DDCCLK Timing Specification ............................ 151
Table 110 MIPI-CSI-2 Receiver Characteristics........................................................ 152
Table 111 MIPI-CSI-2 Clock Signal Specification...................................................... 153
Table 112 MIPI CSI 2 Data Clock Timing Specifications ............................................ 153
Table 113 SD Card AC Specification....................................................................... 154
Table 114 SD Card Default Speed AC Specification .................................................. 156
Table 115 SD Card High Speed AC Specification ...................................................... 158
Table 116 SDIO AC Specification ........................................................................... 159
Table 117 eMMC 4.5 AC Characteristics.................................................................. 162
Table 118 eMMC 4.5 AC Characteristics.................................................................. 164
Table 119 SATA Specification and Interface Timings ................................................ 165
Table 120 USB 2.0 AC specification (HIGH SPEED) .................................................. 167
Table 121 USB 2.0 AC specification (FULL SPEED) ................................................... 168
Table 122 USB 2.0 AC specification (LOW SPEED) ................................................... 168
Table 123 ULPI Signals AC Specification ................................................................. 171
Table 124 HDA_SDO 1.5V Buffer AC Specification ................................................... 173
Table 125 HDA_SDI[x] 1.5V Buffer AC Specification ................................................ 174
Table 126 1.5V Parameters for Maximum AC Signalling Waveforms ........................... 176
Table 127 Resistance value for the AC rating Waveform ........................................... 176
Table 128 I2S AC Timings .................................................................................... 177
Table 129 I2S Master Mode AC Timing ................................................................... 179
Table 130 PCI Express* Interface Timings .............................................................. 180
Table 131 SUS Clock Timings ............................................................................... 182
Table 132 SPI AC Specifications ............................................................................ 182
Table 133 SPI NOR AC Specifications ..................................................................... 182
Table 134 SMBUS Clock Signal Timings .................................................................. 185
Table 135 SMBus Timing...................................................................................... 185
Table 136 LPC AC Specifications (with loop back from ILB_LPC_CLK[0] to
ILB_LPC_CLK[1]) ................................................................................. 186
Table 137 I2C Fast/Standard Mode AC Specifications ............................................... 188
Table 138 AC Specification for High Speed Mode I2C—Bus Devices ............................ 191
Table 139 UART AC Specification........................................................................... 193
Table 140 JTAG AC Specification ........................................................................... 193
Table 141 Boundary Scan AC Specification ............................................................. 194

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Datasheet 15
 Table 142 Ball Listing by Location with GPIO Muxed Functions ................................... 202
Table 143 Memory Channel 0 DDR3L Signals........................................................... 264
Table 144 .......................................................................................................... 265
Table 145 ECC Signals and Memory Channel 1 Signal Muxing .................................... 267
Table 146 ECC Signals ......................................................................................... 267
Table 147 Supported DDR3L DRAM Devices ............................................................ 268
Table 148 Supported DDR3L Memory Size Per Rank ................................................. 268
Table 149 Supported DDR3L ECC Memory Size Per Rank .......................................... 268
Table 150 Supported DDR3L SO-DIMM Size ............................................................ 268
Table 151 Summary of Message Bus Registers—0x00............................................... 272
Table 152 Summary of Transaction Router I/O Registers—........................................ 274
Table 153 Summary of Transaction Router PCI Configuration Registers—0/0/0 ............ 276
Table 154 Analog Display Interface Signals ............................................................. 282
Table 155 Analog Port Characteristics..................................................................... 283
Table 156 Display Physical Interfaces Signal Names ................................................. 284
Table 157 Hardware Accelerated Video Decode Codec Support .................................. 292
Table 158 Summary of Graphics, Video and Display PCI Configuration Registers—0/2/0 294
Table 159 Summary of Display Memory Mapped I/O Registers—GTTMMADR_LSB ......... 320
Table 160 Summary of Display Memory Mapped I/O Registers—GTTMMADR_LSB ......... 502
Table 161 Summary of Display Memory Mapped I/O Registers—GTTMMADR_LSB ......... 862
Table 162 Summary of Display Memory Mapped I/O Registers—GTTMMADR_LSB ......... 868
Table 163 CSI Signals .......................................................................................... 873
Table 164 GPIO Signals........................................................................................ 873
Table 165 Imaging Capabilities.............................................................................. 875
Table 166 Summary of Image Signal Processor PCI Configuration Registers—0/2/0 ...... 885
Table 167 Summary of Image Signal Processor Memory Mapped I/O
Registers—ISPMMADR ........................................................................... 911
Table 168 eMMC Signals..................................................................................... 1580
Table 169 SDIO Signals...................................................................................... 1580
Table 170 SD Card Signals ................................................................................. 1581
Table 171 Summary of eMMC PCI Configuration Registers—0/16/0 .......................... 1587
Table 172 Summary of eMMC Memory Mapped I/O Registers—BAR .......................... 1598
Table 173 Summary of SDIO PCI Configuration Registers—0/17/0 ........................... 1631
Table 174 Summary of SDIO Memory Mapped I/O Registers—BAR ........................... 1642
Table 175 Summary of SD PCI Configuration Registers—0/18/0............................... 1675
Table 176 Summary of SD Memory Mapped I/O Registers—BAR .............................. 1686
Table 177 Summary of eMMC 4.5 PCI Configuration Registers—0/23/0 ..................... 1719
Table 178 Summary of eMMC 4.5 Memory Mapped I/O Registers—BAR..................... 1731
Table 179 Signals .............................................................................................. 1765
Table 180 SATA Feature List ............................................................................... 1765
Table 181 SATA/AHCI Feature Matrix ................................................................... 1766
Table 182 Summary of SATA PCI Configuration Registers—0/19/0 ........................... 1769
Table 183 Summary of SATA Legacy I/O Registers—LBAR....................................... 1798
Table 184 Summary of SATA Index Pair I/O Registers—ABAR .................................. 1803
Table 185 Summary of SATA AHCI Memory Mapped I/O Registers—ABAR ................. 1805
Table 186 Summary of SATA Primary Read Command I/O Registers—PCMDIDEBA ..... 1841
Table 187 Summary of SATA Primary Write Command I/O Registers—PCMDIDEBA..... 1846
Table 188 Summary of SATA Primary Read Control I/O Registers—PCTLIDEBA .......... 1848
Table 189 Summary of SATA Primary Write Control I/O Registers—PCTLIDEBA .......... 1849
Table 190 Summary of SATA Secondary Read Command I/O Registers—SCMDIDEBA . 1850
Table 191 Summary of SATA Secondary Write Command I/O Registers—SCMDIDEBA. 1855
Table 192 Summary of SATA Secondary Read Control I/O Registers—SCTLIDEBA ...... 1857
Table 193 Summary of SATA Secondary Write Control I/O Registers—SCTLIDEBA ...... 1858

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16 Datasheet
 Table 194 Summary of SATA Lane 0 Electrical Message Bus Registers—0xA3 (Global
Offset 2200h) .....................................................................................1859
Table 195 Summary of SATA Lane 0 Electrical Message Bus Registers—0xA3 (Global
Offset 2280h) .....................................................................................1889
Table 196 Summary of SATA Lane 1 Electrical Message Bus Registers—0xA3 (Global
Offset 2400h) .....................................................................................1907
Table 197 Summary of SATA Lane 1 Electrical Message Bus Registers—0xA3 (Global
Offset 2480h) .....................................................................................1937
Table 198 USB 3 SS Signals ................................................................................1955
Table 199 USB 2 FS/HS Signals ...........................................................................1955
Table 200 USB 2 HSIC Signals .............................................................................1955
Table 201 Summary of USB xHCI PCI Configuration Registers—0/20/0......................1961
Table 202 Summary of USB xHCI Memory Mapped I/O Registers—MBAR ...................1997
Table 203 Summary of USB EHCI PCI Configuration Registers—0/29/0......................2164
Table 204 Summary of USB EHCI Memory Mapped I/O Registers—MBAR ...................2182
Table 205 USB 3.0 Device Signals ........................................................................2219
Table 206 USB ULPI Device Signals ......................................................................2219
Table 207 Summary of USB 3.0 Device PCI Configuration Registers—0/22/0..............2223
Table 208 Summary of USB 3.0 Device PCI Configuration Registers—0/22/0..............2232
Table 209 Summary of USB 3.0 Device Memory Mapped I/O Registers—BAR .............2237
Table 210 Summary of USB 3.0 Device Memory Mapped I/O Registers—BAR .............2430
Table 211 Signals ..............................................................................................2451
Table 212 Summary of HD Audio PCI Configuration Registers—0/27/0 ......................2455
Table 213 Summary of HD Audio Memory Mapped I/O Registers—AZLBAR.................2486
Table 214 LPE Signals.........................................................................................2583
Table 215 Clock Frequencies ...............................................................................2589
Table 216 M/N Values, Examples .........................................................................2591
Table 217 M/N Configurable Fields .......................................................................2592
Table 218 Programmable Protocol Parameters .......................................................2597
Table 219 Summary of Low Power Audio PCI Configuration Registers—0/21/0............2603
Table 220 Summary of Memory Mapped I/O Registers—0/21/0 ................................2611
Table 221 Summary of LPE Shim Memory Mapped I/O Registers—BAR ......................2622
Table 222 Summary of Low Power Audio I2S0 Memory Mapped I/O Registers—BAR ....2649
Table 223 Summary of Low Power Audio I2S0 Memory Mapped I/O Registers—BAR ....2669
Table 224 Summary of Low Power Audio I2S0 Memory Mapped I/O Registers—BAR ....2689
Table 225 Summary of Low Power Audio DMA0 Memory Mapped I/O Registers—
lpe_bridge.BAR ...................................................................................2709
Table 226 Summary of Low Power Audio DMA1 Memory Mapped I/O Registers—
lpe_bridge.BAR ...................................................................................2822
Table 227 Signals ..............................................................................................2938
Table 228 Possible Interrupts Generated From Events/Packets .................................2940
Table 229 Interrupt Generated for INT[A-D] Interrupts ...........................................2940
Table 230 Summary of PCI Express* PCI Configuration Registers—0/28/0 .................2944
Table 231 Summary of PCI Express* Lane 0 Electrical Message Bus Registers—0xA6
(Global Offset 200h) ............................................................................2987
Table 232 Summary of PCI Express* Lane 0 Electrical Message Bus Registers—0xA6
(Global Offset 280h) ............................................................................3017
Table 233 Summary of PCI Express* Lane 1 Electrical Message Bus Registers—0xA6
(Global Offset 400h) ............................................................................3035
Table 234 Summary of PCI Express* Lane 1 Electrical Message Bus Registers—0xA6
(Global Offset 480h) ............................................................................3065
Table 235 Summary of PCI Express* Lane 2 Electrical Message Bus Registers—0xA6
(Global Offset 600h) ............................................................................3083

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Datasheet 17
 Table 236 Summary of PCI Express* Lane 2 Electrical Message Bus Registers—0xA6
(Global Offset 680h) ........................................................................... 3113
Table 237 Summary of PCI Express* Lane 3 Electrical Message Bus Registers—0xA6
(Global Offset 800h) ........................................................................... 3131
Table 238 Summary of PCI Express* Lane 3 Electrical Message Bus Registers—0xA6
(Global Offset 880h) ........................................................................... 3161
Table 239 Summary of SIO HSUART, PWM, and SPI DMA PCI Configuration
Registers—0/30/0............................................................................... 3179
Table 240 Summary of SIO HSUART, PWM, and SPI DMA Memory Mapped I/O
Registers—BAR................................................................................... 3188
Table 241 Summary of I2C DMA PCI Configuration Registers—0/24/0 ....................... 3360
Table 242 Summary of SIO I2C DMA Memory Mapped I/O Registers—BAR ................ 3369
Table 243 SPI Modes ......................................................................................... 3543
Table 244 Summary of SIO SPI PCI Configuration Registers—0/30/5........................ 3546
Table 245 Summary of SIO SPI Memory Mapped I/O Registers—BAR ....................... 3555
Table 246 I2C[6:0] Signals ................................................................................. 3571
Table 247 I2C Definition of Bits in First Byte.......................................................... 3575
Table 248 Summary of SIO I2C0 PCI Configuration Registers—0/24/1 ...................... 3582
Table 249 Summary of SIO I2C0 Memory Mapped I/O Registers—BAR ...................... 3591
Table 250 Summary of SIO I2C1 PCI Configuration Registers—0/24/2 ...................... 3630
Table 251 Summary of SIO I2C1 Memory Mapped I/O Registers—BAR ...................... 3639
Table 252 Summary of SIO I2C2 PCI Configuration Registers—0/24/3 ...................... 3678
Table 253 Summary of SIO I2C2 Memory Mapped I/O Registers—BAR ...................... 3687
Table 254 Summary of SIO I2C3 PCI Configuration Registers—0/24/4 ...................... 3726
Table 255 Summary of SIO I2C3 Memory Mapped I/O Registers—BAR ...................... 3735
Table 256 Summary of SIO I2C4 PCI Configuration Registers—0/24/5 ...................... 3774
Table 257 Summary of SIO I2C4 Memory Mapped I/O Registers—BAR ...................... 3783
Table 258 Summary of SIO I2C5 PCI Configuration Registers—0/24/6 ...................... 3822
Table 259 Summary of SIO I2C5 Memory Mapped I/O Registers—BAR ...................... 3831
Table 260 Summary of SIO I2C6 PCI Configuration Registers—0/24/7 ...................... 3870
Table 261 Summary of SIO I2C6 Memory Mapped I/O Registers—BAR ...................... 3879
Table 262 UART 1 Interface Signals ..................................................................... 3918
Table 263 UART 2 Interface Signals ..................................................................... 3919
Table 264 Baud Rates Achievable with Different DLAB Settings ................................ 3920
Table 265 Summary of SIO HSUART1 PCI Configuration Registers—0/30/3 ............... 3924
Table 266 Summary of SIO HSUART1 Memory Mapped I/O Registers—BAR ............... 3933
Table 267 Summary of HSUART2 PCI Configuration Registers—0/30/4 ..................... 3967
Table 268 Summary of HSUART2 Memory Mapped I/O Registers—BAR ..................... 3976
Table 269 Example PWM Output Frequency and Resolution ..................................... 4012
Table 270 Summary of SIO PWM0 PCI Configuration Registers—0/30/1 .................... 4014
Table 271 Summary of SIO PWM0 Memory Mapped I/O Registers—BAR.................... 4023
Table 272 Summary of SIO PWM1 PCI Configuration Registers—0/30/2 .................... 4026
Table 273 Summary of SIO PWM1 Memory Mapped I/O Registers—BAR.................... 4035
Table 274 BBS Configurations ............................................................................. 4040
Table 275 Summary of PCU iLB LPC Port 80h I/O Registers— .................................. 4041
Table 276 PMC Signals ....................................................................................... 4048
Table 277 Transitions Due to Power Failure ........................................................... 4051
Table 278 Transitions Due to Power Button ........................................................... 4052
Table 279 System Power Planes .......................................................................... 4053
Table 280 Causes of SMI and SCI ........................................................................ 4056
Table 281 INIT# Assertion Causes ....................................................................... 4059
Table 282 Summary of PCU iLB PMC Memory Mapped I/O
Registers—PMC_BASE_ADDRESS .......................................................... 4060
Table 283 Summary of PCI iLB PMC I/O Registers .................................................. 4094

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 Table 284 Summary of PCU iLB PMC I/O Registers—ACPI_BASE_ADDRESS................4097
Table 285 SPI Signals.........................................................................................4115
Table 286 SPI Flash Regions................................................................................4116
Table 287 Region Size Versus Erase Granularity of Flash Components .......................4118
Table 288 Region Access Control..........................................................................4120
Table 289 Hardware Sequencing Commands and Opcode Requirements ....................4124
Table 290 Recommended Pinout for 8-Pin Serial Flash Device ..................................4127
Table 291 Recommended Pinout for 16-Pin Serial Flash Device.................................4127
Table 292 Summary of PCU SPI for Firmware Memory Mapped I/O Registers—
SPI_BASE_ADDRESS ...........................................................................4130
Table 293 UART Signals ......................................................................................4163
Table 294 Baud Rate Examples ............................................................................4164
Table 295 Register Access List .............................................................................4167
Table 296 Summary of PCU iLB UART I/O Registers— .............................................4168
Table 297 SMBus Signal Names ...........................................................................4178
Table 298 I2C Block Read....................................................................................4183
Table 299 Enable for PCU_SMB_ALERT# ...............................................................4185
Table 300 Enables for SMBus Host Events .............................................................4185
Table 301 Enables for the Host Notify Command ....................................................4185
Table 302 Host Notify Format ..............................................................................4186
Table 303 Summary of PCU SMBUS PCI Configuration Registers—0/31/3...................4189
Table 304 Summary of PCU SMBUS Memory Mapped I/O
Registers—SMB_Config_MBARL .............................................................4202
Table 305 Summary of PCU SMBUS I/O Registers—SMB_Config_IOBAR ....................4214
Table 306 iLB Signals .........................................................................................4227
Table 307 NMI Sources .......................................................................................4228
Table 308 Summary of PCU iLB Interrupt Decode and Route Memory Mapped I/O
Registers—ILB_BASE_ADDRESS ............................................................4229
Table 309 LPC Signals ........................................................................................4263
Table 310 SERIRQ, Stop Frame Width to Operation Mode Mapping ...........................4267
Table 311 SERIRQ Interrupt Mapping....................................................................4267
Table 312 Summary of PCU iLB Low Pin Count (LPC) Bridge PCI Configuration
Registers—0/31/0 ...............................................................................4272
Table 313 Summary of PCU iLB LPC BIOS Control Memory Mapped I/O Registers—
RCRB_BASE_ADDRESS ........................................................................4291
Table 314 RTC Signals ........................................................................................4293
Table 315 Register Bits Reset by ILB_RTC_RST# Assertion ......................................4295
Table 316 I/O Registers Alias Locations.................................................................4296
Table 317 RTC Indexed Registers .........................................................................4297
Table 318 Summary of PCU iLB Real Time Clock (RTC) I/O Registers—......................4298
Table 319 8254 Signals ......................................................................................4300
Table 320 Counter Operating Modes .....................................................................4302
Table 321 Register Aliases ..................................................................................4304
Table 322 Summary of PCU iLB 8254 Timers I/O Registers— ...................................4305
Table 323 8254 Interrupt Mapping .......................................................................4312
Table 324 Summary of PCU iLB High Performance Event Timer (HPET) Memory
Mapped I/O Registers—........................................................................4313
Table 325 GPIO Signals ......................................................................................4321
Table 326 Summary of PCU iLB GPIO IO Registers—GPIO_BASE_ADDRESS ...............4325
Table 327 Summary of PCU iLB GPIO Memory Mapped I/O Registers—
IO_CONTROLLER_BASE_ADDRESS ........................................................4341
Table 328 Summary of PCU iLB GPIO IO Registers—GPIO_BASE_ADDRESS ...............4800
Table 329 Summary of PCU iLB GPIO Memory Mapped I/O Registers—
IO_CONTROLLER_BASE_ADDRESS ........................................................4809

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 Table 330 Summary of PCU iLB I/O APIC Memory Mapped I/O Registers— ................ 5030
Table 331 Interrupt Controller Connections ........................................................... 5032
Table 332 Interrupt Status Registers.................................................................... 5033
Table 333 Content of Interrupt Vector Byte ........................................................... 5034
Table 334 I/O Registers Alias Locations ................................................................ 5039
Table 335 Summary of PCU iLB 8259 Interrupt Controller (PIC) I/O Registers— ......... 5041

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20 Datasheet
Revision History
Revision
Description Revision Date
Number

1.0 Initial release. October 2013

§§

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Datasheet 21
 Introduction

1 Introduction
The Intel® Atom™ Processor E3800 Product Family is the Intel Architecture (IA) SoC
that integrates the next generation Intel® processor core, Graphics, Memory Controller,
and I/O interfaces into a single system-on-chip solution.

The figures below show the system level block diagram of the SoC. Refer to the
subsequent chapters for detailed information on the functionality of the different
interface blocks.

Notes: Throughout this document Intel® Atom™ Processor E3800 Product Family is referred to
as the SoC or Processor.

This datasheet details features of the silicon only. For platform support and software,
please contact your Intel representative.

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22 Datasheet
Introduction

Figure 1. SoC Block Diagram

IO JTAG

OOE Intel® OOE Intel® OOE Intel® OOE Intel®

AtomTM AtomTM AtomTM AtomTM
Processor Core Processor Core Processor Core Processor Core

1MiB L2 1MiB L2

Video P-Unit

IO
3D Graphics SVID

DDI SoC
Display

IO 2
Channel

Controller
Transaction

Memory
IO
0
IO VGA Router
Channel IO
1
MIPI-CSI
Camera

IO 3
ISP

IO GPIO Integrated Clock O

IO HD Audio APIC
8259
Platform Control Unit

HPET
LPE

IO 3 I2S/PCM
ILB

8254 O

RTC IO
O 2 PWM
GPIO IO
IO 2 HSUART
SIO

LPC IO
IO SPI
PMC IO
IO 7 I2C I/O
SPI IO
Fabric
UART IO
IO 4 PCIe*
SMB IO

IO 2 SATA 3.0 (SS) IO

1/2/3
USB

1/2.0 (HS/FS) 4 IO

2.0 (HSIC) 2 IO

3.0 (SS) IO
USB
Dev

IO 3 SD/MMC ULPI (HS/FS) IO

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 Introduction

1.1 Terminology
Term Description

ACPI Advanced Configuration and Power Interface

Cold Reset Full reset is when PWROK is de-asserted and all system rails except VCCRTC are
powered down
CRT Cathode Ray Tube
CRU Clock Reset Unit
DP Display Port
DTS Digital Thermal Sensor
EIOB Electronic In/Out Board
EMI Electro Magnetic Interference
eDP embedded Display Port
HDMI High Definition Multimedia Interface. HDMI supports standard, enhanced, or high-
definition video, plus multi-channel digital audio on a single cable. HDMI transmits
all Advanced Television Systems Committee (ATSC) HDTV standards and supports
8-channel digital audio, with bandwidth to spare for future requirements and
enhancements (additional details available at http://www.hdmi.org/).
IGD Internal Graphics Unit
Intel® TXE Intel® Trusted Execution Engine
LCD Liquid Crystal Display
LPE Low Power Engine
MIPI CSI MIPI Camera Interface Specification
MPEG Moving Picture Experts Group
MSI Message Signaled Interrupt. MSI is a transaction initiated outside the host,
conveying interrupt information to the receiving agent through the same path that
normally carries read and write commands.
MSR Model Specific Register, as the name implies, is model-specific and may change
from processor model number (n) to processor model number (n+1). An MSR is
accessed by setting ECX to the register number and executing either the RDMSR
or WRMSR instruction. The RDMSR instruction will place the 64 bits of the MSR in
the EDX: EAX register pair. The WRMSR writes the contents of the EDX: EAX
register pair into the MSR.
PCIe* PCI Express* (PCIe*) is a high-speed serial interface. The PCIe* configuration is
software-compatible with the existing PCI specifications.
PWM Pulse Width Modulation
Rank A unit of DRAM corresponding to the set of SDRAM devices that are accessed in
parallel for a given transaction. For a 64-bit wide data bus using 8-bit (x8) wide
SDRAM devices, a rank would be eight devices. Multiple ranks can be added to
increase capacity without widening the data bus, at the cost of additional electrical
loading.
SCI System Control Interrupt. SCI is used in the ACPI protocol.
SDRAM Synchronous Dynamic Random Access Memory
SERR System Error. SERR is an indication that an unrecoverable error has occurred on
an I/O bus.

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Introduction

Term Description

SMC System Management Controller or External Controller refers to a separate system

management controller that handles reset sequences, sleep state transitions, and
other system management tasks.
SMI System Management Interrupt is used to indicate any of several system conditions
(such as thermal sensor events, throttling activated, access to System
Management RAM, chassis open, or other system state related activity).
SIO Serial I/O
TMDS Transition-Minimized Differential Signaling. TMDS is a serial signaling interface
used in DVI and HDMI to send visual data to a display. TMDS is based on low-
voltage differential signaling with 8/10b encoding for DC balancing.
VCO Voltage Controlled Oscillator
Warm Warm reset is a reset of the SoC without removing power (internal only reset for
Reset SoC’s).

1.2 Feature Overview

All features subject to software availability.

1.2.1 Processor Core

See Chapter 11, “Processor Core” for more details.
• Up to four IA-compatible low power Intel® processor cores
— One thread per core
• Two-wide instruction decode, out of order execution
• On-die, 32 KB 8-way L1 instruction cache and 24 KB 6-way L1 data cache per core
• On-die, 1 MB, 16-way L2 cache, shared per two cores
• 36-bit physical address, 48-bit linear address size support
• Supported C-states: C0, C1, C1E, C6
• Supports Intel® Virtualization Technology (Intel® VT-x)

1.2.2 System Memory Controller

See Chapter 12, “System Memory Controller” for more details.
• Supports up to two channels of DDR3L
• 64 bit data bus for each channel
• ECC supported in single channel mode only
• Supports x8 and x16 DDR3L-RS SDRAM device data widths
• Supports DDR3L-RS with 1066 or 1333 MT/s data rates
— Total memory bandwidth supported is 8.5 GB/s (for 1066 MT/s single channel)
scalable to 21.3GB/s(for 1333 MT/s dual channel)

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 Introduction

• Supports different physical mappings of bank addresses to optimize performance

• Out-of-order request processing to increase performance
• Aggressive power management to reduce power consumption
• Proactive page closing policies to close unused pages

1.2.3 Display Controller

See Chapter 14, “Graphics, Video and Display” for more details.
• Support 2 DDI ports to enable eDP 1.3, DP 1.1a, DVI, or HDMI 1.4a
• Support 2 panel power sequence for 2 eDP ports
• Support Audio on DP and HDMI
• Supports Intel® Display Power Saving Technology (DPST) 6.0, Panel Self Refresh
(PSR) and Display Refresh Rate Switching Technology (DRRS)
• Supports one VGA port

1.2.4 Graphics and Media Engine

See Chapter 14, “Graphics, Video and Display” for more details.
• Intel's 7th generation (Gen 7) graphics and media encode/decode engine
• VED video decoder in addition to Gen 7 Media decoder
• Supports DX*11, OpenGL 3.0 (OGL 3.0), OpenCL 1.2 (OCL 1.2), OpenGLES 2.0
(OGLES 2.0)
• GPU shader is capable of up to 8 gigaflops
• 4x anti-aliasing
• Full HW acceleration for decode of H.264, MPEG2, MVC, VC-1, VP8, MJPEG
• Full HW acceleration for encode of H.264, MPEG2, MVC
• Supports 2.0 Stereoscopic 3D Stretch
• Polyphase 8 tap scaling
• HD HQV

1.2.5 Image Signal Processor

See Chapter 15, “MIPI-Camera Serial Interface (CSI) & ISP” for more details.
• Support up to three MIPI CSI ports
• Support for up to 24MP sensors
• Supports Stereoscopic Video

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Introduction

1.2.6 Power Management

See Chapter 6, “Power Management” for more details.
• ACPI 5.0 support
• Processor states: C0-C6
• Display device states: D0, D3
• Graphics device states: D0, D3
• System sleep states: S0, S3, S4, S5
• Dynamic I/O power reductions (disabling sense amps on input buffers, tristating
output buffers)
• Conditional memory self-refresh during C2
• Active power-down of display links
• Downloadable power management firmware

1.2.7 PCI Express*

The SoC has four PCI Express* lanes and up to four PCI Express root ports, each
supporting the PCI Express Base specification Rev 2.0 at a maximum of 5 Gbit/s data
transfer rates.The root ports configurations are flexible and can be configured to be (4)
x1, (2) x2’s, (1) x2 plus (2) x1’s, and (1) x4.

See Chapter 23, “PCI Express* 2.0” for more details.

1.2.8 SATA
See Chapter 17, “Serial ATA (SATA)” for more details.
• Two (2) SATA Revision 2.0 ports (eSATA capable)
• Legacy IDE (including IRQ)/Native IDE/AHCI appearance to OS
• Partial/Slumber power management modes with wake
• Capable of 3 Gbit/s transfer rate
• Supports RunTime D3

1.2.9 USB xHCI Controller

See Chapter 18, “USB Host Controller Interfaces (xHCI, EHCI)” for more details.
• Supports USB 3.0/2.0/1.1
• Implements xHCI software host controller interface
• One USB 3.0 Super Speed (SS) port
• Four ports multiplexed with EHCI controller that are High Speed/Full Speed (HS/FS)
• Two High Speed Inter Chip (HSIC) ports compliant with USB 2.0

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 Introduction

1.2.10 USB 2.0 EHCI Controller

See Chapter 18, “USB Host Controller Interfaces (xHCI, EHCI)” for more details.
• Internal Rate Matching Hub to support USB 1.1 to 2.0 devices
• Four Ports multiplexed with xHCI controller
• Enhanced EHCI descriptor caching

1.2.11 USB 2.0 (ULPI) and 3.0 Device

See Chapter 19, “USB Device Controller Interfaces (3.0, ULPI)” for more details.
• Supports one USB 3.0 SS port with USB device compatibility
• Supports one ULPI port with HS/LS support

1.2.12 Audio Controllers

1.2.12.1 Low Power Engine (LPE) Audio

LPE is a complete audio solution based on an internal audio processing engine, which
includes three I2S output ports. See Chapter 21, “Low Power Engine (LPE) for Audio
(I2S)” for more details.

LPE supports:
• I2S and DDI with dedicated DMA
• MP3, AAC, AC3/DD+, WMA9, PCM (WAV)

Note: Codecs supported depend on software and may be different.

1.2.12.2 Intel® High Definition Audio (Intel® HD Audio)

See Chapter 20, “Intel® High Definition Audio” for more details.
• Four in + four out streams (Only 3 used)
• One stream for each DDI, available for HDMI and DP
• No wake on audio (modem) support

1.2.13 Storage Control Cluster (eMMC, SDIO, SD)

See Chapter 16, “Storage Control Cluster (eMMC, SDIO, SD Card)” for more details.
• Supports one SDIO 3.0 controller
• Supports one eMMC 4.5 controller
• Supports one SDXC controller

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Introduction

1.2.14 Intel® Trusted Execution Engine (Intel® TXE)

Intel TXE system contains a security engine and additional hardware security features
that enable a secure and robust platform.

See Chapter 22, “Intel® Trusted Execution Engine (Intel® TXE)” for more details.

Security features include:

• Isolated execution environment for crypto operations (SKU-enabled)
• Supports secure boot - with customer programmable keys to secure code

Note: The SoC requires TXE firmware in the PCU SPI flash image to function.

1.2.15 Serial I/O (SIO)

See Chapter 24, “Serial IO (SIO) Overview” for links to more information about each
interface.
• Controller for external devices via SPI, UART, I2C or PWM
• Each port is multiplexed with general purpose I/O for configurations flexibility
• Supports up to 7 I2C, 2 HSUART, 2 PWM, 1 SPI interface

1.2.16 Platform Control Unit (PCU)

The platform controller unit is a collection of HW blocks, including SMBus, UART,
debug/boot SPI and Intel legacy block (iLB), that are critical to implement a Windows*
compatible platform. See Chapter 29, “Platform Controller Unit (PCU) Overview” for
links to more information about each interface.

Key PCU features include:

• SMBus Host controller - supports SMBus 2.0 specification
• Universal Asynchronous Receiver/Transmitter (UART) with COM1 interface
• A Serial Peripheral Interface (SPI) for Flash only - stores boot FW and system
configuration data
• Intel Legacy Block (iLB) supports legacy PC platform features
— RTC, Interrupts, Timers, General Purpose I/Os (GPIO) and Peripheral interface
(LPC for TPM) blocks.

1.2.17 Package
This SoC is packaged in a Flip-Chip Ball Grid Array (FCBGA) package with 1170 solder
balls with 0.593 mm (minimum) ball pitch. The package dimensions are 25mm x
27mm. See Chapter 10, “Ballout and Package Information” for more details.

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 Introduction

1.2.18 SKU List

Core GFX
Processor TDP Tj DDR
SKU CPU LFM (MHz)/ Normal / Burst
Number (W) (°C) (MT/s)
HFM (GHz) (MHz)

Premium E3845 4 10 500 / 1.91 -40 to 110 542 / 792 1333

Hi E3827 2 8 500 / 1.75 -40 to 110 542 / 792 1333

Intermediate E3826 2 7 533 / 1.46 -40 to 110 533 / 667 1066

Mid E3825 2 6 533 / 1.33 -40 to 110 533 / NA 1066

Entry E3815 1 5 533 / 1.46 -40 to 110 400 / NA 1066

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Physical Interfaces

2 Physical Interfaces
Many interfaces contain physical pins. These groups of pins make up the physical
interfaces. Because of the large number of interfaces and the small size of the package,
Some interfaces share their pins with GPIOs, while others use dedicated physical pins.
This chapter summarizes the physical interfaces, including the diversity in GPIO
multiplexing options.

Figure 2. Signals (1 of 2)

DRAM[1:0]_DQ[63:0] DDI[1:0]_TXP/N[3:0]
DRAM[1:0]_DQSP/N[7:0] Atom™ DDI[1:0]_AUXN
DRAM[1:0]_DM[7:0] Cores DDI[1:0]_AUXP
DRAM[1:0]_CS[2,0]# Direct DDI[1:0]_DDCCLK
DRAM[1:0]_CKP/N[2,0] Display DDI[1:0]_DDCDATA
DRAM[1:0]_CKE[2,0] Interface DDI[1:0]_HPD

Display
DRAM[1:0]_ODT[2,0] DDI[1:0]_VDDEN
DRAM[1:0]_MA[15:00] Dual Channel DDI[1:0]_BKLTEN
DDR3L Memory
DRAM[1:0]_RAS# Interface DDI[1:0]_BKLTCTL
DRAM[1:0]_CAS#
VGA_R/G/B
DRAM[1:0]_WE#
VGA_HSYNC
DRAM[1:0]_BS[2:0]
VGA VGA_VSYNC
DRAM[1:0]_DRAMRST#
VGA_DDCDATA
DRAM_CORE_PWROK
VGA_DDCCLK
DRAM_VDD_S4_PWROK
DRAM_VREF

MCSI1_DP/N[3:0] TAP_TDI
MCSI1_CLKP/N TAP_TDO
MCSI2_DP/N[0] TAP_TMS
MIPI CSI JTAG/Debug
MCSI2_CLKP/N TAP_TCK
Port
MCSI3_CLKP/N TAP_TRST#
MCSI_GPIO[11:00] TAP_PREQ#
TAP_PRDY#
PROCHOT#

SVID_DATA Processor
Power/Thermal
SVID_CLK ICLK_OSCIN
Integrated Clock
SVID_ALERT# ICLK_OSCOUT

Continued in Figure Below

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 Physical Interfaces

Figure 3. Signals (2 of 2)

Continued in Figure Above

HDA_SDO Speaker ILB_8254_SPKR

HDA_SDI[1:0]
ILB_LPC_AD[3:0]
HDA_SYNC HD Audio
ILB_LPC_FRAME#
HDA_CLK
LPC ILB_LPC_CLK[1:0]

Legacy (ILB)
HDA_RST#
ILB_LPC_CLKRUN#
ILB_LPC_SERIRQ
LPE_I2S2_DATAIN
LPE_I2S2_DATAOUT I2S ILB_RTC_RST#
LPE_I2S2_FRM (LPE Audio) ILB_RTC_TEST#
LPE_I2S2_CLK RTC ILB_RTC_EXTPAD
ILB_RTC_X1
ILB_RTC_X2

SIO_I2C[6:0]_CLK USB_DP/N[3:0]
I2C
SIO_I2C[6:0]_DATA USB 2.0 USB_OC[1:0]#
USB_PLL_MON
SIO_PWM[1:0] PWM
Serial IO (SIO)

USB 2.0 USB_HSIC[1:0]_DATA

SIO_SPI_MISO
(HSIC) USB_HSIC[1:0]_STROBE
SIO_SPI_MOSI
SPI
SIO_SPI_CS# USB3_TXP/N
SIO_SPI_CLK USB 3.0 USB3_RXP/N
USB3_REXT
SIO_UART[2:1]_TXD
USB

SIO_UART[2:1]_RXD USB_ULPI_DATA[7:0]
HSUART
SIO_UART[2:1]_CTS# USB_ULPI_DIR
SIO_UART[2:1]_RTS# USB 2.0 USB_ULPI_NXT
Device USB_ULPI_STP
PCIE_TXP/N[3:0] (ULPI) USB_ULPI_CLK
PCIE_RXP/N[3:0] USB_ULPI_RST#
PCI Express
PCIE_CLKREQ[3:0]# USB_ULPI_REFCLK
PCIE_CLKP/N[3:0]
USB3DEV_TXP/N
USB 3.0
USB3DEV_RXP/N
SATA_TXP/N[1:0] Device
USB3DEV_REXT
SATA_RXP/N[1:0]
SATA
SATA_GP[1:0]
PMC_RSTBTN#
SATA_LED#
PMC_PWRBTN#
PMC_RSMRST#
MMC1_D[7:0]
PMC_SLP_S3#
MMC1_CMD
eMMC PMC_SLP_S4#
MMC1_CLK
Power PMC_SUS_STAT#
MMC1_RST#
Management PMC_SUSPWRDNACK
SD2_D[3:0] Controller PMC_SUSCLK[0]
SD/eMMC

SD2_CMD SDIO (PMC) PMC_PLT_CLK[5:0]

SD2_CLK PMC_CORE_PWROK
PMC_PLTRST#
SD3_D[3:0]
PMC_BATLOW#
SD3_CMD
PMC_ACPRESENT
SD3_CD#
SD PMC_WAKE_PCIE[0]#
SD3_WP
SD3_1P8EN
SD3_PWREN# PCU_SMB_DATA
Platform Control

SMBus PCU_SMB_CLK
GPIO_S0_SC[061:055] PCU_SMB_ALERT#
GPIO_S0_SC[093:092]
PCU_SPI_MISO
GPIO_S5[10:00] GPIO PCU_SPI_MOSI
Boot SPI
GPIO_S5[17] PCU_SPI_CS[1:0]#
GPIO_S5[30:22] PCU_SPI_CLK

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Physical Interfaces

2.1 Pin States Through Reset

This chapter describes the states of each signal before, during and directly after reset.
Additionally, Some signals have internal pull-up/pull-down termination resistors, and
their values are also provided (Term). Termination tolerances are +/- 50% unless
otherwise specified by electrical specs (PCIe*, and other differential termination). All
signals with the “†” symbol are muxed and may not be available without configuration.
See Section 2.30, “Configurable IO: GPIO Muxing” on page 54.

Table 1. Platform Power Well Definitions

Power Type Power Well Description

V1P05S 1.05 V rail. On in S0 only.

V1P0A 1.0 V rail. On in S0 through S4/5.
V1P0S 1.0 V rail. On in S0 only.
V1P24A 1.24 V rail. On in S0 through S4/5.
V1P24S 1.24 V rail. On in S0 only.
V1P35U 1.35 V rail. On in S0 through S3.
V1P8A 1.8 V rail. On in S0 through S4/5.
V1P35S 1.35 V rail. On in S0 only.
V1P8S 1.8 V rail. On in S0 only.
V3P3A 3.3 V rail. On in S0 through S4/5.
VAUD 1.5 V rail for HD Audio. 1.8 V rail for I2S. On in S0 only.
VCC Variable core rail. On in S0 only.
VLPC 1.8 or 3.3 V rail for LPC. On in S0 only.
VNN Variable rail. On in S0 only.
VPCIESATA 1.0 V rail for PCIe* and SATA. On in S0 only.
VRTC RTC voltage rail. On in S0 through G3.
VSDIO 1.8 or 3.3 V rail for SD3. On in S0 only.
VSFR 1.35 V rail for internal PLLs. On in S0 only.
VUSB2 3.3 V rail. On in S0 through S4/5.
VVGA_GPIO 3.3 V rail for VGA sideband. On in S0 only.

Table 2. Default Buffer State Definitions (Sheet 1 of 2)

Buffer State Description

High-Z The SoC places this output in a high-impedance state. For inputs, external
drivers are not expected.
Do Not Care The state of the input (driven or tristated) does not affect the SoC. For outputs,
it is assumed that the output buffer is in a high-impedance state.
VOH The SoC drives this signal high with a termination of 50 Ω.

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 Physical Interfaces

Table 2. Default Buffer State Definitions (Sheet 2 of 2)

Buffer State Description

VOL The SoC drives this signal low with a termination of 50 Ω.

Unknown The SoC drives or expects an indeterminate value.
VIH The SoC expects/requires the signal to be driven high.
VIL The SoC expects/requires the signal to be driven low.
Pull-up This signal is pulled high by a pull-up resistor (internal value specified in “Term”
column).
Pull-down This signal is pulled low by a pull-down resistor (internal value specified in
“Term” column).
Running/T The clock is toggling, or the signal is transitioning.
Off The power plane for this signal is powered down. The SoC does not drive
outputs, and inputs should not be driven to the SoC. (VSS on output)

2.2 System Memory Controller Interface Signals

See Chapter 12, “System Memory Controller” for more details.

Table 3. DDR3L System Memory Signals (Sheet 1 of 2)

Default Buffer State

Plat.
Signal Name Dir Term S4/S5 S3 Reset Enter S0 Notes
Power

DRAM0_CKP[2,0] O - V1P35U Off High-Z High-Z High-Z

DRAM0_CKN[2,0] O - V1P35U Off High-Z High-Z High-Z
DRAM0_CS#[2,0] O - V1P35U Off VOH VOH VOH
DRAM0_CKE[2,0] O - V1P35U Off VOL VOL VOL
DRAM0_CAS# O - V1P35U Off High-Z High-Z High-Z
DRAM0_RAS# O - V1P35U Off High-Z High-Z High-Z
DRAM0_WE# O - V1P35U Off High-Z High-Z High-Z
DRAM0_BS[2:0] O - V1P35U Off High-Z High-Z High-Z
DRAM0_DRAMRST# O - V1P35U Off - - -
DRAM0_ODT[2,0] O - V1P35U Off VOL VOL VOL
DRAM0_DQ[63:0] I/O - V1P35U Off High-Z High-Z High-Z
DRAM0_DM[7:0] O - V1P35U Off High-Z High-Z High-Z
DRAM0_DQSP[7:0] I/O - V1P35U Off High-Z High-Z High-Z
DRAM0_DQSN[7:0] I/O - V1P35U Off High-Z High-Z High-Z
DRAM1_CKP[2,0] O - V1P35U Off High-Z High-Z High-Z
DRAM1_CKN[2,0] O - V1P35U Off High-Z High-Z High-Z
DRAM1_CKE[2,0] O - V1P35U Off VOL VOL VOL
DRAM1_CS#[2,0] O - V1P35U Off VOH VOH VOH

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Table 3. DDR3L System Memory Signals (Sheet 2 of 2)

Default Buffer State

Plat.
Signal Name Dir Term S4/S5 S3 Reset Enter S0 Notes
Power

DRAM1_CAS# O - V1P35U Off High-Z High-Z High-Z

DRAM1_RAS# O - V1P35U Off High-Z High-Z High-Z
DRAM1_WE# O - V1P35U Off High-Z High-Z High-Z
DRAM1_BS[2:0] O - V1P35U Off High-Z High-Z High-Z
DRAM1_DRAMRST# O - V1P35U Off - - -
DRAM1_ODT[2,0] O - V1P35U Off VOL VOL VOL
DRAM1_DQ[63:0] I/O - V1P35U Off High-Z High-Z High-Z
DRAM1_DM[7:0] O - V1P35U Off High-Z High-Z High-Z
DRAM1_DQSP[7:0] I/O - V1P35U Off High-Z High-Z High-Z
DRAM1_DQSN[7:0] I/O - V1P35U Off High-Z High-Z High-Z
DRAM_VDD_S4_PWROK I - V1P35U VIL VIH Unknown VIH
DRAM_CORE_PWROK I - V1P35U VIL VIL Unknown VIH
DRAM_VREF I - V1P35U
DRAM_RCOMP[2:0] - - V1P35U

2.3 PCI Express* 2.0 Interface Signals

See Chapter 23, “PCI Express* 2.0” for more details.

Table 4. PCI Express* 2.0 Interface Signals

Default Buffer State

Plat.
Signal Name Dir Term S4/S5 S3 Reset Enter S0 Notes
Power

PCIE_TXP[3:0] O 50 VPCIESATA Off Off VOL VOL

PCIE_TXN[3:0] O 50 VPCIESATA Off Off VOL VOL
PCIE_RXP[3:0] I 50 VPCIESATA Off Off High-Z High-Z
PCIE_RXN[3:0] I 50 VPCIESATA Off Off High-Z High-Z
PCIE_CLKP[3:0] O - V1P0S Off Off Running/ Running/
VIL VIL
PCIE_CLKN[3:0] O - V1P0S Off Off Running/ Running/
VIL VIL
PCIE_CLKREQ[3:0]#† I 20k(H) V1P8S Off Off Pull_up Pull_up
PCIE_RCOMP_P/N - -
NOTE: All signals with the “†” symbol are muxed and may not be available without configuration.

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2.4 USB 2.0 Host (EHCI/xHCI) Interface Signals

See Chapter 18, “USB Host Controller Interfaces (xHCI, EHCI)” for more details.

Table 5. USB 2.0 Interface Signals

Default Buffer State

Plat.
Signal Name Dir Term S4/S5 S3 Reset Enter S0 Notes
Power

USB_DN[3:0] I/O - VUSB2

USB_DP[3:0] I/O - VUSB2
USB_OC[1:0]#† I 20k(H) V1P8A Pull-up Pull-up Pull-up Pull-up
USB_RCOMPI I - -
USB_RCOMPO O - -
NOTE: All signals with the “†” symbol are muxed and may not be available without configuration.

2.5 USB 2.0 HSIC Interface Signals

See Chapter 18, “USB Host Controller Interfaces (xHCI, EHCI)” for more details.

Table 6. USB 2.0 HSIC Interface Signals

Default Buffer State

Plat.
Signal Name Dir Term S4/S5 S3 Reset Enter S0 Notes
Power

USB_HSIC0_DATA I/O - V1P24A Running Running VOH Running

USB_HSIC0_STROBE I/O - V1P24A VOH
USB_HSIC1_DATA I/O - V1P24A VOH
USB_HSIC1_STROBE I/O - V1P24A VOH
USB_HSIC_RCOMP I - V1P24A VOH

2.6 USB 3.0 (xHCI) Host Interface Signals

Table 7. USB 3.0 Interface Signals (Sheet 1 of 2)

Default Buffer State

Plat.
Signal Name Dir Term S4/S5 S3 Reset Enter S0 Notes
Power

USB3_TXN[0] O - V1P0A
USB3_TXP[0] O - V1P0A

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Table 7. USB 3.0 Interface Signals (Sheet 2 of 2)

Default Buffer State

Plat.
Signal Name Dir Term S4/S5 S3 Reset Enter S0 Notes
Power

USB3_RXN[0] I - V1P0A
USB3_RXP[0] I - V1P0A
USB3_REXT[0] I - V1P0A VOL VOL VOH VOH

2.7 USB 2.0 Device (ULPI) Interface Signals

See Chapter 19, “USB Device Controller Interfaces (3.0, ULPI)” for more details.

Default Buffer State

Plat.
Signal Name Dir Term S4/S5 S3 Reset Enter S0 Notes
Power

USB_ULPI_CLK† I 20k(L) V1P8A Pull-down Pull-down Pull-down Pull-down Pull-down

USB_ULPI_DATA[0:7]† I/O 20k(L) V1P8A Pull-down Pull-down Pull-down Pull-down Pull-down
USB_ULPI_DIR† I - V1P8A Pull-up Pull-up Pull-up Pull-up Pull-up
USB_ULPI_NXT† I 20k(L) V1P8A Pull-down Pull-down Pull-down Pull-down Pull-down
USB_ULPI_STP† O 20k(H) V1P8A Pull-up Pull-up Pull-up Pull-up Pull-up
USB_ULPI_REFCLK† O 20k(L) V1P8A Pull-down Pull-down Pull-down Pull-down Pull-down
USB_ULPI_RST#† O - V1P8A Pull-down Pull-down Pull-down Pull-down Pull-down
NOTE: All signals with the “†” symbol are muxed and may not be available without configuration.

2.8 USB 3.0 Device Interface Signals

See Chapter 19, “USB Device Controller Interfaces (3.0, ULPI)” for more details.

Table 8. USB 3.0 Device Interface Signals

Default Buffer State

Plat.
Signal Name Dir Term S4/S5 S3 Reset Enter S0 Notes
Power

USB3DEV_TXN[0] O - V1P0S
USB3DEV_TXP[0] O - V1P0S
USB3DEV_RXN[0] I - V1P0S
USB3DEV_RXP[0] I - V1P0S
USB3DEV_REXT[0] I - V1P0S

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2.9 Serial ATA (SATA) 2.0 Interface Signals

See Chapter 17, “Serial ATA (SATA)” for more details.

Table 9. SATA 2.0 Interface Signals

Default Buffer State

Plat.
Signal Name Dir Term S4/S5 S3 Reset Enter S0 Notes
Power

SATA_TXP[1:0] O VPCIESATA Off Off

SATA_TXN[1:0] O VPCIESATA Off Off
SATA_RXP[1:0] I VPCIESATA Off Off
SATA_RXN[1:0] I VPCIESATA Off Off
SATA_LED#† O 20k(H) V1P8S Off Off Pull-up Pull-up Pull-up
SATA_GP[1:0]† I 20k(L) V1P8S Off Off Pull-down Pull-down Pull-down
SATA_DEVSLP[1:0]† O 20k(L) V1P8S Off Off Pull-down Pull-down Pull-down
SATA_RCOMP_P/N - - 1.0 V
NOTE: All signals with the “†” symbol are muxed and may not be available without configuration.

2.10 Integrated Clock Interface Signals

See Chapter 5, “Integrated Clock” for more details.

Table 10. Integrated Clock Interface Signals

Default Buffer State

Plat.
Signal Name Dir Term S4/S5 S3 Reset Enter S0 Notes
Power

ICLK_OSCIN I - Off Off Running Running

ICLK_OSCOUT O - Off Off Running Running
ICLK_ICOMP - - Off Off
ICLK_RCOMP - - Off Off
ICLK_DRAM_TERM[1:0] - - - Pull-down Pull-down Pull-down Pull-down
ICLK_USB_TERM[1:0] - - - Pull-down Pull-down Pull-down Pull-down

2.11 Display - Digital Display Interface (DDI) Signals

See Chapter 14, “Graphics, Video and Display” for more details.

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Table 11. Digital Display Interface Signals

Default Buffer State

Plat.
Signal Name Dir Term S4/S5 S3 Reset Enter S0 Notes
Power

DDI0_TXP[3:0] O V1P0S Off Off

DDI0_TXN[3:0] O V1P0S Off Off
DDI0_AUXP I/O V1P0S Off Off
DDI0_AUXN I/O V1P0S Off Off
DDI0_BKLTCTL† I/O 20k(L) V1P8S Off Off Pull-down Pull-down
DDI0_BKLTEN† I/O 20k(L) V1P8S Off Off Pull-down Pull-down
DDI0_DDCCLK† I/O 20k(H) V1P8S Off Off Pull-up Pull-up
DDI0_DDCDATA† I/O 20k(L) V1P8S Off Off Pull-down Pull-down
DDI0_HPD† I/O 20k(L) V1P8S Off Off Pull-down Pull-down
DDI0_VDDEN† I/O 20k(L) V1P8S Off Off Pull-down Pull-down
DDI_RCOMP_P/N - - V1P0S
DDI1_TXP[3:0] O V1P0S Off Off
DDI1_TXN[3:0] O V1P0S Off Off
DDI1_AUXP I/O V1P0S Off Off
DDI1_AUXN I/O V1P0S Off Off
DDI1_BKLTCTL† I/O 20k(L) V1P8S Off Off Pull-down Pull-down
DDI1_BKLTEN† I/O 20k(L) V1P8S Off Off Pull-down Pull-down
DDI1_DDCCLK† I/O 20k(H) V1P8S Off Off Pull-up Pull-up
DDI1_DDCDATA† I/O 20k(L) V1P8S Off Off Pull-down Pull-down
DDI1_HPD† I/O 20k(L) V1P8S Off Off Pull-down Pull-down
DDI1_VDDEN† I/O 20k(L) V1P8S Off Off Pull-down Pull-down
NOTE: All signals with the “†” symbol are muxed and may not be available without configuration.

2.12 Display - VGA Interface Signals

See Chapter 14, “Graphics, Video and Display” for more details.

Table 12. VGA Interface Signals (Sheet 1 of 2)

Default Buffer State

Plat. Enter
Signal Name Dir Term Type S4/S5 S3 Reset Notes
Power S0

VGA_RED O VVGA_GPIO Off Off High-Z

VGA_GREEN O VVGA_GPIO Off Off High-Z
VGA_BLUE O VVGA_GPIO Off Off High-Z

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Table 12. VGA Interface Signals (Sheet 2 of 2)

Default Buffer State

Plat. Enter
Signal Name Dir Term Type S4/S5 S3 Reset Notes
Power S0

VGA_IREF Off Off VOL

VGA_IRTN Off Off High-Z
VGA_HSYNC O VVGA_GPIO Off Off VOL
VGA_VSYNC O VVGA_GPIO Off Off VOL
VGA_DDCCLK O VVGA_GPIO Off Off High-Z
VGA_DDCDATA I/O VVGA_GPIO Off Off High-Z

2.13 MIPI Camera Serial Interface (CSI) & ISP

Interface Signals
See Chapter 15, “MIPI-Camera Serial Interface (CSI) & ISP” for more details.

Table 13. MIPI CSI Interface Signals

Default Buffer State

Plat.
Signal Name Dir Term S4/S5 S3 Reset Enter S0 Notes
Power

MCSI1_CLKN I V1P24S Off

MCSI1_CLKP I V1P24S Off
MCSI1_DN[0:3] I V1P24S Off
MCSI1_DP[0:3] I V1P24S Off
MCSI2_CLKN I V1P24S Off
MCSI2_CLKP I V1P24S Off
MCSI2_DN[0] I V1P24S Off
MCSI2_DP[0] I V1P24S Off
MCSI3_CLKN I V1P24S Off
MCSI3_CLKP I V1P24S Off
MCSI_RCOMP - V1P24S Off High-Z High-Z High-Z

2.14 Intel® High Definition Audio Interface Signals

See Chapter 20, “Intel® High Definition Audio” for more details.

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Table 14. HD Audio Interface Signals

Default Buffer State

Plat.
Signal Name Dir Term S4/S5 S3 Reset Enter S0 Notes
Power

HDA_SDO† O 20k(L) VAUD Off Off Pull-down Pull-down

HDA_SDI[1:0]† I 20k(L) VAUD Off Off Pull-down Pull-down
HDA_CLK† O 20k(L) VAUD Off Off Pull-down Pull-down
HDA_RST#† O 20k(L) VAUD Off Off Pull-down Pull-down
HDA_SYNC† O 20k(L) VAUD Off Off Pull-down Pull-down
HDA_LPE_RCOMP -
NOTE: All signals with the “†” symbol are muxed and may not be available without configuration.

2.15 Low Power Engine (LPE) for Audio (I2S) Interface

Signals
See Chapter 21, “Low Power Engine (LPE) for Audio (I2S)” for more details.

Table 15. LPE Interface Signals

Default Buffer State

Plat.
Signal Name Dir Term S4/S5 S3 Reset Enter S0 Notes
Power

LPE_I2S[2:0]_CLK I/O 20k(L) V1P8S Off Off Pull-down Pull-down

LPE_I2S[2:0]_FRM I/O 20k(H) V1P8S Off Off Pull-up Pull-up
LPE_I2S[2:0]_DATAOUT O 20k(H) V1P8S Off Off Pull-up Pull-up
LPE_I2S[2:0]_DATAIN I 20k(L) V1P8S Off Off Pull-down Pull-down

2.16 Storage Control Cluster (eMMC, SDIO, SD)

Interface Signals
See Chapter 16, “Storage Control Cluster (eMMC, SDIO, SD Card)” for more details.

Table 16. Storage Control Cluster (eMMC, SDIO, SD) Interface Signals (Sheet 1 of 2)

Default Buffer State

Plat.
Signal Name Dir Term S4/S5 S3 Reset Enter S0 Notes
Power

MMC1_D[7:0]† I/O 20k(H) V1P8S Off Off Pull-up Pull-up

MMC1_CMD† I/O 20k(H) V1P8S Off Off Pull-up Pull-up
MMC1_CLK† I/O 20k(L) V1P8S Off Off Pull-down Pull-down
MMC1_RST#† I/O 20k(L) V1P8S Off Off Pull-down Pull-down

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Table 16. Storage Control Cluster (eMMC, SDIO, SD) Interface Signals (Sheet 2 of 2)

Default Buffer State

Plat.
Signal Name Dir Term S4/S5 S3 Reset Enter S0 Notes
Power

MMC1_RCOMP I/O - V1P8S

SD2_D[3:0]† I/O 20k(H) V1P8S Off Off Pull-up Pull-up
SD2_CMD† I/O 20k(H) V1P8S Off Off Pull-up Pull-up
SD2_CLK† I/O 20k(L) V1P8S Off Off Pull-down Pull-down
SD3_D[3:0]† I/O 20k(H) VSDIO Off Off Pull-up Pull-up
SD3_CMD† I/O 20k(H) VSDIO Off Off Pull-up Pull-up
SD3_CLK† I/O 20k(L) VSDIO Off Off Pull-down Pull-down
SD3_PWREN#† O 20k(H) V1P8S Off Off Pull-up Pull-up
SD3_CD#† I 20k(H) V1P8S Off Off Pull-up Pull-up
SD3_1P8EN† O 20k(L) V1P8S Off Off Pull-down Pull-down
SD3_WP† I/O 20k(H) V1P8S Off Off Pull-up Pull-up
SD3_RCOMP - - VSDIO
NOTE: All signals with the “†” symbol are muxed and may not be available without configuration.
NOTE: VSDIO voltage selection is controlled by SD3_1P8EN. 3.3V is default due to pull-down. VSDIO can be
either 1.8 or 3.3 V when these VSDIO referenced signals are configured to be GPIO’s to meet different
platform requirements.

2.17 SIO - High Speed UART Interface Signals

See Chapter 27, “SIO - High Speed UART” for more details.

Table 17. High Speed UART Interface Signals

Default Buffer State

Plat.
Signal Name Dir Term S4/S5 S3 Reset Enter S0 Notes
Power

SIO_UART1_RXD† I/O 20k(H) V1P8S Off Off Pull-up Pull-up

SIO_UART1_TXD† I/O 20k(H) V1P8S Off Off Pull-up Pull-up
SIO_UART1_RTS#† I/O 20k(H) V1P8S Off Off Pull-up Pull-up
SIO_UART1_CTS#† I/O 20k(H) V1P8S Off Off Pull-up Pull-up
SIO_UART2_RXD† I/O 20k(H) V1P8S Off Off Pull-up Pull-up
SIO_UART2_TXD† I/O 20k(H) V1P8S Off Off Pull-up Pull-up
SIO_UART2_RTS#† I/O 20k(H) V1P8S Off Off Pull-up Pull-up
SIO_UART2_CTS#† I/O 20k(H) V1P8S Off Off Pull-up Pull-up
NOTE: All signals with the “†” symbol are muxed and may not be available without configuration.

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2.18 SIO - I2C Interface Signals

See Chapter 26, “SIO - I2C Interface” for more details.

Table 18. SIO - I2C Interface Signals

Default Buffer State

Plat.
Signal Name Dir Term S4/S5 S3 Reset Enter S0 Notes
Power

SIO_I2C0_DATA† I/O 20k(H) V1P8S Off Off Pull-up Pull-up

SIO_I2C0_CLK† I/O 20k(H) V1P8S Off Off Pull-up Pull-up
SIO_I2C1_DATA† I/O 20k(H) V1P8S Off Off Pull-up Pull-up
SIO_I2C1_CLK† I/O 20k(H) V1P8S Off Off Pull-up Pull-up
SIO_I2C2_DATA† I/O 20k(H) V1P8S Off Off Pull-up Pull-up
SIO_I2C2_CLK† I/O 20k(H) V1P8S Off Off Pull-up Pull-up
SIO_I2C3_DATA† I/O 20k(H) V1P8S Off Off Pull-up Pull-up
SIO_I2C3_CLK† I/O 20k(H) V1P8S Off Off Pull-up Pull-up
SIO_I2C4_DATA† I/O 20k(H) V1P8S Off Off Pull-up Pull-up
SIO_I2C4_CLK† I/O 20k(H) V1P8S Off Off Pull-up Pull-up
SIO_I2C5_DATA† I/O 20k(H) V1P8S Off Off Pull-up Pull-up
SIO_I2C5_CLK† I/O 20k(H) V1P8S Off Off Pull-up Pull-up
SIO_I2C6_DATA† I/O 20k(H) V1P8S Off Off Pull-up Pull-up
SIO_I2C6_CLK† I/O 20k(H) V1P8S Off Off Pull-up Pull-up
NOTE: All signals with the “†” symbol are muxed and may not be available without configuration.

2.19 SIO - Serial Peripheral Interface (SPI) Signals

See Chapter 25, “SIO - Serial Peripheral Interface (SPI)” for more details.

Table 19. SIO - Serial Peripheral Interface (SPI) Signals

Default Buffer State

Plat.
Signal Name Dir Term S4/S5 S3 Reset Enter S0 Notes
Power

SIO_SPI_CLK† I/O 20k(L) V1P8S Off Off Pull-down Pull-down

SIO_SPI_CS#† I/O 20k(H) V1P8S Off Off Pull-up Pull-up
SIO_SPI_MOSI† I/O 20k(H) V1P8S Off Off Pull-up Pull-up
SIO_SPI_MISO† I/O 20k(H) V1P8S Off Off Pull-up Pull-up
NOTE: All signals with the “†” symbol are muxed and may not be available without configuration.

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2.20 PCU - iLB - Real Time Clock (RTC) Interface

Signals
See Chapter 36, “PCU - iLB - Real Time Clock (RTC)” for more details.

Table 20. PCU - iLB - Real Time Clock (RTC) Interface Signals

Default Buffer State

Plat.
Signal Name Dir Term S4/S5 S3 Reset Enter S0 Notes
Power

ILB_RTC_X1 I - VRTC Running Running Running Running

ILB_RTC_X2 O - VRTC Running Running Running Running
ILB_RTC_RST# I - VRTC VIH VIH VIH VIH
ILB_RTC_TEST# I - VRTC VIH VIH VIH VIH
ILB_RTC_EXTPAD O - VRTC

2.21 PCU - iLB - Low Pin Count (LPC) Bridge Interface

Signals
See Chapter 35, “PCU - iLB - Low Pin Count (LPC) Bridge” for more details.

Table 21. PCU - iLB - LPC Bridge Interface Signals

Default Buffer State

Plat.
Signal Name Dir Term S4/S5 S3 Reset Enter S0 Notes
Power

ILB_LPC_AD[3:0]† I/O 20k(H) VLPC Off Off Pull-up Running

ILB_LPC_FRAME#† I/O 20k(H) VLPC Off Off VOH Running
ILB_LPC_SERIRQ† I/O 20k(H) V1P8S Off Off Pull-up Running
ILB_LPC_CLKRUN#† I/O 20k(H) VLPC Off Off Pull-up Running
ILB_LPC_CLK[1:0]† I/O 20k(L) VLPC Off Off VOL Running
LPC_RCOMP - VLPC
NOTE: All signals with the “†” symbol are muxed and may not be available without configuration.

2.22 PCU - Serial Peripheral Interface (SPI) Signals

See Chapter 31, “PCU - Serial Peripheral Interface (SPI)” for more details.

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Table 22. PCU - Serial Peripheral Interface (SPI) Signals

Default Buffer State

Plat. Enter
Signal Name Dir Term S4/S5 S3 Reset Notes
Power S0

PCU_SPI_CLK O - V1P8A Pull-up Pull-up Pull-up Running

PCU_SPI_CS[0]# O - V1P8A Pull-up Pull-up Pull-up Running
PCU_SPI_CS[1]#† O 20k(H) V1P8A Pull-up Pull-up Pull-up Running
PCU_SPI_MOSI I/O 20k(H) V1P8A Pull-up Pull-up Pull-up Pull-up
PCU_SPI_MISO I 20k(H) V1P8A Pull-up Pull-up Pull-up Pull-up
NOTE: All signals with the “†” symbol are muxed and may not be available without configuration.

2.23 PCU - System Management Bus (SMBus) Interface

Signals
See Chapter 33, “PCU - System Management Bus (SMBus)” for more details.

Table 23. PCU - System Management Bus (SMBus) Interface Signals

Default Buffer State

Plat.
Signal Name Dir Term S4/S5 S3 Reset Enter S0
Power

PCU_SMB_CLK† I/O 20k(H) V1P8S Off Off Pull-up Pull-up

PCU_SMB_DATA† I/O 20k(H) V1P8S Off Off Pull-up Pull-up
PCU_SMB_ALERT#† I/O 20k(H) V1P8S Off Off Pull-up Pull-up

2.24 PCU - Power Management Controller (PMC)

Interface Signals
See Chapter 30, “PCU - Power Management Controller (PMC)” for more details.

Table 24. PCU - Power Management Controller (PMC) Interface Signals (Sheet 1 of 2)

Default Buffer State

Plat.
Signal Name Dir Term S4/S5 S3 Reset Enter S0 Notes
Power

PMC_PLTRST# O - V1P8A Off/VOL VOL VOL->VOH VOH

PMC_PWRBTN#† I 20k(H) V1P8A Off/Pull-up Pull-up Pull-up Pull-up
PMC_RSTBTN# I 20k(H) V1P8S Off Off Pull-up Pull-up
PMC_SUSPWRDNACK† O - V1P8A VOH/VOL VOH/VOL VOH VOH/VOL
PMC_SUS_STAT#† O - V1P8A VOL VOL VOL VOH

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Table 24. PCU - Power Management Controller (PMC) Interface Signals (Sheet 2 of 2)

Default Buffer State

Plat.
Signal Name Dir Term S4/S5 S3 Reset Enter S0 Notes
Power

PMC_SUSCLK[0]† O - V1P8A Off/Running Running Running Running

PMC_SUSCLK[3:1]† O -
PMC_SLP_S3# O - V1P8A Off/VOL VOL VOH VOH
PMC_SLP_S4# O - V1P8A Off/VOL VOH VOH VOH
PMC_WAKE_PCIE[0]# I 20k(H) V1P8A Off/Pull-up Pull-up Pull-up Pull-up
PMC_WAKE_PCIE[3:1]#† I 20k(H) V1P8A Off/Pull-up Pull-up Pull-up Pull-up
PMC_ACPRESENT I 20k(L) V1P8A Off/High-Z Pull-down Pull-down Pull-down
PMC_BATLOW# I 20k(H) V1P8A Off/Pull-up Pull-up Pull-up Pull-up
PMC_CORE_PWROK I VRTC VIL VIL VIL VIH
PMC_RSMRST# I VRTC VIH VIH VIH VIH
NOTE: All signals with the “†” symbol are muxed and may not be available without configuration.

2.25 JTAG and Debug Interface Signals

Table 25. JTAG and Debug Interface Signals

Default Buffer State

Plat.
Signal Name Dir Term S4/S5 S3 Reset Enter S0 Notes
Power

TAP_TCK I 2k(L) V1P8A Pull-down Pull-down Pull-down Pull-down

TAP_TDI I 2k(H) V1P8A Pull-up Pull-up Pull-up Pull-up
TAP_TDO O - V1P8A Pull-up Pull-up Pull-up Pull-up
TAP_TMS I 2k(H) V1P8A Pull-up Pull-up Pull-up Pull-up
TAP_TRST# I 2k(H) V1P8A Pull-up Pull-up Pull-up Pull-up
TAP_PRDY# O 2k(H) V1P8A Pull-up Pull-up Pull-up Pull-up
TAP_PREQ# I 2k(H) V1P8A Pull-up Pull-up Pull-up Pull-up

2.26 Miscellaneous Signals

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Table 26. Miscellaneous Signals and Clocks

Default Buffer State

Plat.
Signal Name Dir Term S4/S5 S3 Reset Enter S0
Power

SVID_DATA I/O 2k(H) V1P0S Off Off Pull-up Pull-up

SVID_CLK O 2k(H) V1P0S Off Off Pull-up Pull-up
SVID_ALERT# I 2k(H) V1P0S Off Off Pull-up Pull-up
PROCHOT# I/O 2k(H) V1P0S Off Off Pull-up Pull-up
ILB_8254_SPKR† O 20k(H) V1P8S Off Off Pull-up Pull-up
ILB_NMI† I 20k(H) V1P8S Off Off Pull-up Pull-up
PMC_PLT_CLK[5:0]† O 20k(L) V1P8S Off Off Pull-down Pull-down
GPIO_RCOMP - - V1P8S Off Off Active Active
NOTE: All signals with the “†” symbol are muxed and may not be available without configuration.
NOTE: GPIO_RCOMP provides compensation for the following pins: GPIO_S5[10],
PMC_SUSPWRDNACK PMC_SUSCLK[0], GPIO_S5[13], PMC_SLP_S4#, PMC_SLP_S3#,
USB_ULPI_RST#, PMC_ACPRESENT, PMC_WAKE_PCIE[0]#, PMC_BATLOW#,
PMC_PWRBTN#, PMC_PLTRST#, GPIO_S5[17], PMC_SUS_STAT#, USB_OC[1:0]#,
GPIO_S5[09:00], GPIO_S5[30:22], TAP_TCK TAP_TRST#, TAP_TMS, TAP_TDI, TAP_TDO,
TAP_PRDY#, TAP_PREQ#

2.27 GPIO Signals

Most GPIO’s are configurable via multiplexors. See “Ballout and Package Information”
chapter for configuration options with the interfaces presented in this chapter.

Table 27. GPIO Signals

Default Buffer State

Plat.
Signal Name Dir Term S4/S5 S3 Reset Enter S0
Power

GPIO_S0_SC[000]† I/O 20k,L V1P8S Off Off Pull-down Pull-down

GPIO_S0_SC[001]† I/O 20k,L V1P8S Off Off Pull-down Pull-down
GPIO_S0_SC[002]† I/O 20k,H V1P8S Off Off Pull-up Pull-up
GPIO_S0_SC[003]† I/O 20k,H V1P8S Off Off Pull-up Pull-up
GPIO_S0_SC[004]† I/O 20k,H V1P8S Off Off Pull-up Pull-up
GPIO_S0_SC[005]† I/O 20k,H V1P8S Off Off Pull-up Pull-up
GPIO_S0_SC[006]† I/O 20k,H V1P8S Off Off Pull-up Pull-up
GPIO_S0_SC[007]† I/O 20k,H V1P8S Off Off Pull-up Pull-up
GPIO_S0_SC[008]† I/O 20k,L VAUD Off Off Pull-down Pull-down
GPIO_S0_SC[009]† I/O 20k,L VAUD Off Off Pull-down Pull-down
GPIO_S0_SC[010]† I/O 20k,L VAUD Off Off Pull-down Pull-down

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Table 27. GPIO Signals

Default Buffer State

Plat.
Signal Name Dir Term S4/S5 S3 Reset Enter S0
Power

GPIO_S0_SC[011]† I/O 20k,L VAUD Off Off Pull-down Pull-down

GPIO_S0_SC[012]† I/O 20k,L VAUD Off Off Pull-down Pull-down
GPIO_S0_SC[013]† I/O 20k,L VAUD Off Off Pull-down Pull-down
GPIO_S0_SC[014]† I/O 20k,L VAUD Off Off Pull-down Pull-down
GPIO_S0_SC[015]† I/O 20k,L V1P8S Off Off Pull-down Pull-down
GPIO_S0_SC[016]† I/O 20k,L V1P8S Off Off Pull-down Pull-down
GPIO_S0_SC[017]† I/O 20k,H V1P8S Off Off Pull-up Pull-up
GPIO_S0_SC[018]† I/O 20k,H V1P8S Off Off Pull-up Pull-up
GPIO_S0_SC[019]† I/O 20k,H V1P8S Off Off Pull-up Pull-up
GPIO_S0_SC[020]† I/O 20k,H V1P8S Off Off Pull-up Pull-up
GPIO_S0_SC[021]† I/O 20k,H V1P8S Off Off Pull-up Pull-up
GPIO_S0_SC[022]† I/O 20k,H V1P8S Off Off Pull-up Pull-up
GPIO_S0_SC[023]† I/O 20k,H V1P8S Off Off Pull-up Pull-up
GPIO_S0_SC[024]† I/O 20k,H V1P8S Off Off Pull-up Pull-up
GPIO_S0_SC[025]† I/O 20k,H V1P8S Off Off Pull-up Pull-up
GPIO_S0_SC[026]† I/O 20k,L V1P8S Off Off Pull-down Pull-down
GPIO_S0_SC[027]† I/O 20k,L V1P8S Off Off Pull-down Pull-down
GPIO_S0_SC[028]† I/O 20k,H V1P8S Off Off Pull-up Pull-up
GPIO_S0_SC[029]† I/O 20k,H V1P8S Off Off Pull-up Pull-up
GPIO_S0_SC[030]† I/O 20k,H V1P8S Off Off Pull-up Pull-up
GPIO_S0_SC[031]† I/O 20k,H V1P8S Off Off Pull-up Pull-up
GPIO_S0_SC[032]† I/O 20k,H V1P8S Off Off Pull-up Pull-up
GPIO_S0_SC[033]† I/O 20k,L VSDIO Off Off Pull-down Pull-down
GPIO_S0_SC[034]† I/O 20k,H VSDIO Off Off Pull-up Pull-up
GPIO_S0_SC[035]† I/O 20k,H VSDIO Off Off Pull-up Pull-up
GPIO_S0_SC[036]† I/O 20k,H VSDIO Off Off Pull-up Pull-up
GPIO_S0_SC[037]† I/O 20k,H VSDIO Off Off Pull-up Pull-up
GPIO_S0_SC[038]† I/O 20k,H V1P8S Off Off Pull-up Pull-up
GPIO_S0_SC[039]† I/O 20k,H VSDIO Off Off Pull-up Pull-up
GPIO_S0_SC[040]† I/O 20k,L V1P8S Off Off Pull-down Pull-down
GPIO_S0_SC[041]† I/O 20k,H V1P8S Off Off Pull-up Pull-up
GPIO_S0_SC[042]† I/O 20k,H VLPC Off Off Pull-up Pull-up
GPIO_S0_SC[043]† I/O 20k,H VLPC Off Off Pull-up Pull-up
GPIO_S0_SC[044]† I/O 20k,H VLPC Off Off Pull-up Pull-up
GPIO_S0_SC[045]† I/O 20k,H VLPC Off Off Pull-up Pull-up

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Table 27. GPIO Signals

Default Buffer State

Plat.
Signal Name Dir Term S4/S5 S3 Reset Enter S0
Power

GPIO_S0_SC[046]† I/O 20k,H VLPC Off Off

GPIO_S0_SC[047]† I/O 20k,L VLPC Off Off
GPIO_S0_SC[048]† I/O 20k,L VLPC Off Off
GPIO_S0_SC[049]† I/O 20k,H VLPC Off Off Pull-up Pull-up
GPIO_S0_SC[050]† I/O 20k,H V1P8S Off Off Pull-up Pull-up
GPIO_S0_SC[051]† I/O 20k,H V1P8S Off Off Pull-up Pull-up
GPIO_S0_SC[052]† I/O 20k,H V1P8S Off Off Pull-up Pull-up
GPIO_S0_SC[053]† I/O 20k,H V1P8S Off Off Pull-up Pull-up
GPIO_S0_SC[054]† I/O 20k,H V1P8S Off Off Pull-up Pull-up
GPIO_S0_SC[055]† I/O 20k,L V1P8S Off Off Pull-down Pull-down
GPIO_S0_SC[056]† I/O 20k,H V1P8S Off Off Pull-up Pull-up
GPIO_S0_SC[057]† I/O 20k,H V1P8S Off Off Pull-up Pull-up
GPIO_S0_SC[058]† I/O 20k,L V1P8S Off Off Pull-down Pull-down
GPIO_S0_SC[059]† I/O 20k,L V1P8S Off Off Pull-down Pull-down
GPIO_S0_SC[060]† I/O 20k,L V1P8S Off Off Pull-down Pull-down
GPIO_S0_SC[061]† I/O 20k,H V1P8S Off Off Pull-up Pull-up
GPIO_S0_SC[062]† I/O 20k,L V1P8S Off Off Pull-down Pull-down
GPIO_S0_SC[063]† I/O 20k,H V1P8S Off Off Pull-up Pull-up
GPIO_S0_SC[064]† I/O 20k,L V1P8S Off Off Pull-down Pull-down
GPIO_S0_SC[065]† I/O 20k,H V1P8S Off Off Pull-up Pull-up
GPIO_S0_SC[066]† I/O 20k,H V1P8S Off Off Pull-up Pull-up
GPIO_S0_SC[067]† I/O 20k,H V1P8S Off Off Pull-up Pull-up
GPIO_S0_SC[068]† I/O 20k,H V1P8S Off Off Pull-up Pull-up
GPIO_S0_SC[069]† I/O 20k,L V1P8S Off Off Pull-down Pull-down
GPIO_S0_SC[070]† I/O 20k,H V1P8S Off Off Pull-up Pull-up
GPIO_S0_SC[071]† I/O 20k,H V1P8S Off Off Pull-up Pull-up
GPIO_S0_SC[072]† I/O 20k,H V1P8S Off Off Pull-up Pull-up
GPIO_S0_SC[073]† I/O 20k,H V1P8S Off Off Pull-up Pull-up
GPIO_S0_SC[074]† I/O 20k,H V1P8S Off Off Pull-up Pull-up
GPIO_S0_SC[075]† I/O 20k,H V1P8S Off Off Pull-up Pull-up
GPIO_S0_SC[076]† I/O 20k,H V1P8S Off Off Pull-up Pull-up
GPIO_S0_SC[077]† I/O 20k,H V1P8S Off Off Pull-up Pull-up
GPIO_S0_SC[078]† I/O 20k,H V1P8S Off Off Pull-up Pull-up
GPIO_S0_SC[079]† I/O 20k,H V1P8S Off Off Pull-up Pull-up
GPIO_S0_SC[080]† I/O 20k,H V1P8S Off Off Pull-up Pull-up

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Table 27. GPIO Signals

Default Buffer State

Plat.
Signal Name Dir Term S4/S5 S3 Reset Enter S0
Power

GPIO_S0_SC[081]† I/O 20k,H V1P8S Off Off Pull-up Pull-up

GPIO_S0_SC[082]† I/O 20k,H V1P8S Off Off Pull-up Pull-up
GPIO_S0_SC[083]† I/O 20k,H V1P8S Off Off Pull-up Pull-up
GPIO_S0_SC[084]† I/O 20k,H V1P8S Off Off Pull-up Pull-up
GPIO_S0_SC[085]† I/O 20k,H V1P8S Off Off Pull-up Pull-up
GPIO_S0_SC[086]† I/O 20k,H V1P8S Off Off Pull-up Pull-up
GPIO_S0_SC[087]† I/O 20k,H V1P8S Off Off Pull-up Pull-up
GPIO_S0_SC[088]† I/O 20k,H V1P8S Off Off Pull-up Pull-up
GPIO_S0_SC[089]† I/O 20k,H V1P8S Off Off Pull-up Pull-up
GPIO_S0_SC[090]† I/O 20k,H V1P8S Off Off Pull-up Pull-up
GPIO_S0_SC[091]† I/O 20k,H V1P8S Off Off Pull-up Pull-up
GPIO_S0_SC[092]† I/O 20k,H V1P8S Off Off Pull-up Pull-up
GPIO_S0_SC[093]† I/O 20k,H V1P8S Off Off Pull-up Pull-up
GPIO_S0_SC[094]† I/O 20k,L V1P8S Off Off Pull-down Pull-down
GPIO_S0_SC[095]† I/O 20k,L V1P8S Off Off Pull-down Pull-down
GPIO_S0_SC[096]† I/O 20k,L V1P8S Off Off Pull-down Pull-down
GPIO_S0_SC[097]† I/O 20k,L V1P8S Off Off Pull-down Pull-down
GPIO_S0_SC[098]† I/O 20k,L V1P8S Off Off Pull-down Pull-down
GPIO_S0_SC[099]† I/O 20k,L V1P8S Off Off Pull-down Pull-down
GPIO_S0_SC[100]† I/O 20k,L V1P8S Off Off Pull-down Pull-down
GPIO_S0_SC[101]† I/O 20k,L V1P8S Off Off Pull-down Pull-down
GPIO_S5[00]† I/O 20k,H V1P8A Pull-up Pull-up Pull-up Pull-up
GPIO_S5[01]† I/O 20k,H V1P8A Pull-up Pull-up Pull-up Pull-up
GPIO_S5[02]† I/O 20k,H V1P8A Pull-up Pull-up Pull-up Pull-up
GPIO_S5[03]† I/O 20k,H V1P8A Pull-up Pull-up Pull-up Pull-up
GPIO_S5[04]† I/O 20k,L V1P8A Pull-down Pull-down Pull-down Pull-down
GPIO_S5[05]† I/O 20k,L V1P8A Pull-down Pull-down Pull-down Pull-down
GPIO_S5[06]† I/O 20k,L V1P8A Pull-down Pull-down Pull-down Pull-down
GPIO_S5[07]† I/O 20k,L V1P8A Pull-down Pull-down Pull-down Pull-down
GPIO_S5[08]† I/O 20k,L V1P8A Pull-down Pull-down Pull-down Pull-down
GPIO_S5[09]† I/O 20k,L V1P8A Pull-down Pull-down Pull-down Pull-down
GPIO_S5[10]† I/O 20k,H V1P8A Pull-up Pull-up Pull-up Pull-up
GPIO_S5[11]† I/O - V1P8A 0/1 0/1 0 0/1
GPIO_S5[12]† I/O - V1P8A T T T T
GPIO_S5[13]† I/O - V1P8A 0 0 0 0/1

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Table 27. GPIO Signals

Default Buffer State

Plat.
Signal Name Dir Term S4/S5 S3 Reset Enter S0
Power

GPIO_S5[14]† I/O - V1P8A 0 0 0 0/1

GPIO_S5[15]† I/O 20k,H V1P8A Pull-up Pull-up Pull-up
GPIO_S5[16]† I/O 20k,H V1P8A Pull-up Pull-up Pull-up
GPIO_S5[17]† I/O 20k,H V1P8A Pull-up Pull-up Pull-up
GPIO_S5[18]† I/O - V1P8A 0 0 0 1
GPIO_S5[19]† I/O 20k,H V1P8A Pull-up Pull-up Pull-up Pull-up
GPIO_S5[20]† I/O 20k,H V1P8A Pull-up Pull-up Pull-up Pull-up
GPIO_S5[21]† I/O 20k,H V1P8A Pull-up Pull-up Pull-up Pull-up
GPIO_S5[22]† I/O 20k,L V1P8A Pull-down Pull-down Pull-down Pull-down
GPIO_S5[23]† I/O 20k,L V1P8A Pull-down Pull-down Pull-down Pull-down
GPIO_S5[24]† I/O 20k,L V1P8A Pull-down Pull-down Pull-down Pull-down
GPIO_S5[25]† I/O 20k,L V1P8A Pull-down Pull-down Pull-down Pull-down
GPIO_S5[26]† I/O 20k,L V1P8A Pull-down Pull-down Pull-down Pull-down
GPIO_S5[27]† I/O 20k,H V1P8A Pull-up Pull-up Pull-up Pull-up
GPIO_S5[28]† I/O 20k,H V1P8A Pull-up Pull-up Pull-up Pull-up
GPIO_S5[29]† I/O 20k,H V1P8A Pull-up Pull-up Pull-up Pull-up
GPIO_S5[30]† I/O 20k,H V1P8A Pull-up Pull-up Pull-up Pull-up
GPIO_S5[31]† I/O 20k,L V1P8A Pull-down Pull-down Pull-down Pull-down
GPIO_S5[32]† I/O 20k,L V1P8A Pull-down Pull-down Pull-down Pull-down
GPIO_S5[33]† I/O 20k,L V1P8A Pull-down Pull-down Pull-down Pull-down
GPIO_S5[34]† I/O 20k,L V1P8A Pull-down Pull-down Pull-down Pull-down
GPIO_S5[35]† I/O 20k,L V1P8A Pull-down Pull-down Pull-down Pull-down
GPIO_S5[36]† I/O 20k,L V1P8A Pull-down Pull-down Pull-down Pull-down
GPIO_S5[37]† I/O 20k,L V1P8A Pull-down Pull-down Pull-down Pull-down
GPIO_S5[38]† I/O 20k,L V1P8A Pull-down Pull-down Pull-down Pull-down
GPIO_S5[39]† I/O 20k,L V1P8A Pull-down Pull-down Pull-down Pull-down
GPIO_S5[40]† I/O 20k,H V1P8A Pull-up Pull-up Pull-up Pull-up
GPIO_S5[41]† I/O 20k,L V1P8A Pull-down Pull-down Pull-down Pull-down
GPIO_S5[42]† I/O 20k,H V1P8A Pull-up Pull-up Pull-up Pull-up
GPIO_S5[43]† I/O 20k,L V1P8A Pull-down Pull-down Pull-down Pull-down

2.28 Power And Ground Pins

Power Rail Ball Name Format: [Function]_[Voltage]_[S-State]{_[Filter]}:
• [Function]: The SoC function associated with the power rail.

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— E.g CORE, USB, …

• [Voltage]: The nominal voltage associated with the power rail.
— E.g. 1P05, 3P3, VCC, …
• [S-State]: The ACPI system state, from S0 to G3, when the this rail is turned off.
• [Filter]: An optional indicator that one or more power rail balls have unique filtering
requirements or requirement to be uniquely identified.

Note: The Resume power well is a set of supply rails (where [S-State] = G3) that must be
powered even when S3/4/5 states aren’t used. The “Resume Well” is also referred to as
the “Suspend Power Well”, “Always on/SUS”, “SUS power”, or “SUS well”.

Table 28. Power and Ground Pins (Sheet 1 of 2)

Platform Nominal
Power Rails First Off State
Power Voltages

CORE_V1P05_S3 V1P05S 1.05 V S3

CORE_VCC_S3 VCC Variable S3

CORE_VCC_SENSE See CORE_VCC_S3

CORE_VSS_SENSE - - -

DDI_V1P0_S3 V1P0S 1.0 V S3

DRAM_V1P0_S3 V1P0S 1.0 V S3

DRAM_V1P35_S3_F1 VSFR 1.35 V S3

DRAM_VDD_S4 V1P35U 1.35 V S4

GPIO_V1P0_S3 V1P0S 1.0 V S3

HDA_LPE_V1P5V1P8_S3 VAUD 1.5/1.8 V S3

ICLK_V1P35_S3_F1 VSFR 1.35 V S3

ICLK_V1P35_S3_F2 VSFR 1.35 V S3

LPC_V1P8V3P3_S3 VLPC 1.8/3.3 V S3

MIPI_V1P24_S3 V1P24S 1.24 V S3

MIPI_V1P8_S3 V1P8S 1.8 V S3

PCIE_SATA_V1P0_S3 VPCIESATA 1.0 V S3

PCIE_V1P0_S3 VPCIESATA 1.0 V S3

PCU_V1P8_G3 V1P8A 1.8 V G3

PCU_V3P3_G3 V3P3A 3.3 V G3

PMC_V1P8_G3 V1P8A 1.8 V G3

RTC_VCC VRTC 2.0-3.3 (normally battery backed)

SATA_V1P0_S3 VPCIESATA 1.0 V S3

SD3_V1P8V3P3_S3 VSDIO 1.8/3.3 V S3

SVID_V1P0_S3 V1P0S 1.0 V S3

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Table 28. Power and Ground Pins (Sheet 2 of 2)

Platform Nominal
Power Rails First Off State
Power Voltages

UNCORE_V1P0_G3 V1P0A 1.0 V G3

UNCORE_V1P0_S3 V1P0S 1.0 V S3

UNCORE_V1P35_S3_F1 VSFR 1.35 V S3

UNCORE_V1P35_S3_F2 VSFR 1.35 V S3

UNCORE_V1P35_S3_F3 VSFR 1.35 V S3

UNCORE_V1P35_S3_F4 VSFR 1.35 V S3

UNCORE_V1P35_S3_F5 VSFR 1.35 V S3

UNCORE_V1P35_S3_F6 VSFR 1.35 V S3

UNCORE_V1P8_G3 V1P8A 1.8 V G3

UNCORE_V1P8_S3 V1P8S 1.8 V S3

UNCORE_VNN_S3 VNN Variable S3

UNCORE_VNN_SENSE See UNCORE_VNN_S3

USB_HSIC_V1P24_G3 V1P24A 1.24 V G3

USB_ULPI_V1P8_G3 V1P8A 1.8 V G3

USB_V1P0_S3 V1P0S 1.0 V S3

USB_V1P8_G3 V1P8A 1.8 V G3

USB_V3P3_G3 VUSB2 3.3 V G3

USB_VSSA - - -

USB3_V1P0_G3 V1P0A 1.0 V G3

USB3DEV_V1P0_S3 V1P0S 1.0 V S3

VGA_V1P0_S3 V1P0S 1.0 V S3

VGA_V1P35_S3_F1 VSFR 1.35 V S3

VGA_V3P3_S3 VVGA_GPIO 3.3 V S3

VSS - - -
VSSA - - -

Note: USB_HSIC_V1P24_G3 pin(s) can be connected to V1P0A platform rail if USB HSIC is
not used. MIPI_V1P24_S3 can be grounded if MIPI interfaces (CSI) aren’t used.

2.29 Hardware Straps

All straps are sampled on the rising edge of PMC_CORE_PWROK. Defaults are based on
internal termination.

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Table 29. Straps

Signal Name Function Default Strap Exit Strap Description

Top Swap (A16 Override)

PMC_CORE_PWROK
GPIO_S0_SC[056] Legacy 1b 0 = Top address bit is inverted
de-asserted
1 = Top address bit is unchanged
BIOS Boot Selection
PMC_CORE_PWROK
GPIO_S0_SC[063] Legacy 1b 0 = LPC
de-asserted
1 = SPI
Security Flash Descriptors
PMC_CORE_PWROK
GPIO_S0_SC[065] Legacy 1b 0 = Override
de-asserted
1 = Normal Operation
DDI0 Detect
PMC_CORE_PWROK
DDI0_DDCDATA Display 0b 0 = DDI0 not detected
de-asserted
1 = DDI0 detected
DDI1 Detect
PMC_CORE_PWROK
DDI1_DDCDATA Display 0b 0 = DDI1 not detected
de-asserted
1 = DDI1 detected

2.30 Configurable IO: GPIO Muxing

Not all interfaces may be active at the same time. To provide flexibility, some interfaces
are muxed with configurable IO balls. An interface’s signal is selected by a function
number. See Section 10.3, “Ball Name and Function by Location” on page 202 for
details of which balls are muxed, and what functions are available by ball.

Note: Configurable IO defaults to function 0 at boot. All configurable IO with GPIO’s for
function 0 default to input at boot.

2.31 Reserved Pins

Reserved pins are non functional pins. Unless otherwise specified in this document or
related collateral, reserved pins should not be connected to anything. RSVD_GND pins
must be connect to the common ground plane (VSS), but don’t provide a return path
for currents.

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3 Register Access Methods

There are six different common register access methods:
• Fixed IO Register Access
• Fixed Memory Mapped Register Access
• IO Referenced Register Access
• Memory Referenced Register Access
• PCI Configuration Register Access (Indirect - via Memory or IO registers)
• Message Bus Register Access (Indirect - via PCI Configuration Registers)

3.1 Fixed IO Register Access

Fixed IO registers are accessed by specifying their 16-bit address in a PORT IN and/or
PORT OUT transaction from the CPU core. This allows direct manipulation of the
registers. Fixed IO registers are unmovable register in IO space.

Table 30. Fixed IO Register Access Method Example (P80 Register)

Type: I/O Register
P80: 80h
(Size: 32 bits)

3.2 Fixed Memory Mapped Register Access

Fixed Memory Mapped IO (MMIO) registers are accessed by specifying their 32/36-bit
address in a memory transaction from the CPU core. This allows direct manipulation of
the registers. Fixed MMIO registers are unmovable registers in memory space.

Table 31. Fixed Memory Mapped Register Access Method Example (IDX Register)
Type: Memory Mapped I/O Register
IDX: FEC00000h
(Size: 32 bits)

3.3 IO Referenced Register Access

IO referenced registers use programmable base address registers (BARs) to select a
range of IO addresses that it will use to decode PORT IN and/or PORT OUT transactions
from the CPU to directly access a register. Thus, the IO BARs act as pointers to blocks
of actual IO registers. To access an IO referenced register for a specific IO base
address, start with that base address and add the register’s offset. Example pseudo
code for an IO referenced register read is shown below:

Register_Snapshot = IOREAD([IO_BAR]+Register_Offset)

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Base address registers are often located in the PCI configuration space and are
programmable by the BIOS/OS. Other base address register types may include fixed
memory registers, fixed IO registers or message bus registers.

Table 32. Referenced IO Register Access Method Example (HSTS Register)

Type: I/O Register
HSTS: [_IOBAR] + 0h
(Size: 8bits)

_IOBAR Type: PCI Configuration Register (Size: 32 bits)

_IOBAR Reference: [B:0, D:31, F:3] + 20h

3.4 Memory Referenced Register Access

The SoC uses programmable base address registers (BARs) to set a range of physical
address (memory) locations that it will use to decode memory reads and writes from
the CPU to directly access a register. These BARs act as pointers to blocks of actual
memory mapped IO (MMIO) registers. To access a memory referenced register for a
specific base address, start with that base address and add the register’s offset.
Example pseudo code for a read is shown below:

Register_Snapshot = MEMREAD([Mem_BAR]+Register_Offset)

Base address registers are often located in the PCI configuration space and are
programmable by the BIOS/OS. Other common base address register types include
fixed memory registers and IO registers that point to MMIO register blocks.

Table 33. Memory Mapped Register Access Method Example (_MBAR Register)
Type: Memory Mapped I/O Register
HSTS: [_MBAR] + 0h
(Size: 8bits)

_MBAR Type: PCI Configuration Register (Size: 32 bits)

_MBAR Reference: [B:0, D:31, F:3] + 10h

3.5 PCI Configuration Register Access

Access to PCI configuration space registers is performed through one of two different
configuration access methods (CAMs):
• IO indexed - PCI CAM
• Memory mapped - PCI Enhanced CAM (ECAM)
Each PCI function has a standard PCI header consisting of 256 bytes for the IO access
scheme (CAM), or 4096 bytes for the enhanced memory access method (ECAM).
Invalid read accesses return binary strings of 1s.

Table 34. PCI Register Access Method Example (VID Register)

Type: PCI Configuration Register VID: [B:0, D:31, F:3] + 0h
(Size: 16bits)

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3.5.1 PCI Configuration Access - CAM: IO Indexed Scheme

Accesses to configuration space using the IO method relies on two 32-bit IO registers:
• CONFIG_ADDRESS - IO Port CF8h
• CONFIG_DATA - IO Port CFCh
These two registers are both 32-bit registers in IO space. Using this indirect access
mode, software uses CONFIG_ADDRESS (CF8h) as an index register, indicating which
configuration space register to access, and CONFIG_DATA (CFCh) acts as a window to
the register pointed to in CONFIG_ADDRESS. Accesses to CONFIG_ADDRESS (CF8h)
are internally captured. Upon a read or write access to CONFIG_DATA (CFCh),
configuration cycles will be generated to the PCI function specified by the address
captured in CONFIG_ADDRESS. The format of the address is shown below.

Table 35. PCI CONFIG_ADDRESS Register (IO PORT CF8h) Mapping

Field CONFIG_ADDRESS Bits

Enable PCI Config. Space Mapping 31

Reserved 30:24
Bus Number 23:16
Device Number 15:11
Function Number 10:08
Register/Offset Number 07:02

Note: Bit 31 of CONFIG_ADDRESS must be set for a configuration cycle to be generated.

Pseudo code for a PCI register read is shown below:

• MyCfgAddr[23:16] = bus; MyCfgAddr[15:11] = device; MyCfgAddr[10:8] = funct;
• MyCfgAddr[7:2] = dWordMask(offset); MyCfgAddr[31] = 1;
• IOWRITE(0xCF8, MyCfgAddr)
• Register_Snapshot = IOREAD(0xCFC)

3.5.2 PCI Configuration Access - ECAM: Memory Mapped Scheme

A flat, 256 MiB memory space may also be allocated to perform configuration
transactions. This is enabled through the BUNIT.BECREG message bus register (Port:
3h, Register: 27h) found in the SoC Transaction Router. BUNIT.BECREG allows
remapping this 256 MiB region anywhere in physical memory space. Memory accesses
within the programmed MMIO range result in configuration cycles to the appropriate
PCI devices specified by the memory address as shown below.

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Table 36. PCI Configuration Memory Bar Mapping

ECAM Memory Address Field ECAM Memory Address Bits

Use from BAR: BUNIT.BECREG[31:28] 31:28

Bus Number 27:20
Device Number 19:15
Function Number 14:12
Register Number 11:02

Note: ECAM accesses are only possible when BUNIT.BECREG.ECENABLE (bit 0) is set.

Pseudo code for an enhanced PCI configuration register read is shown below:
• MyCfgAddr[27:20] = bus; MyCfgAddr[19:15] = device; MyCfgAddr[14:12] =
funct;
• MyCfgAddr[11:2] = dw_offset; MyCfgAddr[31:28] = BECREG[31:28];
• Register_Snapshot = MEMREAD(MyCfgAddr)

3.6 Message Bus Register Access

Accesses to the message bus space is through the SoC Transaction Router’s PCI
configuration registers. This unit relies on three 32-bit PCI configuration registers to
generate messages:
• Message Bus Control Register (MCR) - PCI[B:0,D:0,F:0] + D0h
• Message Data Register (MDR) - PCI[B:0,D:0,F:0] + D4h
• Message Control Register eXtension (MCRX) - PCI[B:0,D:0,F:0] + D8h
This indirect access mode is similar to PCI CAM. Software uses the MCR/MCRX as an
index register, indicating which message bus space register to access (MCRX only when
required), and MDR as the data register. Writes to the MCR trigger message bus
transactions.

Writes to MCRX and MDR will be captured. Writes to MCR will generate an internal
‘message bus’ transaction with the opcode and target (port, offset, bytes) specified in
the MCR and the captured MCRX. When a write opcode is specified in MCR, the data
that was captured by MDR is used for the write. When a data read opcode is specified in
MCR, the data will be available in the MDR register after the MCR write completes (non-
posted). The format of MCR and MCRX are shown below.

Table 37. MCR Description (Sheet 1 of 2)

Field MBPR Bits

OpCode (typically 10h for read, 11h for write) 31:24

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Table 37. MCR Description (Sheet 2 of 2)

Field MBPR Bits

Port 23:16
Offset/Register 15:08
Byte Enable 07:04

Table 38. MCRX Description

MBPER
Field
Bits

Offset/Register Extension. This is used for messages sent to end points that 31:08
require more than 8 bits for the offset/register. These bits are a direct extension of
MCR[15:8].

Most message bus registers are located in the SoC Transaction Router. The default
opcode messages for those registers are as follows:
• Message ‘Read Register’ Opcode: 06h
• Message ‘Write Register’ Opcode: 07h
Registers with different opcodes will be specified as applicable. Pseudo code of a
message bus register read is shown below (where ReadOp==0x06):
• MyMCR[31:24] = ReadOp; MyMCR[23:16] = port; MyMCR[15:8] = offset;
• MyMCR[7:4] = 0xf
• PCIWRITE(0, 0, 0, 0xD0, MyMCR)
• Register_Snapshot = PCIREAD(0, 0, 0, 0xD4)

3.7 Register Field Access Types

Table 39. Register Access Types and Definitions (Sheet 1 of 2)

Access Type Meaning Description

RO Read Only In some cases, if a register is read only, writes to this register location
have no effect. However, in other cases, two separate registers are located
at the same location where a read accesses one of the registers and a write
accesses the other register. See the I/O and memory map tables for
details.
WO Write Only In some cases, if a register is write only, reads to this register location
have no effect. However, in other cases, two separate registers are located
at the same location where a read accesses one of the registers and a write
accesses the other register. See the I/O and memory map tables for
details.
R/W Read/Write A register with this attribute can be read and written.

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Table 39. Register Access Types and Definitions (Sheet 2 of 2)

Access Type Meaning Description

R/WC Read/Write Clear A register bit with this attribute can be read and written. However, a write
of 1 clears (sets to 0) the corresponding bit and a write of 0 has no effect.
R/WO Read/Write-Once A register bit with this attribute can be written only once after power up.
After the first write, the bit becomes read only.
R/WLO Read/Write, Lock- A register bit with this attribute can be written to the non-locked value
Once multiple times, but to the locked value only once. After the locked value
has been written, the bit becomes read only.
Default Default When the processor is reset, it sets its registers to predetermined default
states. The default state represents the minimum functionality feature set
required to successfully bring up the system. Hence, it does not represent
the optimal system configuration. It is the responsibility of the system
initialization software to determine configuration, operating parameters,
and optional system features that are applicable, and to program the
processor registers accordingly.

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4 Mapping Address Spaces

The SoC supports four different address spaces:
• Physical Address Space Mappings
• IO Address Space
• PCI Configuration Space
• Message Bus Space
The CPU core can only directly access memory space through memory reads and writes
and IO space through the IN and OUT IO port instructions. PCI configuration space is
indirectly accessed through IO or memory space, and the Message Bus space is
accessed through PCI configuration space. See Chapter 3, “Register Access Methods”
for details.

This chapter describes how the memory, IO, PCI and Message Bus spaces are mapped
to interfaces in the SoC.

Note: See Chapter 13, “SoC Transaction Router” for registers specified in the chapter.

4.1 Physical Address Space Mappings

There are 64 GB (36-bits) of physical address space that can be used as:
• Memory Mapped IO (MMIO - IO fabric)
• Physical Memory (DRAM)
The CPU core can access the full physical address space, while downstream devices can
only access SoC DRAM, and each CPU core’s local APIC. Peer to peer transactions are
not supported.

Most devices map their registers and memory to the physical address space. This
chapter summarizes the possible mappings.

4.1.1 SoC Transaction Router Memory Map

The SoC Transaction Router maps the physical address space as follows:
• CPU core to DRAM
• CPU core to IO fabric (MMIO)
• CPU core to extended PCI registers (ECAM accesses)
• IO fabric to CPU cores (local APIC interrupts)
Although 64 GB (36-bits) of physical address space is accessible, some MMIO must
exist for devices and software with 32-bit limits. Further, all DRAM should remain
accessible for devices and software with access to memory above 4 GB. These goals

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are accomplished by moving a section DRAM to start at the fixed 4 GB boundary,

leaving a hole below 4 GB for MMIO. This creates the following distinct memory
regions:
• DOS DRAM + Low DRAM
• Low MMIO
• High DRAM
• High MMIO
There are two registers used to create these regions, BMBOUND and BMBOUND_HI.
Their use is shown in Figure 4.

Figure 4. Physical Address Space - DRAM & MMIO

64 GB

High MMIO

BMBOUND_HI
High DRAM
4 GB

Low MMIO

High DRAM
BMBOUND

Low DRAM Low DRAM

1 MB
DOS DRAM DOS DRAM

Physical Address DRAM Address

Space Space

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4.1.1.1 Low MMIO

The low MMIO mappings are shown in Figure 5.

Figure 5. Physical Address Space - Low MMIO

64 GB

- 1 (FFFFFFFFh)
Boot Vector
- 64 KB (FFFF0000h)
High MMIO

- 17 MB (FEF00000h)
Local APIC
High DRAM - 18 MB (FEE00000h)
4 GB
- 20 MB (FEBFFFFFh)
Abort Page
Low MMIO
- 21 MB (FEB00000h)

BMBOUND

BEGREG + 256 MB

Low DRAM
PCI ECAM

BECREG

1 MB
DOS DRAM

Physical Address
Space

By default, CPU core reads targeting the Boot Vector range (FFFFFFFFh-FFFF0000h)
are sent to the boot Flash connected to the Platform Controller Unit, and write accesses
target DRAM. This allows the boot strap CPU core to fetch boot code from the boot
Flash, and then shadow that code to DRAM.

Upstream writes from the IO fabric to the Local APIC range (FEE00000h-FEF00000h)
are sent to the appropriate CPU core’s APIC.

Write accesses from a CPU core to the Abort Page range (FEB00000h-FEBFFFFFh) will
be dropped, and reads will always return all 1’s in binary.

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Accesses in the 256 MB PCI ECAM range starting at BECREG generate enhanced PCI
configuration register accesses when enabled (BECREG.ECENABLE). Unlike traditional
memory writes, writes to this range are non-posted when enabled. See Chapter 3,
“Register Access Methods” for more details.

All other downstream accesses in the Low MMIO range are sent to the IO Fabric for
further decode based on PCI resource allocations. The IO Fabric’s subtractive agent (for
unclaimed accesses) is the Platform Controller Hub.

4.1.1.2 DOS DRAM

The DOS DRAM is the memory space below 1 MB. In general, accesses from a
processor targeting DOS DRAM target system DRAM. Exceptions are shown in the
below figure.

Figure 6. Physical Address Space - DOS DRAM

64 GB

High MMIO

High DRAM
4 GB

Low MMIO

BMBOUND
PROM ‘F’ Segment 64 KB (F0000h to FFFFFh)

PROM ‘E’ Segment 64 KB (E0000h to EFFFFh)

Low DRAM

VGA/CSEG 128 KB (A0000h to BFFFFh)

1 MB
DOS DRAM

Physical Address
Space

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Processor writes to the 64 KB (each) PROM ‘E’ and ‘F’ segments (E0000h-EFFFFh and
F0000h-FFFFFh) always target DRAM. The BMISC register is used to direct CPU core
reads in these two segments to DRAM or the IO fabric (MMIO).

CPU core accesses to the 128 KB VGA/CSEG range (A0000h-BFFFFh) can target DRAM
or the IO fabric (MMIO). The target is selected with the BMISC.ABSEGINDRAM register.

4.1.1.3 Additional Mappings

There are two additional mappings available in the SoC Transaction Router:
• SMM range
• Non-snoop range
Figure 7 shows these mappings.

Figure 7. Physical Address Space - SMM and Non-Snoop Mappings

Low or High DRAM in Physical Address

Physical Space Space
64 GB

BSMMRRH (SMM Range Hi) BNOCACHE.Upper...

Non-Snoopable
SMM Range
Memory
BSMMRRL (SMM Range Lo) BNOCACHE.Lower...

SMI handlers running on a CPU core execute out of SMM memory. To protect this
memory from non-CPU core access, the SMM Range (BSMMRRL-BSMMRRH) may be
programmed anywhere in low or high DRAM space (1 MB aligned). This range will only
allow accesses from the CPU cores.

To prevent snoops of the CPU cores when DMA devices access a specific memory
region, the Non-Snoopable Memory range (BNOCACHE.Lower-BNOCACHE.Upper)
can be programmed anywhere in physical address space. This range is enabled via the
BNOCACHECTL register’s enable bit (BNOCACHECTL.Enable).

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4.1.2 IO Fabric (MMIO) Map

Memory accesses targeting MMIO are routed by the IO fabric to programmed PCI
ranges, or routed to the PCU by default (subtractive agent). Programmed PCI ranges
can be moved within low or high MMIO, and most can be disabled.

Note: Not all devices can be mapped to high MMIO.

Fixed MMIO is claimed by the Platform Controller Unit (PCU). The default regions are
listed below. Movable ranges are not shown. See the register maps of all PCU devices
for details.

Table 40. Fixed Memory Ranges in the Platform Controller Unit (PCU)

Start End
Device Comments
Address Address

Low BIOS (Flash Boot) 000E0000h 000FFFFFh Starts 128 KB below 1 MB; Firmware/
BIOS
IO APIC FEC00000h FEC00040h Starts 20 MB below 4 GB
HPET FED00000h FED003FFh Starts 19 MB below 4 GB
TPM (LPC) FFD40000h FFD40FFFh Starts 16 KB above HPET range
High BIOS/Boot Vector FFFF0000h FFFFFFFFh Starts 64 KB below 4 GB; Firmware/
BIOS

The following PCI devices may claim memory resources in MMIO space:
• Graphics/Display (High MMIO capable)
• PCI Express* (High MMIO capable)
• SATA
• SD/MMC/SDIO
• SIO
• HD Audio
• Platform Controller Unit (PCU) (Multiple BARs)
• xHCI USB
• EHCI USB
• USB Device
• LPE/I2S
• ISP/MIPI-CSI
See each device’s interface chapter for details.

Warning: Variable memory ranges should not be set to conflict with other memory ranges. There
will be unpredictable results if the configuration software allows conflicts to occur.
Hardware does not check for conflicts.

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4.2 IO Address Space

There are 64 KB + 3 bytes of IO space (0h-10002h) for accessing IO registers. Most IO
registers exists for legacy functions in the PCU or for PCI devices, while some are
claimed by the SoC Transaction Router for graphics and for the PCI configuration space
access registers.

4.2.1 SoC Transaction Router IO Map

The SoC claims IO transactions for VGA/Extended VGA found in the display/graphics
interface. It also claims the two 32-bit registers at port CF8h and CFCh used to access
PCI configuration space.

4.2.2 IO Fabric IO Map

4.2.2.1 PCU Fixed IO Address Ranges

Below table shows the fixed IO space ranges seen by a processor.

Table 41. Fixed IO Ranges in the Platform Controller Unit (PCU)

Device IO Address Comments

8259 Master 20h-21h, 24h-25h,

28h-29h, 2Ch-2Dh,
30h-31h, 34h-35h,
38h-39-, 3Ch-3Dh
8254s 40h-43h, 50h-53h
PS2 Control 60h, 64h
NMI Controller 61h, 63h, 65h, 67h
RTC 70h-77h
Port 80h 80h-83h
Init Register 92h
8259 Slave A0h-A1h, A4h-A5h, A8h-
A9h, ACh-ADh, B0h-B1h,
B4h-B5h, B8h-B9h, BCh-
BDh, 4D0h-4D1h
PCU UART 3F8h-3FFh
Reset Control CF9h Overlaps PCI IO registers
Active Power Management B2h-B3h

4.2.2.2 Variable IO Address Ranges

Table 42 shows the variable IO decode ranges. They are set using base address
registers (BARs) or other similar means. Plug-and-play (PnP) software (PCI/ACPI) can
use their configuration mechanisms to set and adjust these values.

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Warning: The variable IO ranges should not be set to conflict with other IO ranges. There will be
unpredictable results if the configuration software allows conflicts to occur. Hardware
does not check for conflicts.

Table 42. Movable IO Ranges Decoded by PCI Devices on the IO Fabric

Size
Device Target
(bytes)

ACPI Power Management 128 ACPI_BASE_ADDR (PM1BLK): PCI[B:0,D:31,F:0] +

(PCU) 40h
SMBus (PCU) 32 SMBA: PCI[B:0,D:31,F:3] + 20h
GPIO (PCU) 256 GBA: PCI[B:0,D:31,F:0] + 48h
RCBA (PCU) 1024 RCRB_BA: PCI[B:0,D:31,F:0] + F0h

4.3 PCI Configuration Space

All PCI devices/functions are shown below.

Table 43. PCI Devices and Functions (Sheet 1 of 2)

Bus Device Function Device ID Device Description Function Description

0 0 0 0F00h SoC Transaction Router

0 2 0 0F31h Graphics & Display
0 3 0 0F38h Camera Image Signal
Processor
0 16 0 0F14h Storage Control Cluster eMMC Port (de-featured - use Device
(SCC) 23 instead)
0 17 0 0F15h SDIO Port
0 18 0 0F16h SD Port
0 19 0 0F20h (IDE) SATA
0F21h (IDE)
0F22h (AHCI)
0F23h (AHCI)
0 20 0 0F35h xHCI USB
0 21 0 0F28h Low Power Engine Audio Host Bridge + three I2S Ports (0-2)
0 22 0 0F37h USB Device
0 23 0 Storage Control Cluster eMMC 4.5 Port
(SCC)

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Table 43. PCI Devices and Functions (Sheet 2 of 2)

Bus Device Function Device ID Device Description Function Description

0 24 0 0F40h Serial IO (SIO) DMA

1 0F41h I2C Port 1
2 0F42h I2C Port 2
3 0F43h I2C Port 3
4 0F44h I2C Port 4
5 0F45h I2C Port 5
6 0F46h I2C Port 6
7 0F47h I2C Port 7
0 26 0 0F18h Trusted Execution Engine
0 27 0 0F04h HD Audio
0 28 0 0F48h PCI Express* Root Port 1
1 0F4Ah Root Port 2
2 0F4Ch Root Port 3
3 0F4Eh Root Port 4
0 29 0 0F34h EHCI USB
0 30 0 0F06h Serial IO (SIO) DMA
1 0F08h PWM Port 1
2 0F09h PWM Port 2
3 0F0Ah HSUART Port 1
4 0F0Ch HSUART Port 2
5 0F0Eh SPI Port
0 31 0 0F1Ch Platform Controller Unit LPC: Bridge to Intel Legacy Block
0 31 3 0F12h Platform Controller Unit SMBus Port

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Figure 8. Bus 0 PCI Devices and Functions

CPU
Core

SoC Transaction
Router
D:0,F:0
PCI
CAM
Graphics
(I/O)
D:2,F:0
Bus 0
PCI
ECAM
Camera ISP
(Mem)
D:3,F:0

#1 D:16,F:0
xHCI USB

MMC
SD/
D:20,F:0 #2 D:17,F:0
#3 D:18,F:0

USB Dev
D:22,F:0 SATA
D:19,F:0

DMA F:0
I2C0 F:1
LPE Audio (I2S)
I2C1 F:2
D:21,F:0
SIO D:24

I2C2 F:3
I2C3 F:4
I2C4 F:5
I2C5 F:6
I2C6 F:7

RP1 F:0
PCIe D:28

TXE
RP2 F:1 D:26,F:0
RP3 F:2
RP4 F:3
HDA
D:27,F:0
EHCI USB
D:29,F:0
DMA F:0
PWM1 F:1
SIO D:30

LPC (iLB) F:0 PWM2 F:2

D:31
PCU

SMB F:3 HSUART1 F:3

HSUART2 F:4
SPI F:5

§§

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5 Integrated Clock
Clocks are integrated, consisting of multiple variable frequency clock domains, across
different voltage domains. This architecture achieves a low power clocking solution that
supports the various clocking requirements of the SoC’s many interfaces.

Integrated Clock O

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Figure 9. Clocking Example

HDMI/eDP/DP
DDI[1:0]_TXP/N[3] DRAM0_CLKP/N[2,0] DRAM CHANNEL 0
DDI[1:0]_DDCCLK

DRAM1_CLKP/N[2,0] DRAM CHANNEL 1

MMC1_CLK eMMC

Misc PMC_PLT_CLK[5:0]
SDIO2_CLK SDIO

SD3_CLK SD CARD

25MHz
Primary Reference

32kHz iClock Clock Inputs

Primary Reference And Outputs

PMC_SUSCLK[3:0]
Power
PCIe PCIE_CLKP/N[3:0] SIO_I2C5_CLK Management/Seq.
SVID_CLK

5.1 Features
Platform clocking is provided internally by the Integrated Clock logic. No external clock
chips are required for the SoC to function. All the required platform clocks are provided
by two crystal inputs: a 25 MHz primary reference for the integrated clock block and a
32.768 kHz reference for the Real Time Clock (RTC) block.

The different inputs and outputs are listed below.

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Table 44. SoC Clock Inputs

Clock Domain Signal Name Frequency Usage/Description

Main ICLK_OSCIN 25 MHz Reference crystal for the iCLK PLL

ICLK_OSCOUT
RTC ILB_RTC_X1 32.768 kHz RTC crystal I/O for RTC block
ILB_RTC_X2
MIPI CSI MCSI1_CLKP/N 40-533 MHz Clocks for cameras
MCSI2_CLKP/N
MCSI3_CLKP/N
LPC ILB_LPC_CLK[1] 33 MHz Can be configured as an input to
compensate for board routing delays
through Soft Strap.
USB PHY USB_ULPI_CLK 60 MHz Interface clock from ULPI PHY.

Table 45. SoC Clock Outputs (Sheet 1 of 2)

Clock Domain Signal Name Frequency Usage/Description

Memory DRAM0_CKP/N[2,0] 533/667 MHz Drives the Memory ranks 0-1. Data
DRAM1_CKP/N[2,0] rate (MT/s) is 2x the clock rate.
Note: The frequency is fused in each
SoC. It is not possible to support both
frequencies on one SoC.
eMMC MMC1_CLK 25-50 MHz Clock for eMMC 4.41 devices
MMC1_45_CLK 25-200 MHz Clock for eMMC 4.51 devices
SDIO SD2_CLK 25-50 MHz Clock for SDIO devices
SD Card SD3_CLK 25-50 MHz Clock for SD card devices
SPI PCU_SPI_CLK 20 MHz, Clock for SPI flash
33 MHz,
50 MHz
PMIC/COMMS PMC_SUSCLK[3:0] 32.768 kHz Pass through clock from RTC oscillator
LPC ILB_LPC_CLK[0:1] 33 MHz Provided to devices requiring LPC
clock
HDA HDA_CLK 24 MHz Serial clock for external HDA codec
device
PCI Express PCIE_CLKN[3:0] 100 MHz Differential Clocks supplied to
PCIE_CLKP[3:0] external PCI express devices based
on assertion of PCIE_CLKREQ[3:0]#
inputs
USB PHY USB_ULPI_REFCLK 19.2 MHz Clock for USB devices
HDMI DDI[1:0]_TXP/N[3] 25-148.5 MHz Differential clock for HDMI devices
HDMI DDC DDI[1:0]_DDCCLK 100 kHz Clock for HDMI DDC devices
VGA DDC VGA_DDCCLK 100 kHz Clock for VGA DDC devices
SVID SVID_CLK 25 MHz Clock used by voltage regulator

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Table 45. SoC Clock Outputs (Sheet 2 of 2)

Clock Domain Signal Name Frequency Usage/Description

I2S LPE_I2S[2:0]_CLK 12.5 MHz Continuous serial clock for I2S

interfaces
Platform Clocks PMC_PLT_CLK [5:0] 19.2/25 MHz Platform clocks. For example:
PLT_CLK [2:0] - Camera
PLT_CLK [3] - Audio Codec
PLT_CLK [4] -
PLT_CLK [5] - COMMs
NOTE: Intel recommends 25 MHz.
19.2 MHz is not validated.
SIO SPI SIO_SPI_CLK 15 MHz SPI clock output
I2C SIO_I2C[6:0]_CLK 100 kHz, I2C clocks
400 kHz, Note: In I2C Controller the parameter
1 MHz, called IC_CAP_LOADING can be set to
3.4 MHz 400pf/100pf. As per specification
3.4MHz is supported in 100pf loading
while 1.7MHz is the max frequency at
400pf load.

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Power Management

6 Power Management
This chapter provides information on the following power management topics:
• ACPI States
• Processor Core
• PCI Express
• Integrated Graphics Controller

6.1 Power Management Features

• ACPI System States support (S0, S3, S4, S5)
• Processor Core/Package States support (C0 – C6)
• SoC Graphics Adapter States support D0 – D3.
• Support Link Power Management (LPM)
• Thermal throttling
• Dynamic I/O power reductions (disabling sense amps on input buffers, tri-stating
output buffers)
• Active power down of Display links

6.2 Power Management States Supported

The Power Management states supported by the processor are described in this
section.

6.2.1 S-State Definition

6.2.1.1 S0 - Full On

This is the normal operating state of the processor. In S0, the core processor will
transition in and out of the various processor C-States and P-States.

6.2.1.2 S3 - Suspend to RAM (Standby)

S3 is a suspend state in which the core power planes of the processor are turned off
and the suspend wells remain powered.
• All power wells are disabled, except for the suspend and RTC wells.
• The core processor’s macro-state is saved in memory.
• Memory is held in self-refresh and the memory interface is disabled, except the
CKE pin as it is powered from the memory voltage rail. CKE is driven low.

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6.2.1.3 S4 - Suspend to Disk (Hibernate)

S4 is a suspend state in which most power planes of the processor are turned off,
except for the suspend and RTC well. In this ACPI state, system context is saved to the
hard disk.

Key features:
• No activity is allowed.
• All power wells are disabled, except for the suspend and RTC well.

6.2.1.4 S5 - Soft Off

From a hardware perspective the S5 state is identical to the S4 state. The difference is
purely software; software does not write system context to hard disk when entering
S5.

The following table shows the differences in the sleeping states with regards to the
processor’s output signals.

NOTES:

Table 46. SoC Sx-States to SLP_S*#

Reset w/o Reset w/

State S0 S3 S4 S5
Power Cycle Power Cycle

CPU Executing In C0 OFF OFF OFF No OFF

PMC_SLP_S3# HIGH LOW LOW LOW HIGH LOW
PMC_SLP_S4# HIGH HIGH LOW LOW HIGH LOW
S0 Power Rails ON OFF OFF OFF ON OFF
PMC_PLTRST# HIGH0 LOW1 LOW1 LOW1 LOW1 LOW1
PMC_SUS_STAT# HIGH LOW LOW LOW HIGH LOW
PCIe Links L0, L1 L3 L3 L3 L3 Ready L3

NOTES:The processor treats S4 and S5 requests the same. The processor does not have
PMC_SLP_S5#. PMC_SUS_STAT# is required to drive low (asserted) even if core well is left
on because PMC_SUS_STAT# also warns of upcoming reset.

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6.2.2 System States

Table 47. General Power States for System

States/Sub-
Legacy Name / Description
states

G0/S0/C0 FULL ON: CPU operating. Individual devices may be shut down to save
power. The different CPU operating levels are defined by Cx states.
G0/S0/Cx Cx State: CPU manages C-state itself.
G1/S3 Suspend-To-RAM(STR): The system context is maintained in system
DRAM, but power is shut to non-critical circuits. Memory is retained, and
refreshes continue. All external clocks are shut off; RTC clock and internal
ring oscillator clocks are still toggling.
G1/S4 Suspend-To-Disk (STD): The context of the system is maintained on the
disk. All of the power is shut down except power for the logic to resume.
The S4 and S5 states are treated the same.
G2/S5 Soft-Off: System context is not maintained. All of the power is shut down
except power for the logic to restart. A full boot is required to restart. A full
boot is required when waking.
The S4 and S5 states are treated the same.
G3 Mechanical OFF. System content is not maintained. All power shutdown
except for the RTC. No “Wake” events are possible, because the system
does not have any power. This state occurs if the user removes the
batteries, turns off a mechanical switch, or if the system power supply is at
a level that is insufficient to power the “waking” logic. When system power
returns, transition will depend on the state just prior to the entry to G3.

Table 48 shows the transitions rules among the various states. Note that transitions
among the various states may appear to temporarily transition through intermediate
states. These intermediate transitions and states are not listed in the table.

Table 48. ACPI PM State Transition Rules (Sheet 1 of 2)

Present
Transition Trigger Next State
State

G0/S0/C0 IA Code MWAIT or LVL Rd C0/S0/Cx

PM1_CNT.SLP_EN bit set G1/Sx or G2/S5 state (specified by
PM1_CNT.SLP_TYP)
Power Button Override G2/S5
Mechanical Off/Power Failure G3
G0/S0/Cx Cx break events which include: CPU G0/S0/C0
snoop, MSI, Legacy Interrupt, AONT
timer
Power Button Override G2/S5
System Power Failure G3

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Table 48. ACPI PM State Transition Rules (Sheet 2 of 2)

Present
Transition Trigger Next State
State

G1/S3,G1/S4 Any Enabled Wake Event G0/S0/C0

Power button Override G2/S5
Resume Well Power Failure G3
G2/S5 Any Enabled Wake Event G0/S0/C0
Resume Well Power Failure G3
G3 Power Returns Option to go to S0/C0 (reboot) or G2/S5
(stay off until power button pressed or
other enabled wake event) or G1/S4 (if
system state was S4 prior to the power
failure). Some wake events are
preserved through a power failure.

6.2.3 Processor States

Table 49. Processor Core/ States Support

State Description

C0 Active mode, processor executing code

C1 AutoHALT state
C1E AutoHALT State with lowest frequency and voltage operating point.
C6 Deep Power Down. Prior to entering the Deep Power Down
Technology (code named C6) State, The core process will flush its
cache and save its core context to a special on die SRAM on a
different power plane. Once Deep Power Down Technology (code
named C6) sequence has completed. The core processor’s voltage
is completely shut off.

6.2.4 Integrated Graphics Display States

Table 50. SoC Graphics Adapter State Control

State Description

D0 Full on, Display active

D3 Power off display

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6.2.5 Integrated Memory Controller States

Table 51. Main Memory States

States Description

Powerup CKE asserted. Active mode.

Precharge Powerdown CKE de-asserted (not self-refresh) with all banks closed.
Active Powerdown CKE de-asserted (not self-refresh) with at least one bank active.
Self-Refresh CKE de-asserted using device self-refresh

6.2.6 PCIe* States

Table 52. PCIe* States

States Description

L0 Full on – Active transfer state

L0s First Active Power Management low power state – Low exit latency
L1 Lowest Active Power Management - Longer exit latency
L3 Lowest power state (power-off) – Longest exit latency

6.2.7 Interface State Combinations

Table 53. G, S and C State Combinations

Processor
Global Sleep Processor
Core System Clocks Description
(G) State (S) State State
(C) State

G0 S0 C0 Full On On Full On
G0 S0 C1/C1E Auto-Halt On Auto-Halt
G0 S0 C6 Deep Power On Deep Power Down
Down
G1 S3 Power off Off except RTC & internal Suspend to RAM
ring OSC
G1 S4 Power off Off except RTC & internal Suspend to Disk
ring OSC
G2 S5 Power off Off except RTC & internal Soft Off
ring OSC
G3 NA Power Off Power off Hard Off

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Table 54. D, S and C State Combinations

Graphics Adapter
Sleep (S) State (C) State Description
(D) State

D0 S0 C0 Full On, Displaying

D0 S0 C1 Auto-Halt, Displaying
D0 S0 C6 Deep Sleep, Display Off
D3 S0 Any Not Displaying
D3 S3 Not Displaying
Graphics Core power off.
D3 S4 Not Displaying
Suspend to disk
Core power off

6.3 Processor Core Power Management

While executing code, Enhanced Intel SpeedStep® Technology optimizes the
processor’s frequency and core voltage based on workload. Each frequency and voltage
operating point is defined by ACPI as a P-state. When the processor is not executing
code, it is idle. A low-power idle state is defined by ACPI as a C-state. In general, lower
power C-states have longer entry and exit latencies.

6.3.1 Enhanced Intel SpeedStep® Technology

The following are the key features of Enhanced Intel SpeedStep® Technology:
• Applicable to Processor Core Voltage and Graphic Core Voltage
• Multiple frequency and voltage points for optimal performance and power
efficiency. These operating points are known as P-states.
• Frequency selection is software controlled by writing to processor MSRs. The
voltage is optimized based on the selected frequency:
— If the target frequency is higher than the current frequency, Core_VCC_S3 is
ramped up slowly to an optimized voltage. This voltage is signaled by the SVID
signals to the voltage regulator. Once the voltage is established, the PLL locks
on to the target frequency.
— If the target frequency is lower than the current frequency, the PLL locks to the
target frequency, then transitions to a lower voltage by signaling the target
voltage on the SVID signals.
• The processor controls voltage ramp rates by requesting appropriate ramp rates
from an external SVID controller.
• Because there is low transition latency between P-states, a significant number of
transitions per second are possible.
• Thermal Monitor mode.

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— Please refer to Thermal Management Chapter

6.3.2 Dynamic Cache Sizing

Dynamic Cache Sizing allows the processor to flush and disable a programmable
number of L2 cache ways upon each Deeper Sleep entry under the following condition:
• The C0 timer that tracks continuous residency in the Normal state, has not expired.
This timer is cleared during the first entry into Deeper Sleep to allow consecutive
Deeper Sleep entries to shrink the L2 cache as needed.
• The predefined L2 shrink threshold is triggered.
The number of L2 cache ways disabled upon each Deeper Sleep entry is configured in
the BBL_CR_CTL3 MSR. The C0 timer is referenced through the
CLOCK_CORE_CST_CONTROL_STT MSR. The shrink threshold under which the L2
cache size is reduced is configured in the PMG_CST_CONFIG_CONTROL MSR. If the
ratio is zero, then the ratio will not be taken into account for Dynamic Cache Sizing
decisions. Refer to the BIOS Writer’s Guide for more details.

6.3.3 Low-Power Idle States

When the processor core is idle, low-power idle states (C-states) are used to save
power. More power savings actions are taken for numerically higher C-state. However,
higher C-states have longer exit and entry latencies. Resolution of C-state occur at the
thread, processor core, and processor core level.

6.3.3.1 Clock Control and Low-Power States

The processor core supports low power states at core level. The central power
management logic ensures the entire processor core enters the new common processor
core power state. For processor core power states higher than C1, this would be done
by initiating a P_LVLx (P_LVL6) I/O read to all of the cores. States that require external
intervention and typically map back to processor core power states. States for
processor core include Normal (C0, C1).

The processor core implements two software interfaces for requesting low power
states: MWAIT instruction extensions with sub-state specifies and P_LVLx reads to the
ACPI P_BLK register block mapped in the processor core’s I/O address space. The
P_LVLx I/O reads are converted to equivalent MWAIT C-state requests inside the
processor core and do not directly result in I/O reads on the processor core bus. The
monitor address does not need to be setup before using the P_LVLx I/O read interface.
The sub-state specifications used for each P_LVLx read can be configured in a software
programmable MSR by BIOS.

The Cx state ends due to a break event. Based on the break event, the processor
returns the system to C0. The following are examples of such break events:
• Any unmasked interrupt goes active
• Any internal event that will cause an NMI or SMI_B

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• CPU Pending Break Event (PBE_B)

• MSI
Figure 10. Idle Power Management Breakdown of the Processor Cores

Core 0 State Core 1 State

Processor Package State

6.3.4 Processor Core C-States Description

The following state descriptions assume that both threads are in common low power
state.

6.3.4.1 Core C0 State

The normal operating state of a core where code is being executed.

6.3.4.2 Core C1/C1E State

C1/C1E is a low power state entered when a core execute a HLT or MWAIT(C1/C1E)
instruction.

A System Management Interrupt (SMI) handler returns execution to either Normal

state or the C1/C1E state. See the Intel® 64 and IA-32 Architecture Software
Developer’s Manual, Volume 3A/3B: System Programmer’s Guide for more information.

While a core is in C1/C1E state, it processes bus snoops and snoops from other
threads. For more information on C1E, see “Package C1/C1E”.

6.3.4.3 Core C6 State

Individual core can enter the C6 state by initiating a P_LVL3 I/O read or an MWAIT(C6)
instruction. Before entering core C6, the core will save its architectural state to a
dedicated SRAM. Once complete, a core will have its voltage reduced to zero volts.
During exit, the core is powered on and its architectural state is restored.

There are various types of C-state:

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• C6NS implies only the core should be powergated, but the L2 cache contents
should be retained.
• C6IS implies the core should be powergated, and the L2 cache can be
incrementally flushed to get some additional power savings.
• C6FS implies the core should be powergates, and the L2 cache can be fully flushed
to get even more power savings.

6.3.5 Package C-States

The processor supports C0, C1/C1E, and C6 power states. The following is a summary
of the general rules for package C-state entry. These apply to all package C-states
unless specified otherwise:
• Package C-state request is determined by the lowest numerical core C-state
amongst all cores.
• A package C-state is automatically resolved by the processor depending on the
core idle power states and the status of the platform components.
• Each core can be at a lower idle power state than the package if the platform does
not grant the processor permission to enter a requested package C-state.
• The platform may allow additional power savings to be realized in the processor.
• For package C-states, the processor is not required to enter C0 before entering any
other C-state.
• Entry in to a package C-state may be subject to auto-demotion - that is the
processor may keep the package in a shallower package C-state then requested by
the OS if the processor determines via heuristics that the shallower C-state results
in better power/performance.

The processor exits a package C-state when a break event is detected. Depending on
the type of break event, the processor does the following:
• If a core break event is received, the target core is activated and the break event
message is forwarded to the target core.
— If the break event is not masked, the target core enters the core C0 state and
the processor enters package C0.
— If the break event is masked, the processor attempts to re-enter its previous
package state.
• If the break event was due to a memory access or snoop request.
— But the platform did not request to keep the processor in a higher package C-
state, the package returns to its previous C-state.
— And the platform requests a higher power C-state, the memory access or snoop
request is serviced and the package remains in the higher power C-state.

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Table 55. Coordination of Core/Module Power States at the Package Level

Core/Module 1
Package C-State
C0 C1 C6NS C6FS

C0 C0 C11 C0 C0
Core/Module 0

C1 C0 C11 C1 C11

C6NS C0 C11 C6C C6C

C6FS C0 C11 C6C C6

NOTES:

1. If enabled, the package C-state will be C1E if all actives cores have resolved a core C1 state or higher.
2. C6C is C6-Conditional where the L2 cache is still powered.
3. 2 Cores of the SoC will make up one module.

Figure 11. Package C-state Entry and Exit

C0

C1 C6

6.3.5.1 Package C0

The normal operating state for the processor. The processor remains in the normal
state when at least one of its cores is in the C0 state or when the platform has not
granted permission to the processor to go into a low power state. Individual cores may
be in lower power idle states while the package is in C0.

6.3.5.2 Package C1/C1E

No additional power reduction actions are taken in the package C1 state. However, if
the C1E sub-state is enabled, the processor automatically transitions to the lowest
supported core clock frequency, followed by a reduction in voltage.

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The package enters the C1 low power state when:

• At least one core is in the C1 state.
• The other cores are in a C1 or lower power state.
The package enters the C1E state when:
• All cores have directly requested C1E via MWAIT(C1) with a C1E sub-state hint.
• All cores are in a power state lower that C1/C1E but the package low power state is
limited to C1/C1E via the PMG_CST_CONFIG_CONTROL MSR.
• All cores have requested C1 using HLT or MWAIT(C1) and C1E auto-promotion is
enabled in IA32_MISC_ENABLES.

No notification to the system occurs upon entry to C1/C1E.

6.3.5.3 Package C6 State

A processor enters the package C6 low power state when:

• At least one core is in the C6 state.
• The other cores are in a C6 or lower power state, and the processor has been
granted permission by the platform.
• The platform has allowed a package C6 state.
In package C6 state, all cores have saved their architectural state and have had their
core voltages reduced to zero volts.

6.3.6 Graphics Power Management

6.3.6.1 Graphics and video decoder C-State

GFX C-State (GC6) and VED C-state (VC6) are designed to optimize the average power
to the graphics and video decoder engines during times of idleness. GFX C-state is
entered when the graphics engine, has no workload being currently worked on and no
outstanding graphics memory transactions. VED S-state is entered when the video
decoder engine has no workload being currently worked on and no outstanding video
memory transactions. When the idleness condition is met, the processor will power
gate the Graphics and video decoder engines.

6.3.6.2 Intel® Display Power Saving Technology (Intel® DPST)

The Intel DPST technique achieves backlight power savings while maintaining visual
experience. This is accomplished by adaptively enhancing the displayed image while
decreasing the backlight brightness simultaneously. The goal of this technique is to
provide equivalent end-user image quality at a decreased backlight power level.
1. The original (input) image produced by the operating system or application is
analyzed by the Intel DPST subsystem. An interrupt to Intel® DPST software is
generated whenever a meaningful change in the image attributes is detected. (A
meaningful change is when the Intel DPST software algorithm determines that

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enough brightness, contrast, or color change has occurred to the displaying images
that the image enhancement and backlight control needs to be altered.)
2. Intel DPST subsystem applies an image-specific enhancement to increase image
contrast, brightness, and other attributes.
3. A corresponding decrease to the backlight brightness is applied simultaneously to
produce an image with similar user-perceived quality (such as brightness) as the
original image. Intel DPST 5.0 has improved the software algorithms and has minor
hardware changes to better handle backlight phase-in and ensures the documented
and validated method to interrupt hardware phase-in.

6.3.6.3 Intel® Automatic Display Brightness

The Intel Automatic Display Brightness feature dynamically adjusts the backlight
brightness based upon the current ambient light environment. This feature requires an
additional sensor to be on the panel front. The sensor receives the changing ambient
light conditions and sends the interrupts to the Intel Graphics driver. As per the change
in Lux, (current ambient light illuminance), the new backlight setting can be adjusted
through BLC. The converse applies for a brightly lit environment. Intel Automatic
Display Brightness increases the back light setting.

6.3.6.4 Intel® Seamless Display Refresh Rate Switching Technology (Intel®

SDRRS Technology)

When a Local Flat Panel (LFP) supports multiple refresh rates, the Intel® Display
Refresh Rate Switching power conservation feature can be enabled. The higher refresh
rate will be used when on plugged in power or when the end user has not selected/
enabled this feature. The graphics software will automatically switch to a lower refresh
rate for maximum battery life when the design application is on battery power and
when the user has selected/enabled this feature.

There are two distinct implementations of Intel SDRRS—static and seamless. The static
Intel SDRRS method uses a mode change to assign the new refresh rate. The seamless
Intel SDRRS method is able to accomplish the refresh rate assignment without a mode
change and therefore does not experience some of the visual artifacts associated with
the mode change (SetMode) method.

6.4 Memory Controller Power Management

The main memory is power managed during normal operation and in low-power ACPI
Cx states.

6.4.1 Disabling Unused System Memory Outputs

Any system memory (SM) interface signal that goes to a memory module connector in
which it is not connected to any actual memory devices (such as DIMM connector is
unpopulated, or is single-sided) is tri-stated. The benefits of disabling unused SM
signals are:

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• Reduced power consumption.

• Reduced possible overshoot/undershoot signal quality issues seen by the processor
I/O buffer receivers caused by reflections from potentially un-terminated
transmission lines.

When a given rank is not populated, the corresponding chip select and CKE signals are
not driven.

At reset, all rows must be assumed to be populated, until it can be proven that they are
not populated. This is due to the fact that when CKE is tristated with an SO-DIMM
present, the DIMM is not guaranteed to maintain data integrity.

SCKE tri-state should be enabled by BIOS where appropriate, since at reset all rows
must be assumed to be populated.

6.4.2 DRAM Power Management and Initialization

The processor implements extensive support for power management on the SDRAM
interface. There are four SDRAM operations associated with the Clock Enable (CKE)
signals, which the SDRAM controller supports. The processor drives four CKE pins to
perform these operations.

6.4.2.1 Initialization Role of CKE

During power-up, CKE is the only input to the SDRAM that is recognized (other than the
DDR3 reset pin) once power is applied. It must be driven LOW by the DDR controller to
make sure the SDRAM components float DQ and DQS during power- up.

CKE signals remain LOW (while any reset is active) until the BIOS writes to a
configuration register. Using this method, CKE is guaranteed to remain inactive for
much longer than the specified 200 micro-seconds after power and clocks to SDRAM
devices are stable.

6.4.2.2 Conditional Self-Refresh

Intel Rapid Memory Power Management (Intel RMPM) conditionally places memory into
self-refresh in the package C3 and C6 low-power states. RMPM functionality depends
on graphics/display state (relevant only when internal graphics is being used), as well
as memory traffic patterns generated by other connected I/O devices.

When entering the Suspend-to-RAM (STR) state, the processor core flushes pending
cycles and then places all SDRAM ranks into self refresh. In STR, the CKE signals
remain LOW so the SDRAM devices perform self-refresh.

The target behavior is to enter self-refresh for the package C3 and C6 states as long as
there are no memory requests to service.

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6.4.2.3 Dynamic Power Down Operation

Dynamic power-down of memory is employed during normal operation. Based on idle

conditions, a given memory rank may be powered down. The IMC implements
aggressive CKE control to dynamically put the DRAM devices in a power down state.The
processor core controller can be configured to put the devices in active power down
(CKE deassertion with open pages) or precharge power down (CKE deassertion with all
pages closed). Precharge power down provides greater power savings but has a bigger
performance impact, since all pages will first be closed before putting the devices in
power down mode.

If dynamic power-down is enabled, all ranks are powered up before doing a refresh
cycle and all ranks are powered down at the end of refresh.

6.4.2.4 DRAM I/O Power Management

Unused signals should be disabled to save power and reduce electromagnetic

interference. This includes all signals associated with an unused memory channel.
Clocks can be controlled on a per SO-DIMM basis. Exceptions are made for per SO-
DIMM control signals such as CS#, CKE, and ODT for unpopulated SO-DIMM slots.

The I/O buffer for an unused signal should be tri-stated (output driver disabled), the
input receiver (differential sense-amp) should be disabled, and any DLL circuitry
related ONLY to unused signals should be disabled. The input path must be gated to
prevent spurious results due to noise on the unused signals (typically handled
automatically when input receiver is disabled).

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6.5 PCIe* Power Management

• Active power management support using L0s, and L1 states.
• All inputs and outputs disabled in L3 Ready state.

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7 Power Up and Reset Sequence

This chapter provides information on the following topics:
• Power Up Sequences
• Power Down Sequences
• Reset Behavior

7.1 SoC System States

7.1.1 System Sleeping States Control (S-states)

The SoC supports the S0, S3, S4, and S5 sleep states. S4 and S5 states are identical
from a hardware and power perspective. The differentiation is software determined (S4
= Suspend to Disk).

The SoC platform architecture assumes the usage of an external power management
controller e.g., CPLD or PMIC. Some flows in this section refer to the power
management controller for support of the S-states transitions.

The SoC sleep states are described in Chapter 6, “Power Management”.

7.2 Power Up Sequences

7.2.1 RTC Power Well Transition (G5 to G3 States Transition)

When RTC_VCC (Real Time Clock power) is applied via RTC battery, the following
occurs (see Figure 12 for timing):
1. RTC_VCC ramps. ILB_RTC_TEST# should be low.
2. The system starts the real time clock oscillator.
3. A minimum of t1 units after RTC_VCC ramps, the external RTC RC circuit de-asserts
ILB_RTC_TEST#. The system is now in the G3 state. RTC oscillator is unlikely to be
stable at this point.

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Figure 12. RTC Power Well Timing Diagrams

G3
RTC_VCC
t1

ILB_RTC_TEST#

Osc Startup Clock Valid

ILB_RTC_CLK

Table 56. RTC Power Well Timing Parameters

Parameter Description Min Max Units

t1 RTC_VCC to ILB_RTC_TEST# de-assertion 9 - ms

NOTES:
1. This delay is typically created from an RC circuit.
2. The oscillator startup times are component and design specific. A crystal oscillator can take several
second to reach a large enough voltage swing. A silicon oscillator can have startups times <10 ms.
3. Pre-silicon estimates

7.2.2 G3 to S0
The timings shown in Figure 13 occur when a board event such as AC power is applied
or power management controller (PMIC) power button is pressed. The following occurs:
1. Suspend (SUS/Always On) wells ramp in the order shown.
2. The external power management controller de-asserts PMC_RSMRST# after the
suspend rails become stable.
3. PMC_SUSCLK will begin toggling after the de-assertion of PMC_RSMRST#.
4. The system is now in S4/S5 state. Depending on policy bits, the SoC either waits
for a wake event to transition to S0, continues to S0 state automatically, or
proceeds to SoC G3 for power savings.
5. The transition from S4/S5 to S0 is initiated.
6. The SoC de-asserts PMC_SLP_S4#, and the DRAM (VDD/Un-switched) well ramps.
7. After the DRAM power rail ramp, the external power management controller drives
DRAM_VDD_S4_PWROK high.
8. The SoC de-asserts PMC_SLP_S3#, and the Core (S0/Switched On) wells ramp in
the order shown.
9. After all of Core power rails are stable, external power management controller
drives PMC_CORE_PWROK and DRAM_CORE_PWROK to HIGH followed by
PMC_SUS_STAT#.

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10. The SoC de-asserts PMC_PLTRST# after PMC_SUS_STAT# is stable. The

PMC_PLTRST# is the main platform reset to other components.
11. The SoC will begin fetching data from the PCU-located SPI interface and proceed to
finish initialization and start code execution (BIOS).

Note: There is no hard time requirement for transitions for the Always on/SUS rails (V1.0A,
V1.2A, V1.8A, V3.3A). A 10us to 2000us delay is required for two adjacent rails of them
to avoid inrush current which may be caused by multiple loads turning on
simultaneously or fast charging of VR output decoupling. Please contact your Intel
representative for detailed parameters.

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Figure 13. G3/S5 to S0 Cold Boot Sequence

RTC_VCC

RTC Internal Clock

Clock Stable
(from xtal)

t1
ILB_RTC_TEST# (I)
ILB_RTC_RST# (I)
Board
V3P3A Event
Always On/SUS

V1P0A

V1P8A

V1P24A
t2
t3
t1

PMC_RSMRST# (I)

t4

PMC_SUSCLK[0] (O)

High if entering SoC G3

PMC_SUSPWRDNACK (O)
(no wake events enabled)

Event
PMC_SLP_S4# (O)

Unswitched VDD

DRAM_VDD_S4_PWROK (I)

t5

PMC_SLP_S3# (O) Event

VNN

VCC

V1P0S
V1P0Sx

V1P05S
Switched On/CORE

V1P35S

V1P8S

V1P24S

V3P3S

VDD_VTT

t6

DRAM_CORE_PWROK (I)

PMC_CORE_PWROK (I)

PCU SPI Interface SoftStraps Read

t7
PMC_SUS_STAT# (O)

t8

PMC_PLTRST# (O)

G5G3 G3S5/S4 S4/S5S3 S3S0

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S4/S5 to S0 (Power Up) Sequence

Parameter Min Max Unit

t1 RTC_VCC to ILB_RTC_TEST# de-assertion 9 - ms

RTC_VCC to PMC_RSMRST# de-assertion
t2 V3P3A (SUS Rails) valid to PMC_RSMRST# de-assertion 10 - us
(t1 still applies in applications without RTC battery)
t3 PMC_RSMRST# to Internal RTC Clock stable2 - 100 ms
t4 Internal RTC Clock stable to PMC_SUSCLK[0] toggling 5 - ms
t5 PMC_SLP_S4# de-assertion to PMC_SLP_S3# de- 26 - us
assertion
t6a Core well stable to DRAM_CORE_PWROK and 10 - ms
PMC_CORE_PWROK assertion (No PCIe devices)
t6b Core well stable to DRAM_CORE_PWROK and 99 - ms
PMC_CORE_PWROK assertion (for power rails needed by
PCIe devices)
t7 DRAM/PMC_CORE_PWROK to PMC_SUS_STAT# 1 - ms
t8 PMS_SUS_STAT# de-assertion to PMC_PLTRST# de- 60 - us
assertion

NOTES:.
1. RTC and SUS power rails may come up at the same time if no RTC battery is used.
2. Must ensure RTC clock is oscillating within this time, but may not be at 32.768 KHz yet. Depending on
how stable the oscillations are, this time could be longer.
3. Wake events show in figure depend on platform configuration.
4. In the SUS rail sequence, V3P3A can be first in sequence if required for designs with exists 3.3 V rails.
5. For power rail sequences, a 10us delay is required between rails to avoid inrush current caused by
multiple loads turning on simultaneously and fast charging of VR output decoupling. A maximum delay
of 10ms is allowed. Please contact your Intel representative for additional details.
6. VCC can follow VNN in the CORE rail sequence or at the same time. Reference platform sequences both
at the same time.
7. “Board Event” is platform specific. Most likely enabled by a platform power management controller or
PMIC via a dedicated power button or when AC power is applied.
8. For exit from S4 and S3 Events, see “Cause of Wake Events” table in this chapter. S4 wake is required
from PMC_PWRBTN# without prior configuration. S3 wake event is only used when the platform directly
transitions to S3 (STR).

7.3 Power Down Sequences

7.3.1 S0 to S3 and S4/S5/G3 Sequence

Entry to Sleep states (S3,S4, S5) is initiated by any of the following methods:
• Setting the desired sleep type in PM1_CNT.SLP_TYP and setting PM1_CNT.SLP_EN.
• Detection of an external catastrophic temperature event may cause a transition to
S5, if the system is designed to do so.

The following sequence applies to S0-S3 and S0-S4/S5 transitions.

1. The Operating System Power Management (OSPM) will handle the enabling or
disabling of interrupt generation after S3 resume. The Operating System Power

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Management (OSPM) will need to read and clear Wake status information and the
processing of the clearing wake status which will include enabling interrupts (both
at the core level and platform level).
2. All interrupts in the processor need to be disabled before the S3 sequence is
started (and re-enabled on exit). The CPU APIC must be disabled.
3. When the desired sleep state is set in the PM1_CNT.TYP and PM1_CNT.SLP_EN
registers, a sleep state request is sent to the PMC.
4. The PMC flushes all the internal buffers to main memory.
5. The PMC places the PCI Express* devices into the L2/L3 state. The PMC will wait
until the PCI Express* devices are in the L2/L3 state before preceding. A timeout
will occur in 1 ms if there is a non-functional PCI Express* device.

The Power Down Sequence is shown in Figure 14 below.

Other Assumptions:
• Entry to a Cx state is mutually exclusive with software-initiated entry to a Sleep
state. This is because the processor(s) can only perform one register access at a
time. This requirement is enforced by the CPU as well as the OS. The system may
hang if it attempts to do a C-state and S-state at the same time.
• The G3 system state cannot be entered via any software mechanism. The G3 state
indicates a complete loss of power. In this state, the RTC well may or may not be
powered by an external coin cell battery.
• An external Power Management Controller (PMIC/EC) can be used to put the
processor in G3 when the S4/S5 state is requested by the SoC. This is done to save
power in S4/S5 state. This G3 like state is enabled by removing SUS rails via the
SUSPWRDNACK pin. Doing so prevents the use of any of SUS wake events
including USB, RTC, and GPIOs including the power button. The external Power
Management Controller (or re-application of power) is required to return to S0.

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 Power Up and Reset Sequence

Figure 14. S0 to S4/S5 (Power Down) Sequence without S0ix

PMC_PLTRST# (O)

PMC_SLP_S3# first, PMC_SLP_S4#

PMC_SLP_S3# (O)
at the same time or just after.

PMC_CORE_PWROK (I)

DRAM_CORE_PWROK (I)

VDD_VTT

V3P3S

V1P24S

V1P8S
Switched On/CORE

V1P35S

V1P05S

V1P0S

VCC

VNN

PMC_SLP_S4# (O)

DRAM_VDD_S4_PWROK (I)

Unswitched VDD

PMC_RSMRST# (I)

V3P3A
Always On/SUS

V1P24A

V1P8A

V1P0A

Note: SUS rails turned off only if entering SoC G3 state.

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7.3.2 S3/S4/S5 to S0 (Exit Sleep States)

Sleep states (S3-S5) are exited based on Wake events. The Wake events will force the
system to a full on state (S0), although some non-critical subsystems might still be
powered down and have to be brought back manually. For example, the hard disk may
be powered down during a sleep state, and have to be enabled via an I/O pin before it
can be used. Upon exit from software-entered Sleep states (i.e., those initiated via the
PM1_CNT.SLP_EN bit), the PM1_STS_EN.WAK_STS bit will be set.

To enable Wake Events, the possible causes of wake events (and their restrictions) are
shown in Table 57.

Table 57. S3/S4/S5 to S0 Cause of Wake Events

Cause Type How Enabled

RTC Alarm Internal Set PM1_STS_EN.RTC_EN register bit

PMC_PWRBTN# External Default enabled as Wake event
(Power Button)
GPIO_S5[7:0] External GPE0a_EN register (after having gone to S5 via
PM1_CNT.SLP_EN, but not after a power failure.)
Note: GPIOs that are in the core well are not capable of
waking the system from sleep states where the core
well is not powered.
PMC_WAKE_PCIE[0:3]# External PM1_STS_EN.PCIEXP_WAKE_EN register bit
(PCI Express WAKE#) Note: When the PMC_WAKE_PCIE# pin is active and
the PM1_STS_EN.PCIEXP_WAKE_EN register bit is
clear, CPU will wake the platform.
Primary PME# Internal GPEOa_EN.PME_B0_EN register bit. This wake status
bit includes multiple internal agents:
HD Audio
EHCI (USB2)
SATA
Note: SATA can only trigger a wake event if it had
asserted its PME prior to S3/S4/S5 entry and software
doesn't clear GPE0a_STS.PME_B0_STS, a wake event
would still result.
PME_B0_S5_DIS bit is used to prevent these devices
from waking from S5. Does not apply to wake from S3.
PMC - Initiated Internal No enable bits. The PMC can wake the host
independent of other wake events listed, if desired. A
bit is provided in PRSTS for reporting this wake event
to BIOS. Note that this wake event may be used as a
wake trigger on behalf of some other wake source.

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 Power Up and Reset Sequence

7.3.3 Handling Power Failures

The power failures can occur if the AC power or battery is removed. In this case, when
the system was originally in a S0 state, power failure bit (GEN_PMCON1.PWR_FLR) is
set after a power failure. Software can clear the bit.

7.4 Reset Behavior

There are several ways to reset the processor.

Table 58. Types of Resets (Sheet 1 of 2)

Trigger Description Note

Write of 0Eh to Reset Control Write of 0Eh to the Reset Control Host Reset with Power Cycle
Register (RST_CNT) register
Write of 06h to Reset Control Write of 06h to the Reset Control Host Reset without Power Cycle
Register (RST_CNT) register
PMC_RSTBTN# & User presses the reset button, Host Reset without Power Cycle
RST_CNT.full_rst = 0 causing the PMC_RSTBTN# signal
to go active (after the debounce
logic)
PMC_RSTBTN# & User presses the reset button, Host Reset with Power Cycle
RST_CNT.full_rst = 1 causing the PMC_RSTBTN# signal
to go active (after the debounce
logic)
Power Failure PMC_CORE_PWROK signal goes Global, Power Cycle Reset
inactive in S0/S1
S4/S5 The processor is reset when going Sx Entry
to S4 or S5 state
Processor Thermal Trip The internal thermal sensor signals Go-to-S5
a catastrophic temperature
condition – transition to S5 and
reset asserts
PMC_PWRBTN# Power Button 4-second press causes transition to Go-to-S5
Override S5 (and reset asserts)
CPU Shutdown with Policy to assert Shutdown special cycle from CPU Global, Power Cycle Reset (if
PMC_PLTRST# can cause either INIT or Reset ETR.CF9GR = 1b)
Control-style PMC_PLTRST# Host Reset with Power Cycle (if
RST_CNT.full_rst= 1b,
Host Reset without Power Cycle
(others setting)
Write of 06h or 0Eh to Reset Control ETR.CF9GR = 1b Global, Power Cycle Reset
Register (RST_CNT)

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Table 58. Types of Resets (Sheet 2 of 2)

Trigger Description Note

Host Partition Reset Entry Timeout Host partition reset entry sequence Global, Power Cycle Reset
took longer than the allowed
timeout value (presumably due to a
failure to receive one of the internal
or external handshakes)
S3/S4/S5 Entry Timeout S3, S4, or S5 entry sequence took Go-to-S5
longer than the allowed timeout
value (presumably due to a failure
to receive one of the internal or
external handshakes)
Watchdog Timer Firmware hang and Watchdog Go-to-S5
Timeout is detected

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 Thermal Management

8 Thermal Management

8.1 Overview
The SoC’s thermal management system helps in managing the overall thermal profile
of the system to prevent overheating and system breakdown. The architecture
implements various proven methods of maintaining maximum performance while
remaining within the thermal spec. Throttling mechanisms are used to reduce power
consumption when thermal limits of the device are exceeded and the system is notified
of critical conditions via interrupts or thermal signalling pins. SoC thermal management
differs from legacy implementations primarily by replacing dedicated thermal
management hardware with firmware.

The thermal management features are:

• Five digital thermal sensors (DTS)
• Supports a hardware trip point and four programmable trip points based on the
temperature indicated by thermal sensors.
• Supports different thermal throttling mechanisms.

8.2 CPU Thermal Management Registers

The description of the control and status registers can be found in the RS - Bay Trail
SoC BIOS Writer’s Guide.

8.3 Thermal Sensors

SoC provides thermal sensors that use ring oscillator based DTS (Digital Thermal
Sensor) to provide more accurate measure of system thermals.

The SoC instantiates multiple digital thermal sensors (one DTS for each processor core,
one for each BIU-Bus Interface Unit, and two for non-core SoC) and sensor grouping
configurations are provided to optionally select the maximum of all sensors for thermal
readout and interrupt generation.

DTS output are adjusted for silicon variations. For a given temperature the output from
DTS is always the same irrespective of silicon.

Table 59. Temperature Reading Based on DTS (If TJ-MAX =90οC) (Sheet 1 of 2)

DTS Counter Value Temperature Reading

127 90οC
137 80οC
147 70οC
157 60οC

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Table 59. Temperature Reading Based on DTS (If TJ-MAX =90οC) (Sheet 2 of 2)

DTS Counter Value Temperature Reading

167 50οC
177 40οC
187 30οC
197 20οC
207 10οC

Note: DTS encoding of 127 always represents TJ-MAX.If TJ-MAX is at 100oC instead of 90oC
then the encoding 127 from DTS indicates 100OC, 137 indicates 90OC and so forth.

Thermal trip points are of two types:

• Hard Trip: The Catastrophic trip points generated by DTS’s based on predefined
temperature setting defined in fuses.
• Programmable Trips: four programmable trip settings (Hot, Aux2, Aux1, Aux0)
that can be set by firmware/software. Default value for Hot Trip is from Fuses.

Note: DTS accuracy is around 8oC under 60oC and around 6oC above 60oC.

8.4 Hardware Trips

8.4.1 Catastrophic Trip (THERMTRIP)

Catastrophic trip is generated by DTS whenever the ambient temperature around it
reaches (or extends) beyond the max value (indicated by a fuse). Catastrophic trip will
not trip unless enabled (DTS are enabled only after HFPLL is locked). Within each DTS
Catastrophic trips are flopped to prevent any glitches on Catastrophic signals from
affecting the SoC behavior. Catastrophic trips are reset, once set, during power cycles.

Catastrophic trip signals from all DTS in the SoC are combined to generate THERMTRIP
function which will in turn shut off all the PLL’s and power rails to prevent SoC
breakdown. To prevent glitches from triggering shutdown events, Catastrophic trip’s
from DTS’s are registered before being sent out.

8.5 SoC Programmable Trips

Programmable trips can be programmed to cause different actions when triggered to
reduce temperature of the die.

8.5.1 Aux3 Trip

By default, the Aux 3 (Hot Trip) point is set by fuses but the software/firmware has an
option to set these to a different value.

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This trip point is enabled by firmware to monitor and control the system temperature
while the rest of the system is being set up.

8.5.2 Aux2, Aux1, Aux0 Trip

These are fully programmable trip points for general hardware protection mechanisms.
The programmable trips are only active after software/firmware enables the trip.

Note: Unlike Aux3, the Aux[2:0] trip registers are defaulted to zero. To prevent spurious
results, software/firmware should program the trip values prior to enabling the trip
point.

8.6 Platform Trips

8.6.1 PROCHOT#
The platform components use the signal PROCHOT# to indicate thermal events to SoC.
The processor core HOT trip as well as the processor AUX 3 trip are individually sent to
firmware, which internally combines them and drives the appropriate PROCHOT back.
Assertion of the PROCHOT# input will trigger Thermal Monitor 1 or Thermal Monitor 2
throttling mechanisms if they are enabled.

8.7 Thermal Throttling Mechanisms

Thermal throttling mechanisms are implemented to try to reduce temperature by
reducing power consumption in response to a HOT condition. Actions taken as a result
of Thermal Trip indication can be as simple as throttling bandwidth and frequency to as
drastic as shutting down the PLL’s and the entire system. Actions are primarily taken in
to prevent system breakdown and are dependent on the severity of the trips.

8.8 Thermal Status

The firmware captures Thermal Trip events (other than THERMTRIP) in status registers
to trigger thermal actions. Associated with each event is a set of programmable
actions. For a complete list of refer to the RS - Bay Trail SoC BIOS Writer’s Guide.

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9 Electrical Specifications
This chapter is split into the following sections:
• “Thermal Specifications”
• “Storage Conditions”
• “Voltage and Current Specifications”
• “Crystal Specifications”
• “DC Specifications”
• “AC Specifications”

9.1 Thermal Specifications

These specifications define the operating thermal limits of the SoC. Thermal solutions
not designed to provide the following level of thermal capability may affect the long-
term reliability of the processor and system, but more likely result in performance
throttling to ensure silicon junction temperatures within spec. For more details on
thermal solution design, please refer to this product's Thermal/Mechanical Design
Guide.

This section specifies the thermal specifications for all SKUs. Some definitions are
needed, however. “Tj Max” defines the maximum operating silicon junction
temperature. Unless otherwise specified, all specifications in this document assume Tj
Max as the worse case junction temperature. This is the temperature needed to ensure
TDP specifications when running at guaranteed CPU and graphics frequencies. “TDP”
defines the thermal dissipated power for a worse case estimated real world thermal
scenario.

Table 60. Intel® Atom™ Processor E3800 Product Family Thermal Specifications

SKU Tj Min/Max TDP

E3845 -40 to 110 °C 10 W @ Tj Max

E3827 -40 to 110 °C 8 W @ Tj Max
E3826 -40 to 110 °C 7 W @ Tj Max
E3825 -40 to 110 °C 6 W @ Tj Max
E3815 -40 to 110 °C 5 W @ Tj Max

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9.2 Storage Conditions

This section specifies absolute maximum and minimum storage temperature and
humidity limits for given time durations. Failure to adhere to the specified limits could
result in physical damage to the component. If this is suspected, Intel recommends a
visual inspection to determine possible physical damage to the silicon or surface
components.

Table 61. Storage Conditions Prior to Board Attach

Symbol Parameter Min Max

Tabsolute storage Device storage temperature when -25 °C 125 °C

exceeded for any length of time.
Tshort term storage The ambient storage temperature and -25 °C 85 °C
time for up to 72 hours.
Tsustained storage The ambient storage temperature and -5 °C 40 °C
time for up to 30 months.
RHsustained storage The maximum device storage relative 60% @ 24 °C
humidity for up to 30 months.

Note:

• Specified temperatures are not to exceed values based on data collected.

Exceptions for surface mount re-flow are specified by the applicable JEDEC
standard. Non-adherence may affect processor reliability.
• Component product device storage temperature qualification methods may follow
JESD22-A119 (low temperature) and JESD22-A103 (high temperature) standards
when applicable for volatile memory.
• Component stress testing is conducted in conformance with JESD22-A104.
• The JEDEC J-JSTD-020 moisture level rating and associated handling practices
apply to all moisture sensitive devices removed from the moisture barrier bag.

9.2.1 Post Board-Attach

The storage condition limits for the component once attached to the application board
are not specified. Intel does not conduct component-level certification assessments
post board-attach given the multitude of attach methods, socket types, and board
types used by customers.

Provided as general guidance only, board-level Intel-branded products are specified

and certified to meet the following temperature and humidity limits:
• Non-Operating Temperature Limit: -40 °C to 70 °C
• Humidity: 50% to 90%, non-condensing with a maximum wet-bulb of 28 °C

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9.3 Voltage and Current Specifications

The I/O buffer supply voltages are specified at the SoC package balls. The tolerances
shown in Table 79 are inclusive of all noise from DC up to 20 MHz. The voltage rails
should be measured with a bandwidth limited oscilloscope with a roll-off of 3 dB/decade
above 20 MHz under all operating conditions. Table 87 indicates which supplies are
connected directly to a voltage regulator or to a filtered voltage rail. For voltage rails
that are connected to a filter, they should be measured at the input of the filter. If the
recommended platform decoupling guidelines cannot be met, the system designer will
have to make trade-offs between the voltage regulator out DC tolerance and the
decoupling performances of the capacitor network to stay within the voltage tolerances
listed below.

Note: The Bay Trail SoC is a pre-launch product. Voltage and current specifications are
subject to change.

Voltage
Platform Rail Max Icc
Tolerances

V1P0A 1.0 V
- UNCORE_V1P0_G3 375 mA
- USB3_V1P0_G3 DC: ±2%
AC: ±3%
V1P24A 1.24 V
- USB_HSIC_V1P24_G3
35 mA
(Can connect to V1P0A when DC: ±3%
USB HSIC isn’t used) AC: ±2%

V1P8A
- PCU_V1P8_G3 1.8 V
- PMC_V1P8_G3
65 mA
- UNCORE_V1P8_G3 DC: ±3%
- USB_V1P8_G3 AC: ±2%
- USB_ULPI_V1P8_G3
V3P3A 3.3 V
- PCU_V3P3_G3 55 mA
DC: ±2%
- USB_V3P3_G3
AC: ±3%
V1P0S
- GPIO_V1P0_S3
- PCIE_SATA_V1P0_S3
- PCIE_V1P0_S3 1.0 V
- SATA_V1P0_S3 1.1 A
DC: ±2%
- SVID_V1P0_S3 AC: ±3%
- USB3DEV_V1P0_S3
- USB_V1P0_S3
- VGA_V1P0_S3

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Voltage
Platform Rail Max Icc
Tolerances

V1P0S 1.0 V
- DRAM_V1P0_S3
2.5 A
- DDI_V1P0_S3 DC: ±2%
- UNCORE_V1P0_S3 AC: ±3%

V1P05S 1.05 V
- CORE_V1P05_S3 1.3 A
DC: ±2%
AC: ±3%
V1P24S 1.24 V
- MIPI_V1P24_S3 (can be
45 mA
grounded if MIPI CSI not DC: ±2%
used) AC: ±3%
V1P35S (VSFR)
- ICLK_V1P35_S3_F[2:1] 1.35 V
- VGA_V1P35_S3_F1 400 mA
DC: ±3%
- DRAM_V1P35_S3_F1 AC: ±2%
- UNCORE_V1P35_S3_F[6:1]
V1P5V1P8S (VAUD) 1.5 V (LV HDA)
In V1P8S
- HDA_LPE_V1P5V1P8_S3 1.8 V (LPE)
V1P8S 1.8 V
- UNCORE_V1P8_S3 10 mA
DC: ±3%
- MIPI_V1P8_S3
AC: ±2%
V1P8V3P3S (VSDIO,VLPC) 1.8 V
- LPC_V1P8V3P3_S3 3.3 V (V3P3A)
8 mA
- SD3_V1P8V3P3_S3
DC: ±2%
AC: ±3%
V3P3S 3.3 V
- VGA_V3P3_S3 35 mA
DC: ±2%
AC: ±3%
VCC
See Table 63 See Table 62
- CORE_VCC_S3
VNN
See Table 63 See Table 62
- UNCORE_VNN_S3
VDD 1.35 V
- DRAM_VDD_S4 1.3 A
DC: ±2%
AC: ±3%
VRTC G3: 2-3 V at
100 uA
- RTC_VCC battery*
(6 uA Avg.)
Otherwise: V3P3A
(see note)
(pre diode drop)

Note: RTC_VCC average current draw (G3) is specified at 27°C under battery conditions.

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Note: When VGA is used, LPC must be 3.3V as well.

Table 62. VCC and VNN Currents

SKU VCC Icc Max VNN Icc Max

E3845 9 10
E3827 4 10
E3826 4 10
E3825 4 9
E3815 2 8

9.3.1 VCC and VNN Voltage Specifications

Table 63 and Table 79 list the DC specifications for the SoC power rails. They are valid
only while meeting specifications for junction temperature, clock frequency, and input
voltages. Care should be taken to read all notes associated with each parameter.

Table 63. VCC and VNN DC Voltage Specifications

Symbol Parameter Min Typ Max Unit Note

CORE_VCC VID Core VID Target Range 0.40 1.0 V

CORE_VCC_S3 VCC for SoC Core See VCC VID V 2, 5
UNCORE_VNN VID Uncore VID Target Range 0.50 1.05 V
UNCORE_VNN_S3 VNN for SoC Uncore See VNN VID V 2, 5
CORE_VCC/ Default target VCC/VNN voltage for 1.0 or V 4
UNCORE_VNN initial power up. 1.1
VBOOT
SLOPELL Processor Core Supply DC Loadline -5.9 mΩ Figure 15

NOTES:
1. See your Intel representative for load line and tolerance details.
2. Each SoC is programmed with voltage identification value (VID), which is set at manufacturing and
cannot be altered. Individual VID values are calibrated during manufacturing such that two SoCs at the
same frequency may have different settings within the VID range. Please note this differs from the VID
employed by the SoC during a power management event.
3. These are pre-silicon estimates and are subject to change.
4. See the VR12/IMVP7 Pulse Width Modulation specification for additional details. Either value is ok.

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Figure 15. CORE_VCC_S3 and UNCORE_VCC_S3 SoC Loadline

VID
V_TOB_Imin
Load
Line +Ripple
+AVP Tolerance

V_TOB_Imax
-AVP Tolerance
-Ripple
Failure

Icc Max

9.3.2 Voltage Identification (VID)

The VID specifications for the SoC CORE_VCC_S and UNCORE_VNN_S are defined by
the IMVP7 Pulse Width Modulation (PWM) Specification. Table 64 specifies the voltage
level corresponding to the eight bit VID value transmitted over serial VID (SVID)
interface per IMVP7 specification. A ‘1’ in this table refers to a high voltage level and a
‘0’ refers to a low voltage level. If the voltage regulation circuit cannot supply the
voltage that is requested, the voltage regulator must disable itself. The SVID signals
are CMOS push/pull drivers. Refer to Table 96 for the DC specifications for these
signals. The VID codes will change due to performance, temperature and/or current
load changes in order to minimize the power of the part. A voltage range is provided in
Table 63. The specifications are set so that one voltage regulator can operate with all
supported frequencies.

Individual SoC VID values may be set during manufacturing so that two devices at the
same core frequency may have different default VID settings. This is shown in the VID
range values in Table 63. The SoC provides the ability to operate while transitioning to
an adjacent VID and its associated voltage. This will represent a DC shift in the
loadline.

Note: Table below lists all voltages possible per IMVP7 specification. Not all voltages are valid
on actual SKUs.

Table 64. IMVP7.0 Voltage Identification Reference (Sheet 1 of 8)

Hex Hex
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VCC (V)
bit 1 bit 0

0 0 0 0 0 0 0 0 0 0 0.00000
0 0 0 0 0 0 0 1 0 1 0.25000
0 0 0 0 0 0 1 0 0 2 0.25500
0 0 0 0 0 0 1 1 0 3 0.26000

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Table 64. IMVP7.0 Voltage Identification Reference (Sheet 2 of 8)

Hex Hex
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VCC (V)
bit 1 bit 0

0 0 0 0 0 1 0 0 0 4 0.26500
0 0 0 0 0 1 0 1 0 5 0.27000
0 0 0 0 0 1 1 0 0 6 0.27500
0 0 0 0 0 1 1 1 0 7 0.28000
0 0 0 0 1 0 0 0 0 8 0.28500
0 0 0 0 1 0 0 1 0 9 0.29000
0 0 0 0 1 0 1 0 0 A 0.29500
0 0 0 0 1 0 1 1 0 B 0.30000
0 0 0 0 1 1 0 0 0 C 0.30500
0 0 0 0 1 1 0 1 0 D 0.31000
0 0 0 0 1 1 1 0 0 E 0.31500
0 0 0 0 1 1 1 1 0 F 0.32000
0 0 0 1 0 0 0 0 1 0 0.32500
0 0 0 1 0 0 0 1 1 1 0.33000
0 0 0 1 0 0 1 0 1 2 0.33500
0 0 0 1 0 0 1 1 1 3 0.34000
0 0 0 1 0 1 0 0 1 4 0.34500
0 0 0 1 0 1 0 1 1 5 0.35000
0 0 0 1 0 1 1 0 1 6 0.35500
0 0 0 1 0 1 1 1 1 7 0.36000
0 0 0 1 1 0 0 0 1 8 0.36500
0 0 0 1 1 0 0 1 1 9 0.37000
0 0 0 1 1 0 1 0 1 A 0.37500
0 0 0 1 1 0 1 1 1 B 0.38000
0 0 0 1 1 1 0 0 1 C 0.38500
0 0 0 1 1 1 0 1 1 D 0.39000
0 0 0 1 1 1 1 0 1 E 0.39500
0 0 0 1 1 1 1 1 1 F 0.40000
0 0 1 0 0 0 0 0 2 0 0.40500
0 0 1 0 0 0 0 1 2 1 0.41000
0 0 1 0 0 0 1 0 2 2 0.41500
0 0 1 0 0 0 1 1 2 3 0.42000
0 0 1 0 0 1 0 0 2 4 0.42500
0 0 1 0 0 1 0 1 2 5 0.43000
0 0 1 0 0 1 1 0 2 6 0.43500
0 0 1 0 0 1 1 1 2 7 0.44000

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Table 64. IMVP7.0 Voltage Identification Reference (Sheet 3 of 8)

Hex Hex
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VCC (V)
bit 1 bit 0

0 0 1 0 1 0 0 0 2 8 0.44500
0 0 1 0 1 0 0 1 2 9 0.45000
0 0 1 0 1 0 1 0 2 A 0.45500
0 0 1 0 1 0 1 1 2 B 0.46000
0 0 1 0 1 1 0 0 2 C 0.46500
0 0 1 0 1 1 0 1 2 D 0.47000
0 0 1 0 1 1 1 0 2 E 0.47500
0 0 1 0 1 1 1 1 2 F 0.48000
0 0 1 1 0 0 0 0 3 0 0.48500
0 0 1 1 0 0 0 1 3 1 0.49000
0 0 1 1 0 0 1 0 3 2 0.49500
0 0 1 1 0 0 1 1 3 3 0.50000
0 0 1 1 0 1 0 0 3 4 0.50500
0 0 1 1 0 1 0 1 3 5 0.51000
0 0 1 1 0 1 1 0 3 6 0.51500
0 0 1 1 0 1 1 1 3 7 0.52000
0 0 1 1 1 0 0 0 3 8 0.52500
0 0 1 1 1 0 0 1 3 9 0.53000
0 0 1 1 1 0 1 0 3 A 0.53500
0 0 1 1 1 0 1 1 3 B 0.54000
0 0 1 1 1 1 0 0 3 C 0.54500
0 0 1 1 1 1 0 1 3 D 0.55000
0 0 1 1 1 1 1 0 3 E 0.55500
0 0 1 1 1 1 1 1 3 F 0.56000
0 1 0 0 0 0 0 0 4 0 0.56500
0 1 0 0 0 0 0 1 4 1 0.57000
0 1 0 0 0 0 1 0 4 2 0.57500
0 1 0 0 0 0 1 1 4 3 0.58000
0 1 0 0 0 1 0 0 4 4 0.58500
0 1 0 0 0 1 0 1 4 5 0.59000
0 1 0 0 0 1 1 0 4 6 0.59500
0 1 0 0 0 1 1 1 4 7 0.60000
0 1 0 0 1 0 0 0 4 8 0.60500
0 1 0 0 1 0 0 1 4 9 0.61000
0 1 0 0 1 0 1 0 4 A 0.61500
0 1 0 0 1 0 1 1 4 B 0.62000

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Table 64. IMVP7.0 Voltage Identification Reference (Sheet 4 of 8)

Hex Hex
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VCC (V)
bit 1 bit 0

0 1 0 0 1 1 0 0 4 C 0.62500
0 1 0 0 1 1 0 1 4 D 0.63000
0 1 0 0 1 1 1 0 4 E 0.63500
0 1 0 0 1 1 1 1 4 F 0.64000
0 1 0 1 0 0 0 0 5 0 0.64500
0 1 0 1 0 0 0 1 5 1 0.65000
0 1 0 1 0 0 1 0 5 2 0.65500
0 1 0 1 0 0 1 1 5 3 0.66000
0 1 0 1 0 1 0 0 5 4 0.66500
0 1 0 1 0 1 0 1 5 5 0.67000
0 1 0 1 0 1 1 0 5 6 0.67500
0 1 0 1 0 1 1 1 5 7 0.68000
0 1 0 1 1 0 0 0 5 8 0.68500
0 1 0 1 1 0 0 1 5 9 0.69000
0 1 0 1 1 0 1 0 5 A 0.69500
0 1 0 1 1 0 1 1 5 B 0.70000
0 1 0 1 1 1 0 0 5 C 0.70500
0 1 0 1 1 1 0 1 5 D 0.71000
0 1 0 1 1 1 1 0 5 E 0.71500
0 1 0 1 1 1 1 1 5 F 0.72000
0 1 1 0 0 0 0 0 6 0 0.72500
0 1 1 0 0 0 0 1 6 1 0.73000
0 1 1 0 0 0 1 0 6 2 0.73500
0 1 1 0 0 0 1 1 6 3 0.74000
0 1 1 0 0 1 0 0 6 4 0.74500
0 1 1 0 0 1 0 1 6 5 0.75000
0 1 1 0 0 1 1 0 6 6 0.75500
0 1 1 0 0 1 1 1 6 7 0.76000
0 1 1 0 1 0 0 0 6 8 0.76500
0 1 1 0 1 0 0 1 6 9 0.77000
0 1 1 0 1 0 1 0 6 A 0.77500
0 1 1 0 1 0 1 1 6 B 0.78000
0 1 1 0 1 1 0 0 6 C 0.78500
0 1 1 0 1 1 0 1 6 D 0.79000
0 1 1 0 1 1 1 0 6 E 0.79500
0 1 1 0 1 1 1 1 6 F 0.80000

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Table 64. IMVP7.0 Voltage Identification Reference (Sheet 5 of 8)

Hex Hex
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VCC (V)
bit 1 bit 0

0 1 1 1 0 0 0 0 7 0 0.80500
0 1 1 1 0 0 0 1 7 1 0.81000
0 1 1 1 0 0 1 0 7 2 0.81500
0 1 1 1 0 0 1 1 7 3 0.82000
0 1 1 1 0 1 0 0 7 4 0.82500
0 1 1 1 0 1 0 1 7 5 0.83000
0 1 1 1 0 1 1 0 7 6 0.83500
0 1 1 1 0 1 1 1 7 7 0.84000
0 1 1 1 1 0 0 0 7 8 0.84500
0 1 1 1 1 0 0 1 7 9 0.85000
0 1 1 1 1 0 1 0 7 A 0.85500
0 1 1 1 1 0 1 1 7 B 0.86000
0 1 1 1 1 1 0 0 7 C 0.86500
0 1 1 1 1 1 0 1 7 D 0.87000
0 1 1 1 1 1 1 0 7 E 0.87500
0 1 1 1 1 1 1 1 7 F 0.88000
1 0 0 1 0 0 0 0 8 0 0.88500
1 0 0 1 0 0 0 1 8 1 0.89000
1 0 0 1 0 0 1 0 8 2 0.89500
1 0 0 0 0 0 1 1 8 3 0.90000
1 0 0 0 0 1 0 0 8 4 0.90500
1 0 0 0 0 1 0 1 8 5 0.91000
1 0 0 0 0 1 1 0 8 6 0.91500
1 0 0 0 0 1 1 1 8 7 0.92000
1 0 0 0 1 0 0 0 8 8 0.92500
1 0 0 0 1 0 0 1 8 9 0.93000
1 0 0 0 1 0 1 0 8 A 0.93500
1 0 0 0 1 0 1 1 8 B 0.94000
1 0 0 0 1 1 0 0 8 C 0.94500
1 0 0 0 1 1 0 1 8 D 0.95000
1 0 0 0 1 1 1 0 8 E 0.95500
1 0 0 0 1 1 1 1 8 F 0.96000
1 0 0 0 0 0 0 0 9 0 0.96500
1 0 0 0 0 0 0 1 9 1 0.97000
1 0 0 0 0 0 1 0 9 2 0.97500
1 0 0 1 0 0 1 1 9 3 0.98000

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Table 64. IMVP7.0 Voltage Identification Reference (Sheet 6 of 8)

Hex Hex
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VCC (V)
bit 1 bit 0

1 0 0 1 0 1 0 0 9 4 0.98500
1 0 0 1 0 1 0 1 9 5 0.99000
1 0 0 1 0 1 1 0 9 6 0.99500
1 0 0 1 0 1 1 1 9 7 1.00000
1 0 0 1 1 0 0 0 9 8 1.00500
1 0 0 1 1 0 0 1 9 9 1.01000
1 0 0 1 1 0 1 0 9 A 1.01500
1 0 0 1 1 0 1 1 9 B 1.02000
1 0 0 1 1 1 0 0 9 C 1.02500
1 0 0 1 1 1 0 1 9 D 1.03000
1 0 0 1 1 1 1 0 9 E 1.03500
1 0 0 1 1 1 1 1 9 F 1.04000
1 0 1 1 0 0 0 0 A 0 1.04500
1 0 1 1 0 0 0 1 A 1 1.05000
1 0 1 1 0 0 1 0 A 2 1.05500
1 0 1 0 0 0 1 1 A 3 1.06000
1 0 1 0 0 1 0 0 A 4 1.06500
1 0 1 0 0 1 0 1 A 5 1.07000
1 0 1 0 0 1 1 0 A 6 1.07500
1 0 1 0 0 1 1 1 A 7 1.08000
1 0 1 0 1 0 0 0 A 8 1.08500
1 0 1 0 1 0 0 1 A 9 1.09000
1 0 1 0 1 0 1 0 A A 1.09500
1 0 1 0 1 0 1 1 A B 1.10000
1 0 1 0 1 1 0 0 A C 1.10500
1 0 1 0 1 1 0 1 A D 1.11000
1 0 1 0 1 1 1 0 A E 1.11500
1 0 1 0 1 1 1 1 A F 1.12000
1 0 1 0 0 0 0 0 B 0 1.12500
1 0 1 0 0 0 0 1 B 1 1.13000
1 0 1 0 0 0 1 0 B 2 1.13500
1 0 1 1 0 0 1 1 B 3 1.14000
1 0 1 1 0 1 0 0 B 4 1.14500
1 0 1 1 0 1 0 1 B 5 1.15000
1 0 1 1 0 1 1 0 B 6 1.15500
1 0 1 1 0 1 1 1 B 7 1.16000

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Table 64. IMVP7.0 Voltage Identification Reference (Sheet 7 of 8)

Hex Hex
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VCC (V)
bit 1 bit 0

1 0 1 1 1 0 0 0 B 8 1.16500
1 0 1 1 1 0 0 1 B 9 1.17000
1 0 1 1 1 0 1 0 B A 1.17500
1 0 1 1 1 0 1 1 B B 1.18000
1 0 1 1 1 1 0 0 B C 1.18500
1 0 1 1 1 1 0 1 B D 1.19000
1 0 1 1 1 1 1 0 B E 1.19500
1 0 1 1 1 1 1 1 B F 1.20000
1 1 0 0 0 0 0 0 C 0 1.20500
1 1 0 0 0 0 0 1 C 1 1.21000
1 1 0 0 0 0 1 0 C 2 1.21500
1 1 0 0 0 0 1 1 C 3 1.22000
1 1 0 0 0 1 0 0 C 4 1.22500
1 1 0 0 0 1 0 1 C 5 1.23000
1 1 0 0 0 1 1 0 C 6 1.23500
1 1 0 0 0 1 1 1 C 7 1.24000
1 1 0 0 1 1 0 0 C 8 1.24500
1 1 0 0 1 0 0 1 C 9 1.25000
1 1 0 0 1 0 1 0 C A 1.25500
1 1 0 0 1 0 1 1 C B 1.26000
1 1 0 0 1 0 0 0 C C 1.26500
1 1 0 0 1 1 0 1 C D 1.27000
1 1 0 0 1 1 1 0 C E 1.27500
1 1 0 0 1 1 1 1 C F 1.28000
1 1 0 1 0 1 0 0 D 0 1.28500
1 1 0 1 0 1 0 1 D 1 1.29000
1 1 0 1 0 0 1 0 D 2 1.29500
1 1 0 1 0 0 1 1 D 3 1.30000
1 1 0 1 0 1 0 0 D 4 1.30500
1 1 0 1 0 1 0 1 D 5 1.31000
1 1 0 1 0 1 1 0 D 6 1.31500
1 1 0 1 0 1 1 1 D 7 1.32000
1 1 0 1 1 0 0 0 D 8 1.32500
1 1 0 1 1 0 0 1 D 9 1.33000
1 1 0 1 1 0 1 0 D A 1.33500
1 1 0 1 1 0 1 1 D B 1.34000

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Table 64. IMVP7.0 Voltage Identification Reference (Sheet 8 of 8)

Hex Hex
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VCC (V)
bit 1 bit 0

1 1 0 1 1 1 0 0 D C 1.34500
1 1 0 1 1 1 0 1 D D 1.35000
1 1 0 1 1 1 1 0 D E 1.35500
1 1 0 1 1 1 1 1 D F 1.36000
1 1 1 0 0 0 0 0 E 0 1.36500
1 1 1 0 0 0 0 1 E 1 1.37000
1 1 1 0 0 0 1 0 E 2 1.37500
1 1 1 0 0 0 1 1 E 3 1.38000
1 1 1 0 0 1 0 0 E 4 1.38500
1 1 1 0 0 1 0 1 E 5 1.39000
1 1 1 0 0 1 1 0 E 6 1.39500
1 1 1 0 0 1 1 1 E 7 1.40000
1 1 1 0 1 0 0 0 E 8 1.40500
1 1 1 0 1 0 0 1 E 9 1.41000
1 1 1 0 1 0 1 0 E A 1.41500
1 1 1 0 1 0 1 1 E B 1.42000
1 1 1 0 1 1 0 0 E C 1.42500
1 1 1 0 1 1 0 1 E D 1.43000
1 1 1 0 1 1 1 0 E E 1.43500
1 1 1 0 1 1 1 1 E F 1.44000
1 1 1 1 0 0 0 0 F 0 1.44500
1 1 1 1 0 0 0 1 F 1 1.45000
1 1 1 1 0 0 1 0 F 2 1.45500
1 1 1 1 0 0 1 1 F 3 1.46000
1 1 1 1 0 1 0 0 F 4 1.46500
1 1 1 1 0 1 0 1 F 5 1.47000
1 1 1 1 0 1 1 0 F 6 1.47500
1 1 1 1 0 1 1 1 F 7 1.48000
1 1 1 1 1 0 0 0 F 8 1.48500
1 1 1 1 1 0 0 1 F 9 1.49000
1 1 1 1 1 0 1 0 F A 1.49500
1 1 1 1 1 0 1 1 F B 1.50000
1 1 1 1 1 1 0 0 F C 1.49500
1 1 1 1 1 1 0 1 F D 1.50000
1 1 1 1 1 1 1 0 F E 1.49500
1 1 1 1 1 1 1 1 F F 1.50000

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9.4 Crystal Specifications

There are two crystal oscillators. One for RTC which maintains time and provides initial
timing reference for power sequencing. The other is for the Integrated Clock, which
covers clocking for the entire SoC.

Table 65. ILB RTC Crystal Specification

Symbol Parameter Min Typ Max Units Notes

FRTC Frequency - 32.768 - kHz 1

TPPM Crystal frequency tolerance - - +/-50 ppm 1
(see notes)
RESR ESR - - 50 kOhm 1
CX1,2 Capacitance of X1, X2 pins pF 1

NOTES:
1. These are the specifications needed to select a crystal oscillator for the RTC circuit.
2. Crystal tolerance impacts RTC time. A 10 ppm crystal is recommended for 1.7 s tolerance per day, RTC
circuit itself contributes addition 10 ppm for a total of 20 ppm in this example.

Table 66. Integrated Clock Crystal Specification

Symbol Parameter Min Typ Max Units Notes

FICLK Frequency - 25 - MHz 1

TPPM Crystal frequency tolerance & - - +/-100 ppm 1
stability
PDRIVE Crystal drive load - - 100 uW 1
RESR ESR - - 100 Ohm 1
CLOAD Crystal load capacitance 18 pF
CSHUNT Crystal shunt capacitance - - 6 pF 1
CIN/OUT Capacitance of oscillator pins pF 1

NOTES:
1. These are the specifications needed to select a crystal oscillator for the Integrated Clock circuit. Crystal
must be AT cut, fundamental, parallel resonance.

9.5 DC Specifications
Platform reference voltages are specified at DC only. VREF measurements should be
made with respect to the supply voltages specified in “Voltage and Current
Specifications”.

Note: VIH/OH Max and VIL/OL Min values are bounded by reference voltages.

See the following DC Specifications in this section:

• “Display DC Specification”

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• “PCI Express DC Specification”

• “MIPI-Camera Serial Interface (CSI) DC Specification”
• “SCC - SDIO DC Specification”
• “SCC - SD Card DC Specification”
• “SCC - eMMC 4.5 DC Specification”
• “SATA DC Specification”
• “JTAG (TAP) DC Specification”
• “DDR3L-RS Memory Controller DC Specification”
• “USB 2.0 Host DC Specification”
• “USB 3.0 DC Specification”
• “PCU - iLB - LPC DC Specification”
• “PCU - SPI (Platform Control Unit) DC Specification”
• “PCU - Power Management/Thermal (PMC) & iLB RTC DC Specification”
• “SVID DC Specification”
• “GPIO DC Specification”
• “SIO - I2C DC Specification”
• “SIO - UART DC Specification”
• “I2S (Audio) DC Specification”

Note: Care should be taken to read all notes associated with each parameter.

9.5.1 Display DC Specification

DC specifications for display interfaces:
• “Analog VGA Video DC Specification”
• “Digital Display Interface (DDI) Signals DC Specification”

9.5.1.1 Analog VGA Video DC Specification

Interface DC Specifications are referred to the VESA Video Signal Standard, version 1
revision 2.

Table 67. R,G,B/VGA DAC Display DC specification (Functional Operating Range)

Symbol Parameter Min Typ Max Units Notes

Resolution 8 bits 1
Max Luminance (full-scale) 0.665 0.700 0.770 V 1,2,4
(white video level voltage)
Min Luminance 0.0 V 1,3,4
(black video level voltage)

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Table 67. R,G,B/VGA DAC Display DC specification (Functional Operating Range)

Symbol Parameter Min Typ Max Units Notes

LSB Current 73.2 8 µA 4,5

Integral Non Linearity (INL) -1.0 +1.0 LSB 1,6
Differential Non-Linearity -1.0 +1.0 LSB 1,6
(DNL)
Video Channel-to-Channel 6 % 7
Voltage amplitude mismatch
Monotonicity Guaranteed

NOTES:
1. Measured at each R,G,B termination according to the VESA Test Procedure – Evaluation of Analog Display Graphics
Subsystems Proposal (Version 1, Draft 4, December 1, 2000).
2. Max steady-state amplitude
3. Min steady-state amplitude
4. Defined for a double 75 Ω termination
5. Set by external reference resistor value
6. INL & DNL measured and calculated according to VESA Video Signal Standards
7. Max fill-scale voltage difference among R,G,B outputs (percentage of steady-state full-scale voltage).

Table 68. VGA_DDCCLK, VGA_DDCDATA Signal DC Specification

Symbol Parameter Min Typ Max Units Notes

VREF I/O Voltage VGA_V3P3_S3

VIH Input High Voltage 2 V 1
VIL Input Low Voltage 0 0.8 V 2
VOL Output Low Voltage 0.4 V 3

Ii Input Pin Leakage -45 45 µA 4

NOTES:
1. VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high
value
2. VIL is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical low
value.
3. 3 mA sink current.
4. For VIN between 0V and VGA_V3P3_S3. Measured when driver is tri-stated.

Table 69. VGA_HSYNC and VGA_VSYNC DC Specification

Symbol Parameter Min Typ Max Units Notes

VREF I/O Voltage VGA_V3P3_S3

VOH Output High Voltage 2.4 VREF V
VOL Output Low Voltage 0 0.5 V
IOH Output High Current 8 mA
IOL Output Low Current 8 mA
Ii Input Pin Leakage -35 35 µA 1

NOTE:
1. For VIN between 0-V and VGA_V3P3_S3. Measured when driver is tri-stated.

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9.5.1.2 Digital Display Interface (DDI) Signals DC Specification

Table 70. DDI Main Transmitter DC specification

Symbol Parameter Min Typ Max Units Notes

VTX-DIFFp-p- Differential Peak-to-peak 0.34 0.4 0.46 V 1

Level0 Output Voltage Level 0
VTX-DIFFp-p- Differential Peak-to-peak 0.51 0.6 0.68 V 1
Level1 Output Voltage Level 1
VTX-DIFFp-p- Differential Peak-to-peak 0.69 0.8 0.92 V 1
Level2 Output Voltage Level 2
VTX-DIFFp-p- Differential Peak-to-peak 0.85 1.2 1.38 V 1
Level3 Output Voltage Level 3
VTX-PREEMP- No Pre-emphasis 0.0 0.0 0.0 dB 1
RATIO

3.5 dB Pre-emphasis 2.8 3.5 4.2 dB 1

6.0 dB Pre-emphasis 4.8 6.0 7.2 dB 1
9.5 dB Pre-emphasis 7.5 9.5 11.4 dB 1
VTX-DC-CM Tx DC Common Mode 0 2.0 V 1
Voltage
RLTX-DIFF Differential Return Loss at 12 dB 4
0.675GHz at Tx Package
pins
Differential Return Loss at 9 dB 4
1.35 GHz at Tx Package
pins
CTX AC Coupling Capacitor 75 200 nF 5
Voff Single Ended Standby (off), -10 10 mV 6 @ AVcc
output voltage
Vswing Single Ended output swing 400 600 mV
voltage
VOH (<=165 Single Ended high level, -10 10 mv 6 @ AVcc
MHz) output voltage
VOH(>165 Single Ended high level, -200 10 mV 6 @ AVcc
MHz) output voltage
VOL(<=165 Single Ended low level, -600 -400 mV 6 @ AVcc
MHz) output voltage
VOL(>165MH Single Ended low level, -700 -400 mV 6 @ AVcc
z) output voltage

NOTES:
1. For embedded connection, support of programmable voltage swing levels is optional.
2. Total drive current of the transmitter when it is shorted to its ground.
3. Common mode voltage is equal to Vbias_Tx voltage shown in Figure 16.
4. Straight loss line between 0.675 GHz and 1.35 GHz.
5. All DisplayPort Main Link lanes as well as AUX CH must be AC coupled. AC coupling capacitors must be
placed on the transmitter side. Placement of AC coupling capacitors on the receiver side is optional.
6. AVcc =Analog Voltage level

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Table 71. DDI AUX Channel DC Specification

Symbol Parameter Min Typ Max Units Notes

VAUX-DIFFp-p AUX Peak-to-peak Voltage 0.29 1.38 V 1

at a transmitting Device
VAUX-_TERM_R AUX CH termination DC 100 Ω
resistance
VAUX-DC-CM AUX DC Common Mode 0 2.0 V 2
Voltage
VAUX-TURN-CM AUX turn around common 0.3 V 3
mode voltage
IAUX_SHORT AUX Short Circuit Current 90 mA 4
Limit
CAUX AC Coupling Capacitor 75 200 nF 5

NOTES:
1. VAUX-DIFFp-p= 2*|VAUXP – VAUXM|
2. Common mode voltage is equal to Vbias_Tx (or Vbias_Rx) voltage.
3. Steady state common mode voltage shift between transmit and receive modes of operation.
4. Total drive current of the transmitter when it is shorted to its ground.
5. All DisplayPort Main Link lanes as well as AUX CH must be AC coupled. AC coupling capacitors must be
placed on the transmitter side. Placement of AC coupling capacitors on the receiver side is optional.

NOTES:

Table 72. DDI DDC Signal DC Specification (DDI[1:0]_DDCDATA, DDI[1:0]_DDCCLK)

Symbol Parameter Min Typ Max Units Notes

VREF I/O Voltage MIPI_V1P8_S3 V

VIH Input High Voltage 0.65*VREF V 1
VIL Input Low Voltage 0.35*VREF V 2
VOL Output Low Voltage 0.4 V 3
Ii Input Pin Leakage -30 30 µA 4

1. VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high
value
2. VIL is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical low
value.
3. 3mA sink current.
4. For VIN between 0V and CORE_VCC_S0iX. Measured when driver is tri-stated.

NOTES:

Table 73. DDI DDC Misc Signal DC Specification (DDI[1:0]_HPD, DDI[1:0]_BKLTCTL,

DDI[1:0]_VDDEN, DDI[1:0]_BKLTEN)

Symbol Parameter Min Typ Max Units Notes

VREF I/O Voltage MIPI_V1P8_S3 V

VIH Input High Voltage 0.65*VREF V 1
VIL Input Low Voltage 0 0.35*VREF V 2

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Table 73. DDI DDC Misc Signal DC Specification (DDI[1:0]_HPD, DDI[1:0]_BKLTCTL,

DDI[1:0]_VDDEN, DDI[1:0]_BKLTEN)

Symbol Parameter Min Typ Max Units Notes

Zpu Pull up Impedance 40 50 60 Ω 3

Zpd Pull down Impedance 40 50 60 Ω 3
Ii Input Pin Leakage -20 20 µA 4

1. VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high
value
2. VIL is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical low
value.
3. Measured at CORE_VCC_S0iX/2.
4. For VIN between 0V and CORE_VCC_S0iX. Measured when driver is tri-stated.

Figure 16. Definition of Differential Voltage and Differential Voltage Peak-to-Peak

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Figure 17. Definition of Pre-emphasis

9.5.2 PCI Express DC Specification

Table 74. PCI Express DC Receive Signal Characteristics

Symbol Parameter Min Typ Max Unit Notes

VRXDIFF Gen1 Differential RX Peak to Peak 175 1200 mV 1

VRXDIFF Gen2 Differential RX Peak to Peak 100 1200 mV 1

NOTE:
1. PCI Express differential peak to peak = 2*|RXp[x] – RXn[x]|

Table 75. PCI Express DC Transmit Characteristics

Symbol Parameter Min Typ Max Unit Notes

VTXDIFF Differential TX Peak to Peak 800 1200 mV 1

VTXDIFF-LP Differential TX Peak to Peak 400 1200 mV 1
(low power mode)

NOTE:
1. PCI Express differential peak to peak = 2*|TXp[x] – TXn[x]|

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Table 76. PCI Express DC Clock Request Input Signal Characteristics

Symbol Parameter Min Typ Max Unit Notes

VREF I/O Voltage UNCORE_V1P8_S3

VIL Input Low Voltage 0.3*VREF V 1
VIH Input High Voltage 0.65*VREF V 1

NOTE:
1. 3.3 V refers to UNCORE_3P3_S0 for signals in the core well. See Chapter 2, “Physical Interfaces” for signal and power well
association.

9.5.3 MIPI-Camera Serial Interface (CSI) DC Specification

Table 77. MIPI HS-RX/MIPI LP-RX Minimum, Nominal, and Maximum Voltage
Parameters

Symbol Parameter Min. Typ. Max. Unit Notes

ILEAK Pin Leakage current -10 – 10 µA

MIPI-CSI HS-RX Mode

VCMRX(DC) Common-mode voltage HS receive 70 – 330 mV

mode
VIDTH Differential input high threshold – – 70 mV
VIDTL Differential input low threshold -70 – – mV
VIHHS Single-ended input high voltage – – 460 mV
VILHS Single-ended input low voltage -40 – – mV
VTERM-EN Single-ended threshold for HS – – 450 mV
termination enable
ZID Differential input impedance 80 100 125 Ω

MIPI-CSI LP-RX Mode

VIH Logic 1 input voltage 880 – – mV

VIL Logic 0 input voltage, not in ULP state – – 550 mV
VIL-ULPS Logic 0 input voltage, ULP state – – 300 mV
VHYST Input hysteresis 25 – – mV

9.5.4 SCC - SDIO DC Specification

Table 78 provides the SDIO DC Specification, for all other DC Specifications not listed in
Table 78, please refer to Table 97, “GPIO 1.8V Core Well Signal Group DC Specification
(GPIO_S0_SC[101:0]).

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Table 78. SDIO DC Specification

Symbol Parameter Min. Typ. Max. Unit Notes

VOH Output High Voltage 1.4 – – V Measured at

IOH maximum.
IOH/IOL Current at VoL/Voh -2 – – mA

9.5.5 SCC - SD Card DC Specification

Table 79 provides the SD Card DC Specification, for all other DC Specifications not
listed in Table 79, please refer to Table 97, “GPIO 1.8V Core Well Signal Group DC
Specification (GPIO_S0_SC[101:0]).

Table 79. SD Card DC Specification

Symbol Parameter Min. Max. Unit

VREF I/O Voltage SD3_V1P8V3P3_S3

Output High Voltage
VOH 0.75*VREF – V

VOL Output Low Voltage - 0.125*VREF V

Input High Voltage

VIH (3.3) 0.625*VREF - V
(3.3 V)
Input Low Voltage
VIL (3.3) - 0.25*VREF V
(3.3 V)
Peak Voltage on All
VPEAK (3.3) -0.3 VREF+0.3 V
lines
Input High Voltage
VIH (1.8) 1.28 - V
(1.8 V)
Input Low Voltage
VIL (1.8) - 0.58 V
(1.8 V)
Peak Voltage on All
VPEAK (1.8) -0.3 VREF+0.3 V
lines

IOH/IOL Current at VoL/Voh -45 40 µA

Vhysteresis Input Hysteresis None V

CLOAD Input Load Capacitance 4 9 pF

9.5.6 SCC - eMMC 4.5 DC Specification

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Table 80. eMMC 4.5 Signal DC Electrical Specifications

Symbol Parameter Min Max Units

VREF I/O Voltage UNCORE_V1P8_S3

VOH Output HIGH voltage VREF - 0.45 - V
VOl Output LOW voltage - 0.45 V
VIH Input HIGH voltage 0.65 * VREF VREF + 0.3 V
VIL Input LOW voltage -0.3 0.35 * VREF V
CL Bus Signal Line - 30 pF
capacitance
ILI Input Leakage Current -2 2 µA
IL0 Output Leakage Current -2 2 µA

Figure 18. eMMC DC Bus signal level

9.5.7 JTAG (TAP) DC Specification

Table 81. TAP Signal Group DC Specification (TAP_TCK, TAP_TRSRT#, TAP_TMS,

TAP_TDI) (Sheet 1 of 2)

Symbol Parameter Min Typ Max Units Notes

VREF I/O Voltage PMC_V1P8_G3

VIH Input High Voltage 0.8*VREF V 1
VIL Input Low Voltage 0.4*VREF V 2
Zpu Pull up Impedance 60 Ω 3
Zpd Pull down Impedance 60 Ω 3
Rwpu Weak Pull Impedance 1 4 kΩ 3

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Table 81. TAP Signal Group DC Specification (TAP_TCK, TAP_TRSRT#, TAP_TMS,

TAP_TDI) (Sheet 2 of 2)

Symbol Parameter Min Typ Max Units Notes

Rwpd Weak Pull Down 1 4 kΩ 3

Impedance
Rwpu-40K Weak Pull Up Impedance 20 70 kΩ 4
40K
Rwpd-40K Weak Pull Down 20 70 kΩ 4
Impedance 40K

NOTES:
1. VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high
value
2. VIL is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical low
value.
3. Measured at PMC_V1P8_G3/2.
4. Rwpu_40k and Rwpd_40k are only used for TAP_TRST#

Table 82. TAP Signal Group DC Specification (TAP_TDO)

Symbol Parameter Min Typ Max Units Notes

VREF I/O Voltage PMC_V1P8_G3

VIH Input High Voltage 0.8*VREF V 1
VIL Input Low Voltage 0.5*VREF V 2
Zpd Pull down Impedance 30 Ω 3
Rwpu Weak Pull Impedance 1 4 kΩ 3
Rwpd Weak Pull Down 1 4 kΩ 3
Impedance

NOTES:
1. VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high
value
2. VIL is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical low
value.
3. Measured at PMC_V1P8_G3/2.

Table 83. TAP Signal Group DC Specification (TAP_PRDY#, TAP_PREQ#)

Symbol Parameter Min Typ Max Units Notes

VREF I/O Voltage PMC_V1P8_G3

VIH Input High Voltage 0.64*VREF V 1
VIL Input Low Voltage 0.4*VREF V 2
Zpd Pull down Impedance 30 Ω 3
Rwpu Weak Pull Impedance 1 4 kΩ 3

NOTES:
1. VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value
2. VIL is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical low value.
3. Measured at PMC_V1P8_G3/2.

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9.5.8 DDR3L-RS Memory Controller DC Specification

Table 84. DDR3L-RS Signal Group DC Specifications

Symbol Parameter Min Typ Max Units Notes

VIL Input Low DRAM_VREF V 1

Voltage - 200mV
VIH Input High DRAM_VREF V 2, 3
Voltage + 200mV
VOL Output Low (DRAM_VDD_S4 / 2)* (RON / 3,4
Voltage (RON+RVTT_TERM))
VOH Output High DRAM_VDD_S4 - V 3,4
Voltage ((DRAM_VDD_S4 /2)*
(RON/(RON+RVTT_TERM))
IIL Input Leakage 5 µA For all
Current DRAM
Signals
RON DDR3L-RS 26 40 Ω 5
Clock Buffer
strength
CIO DQ/DQS/DQS# 3.0 pF
DDR3L-RS IO
Pin Capacitance

NOTES:
1. VIL is defined as the maximum voltage level at the receiving agent that will be received as a logical low value. DRAM_VREF
is normally DRAM_VDD_S4/2
2. VIH is defined as the minimum voltage level at the receiving agent that will be received as a logical high value.
DRAM_VREF is normally DRAM_VDD_S4/2
3. VIH and VOH may experience excursions above DRAM_VDD_S4. However, input signal drivers must comply with the signal
quality specifications.
4. RON is DRAM driver resistance whereas RTT_TERM is DRAM ODT resistance which is controlled by DRAM.
5. DDR3L-1333 CLK buffer Ron is 26ohm and SR target is 4V/ns; DQ-DQS buffer Ron is 30ohms and SR target is 4V/ns;
CMD/CTL buffer Ron is 20ohms and SR target is 1.8V/ns.

9.5.9 Intel® HD Audio DC Specification

Table 85. HDA Signal Group DC Specifications

Symbol Parameter Condition Min Max Unit Notes

VCCHDA HDA Supply Voltage HDA_LPE_V1P5V1P8_S3

VIH_HDA Input High Voltage 0.7*VCCHDA V
VIL_HDA Input Low Voltage 0.3*VCCHDA V
VOH_HDA Output High Voltage Iout = - 0.9*VCCHDA V
500μA
VOL_HDA Output Low Voltage Iout = 0.1*VCCHDA V
1500μA

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Table 85. HDA Signal Group DC Specifications

Symbol Parameter Condition Min Max Unit Notes

IIL_HDA Input Leakage Current 0<Vin<VCC ±175 μA 1

HDA

CIN_HDA Input Pin Capacitance 7.5 pF

LPIN_HDA Pin Inductance 20 nH 2

NOTES:
1. For HDA_SDI[x] buffers (or in general any bidirectional buffer with tri-state output), input leakage
current also include hi-Z output leakage.
2. This is a recommendation, not an absolute requirement. The actual value should be provided with the
component data sheet.

9.5.10 USB 2.0 Host DC Specification

Symbol Parameter Min Typ Max Units Notes

Supply Voltage:

VBUS High-power Port 4.75 5.25 V 2

VBUS Low-power Port

Supply Current:

ICCPRT High-power Hub Port (out) 500 mA

ICCUPT Low-power Hub Port (out) 100 mA
ICCHPF High-power Function (in) 500 mA
ICCLPF Low-power Function (in) 100 mA
ICCINIT Unconfigured Function/Hub (in) 100 mA
ICCSH Suspended High-power Device 2.5 mA 15
ICCSL Suspended Low-power Device 500 µA

Input Levels for Low-/full-speed:

VIH High (driven) 2.0 V 4

VIHZ High (floating) 2.7 3.6 V 4
VIL Low 0.8 V 4

|(D+)-(D-
VDI Differential Input Sensitivity 0.2 V )|;Figure;
Note 4

Includes
VDI range;
VCM Differential Common Mode Range 0.8 2.5 V
Figure; Note
4
Input Levels for High-speed:

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Symbol Parameter Min Typ Max Units Notes

VHSSQ High-speed squelch detection 100 150 mV

threshold (differential signal
amplitude)
VHSDSC High speed disconnect detection 525 625 mV
threshold (differential signal
amplitude)
High-speed differential input
signaling levels
VHSCM High-speed data signaling common -50 500 mV
mode voltage range (guideline for
receiver)

Output Levels for Low-/full-speed:

VOL Low 0.0 0.3 V 4,5

VOH High (Driven) 2.8 3.6 V 4,6
VOSE1 SE1 0.8 V
VCRS Output Signal Crossover 1.3 2.0 V 10
Voltage

Output Levels for High-speed:

VHSOI High-speed idle level -10 10 mV

VHSOH High-speed data signaling high 360 440 mV
VHSOL High-speed data signaling low -10 10 mV
VCHIRPJ Chirp J level (differential voltage) 700 1100 mV

VCHIRPK Chirp K level (differential voltage) -900 -500 mV

Decoupling Capacitance:

CHPB Downstream Facing Port Bypass 120 µF

Capacitance (per hub)
CRPB Upstream Facing Port Bypass 1.0 10.0 µF 9
Capacitance

Input Capacitance for Low-/full-speed:

CIND Downstream Facing Port 150 pF 2

CINUB Upstream Facing Port (w/o cable) 100 pF 3

CEDGE Transceiver edge rate control 75 pF

capacitance
Input Impedance for High-speed:

TDR spec for high-speed termination

Terminations:

RPU Bus Pull-up Resistor on Upstream 1.425 1.575 kΩ 1.5 kΩ ±5%

Facing Port

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Symbol Parameter Min Typ Max Units Notes

RPD Bus Pull-down Resistor on 14.25 15.75 kΩ 1.5 kΩ ±5%

Downstream Facing Port
ZINP Input impedance exclusive of pull- 300 kΩ
up/pull-down (for low-/full speed)
VTERM Termination voltage for upstream 3.0 3.6 V
facing port pull-up (RPU)
Terminations in High-speed:

VHSTER Termination voltage in high speed -10 10 mV

M

NOTES:
1. Measured at A plug.
2. Measured at A receptacle.
3. Measured at B receptacle.
4. Measured at A or B connector.
5. Measured with RL of 1.425 kΩ to 3.6 V.
6. Measured with RL of 14.25 kΩ to GND.
7. Timing difference between the differential data signals.
8. Measured at crossover point of differential data signals.
9. The maximum load specification is the maximum effective capacitive load allowed that meets the target VBUS drop of 330
mV.
10. Excluding the first transition from the Idle state.
11. The two transitions should be a (nominal) bit time apart.
12. For both transitions of differential signaling.
13. Must accept as valid EOP.
14. Single-ended capacitance of D+ or D- is the capacitance of D+/D- to all other conductors and, if present, shield in the
cable. That is, to measure the single-ended capacitance of D+, short D-, VBUS, GND, and the shield line together and
measure the capacitance of D+ to the other conductors.
15. For high power devices (non-hubs) when enabled for remote wakeup.

9.5.11 USB 3.0 DC Specification

Symbol Parameter Min Typ Max Units Notes

UI Unit Interval 199.94 200.06 ps 1

VTX-DIFF-PP Differential peak-peak 0.9 1 1.05 V
Tx voltage swing
VTX-DIFF-PP- Low-Power Differential 0.4 1.2 V 2
LOW peak-peak Tx voltage
swing
VTX-DE-RATIO Tx De-Emphasis 3.45 3.5 3.65 dB
RTX-DIFF-DC DC differential 88 92 Ω
impedance
VTX-RCV- The amount of voltage 0.6 V 3
DETECT change allowed during
Receiver Detection
CAC-COUPLING AC Coupling Capacitor 75 200 nF 4
tCDR_SLEW_M Maximum slew rate 10 ms/s
AX

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NOTES:
1. The specified UI is equivalent to a tolerance of 300ppm for each device. Period does not account for SSC
induced variations.
2. There is no de-emphasis requirement in this mode. De-emphasis is implementation specific for this
mode.
3. Detect voltage transition should be an increase in voltage on the pin looking at the detect signal to
avoid a high impedance requirement when an “off” receiver's input goes below output.
4. All transmitters shall be AC coupled. The AC coupling is required either within the media or within the
transmitting component itself.

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9.5.12 SATA DC Specification

Table 86. SATA TX/RX Signal Group DC Specifications

Symbol Parameter Min Max Unit Notes

VIMIN_Gen1i Minimum Input Voltage for 1.5 Gb/s 325 - mVdiffp-p 1

VIMAX_Gen1i Maximum Input Voltage for 1.5 Gb/s - 600 mVdiffp-p 1
VIMIN_Gen2i Minimum Input Voltage for 3 Gb/s 275 - mVdiffp-p 2
VIMAX_Gen2i Maximum Input Voltage for 3 Gb/s - 750 mVdiffp-p 2
VOMIN_Gen1i,m Minimum Output Voltage for 1.5 Gb/s 400 - mVdiffp-p 3
VOMAX_Gen1i,m Maximum Output Voltage for 1.5 Gb/s - 600 mVdiffp-p 3
VOMIN_Gen2i,m Minimum Output Voltage for 3 Gb/s 400 - mVdiffp-p 3
VOMAX_Gen2i,m Maximum Output Voltage for 3 Gb/s - 700 mVdiffp-p 3

1. Applicable only when SATA port signaling rate is 1.5 Gb/s: SATA Vdiff, rx is measured at the SATA
connector on the receiver side (generally, the motherboard connector), where
SATA mVdiff p-p = 2*|SATA_RXP[x] – SATA_RXN[x]|
2. Applicable only when SATA port signaling rate is 3 Gb/s: SATA Vdiff, rx is measured at the SATA
connector on the receiver side (generally, the motherboard connector), where
SATA mVdiff p-p = 2*|SATA_RXP[x] – SATA_RXN[x]|
3. SATA Vdiff, tx is measured at the SATA connector on the transmit side (generally, the motherboard
connector), where SATA mVdiff p-p = 2*|SATA_TXP[x] – SATA_TXN[x]|

For SATA_GP[x], SATA_DEVSLP[x] and SATA_LED#, Please refer to the GPIO Buffer
(1.8V) DC Specification in section “GPIO DC Specification”.

9.5.13 PCU - SMBUS DC Specification

For SMBUS, Please refer to the GPIO Buffer (1.8V) DC Specification in section “GPIO DC
Specification”.

9.5.14 PCU - iLB - LPC DC Specification

Table 87. LPC Signal Group DC Specification (LPC_V1P8V3P3_S = 1.8V

(ILB_LPC_AD][3:0], ILB_LPC_FRAME#, ILB_LPC_SERIRQ,
ILB_LPC_CLKRUN#))

Symbol Parameter Min Typ Max Units Notes

VIH Input High Voltage 1.27 1.8 1.8 +0.1 V

VIL Input Low Voltage -0.1 0 0.58 V
VOH Output High Voltage 0.9 x 1.8 V
VOL Output Low Voltage 0.1 x 1.8 V
IOH Output High Current 1.5 mA

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Table 87. LPC Signal Group DC Specification (LPC_V1P8V3P3_S = 1.8V

(ILB_LPC_AD][3:0], ILB_LPC_FRAME#, ILB_LPC_SERIRQ,
ILB_LPC_CLKRUN#))

Symbol Parameter Min Typ Max Units Notes

IOL Output Low Current -0.5 mA

ILEAK Input Leakage 30 µA
Current
CIN Input Capacitance 1 9 pF

Table 88. LPC Signal Group DC Specification LPC_V1P8V3P3_S = 3.3V

(ILB_LPC_AD[3:0], ILB_LPC_FRAME#, ILB_LPC_CLKRUN#)

Symbol Parameter Min Typ Max Units Notes

VIH Input High Voltage 0.5 x 3.3+ 3.3 3.3 +0.1 V 1

0.7
VIL Input Low Voltage -0.1 0 0.5 x 3.3 - V 2
0.7
VOH Output High Voltage 0.9 x 3.3 V 3
VOL Output Low Voltage 0.1 x 3.3 V 3
IOH Output High Current 1.5 mA 3
IOL Output Low Current -0.5 mA 3
ILEAK Input Leakage Current 30 µA
CIN Input Capacitance 1 9 pF

NOTES:
1. VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high
value, Applies to ILB_LPC_AD[3:0], ILB_LPC_CLKRUN#
2. VIL is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical low
value. Applies to ILB_LPC_AD[3:0], ILB_LPC_CLKRUN#
3. VOH is tested with Iout=500uA, VOL is tested with Iout=1500uA
4. Applies to ILB_LPC_AD[3:0],ILB_LPC_CLKRUN# and ILB_LPC_FRAME#
5. ILB_LPC_SERIRQ is always a 1.8V I/O irrespective of the value of LPC_V1P8V3P3_S.

9.5.15 PCU - SPI (Platform Control Unit) DC Specification

Table 89. SPI Signal Group DC Specification (PCU_SPI_MISO, PCU_SPI_CS[1:0]#,

PCU_SPI_MOSI, PCU_SPI_CLK)

Symbol Parameter Min Typ Max Units Notes

VREF I/O Voltage PCU_1P8_G3 V 3

VIH Input High Voltage 0.5 *VREF VREF + 0.5 V 2

VIL Input Low Voltage -0.5 0.3 * VREF V 2

VOH Output High Voltage 0.9 * VREF 1.8V V 1
VOL Output Low Voltage 0.1 * VREF V 1

IOH Output High Current 1.5 mA 1

IOL Output Low Current -0.5 mA 1

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NOTES:
1. Applies to PCU_SPI_CS[1:0], PCU_SPI_CLK, PCU_SPI_MOSI
2. Applies to PCU_SPI_MISO and PCU_SPI_MOSI
3. The I/O buffer supply voltage is measured at the SoC package pins. The tolerances shown are inclusive
of all noise from DC up to 20 MHz. In testing, the voltage rails should be measured with a bandwidth
limited oscilloscope that has a rolloff of 3 dB/decade above 20 MHz.

9.5.16 PCU - Power Management/Thermal (PMC) & iLB RTC DC

Specification

Table 90. Power Management 1.8V Suspend Well Signal Group DC Specification

Symbol Parameter Min Typ Max Units Notes

VREF I/O Voltage PCU_1P8_G3 V

VIH Input High Voltage 0.8*VREF V 1
VIL Input Low Voltage 0.5*VREF V 2
VOH Output High Voltage 0.9*VREF VREF V 1
VOL Output Low Voltage 0.1*VREF V 1

NOTES:
1. The data in this table apply to signals - PMC_ACPRESENT, PMC_BATLOW#, PMC_PLTRST#,
PMC_PWRBTN#, PMC_SLP_S4#, PMC_SUS_STAT#, PMC_SUSCLK[3:0], PMC_SUSPWRDNACK
2. VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high
value
3. VIL is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical low
value.

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Table 91. PMC_RSTBTN# 1.8V Core Well Signal Group DC Specification

Symbol Parameter Min Typ Max Units Notes

VREF I/O Voltage UNCORE_V1P8_S3 V

VIH Input High Voltage 0.8* VREF V 1
VIL Input Low Voltage 0.5* VREF V 2

NOTES:
1. VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high
value
2. VIL is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical low
value.

Table 92. Power Management & RTC Well Signal Group DC Specification
(PMC_RSMRST#, PMC_CORE_PWROK, ILB_RTC_RST#)

Symbol Parameter Min Typ Max Units Notes

VREF I/O Voltage RTC_VCC

VIH Input High Voltage 2.0 - - V 1
VIL Input Low Voltage - - 0.78 V 2

NOTES:
1. VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high
value
2. VIL is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical low
value.

Table 93. iLB RTC Well DC Specification (ILB_RTC_TEST#)

Symbol Parameter Min Typ Max Units Notes

VIH Input High Voltage 2.3 - - V 1

VIL Input Low Voltage - - 0.78 V 1

NOTES:
1. VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high
value
2. VIL is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical low
value.

Table 94. ILB RTC Oscillator Optional DC Specification (ILB_RTC_X1)

Symbol Parameter Min Typ Max Units Notes

VIH Input High Voltage 0.65 0.8 1.2 V 1

VIL Input Low Voltage 0.25 V 1

NOTES:
1. ILB_RTC_X1 DC specification is only used for applications with an active external clock source instead
of a crystal. When a crystal is used (typical case) between ILB_RTC_X2 and ILB_RTC_X1, this spec is
not used.

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Table 95. PROCHOT# Signal Group DC Specification

Symbol Parameter Min Typ Max Units Notes

VREF I/O Voltage CORE_V1P0_S3

VIH Input High Voltage 0.8*VREF VREF V 1
VIL Input Low Voltage 0.4*VREF V 2
VOH Output High Voltage 0.9*VREF VREF V
VOL Output Low Voltage 0.1*VREF V

NOTES:
1. VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value
2. VIL is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical low value.

9.5.17 SVID DC Specification

Table 96. SVID Signal Group DC Specification (SVID_DATA, SVID_CLK, SVID_ALERT#)

Symbol Parameter Min Typ Max Units Notes

VREF I/O Voltage SVID_V1P0_S3

VIH Input High Voltage 0.65*VREF V 1
VIL Input Low Voltage 0.44*VREF V 1
VOH Output High Voltage V 1
VOL Output Low Voltage 0.1*VREF V 4
VHYS Hysteresis Voltage 0.05 V
RON BUffer on Resistance 10 20 Ω 2
IL Leakage Current -100 100 µA 3
CPAD Pad Capacitance 4.0 pF 4
VPIN Pin Capacitance 5.0 pF

NOTES:
1. SVID_V1P0_S3 refers to instantaneous voltage VSS_SENSE
2. Measured at 0.31 * SVID_V1P0_S3
3. VIN between 0V and SVID_V1P0_S3
4. CPAD includes die capacitance only. No package parasitic included.

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Figure 19. Definition of VHYS in Table 169

9.5.18 GPIO DC Specification

GPIO Buffer is used across various interfaces on the SoC such as, GPIOs, I2C, I2S, SPI,
SDIO, SVID, UART, JTAG and ULPI.

Table 97. GPIO 1.8V Core Well Signal Group DC Specification (GPIO_S0_SC[101:0])

Symbol Parameter Min Typ Max Units Notes

VREF I/O Voltage UNCORE_V1P8_S3

VIH Input High Voltage 0.65*VREF V
VIL Input Low Voltage 0.35 * VREF V
VOH Output High Voltage VREF - 0.45 V
VOL Output Low Voltage 0.45 V
VHys Input Hysteresis 0.1 V
IL Leakage Current 5 µA
CLOAD Load Capacitance 2 75 pF

Table 98. GPIO 1.8V Suspend Well Signal Group DC Specification (GPIO_S5[43:0])

Symbol Parameter Min Typ Max Units Notes

VREF I/O Voltage PMC_V1P8_G3 V

VIH Input High Voltage 0.65*VREF V
VIL Input Low Voltage 0.35*VREF V
VOH Output High Voltage VREF - 0.45 V
VOL Output Low Voltage 0.45 V
VHys Input Hysteresis 0.1 V
IL Leakage Current 5 µA
CLOAD Load Capacitance 2 75 pF

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9.5.19 SIO - I2C DC Specification

Table 99. I2C Signal Electrical Specifications

Symbol Parameter Min Typ Max Units Notes

VREF I/O Voltage UNCORE_V1P8_S3 V

VIH Input High Voltage 0.7 * VREF V
VIL Input Low Voltage 0.3 * VREF V
VOL Output Low Voltage 0.2 * VREF V
VHys Input Hysteresis 0.1 V
CPIN Pin Capacitance 2 5 pF

9.5.20 SIO - UART DC Specification

Please refer to the GPIO Buffer (1.8V) DC Specification, mentioned Section 9.5.18,
“GPIO DC Specification”

9.5.21 I2S (Audio) DC Specification

Please refer to the GPIO Buffer (1.8V) DC Specification, mentioned Section 9.5.18,
“GPIO DC Specification”

9.6 AC Specifications
The timings specified in this section are defined at the SoC pads. Therefore, proper
simulation of the signals is the only means to verify proper timing and signal quality.

See Chapter 2, “Physical Interfaces” for signal definitions and Chapter 10, “Ballout and
Package Information” for the ball map. Generic timing diagrams can be found in
“General AC Timing Diagrams”.

The timings specified in this section should be used in conjunction with the SoC signal
integrity models provided by Intel.

See the following DC Specifications in this section:

• “Integrated Clock 25 MHz Crystal AC Specification”
• “Platform Clocks AC Specification”
• “SVID AC Specification”
• “DDR3L Memory Controller AC Specification”
• “Display AC Specifications”
• “MIPI-Camera Serial Interface (CSI) AC Specification”
• “SCC - SD Card AC Specification”
• “SSC - SDIO AC specification”

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• “SCC - eMMC 4.5 AC Specification”

• “SATA AC Specification”
• “USB 3.0 AC Specification”
• “ULPI USB 2.0 Device AC Specification”
• “Intel® HD Audio AC Specification”
• “I2S (Audio) AC Specification”
• “PCI Express* AC Specification”
• “PCU - PMC - Suspended Clock AC Specification”
• “PCU - SPI AC Specification”
• “PCU - iLB - LPC AC Specification”
• “SIO - I2C AC Specifications”
• “SIO - UART AC Specification”
• “JTAG AC Specification”

Note: Care should be taken to read all notes associated with a particular timing parameter.

9.6.1 Integrated Clock 25 MHz Crystal AC Specification

See“Crystal Specifications” for crystal selection.

Table 100. Crystal Clock Timings

Symbol Parameter Min Max Units Notes

TOSC Period 38.84 40.18 ns

THI High Time 16.77 21.78 ns
TLO Low Time 1.37 21.58 ns
Duty Cycle 45 55 %
Rising Edge Rate 1 4 V/ns 1
Falling Edge Rate 1 4 V/ns 1

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Note: 1. Edge rates in a system as measured from 0.8 V to 2.0 V.

Figure 20. Crystal Clock Timing

9.6.2 Platform Clocks AC Specification

Table 101. 19.2 MHz Platform Clock AC Specification

Symbol Parameter Min. Typ Max. Unit Notes

FPLT Frequency 19.2 MHz

TDC Duty Cycle 45 55 %
TRISE/FALL Minimum and Maximum Rise/Fall 5 20 ns
Time
VSWING Voltage Swing 1.8 V
TPEAKJIT Peak Jitter (c-c) -300 300 ps
TPERJIT Period Jitter 550 ps

Table 102. 25 MHz Platform Clock AC Specification

Symbol Parameter Min. Typ Max. Unit Notes

FPLT Frequency 25 MHz

TDC Duty Cycle 45 55 %
TRISE/FALL Minimum and Maximum Rise/Fall 5 20 ns
Time
VSWING Voltage Swing 1.8 V
TPEAKJIT Peak Jitter (c-c) -300 300 ps
TPERJIT Period Jitter 500 ps

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9.6.3 SVID AC Specification

Table 103. SVID AC Specification

Symbol Parameter Min. Typ Max. Unit Figure Notes

FSVID SVID_CLK Frequency 25 MHz 21

TDC SVID_CLK Duty 45 55 %
Cycle
TS_D SVID_DATA Input -2 ns 21
Setup Time
TH_D SVID_DATA Input 9 ns 21
Hold Time
TCO_D Falling edge 0 5 ns 21
SVID_CLK to
SVID_DATA Output
TRISE/ Minimum and 0 5 ns 1, 2
FALL Maximum Rise/Fall
Time

NOTES:
1. Based on trace length of 0.2–4 inches, total maximum far end capacitance of 5 pF and board impedance
of 25–75 Ω.
2. Measured from 30–70%

Figure 21. SVID Timing Diagram

TDC TDC

SVID_CLK 0.5*VDD 0.5*VDD

TSVID

TCO_D Min TCO_D Max

SVID_DATA 0.5*VDD
Output (WRITE)

TS-D TH-D

SVID_DATA
0.5*VDD
Input (READ)

9.6.4 DDR3L Memory Controller AC Specification

Note: The contents of this section are only valid for DRAM_VDD_S4 = 1.35V

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Table 104. DDR3L Interface Timing Specification (Sheet 1 of 2)

Symbol Parameter Min Max Unit Figure Notes

DDR3L Electrical Characteristic and AC timings at 1066 MT/s

TSLR_D DQ, DQSP, DQSN Input Slew Rate 3 5.5 V/ns

System Memory Clock Timings

TCK(AVG) Average CK Period 1.875 ns

TCH Average CK High Time 0.45 tCKAV
G
TCL Average CK Low Time 0.45 tCKAV
G
TSKEW Skew between any System Memory 30 ps
Differential Clock Pair (CKP/CKN)

System Memory Command Signal Timings

TCMD Total CMD Buffer window available for 1380 ps 1

(tCMDVB+tCMDVA) command buffers (RAS#, CAS#,
WE#, BS[2:0], MA)

System Memory Control Signal Timings

TCTL Total Control buffer Window available 1400 ps 2

(tCTLVB + tCTLVA) for Control buffers (CS#, CKE)

System Memory Data and Strobe Signal Timings

TDVB+TVDA Data, DQ and DM timing window 645 ps 3

available at the interface output for
write commands. tDVB is data
available before strobe and tDVA is
data available after corresponding
slope.
TSU + THD Data, DQ Input Setup Plus Hold Time 310 ps 4
requirement for successful Read
operation. These Setup and Hold
numbers are measured w.r.t.
corresponding strobe or Falling Edge
TDQSS Strobe to rising clock edge during -120 120 ps
write.
TWPRE DQSP/N Preamble duration (one 0.9 tCKAV
dummy cycle) G
TWPST DQSP/N Postamble Duration 0.4 tCKAV
G

DDR3L Electrical Characteristic and AC timings at 1333 MT/s. DRAM_VDD_S4 = 1.35 V

TSLR_D DQ, DQSP, DQSN Input Slew Rate 3 5.5 V/ns

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Table 104. DDR3L Interface Timing Specification (Sheet 2 of 2)

Symbol Parameter Min Max Unit Figure Notes

System Memory Clock Timings

TCK(AVG) Average CK Period 1.5 ns

TCH Average CK High Time 0.45 tCKAV
G
TCL Average CK Low Time 0.45 tCKAV
G
TSKEW Skew between any System Memory 30 ps
Differential Clock Pair (CKP/CKN)

System Memory Command Signal Timings

TCMD Total CMD Buffer window available for 1075 ps 1

(tCMDVB+tCMDVA) command buffers (RAS#, CAS#,
WE#, BS[2:0], MA)

System Memory Control Signal Timings

TCTL Total Control buffer Window available 1125 ps 2

(tCTLVB + tCTLVA) for Control buffers (CS#, CKE)

System Memory Data and Strobe Signal Timings

TDVB+TVDA Data, DQ and DM timing window 495 ps 3

available at the interface output for
write commands. tDVB is data
available before strobe and tDVA is
data available after corresponding
slope.
TSU + THD Data, DQ Input Setup Plus Hold Time 255 ps 4
requirement for successful Read
operation. These Setup and Hold
numbers are measured w.r.t.
corresponding strobe or Falling Edge
TDQSS -120 120 ps
TWPRE DQSP/N Preamble duration (one 0.9 tCKAV
dummy cycle) G
TWPST DQSP/N Postamble Duration 0.4 tCKAV
G

NOTES:
1. The CMD time is measured w.r.t. differential crossing of DRAM_CKP and DRAM_CKN. The tCMDVB and tCMDVA will be
adjusted for proper CMD Setup and Hold time requirement at DRAM. The command timing assumes CMD-1N Mode.
2. The CTL time is measured w.r.t. differential crossing of DRAM_CKP and DRAM_CKN. The tCTLVB and tCTLVA will be
adjusted for proper CTL Setup and Hold time requirement at DRAM.
3. The accurate strobe placement using write training algorithm will be performed which will guarantee the required Data
setup/hold time w.r.t. strobe differential crossing at the DRAM input.
4. The Read training algorithm will center the DQS internally inside DRAM interface in order to have equal tSU and tHD
timings.
5. All the timing windows are measured at 50% of the respective DRAM signal swing.

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Figure 22. DDR3L DQ Setup/Hold Relationship to/from DQSP/DQSN (Read Operation)

DQSN
0. 5 x
DRAM_VDD_S4
DQS
tHD

tSU tSU

DQ
Valid Data Valid Data Valid Data Valid Data

tHD

Figure 23. DDR3L DQ and DM Valid before and after DQSP/DQSN (Write Operation)

DQSN
0.5 x
DRAM_VDD_S4
DQSP

tDVB tDVA tDVB tDVA

DQ, DM Valid Data Valid Data Valid Data Valid Data

Figure 24. DDR3L Write Pre-amble Duration

tWPRE
DQSN
DQSP / 0.5 x
DQSN DRAM_VCC
_S3
DQSP

DQSP/DQSN Write Pre-amble DQSP/DQSN Toggle

Figure 25. DDR3L Write Post-amble Duration

tWPST
DQSN

0. 5 x
DRAM_VDD_S4
DQSP
DQSP/ DQSN Write Post
-
DQSP/ DQSN Toggle amble

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Figure 26. DDR3L Command Signals Valid before and after CK Rising Edge

CKN

CKP
tCMDVB tCMDVA

MA, BS,
RAS#,
Valid CMD
CAS#, WE#

CS#

Figure 27. DDR3L CKE Valid before and after CK Rising Edge

CKP

CKN
tCTLVB tCTLVA

CKE Valid

Figure 28. DDR3L CS# Valid before and after CK Rising Edge

CKP

CKN
tCTRL_VB tCTRL_VA

CS#
0.5 x
DRAM_VDD_S4

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Figure 29. DDR3L ODT Valid before CK Rising Edge

CKP

CKN
tCTRL_VB tCTRL_VB

0.5 x
DRAM_VDD_S4
ODT

Figure 30. DDR3L Clock Cycle Time

tCK

CKN

CKP

Figure 31. DDR3L Skew between System Memory Differential Clock Pairs (CKP/CKN)

CKN[x]

CKP[x]

tSKEW

CKN[y]

CKP[y]

NOTE: x represents one differential clock pair, and y represents another differential clock pair
within same channel.

Figure 32. DDR3L CK High Time

tCH

CKN

CKP

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Figure 33. DDR3L CK Low Time

tC L

CKN

CKP

Figure 34. DDR3L DQS Falling Edge Output Access Time to CK Rising Edge

CKN

CKP

tDSS

DQSP

0.5 x
DQSP DQSN
DRAM_VDD_S4

DQSN
DQSP/DQSN Toggle
DQSP/DQSN Write Pre-amble

Figure 35. DDR3L DQS Falling Edge Output Access Time From CK Rising Edge

CKN

CKP
tDSH

DQSN

0.5 x
DQSP DQSN
DRAM_VDD_S4

DQSP
DQSP/DQSN Write Preamble DQSP/DQSN Toggle

Figure 36. DDR3L CK Rising Edge Output Access Time to the 1st DQS Rising Edge

CKN

CKP

MA, BS,
Write CMD
RAS#,
CAS#, WE#
tDQSS
DQSP

0.5 x
DQSP DQSN DRAM_VDD_S4

DQSN
DQSP/DQSN Write Preamble DQSP/DQSN Toggle

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9.6.5 Display AC Specifications

9.6.5.1 DDI Main Transmitter AC specification

Table 105. DDI Main Transmitter AC specification (Sheet 1 of 2)

Symbol Parameter Min Typ Max Units Notes

fHBR Frequency for High Bit Rate 2.68569 2.7 2.70081 Gbps 1
fRBR Frequency for Reduced Bit Rate 1.61141 1.62 1.620048 Gbps 1

UI_High_Rate Unit Interval for high bit rate (2.7 Gbps / 370 ps 1
lane)

UI_Low_Rate Unit Interval for high bit rate (1.62 Gbps / 617 ps 1
lane)

Down_Spread_Amplit Link clock down Spreading 0 0.5 % 2

ude

Down_Spread_Freque Link Clock down Spreading Frequency 30 33 kHz 3

ncy

TTX-EYE_CHIP Minimum TX Eye Width at Tx package 0.72 UI 4

_High_Rate pins

TTX-EYE-MEDIAN-to- Maximum time between the jitter median 0.147 UI 4

MAX-JITTER and maximum deviation from the median
_CHIP__High_Rate at Tx package pins
TTX-EYE_CHIP Minimum TX Eye Width at Tx package 0.82 UI 5
_Low_Rate pins

TTX-EYE-MEDIAN-to- Maximum time between the jitter median 0.09 UI 5

MAX-JITTER CHIP and maximum deviation from the median
Low_Rate at Tx package pins
TTX-RISE_CHIP, D+/D- TX Output Rise/Fall Time at Tx 50 130 ps 6
TTX-FALL_CHIP package pins

ITX-SHORT TX Short Circuit Current Limit 50 mA 7

LTX- Lane-to-Lane Output Skew at Tx package 2 UI
SKEWINTER_PAIR pins
LTX- Lane Intra-pair Output Skew at Tx 20 ps
SKEWINTRA_PAIR package pins
TTX-RISE_FALL Lane Intra-pair Rise-fall Time Mismatch at 5 % 8
_MISMATCH Tx package pins.
_CHIPDIFF

FTX-REJECTION-BW Clock Jitter Rejection 4 MHz 9

Bandwidth
VTX-AC-CM TX AC Common Mode 20 mV 2
Voltage
CTX AC Coupling Capacitor 75 200 nF 11
TRISE/TFALL Rise time/ Fall time (20%-80%) 75 - ps

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Table 105. DDI Main Transmitter AC specification (Sheet 2 of 2)

Symbol Parameter Min Typ Max Units Notes

VUNDERSHOOT Undershoot, max 0.25 of

full
differenti
al
amplitude
LTX- Intra-Pair skew at source connector 0.15 UI ps
SKEWINTER_PAIR

LTX- Intra-Pair skew at source connector 1.212 ns 12

SKEWINTRA_PAIR

Clock duty cycle, min/average/max 40 50 60 %

TMDS differential Clock Jitter 0.25 UI

NOTES:
1. Frequency High limit = +300ppm; Low limit = -5300ppm
2. Range: 0% ~ 0.5% when downspread enabled
3. Range: 30 kHz ~33 kHz when downspread enabled.
4. For High Bit Rate.
5. For Reduced Bit Rate.
6. At 20 to 80
7. Total drive current of the transmitter when it is shorted to its ground.
8. Informative. D+ rise to D- fall mismatch and D+ fall to D- rise mismatch.
9. Informative. Transmitter jitter must be measured at source connector pins using a signal analyzer that has a 2nd order
PLL with tracking bandwidth of 20MHz (for D10.2 pattern) and damping factor of 1.428.
10. Measured at 1.62 GHz and 2.7 GHz (if supported), within the frequency tolerance range. Time-domain measurement using
a spectrum analyzer.
11. All DisplayPort Main Link lanes as well as AUX CH must be AC coupled. AC coupling capacitors must be placed on the
transmitter side. Placement of AC coupling capacitors on the receiver side is optional.
12. 0.20* Tcharacter @165MHz

Table 106. DDI AUX Channel AC Specification

Symbol Parameter Min Typ Max Units Notes1

UI AUX Unit Interval 0.4 0.5 0.6 µs 1

TAUX-BUS-PARK AUX CH bus park time 10 ns 2
TCYCLE-to-CYCLE Maximum allowable UI variation within a 0.08 UI 3
Jitter single transaction at connector pins of a
transmitting Device
Maximum allowable variation for adjacent 0.04 UI 4
bit times within a single transaction at
connector pins of a transmitting Device
IAUX_SHORT AUX Short Circuit Current Limit 90 mA 5
CAUX AC Coupling Capacitor 75 200 nF 6

NOTES:
1. Results in the bit rate of 1Mbps including the overhead of ManchesterII coding.
2. Period after the AUX CH STOP condition for which the bus is parked
3. Equal to 48 ns maximum. The transmitting Device is a Source Device for a Request transaction and a
Sink Device for a Reply Transaction
4. Equal to 24 ns maximum. The transmitting Device is a Source Device for a Request transaction and a
Sink Device for a Reply Transaction.
5. Total drive current of the transmitter when it is shorted to its ground.
6. The AUX CH AC-coupling capacitor placed on both the DP upstream and downstream devices.

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9.6.5.2 Analog VGA Display AC Specification

The VGA DAC (digital-to-analog converter) consists of three identical 8-bit DACs to
provide red, green, and blue color components. Each DAC can output a current from 0
to 255 units of current, where one unit of current (LSB) is defined based on the VESA
video signal standard.

Table 107. R,G,B / VGA DAC Display AC Specification

Symbol Parameter Min Nom Max Unit Notes

Pixel Clock Frequency = 300 MHz

TRISE R,G,B Video Rise 0.33 1.67 ns 1,2,8 (10-90% of “black”-to-

TIme ”white” video transition)
TFALL R,G,B Video Fall 0.33 1.67 ns 1,3,8 (90-10% of “black”-to-
TIme ”white” video transition)
TSETTLING Settling time 1.0 ns 1,4,8
VO Video Channel-to- 0.833 ns 1,5,8
Channel output
skew
Overshoot/ -0.084 +0.084 V 1,6,8 (0.7V full-scale voltage step)
Undershoot
Noise Injection 2.5 %
Ratio

Pixel Clock Frequency = 350 MHz

TRISE R,G,B Video Rise 0.286 1.43 ns 1,2,8 (10-90% of “black”-to-

TIme ”white” video transition)
TFALL R,G,B Video Fall 0.286 1.43 ns 1,3,8 (90-10% of “black”-to-
TIme ”white” video transition)
TSETTLING Settling time 0.857 ns 1,4,8
VO Video Channel-to- 0.714 ns 1,5,8
Channel output
skew
Overshoot/ -0.084 +0.084 V 1,6,8 (0.7V full-scale voltage step)
Undershoot
Noise Injection 2.5 %
Ratio

NOTES:
1. Measured at each R,G,B termination according to the VESA Test Procedure - Evaluation of Analog Display Graphics
Subsystems Proposal (Version 1, Draft 4, December 1, 2000).
2. R,G,B Max Video Rise/Fall Time: 50% of minimum pixel clock period
3. R,G,B Min Video Rise./Fall Time: 10% of minimum pixel clock period
4. Max settling time: 30% of minimum pixel clock period
5. Video channel-to-channel output skew: 25% of minimum pixel clock period
6. Overshoot/Undershoot: ±12% of “black”-to-”white” video step function
7. Noise Injection Ratio: 2.5% of maximum luminance voltage (dc to max pixel clock frequency)
8. R,G,B AC parameters are strongly dependent on the board design & implementation: actual performance may differ from
values noted above depending on board implementation.

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Table 108. VGA_HSYNC and VGA_VSYNC AC Specification

Symbol Parameter Min Max Units Notes1

TF Fall Time -- 80% of minimum pixel clock ns

period
TR Rise Time -- 80% of minimum pixel clock ns
period
-- Overshoot/Undershoot -- 30% of high level signal mA 1
voltage range
-- Jitter (measured -- One half of the difference V 2
between Hsync pulses) between max and min interval
<15% of the pixel clock, DC to
max.

NOTES:
1. No signal non-monotonicity / excursions allowed in the 0.5 to 2.4V range
2. Measured over 100,000 intervals. Horizontal refresh rate at all image format, worse-case screen
patterns.

Table 109. VGA_DDCDATA, and VGA_DDCCLK Timing Specification

Standard mode
Units Figures
100kbits/s
Symbol Parameter
Min Max

fSCL SCL Clock Frequency 0 100 kHz 37

tLOW Low Period of SCL Clock 4.7 -- µs
tHIGH High Period of SCL Clock 4 -- µs
1
tR Rise Time of Both SDA and SCL -- 1000 ns
Signals
tF Fall Time1 of Both SDA and SCL -- 300 ns
Signals
tHD:DAT Data Hold Time3 0 -- µs
tSU:DAT Data Setup Time 250 -- ns

NOTES:
1. Measurement point for rise and fall time: VIL(min) - VIL(max)
2. tHD:DAT is the data hold time that is measured from the falling edge of SCL, applies to data in
transmission and the acknowledge.

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Figure 37. VGA_DDCDATA, and VGA_DDCCLK Timing Diagram

9.6.6 MIPI-Camera Serial Interface (CSI) AC Specification

Based on version 2 of the MIPI-CSI specification.

Table 110. MIPI-CSI-2 Receiver Characteristics

Symbol Parameter Min. Typ. Max. Unit Notes

MIPI HS-Receiver Mode

∆VCMRX(HF) Common-mode interference above – – 100 mV 2, 9

450 MHz
∆VCMTX(LF) Common-mode interference -50 – 50 mV 1, 4
between 50–450 MHz
CCM Common-mode termination – – 60 pF 3
SCDRX differential to common-mode – – -26 dB From 0 to
fMAX
(1.33Ghz)

MIPI LP-Receiver Mode

espike Input pulse rejection – – 300 V*ps 5, 6, 7

TMIN-RX Minimum pulse width response 20 – – ns 8
VINT Peak interference amplitude – – 200 mV
fINT Interference frequency 450 – – MHz

NOTES:
1. Excluding static ground shift of 50 mV.
2. ∆VCMRX(HF) is the peak amplitude of a sine wave superimposed on the receiver inputs.
3. For higher bit rates a 14 pF capacitor is needed to meet the common-mode return loss specification.
4. Voltage difference compared to the DC average common-mode potential.
5. Time-voltage integration of a spike above VIL when in the LP-0 state or below VIH when in the LP-1
state.
6. An impulse spike less than this will not change the receiver state.
7. In addition to the required glitch rejection, designers shall ensure rejection of known RF-interference.
8. An input pulse greater than this will toggle the output
9. Improves on DPHY specification, which requires 100 mV maximum.

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Figure 38. Input Glitch Rejection of Low-Power Receivers

2 *T LPX 2 *T LPX
e S P IK E
V IH
In p u t
V IL

T M IN I-R X T M IN I-R X e S P IK E

O u tp u t

Table 111. MIPI-CSI-2 Clock Signal Specification

Note
Symbol Clock Parameter Min. Typ. Max. Unit
s

UIINST UI Instantaneous (In 1 or 1 2.77 ns 1

2 or 3 or 4 Lane (1Gbps/ (360 Mbps/
configuration) 500Mhz) 180Mhz)

NOTE: 1The minimum UI shall not be violated for any single bit period, that is, any DDR half cycle
within a data burst.

Figure 39. MIPI-CSI-2 Clock Definition

CSI_CLKP

CSI_CLKN

1 Data Bit Time = 1 UI 1 Data Bit Time = 1 UI

UIINST(1) UIINST(2)

1DDR Clock Period = UIINST(1) + UIINST(2)

Table 112. MIPI CSI 2 Data Clock Timing Specifications

Symbol Parameter Min. Typ. Max. Units Notes

TSETUP[RX] Data to Clock Setup Time 0.15 – – UIINST 1, 2

[receiver]
THOLD[RX] Clock to Data Hold Time 0.15 – – UIINST 1, 2
[receiver]

NOTES:
1. Total silicon and package delay budget of 0.3*UIINST
2. Total setup and hold window for receiver of 0.3*UIINST

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Figure 40. MIPI-CSI-2 Data to Clock Timing Definitions

Reference Time

TSETUP THOLD

CSI_DP

CSI_DN
0.5 UIINST +
TSKEW
CSI_CLKP

CSI_CLKN
1 UIINST
TCLKp

9.6.7 SCC - SD Card AC Specification

Table 113. SD Card AC Specification (Sheet 1 of 2)

Symbol Parameter Min. Max. Unit Figure Notes

Twc(DDR50) CLK cycle time 19 – ns 44

for DDR50 Mode
Twc(SDR25) CLK cycle time 19 – ns 45
for SDR25 Mode
Twc(SDR12) CLK cycle time 39 – ns 48
for SDR12 Mode
TODLY(DDR5 SD_CLK Transitioning 2 6 ns 44
0) Edge to SDIO_D
TODLY(SDR2 SD_CLK Rising Edge 2 12 ns 45
5) to SDIO_D
TODLY(SDR1 SD_CLK Falling Edge 0 12 ns 48
2) to SDIO_D
TSU_SOC SoC setup time 3 – ns 44 (For DDR50 Mode)
(DDR) (data valid before
clock launched)
TSU_SOC SoC setup time 5 – ns 43 (For SDR12/25 Mode)
(SDR) (data valid before
clock launched)

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Table 113. SD Card AC Specification (Sheet 2 of 2)

Symbol Parameter Min. Max. Unit Figure Notes

THD_SOC SoC hold time 2 – ns 44 (For DDR50 Mode)

(DDR) (data valid after clock
launched)
THD_SOC SoC hold time 2 – ns 43 (For SDR12/25 Mode)
(SDR) (data valid after clock
launched)
TRISE CLK/ Clock Rise and Fall 1 4 ns 1, 2,
TFALL CLK Time (1.8V 3, 4
(1.8V) operation)
TRISE CLK/ Clock Rise and Fall 1 4 ns 1, 2,
TFALL CLK Time (3.3V 3, 4
(3.3V) operation)

1. Based on trace length of 0.25”–4”, 2–5 pF Far End Load for Port 0 AND 2–10 pF Far End Load (for Port 1
and Board impedance of 25–75 Ω.
2. Minimum time deviates from SDIO Specification 2.0, minimum time is not defined in specification.
3. Measured from 0.58–1.27V.
4. Takes into consideration EMI filter of 10 pF - 40 Ω -10 pF.

Figure 41. SD Card Timing Diagram (DDR50)

min (VIH)
CLK TWC DDR50
max (VIL)
THD_SOC
TSU_SOC
TSU_SOC THD_SOC
min (VIH)

INPUT DATA DATA DATA INVALID

max (VIL)

TODLY(DDR50) - MAX TODLY(DDR50) - MAX

TODLY(DDR50) - MIN TODLY(DDR50) - MIN
min (VOH)
OUTPUT DATA DATA DATA
max (VOL)

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Figure 42. SD card Output Timing Diagram (SDR25)

TWC SDR25
½ V DD

CLK
T ODLY(SDR25)

V OH

DATA/CMD

VOL

Figure 43. SD Card Input Timing Diagram (SDR12)

½ VDD

CLK

THD_SOC
DATA/CMD
VOH
TSU_SOC

VOL

9.6.7.1 SD Card Default Speed Specification

Table 114. SD Card Default Speed AC Specification (Sheet 1 of 2)

Symbol Parameter Min. Max. Unit Figure Notes

fPP Clock Frequency Data 0 25 MHz

transfer mode
fOD Clock Frequency 0 400 kHz 1
identification mode
tFL Clock low time 10 - ns Figure 54, 55
tWH Clock High time 10 - ns Figure 54, 55
tTLH Clock Rise time - 10 ns Figure 54, 55
tTHL Clock Fall time - 10 ns Figure 54, 55
Clock Overshoot - 4.5 V

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Table 114. SD Card Default Speed AC Specification (Sheet 2 of 2)

Symbol Parameter Min. Max. Unit Figure Notes

Clock undershoot -1.5 - V

Outputs CMD,DAT (referenced to CLK)

tODLY Output Delay time 0 14 ns Figure 55

during Data Transfer
Mode
tODLY Output Delay time 0 50 ns Figure 55
during Identification
Mode

Inputs CMD, DAT (referenced to CLK)

tISU Input Set-up time 5 - ns Figure 54

tIH Input hold time 5 - ns Figure 54

NOTES:
1. 0 Hz means to stop the clock. The given minimum frequency range is for cases were continues clock is
required.

Figure 44. SD Card Input Timing Diagram (Default)

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Figure 45. SD card Output Timing Diagram (Default)

9.6.7.2 SD Card High Speed Specification

Table 115. SD Card High Speed AC Specification

Symbol Parameter Min. Max. Unit Figure Notes

fPP Clock Frequency Data 0 50 MHz

transfer mode
tFL Clock low time 7 - ns Figure 56, 57
tWH Clock High time 7 - ns Figure 56, 57
tTLH Clock Rise time - 3 ns Figure 56, 57
tTHL Clock Fall time - 3 ns Figure 56, 57
Clock Overshoot - 4.5 V
Clock undershoot -1.5 - V

Outputs CMD,DAT (referenced to CLK)

tODLY Output Delay time - 14 ns Figure 57

during Data Transfer
Mode
tODLY Output Delay time 2.5 - ns Figure 57
during Identification
Mode

Inputs CMD, DAT (referenced to CLK)

tISU Input Set-up time 6 - ns Figure 56

tIH Input hold time 2 - ns Figure 56
CL Total Capacitance for - 40 pF
each line

NOTES:
1. 0 Hz means to stop the clock. The given minimum frequency range is for cases were continues clock is
required.

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Figure 46. SD Card Input Timing Diagram (High Speed)

Figure 47. SD card Output Timing Diagram (High Speed)

9.6.8 SSC - SDIO AC specification

Table 116. SDIO AC Specification

Symbol Parameter Min. Max. Unit Figure Notes

Twc(DDR50) CLK cycle time 19 – ns 48

for DDR50 Mode
Twc(SDR25) CLK cycle time 19 – ns 49
for SDR25 Mode
Twc(SDR12) CLK cycle time 39 – ns 50
for SDR12 Mode
TODLY(DDR50) SD_CLK Transitioning 1.5 6 ns 48
Edge to SDIO_D

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Table 116. SDIO AC Specification

Symbol Parameter Min. Max. Unit Figure Notes

TODLY(SDR25) SD_CLK Rising Edge 3 11.9 ns 49

to SDIO_D
TODLY(SDR12) SD_CLK Falling Edge 0 11.9 ns 50
to SDIO_D
TSU_SOC SoC setup time 1 – ns 48 (For DDR50 Mode)
(DDR) (data valid before
clock launched)
TSU_SOC SoC setup time 4 – ns 51 (For SDR12/25
(SDR) (data valid before Mode)
clock launched)
THD_SOC SoC hold time 2 – ns 48 (For DDR50 Mode)
(DDR) (data valid after clock
launched)
THD_SOC SoC hold time 2 – ns 51 (For SDR12/25
(SDR) (data valid after clock Mode)
launched)
TRISE CLK/ Clock Rise and Fall 1 3 ns 1, 2,
TFALL CLK Time (1.8V 3, 4
(1.8V) operation)
TRISE CLK/ Clock Rise and Fall 1 3 ns 1, 2,
TFALL CLK Time (3.3V 3, 4
(3.3V) operation)

NOTES:
1. Based on trace length of 0.25”–4”, 2–5 pF Far End Load for Port 0 AND 2–10 pF Far End Load (for Port 1
and Board impedance of 25–75 Ω.
2. Minimum time deviates from SDIO Specification 2.0, minimum time is not defined in specification.
3. Measured from 0.58–1.27V.
4. Takes into consideration EMI filter of 10 pF - 40 Ω -10 pF.

Figure 48. SDIO Timing Diagram (DDR50)

min (VIH)
CLK TWC DDR50
max (VIL)
THD_SOC
TSU_SOC
TSU_SOC THD_SOC
min (VIH)

INPUT DATA DATA DATA INVALID

max (VIL)

TODLY(DDR50) - MAX TODLY(DDR50) - MAX

TODLY(DDR50) - MIN TODLY(DDR50) - MIN
min (VOH)
OUTPUT DATA DATA DATA
max (VOL)

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Figure 49. SDIO Output Timing Diagram (SDR25)

TWC SDR25
½ V DD

CLK
T ODLY(SDR25)

V OH

DATA/CMD

VOL

Figure 50. SDIO Output Timing Diagram (SDR12)

½ V DD TWC SDR12
½ V DD

CLK

TODLY(SDR12)

VOH

DATA/CMD

VOL

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Figure 51. SDIO Input Timing Diagram (SDR12/25)

½ VDD

CLK

THD_SOC
DATA/CMD
VIH
TSU_SOC

VIL

9.6.9 SCC - eMMC 4.5 AC Specification

9.6.9.1 HS/DDR Mode AC Characteristics

Table 117. eMMC 4.5 AC Characteristics (Sheet 1 of 2)

Symbol Parameter Min. Max. Units Figures Notes

Fpp Clock Frequency Data transfer Mode 200 MHZ

Twc(HS/DDR) CLK Cycle Time (High Speed Mode and 20 – ns 52
DDR Modes)
TDC CLK Duty Cycle 40 55 %
TODLY(HS) EMMC_CLK Rising Edge to EMMC_D - 13.7 ns 52
(High Speed Mode)
TODLY(DDR) EMMC_CLK Rising Edge to EMMC_D 1.5 7 ns 53
(DDR Mode)
TSU(HS) EMMC_D Input Setup Time to EMMC_CLK 1.5 – ns 54
Rising Edge (data read - HS mode)
TH(HS) EMMC_D Input Hold Time to EMMC_CLK 3 – ns 54
Rising Edge (data read - HS mode)
TSU(DDR) EMMC_D Input Setup Time to EMMC_CLK 2.5 – ns 53
Rising Edge
(data read - DDR Mode)
TH(DDR) EMMC_D Input Setup Time to EMMC_CLK 2.5 – ns 53
Rising Edge (data read–DDR Mode)
TRISE(HS) Rise Time (Output - HS mode) - 3 ns 1, 2, 3

TFALL(HS) Fall Time (Output -HS mode) - 3 ns 1, 2, 3

TRISE(DDR) Rise Time (Output - DDR mode) - 2 ns 1, 2, 3

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Table 117. eMMC 4.5 AC Characteristics (Sheet 2 of 2)

Symbol Parameter Min. Max. Units Figures Notes

TFALL(DDR) Fall Time (Output - DDR mode) - 2 ns 1, 2, 3

TRSTW eMMC_RST# Pulse Width 1 – µs

TRSTCA eMMC_RST# to Command Time 200 – µs 4

TRSTH eMMC_RST# High Period 1 – µs

(interval time)

NOTES:
1. Based on trace length of 0.25 –2”, 2–12 pF Far End Load and Board impedance of 25–75 Ω.
2. Measured from 35–65%.
3. Minimum time deviates from e-MMC* Specification 4.41, minimum time is not defined in the specification.
4. Seventy-four (74) clock cycles are required before issuing CMD1 or CMD0 with argument 0xFFFFFFFA.

Figure 52. eMMC* Output Timing Diagram (High Speed Mode)

TWC(HS)
½ VDD

CLK
TODLY(HS)

V OH
DATA/ CMD

VOL

Figure 53. eMMC* DDR Timings

min(VIH)
CLK ½ VDD T WC( DDR)
½ VDD
max(VIL)
THD_SOC_DDR
TSU_SOC_DDR
TSU_SOC_DDR THD_SOC_ DDR
min(VIH)

INPUT DATA DATA DATA INVALID

max(VIL)

TODLY( DDR) - MIN

TODLY( DDR) - MAX TODLY( DDR) - MAX
min(VOH)
OUTPUT DATA DATA DATA INVALID
max(VOL)

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Figure 54. eMMC* Input Timing Diagram (High Speed Mode)

½ VDD

CLK

THD_SOC
DATA/CMD
VIH
TSU_SOC

VIL

9.6.9.2 HS200 Mode AC Characteristics

Table 118. eMMC 4.5 AC Characteristics

Symbol Parameter Min. Max. Units Figures Notes

Fpp Clock Frequency Data transfer Mode 200 MHZ

Twc CLK Cycle Time 5 – ns
TDC CLK Duty Cycle 30 70 %
TVW Output Valid Data Window 2.375 - ns 70
TISU Input Setup Time 1.40 – ns 70
TIH Input Hold Time 0.8 – ns 70
TTLH Rise Time - 1 ns 69

TTHL Fall Time - 1 ns 69

Figure 55. eMMC Clock Signal Timing Diagram (HS200 Mode)

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Figure 56. eMMC Input Timing Diagram (HS200 Mode)

9.6.10 SATA AC Specification

Table 119. SATA Specification and Interface Timings (Sheet 1 of 3)

Symbol Parameter Gen1 Gen2 Units Notes

Min Max Min Max

UI Unit Interval 666.43 670.23 333.21 335.11 ps

Receiver Parameter

ZdiffRX RX Pair Differential Impedance 85 115 85 115 Ω

vRX-DIFF-PP VdiffRX, RX Differential Input 325 600 275 750 mvPP
Voltage
TRX-RISE RX Rise Time 100 273 67 136 ps
TRX-FALL RX Fall Time 100 273 67 136 ps
TRX-SKEW RX Differential Skew 100 50 100 ps
VRX-CM-AC Vcm,acRX,RX AC Common Mode 100 100 150 mvPP
Voltage
FRX-CM-AC AC Common Mode Frequency 3 200 2 200 MHz
TJ-Con-DD-5 TJ at Connector, Data-Data, 5 0.43 UI
DJ-Con-DD-5 DJ at Connector, Data-Data, 5 0.35 UI
TJ-Con-DD- TJ at Connector, Data-Data, 250 0.60 UI
250

DJ-Con-DD- DJ at Connector, Data-Data, 250 0.42 UI

250

TTJ-Con-CD- TJ at Connector, Clk-Data, fBAUD/ 0.46 UI

10 10

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Table 119. SATA Specification and Interface Timings (Sheet 2 of 3)

Symbol Parameter Gen1 Gen2 Units Notes

TDJ-Con-CD- DJ at Connector, Clk-Data, fBAUD/ 0.35 UI

10 10
TTJ-Con-CD- TJ at Connector, Clk-Data, fBAUD/ 0.60 UI
500 500
TDJ-Con-CD- DJ at Connector, Clk-Data, fBAUD/ 0.42 UI
500 500
Tjcon CD-1667 Tj at Connector Clk-Data, fbaud/ .65 .65 UI
1667
Dj con CD- Dj at Connector Clk-Data, fbaud/ .35 .35 UI
1667 1667
RLDD11,RX Min Differential Mode return loss 18 dB
(limits 150 - 300 MHz)
Min Differential Mode return loss 8 dB
(limits 1.2 - 2.4 GHz)
Min Differential Mode return loss 3 dB
(limits 2.4 - 3.0 GHz)
RLCC11,RX RX Common Mode Return Loss 5 dB
(limits 150 - 600 MHz)
RX Common Mode Return Loss 2 dB
(limits 1.2 - 2.4 GHz)
RX Common Mode Return Loss 1 dB
(limits 3.0 - 5.0 GHz)
VdiffRX RX Differential Input Voltage 240 600 240 750 mV

Transmitter Parameter

ZdiffTX RX Pair Differential Impedance 85 115 85 115 Ω

vTX-DIFF-PP VdiffTX, TX Differential Input 400 600 400 700 mvPP
Voltage
TTX-RISE TX Rise Time 100 273 67 136 ps 1
TTX-FALL TX Fall Time 100 273 67 136 ps 1
TTX-SKEW TX Differential Skew - 20 - 20 ps
VCM-AC TX AC Common Mode 50 mv
TTJ-Con-DD-5 TJ at Connector, Data-Data, 5 UI 0.355 UI
TDJ-Con-DD-5 DJ at Connector, Data-Data, 5 UI 0.175 UI
TTJ-Con-DD- TJ at Connector, Data-Data, 250 0.470 UI
250 UI
DJ-Con-DD- DJ at Connector, Data-Data, 250 0.220 UI
250

TTJ-Con-CD- TJ at Connector, Clk-Data, fBAUD/ 0.30 UI

10 10
TDJ-Con-CD- DJ at Connector, Clk-Data, fBAUD/ 0.17 UI
10 10

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Table 119. SATA Specification and Interface Timings (Sheet 3 of 3)

Symbol Parameter Gen1 Gen2 Units Notes

TTJ-Con-CD- TJ at Connector, Clk-Data, fBAUD/ 0.37 UI

500 500
TDJ-Con-CD- DJ at Connector, Clk-Data, fBAUD/ 0.19 UI
500 500
Tjcon CD-1667 Tj at Connector Clk-Data, fbaud/ .65 .65 UI
1667
Dj con CD- Dj at Connector Clk-Data, fbaud/ .35 .35 UI
1667 1667
RLDD11,TX Min Differential Mode return loss 14 dB
(limits 150 - 300 MHz)
Min Differential Mode return loss 6 dB
(limits 1.2 - 2.4 GHz)
Min Differential Mode return loss 3 dB
(limits 2.4 - 3.0 GHz)
RLCC11,TX RX Common Mode Return Loss 5-8 dB
(limits 150 - 600 MHz)
RX Common Mode Return Loss 2 dB
(limits 1.2 - 2.4 GHz)
RX Common Mode Return Loss 1 dB
(limits 3.0 - 5.0 GHz)
vRX-DIFF-PP VdiffRX, RX Differential Input 325 600 275 750 mvPP
Voltage
TRX-RISE RX Rise Time 100 273 67 136 ps
TRX-FALL RX Fall Time 100 273 67 136 ps
TRX-SKEW RX Differential Skew 100 50 100 ps
VRX-CM-AC Vcm,acRX,RX AC Common Mode 100 100 150 mvPP
Voltage

NOTES:
1. 20% - 80%
2. All parameters measured at Rload = 100Ω ±10% load.
3. For a detailed description of the symbols, see the IEEE1596.3-1996 Standard.

9.6.11 USB 2.0 Host AC Specification

Table 120. USB 2.0 AC specification (HIGH SPEED)

Symbol Parameter Min Max Units Notes Fig

DRIVER CHARCTERTICS:
THSR Rise Time (10% - 90%) 100 ps
THSF Fall Time (10% - 90%) 100 ps
ZHSDRV Driver Output Resistance (which also 40.5 49.5
serves as high- speed termination)

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Table 120. USB 2.0 AC specification (HIGH SPEED)

Symbol Parameter Min Max Units Notes Fig

CLOCK TIMINGS:
THSDRAT High-speed Data Rate 479.7 480.2 Mb/s
60 40
THSFRAM Microframe Interval 124.9 125.0 us
375 625

Table 121. USB 2.0 AC specification (FULL SPEED)

Symbol Parameter Min Max Units Notes Fig

DRIVER CHARCTERTICS:
TFR Rise Time 4 20 ns 44,4
5
TFF Fall Time 4 20 ns 44,4
5
TFRFM Differential Rise and Fall Time Matching 90 111.1 % 10
1
ZDRV Driver Output Resistance for driver 28 44
which is not high-speed capable
CLOCK TIMINGS:
TFDRATH Full-speed Data Rate for hubs and 11.99 12.00 Mb/s
S devices which are high-speed capable 60
TFDRATE Full-speed Data Rate for hubs and 11.97 12.03 MB/s
devices which are not high-speed 00
capable
TFRAME Frame Interval 0.999 1.000 ms
5 5
FULL-SPEED DATA TIMINGS

TDJ1 Source Jitter Total (including -3.5 3.5 ns 7,8,12 46

-4 4 ns ,10
TDJ2 frequency tolerance): To Next
Transition For Paired Transitions
TFDEOP Source Jitter for Differential -2 5 ns 8,11 47
Transition to SE0 Transition
TFEOPT Source SE0 interval of EOP 160 175 ns 47

Table 122. USB 2.0 AC specification (LOW SPEED)

Symbol Parameter Min Max Units Notes Fig

DRIVER CHARCTERTICS:
TLR Rise Time 75 300 ns 44
TFF Fall Time 75 300 ns 44
TLRFM Differential Rise and Fall Time Matching 80 125 % 10

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Table 122. USB 2.0 AC specification (LOW SPEED)

Symbol Parameter Min Max Units Notes Fig

CLOCK TIMINGS:
TLDRATH Low-speed Data Rate for hubs and 1.499 1.500 Mb/s
S devices which are high-speed capable 25 75
TLDRATE Low-speed Data Rate for hubs and 1.477 1.522 MB/s
devices which are not high-speed 5 5
capable
FULL-SPEED DATA TIMINGS

TUDJ1 Upstream facing port source Jitter -95 95 ns 7,8 46

TUDJ2 Total (including frequency -150 150 ns
tolerance): To Next Transition For
Paired Transitions

TDDJ1 Downstream facing port source -25 25 ns 7,8 46

TDDJ2 Jitter Total (including frequency -14 14 ns
tolerance): To Next Transition For
Paired Transitions
TLDEOP Source Jitter for Differential -40 100 ns 8,11 47
Transition to SE0 Transition
TLEOPT Source SE0 interval of EOP 1.25 1.50 us 47

NOTES:
1. Measured at A plug.
2. Measured at A receptacle.
3. Measured at B receptacle.
4. Measured at A or B connector.
5. Measured with RL of 1.425 kΩ to 3.6 V.
6. Measured with RL of 14.25 kΩ to GND.
7. Timing difference between the differential data signals.
8. Measured at crossover point of differential data signals.
9. The maximum load specification is the maximum effective capacitive load allowed that meets the target
VBUS drop of 330 mV.
10. Excluding the first transition from the Idle state.
11. The two transitions should be a (nominal) bit time apart.
12. For both transitions of differential signaling.
13. Must accept as valid EOP.
14. Single-ended capacitance of D+ or D- is the capacitance of D+/D- to all other conductors and, if
present, shield in the cable. That is, to measure the single-ended capacitance of D+, short D-, VBUS,
GND, and the shield line together and measure the capacitance of D+ to the other conductors.
15. For high power devices (non-hubs) when enabled for remote wakeup.

Figure 57. USB Rise and Fall Times

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Figure 58. USB Full Speed Load

Figure 59. USB Differential Data Jitter for Low/Full- Speed

Figure 60. USB Differential-to-EOP Transition Skew and EOP Width for Low/Full-Speed

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9.6.12 USB 3.0 AC Specification

Figure 61. USB 3.0 Signals AC Specification

Symbol Parameter Min Max Units Notes

TMIN- Deterministic min Pulse - 0.96 UI 1

PULSE-DJ
TMIN- Tx min Pulse - 0.90 UI 2
PULSE-TJ
TTX-EYE Transmitter Eye 0.625 - UI 3
TTx-DJ- Tx deterministic jitter - .205 UI 4
DD

NOTES:
1. Tx pulse width variation that is deterministic.
2. Min Tx Pulse at 10-12 including Dj and Rj.
3. Includes all jitter sources.
4. Deterministic jitter only assuming the Dual Dirac distribution

9.6.13 ULPI USB 2.0 Device AC Specification

Table 123. ULPI Signals AC Specification

Symbol Parameter Min Typ Max Units Notes

FSTEADY Clock frequency steady state 59.97 60 60.03 MHz

TRISE/ Input clock rise/fall time 2 7 ns 1,2
FALL
TSC,TSD Setup time (control in, 8-bit data 6 - ns
in) relative to rising clock edge at
host
THC,THD Hold time (control in, 8-bit data in) 0 ns
relative to rising clock edge at host
TDC,TDD Output delay (control in, 8-bit data 0 - ns 3
in) relative to rising clock edge at
host
TRISE/ Rise/Fall time (control out, 8-bit data 2 7 ns 1,2,4
FALL out)

NOTES:
1. Based on trace length of 1–4”, Far End Load of 1–5 pF and board impedance of 30–75 ohms.
2. Measured from 10–90%.
3. Minimum time deviates from ULPI Specification, minimum time is not defined in ULPI Specification.
4. Minimum time and Maximum time not mentioned in the ULPI Specification.

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Figure 62. ULPI Timing Diagram

THD

Data
in
TSD

TSC
THC
TSC

TDC
Data
out
TDD

ULPI_D[7:0]
ULPI_CLK

ULPI_NXT
ULPI_STP
ULPI_DIR

9.6.14 Intel® HD Audio AC Specification

9.6.14.1 1.5-V AC specification

The output driver on the Intel HD Audio electrical link must be able to deliver an initial
voltage of at least VIL_HDA or VIH_HDA respectively at the receiver through the bus with
known characteristic impedance and at the same time meeting signal quality
requirements.

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The minimum and maximum drive characteristics of Intel HD Audio output buffers are
defined by the V/I curves. Table 124 and Figure 63 describe the SDO buffer AC drive
specification where as the Table 125 and Figure 64 describe the AC drive specification
of the HDA_SDI[x] buffers. The AC drive specification for HDA_SYNC, HDA_RST# and
HDA_CLK buffers is same as that of HDA_SDO.

These curves should be interpreted as traditional ‘DC’ transistor curves with the
following exceptions: ‘DC drive point’ is the only position on the curves at which steady
state operation is intended, while the higher currents are only reached momentarily
during bus switching transients. The ‘AC drive point’ (real definition of buffer strength)
defines the minimum instantaneous current required to switch the bus.

Adherence to these curves should be evaluated at worst case conditions. Minimum pull
up curve is evaluated at minimum VCCHDA and high temperature. Minimum pull down
curve is evaluated at minimum VCCHDA and high temperature. The maximum curve
test points are evaluated at maximum VCCHDA and low temperature.

Inputs must be clamped to both ground and power rails. The clamp diode
characteristics are also listed here for reference.

Figure 63. V/I Curves for HDA_SDO buffers

Table 124. HDA_SDO 1.5V Buffer AC Specification (Sheet 1 of 2)

Symbol Parameter Condition Min Max Unit

IOH switching 0 < VO_HDA < - mA

Current High 0.7VCCHDA 16.67VCCHDA
0.7VCCHDA < VO_HDA - mA
< 0.9VCCHDA 55.57(VCCHD
A-Vout)

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Table 124. HDA_SDO 1.5V Buffer AC Specification (Sheet 2 of 2)

Symbol Parameter Condition Min Max Unit

0.7VCCHDA < VO_HDA (151.52/ mA

< VCCHDA VCCHDA) *
(VO_HDA-
VCCHDA) *
(VO_HDA +
0.4VCCHDA)
(Test Point) VO_HDA = 0.7VCCHDA -50VCCHDA mA
IOL Low Period of VCCHDA > VO_HDA 16.67VCCHDA mA
SCL Clock >0.3VCCHDA
0.3VCCHDA > VO_HDA 57.57Vout mA
> 0.1VCCHDA
0.3VCCHDA > VO_HDA (238.1/ mA
>0 VCCHDA) *
VO_HDA *
(VCCHDA-
VO_HDA)
(Test Point) VO_HDA = 0.3VCCHDA 50VCCHDA mA
ICL Low Clamp -3 < VI_HDA < -1 -25 +
Current (VI_HDA+1)/
0.015
ICH High Clamp VCCHDA+4 > Vin > 25+(VI_HDA-
Current VCCHDA+1 VCCHDA-1)/
0.015
Slew_r Output rise Slew 0.25VCCHDA to 0.5 1.5 V/ns
rate 0.75VCCHDA Slew
rate
(note1)
Slew_f Output rise Slew 0.75VCCHDA to 0.5 1.5 V/ns
rate 0.25VCCHDA Slew
rate
(note1)

NOTE:
1. Slew rate is to be interpreted as the cumulative edge rate across the specified range, (0.25VCCHDA to
0.75VCCHDA load for rise and 0.75VCCHDA to 0.25VCCHDA load for fall), rather than instantaneous rate
at any point within the transition range.

Table 125. HDA_SDI[x] 1.5V Buffer AC Specification (Sheet 1 of 2)

Symbol Parameter Condition Min Max Unit

IOH switching 0 < VO_HDA < -9.38VCCHDA mA

Current High 0.7VCCHDA
0.7VCCHDA < - mA
VO_HDA < 31.27(VCCHDA-
0.9VCCHDA VO_HDA)

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Table 125. HDA_SDI[x] 1.5V Buffer AC Specification (Sheet 2 of 2)

Symbol Parameter Condition Min Max Unit

0.7VCCHDA < (113.64/ mA

VO_HDA < VCCHDA VCCHDA) *
(VO_HDA-
VCCHDA) *
(VO_HDA+
0.4VCCHDA)
(Test Point) VO_HDA = -37.5VCCHDA mA
0.7VCCHDA
IOL Low Period of VCCHDA > VO_HDA 9.38VCCHDA mA
SCL Clock >0.3VCCHDA
0.3VCCHDA > 31.27VO_HDA mA
VO_HDA >
0.1VCCHDA
0.3VCCHDA > (178.57/ mA
VO_HDA >0 VCCHDA) *
VO_HDA *
(VCCHDA-
VO_HDA)
(Test Point) VO_HDA= 0.3VCCHDA 37.55VCCHDA mA
ICL Low Clamp -3 < VI_HDA < -1 -25
Current +(VI_HDA+1)/
0.015
ICH High Clamp VCCHDA+4 > VI_HDA 25+(VI_HDA-
Current > VCCHDA+1 VCCHDA-1)/
0.015
Slew_r Output rise 0.25VCCHDA to 0.5 1.5 V/ns
Slew rate 0.75VCCHDA Slew
rate
(note1)
Slew_f Output rise 0.75VCCHDA to 0.5 1.5 V/ns
Slew rate 0.25VCCHDA Slew
rate
(note1)

NOTE:
1. Slew rate is to be interpreted as the cumulative edge rate across the specified range, (0.25VCCHDA to
0.75VCCHDA load for rise and 0.75VCCHDA to 0.25VCCHDA load for fall), rather than instantaneous rate
at any point within the transition range.

9.6.14.2 Maximum AC Ratings and Device Protection

All Intel HD Audio buffers should be capable of withstanding continuous exposure to the
waveform shown in Figure 64. It is recommended that these waveforms be used as
qualification criteria against which the long term reliability of each device is evaluated.
Table 126 and Table 127 list the parameters of the waveform. This level of robustness
should be guaranteed by design; it is not intended that this waveform should be used
as a production test.

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These waveforms are applied with the equivalent of a zero impedance voltage source,
driving through a series resistor directly into each input or tri-stated output pin. The
open-circuit voltage of the voltage source is shown in Figure 64, which is based on the
worst case overshoot and undershoot expected in actual Intel HD Audio buses. The
resistor values are calculated to produce the worst case current into an effective
internal clamp diode.

Figure 64. Maximum AC Waveforms for 1.5 V Signaling

NOTE:
1. The voltage waveform is supplied at the resistor shown in the evaluation setup, not the
package pin.
2. Any internal clamping in the device being tested will greatly reduce the voltage levels seen
at the package pin.

Table 126. 1.5V Parameters for Maximum AC Signalling Waveforms

Symbol Parameter Min Max Unit

V1 Overshoot Voltage 3.25 V

V2 Undershoot Initial Voltage 1.65 V
V3 Undershoot Voltage -1.6 V
Vpu Waveform peak-to-peak 3.25 V
Vpo Waveform peak-to-peak 3.25 V
trf Rise/fall time 0.5 1.5 V/ns
fSDI Frequency of AC rating waveform as 24 MHz
applied to SDI input buffers
fSDO Frequency of AC rating waveform as 24 MHz
applied to SDO input buffers

Table 127. Resistance value for the AC rating Waveform

Condition Value

Overshoot waveform at the codec 65 Ohms

Undershoot waveform ar the codec 101 Ohms
Overshoot waveform at the controller 108 Ohms

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Table 127. Resistance value for the AC rating Waveform

Condition Value

Undershoot waveform ar the controller 133 Ohms

NOTE:
1. The voltage waveform is supplied at the resistor shown in the evaluation setup, not the
package pin.
2. Any internal clamping in the device being tested will greatly reduce the voltage levels seen
at the package pin.

9.6.15 I2S (Audio) AC Specification

9.6.15.1 I2S Slave Mode AC Specification

Table 128. I2S AC Timings

Symbol Parameter Min. Max. Units Figure Notes

TDC Clock Duty Cycle 45 55 % 65, 66, 67

TI2S Clock Frequency 9.6 MHz 65, 66, 67
TS-RXD Setup for DATAIN with 6 – ns 65, 66, 67 1, 2, 3
respect to the CLK active
edge.
TH_RXD Hold for DATAIN with 6 – ns 65, 66, 67 1, 2, 3
respect to the CLK active
edge.
TS-FS Setup for FRM with respect 6 – ns 65, 66, 67 1, 2, 3
to the CLK active edge.
TH_FS Hold for FRM with respect 20 – ns 65, 66, 67 1, 2, 3
to CLK active edge.
TCO_TXD Tco of DATAOUT with – 18 ns 65, 66, 67 1, 2,3
respect to CLK active edge
at the host
TCO-FS Tco of DATAOUT with – 20 ns 65, 67 1, 2, 3, 4
respect to FRM at the host

NOTE:
1. Active edge refers to the mode selected.
2. For I2S mode, data launches at falling edge and is being captured at rising edge.
3. For PCM mode data launches at rising edge and is being captured at falling edge. PCM Mode has two
different modes, Short Frame Mode and Long Frame Mode.
a. Short Frame Mode—FS is asserted one clock cycle earlier than data is launched by the Master.
b. Long Frame Mode—FS and Data are launched on the same clock edge by the Master.
4. “Measurement of leakage currents require special JTAG instructions. Without special JTAG instructions, pin
leakage measurements on some of these pins can be in the range of 800 μA to 1 mA due to internal weak
PU/PD resistors on these buffers”

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 Electrical Specifications

Figure 65. I2S Slave Port Timings in I2S Mode

I2S MODE
TCO_FS

TH-FS
FRM

TS-FS

TDC TDC

CLK
TI2S

TCO_TXD

DATAOUT

TS-RXD TH-RXD

DATAIN

Figure 66. I2S Slave Port Timings in PCM Short Frame Mode

PCM Short Frame Mode

FRM TH-FS
TS-FS

TDC
TDC

CLK

TI2S

TCO_TXD

DATAOUT

TS-RXD TH-RXD

DATAIN

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Figure 67. I2S Slave Port Timings in PCM Long Frame Mode

PCM Long Frame Mode

TCO_FS

FRM
TDC
TDC

CLK

TI2S

TCO_TXD

DATAOUT
TS-RXD TH-RXD

DATAIN

9.6.15.2 I2S Master Mode AC Specification

Table 129. I2S Master Mode AC Timing

Symbol Parameter Min. Max. Units Figure

TDC Clock Duty Cycle 45 55 %

TI2S Clock Frequency 12.5 MHz
TS-RXD Setup for DATAIN with respect to 10 – ns
the CLK active edge
TH-RXD Hold for DATAIN with respect to the 10 – ns
CLK active edge
TCO_TXD TCO of DATAOUT with respect to – 10 ns
CLK active edge at the SoC
TCO-FS TCO of FRM with respect to CLK at 10 ns
the SoC

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 Electrical Specifications

9.6.16 PCI Express* AC Specification

Table 130. PCI Express* Interface Timings

Symbol Parameter Min Typ Max Unit Figures Notes

Transmitter and Receiver Timings

UI Unit Interval – PCI Express* 399.88 400.12 ps 5

Gen 1 (2.5 GT/s)
UI Unit Interval – PCI Express* 199.9 200.1 ps 5
Gen 2 (5.0 GT/s)
TTX-EYE Minimum Transmission Eye 0.7 — UI 68 1,2
Width
TTX-RISE/Fall TXP/TXN Rise/Fall time 0.125 UI 1,2
(Gen1)

TTX-RISE/Fall TXP/TXN Rise/Fall time 0.15 UI 1,2

(Gen2)

TRX-EYE Minimum Receiver Eye Width 0.40 — UI 69 3,4

NOTES:
1. Specified at the measurement point into a timing and voltage compliance test load and measured over
any 250 consecutive TX UIs. (Also refer to the Transmitter compliance eye diagram)
2. A TTX-EYE = 0.70 UI provides for a total sum of deterministic and random jitter budget of TTXJITTER-MAX =
0.30 UI for the Transmitter collected over any 250 consecutive TX UIs. The TTXEYE-MEDIAN-to-MAX-JITTER
specification ensures a jitter distribution in which the median and the maximum deviation from the
median is less than half of the total TX jitter budget collected over any 250 consecutive TX UIs. It
should be noted that the median is not the same as the mean. The jitter median describes the point in
time where the number of jitter points on either side is approximately equal as opposed to the averaged
time value.
3. Specified at the measurement point and measured over any 250 consecutive UIs. The test load
documented in the PCI Express* specification 2.0 should be used as the RX device when taking
measurements (also refer to the Receiver compliance eye diagram). If the clocks to the RX and TX are
not derived from the same reference clock, the TX UI recovered from 3500 consecutive UI must be used
as a reference for the eye diagram.
4. A TRX-EYE = 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the
Transmitter and interconnect collected any 250 consecutive UIs. The TRX-EYE-MEDIAN-to--MAX-JITTER
specification ensures a jitter distribution in which the median and the maximum deviation from the
median is less than half of the total 0.6 UI jitter budget collected over any 250 consecutive TX UIs. It
should be noted that the median is not the same as the mean. The jitter median describes the point in
time where the number of jitter points on either side is approximately equal as opposed to the averaged
time value. If the clocks to the RX and TX are not derived from the same reference clock, the TX UI
recovered from 3500 consecutive UI must be used as the reference for the eye diagram.
5. Nominal Unit Interval is 400 ps for 2.5 GT/s and 200 ps for 5 GT/s.
6. PCIe Reference clocks follow PCI Express* specification with the exception of edge rate: Max = 8.0 V/ns
instead of 4.0 V/ns. There should be no DC termination of the clocks.

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Figure 68. PCI Express* Transmitter Eye

Figure 69. PCI Express* Receiver Eye

VTS-Diff = 0mV
D+/D- Crossing point

VRS-Diffp-p-Min>175mV

.4 UI =TRX-EYE min

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 Electrical Specifications

9.6.17 PCU - PMC - Suspended Clock AC Specification

Table 131. SUS Clock Timings

Symbol Parameter Min Max Units Notes Figure

fsusclk Operating Frequency 32 kHz 1

t39 High time 9.5 - µs 1
t39a Low Time 9.5 - µs 1

Note: 1. SUSCLK duty cycle can range from 30% minimum to 70% maximum.

9.6.18 PCU - SPI AC Specification

Table 132. SPI AC Specifications

Sym Parameter Min Max Units Notes

t180 Serial Clock Frequency - 25 MHz

t182 SPI Clock duty cycle at Host 44 55 %
t183 Tco of PCU_SPI_MOSI with respect to serial clock edge at -2 10 ns 4
the host
t184 Setup of PCU_SPI_MISO with respect to serial clock edge at 1 ns 4
the host
t185 Hold of PCU_SPI_MISO with respect to serial clock falling 10 ns 4
edge at the host
t186 Setup of PCU_SPI_CS[1:0]# with respect to serial clock 12 ns 4
edge at the host
t187 Hold of PCU_SPI_CS[1:0]# with respect to serial clock at 16 ns 4
the host
t188/t189 Min Idle (de-assertion) time for PCU_SPI_CLK signals 32 ns 5
Trise/Tfall Rise / Fall time 1 5 ns 1,2

NOTES:
1. Based on trace length of up to 4” and board impedance of 30–75 Ω Measured from 30–70%.
2. Total maximum, capacitance of 25 pF
3. Total maximum, capacitance of 5 pF
4. Clock Edge depends on Mode being used on SPI Ports.
5. Applies to Mode 0 and 2 only. This parameter does not apply for Modes 1 and 3.

Table 133. SPI NOR AC Specifications (Sheet 1 of 2)

Sym Parameter Min Max Units Notes

t180 Serial Clock Frequency - 50 MHz

t182 SPI Clock duty cycle at Host 45 55 %
t183 Tco of PCU_SPI_MOSI with respect to serial clock edge at -2 5 ns 4
the host

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Table 133. SPI NOR AC Specifications (Sheet 2 of 2)

Sym Parameter Min Max Units Notes

t184 Setup of PCU_SPI_MISO with respect to serial clock edge 1 ns 4

at the host
t185 Hold of PCU_SPI_MISO with respect to serial clock falling 5 ns 4
edge at the host
t186 Setup of PCU_SPI_CS[1:0]# with respect to serial clock 12 ns 4
edge at the host
t187 Hold of PCU_SPI_CS[1:0]# with respect to serial clock at 16 ns 4
the host
t188/ Min Idle (de-assertion) time for PCU_SPI_CLK signals 32 ns 5
t189
Trise/ Rise / Fall time 1 5 ns 1,2
Tfall

NOTES:
1. Based on trace length of up to 4” and board impedance of 30–75 W Measured from 30–70%.
2. Total maximum, capacitance of 25 pF
3. Total maximum, capacitance of 5 pF
4. Clock Edge depends on Mode being used on SPI Ports.
5. Applies to Mode 0 and 2 only. This parameter does not apply for Modes 1 and 3.

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184
t188
Figure 70. SPI Timing

t186 t187
PCU_SPI_CS#

SCPOL=0
t180
PCU_SPI_CLK t182
t182
SCPOL=1

t183

PCU_SPI_MOSI Data Valid

SCPH=0 t184 t185

PCU_SPI_MOSI

t183

PCU_SPI_MOSI Data Valid

SCPH=1 t184 t185

PCU_SPI_MOSI

Datasheet
Electrical Specifications

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Electrical Specifications

9.6.19 PCU - SMBUS AC Specification

Table 134. SMBUS Clock Signal Timings

Symbol Parameter Min Max Unit Notes Figure

fsmb Operating Frequency 10 100 kHz

tHIGH High time 4.0 50 us 1 71
tLow Low time 4.7 us 71
tRISE Rise time 1000 ns 71
tFALL Fall time 300 ns 71

1. The maximum high time (tHIGH Max) provides a simple method for devices to detect bus idle conditions.

Table 135. SMBus Timing

Sym Parameter Min Max Units Notes Figure

tSTOP_START Bus Tree Time Between Stop and Start 4.7 — µs 72

Condition
tSTART_HOLD Hold Time after (repeated) Start 4.0 — µs 72
Condition. After this period, the first clock
is generated.
tSTART_SET Repeated Start Condition Setup Time 4.7 — µs 72
tSTOP_SET Stop Condition Setup Time 4.0 — µs 72
tDATA_HOLD Data Hold Time 0 — ns 1 72
tDATA_SET Data Setup Time 250 — ns 72
tDEV_TO Device Time Out 25 35 ms 2
tSLVCLK_LOWEXT Cumulative Clock Low Extend Time (slave — 25 ms 3 72
device)
tMSTCLK_LOWEXT Cumulative Clock Low Extend Time — 10 ms 4 72
(master device)

1. tDATA_HOLD has a minimum timing for I2C of 0 ns, while the minimum timing for SMBus is 300 ns.
2. A device will timeout when any clock low exceeds this value.
3. tSLVCLK_LOWEXT is the cumulative time a slave device is allowed to extend the clock cycles in one message from the
initial start to stop. If a slave device exceeds this time, it is expected to release both its clock and data lines and reset
itself.
4. tMSTCLK_LOWEXT is the cumulative time a master device is allowed to extend its clock cycles within each byte of a
message as defined from start-to-ack, ack-to-ack or ack-to-stop.

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 Electrical Specifications

Figure 71. SMBus Transaction

tRISE tFALL
tLOW
PCU_SMB_CLK

tHIGH
t START_HOLD tDATA_HOLD tDATA_SET t START_SET tSTOP_SET

PCU_SMB_DATA

tSTOP_START

Figure 72. SMBus Timeout

Start Stop

tSLVCLK_LOWEXT
CLKack CLKack
tMSTCLK_LOWEXT tMSTCLK_LOWEXT

PCU_SMB_CLK

PCU_SMB_DATA

9.6.20 PCU - iLB - LPC AC Specification

Table 136. LPC AC Specifications (with loop back from ILB_LPC_CLK[0] to

ILB_LPC_CLK[1])

Sym Parameter Min Max Units Notes Fig

TCO ILB_LPC_AD[3:0], ILB_LPC_FRAME#, 2 14 ns 91

ILB_LPC_SERIRQ Valid Delay from
ILB_LPC_CLK[1] Rising
TEN_AD ILB_LPC_AD[3:0], ILB_LPC_FRAME#, 2 ns 92
ILB_LPC_SERIRQ Output Enable Delay
from ILB_LPC_CLK[1] Rising
TFD_AD ILB_LPC_AD[3:0] Float Delay from 28 ns 93
ILB_LPC_CLK[1] Rising
TSU_AD ILB_LPC_AD[3:0] Setup Time to 7 ns 94
ILB_LPC_CLK[1] Rising
THD_AD ILB_LPC_AD[3:0] Hold Time from 0 ns 94
ILB_LPC_CLK[1] Rising
Tlpc ILB_LPC_CLK[1:0] Duty Cycle 35 65 % 1

NOTE:
1. High time is measured from 0.75 x PCU_1P8_G3. Low time is measured from 0.35 x PCU_1P8_G3
2. The load capacitance used for the LPC timing parameters is 30 pF
3. VT is 1/2 of LPC IO voltage

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Figure 73. Valid Delay from Rising Clock Edge

Figure 74. Output Enable Delay

Figure 75. Float Delay

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 Electrical Specifications

Figure 76. Setup and Hold Times

9.6.21 SIO - I2C AC Specifications

9.6.21.1 I2C Fast/Standard Mode Electrical Specification

Table 137. I2C Fast/Standard Mode AC Specifications

Standard- Fast-Mode
Fast-Mode
Mode Plus
Symbol Parameter Units Notes Figure
Min. Max. Min. Max. Min. Max.

fSCL I2C_CLK clock frequency 0 100 0 400 0 1000 kHz

Hold time (repeated) START

condition. After this period, the first
tHD:STA 4.0 – 0.6 – 0.26 – µs 77
clock pulse is generated

tLOW LOW period of the I2C_CLK clock 4.7 – 1.3 – 0.5 – µs 77

2
tHIGH HIGH period of the I C_CLK clock 4.0 – 0.6 – 0.26 – µs 77

Set-up time for a repeated START

tSU:STA condition 4.7 – 0.6 – 0.26 – µs 77

tHD:DAT Data hold time: I2C-bus devices 0 – 0 – 0 – ns 77

tSU:DAT Data set-up time 250 – 100 – 50 – ns 1 77

Rise time of both I2C_DATA and 20 +

tr – 1000 0.1Cb(5) 300 – 120 ns 2, 3 77
I2C_CLK signals
Fall time of both I2C_DATA and
tf 1 300 1 300 1 120 ns 5 77
I2C_CLK signals

tSU:STO Set-up time for STOP condition 4.0 – 0.6 – 0.26 - µs 77

Bus free time between a STOP and

tBUF START condition 4.7 – 1.3 – 0.5 – µs

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Table 137. I2C Fast/Standard Mode AC Specifications

Standard- Fast-Mode
Fast-Mode
Mode Plus
Symbol Parameter Units Notes Figure
Min. Max. Min. Max. Min. Max.

Cb Capacitive load for each bus line – 130 – 130 - TBD pF

Noise margin at the LOW level for

VnL each connected device (including 0.1 – 0.1 VDD – 0.1 – V
VDD VDD
hysteresis)
Noise margin at the HIGH level for
0.2 0.2
VnH each connected device (including VDD – 0.2 VDD – VDD – V
hysteresis)

NOTES:
1. A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSU; DAT ³ 250 ns
must then be met. This will automatically be the case if the device does not stretch the LOW period of the I2C_CLK signal.
If such a device does stretch the LOW period of the I2C_CLK signal, it must output the next data bit to the I2C_DATA line
tr max + tSU; DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the I2C_CLK
line is released
2. Cb = total capacitance of one bus line in pF.
3. No Active current source PU on I2C_CLK signals. Rise time is based upon the Pull-up resistor mentioned in the Platform
Design Guide.
4. The maximum tHD;DAT could be 3.45 ms and 0.9 ms for Standard-mode and Fast-mode, but must be less than the
maximum of tVD;DAT or tVD;ACK by a transition time. This maximum must only be met if the device does not stretch the
LOW period (tLOW) of the I2C_CLK signal. If the clock stretches the I2C_CLK, the data must be valid by the set-up time
before it releases the clock.
5. Specification deviates from the minimum time compared to Industrial specification.

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190
I2C_DATA
0.7 VCC 70% 70% 70% 70%

0.3 VCC 30% 30% 30% 30%

tSU;DAT tr tBUF
tSP

tr tf tHD;STA
tLOW
tf
I2C_CLK
0.7 VCC 70% 70% 70% 70%

0.3 VCC 30% 30% 30% 30%

Figure 77. Definition of Timing for F/S-Mode Devices on I2C Bus

tHD;STA tSU;STA
tHD;DAT tSU;STO
s Sr P S
tHIGH

Datasheet
Electrical Specifications

Intel® Atom™ Processor E3800 Product Family

Electrical Specifications

9.6.21.2 I2C High Speed Mode Electrical Specification

Table 138. AC Specification for High Speed Mode I2C—Bus Devices

Cb = 100 pF
(max)
Symbol Parameter Units Figure
Min. Max.
2
fSCL I C_CLK clock frequency 0 1.7 MHz
tSU:STA Set-Up time for a repeated START 160 – ns
condition

tHD:STA Hold time (repeated) START 160 – ns

condition.

tLOW LOW period of the I2C_CLK clock 160 – ns

2
tHIGH HIGH period of the I C_CLK clock 60 – ns
tHD:DAT 2
Data hold time: I C-bus devices 0 – ns
tSU:DAT Data set-up time 10 – ns
tr CL Rise time of I2C_CLK signals 10 40 ns
tf CL Fall time of I2C_CLK signals 1 40 ns
trCL1 2
Rise time of I C_CLK signal after a 10 40 ns
repeated START condition and after
an acknowledge bit
tr DA Rise time of I2C_DATA signals 10 80 ns
tf DA Fall time of I2C_DATA signals 1 80 ns
tSU:STO Set-up time for STOP condition 160 – ns
VnL Noise margin at the LOW level for 0.1 VDD – V
each connected device (including
hysteresis)
VNH Noise margin at the HIGH level for 0.2 VDD – V
each connected device (including
hysteresis)

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192
Sr
trDA
Sr P
tfDA

70% 70% 70%

I2C_DATA 30% 30%

30%

tSU;STA tSU;STO
tHD;STA tHD;DAT
tSU;DAT

70% 70%
70% 70%

30% 30%
30%

tfCL
I2C_CLK
trCL
trCL1 (1)
trCL1
tLOW tLOW
tHIGH tHIGH (1)

= MCS current source pull-up

Figure 78. Definition of Timing for High Speed-Mode Devices on I2C Bus

= Rp resistor pull-up

(1) First rising edge of the SCLH signal after Sr and after each acknowledge bit.

Datasheet
Electrical Specifications

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Electrical Specifications

9.6.22 SIO - UART AC Specification

Table 139. UART AC Specification

Symbol Parameter Min. Max. Unit Notes

TRISE Maximum Rise Time 2.5 5 ns 1, 2

TFALL Maximum Fall Time 2.5 5 ns 1, 2
TUARTFIL UART Sampling Filter 20 ns 3
Period

NOTES:
1. Based on total trace length of 1-4”, Total maximum, capacitance of 27 pF and board impedance of 30–75Ω.
2. Measured from 10–90%.
3. Each bit including start and stop bit is sampled three times at center of a bit at an interval of 20 ns
(minimum). If three sampled values do not agree, then UART noise error is generated.

Figure 79. UART Timing Diagram

T BAUD
UART_TX

Start Bit Data and Parity Bit Stop Bit

UART_RX

T UARTFILL

9.6.23 JTAG AC Specification

Table 140. JTAG AC Specification

T# Parameter Min Max Unit Figure Notes

TP:TAP_TCK Period 15 ns 66 MHz

TCL:TAP_TCK Clock Low Time 0.4 * TJC ns
TCH:TAP_TCK Clock High Time 0.4 * TJC ns
TSU:TAP_TDI, TAP_TMS Setup Time 11 ns 81
TH: TAP_TDI, TAP_TMS Hold Time 5 ns 81
TCO: TAP_TCK falling to TAP_TDO 11 ns 81
output valid
TCO: TAP_TCK falling to TAP_TDO 11 ns
output high impedance
T18: TAP_TRST# assert time 2 ns 82

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 Electrical Specifications

NOTES:
1. Unless otherwise noted, all specifications in this table apply to all SoC frequencies.
2. Not 100% tested. Specified by design characterization.
3. It is recommended that TAP_TMS be asserted while TAP_TRST# is being deasserted.
4. Board JTAG signal skew max = ±500 ps.

Figure 80. JTAG Timing Diagram

Table 141. Boundary Scan AC Specification

T# Parameter Min Max Unit Notes

Boundary scan all non test output/float 0.5 15 ns Referenced to the

delay falling edge of TCK
Boundary scan all non test input setup 10 ns Referenced to the
falling edge of TCK
Boundary scan all non test input hold 13 µs Referenced to the
falling edge of TCK

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Figure 81. TAP Valid Delay Timing Waveform

V
TCK
Tx Ts Th

V Valid
Signal

TJSU = TDI, TMS Setup Time

TJH = TDI, TMS Hold Time
V = 0.5 * VCCP

Please refer to Table 81, Table 82, Table 83 for TAP Signal Group DC specifications and
Table 140 for TAP Signal Group AC specifications.

Figure 82. Test Reset (TAP_TRST#), Async GTL Input and PROCHOT# Timing Waveform

Tq

T = T38 (PROCHOT# Pulse Width)

q T18 (TAP_TRST# Pulse Width)

9.6.24 General AC Timing Diagrams

Note that the measurement of the differential waveform according to these diagrams
would have to be made directly at the load at the end of the line. In a real system, this
is not possible because the end of the line is at the input pad of the SoC silicon.

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 Electrical Specifications

Figure 83. Clock Cycle Time

Figure 84. Clock Timing

Period
High Time
2.0V
0.8V
Low Time
Fall Time Rise Time

Figure 85. Valid Delay from Rising Clock Edge

Clock 1.5V

Valid Delay

Output VT

Figure 86. Setup and Hold Times

Clock 1.5V

Setup Time Hold Time

Input VT VT

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Figure 87. Float Delay

Input VT

Float
Delay

Output

Figure 88. Pulse Width

Pulse Width

VT VT

Figure 89. Output Enable Delay

Clock 1.5V

Output
Enable
Delay

Output VT

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 Electrical Specifications

Figure 90. Differential Clock Waveform (Measured Single-ended)

Figure 91. Differential Clock Waveform (Using Differential Probe for Measurement)

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Ballout and Package Information

10 Ballout and Package

Information
The SoC comes in a 25 mm X 27 mm Flip-Chip Ball Grid Array (FCBGA) package and
consists of a silicon die mounted face down on an organic substrate populated with
1170 solder balls on the bottom side. Capacitors may be placed in the area surrounding
the die. Because the die-side capacitors are electrically conductive, and only slightly
shorter than the die height, care should be taken to avoid contacting the capacitors
with electrically conductive materials. Doing so may short the capacitors and possibly
damage the device or render it inactive.

The use of an insulating material between the capacitors and any thermal solution
should be considered to prevent capacitor shorting. An exclusion, or keep out zone,
surrounds the die and capacitors, and identifies the contact area for the package. Care
should be taken to avoid contact with the package inside this area.

Refer to the Bay Trail SoC Thermal and Mechanical Design Guide for details on package
mechanical dimensions and tolerance, as well as other key package attributes.

10.1 SoC Attributes

• Package parameters: 25 mm X 27 mm
• Ball Count:1170
All Units: mm

Tolerances if not specified:

• .X: ± 0.1
• .XX: ± 0.05
• Angles: ± 1.0 degrees

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 Ballout and Package Information

10.2 Package Diagrams

Figure 92. Package Mechanical Drawing

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Ballout and Package Information

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Datasheet 201
10.3 Ball Name and Function by Location
Many I/O’s are configurable GPIO’s. These I/O’s are multiplexed with other signals in the ball list. This table matches names and locations of every
ball with all possible multiplexed signals (denoted as GPIO Functions). Configurable GPIO’s default to function 0 during power on and may not match
the ball name. BIOS (platform firmware) is responsible for enabling the platform specific configuration. Please see your BIOS vendor for details.

Table 142. Ball Listing by Location with GPIO Muxed Functions (Sheet 1 of 47)
Location Ball Name X-Location Y-Location GPIO F0 GPIO F1 GPIO F2 GPIO F3 GPIO F6

A3 VSS 11951.46 -11814.05 - - - - -

A5 VSS 11170.41 -11814.05 - - - - -

A6 VSS 10446.51 -11814.05 - - - - -

A7 USB_HSIC_RCOMP 9748.01 -11814.05 - - - - -

A9 ILB_RTC_X2 8835.9 -11814.05 - - - - -

A11 VSS 7774.43 -11814.05 - - - - -

A13 GPIO_S5[09] 6802.63 -11814.05 GPIO_S5[09] RESERVED RESERVED RESERVED RESERVED

A15 VSS 5830.82 -11814.05 - - - - -

A17 GPIO_S5[03] 4859.02 -11814.05 GPIO_S5[03] RESERVED RESERVED RESERVED PMC_WAKE_PCIE[3]#

A19 VSS 3887.22 -11814.05 - - - - -

A21 PCU_SPI_MOSI 2915.41 -11814.05 PCU_SPI_MOSI - - - -

A23 VSS 1943.61 -11814.05 - - - - -

A25 SVID_DATA 971.8 -11814.05 SVID_DATA - - - -

A27 VSS 0 -11814.05 - - - - -

A29 RESERVED -971.8 -11814.05 RESERVED RESERVED - - -

A31 VSS -1943.61 -11814.05 - - - - -

A33 DRAM0_DQ[13] -2915.41 -11814.05 - - - - -

A35 VSS -3887.22 -11814.05 - - - - -

A37 DRAM0_DQ[11] -4859.02 -11814.05 - - - - -

A39 VSS -5830.82 -11814.05 - - - - -

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202 Datasheet
 Table 142. Ball Listing by Location with GPIO Muxed Functions (Sheet 2 of 47)
Location Ball Name X-Location Y-Location GPIO F0 GPIO F1 GPIO F2 GPIO F3 GPIO F6

A41 DRAM0_DQ[24] -6802.63 -11814.05 - - - - -

A43 VSS -7774.43 -11814.05 - - - - -

A45 DRAM0_DQ[26] -8746.24 -11814.05 - - - - -

A47 VSS -9620.5 -11814.05 - - - - -

A48 DRAM_VDD_S4 -10293.6 -11814.05 - - - - -

A49 VSS -10992.1 -11814.05 - - - - -

A51 VSS -11773.15 -11814.05 - - - - -

A52 VSS -12382.75 -11814.05 - - - - -

B2 VSS 12382.75 -11382.76 - - - - -

B4 USB_HSIC0_DATA 11631.68 -11237.72 - - - - -

B5 USB_HSIC0_STROBE 11038.33 -11222.48 - - - - -

B6 UNCORE_V1P0_G3 10444.99 -11220.7 - - - - -

B7 PMC_CORE_PWROK 9851.64 -11229.59 - - - - -

B8 ILB_RTC_EXTPAD 9258.3 -11224.26 - - - - -

B10 PMC_RSMRST# 8260.33 -11428.98 - - - - -

B12 USB_ULPI_REFCLK 7288.53 -11428.98 GPIO_S5[43] USB_ULPI_REFCLK RESERVED RESERVED -

B14 GPIO_S5[06] 6316.73 -11428.98 GPIO_S5[06] PMC_SUSCLK[2] RESERVED RESERVED RESERVED

B16 GPIO_S5[01] 5344.92 -11428.98 GPIO_S5[01] RESERVED RESERVED RESERVED PMC_WAKE_PCIE[1]#

B18 GPIO_S5[00] 4373.12 -11428.98 GPIO_S5[00] RESERVED - - -

B20 USB_OC[1]# 3401.31 -11428.98 USB_OC[1]# GPIO_S5[20] - - -

B22 PCU_SPI_MISO 2429.51 -11428.98 PCU_SPI_MISO - - - -

B24 SVID_ALERT# 1457.71 -11428.98 SVID_ALERT# - - - -

B26 DDI0_BKLTCTL 485.9 -11428.98 RESERVED RESERVED DDI0_BKLTCTL - -

B28 DDI0_VDDEN -485.9 -11428.98 RESERVED RESERVED DDI0_VDDEN - -

B30 RESERVED -1457.71 -11428.98 RESERVED RESERVED - - -

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 Table 142. Ball Listing by Location with GPIO Muxed Functions (Sheet 3 of 47)
Location Ball Name X-Location Y-Location GPIO F0 GPIO F1 GPIO F2 GPIO F3 GPIO F6

B32 DRAM0_DQ[08] -2429.51 -11428.98 - - - - -

B34 DRAM0_DQSN[1] -3401.31 -11428.98 - - - - -

B36 DRAM0_DM[1] -4373.12 -11428.98 - - - - -

B38 DRAM0_DQ[15] -5344.92 -11428.98 - - - - -

B40 DRAM0_DQ[29] -6316.73 -11428.98 - - - - -

B42 DRAM0_DM[3] -7288.53 -11428.98 - - - - -

B44 DRAM0_DQSP[3] -8260.33 -11428.98 - - - - -

B46 DRAM0_DQ[27] -9258.3 -11224.26 - - - - -

B47 DRAM0_DQ[31] -9851.64 -11229.59 - - - - -

B48 DRAM0_DQ[30] -10444.99 -11220.7 - - - - -

B49 DRAM0_MA[14] -11038.33 -11222.48 - - - - -

B50 DRAM0_MA[15] -11631.68 -11237.72 - - - - -

B52 VSS -12225.02 -11225.02 - - - - -

B53 VSS -12814.05 -11382.76 - - - - -

C1 VSS 12814.05 -10951.46 - - - - -

C3 USB3_V1P0_G3 11644.38 -10644.38 - - - - -

C5 UNCORE_V1P0_G3 10579.86 -10642.85 - - - - -

C7 USB_RCOMPI 9553.19 -10709.15 - - - - -

C9 ILB_RTC_X1 8697.98 -11028.17 - - - - -

C11 ILB_RTC_TEST# 7774.43 -11070.59 - - - - -

C12 ILB_RTC_RST# 7288.53 -10729.98 - - - - -

C13 GPIO_S5[08] 6802.63 -11070.59 GPIO_S5[08] RESERVED RESERVED RESERVED RESERVED

C14 VSS 6316.73 -10729.98 - - - - -

C15 GPIO_S5[07] 5830.82 -11070.59 GPIO_S5[07] PMC_SUSCLK[3] RESERVED RESERVED RESERVED

C16 GPIO_S5[05] 5344.92 -10729.98 GPIO_S5[05] PMC_SUSCLK[1] RESERVED RESERVED RESERVED

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204 Datasheet
 Table 142. Ball Listing by Location with GPIO Muxed Functions (Sheet 4 of 47)
Location Ball Name X-Location Y-Location GPIO F0 GPIO F1 GPIO F2 GPIO F3 GPIO F6

C17 GPIO_S5[04] 4859.02 -11070.59 GPIO_S5[04] RESERVED RESERVED RESERVED RESERVED

C18 GPIO_S5[02] 4373.12 -10729.98 GPIO_S5[02] RESERVED RESERVED RESERVED PMC_WAKE_PCIE[2]#

C19 GPIO_S5[10] 3887.22 -11070.59 GPIO_S5[10] RESERVED RESERVED RESERVED -

C20 USB_OC[0]# 3401.31 -10729.98 USB_OC[0]# GPIO_S5[19] - - -

C21 PCU_SPI_CS[1]# 2915.41 -11070.59 PCU_SPI_CS[1]# GPIO_S5[21] - - -

C22 PCU_SPI_CLK 2429.51 -10729.98 PCU_SPI_CLK - - - -

C23 PCU_SPI_CS[0]# 1943.61 -11070.59 PCU_SPI_CS[0]# - - - -

C24 PROCHOT# 1457.71 -10729.98 PROCHOT# - - - -

C25 SVID_CLK 971.8 -11070.59 SVID_CLK - - - -

C26 DDI0_DDCDATA 479.81 -10715.24 RESERVED RESERVED DDI0_DDCDATA - -

C27 DDI0_BKLTEN 0 -11070.59 RESERVED RESERVED DDI0_BKLTEN - -

C28 DDI0_DDCCLK -479.81 -10715.24 RESERVED RESERVED DDI0_DDCCLK - -

C29 RESERVED -971.8 -11070.59 RESERVED RESERVED - - -

C30 RESERVED -1457.71 -10729.98 MDSI_C_TE - - - -

C31 VSS -1943.61 -11070.59 - - - - -

C32 DRAM0_DQ[09] -2429.51 -10729.98 - - - - -

C33 DRAM0_DQ[12] -2915.41 -11070.59 - - - - -

C34 VSS -3401.31 -10729.98 - - - - -

C35 DRAM0_DQSP[1] -3887.22 -11070.59 - - - - -

C36 DRAM0_DQ[10] -4373.12 -10729.98 - - - - -

C37 DRAM0_DQ[14] -4859.02 -11070.59 - - - - -

C38 DRAM0_DQ[21] -5344.92 -10729.98 - - - - -

C39 VSS -5830.82 -11070.59 - - - - -

C40 DRAM0_DQ[28] -6316.73 -10729.98 - - - - -

C41 DRAM0_DQ[25] -6802.63 -11070.59 - - - - -

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 Table 142. Ball Listing by Location with GPIO Muxed Functions (Sheet 5 of 47)
Location Ball Name X-Location Y-Location GPIO F0 GPIO F1 GPIO F2 GPIO F3 GPIO F6

C42 VSS -7288.53 -10729.98 - - - - -

C43 DRAM0_DQSN[3] -7774.43 -11070.59 - - - - -

C45 VSS -8697.98 -11028.17 - - - - -

C47 DRAM0_CKE[0] -9553.19 -10709.15 - - - - -

C49 VSS -10579.86 -10642.85 - - - - -

C51 DRAM_VDD_S4 -11644.38 -10644.38 - - - - -

C53 VSS -12814.05 -10773.16 - - - - -

D2 USB_HSIC1_STROBE 12237.72 -10631.68 - - - - -

D4 USB3_RXP[0] 11162.79 -10162.79 - - - - -

D6 USB_RCOMPO 10112.76 -10238.49 - - - - -

D10 ICLK_USB_TERM[1] 8307.32 -10168.38 - - - - -

D12 VSS 7316.72 -10137.14 - - - - -

D14 TAP_TCK 6326.12 -10136.63 TAP_TCK - - - -

D16 VSS 5335.52 -10136.63 - - - - -

D18 TAP_PRDY# 4388.36 -10136.63 TAP_PRDY# - - - -

D20 PMC_ACPRESENT 3386.07 -10136.63 PMC_ACPRESENT - - - -

D22 PMC_SLP_S3# 2438.91 -10136.63 PMC_SLP_S3# - - - -

D24 VSS 1448.31 -10136.63 - - - - -

D26 PMC_SUSPWRDNACK 462.79 -9994.65 PMC_SUSPWRDNACK GPIO_S5[11] - - -

D27 DDI0_HPD 0 -10365.99 RESERVED RESERVED DDI0_HPD - -

D28 MCSI_GPIO[02] -462.79 -9994.65 RESERVED MCSI_GPIO[02] RESERVED - -

D30 VSS -1448.31 -10136.63 - - - - -

D32 MCSI_GPIO[11] -2438.91 -10136.63 RESERVED MCSI_GPIO[11] - - -

D34 MCSI_GPIO[05] -3386.07 -10136.63 RESERVED MCSI_GPIO[05] RESERVED - -

D36 VSS -4388.36 -10136.63 - - - - -

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 Table 142. Ball Listing by Location with GPIO Muxed Functions (Sheet 6 of 47)
Location Ball Name X-Location Y-Location GPIO F0 GPIO F1 GPIO F2 GPIO F3 GPIO F6

D38 VSS -5335.52 -10136.63 - - - - -

D40 DRAM0_DQSP[2] -6326.12 -10136.63 - - - - -

D42 DRAM0_DQ[23] -7316.72 -10137.14 - - - - -

D44 DRAM_VDD_S4 -8307.32 -10168.38 - - - - -

D48 RESERVED -10112.76 -10238.49 - - - - -

D50 DRAM0_MA[07] -11162.79 -10162.79 - - - - -

D52 DRAM0_BS[2] -12237.72 -10631.68 - - - - -

E1 VSS 12814.05 -10170.41 - - - - -

E2 USB_HSIC1_DATA 12222.48 -10038.33 - - - - -

E3 USB3_RXN[0] 11642.85 -9579.86 - - - - -

E8 VSS 9320.02 -9747 - - - - -

E19 VSS 3887.22 -9818.88 - - - - -

E35 VSS -3887.22 -9818.88 - - - - -

E46 RESERVED -9320.02 -9747 - - - - -

E51 DRAM0_MA[11] -11642.85 -9579.86 - - - - -

E52 DRAM0_MA[09] -12222.48 -10038.33 - - - - -

E53 VSS -12814.05 -9992.11 - - - - -

F1 RESERVED 12814.05 -9446.51 - - - - -

F2 VSS 12220.7 -9444.99 - - - - -

F5 VSS 10565.13 -9301.73 - - - - -

F7 VSS 9712.2 -9301.73 - - - - -

F10 ICLK_USB_TERM[0] 8307.32 -9457.18 - - - - -

F12 TAP_TDI 7316.72 -9463.28 TAP_TDI - - - -

F14 TAP_TMS 6326.12 -9463.28 TAP_TMS - - - -

F16 TAP_PREQ# 5335.52 -9463.28 TAP_PREQ# - - - -

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 Table 142. Ball Listing by Location with GPIO Muxed Functions (Sheet 7 of 47)
Location Ball Name X-Location Y-Location GPIO F0 GPIO F1 GPIO F2 GPIO F3 GPIO F6

F18 GPIO_S5[13] 4362.2 -9463.28 RESERVED GPIO_S5[13] - - -

F19 VSS 3887.22 -9107.68 - - - - -

F20 PMC_PLTRST# 3412.24 -9463.28 PMC_PLTRST# - - - -

F22 PMC_SLP_S4# 2438.91 -9463.28 PMC_SLP_S4# - - - -

F24 VSS 1448.31 -9463.28 - - - - -

F26 PMC_WAKE_PCIE[0]# 525.02 -9404.35 PMC_WAKE_PCIE[0]# GPIO_S5[15] - - -

F27 VSS 0 -9107.68 - - - - -

F28 MCSI_GPIO[07] -525.02 -9404.35 RESERVED MCSI_GPIO[07] RESERVED - -

F30 VSS -1448.31 -9463.28 - - - - -

F32 MCSI_GPIO[06] -2438.91 -9463.28 RESERVED MCSI_GPIO[06] RESERVED - -

F34 MCSI_GPIO[00] -3412.24 -9463.28 RESERVED MCSI_GPIO[00] RESERVED - -

F35 VSS -3887.22 -9107.68 - - - - -

F36 DRAM0_DQ[16] -4362.2 -9463.28 - - - - -

F38 DRAM0_DM[2] -5335.52 -9463.28 - - - - -

F40 DRAM0_DQSN[2] -6326.12 -9463.28 - - - - -

F42 DRAM0_DQ[18] -7316.72 -9463.28 - - - - -

F44 DRAM0_CKE[2] -8307.32 -9457.18 - - - - -

F47 DRAM0_MA[12] -9712.2 -9301.73 - - - - -

F49 DRAM_VDD_S4 -10565.13 -9301.73 - - - - -

F52 DRAM_VDD_S4 -12220.7 -9444.99 - - - - -

F53 DRAM_VDD_S4 -12814.05 -9293.61 - - - - -

G1 USB3DEV_V1P0_S3 12814.05 -8679.18 - - - - -

G2 USB_ULPI_CLK 12246.36 -8852.15 GPIO_S5[31] USB_ULPI_CLK RESERVED RESERVED -

G10 VSS 8307.32 -8763.76 - - - - -

G12 TAP_TRST# 7316.72 -8752.08 TAP_TRST# - - - -

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208 Datasheet
 Table 142. Ball Listing by Location with GPIO Muxed Functions (Sheet 8 of 47)
Location Ball Name X-Location Y-Location GPIO F0 GPIO F1 GPIO F2 GPIO F3 GPIO F6

G14 USB_DN[1] 6326.12 -8752.08 - - - - -

G16 TAP_TDO 5335.52 -8752.08 TAP_TDO - - - -

G18 PMC_SUS_STAT# 4362.2 -8752.08 PMC_SUS_STAT# GPIO_S5[18] - - -

G20 VSS 3412.24 -8752.08 - - - - -

G22 VSS 2438.91 -8752.08 - - - - -

G24 PMC_SUSCLK[0] 1448.31 -8752.08 PMC_SUSCLK[0] GPIO_S5[12] - - -

G26 VSS 474.98 -8752.08 - - - - -

G28 VSS -474.98 -8752.08 - - - - -

G30 DDI1_DDCCLK -1448.31 -8752.08 RESERVED RESERVED DDI1_DDCCLK - -

G32 VSS -2438.91 -8752.08 - - - - -

G34 VSS -3412.24 -8752.08 - - - - -

G36 DRAM0_DM[0] -4362.2 -8752.08 - - - - -

G38 DRAM0_DQ[17] -5335.52 -8752.08 - - - - -

G40 DRAM0_DQ[20] -6326.12 -8752.08 - - - - -

G42 VSS -7316.72 -8752.08 - - - - -

G44 DRAM0_DQ[22] -8307.32 -8763.76 - - - - -

G52 DRAM0_MA[08] -12246.36 -8852.15 - - - - -

G53 DRAM0_MA[05] -12814.05 -8620.51 - - - - -

H3 USB_ULPI_STP 11928.86 -8350.76 GPIO_S5[42] USB_ULPI_STP RESERVED RESERVED -

H4 RESERVED 11257.79 -8307.32 - - - - -

H5 RESERVED 10546.59 -8307.32 - - - - -

H7 RESERVED 9835.39 -8307.32 - - - - -

H8 RESERVED 9124.19 -8307.32 - - - - -

H10 USB_DN[3] 8307.32 -8170.42 - - - - -

H19 VSS 3887.22 -8396.48 - - - - -

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 Table 142. Ball Listing by Location with GPIO Muxed Functions (Sheet 9 of 47)
Location Ball Name X-Location Y-Location GPIO F0 GPIO F1 GPIO F2 GPIO F3 GPIO F6

H27 VSS 0 -8396.48 - - - - -

H35 VSS -3887.22 -8396.48 - - - - -

H44 DRAM0_MA[03] -8307.32 -8170.42 - - - - -

H46 DRAM_VDD_S4 -9124.19 -8307.32 - - - - -

H47 DRAM0_MA[01] -9835.39 -8307.32 - - - - -

H49 DRAM0_MA[06] -10546.59 -8307.32 - - - - -

H50 DRAM0_MA[04] -11257.79 -8307.32 - - - - -

H51 DRAM0_WE# -11928.86 -8350.76 - - - - -

J1 VSS 12814.05 -7815.58 - - - - -

J3 USB_ULPI_DIR 12070.59 -7774.43 GPIO_S5[40] USB_ULPI_DIR RESERVED RESERVED -

J12 USB_DN[2] 7316.72 -8040.88 - - - - -

J14 USB_DP[1] 6326.12 -8040.88 - - - - -

J16 VSS 5335.52 -8040.88 - - - - -

J18 GPIO_S5[25] 4362.2 -8040.88 GPIO_S5[25] RESERVED RESERVED RESERVED RESERVED

J19 VSS 3887.22 -7685.28 - - - - -

J20 USB_ULPI_RST# 3412.24 -8040.88 RESERVED GPIO_S5[14] USB_ULPI_RST# - -

J22 VSS 2438.91 -8040.88 - - - - -

J24 GPIO_S5[17] 1448.31 -8040.88 RESERVED GPIO_S5[17] - - -

J26 PMC_PWRBTN# 474.98 -8040.88 PMC_PWRBTN# GPIO_S5[16] - - -

J27 VSS 0 -7685.28 - - - - -

J28 MCSI_GPIO[03] -474.98 -8040.88 RESERVED MCSI_GPIO[03] RESERVED - -

J30 DDI1_BKLTEN -1448.31 -8040.88 RESERVED RESERVED DDI1_BKLTEN - -

J32 VSS -2438.91 -8040.88 - - - - -

J34 MCSI_GPIO[09] -3412.24 -8040.88 RESERVED MCSI_GPIO[09] - - -

J35 VSS -3887.22 -7685.28 - - - - -

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 Table 142. Ball Listing by Location with GPIO Muxed Functions (Sheet 10 of 47)
Location Ball Name X-Location Y-Location GPIO F0 GPIO F1 GPIO F2 GPIO F3 GPIO F6

J36 DRAM0_DQ[01] -4362.2 -8040.88 - - - - -

J38 DRAM0_DQSP[0] -5335.52 -8040.88 - - - - -

J40 VSS -6326.12 -8040.88 - - - - -

J42 DRAM0_DQ[19] -7316.72 -8040.88 - - - - -

J51 DRAM0_MA[13] -12070.59 -7774.43 - - - - -

J53 VSS -12814.05 -7774.43 - - - - -

K2 USB_ULPI_DATA[2] 12428.98 -7288.53 GPIO_S5[34] USB_ULPI_DATA[2] RESERVED RESERVED -

K3 USB_ULPI_DATA[3] 11729.97 -7288.53 GPIO_S5[35] USB_ULPI_DATA[3] RESERVED RESERVED -

K4 VSS 11137.14 -7316.72 - - - - -

K6 USB3_TXP[0] 10463.28 -7316.72 - - - - -

K7 USB3_TXN[0] 9752.08 -7316.72 - - - - -

K9 VSS 9040.88 -7316.72 - - - - -

K10 USB_DP[3] 8329.68 -7316.72 - - - - -

K12 USB_DP[2] 7316.72 -7339.58 - - - - -

K14 VSS 6326.12 -7329.68 - - - - -

K16 USB_DN[0] 5335.52 -7329.68 - - - - -

K18 GPIO_S5[27] 4362.2 -7329.68 GPIO_S5[27] RESERVED RESERVED RESERVED RESERVED

K20 GPIO_S5[28] 3412.24 -7329.68 GPIO_S5[28] RESERVED RESERVED RESERVED RESERVED

K22 VSS 2438.91 -7329.68 - - - - -

K24 GPIO_S5[22] 1448.31 -7329.68 GPIO_S5[22] RESERVED RESERVED RESERVED RESERVED

K26 PMC_BATLOW# 474.98 -7329.68 PMC_BATLOW# - - - -

K28 MCSI_GPIO[08] -474.98 -7329.68 RESERVED MCSI_GPIO[08] RESERVED - -

K30 DDI1_HPD -1448.31 -7329.68 RESERVED RESERVED DDI1_HPD - -

K32 VSS -2438.91 -7329.68 - - - - -

K34 MCSI_GPIO[04] -3412.24 -7329.68 RESERVED MCSI_GPIO[04] RESERVED - -

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 Table 142. Ball Listing by Location with GPIO Muxed Functions (Sheet 11 of 47)
Location Ball Name X-Location Y-Location GPIO F0 GPIO F1 GPIO F2 GPIO F3 GPIO F6

K36 VSS -4362.2 -7329.68 - - - - -

K38 DRAM0_DQSN[0] -5335.52 -7329.68 - - - - -

K40 DRAM0_DQ[06] -6326.12 -7329.68 - - - - -

K42 DRAM0_DQ[07] -7316.72 -7339.58 - - - - -

K44 DRAM0_BS[1] -8329.68 -7316.72 - - - - -

K45 DRAM0_MA[00] -9040.88 -7316.72 - - - - -

K47 DRAM0_BS[0] -9752.08 -7316.72 - - - - -

K48 DRAM0_MA[10] -10463.28 -7316.72 - - - - -

K50 VSS -11137.14 -7316.72 - - - - -

K51 DRAM0_DQ[33] -11729.97 -7288.53 - - - - -

K52 DRAM0_DQ[32] -12428.98 -7288.53 - - - - -

L1 USB_ULPI_DATA[1] 12814.05 -6802.63 GPIO_S5[33] USB_ULPI_DATA[1] RESERVED RESERVED -

L3 USB_ULPI_DATA[7] 12070.59 -6802.63 GPIO_S5[39] USB_ULPI_DATA[7] RESERVED RESERVED -

L13 VSS 6750.56 -6914.9 - - - - -

L19 VSS 3887.22 -6974.08 - - - - -

L27 VSS 0 -6974.08 - - - - -

L35 VSS -3887.22 -6974.08 - - - - -

L41 DRAM0_MA[02] -6750.56 -6914.9 - - - - -

L51 DRAM0_DQ[36] -12070.59 -6802.63 - - - - -

L53 DRAM0_DQ[37] -12814.05 -6802.63 - - - - -

M2 USB_ULPI_DATA[4] 12428.98 -6316.73 GPIO_S5[36] USB_ULPI_DATA[4] RESERVED RESERVED -

M3 USB_ULPI_DATA[0] 11729.97 -6316.73 GPIO_S5[32] USB_ULPI_DATA[0] RESERVED RESERVED -

M4 USB3DEV_TXP[0] 11136.63 -6326.12 - - - - -

M6 USB3DEV_TXN[0] 10463.28 -6326.12 - - - - -

M7 USB3DEV_REXT[0] 9752.08 -6326.12 - - - - -

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212 Datasheet
 Table 142. Ball Listing by Location with GPIO Muxed Functions (Sheet 12 of 47)
Location Ball Name X-Location Y-Location GPIO F0 GPIO F1 GPIO F2 GPIO F3 GPIO F6

M9 RESERVED 9040.88 -6326.12 - - - - -

M10 RESERVED 8329.68 -6326.12 - - - - -

M12 USB3_REXT[0] 7618.48 -6326.12 - - - - -

M13 USB_PLL_MON 6907.28 -6326.12 - - - - -

M14 USB_V1P0_S3 6326.12 -6446.01 - - - - -

M16 USB_DP[0] 5335.52 -6618.48 - - - - -

M18 GPIO_S5[26] 4362.2 -6618.48 GPIO_S5[26] RESERVED RESERVED RESERVED RESERVED

M19 VSS 3887.22 -6262.88 - - - - -

M20 GPIO_S5[24] 3412.24 -6618.48 GPIO_S5[24] RESERVED RESERVED RESERVED RESERVED

M22 GPIO_S5[29] 2438.91 -6618.48 GPIO_S5[29] RESERVED RESERVED RESERVED RESERVED

M24 GPIO_S5[30] 1448.31 -6618.48 GPIO_S5[30] RESERVED RESERVED RESERVED RESERVED

M26 VSS 474.98 -6618.48 - - - - -

M27 VSS 0 -6262.88 - - - - -

M28 VSS -474.98 -6618.48 - - - - -

M30 DDI1_BKLTCTL -1448.31 -6618.48 RESERVED RESERVED DDI1_BKLTCTL - -

M32 MCSI_GPIO[01] -2438.91 -6618.48 RESERVED MCSI_GPIO[01] RESERVED - -

M34 VSS -3412.24 -6618.48 - - - - -

M35 VSS -3887.22 -6262.88 - - - - -

M36 DRAM0_DQ[00] -4362.2 -6618.48 - - - - -

M38 VSS -5335.52 -6618.48 - - - - -

M40 DRAM0_DQ[03] -6326.12 -6446.01 - - - - -

M41 DRAM_VDD_S4 -6907.28 -6326.12 - - - - -

M42 DRAM_VDD_S4 -7618.48 -6326.12 - - - - -

M44 DRAM0_CAS# -8329.68 -6326.12 - - - - -

M45 DRAM0_RAS# -9040.88 -6326.12 - - - - -

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 Table 142. Ball Listing by Location with GPIO Muxed Functions (Sheet 13 of 47)
Location Ball Name X-Location Y-Location GPIO F0 GPIO F1 GPIO F2 GPIO F3 GPIO F6

M47 VSS -9752.08 -6326.12 - - - - -

M48 DRAM0_CKN[0] -10463.28 -6326.12 - - - - -

M50 DRAM0_CKP[0] -11136.63 -6326.12 - - - - -

M51 VSS -11729.97 -6316.73 - - - - -

M52 DRAM0_DQSN[4] -12428.98 -6316.73 - - - - -

N1 VSS 12814.05 -5830.82 - - - - -

N3 USB_ULPI_DATA[5] 12070.59 -5830.82 GPIO_S5[37] USB_ULPI_DATA[5] RESERVED RESERVED -

N16 VSS 5335.52 -5907.28 - - - - -

N18 USB_V3P3_G3 4362.2 -5907.28 - - - - -

N20 USB_V1P8_G3 3412.24 -5907.28 - - - - -

N22 PCU_V3P3_G3 2438.91 -5907.28 - - - - -

N24 GPIO_S5[23] 1448.31 -5907.28 GPIO_S5[23] RESERVED RESERVED RESERVED RESERVED

N26 GPIO_RCOMP 474.98 -5907.28 - - - - -

N28 CORE_VSS_SENSE -474.98 -5907.28 - - - - -

N30 DDI1_VDDEN -1448.31 -5907.28 RESERVED RESERVED DDI1_VDDEN - -

N32 MCSI_GPIO[10] -2438.91 -5907.28 RESERVED MCSI_GPIO[10] - - -

N34 RESERVED -3412.24 -5907.28 - - - - -

N36 DRAM0_DQ[05] -4362.2 -5907.28 - - - - -

N38 VSS -5335.52 -5907.28 - - - - -

N51 VSS -12070.59 -5830.82 - - - - -

N53 DRAM0_DQSP[4] -12814.05 -5830.82 - - - - -

P2 USB_ULPI_DATA[6] 12428.98 -5344.92 GPIO_S5[38] USB_ULPI_DATA[6] RESERVED RESERVED -

P3 USB_ULPI_NXT 11729.97 -5344.92 GPIO_S5[41] USB_ULPI_NXT RESERVED RESERVED -

P4 VSS 11136.63 -5335.52 - - - - -

P6 RESERVED 10463.28 -5335.52 - - - - -

Intel® Atom™ Processor E3800 Product Family

214 Datasheet
 Table 142. Ball Listing by Location with GPIO Muxed Functions (Sheet 14 of 47)
Location Ball Name X-Location Y-Location GPIO F0 GPIO F1 GPIO F2 GPIO F3 GPIO F6

P7 RESERVED 9752.08 -5335.52 - - - - -

P9 VSS 9040.88 -5335.52 - - - - -

P10 USB3DEV_RXP[0] 8329.68 -5335.52 - - - - -

P12 USB3DEV_RXN[0] 7618.48 -5335.52 - - - - -

P13 VSS 6907.28 -5335.52 - - - - -

P14 MCSI_RCOMP 6304.79 -5335.52 - - - - -

P16 VSS 5335.52 -5196.08 - - - - -

P18 USB_V3P3_G3 4362.2 -5196.08 - - - - -

P19 VSS 3887.22 -5551.68 - - - - -

P20 VSS 3412.24 -5196.08 - - - - -

P22 RTC_VCC 2438.91 -5196.08 - - - - -

P24 VSS 1448.31 -5196.08 - - - - -

P26 CORE_VCC_S3 474.98 -5196.08 - - - - -

P27 CORE_VCC_S3 0 -5551.68 - - - - -

P28 CORE_VCC_SENSE -474.98 -5196.08 - - - - -

P30 DDI1_DDCDATA -1448.31 -5196.08 RESERVED RESERVED DDI1_DDCDATA - -

P32 VSS -2438.91 -5196.08 - - - - -

P34 RESERVED -3412.24 -5196.08 - - - - -

P35 VSS -3887.22 -5551.68 - - - - -

P36 DRAM0_DQ[04] -4362.2 -5196.08 - - - - -

P38 VSS -5335.52 -5196.08 - - - - -

P40 DRAM0_DQ[02] -6304.79 -5335.52 - - - - -

P41 DRAM0_DRAMRST# -6907.28 -5335.52 - - - - -

P42 DRAM0_ODT[2] -7618.48 -5335.52 - - - - -

P44 DRAM0_CS[0]# -8329.68 -5335.52 - - - - -

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 Table 142. Ball Listing by Location with GPIO Muxed Functions (Sheet 15 of 47)
Location Ball Name X-Location Y-Location GPIO F0 GPIO F1 GPIO F2 GPIO F3 GPIO F6

P45 DRAM0_CS[2]# -9040.88 -5335.52 - - - - -

P47 VSS -9752.08 -5335.52 - - - - -

P48 DRAM0_CKN[2] -10463.28 -5335.52 - - - - -

P50 DRAM0_CKP[2] -11136.63 -5335.52 - - - - -

P51 DRAM0_DM[4] -11729.97 -5344.92 - - - - -

P52 VSS -12428.98 -5344.92 - - - - -

R1 RESERVED 12814.05 -4859.02 - - - - -

R3 RESERVED 12070.59 -4859.02 - - - - -

R51 DRAM0_DQ[38] -12070.59 -4859.02 - - - - -

R53 DRAM0_DQ[39] -12814.05 -4859.02 - - - - -

T2 RESERVED 12428.98 -4373.12 - - - - -

T3 RESERVED 11729.97 -4373.12 - - - - -

T4 MCSI3_CLKP 11136.63 -4388.36 - - - - -

T6 MCSI3_CLKN 10463.28 -4362.2 - - - - -

T7 MCSI1_CLKN 9752.08 -4362.2 - - - - -

T9 MCSI1_CLKP 9040.88 -4362.2 - - - - -

T10 MCSI1_DP[3] 8329.68 -4362.2 - - - - -

T12 MCSI1_DN[3] 7618.48 -4362.2 - - - - -

T13 MCSI2_DP[0] 6907.28 -4362.2 - - - - -

T14 MCSI2_DN[0] 6196.08 -4362.2 - - - - -

T40 VSS -6196.08 -4362.2 - - - - -

T41 DRAM0_ODT[0] -6907.28 -4362.2 - - - - -

T42 DRAM0_DQSP[5] -7618.48 -4362.2 - - - - -

T44 DRAM0_DQSN[5] -8329.68 -4362.2 - - - - -

T45 DRAM0_DQ[41] -9040.88 -4362.2 - - - - -

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 Table 142. Ball Listing by Location with GPIO Muxed Functions (Sheet 16 of 47)
Location Ball Name X-Location Y-Location GPIO F0 GPIO F1 GPIO F2 GPIO F3 GPIO F6

T47 DRAM0_DQ[40] -9752.08 -4362.2 - - - - -

T48 DRAM0_DQ[44] -10463.28 -4362.2 - - - - -

T50 DRAM0_DQ[45] -11136.63 -4388.36 - - - - -

T51 DRAM0_DQ[35] -11729.97 -4373.12 - - - - -

T52 DRAM0_DQ[34] -12428.98 -4373.12 - - - - -

U1 VSS 12814.05 -3887.22 - - - - -

U3 VSS 12070.59 -3887.22 - - - - -

U5 VSS 10818.88 -3887.22 - - - - -

U6 VSS 10107.68 -3887.22 - - - - -

U8 VSS 9396.48 -3887.22 - - - - -

U9 VSS 8685.28 -3887.22 - - - - -

U11 VSS 7974.08 -3887.22 - - - - -

U12 VSS 7262.88 -3887.22 - - - - -

U14 VSS 6551.68 -3887.22 - - - - -

U16 USB_VSSA 5307.33 -4313.94 - - - - -

U18 USB_V1P0_S3 4549.14 -4313.94 - - - - -

U19 USB_V1P0_S3 3790.95 -4313.94 - - - - -

U21 VSS 3032.76 -4313.94 - - - - -

U22 UNCORE_V1P0_G3 2274.57 -4313.94 - - - - -

U24 UNCORE_V1P8_G3 1516.38 -4313.94 - - - - -

U25 PMC_V1P8_G3 758.19 -4313.94 - - - - -

U27 CORE_VCC_S3 0 -4313.94 - - - - -

U29 CORE_VCC_S3 -758.19 -4313.94 - - - - -

U30 VSS -1516.38 -4313.94 - - - - -

U32 VSS -2274.57 -4313.94 - - - - -

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 Table 142. Ball Listing by Location with GPIO Muxed Functions (Sheet 17 of 47)
Location Ball Name X-Location Y-Location GPIO F0 GPIO F1 GPIO F2 GPIO F3 GPIO F6

U33 CORE_V1P05_S3 -3032.76 -4313.94 - - - - -

U35 CORE_V1P05_S3 -3790.95 -4313.94 - - - - -

U36 UNCORE_V1P35_S3_F4 -4549.14 -4313.94 - - - - -

U38 MIPI_V1P8_S3 -5307.33 -4313.94 - - - - -

U40 VSS -6551.68 -3887.22 - - - - -

U42 VSS -7262.88 -3887.22 - - - - -

U43 VSS -7974.08 -3887.22 - - - - -

U45 VSS -8685.28 -3887.22 - - - - -

U46 VSS -9396.48 -3887.22 - - - - -

U48 VSS -10107.68 -3887.22 - - - - -

U49 VSS -10818.88 -3887.22 - - - - -

U51 VSS -12070.59 -3887.22 - - - - -

U53 VSS -12814.05 -3887.22 - - - - -

V2 RESERVED 12428.98 -3401.31 - - - - -

V3 RESERVED 11729.97 -3401.31 - - - - -

V4 RESERVED 11136.63 -3386.07 - - - - -

V6 RESERVED 10463.28 -3412.24 - - - - -

V7 VSS 9752.08 -3412.24 - - - - -

V9 MCSI1_DP[2] 9040.88 -3412.24 - - - - -

V10 MCSI1_DN[2] 8329.68 -3412.24 - - - - -

V12 VSS 7618.48 -3412.24 - - - - -

V13 MCSI2_CLKP 6907.28 -3412.24 - - - - -

V14 MCSI2_CLKN 6196.08 -3412.24 - - - - -

V16 VSS 5307.33 -3529.58 - - - - -

V18 USB_HSIC_V1P24_G3 4549.14 -3529.58 - - - - -

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 Table 142. Ball Listing by Location with GPIO Muxed Functions (Sheet 18 of 47)
Location Ball Name X-Location Y-Location GPIO F0 GPIO F1 GPIO F2 GPIO F3 GPIO F6

V19 VSS 3790.95 -3529.58 - - - - -

V21 VSS 3032.76 -3529.58 - - - - -

V22 UNCORE_V1P0_G3 2274.57 -3529.58 - - - - -

V24 UNCORE_V1P0_S3 1516.38 -3529.58 - - - - -

V25 PCU_V1P8_G3 758.19 -3529.58 - - - - -

V27 CORE_VCC_S3 0 -3529.58 - - - - -

V29 CORE_VCC_S3 -758.19 -3529.58 - - - - -

V30 CORE_VCC_S3 -1516.38 -3529.58 - - - - -

V32 SVID_V1P0_S3 -2274.57 -3529.58 - - - - -

V33 CORE_V1P05_S3 -3032.76 -3529.58 - - - - -

V35 VSS -3790.95 -3529.58 - - - - -

V36 UNCORE_V1P35_S3_F3 -4549.14 -3529.58 - - - - -

V38 DRAM_VDD_S4 -5307.33 -3529.58 - - - - -

V40 VSS -6196.08 -3412.24 - - - - -

V41 DRAM0_DQ[43] -6907.28 -3412.24 - - - - -

V42 DRAM0_DM[5] -7618.48 -3412.24 - - - - -

V44 VSS -8329.68 -3412.24 - - - - -

V45 DRAM0_DQ[48] -9040.88 -3412.24 - - - - -

V47 DRAM0_DQ[49] -9752.08 -3412.24 - - - - -

V48 DRAM0_DQ[52] -10463.28 -3412.24 - - - - -

V50 DRAM0_DQ[53] -11136.63 -3386.07 - - - - -

V51 VSS -11729.97 -3401.31 - - - - -

V52 DRAM0_DQ[56] -12428.98 -3401.31 - - - - -

W1 RESERVED 12814.05 -2915.41 - - - - -

W3 RESERVED 12070.59 -2915.41 - - - - -

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Datasheet 219
 Table 142. Ball Listing by Location with GPIO Muxed Functions (Sheet 19 of 47)
Location Ball Name X-Location Y-Location GPIO F0 GPIO F1 GPIO F2 GPIO F3 GPIO F6

W51 DRAM0_DQ[57] -12070.59 -2915.41 - - - - -

W53 DRAM0_DQ[60] -12814.05 -2915.41 - - - - -

Y2 RESERVED 12428.98 -2429.51 - - - - -

Y3 RESERVED 11729.97 -2429.51 - - - - -

Y4 RESERVED 11136.63 -2438.91 - - - - -

Y6 RESERVED 10463.28 -2438.91 - - - - -

Y7 VSS 9752.08 -2438.91 - - - - -

Y9 VSS 9040.88 -2438.91 - - - - -

Y10 VSS 8329.68 -2438.91 - - - - -

Y12 MCSI1_DN[1] 7618.48 -2438.91 - - - - -

Y13 MCSI1_DP[1] 6907.28 -2438.91 - - - - -

Y14 VSS 6196.08 -2438.91 - - - - -

Y16 VSS 5307.33 -2745.23 - - - - -

Y18 USB3DEV_V1P0_S3 4549.14 -2745.23 - - - - -

Y19 USB3_V1P0_G3 3790.95 -2745.23 - - - - -

Y21 VSS 3032.76 -2745.23 - - - - -

Y22 UNCORE_V1P0_S3 2274.57 -2745.23 - - - - -

Y24 UNCORE_V1P0_S3 1516.38 -2745.23 - - - - -

Y25 VSS 758.19 -2745.23 - - - - -

Y27 CORE_VCC_S3 0 -2745.23 - - - - -

Y29 CORE_VCC_S3 -758.19 -2745.23 - - - - -

Y30 CORE_VCC_S3 -1516.38 -2745.23 - - - - -

Y32 CORE_V1P05_S3 -2274.57 -2745.23 - - - - -

Y33 VSS -3032.76 -2745.23 - - - - -

Y35 DRAM_V1P0_S3 -3790.95 -2745.23 - - - - -

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 Table 142. Ball Listing by Location with GPIO Muxed Functions (Sheet 20 of 47)
Location Ball Name X-Location Y-Location GPIO F0 GPIO F1 GPIO F2 GPIO F3 GPIO F6

Y36 DRAM_V1P0_S3 -4549.14 -2745.23 - - - - -

Y38 DRAM_VDD_S4 -5307.33 -2745.23 - - - - -

Y40 DRAM0_DQ[42] -6196.08 -2438.91 - - - - -

Y41 VSS -6907.28 -2438.91 - - - - -

Y42 DRAM0_DQ[46] -7618.48 -2438.91 - - - - -

Y44 VSS -8329.68 -2438.91 - - - - -

Y45 DRAM0_DQ[55] -9040.88 -2438.91 - - - - -

Y47 DRAM0_DQSP[6] -9752.08 -2438.91 - - - - -

Y48 DRAM0_DQSN[6] -10463.28 -2438.91 - - - - -

Y50 DRAM0_DM[6] -11136.63 -2438.91 - - - - -

Y51 DRAM0_DQ[61] -11729.97 -2429.51 - - - - -

Y52 DRAM0_DM[7] -12428.98 -2429.51 - - - - -

AA1 VSS 12814.05 -1943.61 - - - - -

AA3 VSS 12070.59 -1943.61 - - - - -

AA16 VSS 5307.33 -1960.88 - - - - -

AA18 USB_ULPI_V1P8_G3 4549.14 -1960.88 - - - - -

AA19 VSS 3790.95 -1960.88 - - - - -

AA21 VSS 3032.76 -1960.88 - - - - -

AA22 TP2_CORE_VCC_S3 2274.57 -1960.88 - - - - -

AA24 UNCORE_VNN_S3 1516.38 -1960.88 - - - - -

AA25 UNCORE_V1P35_S3_F5 758.19 -1960.88 - - - - -

AA27 CORE_VCC_S3 0 -1960.88 - - - - -

AA29 CORE_VCC_S3 -758.19 -1960.88 - - - - -

AA30 CORE_VCC_S3 -1516.38 -1960.88 - - - - -

AA32 VSS -2274.57 -1960.88 - - - - -

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Datasheet 221
 Table 142. Ball Listing by Location with GPIO Muxed Functions (Sheet 21 of 47)
Location Ball Name X-Location Y-Location GPIO F0 GPIO F1 GPIO F2 GPIO F3 GPIO F6

AA33 CORE_V1P05_S3 -3032.76 -1960.88 - - - - -

AA35 VSS -3790.95 -1960.88 - - - - -

AA36 DRAM_V1P0_S3 -4549.14 -1960.88 - - - - -

AA38 VSS -5307.33 -1960.88 - - - - -

AA51 DRAM0_DQSN[7] -12070.59 -1943.61 - - - - -

AA53 VSS -12814.05 -1943.61 - - - - -

AB2 RESERVED 12428.98 -1457.71 - - - - -

AB3 RESERVED 11729.97 -1457.71 - - - - -

AB4 VSS 11136.63 -1448.31 - - - - -

AB6 VSS 10463.28 -1448.31 - - - - -

AB7 RESERVED 9752.08 -1448.31 - - - - -

AB9 RESERVED 9040.88 -1448.31 - - - - -

AB10 VSS 8329.68 -1448.31 - - - - -

AB12 MCSI1_DP[0] 7618.48 -1448.31 - - - - -

AB13 MCSI1_DN[0] 6907.28 -1448.31 - - - - -

AB14 RESERVED 6196.08 -1448.31 - - - - -

AB40 DRAM0_DQ[47] -6196.08 -1448.31 - - - - -

AB41 VSS -6907.28 -1448.31 - - - - -

AB42 DRAM_CORE_PWROK -7618.48 -1448.31 - - - - -

AB44 DRAM0_DQ[54] -8329.68 -1448.31 - - - - -

AB45 VSS -9040.88 -1448.31 - - - - -

AB47 VSS -9752.08 -1448.31 - - - - -

AB48 VSS -10463.28 -1448.31 - - - - -

AB50 VSS -11136.63 -1448.31 - - - - -

AB51 VSS -11729.97 -1457.71 - - - - -

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222 Datasheet
 Table 142. Ball Listing by Location with GPIO Muxed Functions (Sheet 22 of 47)
Location Ball Name X-Location Y-Location GPIO F0 GPIO F1 GPIO F2 GPIO F3 GPIO F6

AB52 DRAM0_DQSP[7] -12428.98 -1457.71 - - - - -

AC1 DDI1_TXN[3] 12814.05 -971.8 - - - - -

AC3 DDI1_TXP[3] 12070.59 -971.8 - - - - -

AC16 VSS 5307.33 -1176.53 - - - - -

AC18 VSS 4549.14 -1176.53 - - - - -

AC19 VSS 3790.95 -1176.53 - - - - -

AC21 VSS 3032.76 -1176.53 - - - - -

AC22 UNCORE_VNN_S3 2274.57 -1176.53 - - - - -

AC24 UNCORE_VNN_S3 1516.38 -1176.53 - - - - -

AC25 VSS 758.19 -1176.53 - - - - -

AC27 CORE_VCC_S3 0 -1176.53 - - - - -

AC29 CORE_VCC_S3 -758.19 -1176.53 - - - - -

AC30 CORE_VCC_S3 -1516.38 -1176.53 - - - - -

AC32 CORE_V1P05_S3 -2274.57 -1176.53 - - - - -

AC33 VSS -3032.76 -1176.53 - - - - -

AC35 VSS -3790.95 -1176.53 - - - - -

AC36 VSS -4549.14 -1176.53 - - - - -

AC38 VSS -5307.33 -1176.53 - - - - -

AC51 DRAM0_DQ[59] -12070.59 -971.8 - - - - -

AC53 DRAM0_DQ[58] -12814.05 -971.8 - - - - -

AD2 DDI1_TXN[2] 12428.98 -485.9 - - - - -

AD3 DDI1_TXP[2] 11715.24 -479.81 - - - - -

AD4 RESERVED 10994.64 -462.79 - - - - -

AD6 RESERVED 10404.35 -525.02 - - - - -

AD7 VSS 9752.08 -474.98 - - - - -

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Datasheet 223
 Table 142. Ball Listing by Location with GPIO Muxed Functions (Sheet 23 of 47)
Location Ball Name X-Location Y-Location GPIO F0 GPIO F1 GPIO F2 GPIO F3 GPIO F6

AD9 RESERVED 9040.88 -474.98 - - - - -

AD10 RESERVED 8329.68 -474.98 - - - - -

AD12 RESERVED 7618.48 -474.98 - - - - -

AD13 ICLK_RCOMP 6907.28 -474.98 - - - - -

AD14 ICLK_ICOMP 6196.08 -474.98 - - - - -

AD16 MIPI_V1P24_S3 5307.33 -392.18 - - - - -

AD18 MIPI_V1P24_S3 4549.14 -392.18 - - - - -

AD19 VSS 3790.95 -392.18 - - - - -

AD21 VSS 3032.76 -392.18 - - - - -

AD22 UNCORE_VNN_S3 2274.57 -392.18 - - - - -

AD24 UNCORE_VNN_S3 1516.38 -392.18 - - - - -

AD25 VSS 758.19 -392.18 - - - - -

AD27 CORE_VCC_S3 0 -392.18 - - - - -

AD29 CORE_VCC_S3 -758.19 -392.18 - - - - -

AD30 CORE_VCC_S3 -1516.38 -392.18 - - - - -

AD32 VSS -2274.57 -392.18 - - - - -

AD33 VSS -3032.76 -392.18 - - - - -

AD35 DRAM_V1P0_S3 -3790.95 -392.18 - - - - -

AD36 DRAM_V1P35_S3_F1 -4549.14 -392.18 - - - - -

AD38 DRAM_VDD_S4 -5307.33 -392.18 - - - - -

AD40 RESERVED -6196.08 -474.98 - - - - -

AD41 RESERVED -6907.28 -474.98 - - - - -

AD42 DRAM_VDD_S4_PWROK -7618.48 -474.98 - - - - -

AD44 DRAM_RCOMP[0] -8329.68 -474.98 - - - - -

AD45 DRAM_RCOMP[2] -9040.88 -474.98 - - - - -

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224 Datasheet
 Table 142. Ball Listing by Location with GPIO Muxed Functions (Sheet 24 of 47)
Location Ball Name X-Location Y-Location GPIO F0 GPIO F1 GPIO F2 GPIO F3 GPIO F6

AD47 VSS -9752.08 -474.98 - - - - -

AD48 DRAM0_DQ[50] -10404.35 -525.02 - - - - -

AD50 DRAM0_DQ[51] -10994.64 -462.79 - - - - -

AD51 DRAM0_DQ[63] -11715.24 -479.81 - - - - -

AD52 DRAM0_DQ[62] -12428.98 -485.9 - - - - -

AE1 VSS 12814.05 0 - - - - -

AE3 VSS 12070.59 0 - - - - -

AE4 VSS 11365.99 0 - - - - -

AE6 VSS 10107.68 0 - - - - -

AE8 VSS 9396.48 0 - - - - -

AE9 VSS 8685.28 0 - - - - -

AE11 VSS 7974.08 0 - - - - -

AE12 VSS 7262.88 0 - - - - -

AE14 VSS 6551.68 0 - - - - -

AE40 VSS -6551.68 0 - - - - -

AE42 VSS -7262.88 0 - - - - -

AE43 VSS -7974.08 0 - - - - -

AE45 VSS -8685.28 0 - - - - -

AE46 VSS -9396.48 0 - - - - -

AE48 VSS -10107.68 0 - - - - -

AE50 VSS -11365.99 0 - - - - -

AE51 VSS -12070.59 0 - - - - -

AE53 VSS -12814.05 0 - - - - -

AF2 DDI1_TXN[1] 12428.98 485.9 - - - - -

AF3 DDI1_TXP[1] 11715.24 479.81 - - - - -

Intel® Atom™ Processor E3800 Product Family

Datasheet 225
 Table 142. Ball Listing by Location with GPIO Muxed Functions (Sheet 25 of 47)
Location Ball Name X-Location Y-Location GPIO F0 GPIO F1 GPIO F2 GPIO F3 GPIO F6

AF4 PCIE_CLKP[0] 10994.64 462.79 - - - - -

AF6 PCIE_CLKN[0] 10404.35 525.02 - - - - -

AF7 PCIE_CLKP[1] 9752.08 474.98 - - - - -

AF9 PCIE_CLKN[1] 9040.88 474.98 - - - - -

AF10 VSS 8329.68 474.98 - - - - -

AF12 VSS 7618.48 474.98 - - - - -

AF13 RESERVED 6907.28 474.98 - - - - -

AF14 RESERVED 6196.08 474.98 - - - - -

AF16 UNCORE_V1P0_S3 5307.33 392.18 - - - - -

AF18 UNCORE_V1P0_S3 4549.14 392.18 - - - - -

AF19 UNCORE_V1P35_S3_F6 3790.95 392.18 - - - - -

AF21 UNCORE_V1P0_S3 3032.76 392.18 - - - - -

AF22 UNCORE_VNN_S3 2274.57 392.18 - - - - -

AF24 UNCORE_VNN_S3 1516.38 392.18 - - - - -

AF25 VSS 758.19 392.18 - - - - -

AF27 CORE_VCC_S3 0 392.18 - - - - -

AF29 CORE_VCC_S3 -758.19 392.18 - - - - -

AF30 TP_CORE_V1P05_S4 -1516.38 392.18 - - - - -

AF32 VSS -2274.57 392.18 - - - - -

AF33 CORE_V1P05_S3 -3032.76 392.18 - - - - -

AF35 DRAM_V1P0_S3 -3790.95 392.18 - - - - -

AF36 DRAM_V1P0_S3 -4549.14 392.18 - - - - -

AF38 DRAM_VDD_S4 -5307.33 392.18 - - - - -

AF40 RESERVED -6196.08 474.98 - - - - -

AF41 RESERVED -6907.28 474.98 - - - - -

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 Table 142. Ball Listing by Location with GPIO Muxed Functions (Sheet 26 of 47)
Location Ball Name X-Location Y-Location GPIO F0 GPIO F1 GPIO F2 GPIO F3 GPIO F6

AF42 ICLK_DRAM_TERM[0] -7618.48 474.98 - - - - -

AF44 DRAM_VREF -8329.68 474.98 - - - - -

AF45 DRAM_RCOMP[1] -9040.88 474.98 - - - - -

AF47 VSS -9752.08 474.98 - - - - -

AF48 DRAM1_DQ[50] -10404.35 525.02 - - - - -

AF50 DRAM1_DQ[51] -10994.64 462.79 - - - - -

AF51 DRAM1_DQ[63] -11715.24 479.81 - - - - -

AF52 DRAM1_DQ[62] -12428.98 485.9 - - - - -

AG1 DDI1_TXN[0] 12814.05 971.8 - - - - -

AG3 DDI1_TXP[0] 12070.59 971.8 - - - - -

AG16 VSS 5307.33 1176.53 - - - - -

AG18 ICLK_V1P35_S3_F2 4549.14 1176.53 - - - - -

AG19 UNCORE_V1P35_S3_F1 3790.95 1176.53 - - - - -

AG21 UNCORE_V1P0_S3 3032.76 1176.53 - - - - -

AG22 UNCORE_VNN_S3 2274.57 1176.53 - - - - -

AG24 UNCORE_VNN_S3 1516.38 1176.53 - - - - -

AG25 VSS 758.19 1176.53 - - - - -

AG27 CORE_VCC_S3 0 1176.53 - - - - -

AG29 CORE_VCC_S3 -758.19 1176.53 - - - - -

AG30 CORE_VCC_S3 -1516.38 1176.53 - - - - -

AG32 UNCORE_V1P35_S3_F2 -2274.57 1176.53 - - - - -

AG33 CORE_V1P05_S3 -3032.76 1176.53 - - - - -

AG35 CORE_V1P05_S3 -3790.95 1176.53 - - - - -

AG36 VSS -4549.14 1176.53 - - - - -

AG38 VSS -5307.33 1176.53 - - - - -

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 Table 142. Ball Listing by Location with GPIO Muxed Functions (Sheet 27 of 47)
Location Ball Name X-Location Y-Location GPIO F0 GPIO F1 GPIO F2 GPIO F3 GPIO F6

AG51 DRAM1_DQ[59] -12070.59 971.8 - - - - -

AG53 DRAM1_DQ[58] -12814.05 971.8 - - - - -

AH2 RSVD_GND[3] 12428.98 1457.71 - - - - -

AH3 RSVD_GND[2] 11729.97 1457.71 - - - - -

AH4 VSS 11136.63 1448.31 - - - - -

AH6 VSS 10463.28 1448.31 - - - - -

AH7 VSS 9752.08 1448.31 - - - - -

AH9 VSS 9040.88 1448.31 - - - - -

AH10 ICLK_OSCOUT 8329.68 1448.31 - - - - -

AH12 ICLK_OSCIN 7618.48 1448.31 - - - - -

AH13 RESERVED 6907.28 1448.31 - - - - -

AH14 RESERVED 6196.08 1448.31 - - - - -

AH40 DRAM1_DQ[47] -6196.08 1448.31 - - - - -

AH41 VSS -6907.28 1448.31 - - - - -

AH42 ICLK_DRAM_TERM[1] -7618.48 1448.31 - - - - -

AH44 DRAM1_DQ[54] -8329.68 1448.31 - - - - -

AH45 VSS -9040.88 1448.31 - - - - -

AH47 VSS -9752.08 1448.31 - - - - -

AH48 VSS -10463.28 1448.31 - - - - -

AH50 VSS -11136.63 1448.31 - - - - -

AH51 VSS -11729.97 1457.71 - - - - -

AH52 DRAM1_DQSP[7] -12428.98 1457.71 - - - - -

AJ1 VSS 12814.05 1943.61 - - - - -

AJ3 VSS 12070.59 1943.61 - - - - -

AJ16 VSS 5307.33 1960.88 - - - - -

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 Table 142. Ball Listing by Location with GPIO Muxed Functions (Sheet 28 of 47)
Location Ball Name X-Location Y-Location GPIO F0 GPIO F1 GPIO F2 GPIO F3 GPIO F6

AJ18 DDI_V1P0_S3 4549.14 1960.88 - - - - -

AJ19 ICLK_V1P35_S3_F1 3790.95 1960.88 - - - - -

AJ21 VSS 3032.76 1960.88 - - - - -

AJ22 UNCORE_VNN_S3 2274.57 1960.88 - - - - -

AJ24 UNCORE_VNN_S3 1516.38 1960.88 - - - - -

AJ25 VSS 758.19 1960.88 - - - - -

AJ27 VSS 0 1960.88 - - - - -

AJ29 VSS -758.19 1960.88 - - - - -

AJ30 VSS -1516.38 1960.88 - - - - -

AJ32 VSS -2274.57 1960.88 - - - - -

AJ33 VSS -3032.76 1960.88 - - - - -

AJ35 VSS -3790.95 1960.88 - - - - -

AJ36 DRAM_V1P0_S3 -4549.14 1960.88 - - - - -

AJ38 VSS -5307.33 1960.88 - - - - -

AJ51 DRAM1_DQSN[7] -12070.59 1943.61 - - - - -

AJ53 VSS -12814.05 1943.61 - - - - -

AK2 DDI1_AUXN 12428.98 2429.51 - - - - -

AK3 DDI1_AUXP 11729.97 2429.51 - - - - -

AK4 PCIE_CLKN[2] 11136.63 2438.91 - - - - -

AK6 PCIE_CLKP[2] 10463.28 2438.91 - - - - -

AK7 RESERVED 9752.08 2438.91 - - - - -

AK9 RESERVED 9040.88 2438.91 - - - - -

AK10 VSS 8329.68 2438.91 - - - - -

AK12 DDI_RCOMP_P 7618.48 2438.91 - - - - -

AK13 DDI_RCOMP_N 6907.28 2438.91 - - - - -

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 Table 142. Ball Listing by Location with GPIO Muxed Functions (Sheet 29 of 47)
Location Ball Name X-Location Y-Location GPIO F0 GPIO F1 GPIO F2 GPIO F3 GPIO F6

AK14 VSS 6196.08 2438.91 - - - - -

AK16 VSS 5307.33 2745.23 - - - - -

AK18 PCIE_V1P0_S3 4549.14 2745.23 - - - - -

AK19 DDI_V1P0_S3 3790.95 2745.23 - - - - -

AK21 DDI_V1P0_S3 3032.76 2745.23 - - - - -

AK22 UNCORE_VNN_S3 2274.57 2745.23 - - - - -

AK24 UNCORE_VNN_S3 1516.38 2745.23 - - - - -

AK25 UNCORE_VNN_S3 758.19 2745.23 - - - - -

AK27 UNCORE_VNN_S3 0 2745.23 - - - - -

AK29 UNCORE_VNN_S3 -758.19 2745.23 - - - - -

AK30 UNCORE_VNN_S3 -1516.38 2745.23 - - - - -

AK32 UNCORE_VNN_S3 -2274.57 2745.23 - - - - -

AK33 VSS -3032.76 2745.23 - - - - -

AK35 DRAM_V1P0_S3 -3790.95 2745.23 - - - - -

AK36 DRAM_V1P0_S3 -4549.14 2745.23 - - - - -

AK38 DRAM_VDD_S4 -5307.33 2745.23 - - - - -

AK40 DRAM1_DQ[42] -6196.08 2438.91 - - - - -

AK41 VSS -6907.28 2438.91 - - - - -

AK42 DRAM1_DQ[46] -7618.48 2438.91 - - - - -

AK44 VSS -8329.68 2438.91 - - - - -

AK45 DRAM1_DQ[55] -9040.88 2438.91 - - - - -

AK47 DRAM1_DQSP[6] -9752.08 2438.91 - - - - -

AK48 DRAM1_DQSN[6] -10463.28 2438.91 - - - - -

AK50 DRAM1_DM[6] -11136.63 2438.91 - - - - -

AK51 DRAM1_DQ[61] -11729.97 2429.51 - - - - -

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 Table 142. Ball Listing by Location with GPIO Muxed Functions (Sheet 30 of 47)
Location Ball Name X-Location Y-Location GPIO F0 GPIO F1 GPIO F2 GPIO F3 GPIO F6

AK52 DRAM1_DM[7] -12428.98 2429.51 - - - - -

AL1 DDI0_AUXN 12814.05 2915.41 - - - - -

AL3 DDI0_AUXP 12070.59 2915.41 - - - - -

AL51 DRAM1_DQ[57] -12070.59 2915.41 - - - - -

AL53 DRAM1_DQ[60] -12814.05 2915.41 - - - - -

AM2 RSVD_GND[1] 12428.98 3401.31 - - - - -

AM3 RSVD_GND[0] 11729.97 3401.31 - - - - -

AM4 PCIE_CLKN[3] 11136.63 3386.07 - - - - -

AM6 PCIE_CLKP[3] 10463.28 3412.24 - - - - -

AM7 VSS 9752.08 3412.24 - - - - -

AM9 RESERVED 9040.88 3412.24 - - - - -

AM10 RESERVED 8329.68 3412.24 - - - - -

AM12 VSS 7618.48 3412.24 - - - - -

AM13 RESERVED 6907.28 3412.24 - - - - -

AM14 RESERVED 6196.08 3412.24 - - - - -

AM16 DDI_V1P0_S3 5307.33 3529.58 - - - - -

AM18 PCIE_V1P0_S3 4549.14 3529.58 - - - - -

AM19 VSS 3790.95 3529.58 - - - - -

AM21 PCIE_V1P0_S3 3032.76 3529.58 - - - - -

AM22 UNCORE_VNN_S3 2274.57 3529.58 - - - - -

AM24 VSS 1516.38 3529.58 - - - - -

AM25 VSS 758.19 3529.58 - - - - -

AM27 LPC_V1P8V3P3_S3 0 3529.58 - - - - -

AM29 VSS -758.19 3529.58 - - - - -

AM30 UNCORE_V1P8_S3 -1516.38 3529.58 - - - - -

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 Table 142. Ball Listing by Location with GPIO Muxed Functions (Sheet 31 of 47)
Location Ball Name X-Location Y-Location GPIO F0 GPIO F1 GPIO F2 GPIO F3 GPIO F6

AM32 HDA_LPE_V1P5V1P8_S3 -2274.57 3529.58 - - - - -

AM33 VSS -3032.76 3529.58 - - - - -

AM35 VSS -3790.95 3529.58 - - - - -

AM36 VSS -4549.14 3529.58 - - - - -

AM38 DRAM_VDD_S4 -5307.33 3529.58 - - - - -

AM40 VSS -6196.08 3412.24 - - - - -

AM41 DRAM1_DQ[43] -6907.28 3412.24 - - - - -

AM42 DRAM1_DM[5] -7618.48 3412.24 - - - - -

AM44 VSS -8329.68 3412.24 - - - - -

AM45 DRAM1_DQ[48] -9040.88 3412.24 - - - - -

AM47 DRAM1_DQ[49] -9752.08 3412.24 - - - - -

AM48 DRAM1_DQ[52] -10463.28 3412.24 - - - - -

AM50 DRAM1_DQ[53] -11136.63 3386.07 - - - - -

AM51 VSS -11729.97 3401.31 - - - - -

AM52 DRAM1_DQ[56] -12428.98 3401.31 - - - - -

AN1 VSS 12814.05 3887.22 - - - - -

AN3 VSS 12070.59 3887.22 - - - - -

AN5 VSS 10818.88 3887.22 - - - - -

AN6 VSS 10107.68 3887.22 - - - - -

AN8 VSS 9396.48 3887.22 - - - - -

AN9 VSS 8685.28 3887.22 - - - - -

AN11 VSS 7974.08 3887.22 - - - - -

AN12 VSS 7262.88 3887.22 - - - - -

AN14 VSS 6551.68 3887.22 - - - - -

AN16 VSSA 5307.33 4313.94 - - - - -

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 Table 142. Ball Listing by Location with GPIO Muxed Functions (Sheet 32 of 47)
Location Ball Name X-Location Y-Location GPIO F0 GPIO F1 GPIO F2 GPIO F3 GPIO F6

AN18 PCIE_SATA_V1P0_S3 4549.14 4313.94 - - - - -

AN19 SATA_V1P0_S3 3790.95 4313.94 - - - - -

AN21 PCIE_V1P0_S3 3032.76 4313.94 - - - - -

AN22 VSS 2274.57 4313.94 - - - - -

AN24 VGA_V3P3_S3 1516.38 4313.94 - - - - -

AN25 GPIO_V1P0_S3 758.19 4313.94 - - - - -

AN27 SD3_V1P8V3P3_S3 0 4313.94 - - - - -

AN29 UNCORE_V1P0_S3 -758.19 4313.94 - - - - -

AN30 UNCORE_V1P0_S3 -1516.38 4313.94 - - - - -

AN32 UNCORE_V1P8_S3 -2274.57 4313.94 - - - - -

AN33 VSS -3032.76 4313.94 - - - - -

AN35 VSS -3790.95 4313.94 - - - - -

AN36 VSS -4549.14 4313.94 - - - - -

AN38 VSS -5307.33 4313.94 - - - - -

AN40 VSS -6551.68 3887.22 - - - - -

AN42 VSS -7262.88 3887.22 - - - - -

AN43 VSS -7974.08 3887.22 - - - - -

AN45 VSS -8685.28 3887.22 - - - - -

AN46 VSS -9396.48 3887.22 - - - - -

AN48 VSS -10107.68 3887.22 - - - - -

AN49 VSS -10818.88 3887.22 - - - - -

AN51 VSS -12070.59 3887.22 - - - - -

AN53 VSS -12814.05 3887.22 - - - - -

AP2 DDI0_TXN[3] 12428.98 4373.12 - - - - -

AP3 DDI0_TXP[3] 11729.97 4373.12 - - - - -

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Datasheet 233
 Table 142. Ball Listing by Location with GPIO Muxed Functions (Sheet 33 of 47)
Location Ball Name X-Location Y-Location GPIO F0 GPIO F1 GPIO F2 GPIO F3 GPIO F6

AP4 PCIE_TXN[3] 11136.63 4388.36 - - - - -

AP6 PCIE_TXP[3] 10463.28 4362.2 - - - - -

AP7 PCIE_RXN[3] 9752.08 4362.2 - - - - -

AP9 PCIE_RXP[3] 9040.88 4362.2 - - - - -

AP10 PCIE_RXN[2] 8329.68 4362.2 - - - - -

AP12 PCIE_RXP[2] 7618.48 4362.2 - - - - -

AP13 PCIE_RCOMP_N 6907.28 4362.2 - - - - -

AP14 PCIE_RCOMP_P 6196.08 4362.2 - - - - -

AP40 VSS -6196.08 4362.2 - - - - -

AP41 DRAM1_ODT[0] -6907.28 4362.2 - - - - -

AP42 DRAM1_DQSP[5] -7618.48 4362.2 - - - - -

AP44 DRAM1_DQSN[5] -8329.68 4362.2 - - - - -

AP45 DRAM1_DQ[41] -9040.88 4362.2 - - - - -

AP47 DRAM1_DQ[40] -9752.08 4362.2 - - - - -

AP48 DRAM1_DQ[44] -10463.28 4362.2 - - - - -

AP50 DRAM1_DQ[45] -11136.63 4388.36 - - - - -

AP51 DRAM1_DQ[35] -11729.97 4373.12 - - - - -

AP52 DRAM1_DQ[34] -12428.98 4373.12 - - - - -

AR1 DDI0_TXN[2] 12814.05 4859.02 - - - - -

AR3 DDI0_TXP[2] 12070.59 4859.02 - - - - -

AR51 DRAM1_DQ[38] -12070.59 4859.02 - - - - -

AR53 DRAM1_DQ[39] -12814.05 4859.02 - - - - -

AT2 DDI0_TXP[1] 12428.98 5344.92 - - - - -

AT3 DDI0_TXN[1] 11729.97 5344.92 - - - - -

AT4 VSS 11136.63 5335.52 - - - - -

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234 Datasheet
 Table 142. Ball Listing by Location with GPIO Muxed Functions (Sheet 34 of 47)
Location Ball Name X-Location Y-Location GPIO F0 GPIO F1 GPIO F2 GPIO F3 GPIO F6

AT6 PCIE_TXN[2] 10463.28 5335.52 - - - - -

AT7 PCIE_TXP[2] 9752.08 5335.52 - - - - -

AT9 PCIE_RXN[1] 9040.88 5335.52 - - - - -

AT10 PCIE_RXP[1] 8329.68 5335.52 - - - - -

AT12 VSS 7618.48 5335.52 - - - - -

AT13 PCIE_RXN[0] 6907.28 5335.52 - - - - -

AT14 PCIE_RXP[0] 6304.79 5335.52 - - - - -

AT16 VSS 5335.52 5196.08 - - - - -

AT18 SATA_RCOMP_N 4362.2 5196.08 - - - - -

AT19 VSS 3887.22 5551.68 - - - - -

AT20 MMC1_D[3] 3412.24 5196.08 GPIO_S0_SC[020] MMC1_D[3] - MMC1_45_D[3] -

AT22 MMC1_CLK 2438.91 5196.08 GPIO_S0_SC[016] MMC1_CLK - MMC1_45_CLK -

AT24 VSS 1448.31 5196.08 - - - - -

AT26 MMC1_D[6] 474.98 5196.08 GPIO_S0_SC[023] MMC1_D[6] - MMC1_45_D[6] -

AT27 VSS 0 5551.68 - - - - -

AT28 SD3_D[0] -474.98 5196.08 GPIO_S0_SC[034] SD3_D[0] - - -

AT30 VSS -1448.31 5196.08 - - - - -

AT32 SIO_PWM[1] -2438.91 5196.08 GPIO_S0_SC[095] SIO_PWM[1] - - -

AT34 RESERVED -3412.24 5196.08 RESERVED - - - -

AT35 VSS -3887.22 5551.68 - - - - -

AT36 DRAM1_DQ[17] -4362.2 5196.08 - - - - -

AT38 VSS -5335.52 5196.08 - - - - -

AT40 DRAM1_DQ[19] -6304.79 5335.52 - - - - -

AT41 DRAM1_DRAMRST# -6907.28 5335.52 - - - - -

AT42 DRAM1_ODT[2] -7618.48 5335.52 - - - - -

Intel® Atom™ Processor E3800 Product Family

Datasheet 235
 Table 142. Ball Listing by Location with GPIO Muxed Functions (Sheet 35 of 47)
Location Ball Name X-Location Y-Location GPIO F0 GPIO F1 GPIO F2 GPIO F3 GPIO F6

AT44 DRAM1_CS[0]# -8329.68 5335.52 - - - - -

AT45 DRAM1_CS[2]# -9040.88 5335.52 - - - - -

AT47 VSS -9752.08 5335.52 - - - - -

AT48 DRAM1_CKN[2] -10463.28 5335.52 - - - - -

AT50 DRAM1_CKP[2] -11136.63 5335.52 - - - - -

AT51 DRAM1_DM[4] -11729.97 5344.92 - - - - -

AT52 VSS -12428.98 5344.92 - - - - -

AU1 VSS 12814.05 5830.82 - - - - -

AU3 VSS 12070.59 5830.82 - - - - -

AU16 SATA_RXP[0] 5335.52 5907.28 - - - - -

AU18 SATA_RCOMP_P 4362.2 5907.28 - - - - -

AU20 MMC1_D[7] 3412.24 5907.28 GPIO_S0_SC[024] MMC1_D[7] - MMC1_45_D[7] -

AU22 MMC1_D[1] 2438.91 5907.28 GPIO_S0_SC[018] MMC1_D[1] - MMC1_45_D[1] -

AU24 VSS 1448.31 5907.28 - - - - -

AU26 MMC1_D[5] 474.98 5907.28 GPIO_S0_SC[022] MMC1_D[5] - MMC1_45_D[5] -

AU28 SD3_D[2] -474.98 5907.28 GPIO_S0_SC[036] SD3_D[2] - - -

AU30 VSS -1448.31 5907.28 - - - - -

AU32 SIO_PWM[0] -2438.91 5907.28 GPIO_S0_SC[094] SIO_PWM[0] - - -

AU34 SIO_UART1_RXD -3412.24 5907.28 GPIO_S0_SC[070] SIO_UART1_RXD RESERVED - -

AU36 DRAM1_DQ[16] -4362.2 5907.28 - - - - -

AU38 VSS -5335.52 5907.28 - - - - -

AU51 VSS -12070.59 5830.82 - - - - -

AU53 DRAM1_DQSP[4] -12814.05 5830.82 - - - - -

AV2 DDI0_TXN[0] 12428.98 6316.73 - - - - -

AV3 DDI0_TXP[0] 11729.97 6316.73 - - - - -

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236 Datasheet
 Table 142. Ball Listing by Location with GPIO Muxed Functions (Sheet 36 of 47)
Location Ball Name X-Location Y-Location GPIO F0 GPIO F1 GPIO F2 GPIO F3 GPIO F6

AV4 PCIE_TXN[1] 11136.63 6326.12 - - - - -

AV6 PCIE_TXP[1] 10463.28 6326.12 - - - - -

AV7 VSS 9752.08 6326.12 - - - - -

AV9 RESERVED 9040.88 6326.12 - - - - -

AV10 RESERVED 8329.68 6326.12 - - - - -

AV12 VSS 7618.48 6326.12 - - - - -

AV13 VSS 6907.28 6326.12 - - - - -

AV14 VSS 6326.12 6446.01 - - - - -

AV16 SATA_RXN[0] 5335.52 6618.48 - - - - -

AV18 VSS 4362.2 6618.48 - - - - -

AV19 VSS 3887.22 6262.88 - - - - -

AV20 MMC1_D[0] 3412.24 6618.48 GPIO_S0_SC[017] MMC1_D[0] - MMC1_45_D[0] -

AV22 MMC1_D[2] 2438.91 6618.48 GPIO_S0_SC[019] MMC1_D[2] - MMC1_45_D[2] -

AV24 VSS 1448.31 6618.48 - - - - -

AV26 MMC1_CMD 474.98 6618.48 GPIO_S0_SC[025] MMC1_CMD - MMC1_45_CMD -

AV27 VSS 0 6262.88 - - - - -

AV28 SD3_CMD -474.98 6618.48 GPIO_S0_SC[039] SD3_CMD - - -

AV30 VSS -1448.31 6618.48 - - - - -

AV32 SIO_SPI_CS# -2438.91 6618.48 GPIO_S0_SC[066] SIO_SPI_CS# - - -

AV34 SIO_UART1_TXD -3412.24 6618.48 GPIO_S0_SC[071] SIO_UART1_TXD RESERVED - -

AV35 VSS -3887.22 6262.88 - - - - -

AV36 DRAM1_DQ[21] -4362.2 6618.48 - - - - -

AV38 VSS -5335.52 6618.48 - - - - -

AV40 DRAM1_DQ[18] -6326.12 6446.01 - - - - -

AV41 DRAM_VDD_S4 -6907.28 6326.12 - - - - -

Intel® Atom™ Processor E3800 Product Family

Datasheet 237
 Table 142. Ball Listing by Location with GPIO Muxed Functions (Sheet 37 of 47)
Location Ball Name X-Location Y-Location GPIO F0 GPIO F1 GPIO F2 GPIO F3 GPIO F6

AV42 DRAM_VDD_S4 -7618.48 6326.12 - - - - -

AV44 DRAM1_CAS# -8329.68 6326.12 - - - - -

AV45 DRAM1_RAS# -9040.88 6326.12 - - - - -

AV47 VSS -9752.08 6326.12 - - - - -

AV48 DRAM1_CKN[0] -10463.28 6326.12 - - - - -

AV50 DRAM1_CKP[0] -11136.63 6326.12 - - - - -

AV51 VSS -11729.97 6316.73 - - - - -

AV52 DRAM1_DQSN[4] -12428.98 6316.73 - - - - -

AW1 VGA_IREF 12814.05 6802.63 - - - - -

AW3 VSS 12070.59 6802.63 - - - - -

AW13 VSS 6750.56 6914.9 - - - - -

AW19 VSS 3887.22 6974.08 - - - - -

AW27 VSS 0 6974.08 - - - - -

AW35 VSS -3887.22 6974.08 - - - - -

AW41 DRAM1_MA[02] -6750.56 6914.9 - - - - -

AW51 DRAM1_DQ[36] -12070.59 6802.63 - - - - -

AW53 DRAM1_DQ[37] -12814.05 6802.63 - - - - -

AY2 VGA_BLUE 12428.98 7288.53 - - - - -

AY3 VGA_IRTN 11729.97 7288.53 - - - - -

AY4 VSS 11137.14 7316.72 - - - - -

AY6 PCIE_TXN[0] 10463.28 7316.72 - - - - -

AY7 PCIE_TXP[0] 9752.08 7316.72 - - - - -

AY9 VSS 9040.88 7316.72 - - - - -

AY10 VSS 8329.68 7316.72 - - - - -

AY12 SATA_LED# 7316.72 7339.58 GPIO_S0_SC[002] SATA_LED# - - -

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238 Datasheet
 Table 142. Ball Listing by Location with GPIO Muxed Functions (Sheet 38 of 47)
Location Ball Name X-Location Y-Location GPIO F0 GPIO F1 GPIO F2 GPIO F3 GPIO F6

AY14 SATA_GP[1] 6326.12 7329.68 GPIO_S0_SC[001] SATA_GP[1] SATA_DEVSLP[0] - -

AY16 SATA_RXP[1] 5335.52 7329.68 - - - - -

AY18 MMC1_RCOMP 4362.2 7329.68 - - - - -

AY20 SD2_D[0] 3412.24 7329.68 GPIO_S0_SC[028] SD2_D[0] - - -

AY22 VSS 2438.91 7329.68 - - - - -

AY24 MMC1_D[4] 1448.31 7329.68 GPIO_S0_SC[021] MMC1_D[4] - MMC1_45_D[4] -

AY26 SD3_CLK 474.98 7329.68 GPIO_S0_SC[033] SD3_CLK - - -

AY28 SIO_SPI_MOSI -474.98 7329.68 GPIO_S0_SC[068] SIO_SPI_MOSI - - -

AY30 SIO_SPI_CLK -1448.31 7329.68 GPIO_S0_SC[069] SIO_SPI_CLK - - -

AY32 VSS -2438.91 7329.68 - - - - -

AY34 SIO_UART1_CTS# -3412.24 7329.68 GPIO_S0_SC[073] SIO_UART1_CTS# - - -

AY36 VSS -4362.2 7329.68 - - - - -

AY38 DRAM1_DQSN[2] -5335.52 7329.68 - - - - -

AY40 DRAM1_DQ[23] -6326.12 7329.68 - - - - -

AY42 DRAM1_DQ[22] -7316.72 7339.58 - - - - -

AY44 DRAM1_BS[1] -8329.68 7316.72 - - - - -

AY45 DRAM1_MA[00] -9040.88 7316.72 - - - - -

AY47 DRAM1_BS[0] -9752.08 7316.72 - - - - -

AY48 DRAM1_MA[10] -10463.28 7316.72 - - - - -

AY50 VSS -11137.14 7316.72 - - - - -

AY51 DRAM1_DQ[33] -11729.97 7288.53 - - - - -

AY52 DRAM1_DQ[32] -12428.98 7288.53 - - - - -

BA1 VGA_GREEN 12814.05 7774.43 - - - - -

BA3 VGA_RED 12070.59 7774.43 - - - - -

BA12 SATA_GP[0] 7316.72 8040.88 GPIO_S0_SC[000] SATA_GP[0] - - -

Intel® Atom™ Processor E3800 Product Family

Datasheet 239
 Table 142. Ball Listing by Location with GPIO Muxed Functions (Sheet 39 of 47)
Location Ball Name X-Location Y-Location GPIO F0 GPIO F1 GPIO F2 GPIO F3 GPIO F6

BA14 VSS 6326.12 8040.88 - - - - -

BA16 SATA_RXN[1] 5335.52 8040.88 - - - - -

BA18 SD2_CLK 4362.2 8040.88 GPIO_S0_SC[027] SD2_CLK - - -

BA19 VSS 3887.22 7685.28 - - - - -

BA20 SD2_D[2] 3412.24 8040.88 GPIO_S0_SC[030] SD2_D[2] - - -

BA22 VSS 2438.91 8040.88 - - - - -

BA24 MMC1_RST# 1448.31 8040.88 GPIO_S0_SC[026] MMC1_RST# SATA_DEVSLP[0] MMC1_45_RST# -

BA26 SD3_D[3] 474.98 8040.88 GPIO_S0_SC[037] SD3_D[3] - - -

BA27 VSS 0 7685.28 - - - - -

BA28 SIO_SPI_MISO -474.98 8040.88 GPIO_S0_SC[067] SIO_SPI_MISO - - -

BA30 LPE_I2S2_FRM -1448.31 8040.88 GPIO_S0_SC[063] LPE_I2S2_FRM RESERVED - -

BA32 VSS -2438.91 8040.88 - - - - -

BA34 SIO_UART1_RTS# -3412.24 8040.88 GPIO_S0_SC[072] SIO_UART1_RTS# - - -

BA35 VSS -3887.22 7685.28 - - - - -

BA36 DRAM1_DQ[20] -4362.2 8040.88 - - - - -

BA38 DRAM1_DQSP[2] -5335.52 8040.88 - - - - -

BA40 VSS -6326.12 8040.88 - - - - -

BA42 DRAM1_DQ[02] -7316.72 8040.88 - - - - -

BA51 DRAM1_MA[13] -12070.59 7774.43 - - - - -

BA53 VSS -12814.05 7774.43 - - - - -

BB3 RESERVED 11928.86 8350.76 - - - - -

BB4 RESERVED 11257.79 8307.32 - - - - -

BB5 RSVD_GND[6] 10546.59 8307.32 - - - - -

BB7 RSVD_GND[7] 9835.39 8307.32 - - - - -

BB8 UNCORE_VNN_SENSE 9124.19 8307.32 - - - - -

Intel® Atom™ Processor E3800 Product Family

240 Datasheet
 Table 142. Ball Listing by Location with GPIO Muxed Functions (Sheet 40 of 47)
Location Ball Name X-Location Y-Location GPIO F0 GPIO F1 GPIO F2 GPIO F3 GPIO F6

BB10 RSVD_GND[4] 8307.32 8170.42 - - - - -

BB19 VSS 3887.22 8396.48 - - - - -

BB27 VSS 0 8396.48 - - - - -

BB35 VSS -3887.22 8396.48 - - - - -

BB44 DRAM1_MA[03] -8307.32 8170.42 - - - - -

BB46 DRAM_VDD_S4 -9124.19 8307.32 - - - - -

BB47 DRAM1_MA[01] -9835.39 8307.32 - - - - -

BB49 DRAM1_MA[06] -10546.59 8307.32 - - - - -

BB50 DRAM1_MA[04] -11257.79 8307.32 - - - - -

BB51 DRAM1_WE# -11928.86 8350.76 - - - - -

BC1 VGA_DDCCLK 12814.05 8620.51 VGA_DDCCLK - - - -

BC2 VGA_DDCDATA 12246.36 8852.15 VGA_DDCDATA - - - -

BC10 RSVD_GND[5] 8307.32 8763.76 - - - - -

BC12 GPIO_S0_SC[056] 7316.72 8752.08 GPIO_S0_SC[056] RESERVED - - -

BC14 GPIO_S0_SC[058] 6326.12 8752.08 GPIO_S0_SC[058] RESERVED - - -

BC16 GPIO_S0_SC[061] 5335.52 8752.08 GPIO_S0_SC[061] PCU_UART_RXD - - -

BC18 SD2_CMD 4362.2 8752.08 GPIO_S0_SC[032] SD2_CMD - - -

BC20 VSS 3412.24 8752.08 - - - - -

BC22 VSS 2438.91 8752.08 - - - - -

BC24 SD3_CD# 1448.31 8752.08 GPIO_S0_SC[038] SD3_CD# - - -

BC26 VSS 474.98 8752.08 - - - - -

BC28 VSS -474.98 8752.08 - - - - -

BC30 LPE_I2S2_DATAOUT -1448.31 8752.08 GPIO_S0_SC[065] LPE_I2S2_DATAOUT - - -

BC32 VSS -2438.91 8752.08 - - - - -

BC34 VSS -3412.24 8752.08 - - - - -

Intel® Atom™ Processor E3800 Product Family

Datasheet 241
 Table 142. Ball Listing by Location with GPIO Muxed Functions (Sheet 41 of 47)
Location Ball Name X-Location Y-Location GPIO F0 GPIO F1 GPIO F2 GPIO F3 GPIO F6

BC36 DRAM1_DM[2] -4362.2 8752.08 - - - - -

BC38 DRAM1_DQ[04] -5335.52 8752.08 - - - - -

BC40 DRAM1_DQ[01] -6326.12 8752.08 - - - - -

BC42 VSS -7316.72 8752.08 - - - - -

BC44 DRAM1_DQ[07] -8307.32 8763.76 - - - - -

BC52 DRAM1_MA[08] -12246.36 8852.15 - - - - -

BC53 DRAM1_MA[05] -12814.05 8620.51 - - - - -

BD1 VGA_V1P35_S3_F1 12814.05 9293.61 - - - - -

BD2 VGA_HSYNC 12220.7 9444.99 VGA_HSYNC - - - -

BD5 SD3_WP 10565.13 9301.73 GPIO_S0_SC[007] RESERVED SD3_WP - -

BD7 PCIE_CLKREQ[1]# 9712.2 9301.73 GPIO_S0_SC[004] PCIE_CLKREQ[1]# - - -

BD10 SATA_TXP[1] 8307.32 9457.18 - - - - -

BD12 GPIO_S0_SC[055] 7316.72 9463.28 GPIO_S0_SC[055] RESERVED - - -

BD14 GPIO_S0_SC[057] 6326.12 9463.28 GPIO_S0_SC[057] PCU_UART_TXD - - -

BD16 GPIO_S0_SC[060] 5335.52 9463.28 GPIO_S0_SC[060] RESERVED - - -

BD18 SD2_D[3]_CD# 4362.2 9463.28 GPIO_S0_SC[031] SD2_D[3]_CD# - - -

BD19 VSS 3887.22 9107.68 - - - - -

BD20 SD2_D[1] 3412.24 9463.28 GPIO_S0_SC[029] SD2_D[1] - - -

BD22 SD3_PWREN# 2438.91 9463.28 GPIO_S0_SC[041] SD3_PWREN# - - -

BD24 VSS 1448.31 9463.28 - - - - -

BD26 SD3_D[1] 525.02 9404.35 GPIO_S0_SC[035] SD3_D[1] - - -

BD27 VSS 0 9107.68 - - - - -

BD28 LPE_I2S2_DATAIN -525.02 9404.35 GPIO_S0_SC[064] LPE_I2S2_DATAIN - - -

BD30 VSS -1448.31 9463.28 - - - - -

BD32 SIO_UART2_RTS# -2438.91 9463.28 GPIO_S0_SC[076] SIO_UART2_RTS# - - -

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242 Datasheet
 Table 142. Ball Listing by Location with GPIO Muxed Functions (Sheet 42 of 47)
Location Ball Name X-Location Y-Location GPIO F0 GPIO F1 GPIO F2 GPIO F3 GPIO F6

BD34 SIO_UART2_TXD -3412.24 9463.28 GPIO_S0_SC[075] SIO_UART2_TXD - - -

BD35 VSS -3887.22 9107.68 - - - - -

BD36 DRAM1_DQ[05] -4362.2 9463.28 - - - - -

BD38 DRAM1_DM[0] -5335.52 9463.28 - - - - -

BD40 DRAM1_DQSN[0] -6326.12 9463.28 - - - - -

BD42 DRAM1_DQ[03] -7316.72 9463.28 - - - - -

BD44 DRAM1_CKE[2] -8307.32 9457.18 - - - - -

BD47 DRAM1_MA[12] -9712.2 9301.73 - - - - -

BD49 DRAM_VDD_S4 -10565.13 9301.73 - - - - -

BD52 DRAM_VDD_S4 -12220.7 9444.99 - - - - -

BD53 DRAM_VDD_S4 -12814.05 9293.61 - - - - -

BE1 VSS 12814.05 9992.11 - - - - -

BE2 VSS 12222.48 10038.33 - - - - -

BE3 PCIE_CLKREQ[3]# 11642.85 9579.86 GPIO_S0_SC[006] PCIE_CLKREQ[3]# - - -

BE8 VSS 9320.02 9747 - - - - -

BE19 VSS 3887.22 9818.88 - - - - -

BE35 VSS -3887.22 9818.88 - - - - -

BE46 RESERVED -9320.02 9747 - - - - -

BE51 DRAM1_MA[11] -11642.85 9579.86 - - - - -

BE52 DRAM1_MA[09] -12222.48 10038.33 - - - - -

BE53 VSS -12814.05 9992.11 - - - - -

BF2 VGA_VSYNC 12237.72 10631.68 VGA_VSYNC - - - -

BF4 VSS 11162.79 10162.79 - - - - -

BF6 SATA_TXP[0] 10112.76 10238.49 - - - - -

BF10 SATA_TXN[1] 8307.32 10168.38 - - - - -

Intel® Atom™ Processor E3800 Product Family

Datasheet 243
 Table 142. Ball Listing by Location with GPIO Muxed Functions (Sheet 43 of 47)
Location Ball Name X-Location Y-Location GPIO F0 GPIO F1 GPIO F2 GPIO F3 GPIO F6

BF12 VSS 7316.72 10137.14 - - - - -

BF14 GPIO_S0_SC[059] 6326.12 10136.63 GPIO_S0_SC[059] RESERVED - - -

BF16 VSS 5335.52 10136.63 - - - - -

BF18 LPC_RCOMP 4388.36 10136.63 LPC_RCOMP - - - -

BF20 HDA_LPE_RCOMP 3386.07 10136.63 - - - - -

BF22 SD3_1P8EN 2438.91 10136.63 GPIO_S0_SC[040] SD3_1P8EN - - -

BF24 VSS 1448.31 10136.63 - - - - -

BF26 SD3_RCOMP 462.79 9994.65 - - - - -

BF27 SIO_I2C4_DATA 0 10365.99 GPIO_S0_SC[086] SIO_I2C4_DATA - - -

BF28 LPE_I2S2_CLK -462.79 9994.65 GPIO_S0_SC[062] LPE_I2S2_CLK SATA_DEVSLP[1] RESERVED -

BF30 VSS -1448.31 10136.63 - - - - -

BF32 SIO_UART2_CTS# -2438.91 10136.63 GPIO_S0_SC[077] SIO_UART2_CTS# - - -

BF34 SIO_UART2_RXD -3386.07 10136.63 GPIO_S0_SC[074] SIO_UART2_RXD - - -

BF36 VSS -4388.36 10136.63 - - - - -

BF38 VSS -5335.52 10136.63 - - - - -

BF40 DRAM1_DQSP[0] -6326.12 10136.63 - - - - -

BF42 DRAM1_DQ[06] -7316.72 10137.14 - - - - -

BF44 DRAM_VDD_S4 -8307.32 10168.38 - - - - -

BF48 RESERVED -10112.76 10238.49 - - - - -

BF50 DRAM1_MA[07] -11162.79 10162.79 - - - - -

BF52 DRAM1_BS[2] -12237.72 10631.68 - - - - -

BG1 VSS 12814.05 10773.16 - - - - -

BG3 PCIE_CLKREQ[0]# 11644.38 10644.38 GPIO_S0_SC[003] PCIE_CLKREQ[0]# - - -

BG5 PCIE_CLKREQ[2]# 10579.86 10642.85 GPIO_S0_SC[005] PCIE_CLKREQ[2]# - - -

BG7 SATA_TXN[0] 9553.19 10709.15 - - - - -

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244 Datasheet
 Table 142. Ball Listing by Location with GPIO Muxed Functions (Sheet 44 of 47)
Location Ball Name X-Location Y-Location GPIO F0 GPIO F1 GPIO F2 GPIO F3 GPIO F6

BG9 PMC_RSTBTN# 8697.98 11028.17 PMC_RSTBTN# - - - -

BG11 PCU_SMB_ALERT# 7774.43 11070.59 GPIO_S0_SC[053] PCU_SMB_ALERT# - - -

BG12 PCU_SMB_DATA 7288.53 10729.98 GPIO_S0_SC[051] PCU_SMB_DATA - - -

BG13 ILB_LPC_SERIRQ 6802.63 11070.59 GPIO_S0_SC[050] ILB_LPC_SERIRQ - - -

BG14 ILB_LPC_AD[3] 6316.73 10729.98 GPIO_S0_SC[045] ILB_LPC_AD[3] - - -

BG15 ILB_LPC_CLK[0] 5830.82 11070.59 GPIO_S0_SC[047] ILB_LPC_CLK[0] - - -

BG16 ILB_LPC_CLKRUN# 5344.92 10729.98 GPIO_S0_SC[049] ILB_LPC_CLKRUN# - - -

BG17 ILB_LPC_FRAME# 4859.02 11070.59 GPIO_S0_SC[046] ILB_LPC_FRAME# - - -

BG18 GPIO_S0_SC[015] 4373.12 10729.98 GPIO_S0_SC[015] I2S1_DATAIN RESERVED - -

BG19 HDA_SDI[0] 3887.22 11070.59 GPIO_S0_SC[012] I2S1_CLK HDA_SDI[0] - -

BG20 HDA_SDO 3401.31 10729.98 GPIO_S0_SC[011] I2S0_DATAIN HDA_SDO - -

BG21 HDA_SDI[1] 2915.41 11070.59 GPIO_S0_SC[013] I2S1_FRM HDA_SDI[1] - -

BG22 HDA_RST# 2429.51 10729.98 GPIO_S0_SC[008] I2S0_CLK HDA_RST# - -

BG23 SIO_I2C0_CLK 1943.61 11070.59 GPIO_S0_SC[079] SIO_I2C0_CLK - - -

BG24 SIO_I2C1_DATA 1457.71 10729.98 GPIO_S0_SC[080] SIO_I2C1_DATA - - -

BG25 SIO_I2C2_DATA 971.8 11070.59 GPIO_S0_SC[082] SIO_I2C2_DATA - - -

BG26 SIO_I2C3_DATA 479.81 10715.24 GPIO_S0_SC[084] SIO_I2C3_DATA - - -

BG27 SIO_I2C4_CLK 0 11070.59 GPIO_S0_SC[087] SIO_I2C4_CLK - - -

BG28 SIO_I2C5_CLK -479.81 10715.24 GPIO_S0_SC[089] SIO_I2C5_CLK - - -

BG29 SIO_I2C6_CLK -971.8 11070.59 GPIO_S0_SC[091] SIO_I2C6_CLK SD3_WP - -

BG30 GPIO_S0_SC[093] -1457.71 10729.98 RESERVED GPIO_S0_SC[093] - - -

BG31 VSS -1943.61 11070.59 - - - - -

BG32 DRAM1_DQ[09] -2429.51 10729.98 - - - - -

BG33 DRAM1_DQ[12] -2915.41 11070.59 - - - - -

BG34 VSS -3401.31 10729.98 - - - - -

Intel® Atom™ Processor E3800 Product Family

Datasheet 245
 Table 142. Ball Listing by Location with GPIO Muxed Functions (Sheet 45 of 47)
Location Ball Name X-Location Y-Location GPIO F0 GPIO F1 GPIO F2 GPIO F3 GPIO F6

BG35 DRAM1_DQSP[1] -3887.22 11070.59 - - - - -

BG36 DRAM1_DQ[10] -4373.12 10729.98 - - - - -

BG37 DRAM1_DQ[14] -4859.02 11070.59 - - - - -

BG38 DRAM1_DQ[00] -5344.92 10729.98 - - - - -

BG39 VSS -5830.82 11070.59 - - - - -

BG40 DRAM1_DQ[28] -6316.73 10729.98 - - - - -

BG41 DRAM1_DQ[25] -6802.63 11070.59 - - - - -

BG42 VSS -7288.53 10729.98 - - - - -

BG43 DRAM1_DQSN[3] -7774.43 11070.59 - - - - -

BG45 VSS -8697.98 11028.17 - - - - -

BG47 DRAM1_CKE[0] -9553.19 10709.15 - - - - -

BG49 VSS -10579.86 10642.85 - - - - -

BG51 DRAM_VDD_S4 -11644.38 10644.38 - - - - -

BG53 VSS -12814.05 10773.16 - - - - -

BH1 VSS 12814.05 11382.76 - - - - -

BH2 VSS 12225.02 11225.02 - - - - -

BH4 PMC_PLT_CLK[2] 11631.68 11237.72 GPIO_S0_SC[098] PMC_PLT_CLK[2] - - -

BH5 PMC_PLT_CLK[1] 11038.33 11222.48 GPIO_S0_SC[097] PMC_PLT_CLK[1] - - -

BH6 PMC_PLT_CLK[4] 10444.99 11220.7 GPIO_S0_SC[100] PMC_PLT_CLK[4] - - -

BH7 PMC_PLT_CLK[0] 9851.64 11229.59 GPIO_S0_SC[096] PMC_PLT_CLK[0] - - -

BH8 PMC_PLT_CLK[3] 9258.3 11224.26 GPIO_S0_SC[099] PMC_PLT_CLK[3] - - -

BH10 PCU_SMB_CLK 8260.33 11428.98 GPIO_S0_SC[052] PCU_SMB_CLK - - -

BH12 ILB_8254_SPKR 7288.53 11428.98 GPIO_S0_SC[054] ILB_8254_SPKR RESERVED - -

BH14 ILB_LPC_CLK[1] 6316.73 11428.98 GPIO_S0_SC[048] ILB_LPC_CLK[1] - - -

BH16 ILB_LPC_AD[0] 5344.92 11428.98 GPIO_S0_SC[042] ILB_LPC_AD[0] - - -

Intel® Atom™ Processor E3800 Product Family

246 Datasheet
 Table 142. Ball Listing by Location with GPIO Muxed Functions (Sheet 46 of 47)
Location Ball Name X-Location Y-Location GPIO F0 GPIO F1 GPIO F2 GPIO F3 GPIO F6

BH18 GPIO_S0_SC[014] 4373.12 11428.98 GPIO_S0_SC[014] I2S1_DATAOUT RESERVED - -

BH20 HDA_SYNC 3401.31 11428.98 GPIO_S0_SC[009] I2S0_FRM HDA_SYNC - -

BH22 SIO_I2C0_DATA 2429.51 11428.98 GPIO_S0_SC[078] SIO_I2C0_DATA - - -

BH24 SIO_I2C1_CLK 1457.71 11428.98 GPIO_S0_SC[081] SIO_I2C1_CLK RESERVED - -

BH26 SIO_I2C3_CLK 485.9 11428.98 GPIO_S0_SC[085] SIO_I2C3_CLK - - -

BH28 SIO_I2C5_DATA -485.9 11428.98 GPIO_S0_SC[088] SIO_I2C5_DATA - - -

BH30 GPIO_S0_SC[092] -1457.71 11428.98 RESERVED GPIO_S0_SC[092] - - -

BH32 DRAM1_DQ[08] -2429.51 11428.98 - - - - -

BH34 DRAM1_DQSN[1] -3401.31 11428.98 - - - - -

BH36 DRAM1_DM[1] -4373.12 11428.98 - - - - -

BH38 DRAM1_DQ[15] -5344.92 11428.98 - - - - -

BH40 DRAM1_DQ[29] -6316.73 11428.98 - - - - -

BH42 DRAM1_DM[3] -7288.53 11428.98 - - - - -

BH44 DRAM1_DQSP[3] -8260.33 11428.98 - - - - -

BH46 DRAM1_DQ[27] -9258.3 11224.26 - - - - -

BH47 DRAM1_DQ[31] -9851.64 11229.59 - - - - -

BH48 DRAM1_DQ[30] -10444.99 11220.7 - - - - -

BH49 DRAM1_MA[14] -11038.33 11222.48 - - - - -

BH50 DRAM1_MA[15] -11631.68 11237.72 - - - - -

BH52 VSS -12225.02 11225.02 - - - - -

BH53 VSS -12814.05 11382.76 - - - - -

BJ2 VSS 12382.75 11814.05 - - - - -

BJ3 VSS 11773.15 11814.05 - - - - -

BJ5 VSS 10992.1 11814.05 - - - - -

BJ6 VGA_V1P0_S3 10293.6 11814.05 - - - - -

Intel® Atom™ Processor E3800 Product Family

Datasheet 247
 Table 142. Ball Listing by Location with GPIO Muxed Functions (Sheet 47 of 47)
Location Ball Name X-Location Y-Location GPIO F0 GPIO F1 GPIO F2 GPIO F3 GPIO F6

BJ7 VSS 9620.5 11814.05 - - - - -

BJ9 PMC_PLT_CLK[5] 8746.24 11814.05 GPIO_S0_SC[101] PMC_PLT_CLK[5] - - -

BJ11 VSS 7774.43 11814.05 - - - - -

BJ13 ILB_LPC_AD[2] 6802.63 11814.05 GPIO_S0_SC[044] ILB_LPC_AD[2] - - -

BJ15 VSS 5830.82 11814.05 - - - - -

BJ17 ILB_LPC_AD[1] 4859.02 11814.05 GPIO_S0_SC[043] ILB_LPC_AD[1] - - -

BJ19 VSS 3887.22 11814.05 - - - - -

BJ21 HDA_CLK 2915.41 11814.05 GPIO_S0_SC[010] I2S0_DATAOUT HDA_CLK - -

BJ23 VSS 1943.61 11814.05 - - - - -

BJ25 SIO_I2C2_CLK 971.8 11814.05 GPIO_S0_SC[083] SIO_I2C2_CLK - - -

BJ27 VSS 0 11814.05 - - - - -

BJ29 SIO_I2C6_DATA -971.8 11814.05 GPIO_S0_SC[090] SIO_I2C6_DATA ILB_NMI - -

BJ31 VSS -1943.61 11814.05 - - - - -

BJ33 DRAM1_DQ[13] -2915.41 11814.05 - - - - -

BJ35 VSS -3887.22 11814.05 - - - - -

BJ37 DRAM1_DQ[11] -4859.02 11814.05 - - - - -

BJ39 VSS -5830.82 11814.05 - - - - -

BJ41 DRAM1_DQ[24] -6802.63 11814.05 - - - - -

BJ43 VSS -7774.43 11814.05 - - - - -

BJ45 DRAM1_DQ[26] -8746.24 11814.05 - - - - -

BJ47 VSS -9620.5 11814.05 - - - - -

BJ48 DRAM_VDD_S4 -10293.6 11814.05 - - - - -

BJ49 VSS -10992.1 11814.05 - - - - -

BJ51 VSS -11773.15 11814.05 - - - - -

BJ52 VSS -12382.75 11814.05 - - - - -

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248 Datasheet
10.4 Alphabetical Ball Name List
Ball Name Location Ball Name Location Ball Name Location

CORE_V1P05_S3 U33 DDI0_TXN[0] AV2 DRAM0_CS[2]# P45

CORE_V1P05_S3 U35 DDI0_TXN[1] AT3 DRAM0_DM[0] G36

CORE_V1P05_S3 V33 DDI0_TXN[2] AR1 DRAM0_DM[1] B36

CORE_V1P05_S3 Y32 DDI0_TXN[3] AP2 DRAM0_DM[2] F38

CORE_V1P05_S3 AA33 DDI0_TXP[0] AV3 DRAM0_DM[3] B42

CORE_V1P05_S3 AC32 DDI0_TXP[1] AT2 DRAM0_DM[4] P51

CORE_V1P05_S3 AF33 DDI0_TXP[2] AR3 DRAM0_DM[5] V42

CORE_V1P05_S3 AG33 DDI0_TXP[3] AP3 DRAM0_DM[6] Y50

CORE_V1P05_S3 AG35 DDI0_VDDEN B28 DRAM0_DM[7] Y52

CORE_VCC_S3 P26 DDI1_AUXN AK2 DRAM0_DQ[00] M36

CORE_VCC_S3 P27 DDI1_AUXP AK3 DRAM0_DQ[01] J36

CORE_VCC_S3 U27 DDI1_BKLTCTL M30 DRAM0_DQ[02] P40

CORE_VCC_S3 U29 DDI1_BKLTEN J30 DRAM0_DQ[03] M40

CORE_VCC_S3 V27 DDI1_DDCCLK G30 DRAM0_DQ[04] P36

CORE_VCC_S3 V29 DDI1_DDCDATA P30 DRAM0_DQ[05] N36

CORE_VCC_S3 V30 DDI1_HPD K30 DRAM0_DQ[06] K40

CORE_VCC_S3 Y27 DDI1_TXN[0] AG1 DRAM0_DQ[07] K42

CORE_VCC_S3 Y29 DDI1_TXN[1] AF2 DRAM0_DQ[08] B32

CORE_VCC_S3 Y30 DDI1_TXN[2] AD2 DRAM0_DQ[09] C32

CORE_VCC_S3 AA27 DDI1_TXN[3] AC1 DRAM0_DQ[10] C36

CORE_VCC_S3 AA29 DDI1_TXP[0] AG3 DRAM0_DQ[11] A37

CORE_VCC_S3 AA30 DDI1_TXP[1] AF3 DRAM0_DQ[12] C33

CORE_VCC_S3 AC27 DDI1_TXP[2] AD3 DRAM0_DQ[13] A33

CORE_VCC_S3 AC29 DDI1_TXP[3] AC3 DRAM0_DQ[14] C37

CORE_VCC_S3 AC30 DDI1_VDDEN N30 DRAM0_DQ[15] B38

CORE_VCC_S3 AD27 DDI_RCOMP_N AK13 DRAM0_DQ[16] F36

CORE_VCC_S3 AD29 DDI_RCOMP_P AK12 DRAM0_DQ[17] G38

CORE_VCC_S3 AD30 DDI_V1P0_S3 AJ18 DRAM0_DQ[18] F42

CORE_VCC_S3 AF27 DDI_V1P0_S3 AK19 DRAM0_DQ[19] J42

CORE_VCC_S3 AF29 DDI_V1P0_S3 AK21 DRAM0_DQ[20] G40

CORE_VCC_S3 AG27 DDI_V1P0_S3 AM16 DRAM0_DQ[21] C38

CORE_VCC_S3 AG29 DRAM0_BS[0] K47 DRAM0_DQ[22] G44

CORE_VCC_S3 AG30 DRAM0_BS[1] K44 DRAM0_DQ[23] D42

CORE_VCC_SENSE P28 DRAM0_BS[2] D52 DRAM0_DQ[24] A41

CORE_VSS_SENSE N28 DRAM0_CAS# M44 DRAM0_DQ[25] C41

DDI0_AUXN AL1 DRAM0_CKE[0] C47 DRAM0_DQ[26] A45

DDI0_AUXP AL3 DRAM0_CKE[2] F44 DRAM0_DQ[27] B46

DDI0_BKLTCTL B26 DRAM0_CKN[0] M48 DRAM0_DQ[28] C40

DDI0_BKLTEN C27 DRAM0_CKN[2] P48 DRAM0_DQ[29] B40

DDI0_DDCCLK C28 DRAM0_CKP[0] M50 DRAM0_DQ[30] B48

DDI0_DDCDATA C26 DRAM0_CKP[2] P50 DRAM0_DQ[31] B47

DDI0_HPD D27 DRAM0_CS[0]# P44 DRAM0_DQ[32] K52

Intel® Atom™ Processor E3800 Product Family

Datasheet 249
 Ball Name Location Ball Name Location Ball Name Location

DRAM0_DQ[33] K51 DRAM0_DQSP[5] T42 DRAM1_DQ[00] BG38

DRAM0_DQ[34] T52 DRAM0_DQSP[6] Y47 DRAM1_DQ[01] BC40
DRAM0_DQ[35] T51 DRAM0_DQSP[7] AB52 DRAM1_DQ[02] BA42
DRAM0_DQ[36] L51 DRAM0_DRAMRST# P41 DRAM1_DQ[03] BD42
DRAM0_DQ[37] L53 DRAM0_MA[00] K45 DRAM1_DQ[04] BC38
DRAM0_DQ[38] R51 DRAM0_MA[01] H47 DRAM1_DQ[05] BD36
DRAM0_DQ[39] R53 DRAM0_MA[02] L41 DRAM1_DQ[06] BF42
DRAM0_DQ[40] T47 DRAM0_MA[03] H44 DRAM1_DQ[07] BC44
DRAM0_DQ[41] T45 DRAM0_MA[04] H50 DRAM1_DQ[08] BH32
DRAM0_DQ[42] Y40 DRAM0_MA[05] G53 DRAM1_DQ[09] BG32
DRAM0_DQ[43] V41 DRAM0_MA[06] H49 DRAM1_DQ[10] BG36
DRAM0_DQ[44] T48 DRAM0_MA[07] D50 DRAM1_DQ[11] BJ37
DRAM0_DQ[45] T50 DRAM0_MA[08] G52 DRAM1_DQ[12] BG33
DRAM0_DQ[46] Y42 DRAM0_MA[09] E52 DRAM1_DQ[13] BJ33
DRAM0_DQ[47] AB40 DRAM0_MA[10] K48 DRAM1_DQ[14] BG37
DRAM0_DQ[48] V45 DRAM0_MA[11] E51 DRAM1_DQ[15] BH38
DRAM0_DQ[49] V47 DRAM0_MA[12] F47 DRAM1_DQ[16] AU36
DRAM0_DQ[50] AD48 DRAM0_MA[13] J51 DRAM1_DQ[17] AT36
DRAM0_DQ[51] AD50 DRAM0_MA[14] B49 DRAM1_DQ[18] AV40
DRAM0_DQ[52] V48 DRAM0_MA[15] B50 DRAM1_DQ[19] AT40
DRAM0_DQ[53] V50 DRAM0_ODT[0] T41 DRAM1_DQ[20] BA36
DRAM0_DQ[54] AB44 DRAM0_ODT[2] P42 DRAM1_DQ[21] AV36
DRAM0_DQ[55] Y45 DRAM0_RAS# M45 DRAM1_DQ[22] AY42
DRAM0_DQ[56] V52 DRAM0_WE# H51 DRAM1_DQ[23] AY40
DRAM0_DQ[57] W51 DRAM1_BS[0] AY47 DRAM1_DQ[24] BJ41
DRAM0_DQ[58] AC53 DRAM1_BS[1] AY44 DRAM1_DQ[25] BG41
DRAM0_DQ[59] AC51 DRAM1_BS[2] BF52 DRAM1_DQ[26] BJ45
DRAM0_DQ[60] W53 DRAM1_CAS# AV44 DRAM1_DQ[27] BH46
DRAM0_DQ[61] Y51 DRAM1_CKE[0] BG47 DRAM1_DQ[28] BG40
DRAM0_DQ[62] AD52 DRAM1_CKE[2] BD44 DRAM1_DQ[29] BH40
DRAM0_DQ[63] AD51 DRAM1_CKN[0] AV48 DRAM1_DQ[30] BH48
DRAM0_DQSN[0] K38 DRAM1_CKN[2] AT48 DRAM1_DQ[31] BH47
DRAM0_DQSN[1] B34 DRAM1_CKP[0] AV50 DRAM1_DQ[32] AY52
DRAM0_DQSN[2] F40 DRAM1_CKP[2] AT50 DRAM1_DQ[33] AY51
DRAM0_DQSN[3] C43 DRAM1_CS[0]# AT44 DRAM1_DQ[34] AP52
DRAM0_DQSN[4] M52 DRAM1_CS[2]# AT45 DRAM1_DQ[35] AP51
DRAM0_DQSN[5] T44 DRAM1_DM[0] BD38 DRAM1_DQ[36] AW51
DRAM0_DQSN[6] Y48 DRAM1_DM[1] BH36 DRAM1_DQ[37] AW53
DRAM0_DQSN[7] AA51 DRAM1_DM[2] BC36 DRAM1_DQ[38] AR51
DRAM0_DQSP[0] J38 DRAM1_DM[3] BH42 DRAM1_DQ[39] AR53
DRAM0_DQSP[1] C35 DRAM1_DM[4] AT51 DRAM1_DQ[40] AP47
DRAM0_DQSP[2] D40 DRAM1_DM[5] AM42 DRAM1_DQ[41] AP45
DRAM0_DQSP[3] B44 DRAM1_DM[6] AK50 DRAM1_DQ[42] AK40
DRAM0_DQSP[4] N53 DRAM1_DM[7] AK52 DRAM1_DQ[43] AM41

Intel® Atom™ Processor E3800 Product Family

250 Datasheet
 Ball Name Location Ball Name Location Ball Name Location

DRAM1_DQ[44] AP48 DRAM1_MA[07] BF50 DRAM_VDD_S4 BB46

DRAM1_DQ[45] AP50 DRAM1_MA[08] BC52 DRAM_VDD_S4 BD49
DRAM1_DQ[46] AK42 DRAM1_MA[09] BE52 DRAM_VDD_S4 BD52
DRAM1_DQ[47] AH40 DRAM1_MA[10] AY48 DRAM_VDD_S4 BD53
DRAM1_DQ[48] AM45 DRAM1_MA[11] BE51 DRAM_VDD_S4 BF44
DRAM1_DQ[49] AM47 DRAM1_MA[12] BD47 DRAM_VDD_S4 BG51
DRAM1_DQ[50] AF48 DRAM1_MA[13] BA51 DRAM_VDD_S4 BJ48
DRAM1_DQ[51] AF50 DRAM1_MA[14] BH49 DRAM_VDD_S4_PWROK AD42
DRAM1_DQ[52] AM48 DRAM1_MA[15] BH50 DRAM_VREF AF44
DRAM1_DQ[53] AM50 DRAM1_ODT[0] AP41 GPIO_RCOMP N26
DRAM1_DQ[54] AH44 DRAM1_ODT[2] AT42 RESERVED B30
DRAM1_DQ[55] AK45 DRAM1_RAS# AV45 GPIO_S0_SC[014] BH18
DRAM1_DQ[56] AM52 DRAM1_WE# BB51 GPIO_S0_SC[015] BG18
DRAM1_DQ[57] AL51 DRAM_CORE_PWROK AB42 GPIO_S0_SC[055] BD12
DRAM1_DQ[58] AG53 DRAM_RCOMP[0] AD44 GPIO_S0_SC[056] BC12
DRAM1_DQ[59] AG51 DRAM_RCOMP[1] AF45 GPIO_S0_SC[057] BD14
DRAM1_DQ[60] AL53 DRAM_RCOMP[2] AD45 GPIO_S0_SC[058] BC14
DRAM1_DQ[61] AK51 DRAM_V1P0_S3 Y35 GPIO_S0_SC[059] BF14
DRAM1_DQ[62] AF52 DRAM_V1P0_S3 Y36 GPIO_S0_SC[060] BD16
DRAM1_DQ[63] AF51 DRAM_V1P0_S3 AA36 GPIO_S0_SC[061] BC16
DRAM1_DQSN[0] BD40 DRAM_V1P0_S3 AD35 GPIO_S0_SC[092] BH30
DRAM1_DQSN[1] BH34 DRAM_V1P0_S3 AF35 GPIO_S0_SC[093] BG30
DRAM1_DQSN[2] AY38 DRAM_V1P0_S3 AF36 GPIO_S5[00] B18
DRAM1_DQSN[3] BG43 DRAM_V1P0_S3 AJ36 GPIO_S5[01] B16
DRAM1_DQSN[4] AV52 DRAM_V1P0_S3 AK35 GPIO_S5[02] C18
DRAM1_DQSN[5] AP44 DRAM_V1P0_S3 AK36 GPIO_S5[03] A17
DRAM1_DQSN[6] AK48 DRAM_V1P35_S3_F1 AD36 GPIO_S5[04] C17
DRAM1_DQSN[7] AJ51 DRAM_VDD_S4 A48 GPIO_S5[05] C16
DRAM1_DQSP[0] BF40 DRAM_VDD_S4 C51 GPIO_S5[06] B14
DRAM1_DQSP[1] BG35 DRAM_VDD_S4 D44 GPIO_S5[07] C15
DRAM1_DQSP[2] BA38 DRAM_VDD_S4 F49 GPIO_S5[08] C13
DRAM1_DQSP[3] BH44 DRAM_VDD_S4 F52 GPIO_S5[09] A13
DRAM1_DQSP[4] AU53 DRAM_VDD_S4 F53 GPIO_S5[10] C19
DRAM1_DQSP[5] AP42 DRAM_VDD_S4 H46 GPIO_S5[13] F18
DRAM1_DQSP[6] AK47 DRAM_VDD_S4 M41 GPIO_S5[17] J24
DRAM1_DQSP[7] AH52 DRAM_VDD_S4 M42 GPIO_S5[22] K24
DRAM1_DRAMRST# AT41 DRAM_VDD_S4 V38 GPIO_S5[23] N24
DRAM1_MA[00] AY45 DRAM_VDD_S4 Y38 GPIO_S5[24] M20
DRAM1_MA[01] BB47 DRAM_VDD_S4 AD38 GPIO_S5[25] J18
DRAM1_MA[02] AW41 DRAM_VDD_S4 AF38 GPIO_S5[26] M18
DRAM1_MA[03] BB44 DRAM_VDD_S4 AK38 GPIO_S5[27] K18
DRAM1_MA[04] BB50 DRAM_VDD_S4 AM38 GPIO_S5[28] K20
DRAM1_MA[05] BC53 DRAM_VDD_S4 AV41 GPIO_S5[29] M22
DRAM1_MA[06] BB49 DRAM_VDD_S4 AV42 GPIO_S5[30] M24

Intel® Atom™ Processor E3800 Product Family

Datasheet 251
 Ball Name Location Ball Name Location Ball Name Location

GPIO_V1P0_S3 AN25 MCSI1_DN[2] V10 PCIE_CLKP[0] AF4

HDA_CLK BJ21 MCSI1_DN[3] T12 PCIE_CLKP[1] AF7
HDA_LPE_RCOMP BF20 MCSI1_DP[0] AB12 PCIE_CLKP[2] AK6
HDA_LPE_V1P5V1P8_S3 AM32 MCSI1_DP[1] Y13 PCIE_CLKP[3] AM6
HDA_RST# BG22 MCSI1_DP[2] V9 PCIE_CLKREQ[0]# BG3
HDA_SDI[0] BG19 MCSI1_DP[3] T10 PCIE_CLKREQ[1]# BD7
HDA_SDI[1] BG21 MCSI2_CLKN V14 PCIE_CLKREQ[2]# BG5
HDA_SDO BG20 MCSI2_CLKP V13 PCIE_CLKREQ[3]# BE3
HDA_SYNC BH20 MCSI2_DN[0] T14 PCIE_RCOMP_N AP13
ICLK_DRAM_TERM[0] AF42 MCSI2_DP[0] T13 PCIE_RCOMP_P AP14
ICLK_DRAM_TERM[1] AH42 MCSI3_CLKN T6 PCIE_RXN[0] AT13
ICLK_ICOMP AD14 MCSI3_CLKP T4 PCIE_RXN[1] AT9
ICLK_OSCIN AH12 MCSI_GPIO[00] F34 PCIE_RXN[2] AP10
ICLK_OSCOUT AH10 MCSI_GPIO[01] M32 PCIE_RXN[3] AP7
ICLK_RCOMP AD13 MCSI_GPIO[02] D28 PCIE_RXP[0] AT14
ICLK_USB_TERM[0] F10 MCSI_GPIO[03] J28 PCIE_RXP[1] AT10
ICLK_USB_TERM[1] D10 MCSI_GPIO[04] K34 PCIE_RXP[2] AP12
ICLK_V1P35_S3_F1 AJ19 MCSI_GPIO[05] D34 PCIE_RXP[3] AP9
ICLK_V1P35_S3_F2 AG18 MCSI_GPIO[06] F32 PCIE_SATA_V1P0_S3 AN18
ILB_8254_SPKR BH12 MCSI_GPIO[07] F28 PCIE_TXN[0] AY6
ILB_LPC_AD[0] BH16 MCSI_GPIO[08] K28 PCIE_TXN[1] AV4
ILB_LPC_AD[1] BJ17 MCSI_GPIO[09] J34 PCIE_TXN[2] AT6
ILB_LPC_AD[2] BJ13 MCSI_GPIO[10] N32 PCIE_TXN[3] AP4
ILB_LPC_AD[3] BG14 MCSI_GPIO[11] D32 PCIE_TXP[0] AY7
ILB_LPC_CLK[0] BG15 MCSI_RCOMP P14 PCIE_TXP[1] AV6
ILB_LPC_CLK[1] BH14 MIPI_V1P8_S3 U38 PCIE_TXP[2] AT7
ILB_LPC_CLKRUN# BG16 MIPI_V1P24_S3 AD16 PCIE_TXP[3] AP6
ILB_LPC_FRAME# BG17 MIPI_V1P24_S3 AD18 PCIE_V1P0_S3 AK18
ILB_LPC_SERIRQ BG13 MMC1_CLK AT22 PCIE_V1P0_S3 AM18
ILB_RTC_EXTPAD B8 MMC1_CMD AV26 PCIE_V1P0_S3 AM21
ILB_RTC_RST# C12 MMC1_D[0] AV20 PCIE_V1P0_S3 AN21
ILB_RTC_TEST# C11 MMC1_D[1] AU22 PCU_SMB_ALERT# BG11
ILB_RTC_X1 C9 MMC1_D[2] AV22 PCU_SMB_CLK BH10
ILB_RTC_X2 A9 MMC1_D[3] AT20 PCU_SMB_DATA BG12
LPC_RCOMP BF18 MMC1_D[4] AY24 PCU_SPI_CLK C22
LPC_V1P8V3P3_S3 AM27 MMC1_D[5] AU26 PCU_SPI_CS[0]# C23
LPE_I2S2_CLK BF28 MMC1_D[6] AT26 PCU_SPI_CS[1]# C21
LPE_I2S2_DATAIN BD28 MMC1_D[7] AU20 PCU_SPI_MISO B22
LPE_I2S2_DATAOUT BC30 MMC1_RCOMP AY18 PCU_SPI_MOSI A21
LPE_I2S2_FRM BA30 MMC1_RST# BA24 PCU_V1P8_G3 V25
MCSI1_CLKN T7 PCIE_CLKN[0] AF6 PCU_V3P3_G3 N22
MCSI1_CLKP T9 PCIE_CLKN[1] AF9 PMC_ACPRESENT D20
MCSI1_DN[0] AB13 PCIE_CLKN[2] AK4 PMC_BATLOW# K26
MCSI1_DN[1] Y12 PCIE_CLKN[3] AM4 PMC_CORE_PWROK B7

Intel® Atom™ Processor E3800 Product Family

252 Datasheet
 Ball Name Location Ball Name Location Ball Name Location

PMC_PLT_CLK[0] BH7 RESERVED Y2 SATA_GP[0] BA12

PMC_PLT_CLK[1] BH5 RESERVED Y3 SATA_GP[1] AY14
PMC_PLT_CLK[2] BH4 RESERVED Y4 SATA_LED# AY12
PMC_PLT_CLK[3] BH8 RESERVED Y6 SATA_RCOMP_N AT18
PMC_PLT_CLK[4] BH6 RESERVED AB2 SATA_RCOMP_P AU18
PMC_PLT_CLK[5] BJ9 RESERVED AB3 SATA_RXN[0] AV16
PMC_PLTRST# F20 RESERVED AB7 SATA_RXN[1] BA16
PMC_PWRBTN# J26 RESERVED AB9 SATA_RXP[0] AU16
PMC_RSMRST# B10 RESERVED AB14 SATA_RXP[1] AY16
PMC_RSTBTN# BG9 RESERVED AD4 SATA_TXN[0] BG7
PMC_SLP_S3# D22 RESERVED AD6 SATA_TXN[1] BF10
PMC_SLP_S4# F22 RESERVED AD9 SATA_TXP[0] BF6
PMC_SUS_STAT# G18 RESERVED AD10 SATA_TXP[1] BD10
PMC_SUSCLK[0] G24 RESERVED AD12 SATA_V1P0_S3 AN19
PMC_SUSPWRDNACK D26 RESERVED AD40 SD2_CLK BA18
PMC_V1P8_G3 U25 RESERVED AD41 SD2_CMD BC18
PMC_WAKE_PCIE[0]# F26 RESERVED AF13 SD2_D[0] AY20
PROCHOT# C24 RESERVED AF14 SD2_D[1] BD20
RESERVED A29 RESERVED AF40 SD2_D[2] BA20
RESERVED C29 RESERVED AF41 SD2_D[3]_CD# BD18
RESERVED C30 RESERVED AH13 SD3_1P8EN BF22
RESERVED D48 RESERVED AH14 SD3_CD# BC24
RESERVED E46 RESERVED AK7 SD3_CLK AY26
RESERVED F1 RESERVED AK9 SD3_CMD AV28
RESERVED H4 RESERVED AM9 SD3_D[0] AT28
RESERVED H5 RESERVED AM10 SD3_D[1] BD26
RESERVED H7 RESERVED AM13 SD3_D[2] AU28
RESERVED H8 RESERVED AM14 SD3_D[3] BA26
RESERVED M9 RESERVED AT34 SD3_PWREN# BD22
RESERVED M10 RESERVED AV9 SD3_RCOMP BF26
RESERVED N34 RESERVED AV10 SD3_V1P8V3P3_S3 AN27
RESERVED P6 RESERVED BB3 SD3_WP BD5
RESERVED P7 RESERVED BB4 SIO_I2C0_CLK BG23
RESERVED P34 RESERVED BE46 SIO_I2C0_DATA BH22
RESERVED R1 RESERVED BF48 SIO_I2C1_CLK BH24
RESERVED R3 RSVD_GND[0] AM3 SIO_I2C1_DATA BG24
RESERVED T2 RSVD_GND[1] AM2 SIO_I2C2_CLK BJ25
RESERVED T3 RSVD_GND[2] AH3 SIO_I2C2_DATA BG25
RESERVED V2 RSVD_GND[3] AH2 SIO_I2C3_CLK BH26
RESERVED V3 RSVD_GND[4] BB10 SIO_I2C3_DATA BG26
RESERVED V4 RSVD_GND[5] BC10 SIO_I2C4_CLK BG27
RESERVED V6 RSVD_GND[6] BB5 SIO_I2C4_DATA BF27
RESERVED W1 RSVD_GND[7] BB7 SIO_I2C5_CLK BG28
RESERVED W3 RTC_VCC P22 SIO_I2C5_DATA BH28

Intel® Atom™ Processor E3800 Product Family

Datasheet 253
 Ball Name Location Ball Name Location Ball Name Location

SIO_I2C6_CLK BG29 UNCORE_V1P8_S3 AN32 USB_HSIC1_DATA E2

SIO_I2C6_DATA BJ29 UNCORE_V1P35_S3_F1 AG19 USB_HSIC1_STROBE D2
SIO_PWM[0] AU32 UNCORE_V1P35_S3_F2 AG32 USB_HSIC_RCOMP A7
SIO_PWM[1] AT32 UNCORE_V1P35_S3_F3 V36 USB_HSIC_V1P24_G3 V18
SIO_SPI_CLK AY30 UNCORE_V1P35_S3_F4 U36 USB_OC[0]# C20
SIO_SPI_CS# AV32 UNCORE_V1P35_S3_F5 AA25 USB_OC[1]# B20
SIO_SPI_MISO BA28 UNCORE_V1P35_S3_F6 AF19 USB_PLL_MON M13
SIO_SPI_MOSI AY28 UNCORE_VNN_S3 AA24 USB_RCOMPI C7
SIO_UART1_CTS# AY34 UNCORE_VNN_S3 AC22 USB_RCOMPO D6
SIO_UART1_RTS# BA34 UNCORE_VNN_S3 AC24 USB_ULPI_CLK G2
SIO_UART1_RXD AU34 UNCORE_VNN_S3 AD22 USB_ULPI_DATA[0] M3
SIO_UART1_TXD AV34 UNCORE_VNN_S3 AD24 USB_ULPI_DATA[1] L1
SIO_UART2_CTS# BF32 UNCORE_VNN_S3 AF22 USB_ULPI_DATA[2] K2
SIO_UART2_RTS# BD32 UNCORE_VNN_S3 AF24 USB_ULPI_DATA[3] K3
SIO_UART2_RXD BF34 UNCORE_VNN_S3 AG22 USB_ULPI_DATA[4] M2
SIO_UART2_TXD BD34 UNCORE_VNN_S3 AG24 USB_ULPI_DATA[5] N3
SVID_ALERT# B24 UNCORE_VNN_S3 AJ22 USB_ULPI_DATA[6] P2
SVID_CLK C25 UNCORE_VNN_S3 AJ24 USB_ULPI_DATA[7] L3
SVID_DATA A25 UNCORE_VNN_S3 AK22 USB_ULPI_DIR J3
SVID_V1P0_S3 V32 UNCORE_VNN_S3 AK24 USB_ULPI_NXT P3
TAP_PRDY# D18 UNCORE_VNN_S3 AK25 USB_ULPI_REFCLK B12
TAP_PREQ# F16 UNCORE_VNN_S3 AK27 USB_ULPI_RST# J20
TAP_TCK D14 UNCORE_VNN_S3 AK29 USB_ULPI_STP H3
TAP_TDI F12 UNCORE_VNN_S3 AK30 USB_ULPI_V1P8_G3 AA18
TAP_TDO G16 UNCORE_VNN_S3 AK32 USB_V1P0_S3 M14
TAP_TMS F14 UNCORE_VNN_S3 AM22 USB_V1P0_S3 U18
TAP_TRST# G12 UNCORE_VNN_SENSE BB8 USB_V1P0_S3 U19
TP2_CORE_VCC_S3 AA22 USB3_REXT[0] M12 USB_V1P8_G3 N20
TP_CORE_V1P05_S4 AF30 USB3_RXN[0] E3 USB_V3P3_G3 N18
UNCORE_V1P0_G3 B6 USB3_RXP[0] D4 USB_V3P3_G3 P18
UNCORE_V1P0_G3 C5 USB3_TXN[0] K7 USB_VSSA U16
UNCORE_V1P0_G3 U22 USB3_TXP[0] K6 USB3DEV_REXT[0] M7
UNCORE_V1P0_G3 V22 USB3_V1P0_G3 C3 USB3DEV_RXN[0] P12
UNCORE_V1P0_S3 V24 USB3_V1P0_G3 Y19 USB3DEV_RXP[0] P10
UNCORE_V1P0_S3 Y22 USB_DN[0] K16 USB3DEV_TXN[0] M6
UNCORE_V1P0_S3 Y24 USB_DN[1] G14 USB3DEV_TXP[0] M4
UNCORE_V1P0_S3 AF16 USB_DN[2] J12 USB3DEV_V1P0_S3 G1
UNCORE_V1P0_S3 AF18 USB_DN[3] H10 USB3DEV_V1P0_S3 Y18
UNCORE_V1P0_S3 AF21 USB_DP[0] M16 VGA_BLUE AY2
UNCORE_V1P0_S3 AG21 USB_DP[1] J14 VGA_DDCCLK BC1
UNCORE_V1P0_S3 AN29 USB_DP[2] K12 VGA_DDCDATA BC2
UNCORE_V1P0_S3 AN30 USB_DP[3] K10 VGA_GREEN BA1
UNCORE_V1P8_G3 U24 USB_HSIC0_DATA B4 VGA_HSYNC BD2
UNCORE_V1P8_S3 AM30 USB_HSIC0_STROBE B5 VGA_IREF AW1

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 Ball Name Location Ball Name Location Ball Name Location

VGA_IRTN AY3 VSS E53 VSS M34

VGA_RED BA3 VSS F2 VSS M35
VGA_V1P0_S3 BJ6 VSS F5 VSS M38
VGA_V1P35_S3_F1 BD1 VSS F7 VSS M47
VGA_V3P3_S3 AN24 VSS F19 VSS M51
VGA_VSYNC BF2 VSS F24 VSS N1
VSS A3 VSS F27 VSS N16
VSS A5 VSS F30 VSS N38
VSS A6 VSS F35 VSS N51
VSS A11 VSS G10 VSS P4
VSS A15 VSS G20 VSS P9
VSS A19 VSS G22 VSS P13
VSS A23 VSS G26 VSS P16
VSS A27 VSS G28 VSS P19
VSS A31 VSS G32 VSS P20
VSS A35 VSS G34 VSS P24
VSS A39 VSS G42 VSS P32
VSS A43 VSS H19 VSS P35
VSS A47 VSS H27 VSS P38
VSS A49 VSS H35 VSS P47
VSS A51 VSS J1 VSS P52
VSS A52 VSS J16 VSS T40
VSS B2 VSS J19 VSS U1
VSS B52 VSS J22 VSS U3
VSS B53 VSS J27 VSS U5
VSS C1 VSS J32 VSS U6
VSS C14 VSS J35 VSS U8
VSS C31 VSS J40 VSS U9
VSS C34 VSS J53 VSS U11
VSS C39 VSS K4 VSS U12
VSS C42 VSS K9 VSS U14
VSS C45 VSS K14 VSS U21
VSS C49 VSS K22 VSS U30
VSS C53 VSS K32 VSS U32
VSS D12 VSS K36 VSS U40
VSS D16 VSS K50 VSS U42
VSS D24 VSS L13 VSS U43
VSS D30 VSS L19 VSS U45
VSS D36 VSS L27 VSS U46
VSS D38 VSS L35 VSS U48
VSS E1 VSS M19 VSS U49
VSS E8 VSS M26 VSS U51
VSS E19 VSS M27 VSS U53
VSS E35 VSS M28 VSS V7

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 Ball Name Location Ball Name Location Ball Name Location

VSS V12 VSS AC38 VSS AH51

VSS V16 VSS AD7 VSS AJ1
VSS V19 VSS AD19 VSS AJ3
VSS V21 VSS AD21 VSS AJ16
VSS V35 VSS AD25 VSS AJ21
VSS V40 VSS AD32 VSS AJ25
VSS V44 VSS AD33 VSS AJ27
VSS V51 VSS AD47 VSS AJ29
VSS Y7 VSS AE1 VSS AJ30
VSS Y9 VSS AE3 VSS AJ32
VSS Y10 VSS AE4 VSS AJ33
VSS Y14 VSS AE6 VSS AJ35
VSS Y16 VSS AE8 VSS AJ38
VSS Y21 VSS AE9 VSS AJ53
VSS Y25 VSS AE11 VSS AK10
VSS Y33 VSS AE12 VSS AK14
VSS Y41 VSS AE14 VSS AK16
VSS Y44 VSS AE40 VSS AK33
VSS AA1 VSS AE42 VSS AK41
VSS AA3 VSS AE43 VSS AK44
VSS AA16 VSS AE45 VSS AM7
VSS AA19 VSS AE46 VSS AM12
VSS AA21 VSS AE48 VSS AM19
VSS AA32 VSS AE50 VSS AM24
VSS AA35 VSS AE51 VSS AM25
VSS AA38 VSS AE53 VSS AM29
VSS AA53 VSS AF10 VSS AM33
VSS AB4 VSS AF12 VSS AM35
VSS AB6 VSS AF25 VSS AM36
VSS AB10 VSS AF32 VSS AM40
VSS AB41 VSS AF47 VSS AM44
VSS AB45 VSS AG16 VSS AM51
VSS AB47 VSS AG25 VSS AN1
VSS AB48 VSS AG36 VSS AN3
VSS AB50 VSS AG38 VSS AN5
VSS AB51 VSS AH4 VSS AN6
VSS AC16 VSS AH6 VSS AN8
VSS AC18 VSS AH7 VSS AN9
VSS AC19 VSS AH9 VSS AN11
VSS AC21 VSS AH41 VSS AN12
VSS AC25 VSS AH45 VSS AN14
VSS AC33 VSS AH47 VSS AN22
VSS AC35 VSS AH48 VSS AN33
VSS AC36 VSS AH50 VSS AN35

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VSS AN36 VSS AW19 VSS BF36

VSS AN38 VSS AW27 VSS BF38
VSS AN40 VSS AW35 VSS BG1
VSS AN42 VSS AY4 VSS BG31
VSS AN43 VSS AY9 VSS BG34
VSS AN45 VSS AY10 VSS BG39
VSS AN46 VSS AY22 VSS BG42
VSS AN48 VSS AY32 VSS BG45
VSS AN49 VSS AY36 VSS BG49
VSS AN51 VSS AY50 VSS BG53
VSS AN53 VSS BA14 VSS BH1
VSS AP40 VSS BA19 VSS BH2
VSS AT4 VSS BA22 VSS BH52
VSS AT12 VSS BA27 VSS BH53
VSS AT16 VSS BA32 VSS BJ2
VSS AT19 VSS BA35 VSS BJ3
VSS AT24 VSS BA40 VSS BJ5
VSS AT27 VSS BA53 VSS BJ7
VSS AT30 VSS BB19 VSS BJ11
VSS AT35 VSS BB27 VSS BJ15
VSS AT38 VSS BB35 VSS BJ19
VSS AT47 VSS BC20 VSS BJ23
VSS AT52 VSS BC22 VSS BJ27
VSS AU1 VSS BC26 VSS BJ31
VSS AU3 VSS BC28 VSS BJ35
VSS AU24 VSS BC32 VSS BJ39
VSS AU30 VSS BC34 VSS BJ43
VSS AU38 VSS BC42 VSS BJ47
VSS AU51 VSS BD19 VSS BJ49
VSS AV7 VSS BD24 VSS BJ51
VSS AV12 VSS BD27 VSS BJ52
VSS AV13 VSS BD30 VSSA AN16
VSS AV14 VSS BD35
VSS AV18 VSS BE1
VSS AV19 VSS BE2
§§
VSS AV24 VSS BE8
VSS AV27 VSS BE19
VSS AV30 VSS BE35
VSS AV35 VSS BE53
VSS AV38 VSS BF4
VSS AV47 VSS BF12
VSS AV51 VSS BF16
VSS AW3 VSS BF24
VSS AW13 VSS BF30

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 Processor Core

11 Processor Core
Up to four out-of-order execution processor cores are supported, each dual core
module supports up to 1 MiB of L2 cache.

OOE Intel® OOE Intel® OOE Intel® OOE Intel®

AtomTM AtomTM AtomTM AtomTM
Processor Core Processor Core Processor Core Processor Core

1MiB L2 1MiB L2

11.1 Features
• Single, Dual or Quad Out-of-Order Execution (OOE) processor cores
• Primary 32 KiB, 8-way L1 instruction cache and 24 KiB, 6-way L1 write-back data
cache
• Cores are grouped into dual-core modules: modules share a 1 MiB, 16-way L2
cache (2 MiB total for Quad Core)
— Dual core SKU’s use 512 KiB per core. Each core has a dedicated link to
memory.
• Intel® Streaming SIMD Extensions 4.1 and 4.2 (SSE4.1 and SSE4.2), which include
new instructions for media and for fast XML parsing
• Intel® 64 architecture
• Support for IA 32-bit
• Support for Intel® VT-x
• Support for Intel® Carry-Less Multiplication Instruction (PCLMULQDQ)
• Support for a Digital Random Number Generator (DRNG)
• Supports C0, C1, C1E, C6C, C6
• Thermal management support via Intel® Thermal Monitor (TM1 & TM2))
• Uses Power Aware Interrupt Routing (PAIR)
• Uses 22 nm process technology
• Real Time Instruction Trace for debug
— Please see your Intel representative for details

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Note: Intel® Hyper-Threading Technology is not supported.

11.1.1 Intel® Virtualization Technology (Intel® VT)

Intel® Virtualization Technology (Intel® VT) makes a single system appear as multiple
independent systems to software. This allows multiple, independent operating systems
to run simultaneously on a single system. Intel® VT comprises technology components
to support virtualization of platforms based on Intel architecture microprocessors and
chipsets. Intel® Virtualization Technology for IA-32, Intel® 64 and Intel® Architecture
(Intel® VT-x) added hardware support in the processor to improve the virtualization
performance and robustness.

Intel® VT-x specifications and functional descriptions are included in the Intel® 64 and
IA-32 Architectures Software Developer’s Manual, Volume 3B and is available at: http:/
/www.intel.com/products/processor/manuals/index.htm

Other Intel® VT documents can be referenced at: http://www.intel.com/technology/

virtualization/index.htm

11.1.1.1 Intel® VT-x Objectives

• Robust: VMMs no longer need to use paravirtualization or binary translation. This

means that they will be able to run off-the-shelf OSs and applications without any
special steps.
• Enhanced: Intel® VT enables VMMs to run 64-bit guest operating systems on IA
x86 processors.
• More reliable: Due to the hardware support, VMMs can now be smaller, less
complex, and more efficient. This improves reliability and availability and reduces
the potential for software conflicts.
• More secure: The use of hardware transitions in the VMM strengthens the isolation
of VMs and further prevents corruption of one VM from affecting others on the
same system. Intel® VT-x provides hardware acceleration for virtualization of IA
platforms. Virtual Machine Monitor (VMM) can use Intel® VT-x features to provide
improved reliable virtualized platform.

11.1.1.1.1 Intel® VT-x Features

• Extended Page Tables (EPT)
— EPT is hardware assisted page table physical memory virtualization
— Support guest VM execution in unpaged protected mode or in real-address
mode
— It eliminates VM exits from guest OS to the VMM for shadow page-table
maintenance
• Virtual Processor IDs (VPID)

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— A VM Virtual Processor ID is used to tag processor core hardware structures

(such as TLBs) to allow a logic processor to cache information (such as TLBs) for
multiple linear address spaces
— This avoids flushes on VM transitions to give a lower-cost VM transition time and
an overall reduction in virtualization overhead
• Guest Preemption Timer
— Mechanism for a VMM to preempt the execution of a guest OS VM after an
amount of time specified by the VMM. The VMM sets a timer value before
entering a guest.
— The feature aids VMM developers in flexibility and Quality of Service (QoS)
guarantees flexibility in guest VM scheduling and building Quality of Service
(QoS) schemes
• Descriptor-Table Exiting
— Descriptor-table exiting allows a VMM to protect a guest OS from internal
(malicious software based) attack by preventing relocation of key system data
structures like IDT (interrupt descriptor table), GDT (global descriptor table),
LDT (local descriptor table), and TSS (task segment selector)
— A VMM using this feature can intercept (by a VM exit) attempts to relocate these
data structures and prevent them from being tampered by malicious software
• VM Functions
— A VM function is an operation provided by the processor that can be invoked
using the VMFUNC instruction from guest VM without a VM exit
— A VM function to perform EPTP switching is supported and allows guest VM to
load a new value for the EPT pointer, thereby establishing a different EPT paging
structure hierarchy

11.1.2 Security and Cryptography Technologies

11.1.2.1 Advanced Encryption Standard New Instructions (AES-NI)

The processor supports Advanced Encryption Standard New Instructions (AES-NI) that
are a set of Single Instruction Multiple Data (SIMD) instructions that enable fast and
secure data encryption and decryption based on the Advanced Encryption Standard
(AES). AES-NI are valuable for a wide range of cryptographic applications, for example:
applications that perform bulk encryption/decryption, authentication, random number
generation, and authenticated encryption. AES is broadly accepted as the standard for
both government and industry applications, and is widely deployed in various protocols.

AES-NI consists of six Intel® SSE instructions. Four instructions, namely AESENC,
AESENCLAST, AESDEC, and AESDELAST facilitate high performance AES encryption and
decryption. The other two, AESIMC and AESKEYGENASSIST, support the AES key
expansion procedure. Together, these instructions provide a full hardware for support
AES, offering security, high performance, and a great deal of flexibility.

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11.1.2.2 PCLMULQDQ Instruction

The processor supports the carry-less multiplication instruction, PCLMULQDQ.

PCLMULQDQ is a Single Instruction Multiple Data (SIMD) instruction that computes the
128-bit carry-less multiplication of two, 64-bit operands without generating and
propagating carries. Carry-less multiplication is an essential processing component of
several cryptographic systems and standards. Hence, accelerating carry-less
multiplication can significantly contribute to achieving high speed secure computing
and communication.

11.1.2.3 Digital Random Number Generator

The processor introduces a software visible digital random number generation

mechanism supported by a high quality entropy source. This capability is available to
programmers through the new RDRAND instruction. The resultant random number
generation capability is designed to comply with existing industry standards (ANSI
X9.82 and NIST SP 800-90).

Some possible uses of the new RDRAND instruction include cryptographic key
generation as used in a variety of applications including communication, digital
signatures, secure storage, etc.

11.1.3 Power Aware Interrupt Routing

PAIR is an improvement in H/W routing of “redirectable” interrupts. Each core power-
state is considered in the routing selection to reduce the power or performance impact
of interrupts. System BIOS configures the routing algorithm, e.g. fixed-priority,
rotating, hash, or PAIR, during setup via non-architectural register. The PAIR algorithm
can be biased to optimize for power or performance and the largest gains will be seen
in systems with high interrupt rates.

11.2 Platform Identification and CPUID

In addition to verifying the processor signature, the intended processor platform type
must be determined to properly target the microcode update. The intended processor
platform type is determined by reading bits [52:50] of the IA32_PLATFORM_ID
register, (MSR 17h) within the processor. This is a 64-bit register that must be read
using the RDMSR instruction. The 3 Platform Id bits, when read as a binary coded
decimal (BCD) number, indicate the bit position in the microcode update header’s
Processor Flags field that is asSoCiated with the installed processor.

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Executing the CPUID instruction with EAX=1 will provide the following information.

EAX Field description

[31:28] Reserved
[27:20] Extended Family value
[19:16] Extended Model value
[15:13] Reserved
[12] Processor Type Bit
[11:8] Family value
[7:4] Model value
[3:0] Stepping ID Value

11.3 References
For further details of Intel® 64 and IA-32 architectures refer to Intel® 64 and IA-32
Architectures Software Developer’s Manual Combined Volumes:1, 2A, 2B, 2C, 3A, 3B,
and 3C:
• http://www.intel.com/content/www/µs/en/processors/architectures-software-
developer-manuals.html

For more details on AES-NI refer to:

• Intel ® Performance Primitives (IPP) web page - http://software.intel.com/en-us/
intel-ipp/
• White Paper on AES-NI - http://software.intel.com/en-us/articles/intel-advanced-
encryption-standard-aes-instructions-set/

For more details on using the RDRAND instruction refer to Intel® Advanced Vector
Extensions Programming Reference.
•

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12 System Memory Controller

The system memory controller supports DDR3L protocol with up to two 64-bit wide
dual rank channels at data rates up to 1333 MT/s. ECC is also available on a single
channel.

Note: The memory data rate is fixed for each SKU. For example, a SKU that supports
1333 MT/s will only run at 1333 MT/s, nothing lower. For single channel use cases,
Channel 0 must be used.

Channel

Controller
Memory
IO
0
Channel
IO
1

12.1 Signal Descriptions

Please see Chapter 2, “Physical Interfaces” for additional details.

The signal description table has the following headings:

• Signal Name: The name of the signal/pin
• Direction: The buffer direction can be either input, output, or I/O (bidirectional)
• Type: The buffer type found in Chapter 9, “Electrical Specifications”
• Description: A brief explanation of the signal’s function

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Table 143. Memory Channel 0 DDR3L Signals (Sheet 1 of 2)

Direction
Signal Name Description
Type

DRAM0_CKP[2,0] O SDRAM and inverted Differential Clock: (1 pair per

DRAM0_CKN[2,0] DDR3 Rank)
The differential clock pair is used to latch the command
into DRAM. Each pair corresponds to one rank on DRAM
side.
DRAM0_CS[2,0]# O Chip Select: (1 per Rank). Used to qualify the
DDR3 command on the command bus for a particular rank.

DRAM0_CKE[2,0] O Clock Enable: (power management)

DDR3 It is used during DRAM power up/power down and Self
refresh.
Note: DDR3L uses only DRAM0_CKE[2,0].
DRAM0_CKE[1,3] are not being used for DDR3L.
DRAM0_MA[15:0] O Memory Address: Memory address bus for writing
DDR3 data to memory and reading data from memory. These
signals follow common clock protocol w.r.t.
DRAM0_CKN, DRAM0_CKP pairs
DRAM0_BS[2:0] O Bank Select: These signals define which banks are
DDR3 selected within each DRAM rank

DRAM0_RAS# O Row Address Select: Used with DRAM0_CAS# and

DDR3 DRAM0_WE# (along with DRAM0_CS#) to define the
DRAM Commands
DRAM0_CAS# O Column Address Select: Used with DRAM0_RAS#
DDR3 and DRAM0_WE# (along with DRAM0_CS#) to define
the DRAM Commands
DRAM0_WE# O Write Enable Control Signal: Used with
DDR3 DRAM0_WE# and DRAM0_CAS# (along with control
signal, DRAM0_CS#) to define the DRAM Commands.
DRAM0_DQ[63:0] I/O Data Lines: Data signal interface to the DRAM data
DDR3 bus

DRAM0_DM[7:0] O Data Mask: DM is an output mask signal for write

DDR3 data. Output data is masked when DM is sampled HIGH
coincident with that output data during a Write access.
DM is sampled on both edges of DQS.
DRAM0_DQSP[7:0] I/O Data Strobes: The data is captured at the crossing
DRAM0_DQSN[7:0] DDR3 point of each ‘P’ and its compliment ‘N’ during read and
write transactions.
For reads, the strobe crossover and data are edge
aligned, whereas in the Write command, the strobe
crossing is in the centre of the data window.
DRAM0_ODT[2,0] O On Die Termination: ODT signal going to DRAM in
DDR3 order to turn ON the DRAM ODT during Write.

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Table 143. Memory Channel 0 DDR3L Signals (Sheet 2 of 2)

Direction
Signal Name Description
Type

DRAM_RCOMP[2] O Resistor Compensation: This signal needs to be

Analog terminated to VSS on board (refer to platform design
guide for resistor value). This external resistor
termination scheme is used for Resistor compensation
of DRAM ODT strength.
DRAM_RCOMP[1] O Resistor Compensation: This signal needs to be
Analog terminated to VSS on board (refer to platform design
guide for resistor value). This external resistor
termination scheme is used for Resistor compensation
of DQ buffers
DRAM_RCOMP[0] O Resistor Compensation: This signal needs to be
Analog terminated to VSS on board (refer to platform design
guide for resistor value). This external resistor
termination scheme is used for Resistor compensation
of CMD buffers.
DRAM_VREF I Reference Voltage: DRAM interface Reference
Analog Voltage

DRAM_CORE_PWROK I Core Power OK: This signal indicates the status of the
Asynchro DRAM Core power supply (power on in S0).
nous
CMOS
DRAM_VDD_S4_PWR I VDD Power OK: Asserted once the VRM is settled.
OK Asynchro Used primarily in the DRAM PHY to determine S3 state.
nous
CMOS
DRAM0_DRAMRST# O DRAM Reset: This signal is used to reset DRAM
devices.
ICLK_DRAM_TERM I/O Pull-down to VSS through an 100kOhm 1% resistor.
[1:0]

Table 144.

Direction
Signal Name Description
Type

DRAM1_CKP[2,0] O SDRAM and inverted Differential Clock: (1 pair per

DRAM1_CKN[2,0] DDR3 Rank)
The differential clock pair is used to latch the command
into DRAM. Each pair corresponds to one rank on DRAM
side.
DRAM1_CS[2,0]# O Chip Select: (1 per Rank). Used to qualify the command
DDR3 on the command bus for a particular rank.

DRAM1_CKE[2,0] O Clock Enable: (power management)

DDR3 It is used during DRAM power up/power down and Self
refresh.
Note: DDR3L uses only DRAM1_CKE[0,2].
DRAM1_CKE[1,3] are not being used for DDR3L.

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Table 144.

Direction
Signal Name Description
Type

DRAM1_MA[15:0] O Memory Address: Memory address bus for writing data

DDR3 to memory and reading data from memory. These signals
follow common clock protocol relative to DRAM1_CKN,
DRAM1_CKP pairs
DRAM1_BS[2:0] O Bank Select: These signals define which banks are
DDR3 selected within each DRAM rank

DRAM1_RAS# O Row Address Select: Used with DRAM1_CAS# and

DDR3 DRAM1_WE# (along with DRAM1_CS#) to define the
DRAM Commands
DRAM1_CAS# O Column Address Select: Used with DRAM1_RAS# and
DDR3 DRAM1_WE# (along with DRAM1_CS#) to define the
DRAM Commands
DRAM1_WE# O Write Enable Control Signal: Used with DRAM1_WE#
DDR3 and DRAM1_CAS# (along with control signal,
DRAM1_CS#) to define the DRAM Commands.
DRAM1_DQ[63:0] I/O Data Lines: Data signal interface to the DRAM data bus.
DDR3
DRAM1_DM[7:0] O Data Mask: DM is an output mask signal for write data.
DDR3 Output data is masked when DM is sampled HIGH
coincident with that output data during a Write access. DM
is sampled on both edges of DQS.
DRAM1_DQSP[7:0] I/O Data Strobes: The data is captured at the crossing point
DRAM1_DQSN[7:0] DDR3 of DRAM1_DQSP[7:0] and its compliment ‘N’ during read
and write transactions.
For reads, the strobe crossover and data are edge aligned,
whereas in the Write command, the strobe crossing is in
the centre of the data window.
DRAM1_ODT[2,0] O On Die Termination: ODT signal going to DRAM in order
DDR3 to turn ON the DRAM ODT during Write.

DRAM1_DRAMRST# O Reset DRAM: This signal can be used to reset DRAM

devices.

12.1.1 ECC Support

The system memory controller supports ECC. When ECC is enabled, only Memory
Channel 0 will be active. Memory Channel 1 will be disabled and used for the ECC data
signals. Signals on Memory Channel 1 not used for ECC will be tri-stated. The table
below shows the details on the muxing relationship between the ECC signals and the
Memory Channel 1 signals.

Note: Although ECC and non-ECC SO-DIMM’s share the same socket, ECC SO-DIMMs are not
pinout compatible with standard, non-ECC SO-DIMMs.

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Table 145. ECC Signals and Memory Channel 1 Signal Muxing

Signal Names when ECC is

Memory Channel 1 Signal Names Ball #
Enabled

DRAM1_DQ[56] AM52 DRAM0_ECC_DQ[0]

DRAM1_DQ[57] AL51 DRAM0_ECC_DQ[1]
DRAM1_DQ[58] AG53 DRAM0_ECC_DQ[2]
DRAM1_DQ[59] AG51 DRAM0_ECC_DQ[3]
DRAM1_DQ[60] AL53 DRAM0_ECC_DQ[4]
DRAM1_DQ[61] AK51 DRAM0_ECC_DQ[5]
DRAM1_DQ[62] AF52 DRAM0_ECC_DQ[6]
DRAM1_DQ[63] AF51 DRAM0_ECC_DQ[7]
DRAM1_DM[7] AK52 DRAM0_ECC_DM
DRAM1_DQSP[7] AH52 DRAM0_ECC_DQSP
DRAM1_DQSN[7] AJ51 DRAM0_ECC_DQSN

Table 146. ECC Signals

Direction
Signal Name Description
Type

DRAM0_ECC_DQ[7:0] I/O ECC Check Data Bits

DDR3 These are muxed with channel 1.
DRAM0_ECC_DM O ECC Data Mask: DM is an optional output mask signal
DDR3 for write data. Output data is masked when DM is
sampled HIGH coincident with that output data during a
Write access. DM is sampled on both edges of ECC_DQS.
This signal is muxed with channel 1 and may not be
needed.
DRAM0_ECC_DQSP I/O ECC Data Strobes: The data is captured at the crossing
DRAM0_ECC_DQSN DDR3 point the ‘P’ and its compliment ‘N’ during read and write
transactions. For reads, the strobe crossover and data
are edge aligned, whereas in the Write command, the
strobe crossing is in the centre of the data window.
These are muxed with channel 1.

12.2 Features
The system memory controller supports the following DDR3L DRAM technologies, Data
Transfer Rates, SO-DIMM Modules and other features:
• DDR3L Data Transfer Rates (Fixed per SKU): 1066MT/s (8.5 GB/s per channel) or
1333MT/s (10.6 GB/s per channel)
• DDR3L SDRAM’s (1.35 V DRAM interface I/Os, including DDR3L-RS)
• DDR3L DRAM Device Technology
— Standard 1Gb, 2Gb and 4Gb technologies and addressing

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 System Memory Controller

— Read latency 5, 6, 7, 8, 9, 10, 11

— Write latency 5, 6, 7, 8
• DDR3L SO-DIMM Modules (unbuffered)
— Raw Card B = 1 rank of x8 SDRAM
— Raw Card C = 1 rank of x16 SDRAM
— Raw Card F = 2 ranks of x8 SDRAM
— ECC Raw Card C = 1 rank of x8 SDRAM
— ECC Raw Card D = 2 ranks of x8 SDRAM
— No mixed Raw Card support
— Please contact your Intel representative for platform supportable memory
configurations and limitations based on layout and firmware initialization (MRC)
requirements
• Support Trunk Clock Gating
• Supports up to two 64-bit channels
— Channel 0 only for single channel configuration
• ECC support for 64-bit data bus
• Support early SR exit
• Support slow power down

12.2.1 System Memory Technology Support

Table 149. Supported DDR3L ECC Memory Size Per Rank

DRAM
Memory DRAM Chip DRAM Chip
Chips/ Page Size @ 64-bit Data Bus
Size/ Rank Density Data Width
Rank

2GB 8 2Gb x8 8KB = 1KB * 8 chips

4GB 8 4Gb x8 8KB = 1KB * 8 chips

The frequency of system memory is fixed based on SKU. Timing parameters (CAS
latency or CL + AL for DDR3, tRAS, tRCD, tRP) must be programmed to match within a
channel (Contact your Intel field representative for more information on memory
reference code (MRC)). The controller supports these configurations:
— Supports 1 SO-DIMM per channel.
— Each SO-DIMM can have 1 or 2 ranks.
— If a SO-DIMM has two ranks, then both ranks must be symmetrical (same chip
width, same chip density, and same total memory size per rank).
— For dual channel population, the two channels must be populated symmetrically
(chip width, density, ranks).

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— The maximum total memory supported by SoC is 8GB. Please contact your Intel
representative for guidelines on the specific SO-DIMM Raw cards supported.

12.2.2 Rules for Populating SO-DIMM Slots

SO-DIMMs must share DRAM technology and total capacity. When channel 0 is
populated with a SO-DIMM, the other channel must either be identical (same DRAM
density, width, and number of ranks) or empty.

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 SoC Transaction Router

13 SoC Transaction Router

The SoC Transaction Router is a central hub that routes transactions between the CPU
cores, graphics controller, IO and the memory controller. In general, it handles:
• CPU Core Interface: Requests for CPU Core-initiated memory and IO read and write
operations and processor-initiated message-signaled interrupt transactions
• Device MMIO and PCI configuration routing
• Buffering and memory arbitration
• PCI Config and MMIO accesses to host device (0/0/0)

To Processor Cores

T-Unit
To
B-Unit
Memory
A-Unit

To I/O Fabric

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13.1 Register Map

Figure 93. Soc Transaction Router Register Map

PCI Space

CPU
Core

SoC Transaction
Router
D:0,F:0
PCI
CAM
Graphics
(I/O)
D:2,F:0
Bus 0
PCI
ECAM
Camera ISP
(Mem)
D:3,F:0

#1 D:16,F:0
xHCI USB MMC
SD/

D:20,F:0 #2 D:17,F:0
#3 D:18,F:0

USB Dev
D:22,F:0 SATA
D:19,F:0

DMA F:0
I2C0 F:1
I2C1 F:2
SIO D:24

LPE Audio (I2S)

I2C2 F:3
D:21,F:0
I2C3 F:4
I2C4 F:5
I2C5 F:6
I2C6 F:7 Trusted Execution
Engine (TXE)
D:26,F:0
RP1 F:0
PCIe D:28

RP2 F:1
RP3 F:2
HDA
RP4 F:3 D:27,F:0

EHCI USB DMA F:0

D:29,F:0
PWM1 F:1
SIO D:30

PWM2 F:2
LPC (iLB) F:0 HSUART1 F:3
D:31
PCU

HSUART2 F:4
SMB F:3 SPI F:5

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 SoC Transaction Router

13.2 Transaction Router A-Unit Message Bus Registers

Table 151. Summary of Message Bus Registers—0x00

Default
Offset Register ID—Description
Value

10h “ACF8—Offset 10h” on page 272 00000000h

52h “ADBGERRLOG—Offset 52h” on page 273 00000000h

13.2.1 ACF8—Offset 10h

A-Unit Configuration CF8 Value (ACF8) The A-Unit CF8 (PCI Configuration Address
Register) is made available for save/restore purposes. This register is saved and
restored by the Punit during S0iX transitions in order to ensure proper handling of a
possible subsequent CFC transaction after returning from standby or hibernate state.
This is carried over from Aunit implementation in LNC.

Access Method
Type: Message Bus Register ACF8: [Port: 0x00] + 10h
(Size: 32 bits)
Op Codes:
6h - Read, 7h - Write

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DBL_WD
CF8_RESERVED_0

CF8_RESERVED_1
BUS_NUM

DEVICE_NUM

FUNCTION_NUM
CFG_MAP_EN

Bit Default &

Description
Range Access

0h CFG_MAP_EN: Configuration Space Mapping Enable: This bit enables Configuration

31
RW Space mapping. The value set by full-dword writes to I/O address CF8

0h
30:24 CF8_RESERVED_0: Reserved. The value set by full-dword writes to I/O address CF8
RW

0h BUS_NUM: Bus Number: This is the target Bus Number of the resulting Configuration
23:16
RW request. The value set by full-dword writes to I/O address CF8

0h DEVICE_NUM: Device Number: This is the target Device Number of the resulting
15:11
RW Configuration request. The value set by full-dword writes to I/O address CF8

0h FUNCTION_NUM: Function Number: This is the target Function Number of the

10:8
RW resulting Configuration request. The value set by full-dword writes to I/O address CF8

0h DBL_WD: Double Word: This is the target dword of the resulting Configuration request.
7:2
RW The value set by full-dword writes to I/O address CF8

0h CF8_RESERVED_1: Reserved. This field should be always set to 2'b00. The value set
1:0
RW by full-dword writes to I/O address CF8

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13.2.2 ADBGERRLOG—Offset 52h

Aunit Error Logging Register (ADBGERRLOG) This register is used as a means to log
errors in Aunit. All upstream errors are logged with Port ID. Each error has a bit mask
that enables the error logging.

Access Method
Type: Message Bus Register ADBGERRLOG: [Port: 0x00] + 52h
(Size: 32 bits)
Op Codes:
6h - Read, 7h - Write

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ERR_BIT_MASK

UPSTREAM_VIO
ENABLE_ERR_LOG

DOWNSTREAM_VIO

UPSTREAM_PORTID
RESERVED_0

RESERVED_1

RESERVED_2
Bit Default &
Description
Range Access

0h ENABLE_ERR_LOG: Enable error logging for error. When set, the Aunit will latch
31 violation information into this register. This bit is cleared upon triggering and must be
RW reset by software in order to trigger again.

0h
30 RESERVED_0: Reserved
RO

ERR_BIT_MASK: When set enables error logging of the error. 0 disables the error
0h logging. Bit 29 IO_length8_notqw_aligned Bit 28 IO_unsupported_length Bit 27
29:18 ecam_unsupported_length Bit 26 ecamcross_dw_boundary Bit 25 mult_tdec_hit Bit 24
RW unsupported_iosf_op Bit 23 cfgwrite Bit 22 cfgread Bit 21 iowrite Bit 20 ioread Bit 19
unsupported_cmd Bit 18 unsupported_vdm

0h
17 RESERVED_1: Reserved
RO

DOWNSTREAM_VIO: Downstream violations Bit 16 - IO request length is 8 but not

0h QW aligned Bit 15 - IO request length is not 1, 2, 3, 4, or 8 Bit 14 - ECAM with
16:12
RO unsupported length Bit 13 - ECAM crosses dw boundary Bit 12 - target decode multiple
hits
0h
11:8 UPSTREAM_PORTID: Port ID for upstream error
RO
0h
7 RESERVED_2: Reserved
RO
UPSTREAM_VIO: Upstream violation Bit 6 - received other unsupported IOSF
0h transaction that arent translated correctly LTMemRead/Wr, FetchAdd, Swap, CAS Bit 5 -
6:0 received CFGWrite Bit 4 - received CFGRead Bit 3 - received IOWrite Bit 2 - received
RO IORead Bit 1 - received unsuccessful completion (e.g. UR, CRS, CA) Bit 0 - received
unsupported VDM

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13.3 Transaction Router IO Registers

Table 152. Summary of Transaction Router I/O Registers—

Default
Offset Size Register ID—Description
Value

CF8h 1 “ACF8—Offset CF8h” on page 274 00000000h

CFCh 4 “ACFC—Offset CFCh” on page 274 00000000h

13.3.1 ACF8—Offset CF8h

A-Unit Configuration CF8 Value (ACF8) The A-Unit CF8 (PCI Configuration Address
Register) is made available for save/restore purposes. This register is saved and
restored by the Punit during S0iX transitions in order to ensure proper handling of a
possible subsequent CFC transaction after returning from standby or hibernate state.
This is carried over from Aunit implementation in LNC.

Access Method
Type: I/O Register ACF8: CF8h
(Size: 32 bits)

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CFG_MAP_EN

CF8_RESERVED_0

BUS_NUM

CF8_RESERVED_1
DEVICE_NUM

FUNCTION_NUM

DBL_WD
Bit Default &
Description
Range Access

0h CFG_MAP_EN: Configuration Space Mapping Enable: This bit enables Configuration

31
RW Space mapping. The value set by full-dword writes to I/O address CF8

0h
30:24 CF8_RESERVED_0: Reserved. The value set by full-dword writes to I/O address CF8
RW
0h BUS_NUM: Bus Number: This is the target Bus Number of the resulting Configuration
23:16
RW request. The value set by full-dword writes to I/O address CF8

0h DEVICE_NUM: Device Number: This is the target Device Number of the resulting
15:11
RW Configuration request. The value set by full-dword writes to I/O address CF8

0h FUNCTION_NUM: Function Number: This is the target Function Number of the

10:8
RW resulting Configuration request. The value set by full-dword writes to I/O address CF8

0h DBL_WD: Double Word: This is the target dword of the resulting Configuration request.
7:2
RW The value set by full-dword writes to I/O address CF8

0h CF8_RESERVED_1: Reserved. This field should be always set to 2'b00. The value set
1:0
RW by full-dword writes to I/O address CF8

13.3.2 ACFC—Offset CFCh

A-Unit Configuration CFC Value (ACFC) The A-Unit CFC (PCI Configuration Data Port).

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Access Method
Type: I/O Register ACFC: CFCh
(Size: 32 bits)

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CFC_VAL
Bit Default &
Description
Range Access

0h
31:0 CFC_VAL: CFC Value: The value set by full-dword writes to I/O address CFC
RW

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 SoC Transaction Router

13.4 Transaction Router C-Unit PCI Configuration Registers

Table 153. Summary of Transaction Router PCI Configuration Registers—0/0/0

Default
Offset Size Register ID—Description
Value

0h 1 “CUNIT_REG_DEVICEID—Offset 0h” on page 276 00008086h

4h 1 “CUNIT_CFG_REG_PCISTATUS—Offset 4h” on page 277 00000007h

8h 1 “CUNIT_CFG_REG_CLASSCODE—Offset 8h” on page 277 06000000h
Ch 1 “CUNIT_CFG_REG_HDR_TYPE—Offset Ch” on page 278 00000000h

2Ch 1 “CUNIT_CFG_REG_STRAP_SSID—Offset 2Ch” on page 278 00000000h

F8h 1 “CUNIT_MANUFACTURING_ID—Offset F8h” on page 279 00000000h

13.4.1 CUNIT_REG_DEVICEID—Offset 0h
CUnit Configuration Register Device ID/Vendor ID. Device ID and Vendor ID Strapped
in from top level. Reset value to strapDID[15:3],fuse[2:0], 16'h8086 these bits can be
re-written from SETIDVALUE message 1st DW data byte 2, byte 3

Access Method
Type: PCI Configuration Register CUNIT_REG_DEVICEID: [B:0, D:0, F:0] + 0h
(Size: 32 bits)

Default: 00008086h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0
DEVICEID_BIT_22_19

DEVICEID_BIT_18_16

DEVICEID_BIT_15_0
DEVICEID_VENDOR_ID

Bit Default &

Description
Range Access

DEVICEID_VENDOR_ID: Device ID and Vendor ID bit [15:7] are strapped in from top
level. These bits can be re-written from SETIDVALUE message 1st DW data byte 2, byte
0h 3. for VLV/VLV2, final setting of this field is from SETIDVALUE message, while for TNG it
31:23
RW uses the strapped setting. For all SOC's, the RDL defalut is set to the strapped setting in
that SOC. Please refer to the SoC documentation to determine the proper Device ID for
the chip.

0h DEVICEID_bit_22_19 (DEVICEID_BIT_22_19): Device ID [6:3] Hardwired in the

22:19 design. SETIDVALUE message will not re-write this field. RDL default is set to the
RO strapped value

0h DEVICEID_bit_18_16 (DEVICEID_BIT_18_16): Device ID [2:0]. Strapped in from

18:16 top level and tied to fuses to determine product SKU. SETIDVALUE message will not re-
RO write this field.
8086h
15:0 DEVICEID_bit_15_0 (DEVICEID_BIT_15_0): Hardwired
RO

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13.4.2 CUNIT_CFG_REG_PCISTATUS—Offset 4h
CUnit Configuration Register Device ID/Vendor ID

Access Method
Type: PCI Configuration Register
(Size: 32 bits) CUNIT_CFG_REG_PCISTATUS: [B:0, D:0, F:0] + 4h

Default: 00000007h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1

PCI_STATUS_PCI_CMD
Bit Default &
Description
Range Access

00000007h
31:0 PCI_STATUS_PCI_CMD: PCI Status and PCI Command. Hardwired to 32'h00000007
RO

13.4.3 CUNIT_CFG_REG_CLASSCODE—Offset 8h
CUnit Configuration register Header Type and Master Latency Time

Access Method
Type: PCI Configuration Register
CUNIT_CFG_REG_CLASSCODE: [B:0, D:0, F:0] + 8h
(Size: 32 bits)

Default: 06000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PCI_CLASSCODE_REVID

PCI_BIT_15_8

PCI_BIT_7_0

Bit Default &

Description
Range Access

0600h
31:16 PCI_CLASSCODE_REVID: PCI Class Code
RO
00h
15:8 PCI_BIT_15_8: Hardwired to 8'h00
RO

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Bit Default &

Description
Range Access

0h PCI_BIT_7_0: PCI revision ID. these bits can be re-written from SETIDVALUE message
7:0
RW 1st DW data byte 0

13.4.4 CUNIT_CFG_REG_HDR_TYPE—Offset Ch
CUnit Configuration Register Device ID/Vendor ID

Access Method
Type: PCI Configuration Register
(Size: 32 bits) CUNIT_CFG_REG_HDR_TYPE: [B:0, D:0, F:0] + Ch

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MSTRLATENCY_HDRTYPE

Bit Default &

Description
Range Access

00000000h
31:0 MSTRLATENCY_HDRTYPE: Master Latency Timer and Header Type hardwired to 0
RO

13.4.5 CUNIT_CFG_REG_STRAP_SSID—Offset 2Ch

CUnit Configuration Register Device ID/Vendor ID

Access Method
Type: PCI Configuration Register CUNIT_CFG_REG_STRAP_SSID: [B:0, D:0, F:0] + 2Ch
(Size: 32 bits)

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PCI_SUBSYSTEMID

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Bit Default &

Description
Range Access

00000000h PCI_SUBSYSTEMID: PCI Subsystem ID passed in from top-level straps

31:0
RO strapSSID[31:0]

13.4.6 CUNIT_MANUFACTURING_ID—Offset F8h

CUnit Manufacturing ID Register

Access Method
Type: PCI Configuration Register
CUNIT_MANUFACTURING_ID: [B:0, D:0, F:0] + F8h
(Size: 32 bits)

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MANUFACTURING_ID_BIT_27_24

MANUFACTURING_ID_BIT_23_16

MANUFACTURING_ID_BIT_15_8

MANUFACTURING_ID_BIT_7_0
RESERVED

Bit Default &

Description
Range Access

0h RESERVED: Reserved, these bits can be re-written frmo SETIDVALUE message 2nd DW
31:28
RW data byte 3 upper nibble

0h MANUFACTURING_ID_BIT_27_24: Dot Portion of Process, these bits can be re-

27:24
RW written from SETIDVALUE message 2nd DW data byte 3 lower nibble

0h MANUFACTURING_ID_BIT_23_16: Process Portion of Process ID, these bits can be

23:16
RW re-written from SETIDVALUE message 2nd DW data byte 0

0h MANUFACTURING_ID_BIT_15_8: Manufacturing ID (MID), these bits can be re-

15:8
RW written from SETIDVALUE message 2nd DW data byte 1

0h MANUFACTURING_ID_BIT_7_0: Manufacturing Stepping ID (MSID), these bits can

7:0
RW be re-written from SETIDVALUE message 2nd DW data byte 2

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 Graphics, Video and Display

14 Graphics, Video and Display

This section provides an overview of Graphics, Video and Display features of the SoC.

14.1 Features
The key features of the individual blocks are as follows:
• Refreshed seventh generation Intel graphics core with four Execution Units (EUs)
— 3D graphics hardware acceleration including support for DirectX*11, OCL 1.2,
OGL ES Halti/2.0/1.1, OGL 3.2
— Video decode hardware acceleration including support for H.264, MPEG2, MVC,
VC-1, WMV9 and VP8 formats
— Video encode hardware acceleration including support for H.264, MPEG2 and
MVC formats
— Display controller, incorporating the display planes, pipes and physical interfaces
— Four planes available per pipe - 1x Primary, 2x Video Sprite & 1x Cursor- plus a
single legacy VGA plane
— A single Analog Display physical interface, implementing VGA support
— Two multi-purpose Digital Display Interface (DDI) PHYs implementing HDMI,
DVI, DisplayPort (DP) or Embedded DisplayPort (eDP) support

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14.2 SoC Graphics Display

3D Graphics Display Controller

SoC Transaction

Display Phyiscal
Display Arbiter
Video Pipe A

Interfaces
Router
To SoC Display
Transaction DDI0 IO Planes
Controller
Router Display
DDI1 IO
Pipe B

VGA IO

The Processor Graphics controller display pipe can be broken down into three
components:
• Display Planes
• Display Pipes
• Display Physical Interfaces
A display plane is a single displayed surface in memory and contains one image
(desktop, cursor, overlay). It is the portion of the display hardware logic that defines
the format and location of a rectangular region of memory that can be displayed on a
display output device and delivers that data to a display pipe. This is clocked by the
Core Display Clock.

14.2.1 Primary Planes A and B

Planes A and B are the main display planes and are associated with Pipes A and B
respectively. Each plane supports per-pixel alpha blending.

14.2.2 Video Sprite Planes A, B, C and D

Video Sprite Planes A, B, C & D are planes optimized for video decode. Planes A and B
are associated with Pipe A and Planes C and D are associated with Pipe B.

14.2.3 Cursors A and B

Cursors A and B are small, fixed-sized planes dedicated for mouse cursor acceleration,
and are associated with Planes A and B respectively.

14.2.4 VGA
VGA is used for boot, safe mode, legacy games, etc. It can be changed by an
application without OS/driver notification, due to legacy requirements.

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 Graphics, Video and Display

14.3 Display Pipes

The display pipe blends and synchronizes pixel data received from one or more display
planes and adds the timing of the display output device upon which the image is
displayed.

The display pipes A and B operate independently of each other at the rate of one pixel
per clock. They can attach to any of the display interfaces.

14.4 Display Physical Interfaces

The display physical interfaces consist of output logic and pins that transmit the display
data to the associated encoding logic and send the data to the display device. These
interfaces can be subdivided into analog (VGA) and digital (DisplayPort*, Embedded
DisplayPort*, DVI and HDMI*) interfaces.

14.4.1 Analog Display Physical Interface

The analog port provides a RGB signal output along with a HSYNC and VSYNC signal.
There is an associated Display Data Channel (DDC) signal pair dedicated to the analog
port. The intended target device is for a monitor with a VGA connector. Display devices
such as LCD panels with analog inputs may work satisfactorily but no functionality is
added to the signals to enhance that capability.

14.4.1.1 Signal Descriptions

Please see Chapter 2, “Physical Interfaces” for additional details.

The signal description table has the following headings:

• Signal Name: The name of the signal/pin
• Direction: The buffer direction can be either input, output, or I/O (bidirectional)
• Platform Power: The reference power plane.
• Description: A brief explanation of the signal’s function.

Table 154. Analog Display Interface Signals

Direction
Signal Name Description
Plat. Power

VGA_BLUE O Blue Analog Video Output: This signal is a VGA Analog video
VVGA_GPIO output from the internal color palette DAC.

VGA_GREEN O Green Analog Video Output: This signal is a VGA Analog

VVGA_GPIO video output from the internal color palette DAC.

VGA_RED O Red Analog Video Output: This signal is a VGA Analog video
VVGA_GPIO output from the internal color palette DAC.

VGA_HSYNC O VGA Horizontal Synchronization: This signal is used as the

VVGA_GPIO horizontal sync (polarity is programmable) or “sync interval”.

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Table 154. Analog Display Interface Signals

Direction
Signal Name Description
Plat. Power

VGA_VSYNC O VGA Vertical Synchronization: This signal is used as the

VVGA_GPIO horizontal sync (polarity is programmable) or “sync interval”.

VGA_DDCCLK I/O VGA DDC Clock: EDID support for an external VGA display
VVGA_GPIO

VGA_DDCDATA I/O VGA DDC Data: EDID support for an external VGA display
VVGA_GPIO

VGA_IREF I Resistor Set: Set point resistor for the internal color palette
DAC. A 357ohm+/-0.5% precision resistor is required between
VGA_IREF and motherboard ground.

VGA_IRTN O This signal is the complement video signal output from the
internal color palette DAC channels and this signal connects
directly to the ground plane of the board.

LPC_RCOMP - VGA Impedance Compensation.

14.4.1.2 Features

Table 155 lists the characteristics of the analog port.

Table 155. Analog Port Characteristics

Signal Port Characteristics Support

RGB Voltage range 0.7 Vp-p nominal only

CRT/Monitor sense Analog compare
Analog copy protection No
Sync on green No
HSYNC Voltage 3.3 V
VSYNC Enable/Disable Port control
Polarity adjust VGA or port control
Composite sync support No
Special flat panel sync No
Stereo sync No
DDC Voltage External buffered to 5 V
Control Through GPIO interface

14.4.1.2.1 Integrated RAMDAC

The display function contains a RAM-based Digital-to-Analog Converter (RAMDAC) that

transforms the digital data from the graphics and video subsystems to analog data for
the VGA monitor. The SoC integrated 320 MHz RAMDAC supports resolutions up to
2560x1600 at 60 Hz. Three 8-bit DACs provide the R, G, and B signals to the monitor.

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 Graphics, Video and Display

14.4.1.2.2 Sync Signals

HSYNC and VSYNC signals are digital and conform to TTL signal levels at the connector.
Since these levels cannot be generated internal to the device, external level shifting
buffers are required. These signals can be polarity adjusted and individually disabled in
one of the two possible states. The sync signals should power up disabled in the high
state. No composite sync or special flat panel sync support are included.

14.4.1.2.3 VESA/VGA Mode

VESA/VGA mode provides compatibility for pre-existing software that set the display
mode using the VGA CRTC registers. Timings are generated based on the VGA register
values and the timing generator registers are not used.

14.4.1.2.4 Display Data Channel (DDC)

DDC is a standard defined by VESA. Its purpose is to allow communication between the
host system and display. Both configuration and control information can be exchanged
allowing plug-and-play systems to be realized. Support for DDC 1 and 2 is
implemented. The SoC uses the VGA_DDCCLK and VGA_DDCDATA signals to
communicate with the analog monitor. The SoC does not generate these signals at 5 V
so external pull-up resistors and level shifting circuitry should be implemented on the
board.

14.4.2 Digital Display Interfaces

14.4.2.1 Signal Descriptions

Please see Chapter 2, “Physical Interfaces” for additional details.

The signal description table has the following headings:

• Signal Name: The name of the signal/pin
• Direction: The buffer direction can be either input, output, or I/O (bidirectional)
• Platform Power: The reference power plane.
• Description: A brief explanation of the signal’s function

Table 156. Display Physical Interfaces Signal Names (Sheet 1 of 2)

Signal Name Direction Description

HDMI / DVI DP / eDP

DDI[1,0]_TXP[0] O Ports 1,0: Transmit Signals

DDI[1,0]_TXP[1] TMDS[1,0]_DATAP[2] DP[1,0]_MAINP[0]
DDI[1,0]_TXP[2] TMDS[1,0]_DATAP[1] DP[1,0]_MAINP[1]
DDI[1,0]_TXP[3] TMDS[1,0]_DATAP[0] DP[1,0]_MAINP[2]
TMDS[1,0]_CLKP DP[1,0]_MAINP[3]

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Table 156. Display Physical Interfaces Signal Names (Sheet 2 of 2)

Signal Name Direction Description

HDMI / DVI DP / eDP

DDI[1,0]_TXN[0] O Ports 1,0: Transmit Complement Signals

DDI[1,0]_TXN[1] TMDS[1,0]_DATAN[2] DP[1,0]_MAINN[0]
DDI[1,0]_TXN[2] TMDS[1,0]_DATAN[1] DP[1,0]_MAINN[1]
DDI[1,0]_TXN[3] TMDS[1,0]_DATAN[0] DP[1,0]_MAINN[2]
TMDS[1,0]_CLKN DP[1,0]_MAINN[3]
DDI[1,0]_AUXP I/O Ports 1,0: Display Port Auxiliary Channel
Unused DP[1,0]_AUXP
DDI[1,0]_AUXN I/O Ports 1,0: Display Port Auxiliary Channel Complement
Unused DP[1,0]_AUXN
DDI[1,0]_HPD I Ports 1,0: Hot Plug Detect
TMDS[1,0]_HPD DP[1,0]_HPD
DDI[1,0]_DDCCLK I/O Ports 1,0: DDC Clock
TMDS[1,0]_DDCCLK Unused
DDI[1,0]_DDCDATA I/O Ports 1,0: DDC Data
TMDS[1,0]_DDCDATA DP[1,0]_EN - Port 0 Enable Strap
DDI[1,0]_BKLTCTL O Ports 1,0: Panel Backlight Brightness Control

HDMI / DVI / DP eDP Only

Unused EDP[1,0]_BKLTCTL
DDI[1,0]_BKLTEN O Ports 1,0: Panel Backlight Enable

HDMI / DVI / DP eDP Only

Unused EDP[1,0]_BKLTEN
DDI[1,0]_VDDEN O Ports 1,0: Panel Power Enable

HDMI / DVI / DP eDP Only

Unused EDP[1,0]_VDDEN
DDI_RCOMP_P/N I/O DDI RCOMP
This signal is used for pre-driver slew rate compensation.
An external precision resistor of 402 Ω ±1% should be connected between
DDI_RCOMP_P and DDI_RCOMP_N.

14.4.2.2 Features

Note: If MIPI dual-link feature is enabled, the software driver should not enable DP or HDMI

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14.4.2.3 High Definition Multimedia Interface

The High-Definition Multimedia Interface (HDMI) is provided for transmitting digital

audio and video signals from DVD players, set-top boxes and other audiovisual sources
to television sets, projectors and other video displays. It can carry high quality multi-
channel audio data and all standard and high-definition consumer electronics video
formats. HDMI display interface connecting the SoC and display devices utilizes
transition minimized differential signaling (TMDS) to carry audiovisual information
through the same HDMI cable.

HDMI includes three separate communications channels: TMDS, DDC, and the optional
CEC (consumer electronics control) (not supported by the SoC). As shown in
Figure 94 the HDMI cable carries four differential pairs that make up the TMDS data
and clock channels. These channels are used to carry video, audio, and auxiliary data.
In addition, HDMI carries a VESA DDC. The DDC is used by an HDMI Source to
determine the capabilities and characteristics of the sink.

Audio, video and auxiliary (control/status) data is transmitted across the three TMDS
data channels. The video pixel clock is transmitted on the TMDS clock channel and is
used by the receiver for data recovery on the three data channels. The digital display
data signals driven natively through the SoC are AC coupled and needs level shifting
to convert the AC coupled signals to the HDMI compliant digital signals.

The SoC HDMI interface is designed as per the High-Definition Multimedia Interface
Specification 1.4. The SoC supports High-Definition Multimedia Interface Compliance
Test Specification 1.4.

14.4.2.3.1 Stereoscopic Support on HDMI

SoC display supports HDMI 1.4 3D video formats. If the HDMI panel is detected to
support 3D video format then the SW driver will program Pipe2dB for the correct pipe
timing parameters.

The left and right frames can be loaded from independent frame buffers in the main
memory. Depending on the input S3D format, the display controller can be enabled do
perform frame repositioning, image scaling, line interleaving.

Figure 94. HDMI Overview

TMDS Data Channel 0

TMDS Data Channel 1

HDMI TMDS Data Channel 2
HDMI
TX RX
TMDS Clock Channel

Hot Plug Detect

Display Data Channel (DDC)

HDMI HDMI
SOURCE SINK

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14.4.2.4 Digital Video Interface (DVI)

The Digital Ports can be configured to drive DVI-D. DVI uses TMDS for transmitting
data from the transmitter to the receiver which is similar to the HDMI protocol but
without the audio and CEC. Refer to the HDMI section for more information on the
signals and data transmission. To drive DVI-I through the back panel the VGA DDC
signals are connected along with the digital data and clock signals from one of the
Digital Ports. When a system has support for a DVI-I port, then either VGA or the DVI-
D through a single DVI-I connector can be driven but not both simultaneously.

14.4.2.5 Display Port

Display Port is a digital communication interface that utilizes differential signalling to

achieve a high bandwidth bus interface designed to support connections between PCs
and monitors, projectors, and TV displays. Display Port is also suitable for display
connections between consumer electronics devices such as high definition optical disc
players, set top boxes, and TV displays.

A Display Port consists of a Main Link, Auxiliary channel, and a Hot Plug Detect signal.
The Main Link is a uni-directional, high-bandwidth, and low latency channel used for
transport of isochronous data streams such as uncompressed video and audio. The
Auxiliary Channel (AUX CH) is a half-duplex bidirectional channel used for link
management and device control. The Hot Plug Detect (HPD) signal serves as an
interrupt request for the sink device.

The SoC supports DisplayPort Standard Version 1.1.

Figure 95. DisplayPort* Overview

Main Link (Isochronous Streams )

DP TX Auxiliary Channel (Link/Device Management) DP RX

Hot Plug Detect (Interrupt Request)

DisplayPort DisplayPort
SOURCE SINK

14.4.2.6 Embedded DisplayPort (eDP)

Embedded DisplayPort (eDP) is a embedded version of the DisplayPort standard

oriented towards applications such as notebook and All-In-One PCs. eDP is supported
only on Digital Display Interfaces 0 and/or 1. Like DisplayPort, Embedded DisplayPort
also consists of a Main Link, Auxiliary channel, and a optional Hot Plug Detect signal.

Each eDP port can be configured for up-to 4 lanes.

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The SoC supports Embedded DisplayPort Standard Version 1.3.

14.4.2.6.1 DisplayPort Auxiliary Channel

A bidirectional AC coupled AUX channel interface replaces the I2C for EDID read, link
management and device control. I2C-to-Aux bridges are required to connect legacy
display devices.

14.4.2.6.2 Hot-Plug Detect (HPD)

The SoC supports HPD for Hot-Plug sink events on the HDMI and DisplayPort interfaces.

14.4.2.6.3 Integrated Audio over HDMI and DisplayPort

SoC can support two audio streams on DP/HDMI ports. Each stream can be
programmable to either DDI port. HDMI/DP audio streams can be sent with video
streams as follows.

LPE mode: In this mode the uncompressed or compressed audio sample buffers are
generated either by OS the audio stack or by audio Lower Power Engine (LPE) and
stored in system memory.The display controller fetches audio samples from these
buffers, forms an SPDIF frame with VUCP and preamble (if needed), then sends out
with video packets.

14.4.2.6.4 High-Bandwidth Digital Content Protection (HDCP)

HDCP is the technology for protecting high definition content against unauthorized copy
or unreceptive between a source (computer, digital set top boxes, etc.) and the sink
(panels, monitor, and TV). The SoC supports HDCP 1.4/2.1 for content protection over
wired displays (HDMI, DisplayPort and Embedded DisplayPort).

14.5 References
• High-Definition Multimedia Interface Specification, Version 1.4
• High-bandwidth Digital Content Protection System, Revision 1.4
• VESA DisplayPort Standard, Version 1.1
• VESA Embedded DisplayPort Standard, Version 1.3

14.6 3D Graphics and Video

The SoC implements a derivative of the Generation 7 graphics engine which consists of
rendering engine and bit stream encoder/decoder engine. The rendering engine is used
for 3D rendering, media compositing and video encoding. The Graphics engine is built
around four execution units (EUs).

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3D Graphics

Video
To SoC
Transaction DDI0 IO

Controller
Router

Display
DDI1 IO

VGA IO

Figure 96. 3D Graphics Block Diagram

14.7 Features
The 3D graphics pipeline architecture simultaneously operates on different primitives or
on different portions of the same primitive. All the cores are fully programmable,
increasing the versatility of the 3D Engine. The Gen 7.0 3D engine provides the
following performance and power-management enhancements:
• Hierarchal-Z
• Video quality enhancements

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14.7.1 3D Engine Execution Units

• The EUs perform 128-bit wide execution per clock.
• Support SIMD8 instructions for vertex processing and SIMD16 instructions for pixel
processing.

14.7.2 3D Pipeline
14.7.2.1 Vertex Fetch (VF) Stage

The VF stage executes 3DPRIMITIVE commands. Some enhancements have been

included to better support legacy D3D APIs as well as SGI OpenGL*.

14.7.2.2 Vertex Shader (VS) Stage

The VS stage performs shading of vertices output by the VF function. The VS unit
produces an output vertex reference for every input vertex reference received from the
VF unit, in the order received.

14.7.2.3 Geometry Shader (GS) Stage

The GS stage receives inputs from the VS stage. Compiled application-provided GS

programs, specifying an algorithm to convert the vertices of an input object into some
output primitives. For example, a GS shader may convert lines of a line strip into
polygons representing a corresponding segment of a blade of grass centered on the
line. Or it could use adjacency information to detect silhouette edges of triangles and
output polygons extruding out from the edges.

14.7.2.4 Clip Stage

The Clip stage performs general processing on incoming 3D objects. However, it also
includes specialized logic to perform a Clip Test function on incoming objects. The Clip
Test optimizes generalized 3D Clipping. The Clip unit examines the position of incoming
vertices, and accepts/rejects 3D objects based on its Clip algorithm.

14.7.2.5 Strips and Fans (SF) Stage

The SF stage performs setup operations required to rasterize 3D objects. The outputs
from the SF stage to the Windower stage contain implementation-specific information
required for the rasterization of objects and also supports clipping of primitives to some
extent.

14.7.2.6 Windower/IZ (WIZ) Stage

The WIZ unit performs an early depth test, which removes failing pixels and eliminates
unnecessary processing overhead.

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The Windower uses the parameters provided by the SF unit in the object-specific
rasterization algorithms. The WIZ unit rasterizes objects into the corresponding set of
pixels. The Windower is also capable of performing dithering, whereby the illusion of a
higher resolution when using low-bpp channels in color buffers is possible. Color
dithering diffuses the sharp color bands seen on smooth-shaded objects.

14.7.3 Video Engine

The video engine is part of the Intel Processor Graphics for image processing, play-
back and transcode of Video applications. Processor Graphics video engine has a
dedicated fixed hardware pipe-line for high quality decode and encode of media
content. This engine supports Full HW acceleration for decode of AVC/H.264, VC-1 and
MPEG -2 contents along with encode of MPEG-2 and AVC/H.264 apart from various
video processing features. The new Processor Graphics Video engine adds support for
processing features such as frame rate conversion, image stabilization and gamut
conversion.

14.8 VED (Video Encode/Decode)

The video engine is part of the Intel Processor Graphics for image processing, play-
back and transcode of Video applications. Processor Graphics video engine has a
dedicated fixed hardware pipe-line for high quality decode and encode of media
content. SoC Video Encode Decode block incorporates VXD 392 video decode core and
supports the following codec: VP8.

3 D G ra p h ic s

V id e o
To SoC
T ra n s a c tio n D D I0 IO
Controller

R o u te r
Display

D D I1 IO

VGA IO

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14.8.1 Features
The features for the Video decode hardware accelerator in SoC are:
• VED core can be configured on a time division multiplex basis to handle single, dual
and multi-stream HD decoding.
• VED provides full hardware acceleration support for VP8.

Table 157. Hardware Accelerated Video Decode Codec Support

Codec Format Level

VP8 1080p30

Note: SoC uses IMG VP8 video decode engine. There are 21 functional units in this decoder.
The Specification states that you can dynamically clock gate some of these units.

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14.9 PCI Configuration Registers

Table 158. Summary of Graphics, Video and Display PCI Configuration Registers—0/2/0
Default
Offset Size Register ID—Description
Value

0h 4 “DID—Offset 0h” on page 294 0F318086h

4h 4 “PCICMD_STS—Offset 4h” on page 295 00100000h

8h 4 “RID_CC—Offset 8h” on page 296 03000000h
Ch 4 “HDR—Offset Ch” on page 297 00000000h

10h 4 “GTTMMADR_LSB—Offset 10h” on page 297 00000000h

14h 4 “GTTMMADR_MSB—Offset 14h” on page 298 00000000h
18h 4 “GMADR_LSB—Offset 18h” on page 299 00000008h

1Ch 4 “GMADR_MSB—Offset 1Ch” on page 299 00000000h

20h 4 “IOBAR—Offset 20h” on page 300 00000001h
2Ch 4 “SSID_SID—Offset 2Ch” on page 301 00000000h

34h 4 “CAPPOINT—Offset 34h” on page 301 000000D0h

3Ch 4 “INTRLINE—Offset 3Ch” on page 302 00000100h
50h 4 “GGC—Offset 50h” on page 303 00000028h

5Ch 4 “BDSM—Offset 5Ch” on page 304 00000000h

60h 4 “MSAC—Offset 60h” on page 305 00020000h
70h 4 “BGSM—Offset 70h” on page 305 00000000h

74h 4 “PAVPC—Offset 74h” on page 306 00000000h

90h 4 “MSI_CAPID_MC—Offset 90h” on page 307 0000B005h
94h 4 “MA—Offset 94h” on page 308 00000000h

98h 4 “MD—Offset 98h” on page 309 00000000h

A4h 4 “AFLC—Offset A4h” on page 309 03060013h

A8h 4 “AFCTLSTS—Offset A8h” on page 310 00000000h

B0h 4 “VCID—Offset B0h” on page 311 01070009h
B4h 4 “VCID—Offset B0h” on page 311 00000000h

C4h 4 “FD—Offset C4h” on page 312 00000000h

D0h 4 “PMCAPID—Offset D0h” on page 313 00229001h
D4h 4 “PMCS—Offset D4h” on page 314 00000000h

E0h 4 “SWSMISCI—Offset E0h” on page 314 00000000h

E4h 4 “ASLE—Offset E4h” on page 315 00000000h
F8h 4 “MANID—Offset F8h” on page 316 00000000h

FCh 4 “ASLS—Offset FCh” on page 317 00000000h

14.9.1 DID—Offset 0h
PCI Device ID and Vendor ID Register

Access Method

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Type: PCI Configuration Register

DID: [B:0, D:2, F:0] + 0h
(Size: 32 bits)

Power Well: Core

Default: 0F318086h
31 28 24 20 16 12 8 4 0

0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0

DEVICEID_0

VENDORID_1
Bit Default &
Description
Range Access

0F31h
31:16 DEVICEID (DEVICEID_0): DID: Identifier assigned to the dev2 PCI
RO

8086h
15:0 VENDORID (VENDORID_1): VID: PCI standard identification for Intel
RO

14.9.2 PCICMD_STS—Offset 4h
PCI Command Register and Status Register

Access Method
Type: PCI Configuration Register PCICMD_STS: [B:0, D:2, F:0] + 4h
(Size: 32 bits)

Power Well: Core

Default: 00100000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CAPABILITY_LIST_7

INTERRUPT_DISABLE_1

BUS_MASTER_ENABLE_3
MEMORY_SPACE_ENABLE_4
IO_SPACE_ENABLE_5
RSVD_6

INTERRUPT_STATUS_8

RSVD_9

RSVD_0

RSVD_2

Bit Default &

Description
Range Access

000h
31:21 RSVD (RSVD_6): Reserved
RO

1b CAPABILITY_LIST (CAPABILITY_LIST_7): CAP: CAPPOINT register at 34h provides

20
RO an offset

0b INTERRUPT_STATUS (INTERRUPT_STATUS_8): IS: 1= Determined by IIR and IER

19
RO memory interface register, 0=no interrupt pending

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Bit Default &

Description
Range Access

000b
18:16 RSVD (RSVD_9): Reserved
RO
00h
15:11 RSVD (RSVD_0): Reserved
RO
0b INTERRUPT_DISABLE (INTERRUPT_DISABLE_1): ID: 0= Interrupt message
10
RW enabled, 1= disabled

00h
9:3 RSVD (RSVD_2): Reserved
RO
0b BUS_MASTER_ENABLE (BUS_MASTER_ENABLE_3): BME: 0= Blocks the sending of
2
RW MSI interrupts, 1= permits

0b MEMORY_SPACE_ENABLE (MEMORY_SPACE_ENABLE_4): MSE: 0= Memory space

1
RW disabled, 1= enabled

0b IO_SPACE_ENABLE (IO_SPACE_ENABLE_5): IOSE: 0= I/O space is disabled,

0
RW 1=enabled

14.9.3 RID_CC—Offset 8h
Revision Identification and Class code registerSOXi Context Save/Restore: Yes

Access Method
Type: PCI Configuration Register
(Size: 32 bits) RID_CC: [B:0, D:2, F:0] + 8h

Power Well: Core

Default: 03000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BASE_CLASS_CODE_1

SUB_CLASS_CODE_2

PROGRAMMING_INTERFACE_3

REVISION_ID_0

Bit Default &

Description
Range Access

00000011b BASE_CLASS_CODE (BASE_CLASS_CODE_1): BCC: MGGC0[VAMEN]=0, 03h else

31:24
RO 04h

00000000b SUB_CLASS_CODE (SUB_CLASS_CODE_2): MGGC0[VAMEN]= 1, 80h,

23:16
RO MGGC0[VAMEN]=0,determined based on GGC register, GMS and IVD

00h PROGRAMMING_INTERFACE (PROGRAMMING_INTERFACE_3):

15:8
RO MGGC0[VAMEN]= 0, 00h display controller, =1, 00h NOP

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Bit Default &

Description
Range Access

00000000b
7:0 REVISION_ID (REVISION_ID_0): RID: value of strapRID[7:0] input pin to GVD
RO

14.9.4 HDR—Offset Ch
Header Type

Access Method
Type: PCI Configuration Register
(Size: 32 bits) HDR: [B:0, D:2, F:0] + Ch

Power Well: Core

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MULTI_FUNCTION_STATUS_1
RSVD_0

RSVD_3
HEADER_CODE_2

Bit Default &

Description
Range Access

00h
31:24 RSVD (RSVD_0): Reserved
RO

0b MULTI_FUNCTION_STATUS (MULTI_FUNCTION_STATUS_1): MFUNC: Integrated

23
RO graphics is a single function

00h HEADER_CODE (HEADER_CODE_2): HDR: Indicates a type 0 configuration space

22:16
RO header format

0000h
15:0 RSVD (RSVD_3): Reserved
RO

14.9.5 GTTMMADR_LSB—Offset 10h

Gfx Memory Mapped Address Range. This is the base address for all memory mapped
registers and GTT table. SOXi Context Save/Restore : Yes This register requests
allocation for the combined Graphics Translation Table Modification Range and Memory
Mapped Range. The range requires 4 MB combined for MMIO and Global GTT aperture,
with 512K of that used by MMIO and 2MB used by GTT. GTTADR will begin at
(GTTMMADR + 2 MB) while the MMIO base address will be the same as GTTMMADR. For
the Global GTT, this range is defined as a memory BAR in graphics device config space.
It is an alias into which software is required to write Page Table Entry values (PTEs).
Software may read PTE values from the global Graphics Translation Table (GTT). PTEs

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cannot be written directly into the global GTT memory area. The allocation is for 4MB
and the base address is defined by bits [35:22]. NOTE : Cedarview only supported 32
bit BARs.

Access Method
Type: PCI Configuration Register
GTTMMADR_LSB: [B:0, D:2, F:0] + 10h
(Size: 32 bits)

Power Well: Core

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MBA_LSB_0

RSVD_1

RSVD_2

MEMTYP_3

RSVD_4
Bit Default &
Description
Range Access

000h MBA_LSB (MBA_LSB_0): Memory Base Address (MBA): Set by the OS, these bits
31:22 correspond to address signals [35:22]. 4MB combined for MMIO and Global GTT table
RW aperture (2MB for MMIO and 2 MB for GTT).
00000h
21:4 RSVD (RSVD_1): RSVD: Hardwired to 0 to indicate at least 4MB address range.
RO
0b RSVD (RSVD_2): Prefetchable Memory (PREFMEM): Hardwired to 0to prevent
3
RO prefetching.

00b MEMTYP (MEMTYP_3): Memory Type (MEMTYP): 00 : To indicate 32 bit base address
2:1
RO 01: Reserved 10 : To indicate 64 bit base address 11: Reserved

0b RSVD (RSVD_4): Memory/IO Space (MIOS): Hardwired to 0 to indicate memory

0
RO space.

14.9.6 GTTMMADR_MSB—Offset 14h

Access Method
Type: PCI Configuration Register GTTMMADR_MSB: [B:0, D:2, F:0] + 14h
(Size: 32 bits)

Power Well: Core

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MBA_MSB_1
RSVD_0

Bit Default &

Description
Range Access

00000000h RSVD (RSVD_0): Reserved for Memory Base Address (RSVD): Must be set to 0 since
31:4
RO addressing above 64GB is not supported.

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Bit Default &

Description
Range Access

0h MBA_MSB (MBA_MSB_1): Memory Base Address (MBA): Set by the OS, these bits
3:0 correspond to address signals [35:22]. 4MB combined for MMIO and Global GTT table
RO aperture (2MB for MMIO and 2 MB for GTT).

14.9.7 GMADR_LSB—Offset 18h

Gfx Aperture location. SOXi Context Save/Restore : Yes GMADR is a Prefetchable range
in order to apply USWC attribute (from the processor point of view) to that range. The
USWC attribute is used by the processor for write combining. Accesses to this range
will be translated to DRAM Physical memory addresses. Fence registers may be used to
sub-divide this range and allow tiled surfaces (determined by fence registers). The
following sizes are supported : 128MB, 256MB, 512MB. (Determined by the MSAC
register) NOTE : Cedarview did not have this BAR.

Access Method
Type: PCI Configuration Register
(Size: 32 bits) GMADR_LSB: [B:0, D:2, F:0] + 18h

Power Well: Core

Default: 00000008h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
ADMSK512_1
ADMSK256_2
RSVD_0

RSVD_3

PREFMEM_4

MEMTYP_5

RSVD_6
Bit Default &
Description
Range Access

000b RSVD (RSVD_0): Memory Base Address (MBA): Memory Base Address (MBA): Set by
31:29
RO the OS, these bits correspond to address signals [35:29].

0b ADMSK512 (ADMSK512_1): 512MB Address Mask (ADMSK512): This bit is either

28 part of the Memory Base Address (R/W) or part of the Address Mask (RO), depending on
RW/L the value of MSAC[2:1]. See MSAC (Dev2, Func 0, offset 62h) for details.

0b ADMSK256 (ADMSK256_2): 256MB Address Mask (ADMSK256): This bit is either

27 part of the Memory Base Address (R/W) or part of the Address Mask (RO), depending on
RW/L the value of MSAC[2:1]. See MSAC (Dev 2, Func 0, offset 62h) for details.
0000000h RSVD (RSVD_3): Address Mask (ADM): Hardwired to 0s to indicate at least 128MB
26:4
RO address range.

1b PREFMEM (PREFMEM_4): Prefetchable Memory (PREFMEM): Hardwired to 1 to enable

3
RO prefetching.

00b MEMTYP (MEMTYP_5): Memory Type (MEMTYP): 00 : To indicate 32 bit base address
2:1
RO 01: Reserved 10 : To indicate 64 bit base address 11: Reserved

0b RSVD (RSVD_6): Memory/IO Space (MIOS): Hardwired to 0 to indicate memory

0
RO space.

14.9.8 GMADR_MSB—Offset 1Ch

Access Method

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Type: PCI Configuration Register

GMADR_MSB: [B:0, D:2, F:0] + 1Ch
(Size: 32 bits)

Power Well: Core

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MBA_1
RSVD_0
Bit Default &
Description
Range Access

0000000h RSVD (RSVD_0): Memory Base Address (MBA2): Set by the OS, these bits correspond
31:4
RO to address signals [63:36].

0h MBA (MBA_1): Memory Base Address (MBA)Set by the OS, these bits correspond to
3:0
RO address signals [35:32]

14.9.9 IOBAR—Offset 20h

I/O Base Address. This is used only by SBIOS. This register is the base address for the
MMIO_INDEX and MMIO_DATA registers SOXi Context Save/Restore : Yes NOTE : This
was at 14h for CDV. This register provides the Base offset of the I/O registers within
Device #2. Access to the 8Bs of IO space is allowed in PM state D0 when IO Enable
(PCICMD bit 0) set. Access is disallowed : 1)in PM states D1-D3 or 2)if IO Enable is
clear or 3)if Device #2 is turned off or 4)if Internal graphics is disabled thru the fuse or
fuse override mechanisms. Note that access to this IO BAR is independent of VGA
functionality within Device #2. If accesses to this IO bar is allowed then the GMCH
claims all 8, 16 or 32 bit IO cycles from the CPU that falls within the 8B claimed.

Access Method
Type: PCI Configuration Register
(Size: 32 bits) IOBAR: [B:0, D:2, F:0] + 20h

Power Well: Core

Default: 00000001h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
BASE_ADDRESS_1
RSVD_0

RSVD_2

RESOURCE_TYPE_RTE_3

Bit Default &

Description
Range Access

0000h
31:16 RSVD (RSVD_0): Reserved
RO

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Bit Default &

Description
Range Access

0000h BASE_ADDRESS (BASE_ADDRESS_1): BA: Set by the OS, these bits correspond to
15:3 address signals [15:6].IOBAR is to be used for both GTLC register programming and
RW GTT table programming. This is an indirect access method.
00b
2:1 RSVD (RSVD_2): Reserved
RO
1b RESOURCE_TYPE_RTE (RESOURCE_TYPE_RTE_3): Indicates a request for I/O
0
RO space

14.9.10 SSID_SID—Offset 2Ch

This register is used to uniquely identify the subsystem where the PCI device resides.

Access Method
Type: PCI Configuration Register
(Size: 32 bits) SSID_SID: [B:0, D:2, F:0] + 2Ch

Power Well: Core

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SUBID_1

SUBVID_0
Bit Default &
Description
Range Access

0000h SUBID (SUBID_1): This value is used to identify the vendor of the subsystem. This
31:16 register should be programmed by BIOS during boot-up. Once written, this register
RW/O becomes Read_Only. This register can only be cleared by a Reset.

0000h SUBVID (SUBVID_0): This value is used to identify the vendor of the subsystem. This
15:0 register should be programmed by BIOS during boot-up. Once written, this register
RW/O becomes Read_Only. This register can only be cleared by a Reset.

14.9.11 CAPPOINT—Offset 34h

This register points to a linked list of capabilities implemented by this device.For VV, the
capability linked list is expected to be : (Head-34, PMCAP-D0, MSI-90, VID-B0,
..End)Old : (Head-34, PMCAP-D0, MSI-90, AFLC-A4, VID-B0, .. End)

Access Method
Type: PCI Configuration Register
(Size: 32 bits) CAPPOINT: [B:0, D:2, F:0] + 34h

Power Well: Core

Default: 000000D0h

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31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0

RSVD_0

CAPABILITIES_POINTER_1
Bit Default &
Description
Range Access

000000h
31:8 RSVD (RSVD_0): Reserved
RO
CAPABILITIES_POINTER (CAPABILITIES_POINTER_1): The first item in the
D0h capabilities list is at address D0h (PMCS). This register should be programmed by BIOS
7:0
RW/O during boot-up. Once written, this register becomes Read_Only. This register can only
be cleared by a Reset.

14.9.12 INTRLINE—Offset 3Ch

3C - Interrupt. This register is programmed by SBIOS. It is not used by the graphics/
display driver. This 8-bit register is used to communicate interrupt line routing
information. It is read/write and must be implemented by the device. POST software
will write the routing information into this register as it initializes and configures the
system. SOXi Context Save/Restore : Yes The value in this register tells which input of
the system interrupt controller(s) the device?s interrupt pin is connected to. The device
itself does not use this value, rather it is used by device drivers and operating systems
to determine priority and vector information. 3D - Interrupt. This register is
programmed by SBIOS. It is not used by the graphics/display driver SOXi Context
Save/Restore : Not required

Access Method
Type: PCI Configuration Register INTRLINE: [B:0, D:2, F:0] + 3Ch
(Size: 32 bits)

Default: 00000100h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
RSVD0

INTERRUPT_PIN_1

INTRLINE_0

Bit Default &

Description
Range Access

0b
31:16 RSVD0: Reserved
RO

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Bit Default &

Description
Range Access

01h INTERRUPT_PIN (INTERRUPT_PIN_1): IPIN: Value indicates which interrupt pin

15:8 this device uses. This field is hard coded to 1h since Valleyview Device 2 is a single
RO function device. The PCI spec requires that it use INTA#.01h: INTA
INTRLINE (INTRLINE_0): ILIN: BIOS written value to communicate interrupt line
00h routing information to the device driverUsed to communicate interrupt line routing
7:0 information. POST software writes the routing information into this register as it
RW initializes and configures the system. The value in this register indicates to which input
of the system interrupt controller the device?s interrupt pin is connected.

14.9.13 GGC—Offset 50h

GMCH Graphics Control Register. SOXi Context Save/Restore : Yes Note : CDV
supported 64MB maximum. CDV had no GGMS field. Note : CDV had more granularity
on the encodings for graphics mode select and only 3 bits.

Access Method
Type: PCI Configuration Register
(Size: 32 bits) GGC: [B:0, D:2, F:0] + 50h

Default: 00000028h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0

VGA_DISABLE_6
RSVD0

RSVD_0
VAMEN_1

RSVD_2

GGMS_3

GMS_4

RSVD_5

GGCLCK_7
Bit Default &
Description
Range Access

0b
31:16 RSVD0: Reserved
RO
0b
15 RSVD (RSVD_0): Reserved
RO

0b VAMEN (VAMEN_1): Enables the use of the iGFX engines for Versatile Acceleration. 1
14 - iGFX engines are in Versatile Acceleration Mode. Device 2 Class Code is 048000h. 0 -
RW/L iGFX engines are in iGFX Mode. Device 2 Class Code is 030000h.
0h
13:10 RSVD (RSVD_2): Reserved
RO
GGMS (GGMS_3): GTT Graphics Memory Size (GGMS): This field is used to select the
amount of Main Memory that is pre-allocated to support the Internal Graphics
Translation Table. The BIOS ensures that memory is pre-allocated only when Internal
graphics is enabled. GSM is assumed to be a contiguous physical DRAM space with DSM,
00b and BIOS needs to allocate a contiguous memory chunk. Hardware will drive the base of
9:8
RW/L GSM from DSM only using the GSM size programmed in the register. 0h: No memory
pre-allocated. GTT cycles (Mem and IO) are not claimed. 1h: 1 MB of memory pre-
allocated for GTT. 2h: 2 MB of memory pre-allocated for GTT. 3h: Reserved. All
unspecified encodings of this register field are reserved, hardware functionality is not
guaranteed if used.

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 Graphics, Video and Display

Bit Default &

Description
Range Access

GMS (GMS_4): Graphics Mode Select (GMS). This field is used to select the amount of
Main Memory that is pre-allocated to support the Internal Graphics device in VGA (non-
linear) and Native (linear) modes. The BIOS ensures that memory is pre-allocated only
when Internal graphics is enabled. Hardware does not clear or set any of these bits
automatically based on IGD being disabled/enabled. BIOS Requirement: BIOS must not
set this field to 0h if IVD (bit 1 of this register) is 0. 0h = 0MB 10h = 512MB 1h = 32MB
2h = 64MB 3h = 96MB 4h = 128MB 5h = 160MB 6h = 192MB 7h = 224MB 8h = 256MB
9h = 288MB Ah = 320MB Bh = 352MB Ch = 384MB Dh = 416MB Eh = 448MB Fh =
00101b 480MB Other = Reserved When GMS != 000 (and VD=0): Address[31:0] is compared
7:3 with VGA memory range. (The VGA memory range is A_0000h to B_FFFFh.). If there is
RW/L a match and MSE = 1 and MEMRD or MEMWR, the access will route as a
Rmdwvgamemen_cr cycle on the RMbus. If the RMbus returns a hit the GVD will select
the command. As well, when 0 the GVD will check if scldown3_address[15:0] is one of
the VGA IO register range. (The VGA IO range is 03B0h - 03BBh and 03C0h - 03DFh.) If
there is a match and IOSE = 1 and the SCL command is either an IORD or IOWR, the
GVD will intiate a (VGA) register cycle on the RMbus. If the RMbus returns a hit the GVD
will select the command When GMS == 000 : No address compare will occur against
VGA memory range or the VGA IO register range. Also, CC[15:8] is changed to 8?h80
from 8'h00
0b
2 RSVD (RSVD_5): Reserved
RO
VGA_DISABLE (VGA_DISABLE_6): VGA Disable (VD): 0: Enable. Device 2 (IGD)
claims VGA memory and IO cycles, the Sub-Class Code within Device 2 Class Code
0b register is 00. 1: Disable. Device 2 (IGD) does not claim VGA cycles (Mem and IO), and
1 the Sub- Class Code field within Device 2 function 0 Class Code register is 80. BIOS
RW/L Requirement: BIOS must not set this bit to 0 if the GMS field pre-allocates no memory.
This bit MUST be set to 1 if Device 2 is disabled either via a fuse or fuse override
(CAPID0[38] = 1) or via a register (DEVEN[3] = 0).

0b
0 GGCLCK (GGCLCK_7): When set to 1b, this bit will lock all bits in this register.
RW/L

14.9.14 BDSM—Offset 5Ch

This register contains the base address of Graphics Data Stolen DRAM memory. Note :
IVB located this register in device 0, 0xB0. Mirrored into device 2, 0x5C.Graphics
Stolen Memory is within DRAM space. The base of stolen memory will always be below
4G.

Access Method
Type: PCI Configuration Register
(Size: 32 bits) BDSM: [B:0, D:2, F:0] + 5Ch

Power Well: Core

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BDSM_0

RSVD_1

BDSM_LOCK_2

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Bit Default &

Description
Range Access

BDSM (BDSM_0): BDSM: BASE_OF_Data_STOLEN_MEMORY. This register contains

bits 31 to 20 of the base address of Data stolen DRAM memory. For certain GTLC
000h generated accesses, this base register will be added to the GTLC provided offset
31:20
RW/L address, forming the full physical address for the PFI fabric. This is also used as a base
for VGA paged accesses. The display engine also uses the register. Signal :
gvd_dsp_cfg_BSM_zcznfwh[31:20].
00000h
19:1 RSVD (RSVD_1): Reserved
RO
0b BDSM_LOCK (BDSM_LOCK_2): This bit will lock all writeable settings in this register,
0
RW/L including itself.

14.9.15 MSAC—Offset 60h

This register determines the size of the graphics memory aperture. Only the system
BIOS will write this register based on pre- boot address allocation efforts. Graphics may
read this register to determine the correct aperture size. System BIOS needs to save
this value on boot so that it can reset it correctly during S3 resume. SOXi Context
Save/Restore : Yes. Note : Cedarview didn't have this register. The size of the aperture
must not be modified by software after its location is written into GMADR (offset 18h).

Access Method
Type: PCI Configuration Register MSAC: [B:0, D:2, F:0] + 60h
(Size: 32 bits)

Power Well: Core

Default: 00020000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
LHSAS_1
RSVD_0

RSVD_2

Bit Default &

Description
Range Access

0000h
31:19 RSVD (RSVD_0): Reserved
RO

LHSAS (LHSAS_1): Untrusted Aperture Size (LHSAS): 00 : bits [28:27] of GMADR

01b register are made R/W allowing 128MB of GMADR. 01 : bit [28] of GMADR is made R/W
18:17 and bit [27] of GMADR is forced to zero allowing 256MB of GMADR. 10 : Illegal
RW programming. 11: bits [28:27] of GMADR register are made Read only and forced to
zero, allowing only 512MB of GMADR.
00000h
16:0 RSVD (RSVD_2): Reserved
RO

14.9.16 BGSM—Offset 70h

Base of GTT table in Gfx Stolen Memory SOXi Context Save/Restore : Yes. Note : IVB
located this register in device 0, 0xB4. Mirrored into Device 2. The GTT table is located
within Graphics Stolen Memory in DRAM space. The base of stolen memory will always
be below 4G.

Access Method

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 Graphics, Video and Display

Type: PCI Configuration Register

BGSM: [B:0, D:2, F:0] + 70h
(Size: 32 bits)

Power Well: Core

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BGSM_0

BGSM_LOCK_2
RSVD_1
Bit Default &
Description
Range Access

BGSM (BGSM_0): BGSM: Gfx Base of GTT Stolen Memory. This register contains bits
31 to 20 of the base address of GTT Table in stolen DRAM memory. BIOS determines the
000h base of GTT stolen memory by subtracting the GTT graphics stolen memory size (PCI
31:20
RW/L Device 2 offset 50 bits 9:8) from the Graphics Base of Data Stolen Memory (PCI Device
2 offset 5C bits 31:20). Signal : gvd_dsp_Cspgtbladdr_dczfwohdczfwoh[31:20].Note :
was 4KB aligned on CDV ie. [31:12]

00000h
19:1 RSVD (RSVD_1): Reserved
RO

0b BGSM_LOCK (BGSM_LOCK_2): This bit will lock all writeable settings in this register
0
RW/L including itself

14.9.17 PAVPC—Offset 74h

Protected Audio Video Control. Similar to IVB, BIOS will program this register for
Valleyview (not the Gfx Driver). SOXi Context Save/Restore : Yes. For Valleyview,
device 2 configuration accesses to 0x74 and Gfx MMIO accesses to 0x1082C0 will both
alias to the same register. This register will be located within Gunit.WOPCMBASE is
derived from : BDSMbase + GMS size - WOPCMSZ. Note : IVB currently derives from :
TOLUD + WOPCMSZ

Access Method
Type: PCI Configuration Register
(Size: 32 bits) PAVPC: [B:0, D:2, F:0] + 74h

Power Well: Core

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSVD_0

RSVD_1

RSVD_2

WOPCMSZ_3
OVTATTACK_4
HVYMODSEL_5
PAVPLOCK_6
PAVPE_7
PCME_8

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Bit Default &

Description
Range Access

RSVD (RSVD_0): Reserved. This field is used to set the base of Protected Content
000h Memory. This corresponds to bits 31:20 of the system memory address range, giving a
31:20
RO 1MB granularity. This value MUST be at least 1MB above the base and below the top of
stolen memory. This register is locked (becomes read-only) when PAVPLOCK = 1b.

00b RSVD (RSVD_1): Reserved. Note : IVB provided 256KB granularity, so these 2 bits
19:18 were RW to support that size option. However, VV will only support 1MB so Gunit will tie
RO bits 19:18 to '00'.

000h
17:6 RSVD (RSVD_2): Reserved
RO

WOPCMSZ (WOPCMSZ_3): 0b ? 1MB Note : IVB had this as a RW bit with value '1'
indicating size 256KB support. Since VV only supports 1MB size, this register is RO for
VV. These are the only sizes supported for IVB. The IVB is going to run PAVP3 Mode
Serpent applications using per-App selection. Therefore, the size chosen should always
0b be 1MB configuration even if Lite mode is chosen using PAVPC register (bit_3 = 0) for
5
RO PAVP2 Mode Applications. This is because CB^2 code needs to be always loaded, since
an App. Which opts for per-App Serpent mode will also execute the CB^2 code). The
driver may consider it a BIOS programming error, if PAVPC Serpent Mode is selected
with only 256KB of WOPCM size. However PAVPC Lite Mode with 1M WOPCM size is
acceptable and not an error, as this may involve per-App selected Serpent Mode.
OVTATTACK (OVTATTACK_4): Override of Unsolicited Connection State Attack and
0b Terminate. 0b Disable Override. Attack Terminate allowed. 1b Enable Override. Attack
4
RW/L Terminate disallowed. This register bit is locked (becomes read-only) when PAVPLOCK =
1b
HVYMODSEL (HVYMODSEL_5): In IVB, this bit is a care only for PAVP2 mode of
operation (and a chicken bit is also set). For IVB PAVP2 mode: 0 : Lite Mode (Non-
Serpent Mode) 1: Serpent Mode For PAVP3 mode of operation, this bit_3 is a care, only
if the per-App Memory Config is disabled due to the clearing of an additional Chicken
bit_9 in IVB Crypto Function Control_1 Reg (@ address 0x320F0h). For chicken bit
0b enabled IVB PAVP3 mode, this one type boot time programming has been replaced by
3 per-Media App. Programming (through the Media Crypto Copy command). Note that IVB
RW/L PAVP2 or PAVP3 Mode selection is done by programming bit_8 of MFX_MODE ? Video
Mode Register. (Note again, that when in PAVP3 Mode, the per-App Memory Config.
(Serpent/Lite) feature for enabling, requires the further setting of a global one time
chicken bit to be set (bit_9 = ?1/mask_bit_25 = ?1) in the IVB Crypto Function
Control_1 Register @ address 0x320F0h). Note : Valleyview does not support PAVP2
mode. Only PAVP3 mode is supported (a superset of PAVP2).

0b PAVPLOCK (PAVPLOCK_6): This bit will lock all writeable contents in this register
2 when set(including itself).Only a hw reset can unlock the register again. This Lock bit if
RW/L PAVP is enabled (PAVPE = 1)

0b PAVPE (PAVPE_7): 0: PAVP functionality is disabled. 1: enabled. This register is

1
RW/L locked when PAVPLOCK=1

PCME (PCME_8): PCME = Protected Content Memory Enable This field enables
Protected Content Memory within Graphics Stolen Memory. This memory is the same as
the WOPCM area. The size of the WOPCM area is defined by bit_5 of this register.
0b WOPCM is the only remaining flavor of range protected memory. 0: WOPCM protection
0
RW/L disabled. 1 : WOPCM protection enabled. This bit must be programmed to 1 when PAVP
is enabled. With per-App Memory configuration support in IVB, the range check for the
WOPCM memory area should always happen when this bit is set, irrespective of Lite or
AES mode programming, or PAVP2 or PAVP3 Mode programming.

14.9.18 MSI_CAPID_MC—Offset 90h

Message Signaled Interrupts Capability ID.SOXi Context Save/Restore : Yes. Message
Signaled Control Register. SOXi Context Save/Restore : Yes

Access Method

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 Graphics, Video and Display

Type: PCI Configuration Register

MSI_CAPID_MC: [B:0, D:2, F:0] + 90h
(Size: 32 bits)

Power Well: Core

Default: 0000B005h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 1 0 1

ADDRESS_64_BIT_CAPABLE_3

POINTER_TO_NEXT_CAPABILITY_0
MULTIPLE_MESSAGE_ENABLE_4

MULTIPLE_MESSAGE_CAPABLE_5

CAPABILITY_ID_1
MSI_ENABLE_6
RSVD_2

Bit Default &

Description
Range Access

00h
31:24 RSVD (RSVD_2): Reserved
RO
0b ADDRESS_64_BIT_CAPABLE (ADDRESS_64_BIT_CAPABLE_3): C64: 32-bit
23
RO capable only

MULTIPLE_MESSAGE_ENABLE (MULTIPLE_MESSAGE_ENABLE_4): MME: This

000b field is RW for software compatibility, but only a single message is ever generated.
22:20 System software programs this field to indicate the actual number of messages
RW allocated to this device. This number will be equal to or less than the number actually
requested. The encoding is the same as for the MMC field below.
MULTIPLE_MESSAGE_CAPABLE (MULTIPLE_MESSAGE_CAPABLE_5): MMC: This
000b device is only single message capable System Software reads this field to determine the
19:17
RO number of messages being requested by this device. Value: Number of requests 000: 1.
001- 111: Reserved

MSI_ENABLE (MSI_ENABLE_6): MSIE: If set, MSI is enabled and traditional

0b interrupts are not used to generate interrupts. PCICMDSTS.BME must be set for an MSI
16
RW to be generated. 0 : MSI interrupts are disabled. 1 : MSI interrupts are enabled. Permits
sending an MSI interrupt.
POINTER_TO_NEXT_CAPABILITY (POINTER_TO_NEXT_CAPABILITY_0): Points
B0h to the next item in the list (B0=VCID support). This register should be programmed by
15:8
RW/O BIOS during boot-up. Once written, this register becomes Read_Only. This register can
only be cleared by a Reset.
05h
7:0 CAPABILITY_ID (CAPABILITY_ID_1): CAPID: Indicates an MSI capability
RO

14.9.19 MA—Offset 94h

Message Address.SOXi Context Save/Restore : Yes

Access Method
Type: PCI Configuration Register
(Size: 32 bits) MA: [B:0, D:2, F:0] + 94h

Power Well: Core

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Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADDRESS_0

RSVD_1
Bit Default &
Description
Range Access

00000000h ADDRESS (ADDRESS_0): MA: Lower 32-bits of the system specified message
31:2 address, always DW aligned. When the GVD issues an MSI interrupt as a MEMWR on the
RW SCL, the memory address corresponds to the value of this field
00b
1:0 RSVD (RSVD_1): Reserved
RO

14.9.20 MD—Offset 98h

Message Data.SOXi Context Save/Restore : Yes

Access Method
Type: PCI Configuration Register
(Size: 32 bits) MD: [B:0, D:2, F:0] + 98h

Power Well: Core

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSVD_0

DATA_1

Bit Default &

Description
Range Access

0000h
31:16 RSVD (RSVD_0): Reserved
RO

0000h DATA (DATA_1): MD: This 16-bit field is programmed by system software. This is
15:0
RW forms the lower word of data for the MSI write transaction.

14.9.21 AFLC—Offset A4h

FLR capability advertisement.SOXi Context Save/Restore : Yes

Access Method
Type: PCI Configuration Register AFLC: [B:0, D:2, F:0] + A4h
(Size: 32 bits)

Power Well: Core

Default: 03060013h

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 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 1 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1

RSVD_2

TP_CAP_4
FLR_CAP_3

LENGTH_5

NXT_PTR_0

CAP_ID_1
Bit Default &
Description
Range Access

00h
31:26 RSVD (RSVD_2): Reserved
RO
1b FLR_CAP (FLR_CAP_3): Function Level Reset Capability (FLR_CAP): 0: Function Level
25
RO Reset is not supported 1: Function Level Reset is supported

1b TP_CAP (TP_CAP_4): Transactions Pending Capability (TP_CAP): 0: Transactions

24
RO Pending bit is not supported 1: Transactions Pending bit is supported

06h LENGTH (LENGTH_5): Advanced Features Structure Length (LENGTH): The Advanced
23:16
RO Features Capability structure is 6 bytes long.

NXT_PTR (NXT_PTR_0): Next Pointer (NXT_PTR): Removed FLR capability per HSD
00h 259253. Nulled the next pointer. Points to the next item in the list (B0=Vendor
15:8 Capabilities ID)This register should be programmed by BIOS during boot-up. Once
RW/O written, this register becomes Read_Only. This register can only be cleared by a Reset.
Write once so capabilities list can be changed if needed.

13h CAP_ID (CAP_ID_1): Capability Identifier (CAP_ID): A value of 13h identifies that this
7:0
RO PCI Function is capable of Advanced Features.

14.9.22 AFCTLSTS—Offset A8h

FLR control. Advanced Feature Status.SOXi Context Save/Restore : Not required

Access Method
Type: PCI Configuration Register AFCTLSTS: [B:0, D:2, F:0] + A8h
(Size: 32 bits)

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSVD0

RSVD_2

TP_3

RSVD_0

INIT_FLR_1

Bit Default &

Description
Range Access

0b
31:16 RSVD0: Reserved
RO

00h
15:9 RSVD (RSVD_2): Reserved (RSVD):
RO

TP (TP_3): Transaction Pending (TP): 1: The Function has issued one or more non-
0b posted transactions which have not been completed, including non-posted transactions
8
RO that a target has terminated with Retry. 0: All non-posted transactions have been
completed.

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Bit Default &

Description
Range Access

00h
7:1 RSVD (RSVD_0): Reserved (RSVD):
RO
INIT_FLR (INIT_FLR_1): Initiate Function Level Reset (INIT_FLR): A write of 1b
initiates Function Level Reset (FLR). FLR requirements are defined in the PCI Express
0b Base Specification. Registers and state information that do not apply to conventional PCI
0
RW/1S are exempt from the FLR requirements given there. Once written 1, FLR will be initiated.
During FLR, a read will return 1?s since device 2 reads abort. Once FLR completes,
hardware will clear the bit to 0.

14.9.23 VCID—Offset B0h

Vendor Capability ID.SOXi Context Save/Restore : Yes

Access Method
Type: PCI Configuration Register
(Size: 32 bits) VCID: [B:0, D:2, F:0] + B0h

Power Well: Core

Default: 01070009h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1
VERSION_0

LENGTH_1

NEXT_CAPABILITY_POINTER_2

CAPABILITY_ID_CID_3
Bit Default &
Description
Range Access

01h VERSION (VERSION_0): VS: Identifies this as the first revision of the CAPID register
31:24
RO definition

07h LENGTH (LENGTH_1): LEN: this field has the value of 07h to indicate structure length
23:16
RO (8 bytes)

NEXT_CAPABILITY_POINTER (NEXT_CAPABILITY_POINTER_2): 00 indicates

00h capability list ends here. This register should be programmed by BIOS during boot-up.
15:8
RW/O Once written, this register becomes Read_Only. This register can only be cleared by a
Reset.Write-once allowing the capability list to be changed.
09h CAPABILITY_ID_CID (CAPABILITY_ID_CID_3): Identifies this as a vendor
7:0
RO dependent capability pointers

14.9.24 VC—Offset B4h

Vendor Capabilities. Any SKU related fuses would be added here.SOXi Context Save/
Restore : Not required

Access Method

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 Graphics, Video and Display

Type: PCI Configuration Register

VC: [B:0, D:2, F:0] + B4h
(Size: 32 bits)

Power Well: Core

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RSVD_0

RSVD_1
Bit Default &
Description
Range Access

0000000h
31:1 Reserved (RSVD_0): Reserved
RO
0b
0 Reserved (RSVD_1): Placeholder for sku related fusing. VLV has no need for this
RO

14.9.25 FD—Offset C4h

Functional Disable. used by SBIOS, not by driver.SOXi Context Save/Restore : Yes

Access Method
Type: PCI Configuration Register
FD: [B:0, D:2, F:0] + C4h
(Size: 32 bits)

Power Well: Core

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSVD_0

FUNCTION_DISABLE_1

Bit Default &

Description
Range Access

00000000h
31:1 RSVD (RSVD_0): Reserved
RO

FUNCTION_DISABLE (FUNCTION_DISABLE_1): FD: 0 : Default - normal operation.

1 : When set, the function is disabled (configuration space is disabled). All new requests
0b on the IOSF Primary bus, including any new configuration cycle requests are not claimed
0
RW on IOSF Primary. This bit as no effect register accessibility via IOSF SB. Once
programmed to '1', the only way to re-enable device 2 is via an IOSF SB write of '0' to
this register.

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14.9.26 PMCAPID—Offset D0h

Power Management Capabilities ID and PM capabilities.SOXi Context Save/Restore :
Yes

Access Method
Type: PCI Configuration Register
PMCAPID: [B:0, D:2, F:0] + D0h
(Size: 32 bits)

Power Well: Core

Default: 00229001h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1
D2_SUPPORT_3
D1_SUPPORT_4

CAPABILITIES_ID_1
RSVD_5

DEVICE_SPECIFIC_INITIALIZATION_6

RSVD_7

VERSION_8
PME_SUPPORT_2

NEXT_POINTER_0

Bit Default &

Description
Range Access

00h PME_SUPPORT (PME_SUPPORT_2): PMES The graphics controller does not generate
31:27
RO PME

0b
26 D2_SUPPORT (D2_SUPPORT_3): D2S: D2 not supported
RO

0b
25 D1_SUPPORT (D1_SUPPORT_4): D1S: D1 not supported
RO
000b
24:22 RSVD (RSVD_5): Reserved
RO
1b DEVICE_SPECIFIC_INITIALIZATION (DEVICE_SPECIFIC_INITIALIZATION_6):
21
RO Hardwired to 1

00b
20:19 RSVD (RSVD_7): Reserved
RO
010b
18:16 VERSION (VERSION_8): Verion compliance with revision 1.1 of PCI PM spec
RO
NEXT_POINTER (NEXT_POINTER_0): Indicates the next item in the capabilities
90h list.This register should be programmed by BIOS during boot-up. Once written, this
15:8
RW/O register becomes Read_Only. This register can only be cleared by a Reset. Write once
allowing changing of the capabilities list.
01h
7:0 CAPABILITIES_ID (CAPABILITIES_ID_1): CAPID: SIG defines this ID is 01h for PM
RO

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 Graphics, Video and Display

14.9.27 PMCS—Offset D4h

Power Management Control/Status. Driver doesn't use this register. SBIOS doesn't use
this register SOXi Context Save/Restore : Yes.

Access Method
Type: PCI Configuration Register
PMCS: [B:0, D:2, F:0] + D4h
(Size: 32 bits)

Power Well: Core

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RSVD_0

POWER_STATE_PS_1
Bit Default &
Description
Range Access

00000000h
31:2 RSVD (RSVD_0): Reserved
RO

POWER_STATE_PS (POWER_STATE_PS_1): This field indicates the current power

state of the IGD and can be used to set the IGD into a new power state. If software
attempts to write an unsupported state to this field, write operation must complete
00b normally on the bus, but the data is discarded and no state change occurs. On a
1:0 transition from D3 to D0 the graphics controller is optionally reset to initial values.
RW Behavior of the graphics controller in supported states is detailed in the power
management section of the Bspec. Bits[1:0] Power state 00: D0 Default 01: D1 Not
Supported 10: D2 Not Supported 11: D3 Signal : gvd_dsp_power_state_d3_zncznfwoh
output to 2D.

14.9.28 SWSMISCI—Offset E0h

Software SMI or SCI.To generate a SW SMI event, software should program bit 15:0
and trigger SMI.This register follows the Cedarview format. Note : ILK/SNB/IVB had
SCI and SMI separated (E0 and E8) As long as there is the potential that DVO port
legacy drivers exist which expect this register at this address, this must be reserved for
this register. The SCI mechanism for driver / BIOS communication. SMI is a system
wide lock interrupt (halts the all the cores) as opposed to SCI. Vista and Win7
recommend to use the SCI. The SMI is slowly being phased out. This register serves 2
purposes: 1) Support selection of SMI or SCI event source (SMISCISEL - bit15) 2)
Event trigger (bit 0). To generate a SW SCI event, software (System BIOS/Graphics
driver) should program bit 15 (SMISCISEL) to 1. This is typically programmed once
(assuming SMIs are never triggered). On a ?0? to ?1? subsequent transition in bit 0 of
this register (caused by a software write operation), GMCH sends a single SCI
message. The SCI will set the DMISCI bit in its TCO1_STS register and TCOSCI_STS bit
in its GPE0 register upon receiving this message from DMI. Once written as 1, software
must write a ?0? to this bit to clear it, and all other write transitions (1-)0, 0-)0, 1-)1)
or if bit 15 is ?0? will not cause GMCH to send SCI message to DMI link. To generate a
SW SMI event, software should program bit 15 to 0 and trigger an SMI.

Access Method

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Type: PCI Configuration Register

SWSMISCI: [B:0, D:2, F:0] + E0h
(Size: 32 bits)

Power Well: Core

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SMI_OR_SCI_EVENT_SELECT_1

SOFTWARE_SCRATCH_BITS_2
RSVD_0

SMI_OR_SCI_EVENT_3
Bit Default &
Description
Range Access

0000h
31:16 RSVD (RSVD_0): Reserved
RO

0b SMI_OR_SCI_EVENT_SELECT (SMI_OR_SCI_EVENT_SELECT_1): MCS: SMI or

15
RW SCI event select. 0 = SMI,1 = SCI

0000h SOFTWARE_SCRATCH_BITS (SOFTWARE_SCRATCH_BITS_2): Used by driver to

14:1
RW communicate information to SBIOS

SMI_OR_SCI_EVENT (SMI_OR_SCI_EVENT_3): MCE:MCS=1, setting this bit

0b causes an SCI. MCS=0, setting this bit causes an SMI. A 1 to 0, 0 to 0 or 1 to 1
0
RW transition of this bit does not trigger any events. The graphics driver writes to this
register as a means to interrupt the SBIOS

14.9.29 ASLE—Offset E4h

System Display Event Register. SBIOS writes this reg to generate interrupt to graphics/
display driver.

Access Method
Type: PCI Configuration Register
ASLE: [B:0, D:2, F:0] + E4h
(Size: 32 bits)

Power Well: Core

Default: 00000000h

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 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ASLE_SCRATCH_TRIGGER_3_0

ASLE_SCRATCH_TRIGGER_2_1

ASLE_SCRATCH_TRIGGER_1_2

ASLE_SCRATCH_TRIGGER_0_3
Bit Default &
Description
Range Access

ASLE_SCRATCH_TRIGGER_3 (ASLE_SCRATCH_TRIGGER_3_0): AST3: The

00h writing of this by field (byte) ? even if just writing back the original contents ? will
31:24 trigger a display controller interrupt (when the memory interface register bits IER[0] =
RW 1 and IMR[0] = 0). If written as part of a 16-bit or 32-bit write, only one interrupt is
generated in common
ASLE_SCRATCH_TRIGGER_2 (ASLE_SCRATCH_TRIGGER_2_1): AST2: The
00h writing of this by field (byte) ? even if just writing back the original contents ? will
23:16 trigger a display controller interrupt (when the memory interface register bits IER[0] =
RW 1 and IMR[0] = 0). If written as part of a 16-bit or 32-bit write, only one interrupt is
generated in common

ASLE_SCRATCH_TRIGGER_1 (ASLE_SCRATCH_TRIGGER_1_2): AST1: The

00h writing of this by field (byte) ? even if just writing back the original contents ? will
15:8 trigger a display controller interrupt (when the memory interface register bits IER[0] =
RW 1 and IMR[0] = 0). If written as part of a 16-bit or 32-bit write, only one interrupt is
generated in common
ASLE_SCRATCH_TRIGGER_0 (ASLE_SCRATCH_TRIGGER_0_3): AST0: The
00h writing of this by field (byte) ? even if just writing back the original contents ? will
7:0 trigger a display controller interrupt (when the memory interface register bits IER[0] =
RW 1 and IMR[0] = 0). If written as part of a 16-bit or 32-bit write, only one interrupt is
generated in common

14.9.30 MANID—Offset F8h

Manufacturing ID. SOXi Context Save/Restore : Not required

Access Method
Type: PCI Configuration Register
(Size: 32 bits) MANID: [B:0, D:2, F:0] + F8h

Power Well: Core

Default: 00000000h

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31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RSVD_0

STEPPING_ID_1

MANUFACTURING_ID_2
Bit Default &
Description
Range Access

00h
31:24 RSVD (RSVD_0): Reserved
RO
00000000b Stepping_ID (STEPPING_ID_1): Hardwired to strapRID[7:0] via top level
23:16
RO metal.23:16 - Manufacturing Stepping ID (00 = A0)

MANUFACTURING_ID (MANUFACTURING_ID_2): Hardwired to strapMANID[15:0]

0000h via top level metal. 15:8 - Foundry (0Fh = Intel, Others = Reserved) 7:3 - Fab process
15:0 12h : Fab code for P1263 13h : P1264 14h : P1265 15h : P1266 ... 1Ah : P1271 (VV
RO POR) Others : Reserved 2:0 - Identifies the dot process 000 = Code for 0 001 = Code
for .1 (VV POR) 010 = Code for .2 110 = Code for .4 011 = Code for .7

14.9.31 ASLS—Offset FCh

ASL Storage. The Valleyview display driver does not need this register since memory
Operational Region (OpRegion) is available. This register is kept for use as scratch
space. SOXi Context Save/Restore : Yes This software scratch register only needs to be
read/write accessible. The exact bit register usage must be worked out in common
between System BIOS and driver software, but storage for switching/indicating up to 6
devices is possible with this amount. For each device, the ASL control method with
require two bits for _DOD (BIOS detectable yes or no, VGA/NonVGA), one bit for _DGS
(enable/disable requested), and two bits for _DCS (enabled now/disabled now,
connected or not).

Access Method
Type: PCI Configuration Register
(Size: 32 bits) ASLS: [B:0, D:2, F:0] + FCh

Power Well: Core

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCRATCH_0

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 Graphics, Video and Display

Bit Default &

Description
Range Access

SCRATCH (SCRATCH_0): This register provides a means for the BIOS to communicate
with the driver. This definition of this scratch register is worked out in common between
00000000h System BIOS and driver software. Storage for up to 6 devices is possible. For each
31:0
RW device, the ASL control method requires two bits for _DOD (BIOS detectable yes or no,
VGA/NonVGA), one bit for _DGS (enable/disable requested), and two bits for DCS
(enabled now/disabled now, connected or not).

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 Graphics, Video and Display

14.10 Memory Mapped Registers (1 of 2)

Table 159. Summary of Display Memory Mapped I/O Registers—GTTMMADR_LSB

Offset Size Register ID—Description Default Value

3B4h 1 “CRX (CRX_MDA)—Offset 3B4h” on page 325 00h

3B5h 1 “CR (CR_MDA)—Offset 3B5h” on page 326 00h

3C0h 1 “ARX—Offset 3C0h” on page 326 00h

3C1h 1 “ARX—Offset 3C0h” on page 326 00h
3C4h 1 “SRX—Offset 3C4h” on page 328 00h

3C5h 1 “SRX—Offset 3C4h” on page 328 00h

3C6h 1 “DACMASK—Offset 3C6h” on page 329 00h
3C8h 1 “DACWX—Offset 3C8h” on page 329 00h

3C9h 1 “DACDATA—Offset 3C9h” on page 330 00h

3CAh 1 “FCR (FCR_Read)—Offset 3CAh” on page 331 00h
3CCh 1 “MSR (MSR_READ)—Offset 3CCh” on page 332 00h

3CEh 1 “GRX—Offset 3CEh” on page 333 00h

3CFh 1 “GRX—Offset 3CEh” on page 333 00h
3D4h 1 “CRX (CRX_CGA)—Offset 3D4h” on page 334 00h

3D5h 1 “CR (CR_CGA)—Offset 3D5h” on page 335 00h

5010h 4 “GPIOCTL_0—Offset 5010h” on page 335 00000808h
5014h 4 “GPIOCTL_1—Offset 5014h” on page 337 00000808h

5018h 4 “GPIOCTL_2—Offset 5018h” on page 338 00000808h

501Ch 4 “GPIOCTL_3—Offset 501Ch” on page 340 00000808h
5020h 4 “GPIOCTL_4—Offset 5020h” on page 341 00000808h

5100h 4 “GMBUS0—Offset 5100h” on page 343 00000000h

5104h 4 “GMBUS1—Offset 5104h” on page 344 00000000h

5108h 4 “GMBUS2—Offset 5108h” on page 346 00000800h

510Ch 4 “GMBUS3—Offset 510Ch” on page 348 00000000h
5110h 4 “GMBUS4—Offset 5110h” on page 349 00000000h

5120h 4 “GMBUS5—Offset 5120h” on page 349 00000000h

5130h 4 “GMBUS6—Offset 5130h” on page 350 00000000h
5134h 4 “GMBUS7—Offset 5134h” on page 351 00000000h

6014h 4 “DPLLA_CTRL—Offset 6014h” on page 351 00002000h

6018h 4 “DPLLB_CTRL—Offset 6018h” on page 353 00006000h
601Ch 4 “DPLLAMD—Offset 601Ch” on page 355 00000003h

6020h 4 “DPLLBMD—Offset 6020h” on page 356 00000003h

6024h 4 “RAWCLK_FREQ—Offset 6024h” on page 358 0000007Dh
6104h 4 “D_STATE—Offset 6104h” on page 358 20D00400h

6200h 4 “DSPCLK_GATE_D—Offset 6200h” on page 359 10000000h

6204h 4 “DPPSR_CGDIS—Offset 6204h” on page 362 00000200h
6210h 4 “RAMCLK_GATE_D—Offset 6210h” on page 364 00000000h

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Table 159. Summary of Display Memory Mapped I/O Registers—GTTMMADR_LSB

Offset Size Register ID—Description Default Value

6500h 4 “FW_BLC_SELF—Offset 6500h” on page 366 00000000h

6504h 4 “MI_ARB—Offset 6504h” on page 367 00000000h

6508h 4 “CZCLK_CDCLK_FREQ_RATIO—Offset 6508h” on page 368 00000077h
650Ch 4 “GCI_CONTROL—Offset 650Ch” on page 371 00004000h

6510h 4 “GMBUSFREQ—Offset 6510h” on page 372 000000A0h

A000h 4 “DPALETTE_A—Offset A000h” on page 373 00000000h
A800h 4 “DPALETTE_B—Offset A800h” on page 374 00000000h

B000h 4 “MIPIA_DEVICE_READY_REG—Offset B000h” on page 374 00000000h

B004h 4 “MIPIA_INTR_STAT_REG—Offset B004h” on page 375 00000000h
B008h 4 “MIPIA_INTR_EN_REG—Offset B008h” on page 377 00000000h

B00Ch 4 “MIPIA_DSI_FUNC_PRG__REG—Offset B00Ch” on page 379 00000001h

B010h 4 “MIPIA_HS_TX_TIMEOUT_REG—Offset B010h” on page 380 00000000h
B014h 4 “MIPIA_LP_RX_TIMEOUT_REG—Offset B014h” on page 381 00000000h

B018h 4 “MIPIA_TURN_AROUND_TIMEOUT_REG—Offset B018h” on page 382 00000000h

B01Ch 4 “MIPIA_DEVICE_RESET_TIMER—Offset B01Ch” on page 383 00000000h
B020h 4 “MIPIA_DPI_RESOLUTION_REG—Offset B020h” on page 384 00000000h

B024h 4 “MIPIA_DBI_RESOLUTION_REG—Offset B024h” on page 384 00000000h

B028h 4 “MIPIA_HORIZ_SYNC_PADDING_COUNT—Offset B028h” on page 385 00000000h
B02Ch 4 “MIPIA_HORIZ_BACK_PORCH_COUNT—Offset B02Ch” on page 386 00000000h

B030h 4 “MIPIA_HORIZ_FRONT_PORCH_COUNT—Offset B030h” on page 386 00000000h

B034h 4 “MIPIA_HORIZ_ACTIVE_AREA_COUNT—Offset B034h” on page 387 00000000h
B038h 4 “MIPIA_VERT_SYNC_PADDING_COUNT—Offset B038h” on page 388 00000000h

B03Ch 4 “MIPIA_VERT_BACK_PORCH_COUNT—Offset B03Ch” on page 388 00000000h

B040h 4 “MIPIA_VERT_FRONT_PORCH_COUNT—Offset B040h” on page 389 00000000h

B044h 4 “MIPIA_HIGH_LOW_SWITCH_COUNT—Offset B044h” on page 390 00000000h

B048h 4 “MIPIA_DPI_CTRL_REG—Offset B048h” on page 391 00000000h
B04Ch 4 “MIPIA_DPI_DATA_REGISTER—Offset B04Ch” on page 392 00000000h

B050h 4 “MIPIA_INIT_COUNT_REGISTER—Offset B050h” on page 392 00000000h

B054h 4 “MIPIA_MAX_RETURN_PKT_SIZE_REGISTER—Offset B054h” on page 393 00000000h
B058h 4 “MIPIA_VIDEO_MODE_FORMAT_REGISTER—Offset B058h” on page 393 00000000h

B05Ch 4 “MIPIA_EOT_DISABLE_REGISTER—Offset B05Ch” on page 394 00000000h

B060h 4 “MIPIA_LP_BYTECLK_REGISTER—Offset B060h” on page 396 00000000h
B064h 4 “MIPIA_LP_GEN_DATA_REGISTER—Offset B064h” on page 396 00000000h

B068h 4 “MIPIA_HS_GEN_DATA_REGISTER—Offset B068h” on page 397 00000000h

B06Ch 4 “MIPIA_LP_GEN_CTRL_REGISTER—Offset B06Ch” on page 397 00000000h
B070h 4 “MIPIA_HS_GEN_CTRL_REGISTER—Offset B070h” on page 398 00000000h

B074h 4 “MIPIA_GEN_FIFO_STAT_REGISTER—Offset B074h” on page 399 1E060606h

B078h 4 “MIPIA_HS_LS_DBI_ENABLE_REG—Offset B078h” on page 400 00000000h
B07Ch 4 “MIPIA_RESERVED—Offset B07Ch” on page 401 00000000h

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 Graphics, Video and Display

Table 159. Summary of Display Memory Mapped I/O Registers—GTTMMADR_LSB

Offset Size Register ID—Description Default Value

B080h 4 “MIPIA_DPHY_PARAM_REG—Offset B080h” on page 401 0B061A04h

B084h 4 “MIPIA_DBI_BW_CTRL_REG—Offset B084h” on page 402 00000000h

B088h 4 “MIPIA_CLK_LANE_SWITCHING_TIME_CNT—Offset B088h” on page 403 00000000h
B08Ch 4 “MIPIA_STOP_STATE_STALL—Offset B08Ch” on page 404 00000000h

B090h 4 “MIPIA_INTR_STAT_REG_1—Offset B090h” on page 404 00000000h

B094h 4 “MIPIA_INTR_EN_REG_1—Offset B094h” on page 405 00000000h
B100h 4 “MIPIA_DBI_TYPEC_CTRL—Offset B100h” on page 406 00000000h

B104h 4 “MIPIA_CTRL—Offset B104h” on page 407 00000000h

B108h 4 “MIPIA_DATA_ADD—Offset B108h” on page 407 00000000h
B10Ch 4 “MIPIA_DATA_LEN—Offset B10Ch” on page 408 00000000h

B110h 4 “MIPIA_CMD_ADD—Offset B110h” on page 408 00000000h

B114h 4 “MIPIA_CMD_LEN—Offset B114h” on page 409 00000000h
B118h 4 “MIPIA_RD_DATA_RETURN0—Offset B118h” on page 410 00000000h

B11Ch 4 “MIPIA_RD_DATA_RETURN1—Offset B11Ch” on page 410 00000000h

B120h 4 “MIPIA_RD_DATA_RETURN2—Offset B120h” on page 411 00000000h
B124h 4 “MIPIA_RD_DATA_RETURN3—Offset B124h” on page 412 00000000h

B128h 4 “MIPIA_RD_DATA_RETURN4—Offset B128h” on page 412 00000000h

B12Ch 4 “MIPIA_RD_DATA_RETURN5—Offset B12Ch” on page 413 00000000h
B130h 4 “MIPIA_RD_DATA_RETURN6—Offset B130h” on page 413 00000000h

B134h 4 “MIPIA_RD_DATA_RETURN7—Offset B134h” on page 414 00000000h

B138h 4 “MIPIA_RD_DATA_VALID—Offset B138h” on page 414 00000000h
B800h 4 “MIPIC_DEVICE_READY_REG—Offset B800h” on page 415 00000000h

B804h 4 “MIPIC_INTR_STAT_REG—Offset B804h” on page 416 00000000h

B808h 4 “MIPIC_INTR_EN_REG—Offset B808h” on page 418 00000000h

B80Ch 4 “MIPIC_DSI_FUNC_PRG__REG—Offset B80Ch” on page 420 00000001h

B810h 4 “MIPIC_HS_TX_TIMEOUT_REG—Offset B810h” on page 421 00000000h
B814h 4 “MIPIC_LP_RX_TIMEOUT_REG—Offset B814h” on page 422 00000000h

B818h 4 “MIPIC_TURN_AROUND_TIMEOUT_REG—Offset B818h” on page 422 00000000h

B81Ch 4 “MIPIC_DEVICE_RESET_TIMER—Offset B81Ch” on page 423 00000000h
B820h 4 “MIPIC_DPI_RESOLUTION_REG—Offset B820h” on page 424 00000000h

B824h 4 “MIPIC_DBI_RESOLUTION_REG—Offset B824h” on page 424 00000000h

B828h 4 “MIPIC_HORIZ_SYNC_PADDING_COUNT—Offset B828h” on page 425 00000000h
B82Ch 4 “MIPIC_HORIZ_BACK_PORCH_COUNT—Offset B82Ch” on page 426 00000000h

B830h 4 “MIPIC_HORIZ_FRONT_PORCH_COUNT—Offset B830h” on page 426 00000000h

B834h 4 “MIPIC_HORIZ_ACTIVE_AREA_COUNT—Offset B834h” on page 427 00000000h
B838h 4 “MIPIC_VERT_SYNC_PADDING_COUNT—Offset B838h” on page 428 00000000h

B83Ch 4 “MIPIC_VERT_BACK_PORCH_COUNT—Offset B83Ch” on page 428 00000000h

B840h 4 “MIPIC_VERT_FRONT_PORCH_COUNT—Offset B840h” on page 429 00000000h
B844h 4 “MIPIC_HIGH_LOW_SWITCH_COUNT—Offset B844h” on page 430 00000000h

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Table 159. Summary of Display Memory Mapped I/O Registers—GTTMMADR_LSB

Offset Size Register ID—Description Default Value

B848h 4 “MIPIC_DPI_CTRL_REG—Offset B848h” on page 431 00000000h

B84Ch 4 “MIPIC_DPI_DATA_REGISTER—Offset B84Ch” on page 432 00000000h

B850h 4 “MIPIC_INIT_COUNT_REGISTER—Offset B850h” on page 432 00000000h
B854h 4 “MIPIC_MAX_RETURN_PKT_SIZE_REGISTER—Offset B854h” on page 433 00000000h

B858h 4 “MIPIC_VIDEO_MODE_FORMAT_REGISTER—Offset B858h” on page 433 00000000h

B85Ch 4 “MIPIC_EOT_DISABLE_REGISTER—Offset B85Ch” on page 434 00000000h
B860h 4 “MIPIC_LP_BYTECLK_REGISTER—Offset B860h” on page 436 00000000h

B864h 4 “MIPIC_LP_GEN_DATA_REGISTER—Offset B864h” on page 436 00000000h

B868h 4 “MIPIC_HS_GEN_DATA_REGISTER—Offset B868h” on page 437 00000000h
B86Ch 4 “MIPIC_LP_GEN_CTRL_REGISTER—Offset B86Ch” on page 437 00000000h

B870h 4 “MIPIC_HS_GEN_CTRL_REGISTER—Offset B870h” on page 438 00000000h

B874h 4 “MIPIC_GEN_FIFO_STAT_REGISTER—Offset B874h” on page 439 1E060606h
B878h 4 “MIPIC_HS_LS_DBI_ENABLE_REG—Offset B878h” on page 440 00000000h

B87Ch 4 “MIPIC_RESERVED—Offset B87Ch” on page 441 00000000h

B880h 4 “MIPIC_DPHY_PARAM_REG—Offset B880h” on page 441 0B061A04h
B884h 4 “MIPIC_DBI_BW_CTRL_REG—Offset B884h” on page 442 00000000h

B888h 4 “MIPIC_CLK_LANE_SWITCHING_TIME_CNT—Offset B888h” on page 443 00000000h

B88Ch 4 “MIPIC_STOP_STATE_STALL—Offset B88Ch” on page 444 00000000h
B890h 4 “MIPIC_INTR_STAT_REG_1—Offset B890h” on page 444 00000000h

B894h 4 “MIPIC_INTR_EN_REG_1—Offset B894h” on page 445 00000000h

B904h 4 “MIPIC_CTRL—Offset B904h” on page 446 00000000h
B908h 4 “MIPIC_DATA_ADD—Offset B908h” on page 446 00000000h

B90Ch 4 “MIPIC_DATA_LEN—Offset B90Ch” on page 447 00000000h

B910h 4 “MIPIC_CMD_ADD—Offset B910h” on page 447 00000000h

B914h 4 “MIPIC_CMD_LEN—Offset B914h” on page 448 00000000h

B918h 4 “MIPIC_RD_DATA_RETURN0—Offset B918h” on page 449 00000000h
B91Ch 4 “MIPIC_RD_DATA_RETURN1—Offset B91Ch” on page 449 00000000h

B920h 4 “MIPIC_RD_DATA_RETURN2—Offset B920h” on page 450 00000000h

B924h 4 “MIPIC_RD_DATA_RETURN3—Offset B924h” on page 450 00000000h
B928h 4 “MIPIC_RD_DATA_RETURN4—Offset B928h” on page 451 00000000h

B92Ch 4 “MIPIC_RD_DATA_RETURN5—Offset B92Ch” on page 452 00000000h

B930h 4 “MIPIC_RD_DATA_RETURN6—Offset B930h” on page 452 00000000h
B934h 4 “MIPIC_RD_DATA_RETURN7—Offset B934h” on page 453 00000000h

B938h 4 “MIPIC_RD_DATA_VALID—Offset B938h” on page 453 00000000h

60000h 4 “HTOTAL_A—Offset 60000h” on page 454 00000000h
60004h 4 “HBLANK_A—Offset 60004h” on page 455 00000000h

60008h 4 “HSYNC_A—Offset 60008h” on page 456 00000000h

6000Ch 4 “VTOTAL_A—Offset 6000Ch” on page 457 00000000h
60010h 4 “VBLANK_A—Offset 60010h” on page 458 00000000h

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Table 159. Summary of Display Memory Mapped I/O Registers—GTTMMADR_LSB

Offset Size Register ID—Description Default Value

60014h 4 “VSYNC_A—Offset 60014h” on page 459 00000000h

6001Ch 4 “PIPESRCA—Offset 6001Ch” on page 460 00000000h

60020h 4 “BCLRPAT_A—Offset 60020h” on page 461 00000000h
60028h 4 “VSYNCSHIFT_A—Offset 60028h” on page 462 00000000h

60030h 4 “TRANSADATAM1—Offset 60030h” on page 463 7E000000h

60034h 4 “TRANSADATAN1—Offset 60034h” on page 463 00000000h
60038h 4 “TRANSADATAM2—Offset 60038h” on page 464 7E000000h

6003Ch 4 “TRANSADATAN2—Offset 6003Ch” on page 465 00000000h

60040h 4 “TRANSADPLINKM1—Offset 60040h” on page 465 00000000h
60044h 4 “TRANSADPLINKN1—Offset 60044h” on page 466 00000000h

60048h 4 “TRANSADPLINKM2—Offset 60048h” on page 467 00000000h

6004Ch 4 “TRANSADPLINKN2—Offset 6004Ch” on page 467 00000000h
60050h 4 “CRCCTRLREDA—Offset 60050h” on page 468 00000000h

60054h 4 “CRCCTRLGREENA—Offset 60054h” on page 469 00000000h

60058h 4 “CRCCTRLBLUEA—Offset 60058h” on page 469 00000000h
6005Ch 4 “CRCCTRLALPHAA—Offset 6005Ch” on page 470 00000000h

60060h 4 “CRCRESREDA—Offset 60060h” on page 471 00000000h

60064h 4 “CRCRESGREENA—Offset 60064h” on page 471 00000000h
60068h 4 “CRCRESBLUEA—Offset 60068h” on page 472 00000000h

6006Ch 4 “CRCRESALPHAA—Offset 6006Ch” on page 473 00000000h

60070h 4 “CRCCTRLRESIDUE2A—Offset 60070h” on page 473 00000000h
60080h 4 “CRCRESRESIDUE2A—Offset 60080h” on page 474 00000000h

60090h 4 “PSRCTLA—Offset 60090h” on page 475 00000000h

60094h 4 “PSRSTATA—Offset 60094h” on page 477 00000000h

60098h 4 “PSRCRC1A—Offset 60098h” on page 478 00000000h

6009Ch 4 “PSRCRC2A—Offset 6009Ch” on page 478 00000000h
600A0h 4 “VSCSDPA—Offset 600A0h” on page 479 00000000h

“PIPEAWIDEGAMUTCOLORCORRECTIONC01_C00COEFFICIENTS—Offset
600B0h 4 00000000h
600B0h” on page 480
“PIPEAWIDEGAMUTCOLORCORRECTIONC02COEFFICIENT—Offset 600B4h”
600B4h 4 00000000h
on page 481
“PIPEAWIDEGAMUTCOLORCORRECTIONC11_C10COEFFICIENTS—Offset
600B8h 4 00000000h
600B8h” on page 481

“PIPEAWIDEGAMUTCOLORCORRECTIONC12COEFFICIENT—Offset 600BCh”
600BCh 4 00000000h
on page 482
“PIPEAWIDEGAMUTCOLORCORRECTIONC21_C20COEFFICIENTS—Offset
600C0h 4 00000000h
600C0h” on page 483
“PIPEAWIDEGAMUTCOLORCORRECTIONC22COEFFICIENT—Offset 600C4h”
600C4h 4 00000000h
on page 483

60200h 4 “VIDEO_DIP_CTL_A—Offset 60200h” on page 484 20200900h

60208h 4 “VIDEO_DIP_DATA_A—Offset 60208h” on page 486 00000000h
60210h 4 “VIDEO_DIP_GDCP_PAYLOAD_A—Offset 60210h” on page 486 00000000h

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Table 159. Summary of Display Memory Mapped I/O Registers—GTTMMADR_LSB

Offset Size Register ID—Description Default Value

61000h 4 “HTOTAL_B—Offset 61000h” on page 487 00000000h

61004h 4 “HBLANK_B—Offset 61004h” on page 488 00000000h

61008h 4 “HSYNC_B—Offset 61008h” on page 489 00000000h
6100Ch 4 “VTOTAL_B—Offset 6100Ch” on page 490 00000000h

61010h 4 “VBLANK_B—Offset 61010h” on page 491 00000000h

61014h 4 “VSYNC_B—Offset 61014h” on page 492 00000000h
6101Ch 4 “PIPEBSRC—Offset 6101Ch” on page 492 00000000h

61020h 4 “BCLRPAT_B—Offset 61020h” on page 493 00000000h

61028h 4 “VSYNCSHIFT_B—Offset 61028h” on page 494 00000000h
61030h 4 “TRANSBDATAM1—Offset 61030h” on page 495 7E000000h

61034h 4 “TRANSBDATAN1—Offset 61034h” on page 496 00000000h

61038h 4 “TRANSBDATAM2—Offset 61038h” on page 497 7E000000h
6103Ch 4 “TRANSBDATAN2—Offset 6103Ch” on page 497 00000000h

61040h 4 “TRANSBDPLINKM1—Offset 61040h” on page 498 00000000h

61044h 4 “TRANSBDPLINKN1—Offset 61044h” on page 498 00000000h
61048h 4 “TRANSBDPLINKM2—Offset 61048h” on page 499 00000000h

6104Ch 4 “TRANSBDPLINKN2—Offset 6104Ch” on page 500 00000000h

14.10.1 CRX (CRX_MDA)—Offset 3B4h

CRT Controller Index Register

Access Method
Type: Memory Mapped I/O Register
(Size: 8 bits) CRX_MDA: [GTTMMADR_LSB + 2BF20h] + 3B4h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00h
7 4 0

0 0 0 0 0 0 0 0
RESERVED

CRT_CONTROLLER_INDEX

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Bit Default &

Description
Range Access

0b
7 RESERVED: Read as 0.
RW
CRT_CONTROLLER_INDEX: These 7 bits are used to select any one of the CRT
0b controller registers to be accessed via the data port at I/O location 3B5h or 3D5h,
6:0
RW depending upon whether the graphics system is configured for MDA or CGA emulation.
The data port memory address offsets are 3B5h/3D5h.

14.10.2 CR (CR_MDA)—Offset 3B5h

CR index registers

Access Method
Type: Memory Mapped I/O Register CR_MDA: [GTTMMADR_LSB + 2BF20h] + 3B5h
(Size: 8 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00h
7 4 0

0 0 0 0 0 0 0 0
CR_REGISTER_DESCRIPTIONS

Bit Default &

Description
Range Access

0b
7:0 CR_REGISTER_DESCRIPTIONS: CR indexed register descriptions
RW

14.10.3 ARX—Offset 3C0h

Attribute Controller Index Register. Includes the 22 registers that share this offset (with
different indexes). -enum ARX_e

Access Method
Type: Memory Mapped I/O Register
(Size: 8 bits) ARX: [GTTMMADR_LSB + 2BF20h] + 3C0h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00h

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7 4 0

0 0 0 0 0 0 0 0

ARX_REGISTER_DESCRIPTIONS
Bit Default &
Description
Range Access

0b
7:0 ARX_REGISTER_DESCRIPTIONS: ARX indexed register descriptions
RW

14.10.4 AR—Offset 3C1h

AR index registers. Includes the 21 registers that share this offset (with differnet
indexes.) -enum AR_e- in this document will lead to register definitions

Access Method
Type: Memory Mapped I/O Register AR: [GTTMMADR_LSB + 2BF20h] + 3C1h
(Size: 8 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00h
7 4 0

0 0 0 0 0 0 0 0
AR_REGISTER_DESCRIPTIONS

Bit Default &

Description
Range Access

0b
7:0 AR_REGISTER_DESCRIPTIONS: AR indexed register descriptions
RW

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14.10.5 SRX—Offset 3C4h

Sequencer Index

Access Method
Type: Memory Mapped I/O Register
(Size: 8 bits) SRX: [GTTMMADR_LSB + 2BF20h] + 3C4h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00h
7 4 0

0 0 0
RESERVED 0 0 0 0 0

SEQUENCER_INDEX
Bit Default &
Description
Range Access

0b
7:3 RESERVED: Read as 0s.
RW

SEQUENCER_INDEX: This field contains a 3-bit Sequencer Index value used to access
sequencer data re gisters at indices 0 through 7. Notes: SR02 is referred to in the VGA
0b standard as the Map Mask Register. However, the word map is used with multiple
2:0
RW meanings in the VGA standard and was, therefore, deemed too confusing; hence, the
reason for calling it the Plane Mask Register. SR07 is a standard VGA register that was
not documented by IBM. It is not a graphics controller extension.

14.10.6 SR—Offset 3C5h

SR index registers

Access Method
Type: Memory Mapped I/O Register SR: [GTTMMADR_LSB + 2BF20h] + 3C5h
(Size: 8 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00h

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7 4 0

0 0 0 0 0 0 0 0

SR_REGISTER_DESCRIPTIONS
Bit Default &
Description
Range Access

0b
7:0 SR_REGISTER_DESCRIPTIONS: SR indexed register descriptions
RW

14.10.7 DACMASK—Offset 3C6h

Pixel Data Mask Register

Access Method
Type: Memory Mapped I/O Register DACMASK: [GTTMMADR_LSB + 2BF20h] + 3C6h
(Size: 8 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00h
7 4 0

0 0 0 0 0 0 0 0
PIXEL_DATA_MASK

Bit Default &

Description
Range Access

PIXEL_DATA_MASK: In indexed-color mode, the 8 bits of this register are logically

ANDed with the 8 bits of pixel data received from the frame buffer for each pixel. The
0b result of this ANDing process becomes the actual index used to select color data
7:0 positions within the palette. This has the effect of limiting the choice of color data
RW positions that may be specified by the incoming 8-bit data. 0 = Corresponding bit in the
resulting 8-bit index being forced to 0. 1 = Allows the corresponding bit in the resulting
index to reflect the actual value of the corresponding bit in the incoming 8-bit pixel data.

14.10.8 DACWX—Offset 3C8h

Palette Write Index Register

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Access Method
Type: Memory Mapped I/O Register
DACWX: [GTTMMADR_LSB + 2BF20h] + 3C8h
(Size: 8 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00h
7 4 0

0 0 0 0 0 0 0 0

Bit Default & PALETTE_WRITE_INDEX

Description
Range Access

PALETTE_WRITE_INDEX: The 8-bit index value programmed into this register

chooses which of 256 standard color data positions within the palette are to be made
0b accessible for being written via the Palette Data Register (DACDATA). The index value
7:0
WO held in this register is automatically incremented when all three bytes of the color data
position selected by the current index have been written. This register allows access to
the palette even when running non-VGA display modes.

14.10.9 DACDATA—Offset 3C9h

Palette Data Register

Access Method
Type: Memory Mapped I/O Register
DACDATA: [GTTMMADR_LSB + 2BF20h] + 3C9h
(Size: 8 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00h
7 4 0

0 0 0 0 0 0 0 0
PALETTE_DATA

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Bit Default &

Description
Range Access

PALETTE_DATA: This byte-wide data port provides read or write access to the three
bytes of data of each color data position selected using the Palette Read Index Register
(DACRX) or the Palette Write Index Register (DACWX). The three bytes in each color
data position are read or written in three successive read or write operations. The first
byte read or written specifies the intensity of the red component of the color specified in
the selected color data position. The second byte is for the green component, and the
third byte is for the blue component. When writing data to a color data position, all
three bytes must be written before the hardware will actually update the three bytes of
0b the selected color data position. When reading or writing to a color data position, ensure
7:0 that neither the Palette Read Index Register (DACRX) or the Palette Write Index Register
RW (DACWX) are written to before all three bytes are read or written. A write to either of
these two registers causes the circuitry that automatically cycles through providing
access to the bytes for red, green and blue components to be reset such that the byte
for the red component is the one that will be accessed by the next read or write
operation via this register. This register allows access to the palette even when running
non-VGA display modes. Writes to the palette can cause sparkle if not done during
inactive video periods. This sparkle is caused by an attempt to write and read the same
address on the same cycle. Anti-sparkle circuits will substitute the previous pixel value
for the read output.

14.10.10 FCR (FCR_Read)—Offset 3CAh

Feature Control

Access Method
Type: Memory Mapped I/O Register FCR_Read: [GTTMMADR_LSB + 2BF20h] + 3CAh
(Size: 8 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00h
7 4 0

0 0 0 0 0 0 0 0
RESERVED_1
RESERVED

VSYNC_CONTROL

Bit Default &

Description
Range Access

0b
7:4 RESERVED: Read as 0.
RW
VSYNC_CONTROL: This bit is provided for compatibility only and has no other
function. Reads and writes to this bit have no effect other than to change the value of
0b this bit. The previous definition of this bit selected the output on the VSYNC pin. 0 =
3
RW Was used to set VSYNC out put on the VSYNC pin (default). 1 = Was used to set the log
i cal 'OR' of VSYNC and Display Ena ble output on the VSYNC pin. This capability was not
typically very useful..
0b
2:0 RESERVED_1: Read as 0.
RW

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14.10.11 MSR (MSR_READ)—Offset 3CCh

Miscellaneous Output

Access Method
Type: Memory Mapped I/O Register
(Size: 8 bits) MSR_READ: [GTTMMADR_LSB + 2BF20h] + 3CCh

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00h
7 4 0

0 0 0 0 0 0 0 0

A0000_BFFFFH_MEMORY_ACCESS_ENABLE
PAGE_SELECT

I_O_ADDRESS_SELECT
CLOCK_SELECT
RESERVED
CRT_HSYNC_POLA_RITY
CRT_VSYNC_POLARITY

Bit Default &

Description
Range Access

CRT_VSYNC_POLARITY: This is a legacy function that is used in native VGA modes.

0b For most cases, sync polarity will be controlled by the port control bits. The VGA settings
7 can be optionally selected for compatibility with the original VGA when used in the VGA
RW native mode. Sync polarity was used in VGA to signal the monitor how many lines of
active display are being generated. 0 = Positive Polarity (default). 1 = Negative Polarity.
CRT_HSYNC_POLA_RITY: This is a legacy function that is used in native VGA modes.
0b For most cases, sync polarity will be controlled by the port control bits. The VGA settings
6
RW can be optionally selected for compatibility with the original VGA when used in the VGA
native mode. 0 = Positive Polarity (default). 1 = Negative Polarity
PAGE_SELECT: In Odd/Even Memory Map Mode 1 (GR6), this bit selects the upper or
0b lower 64 KB page in dis play mem ory for CPU access: 0 = Upper page (default) 1 =
5 Lower page. Selects between two 64KB pages of frame buffer memory during standard
RW VGA odd/even modes (modes 0h through 5h). Bit 1 of register GR06 can also program
this bit in other modes. Note that this bit is would normally set to 1 by the software.
0b
4 RESERVED: Read as 0.
RW
CLOCK_SELECT: These bits can select the dot clock source for the CRT interface. The
bits should be used to select the dot clock in standard native VGA modes only. When in
the centering or upper left corner modes, these bits should be set to have no effect on
0b the clock rate. The actual frequencies that these bits select, if they have any affect at
3:2 all, is programmable through the DPLL registers that default to the standard values used
RW for VGA. 00 = CLK0, 25.175 MHz (for standard VGA modes with 640 pixel (8-dot)
horizontal resolution) (default) 01 = CLK1, 28.322 MHz. (for standard VGA modes with
720 pixel (9-dot) horizontal resolution) 10 = Was used to select an external clock (now
unused) 11 = Reserved

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Bit Default &

Description
Range Access

A0000_BFFFFH_MEMORY_ACCESS_ENABLE: VGA Compatibility bit enables access

to local video memory (frame buffer) at A0000(BFFFFh. When disabled, accesses to VGA
memory are blocked in this region. This bit is independent of and does not block CPU
0b access to the video linear frame buffer at other addresses. Note that it is typical for AGP
1 chipsets to shadow this register to allow proper steering of memory accesses to the
RW proper bus. 0 = Prevent CPU access to memory/registers/ROM through the A0000-
BFFFF VGA memory aperture (default). 1 = Allow CPU access to memory/registers/ROM
through the A0000-BFFFF VGA memory aperture. This memory must be mapped as UC
by the CPU; see VGA Host Access Memory Munging in Display and Overlay Functions.
I_O_ADDRESS_SELECT: This bit selects 3Bxh or 3Dxh as the I/O address for the CRT
Controller re gisters, the Feature Control Register (FCR), and Input Status Register 1
0b (ST01). Presently ignored (whole range is claimed), but will ignore 3Bx for color
0 configuration or 3Dx for monochrome. Note that it is typical in AGP chipsets to shadow
RW this bit and properly steer I/O cycles to the proper bus for operation where a MDA exists
on another bus such as ISA. 0 = Select 3Bxh I/O address (MDA emulation) (default). 1
= Select 3Dxh I/O address (CGA emulation).

14.10.12 GRX—Offset 3CEh

GRX Graphics Controller Index Register

Access Method
Type: Memory Mapped I/O Register GRX: [GTTMMADR_LSB + 2BF20h] + 3CEh
(Size: 8 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00h
7 4 0

0 0 0 0 0 0 0 0
SEQUENCER_REGISTER_INDEX
RESERVED

Bit Default &

Description
Range Access

0b
7:5 RESERVED: Read as 0.
RW

0b SEQUENCER_REGISTER_INDEX: This field selects any one of the graphics controller

4:0 registers (GR00-GR11]) to be accessed via the data port at I/O (or memory offset)
RW location 3CFh.

14.10.13 GR—Offset 3CFh

GR index registers

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Access Method
Type: Memory Mapped I/O Register
GR: [GTTMMADR_LSB + 2BF20h] + 3CFh
(Size: 8 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00h
7 4 0

0 0 0 0 0 0 0 0

GR_REGISTER_DESCRIPTIONS

Bit Default &

Description
Range Access

0b
7:0 GR_REGISTER_DESCRIPTIONS: GR indexed register descriptions
RW

14.10.14 CRX (CRX_CGA)—Offset 3D4h

CRT Controller Index Register

Access Method
Type: Memory Mapped I/O Register
CRX_CGA: [GTTMMADR_LSB + 2BF20h] + 3D4h
(Size: 8 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00h
7 4 0

0 0 0 0 0 0 0 0
RESERVED

CRT_CONTROLLER_INDEX

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Bit Default &

Description
Range Access

0b
7 RESERVED: Read as 0.
RW
CRT_CONTROLLER_INDEX: These 7 bits are used to select any one of the CRT
0b controller registers to be accessed via the data port at I/O location 3B5h or 3D5h,
6:0
RW depending upon whether the graphics system is configured for MDA or CGA emulation.
The data port memory address offsets are 3B5h/3D5h.

14.10.15 CR (CR_CGA)—Offset 3D5h

CR index registers

Access Method
Type: Memory Mapped I/O Register CR_CGA: [GTTMMADR_LSB + 2BF20h] + 3D5h
(Size: 8 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00h
7 4 0

0 0 0 0 0 0 0 0
CR_REGISTER_DESCRIPTIONS

Bit Default &

Description
Range Access

0b
7:0 CR_REGISTER_DESCRIPTIONS: CR indexed register descriptions
RW

14.10.16 GPIOCTL_0—Offset 5010h

GPIO Control Registers GPIO I2C register (gmbus_register.v reg_gpio0, reg_gpio1,
reg_gpio2. reg_gpio3, reg_gpio4)

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) GPIOCTL_0: [GTTMMADR_LSB + 2BF20h] + 5010h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000808h

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 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0

GPIO_DATA_MASK_WO
RESERVED

GPIO_DATA_DIRECTION_MASK_WO

GPIO_CLOCK_DATA_IN_RO

GPIO_CLOCK_DATA_MASK_WO

GPIO_CLOCK_DIRECTION_MASK_WO
GPIO_DATA_IN_RO
GPIO_DATA_VALUE_R_W

GPIO_DATA_DIRECTION_VALUE_R_W

GPIO_CLOCK_DATA_VALUE_R_W
RESERVED_1

GPIO_CLOCK_DIRECTION_VALUE_R_W
Bit Default &
Description
Range Access

0b
31:13 RESERVED: Reserved.
RW

0b GPIO_DATA_IN_RO: This is the value that is sampled on the GPIO_Data pin as an

12 input. This input is synchronized to the Core Clock domain. Because the default setting
RO is this buffer is an input, this bit is undefined at reset. AccessType: Read Only
GPIO_DATA_VALUE_R_W: This is the value that should be place on the GPIO Data
pin as an output. This value is only written into the register if GPIO DATA MASK is also
1b asserted. The value will appear on the pin if this data value is actually written to this
11 register and the GPIO Data DIRECTION VALUE contains a value that will configure the
RW pin as an output. Default = 1. The GPIO default clock data value is programmed to 1 in
hardware. The hardware drives a default of 1 since the I2C interface defaults to a 1 .
(this mimics the I2C external pull-ups on the bus)

GPIO_DATA_MASK_WO: This is a mask bit to determine whether the GPIO DATA

0b VALUE bit should be written into the register. This value is not stored and when read
10
WO returns 0. 0 = Do NOT write GPIO Data Value bit (default). 1 = Write GPIO Data Value
bit. AccessType: Write Only
GPIO_DATA_DIRECTION_VALUE_R_W: This is the value that should be used to
0b define the output enable of the GPIO Data pin. This value is only written into the register
9 if GPIO Data DIRECTION MASK is also asserted. The value that will appear on the pin is
RW defined by what is in the register for the GPIO DATA VALUE bit. 0 = Pin is configured as
an input (default) 1 = Pin is configured as an output.
GPIO_DATA_DIRECTION_MASK_WO: This is a mask bit to determine whether the
0b GPIO DIRECTION VALUE bit should be written into the register. This value is not stored
8
WO and when read always returns 0. 0 = Do NOT write GPIO Data Direction Value bit
(default). 1 = Write GPIO Data Direction Value bit. AccessType: Write Only
0b
7:5 RESERVED_1: must be written with zeros.
RW

0b GPIO_CLOCK_DATA_IN_RO: This is the value that is sampled on the GPIO Clock pin
4 as an input. This input is synchronized to the Core Clock domain. Because the default
RO setting is this buffer is an input, this bit is undefined at reset. AccessType: Read Only
GPIO_CLOCK_DATA_VALUE_R_W: This is the value that should be place on the
GPIO Clk pin as an output. This value is only written into the register if GPIO Clock DATA
1b MASK is also asserted. The value will appear on the pin if this data value is actually
3 written to this register and the GPIO Clock DIRECTION VALUE contains a value that will
RW configure the pin as an output. Default = 1. The GPIO default clock data value is
programmed to 1 in hardware. The hardware drives a default of 1 since the I2C
interface defaults to a 1 . (this mimics the I2C external pull-ups on the bus)

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Bit Default &

Description
Range Access

GPIO_CLOCK_DATA_MASK_WO: This is a mask bit to determine whether the GPIO

0b Clock DATA VALUE bit should be written into the register. This value is not stored and
2
WO when read always returns 0. 0 = Do NOT write GPIO Clock Data Value bit (default). 1 =
Write GPIO Clock Data Value bit. AccessType: Write Only
GPIO_CLOCK_DIRECTION_VALUE_R_W: This is the value that should be used to
define the output enable of the GPIO Clock pin. This value is only written into the
0b register if GPIO Clock DIRECTION MASK is also asserted. The value that will appear on
1
RW the pin is defined by what is in the register for the GPIO Clock DATA VALUE bit. 0 = Pin
is configured as an input and the output driver is set to tri-state (default) 1 = Pin is
configured as an output.
GPIO_CLOCK_DIRECTION_MASK_WO: This is a mask bit to determine whether the
0b GPIO Clock DIRECTION VALUE bit should be written into the register. This value is not
0 stored and when read returns 0. 0 = Do NOT update the GPIO Clock Direction Value bit
WO on a write (default). 1 = Update the GPIO Clock Direction Value bit. on a write operation
to this register. AccessType: Write Only

14.10.17 GPIOCTL_1—Offset 5014h

GPIO Control Registers GPIO I2C register (gmbus_register.v reg_gpio0, reg_gpio1,
reg_gpio2. reg_gpio3, reg_gpio4)

Access Method
Type: Memory Mapped I/O Register
GPIOCTL_1: [GTTMMADR_LSB + 2BF20h] + 5014h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000808h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0

GPIO_CLOCK_DATA_MASK_WO
GPIO_DATA_DIRECTION_MASK_WO
GPIO_DATA_IN_RO

GPIO_DATA_MASK_WO

GPIO_CLOCK_DATA_IN_RO
GPIO_DATA_VALUE_R_W

GPIO_DATA_DIRECTION_VALUE_R_W

GPIO_CLOCK_DATA_VALUE_R_W

GPIO_CLOCK_DIRECTION_MASK_WO
RESERVED

RESERVED_1

GPIO_CLOCK_DIRECTION_VALUE_R_W

Bit Default &

Description
Range Access

0b
31:13 RESERVED: Reserved.
RW

0b GPIO_DATA_IN_RO: This is the value that is sampled on the GPIO_Data pin as an

12 input. This input is synchronized to the Core Clock domain. Because the default setting
RO is this buffer is an input, this bit is undefined at reset. AccessType: Read Only

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Bit Default &

Description
Range Access

GPIO_DATA_VALUE_R_W: This is the value that should be place on the GPIO Data
pin as an output. This value is only written into the register if GPIO DATA MASK is also
1b asserted. The value will appear on the pin if this data value is actually written to this
11 register and the GPIO Data DIRECTION VALUE contains a value that will configure the
RW pin as an output. Default = 1. The GPIO default clock data value is programmed to 1 in
hardware. The hardware drives a default of 1 since the I2C interface defaults to a 1 .
(this mimics the I2C external pull-ups on the bus)
GPIO_DATA_MASK_WO: This is a mask bit to determine whether the GPIO DATA
0b VALUE bit should be written into the register. This value is not stored and when read
10
WO returns 0. 0 = Do NOT write GPIO Data Value bit (default). 1 = Write GPIO Data Value
bit. AccessType: Write Only

GPIO_DATA_DIRECTION_VALUE_R_W: This is the value that should be used to

0b define the output enable of the GPIO Data pin. This value is only written into the register
9 if GPIO Data DIRECTION MASK is also asserted. The value that will appear on the pin is
RW defined by what is in the register for the GPIO DATA VALUE bit. 0 = Pin is configured as
an input (default) 1 = Pin is configured as an output.
GPIO_DATA_DIRECTION_MASK_WO: This is a mask bit to determine whether the
0b GPIO DIRECTION VALUE bit should be written into the register. This value is not stored
8
WO and when read always returns 0. 0 = Do NOT write GPIO Data Direction Value bit
(default). 1 = Write GPIO Data Direction Value bit. AccessType: Write Only

0b
7:5 RESERVED_1: must be written with zeros.
RW

0b GPIO_CLOCK_DATA_IN_RO: This is the value that is sampled on the GPIO Clock pin
4 as an input. This input is synchronized to the Core Clock domain. Because the default
RO setting is this buffer is an input, this bit is undefined at reset. AccessType: Read Only

GPIO_CLOCK_DATA_VALUE_R_W: This is the value that should be place on the

GPIO Clk pin as an output. This value is only written into the register if GPIO Clock DATA
1b MASK is also asserted. The value will appear on the pin if this data value is actually
3 written to this register and the GPIO Clock DIRECTION VALUE contains a value that will
RW configure the pin as an output. Default = 1. The GPIO default clock data value is
programmed to 1 in hardware. The hardware drives a default of 1 since the I2C
interface defaults to a 1 . (this mimics the I2C external pull-ups on the bus)
GPIO_CLOCK_DATA_MASK_WO: This is a mask bit to determine whether the GPIO
0b Clock DATA VALUE bit should be written into the register. This value is not stored and
2
WO when read always returns 0. 0 = Do NOT write GPIO Clock Data Value bit (default). 1 =
Write GPIO Clock Data Value bit. AccessType: Write Only
GPIO_CLOCK_DIRECTION_VALUE_R_W: This is the value that should be used to
define the output enable of the GPIO Clock pin. This value is only written into the
0b register if GPIO Clock DIRECTION MASK is also asserted. The value that will appear on
1
RW the pin is defined by what is in the register for the GPIO Clock DATA VALUE bit. 0 = Pin
is configured as an input and the output driver is set to tri-state (default) 1 = Pin is
configured as an output.

GPIO_CLOCK_DIRECTION_MASK_WO: This is a mask bit to determine whether the

0b GPIO Clock DIRECTION VALUE bit should be written into the register. This value is not
0 stored and when read returns 0. 0 = Do NOT update the GPIO Clock Direction Value bit
WO on a write (default). 1 = Update the GPIO Clock Direction Value bit. on a write operation
to this register. AccessType: Write Only

14.10.18 GPIOCTL_2—Offset 5018h

GPIO Control Registers GPIO I2C register (gmbus_register.v reg_gpio0, reg_gpio1,
reg_gpio2. reg_gpio3, reg_gpio4)

Access Method

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Type: Memory Mapped I/O Register

GPIOCTL_2: [GTTMMADR_LSB + 2BF20h] + 5018h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000808h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0

GPIO_DATA_MASK_WO
RESERVED

GPIO_DATA_DIRECTION_MASK_WO

GPIO_CLOCK_DATA_IN_RO

GPIO_CLOCK_DATA_MASK_WO

GPIO_CLOCK_DIRECTION_MASK_WO
GPIO_DATA_IN_RO
GPIO_DATA_VALUE_R_W

GPIO_DATA_DIRECTION_VALUE_R_W

GPIO_CLOCK_DATA_VALUE_R_W
RESERVED_1

GPIO_CLOCK_DIRECTION_VALUE_R_W
Bit Default &
Description
Range Access

0b
31:13 RESERVED: Reserved.
RW

0b GPIO_DATA_IN_RO: This is the value that is sampled on the GPIO_Data pin as an

12 input. This input is synchronized to the Core Clock domain. Because the default setting
RO is this buffer is an input, this bit is undefined at reset. AccessType: Read Only
GPIO_DATA_VALUE_R_W: This is the value that should be place on the GPIO Data
pin as an output. This value is only written into the register if GPIO DATA MASK is also
1b asserted. The value will appear on the pin if this data value is actually written to this
11 register and the GPIO Data DIRECTION VALUE contains a value that will configure the
RW pin as an output. Default = 1. The GPIO default clock data value is programmed to 1 in
hardware. The hardware drives a default of 1 since the I2C interface defaults to a 1 .
(this mimics the I2C external pull-ups on the bus)
GPIO_DATA_MASK_WO: This is a mask bit to determine whether the GPIO DATA
0b VALUE bit should be written into the register. This value is not stored and when read
10
WO returns 0. 0 = Do NOT write GPIO Data Value bit (default). 1 = Write GPIO Data Value
bit. AccessType: Write Only
GPIO_DATA_DIRECTION_VALUE_R_W: This is the value that should be used to
0b define the output enable of the GPIO Data pin. This value is only written into the register
9 if GPIO Data DIRECTION MASK is also asserted. The value that will appear on the pin is
RW defined by what is in the register for the GPIO DATA VALUE bit. 0 = Pin is configured as
an input (default) 1 = Pin is configured as an output.
GPIO_DATA_DIRECTION_MASK_WO: This is a mask bit to determine whether the
0b GPIO DIRECTION VALUE bit should be written into the register. This value is not stored
8
WO and when read always returns 0. 0 = Do NOT write GPIO Data Direction Value bit
(default). 1 = Write GPIO Data Direction Value bit. AccessType: Write Only
0b
7:5 RESERVED_1: must be written with zeros.
RW

0b GPIO_CLOCK_DATA_IN_RO: This is the value that is sampled on the GPIO Clock pin
4 as an input. This input is synchronized to the Core Clock domain. Because the default
RO setting is this buffer is an input, this bit is undefined at reset. AccessType: Read Only

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Bit Default &

Description
Range Access

GPIO_CLOCK_DATA_VALUE_R_W: This is the value that should be place on the

GPIO Clk pin as an output. This value is only written into the register if GPIO Clock DATA
1b MASK is also asserted. The value will appear on the pin if this data value is actually
3 written to this register and the GPIO Clock DIRECTION VALUE contains a value that will
RW configure the pin as an output. Default = 1. The GPIO default clock data value is
programmed to 1 in hardware. The hardware drives a default of 1 since the I2C
interface defaults to a 1 . (this mimics the I2C external pull-ups on the bus)
GPIO_CLOCK_DATA_MASK_WO: This is a mask bit to determine whether the GPIO
0b Clock DATA VALUE bit should be written into the register. This value is not stored and
2
WO when read always returns 0. 0 = Do NOT write GPIO Clock Data Value bit (default). 1 =
Write GPIO Clock Data Value bit. AccessType: Write Only

GPIO_CLOCK_DIRECTION_VALUE_R_W: This is the value that should be used to

define the output enable of the GPIO Clock pin. This value is only written into the
0b register if GPIO Clock DIRECTION MASK is also asserted. The value that will appear on
1
RW the pin is defined by what is in the register for the GPIO Clock DATA VALUE bit. 0 = Pin
is configured as an input and the output driver is set to tri-state (default) 1 = Pin is
configured as an output.

GPIO_CLOCK_DIRECTION_MASK_WO: This is a mask bit to determine whether the

0b GPIO Clock DIRECTION VALUE bit should be written into the register. This value is not
0 stored and when read returns 0. 0 = Do NOT update the GPIO Clock Direction Value bit
WO on a write (default). 1 = Update the GPIO Clock Direction Value bit. on a write operation
to this register. AccessType: Write Only

14.10.19 GPIOCTL_3—Offset 501Ch

GPIO Control Registers GPIO I2C register (gmbus_register.v reg_gpio0, reg_gpio1,
reg_gpio2. reg_gpio3, reg_gpio4)

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) GPIOCTL_3: [GTTMMADR_LSB + 2BF20h] + 501Ch

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000808h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0
GPIO_DATA_VALUE_R_W

GPIO_CLOCK_DATA_VALUE_R_W
GPIO_DATA_MASK_WO
GPIO_DATA_DIRECTION_VALUE_R_W
GPIO_DATA_DIRECTION_MASK_WO
GPIO_DATA_IN_RO

GPIO_CLOCK_DATA_MASK_WO
GPIO_CLOCK_DIRECTION_VALUE_R_W
GPIO_CLOCK_DIRECTION_MASK_WO
RESERVED

RESERVED_1

GPIO_CLOCK_DATA_IN_RO

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Bit Default &

Description
Range Access

0b
31:13 RESERVED: Reserved.
RW

0b GPIO_DATA_IN_RO: This is the value that is sampled on the GPIO_Data pin as an

12 input. This input is synchronized to the Core Clock domain. Because the default setting
RO is this buffer is an input, this bit is undefined at reset. AccessType: Read Only
GPIO_DATA_VALUE_R_W: This is the value that should be place on the GPIO Data
pin as an output. This value is only written into the register if GPIO DATA MASK is also
1b asserted. The value will appear on the pin if this data value is actually written to this
11 register and the GPIO Data DIRECTION VALUE contains a value that will configure the
RW pin as an output. Default = 1. The GPIO default clock data value is programmed to 1 in
hardware. The hardware drives a default of 1 since the I2C interface defaults to a 1 .
(this mimics the I2C external pull-ups on the bus)

GPIO_DATA_MASK_WO: This is a mask bit to determine whether the GPIO DATA

0b VALUE bit should be written into the register. This value is not stored and when read
10
WO returns 0. 0 = Do NOT write GPIO Data Value bit (default). 1 = Write GPIO Data Value
bit. AccessType: Write Only
GPIO_DATA_DIRECTION_VALUE_R_W: This is the value that should be used to
0b define the output enable of the GPIO Data pin. This value is only written into the register
9 if GPIO Data DIRECTION MASK is also asserted. The value that will appear on the pin is
RW defined by what is in the register for the GPIO DATA VALUE bit. 0 = Pin is configured as
an input (default) 1 = Pin is configured as an output.

GPIO_DATA_DIRECTION_MASK_WO: This is a mask bit to determine whether the

0b GPIO DIRECTION VALUE bit should be written into the register. This value is not stored
8
WO and when read always returns 0. 0 = Do NOT write GPIO Data Direction Value bit
(default). 1 = Write GPIO Data Direction Value bit. AccessType: Write Only
0b
7:5 RESERVED_1: must be written with zeros.
RW

0b GPIO_CLOCK_DATA_IN_RO: This is the value that is sampled on the GPIO Clock pin
4 as an input. This input is synchronized to the Core Clock domain. Because the default
RO setting is this buffer is an input, this bit is undefined at reset. AccessType: Read Only
GPIO_CLOCK_DATA_VALUE_R_W: This is the value that should be place on the
GPIO Clk pin as an output. This value is only written into the register if GPIO Clock DATA
1b MASK is also asserted. The value will appear on the pin if this data value is actually
3 written to this register and the GPIO Clock DIRECTION VALUE contains a value that will
RW configure the pin as an output. Default = 1. The GPIO default clock data value is
programmed to 1 in hardware. The hardware drives a default of 1 since the I2C
interface defaults to a 1 . (this mimics the I2C external pull-ups on the bus)

GPIO_CLOCK_DATA_MASK_WO: This is a mask bit to determine whether the GPIO

0b Clock DATA VALUE bit should be written into the register. This value is not stored and
2
WO when read always returns 0. 0 = Do NOT write GPIO Clock Data Value bit (default). 1 =
Write GPIO Clock Data Value bit. AccessType: Write Only
GPIO_CLOCK_DIRECTION_VALUE_R_W: This is the value that should be used to
define the output enable of the GPIO Clock pin. This value is only written into the
0b register if GPIO Clock DIRECTION MASK is also asserted. The value that will appear on
1
RW the pin is defined by what is in the register for the GPIO Clock DATA VALUE bit. 0 = Pin
is configured as an input and the output driver is set to tri-state (default) 1 = Pin is
configured as an output.
GPIO_CLOCK_DIRECTION_MASK_WO: This is a mask bit to determine whether the
0b GPIO Clock DIRECTION VALUE bit should be written into the register. This value is not
0 stored and when read returns 0. 0 = Do NOT update the GPIO Clock Direction Value bit
WO on a write (default). 1 = Update the GPIO Clock Direction Value bit. on a write operation
to this register. AccessType: Write Only

14.10.20 GPIOCTL_4—Offset 5020h

GPIO Control Registers GPIO I2C register (gmbus_register.v reg_gpio0, reg_gpio1,
reg_gpio2. reg_gpio3, reg_gpio4)

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Access Method
Type: Memory Mapped I/O Register
GPIOCTL_4: [GTTMMADR_LSB + 2BF20h] + 5020h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000808h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0

GPIO_CLOCK_DATA_VALUE_R_W
GPIO_DATA_VALUE_R_W

GPIO_DATA_DIRECTION_MASK_WO

GPIO_CLOCK_DATA_MASK_WO
GPIO_DATA_IN_RO

GPIO_DATA_MASK_WO
RESERVED

GPIO_DATA_DIRECTION_VALUE_R_W

RESERVED_1

GPIO_CLOCK_DATA_IN_RO

GPIO_CLOCK_DIRECTION_VALUE_R_W
GPIO_CLOCK_DIRECTION_MASK_WO
Bit Default &
Description
Range Access

0b
31:13 RESERVED: Reserved.
RW

0b GPIO_DATA_IN_RO: This is the value that is sampled on the GPIO_Data pin as an

12 input. This input is synchronized to the Core Clock domain. Because the default setting
RO is this buffer is an input, this bit is undefined at reset. AccessType: Read Only
GPIO_DATA_VALUE_R_W: This is the value that should be place on the GPIO Data
pin as an output. This value is only written into the register if GPIO DATA MASK is also
1b asserted. The value will appear on the pin if this data value is actually written to this
11 register and the GPIO Data DIRECTION VALUE contains a value that will configure the
RW pin as an output. Default = 1. The GPIO default clock data value is programmed to 1 in
hardware. The hardware drives a default of 1 since the I2C interface defaults to a 1 .
(this mimics the I2C external pull-ups on the bus)

GPIO_DATA_MASK_WO: This is a mask bit to determine whether the GPIO DATA

0b VALUE bit should be written into the register. This value is not stored and when read
10
WO returns 0. 0 = Do NOT write GPIO Data Value bit (default). 1 = Write GPIO Data Value
bit. AccessType: Write Only
GPIO_DATA_DIRECTION_VALUE_R_W: This is the value that should be used to
0b define the output enable of the GPIO Data pin. This value is only written into the register
9 if GPIO Data DIRECTION MASK is also asserted. The value that will appear on the pin is
RW defined by what is in the register for the GPIO DATA VALUE bit. 0 = Pin is configured as
an input (default) 1 = Pin is configured as an output.

GPIO_DATA_DIRECTION_MASK_WO: This is a mask bit to determine whether the

0b GPIO DIRECTION VALUE bit should be written into the register. This value is not stored
8
WO and when read always returns 0. 0 = Do NOT write GPIO Data Direction Value bit
(default). 1 = Write GPIO Data Direction Value bit. AccessType: Write Only
0b
7:5 RESERVED_1: must be written with zeros.
RW

0b GPIO_CLOCK_DATA_IN_RO: This is the value that is sampled on the GPIO Clock pin
4 as an input. This input is synchronized to the Core Clock domain. Because the default
RO setting is this buffer is an input, this bit is undefined at reset. AccessType: Read Only

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Bit Default &

Description
Range Access

GPIO_CLOCK_DATA_VALUE_R_W: This is the value that should be place on the

GPIO Clk pin as an output. This value is only written into the register if GPIO Clock DATA
1b MASK is also asserted. The value will appear on the pin if this data value is actually
3 written to this register and the GPIO Clock DIRECTION VALUE contains a value that will
RW configure the pin as an output. Default = 1. The GPIO default clock data value is
programmed to 1 in hardware. The hardware drives a default of 1 since the I2C
interface defaults to a 1 . (this mimics the I2C external pull-ups on the bus)
GPIO_CLOCK_DATA_MASK_WO: This is a mask bit to determine whether the GPIO
0b Clock DATA VALUE bit should be written into the register. This value is not stored and
2
WO when read always returns 0. 0 = Do NOT write GPIO Clock Data Value bit (default). 1 =
Write GPIO Clock Data Value bit. AccessType: Write Only

GPIO_CLOCK_DIRECTION_VALUE_R_W: This is the value that should be used to

define the output enable of the GPIO Clock pin. This value is only written into the
0b register if GPIO Clock DIRECTION MASK is also asserted. The value that will appear on
1
RW the pin is defined by what is in the register for the GPIO Clock DATA VALUE bit. 0 = Pin
is configured as an input and the output driver is set to tri-state (default) 1 = Pin is
configured as an output.

GPIO_CLOCK_DIRECTION_MASK_WO: This is a mask bit to determine whether the

0b GPIO Clock DIRECTION VALUE bit should be written into the register. This value is not
0 stored and when read returns 0. 0 = Do NOT update the GPIO Clock Direction Value bit
WO on a write (default). 1 = Update the GPIO Clock Direction Value bit. on a write operation
to this register. AccessType: Write Only

14.10.21 GMBUS0—Offset 5100h

GMBUS Clock/Port Select gmbus clock and port select (gmbus_register.v reg_gmbus0)

Access Method
Type: Memory Mapped I/O Register GMBUS0: [GTTMMADR_LSB + 2BF20h] + 5100h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED_1

AKSV_BUFFER_SELECT

RESERVED_2
GMBUS_RATE_SELECT

PIN_PAIR_SELECT
RESERVED

HOLD_TIME_EXTENSION

Bit Default &

Description
Range Access

0b
31:16 RESERVED: Reserved.
RW
0b HOLD_TIME_EXTENSION: This bit selects the hold time on the data line driven from
15
RW the GMCH. 0 = Hold time of 0ns 1 = Hold time of 300 ns

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Bit Default &

Description
Range Access

0b
14:12 RESERVED_1: Reserved.
RW
AKSV_BUFFER_SELECT: [DevBLC, DevCTG, DevCDV] This bit selects whether the
data to be written over GMBUS comes from the Aksv buffer for HDCP authentication, or
0b from the GMBUS data buffer. Please note that when writing data from the Aksv buffer,
11 all GMBUS protocol must be followed, including indicating the number of bytes to be
RW transferred during the DATA phase of a GMBUS cycle. 0 (Default) Use the GMBUS data
buffer (GMBUS3) for data transmission 1 Use the Aksv data buffer (GMBUS6 and
GMBUS7) for data transmission. [DevBW, DevCL] Reserved:
GMBUS_RATE_SELECT: These two bits select the rate that the GMBUS will run at. It
0b also defines the AC timing parameters used. It should only be changed when between
10:8
RW transfers when the GMBUS is idle. 1xx = Reserved. 000 = 100 KHz 001 = 50 KHz 010 =
400 KHz 011 = 1 MHz for SDVO

0b
7:3 RESERVED_2: Reserved.
RW

PIN_PAIR_SELECT: This field selects an GMBUS pin pair for use in the GMBUS
communication. Use the table above to determine which pin pairs are available for a
0b particular device and the intended function of that pin pair. Note that it is not a straight
2:0 forward mapping of port numbers to pair select numbers. 000 = None (disabled) 001 =
RW MIPI I2C use 010 = Dedicated Analog Monitor DDC Pins (DDC1DATA, DDC1CLK) 011 =
Reserved 100 = DP/HDMI port C Use [DevCTG] 101 = sDVO/HDMI Use 110 = Reserved
111 = D connector control signals

14.10.22 GMBUS1—Offset 5104h

GMBUS Command and Status gmbus command and status (gmbus_register.v
reg_gmbus1)

Access Method
Type: Memory Mapped I/O Register
GMBUS1: [GTTMMADR_LSB + 2BF20h] + 5104h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

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31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

_7_BIT_GMBUS_SLAVE_ADDRESS_SADDR
_8_BIT_GMBUS_SLAVE_REGISTER_INDEX_INDEX
SOFTWARE_CLEAR_INTERRUPT_SW_CLR_INT

SLAVE_DIRECTION_BIT
SOFTWARE_READY_SW_RDY
ENABLE_TIMEOUT_ENT
RESERVED

TOTAL_BYTE_COUNT
BUS_CYCLE_SELECT

Bit Default &

Description
Range Access

SOFTWARE_CLEAR_INTERRUPT_SW_CLR_INT: This bit must be clear for normal

operation. Setting the bit , then clearing it acts as local reset to the GMBUS controller.
This bit is commonly used by software to clear a BUS_ERROR when a slave device
delivers a NACK. 0 = If this bit is written as a zero when its current state is a one, will
0b clear the HW_RDY bit and allows register writes to be accepted to the GMBUS registers
31 (Write Protect Off). This bit is cleared to zero when an event causes the HW_RDY bit
RW transition to occur. 1 = Asserted by software after servicing the GMBUS interrupt.
Setting this bit causes the INT status bit to be cleared. Setting (1) this bit also asserts
the HW_RDY bit (until this bit is written with a 0). When this bit is set, no writes to
GMBUS registers will cause the contents to change with the exception of this bit which
can be written.

0b SOFTWARE_READY_SW_RDY: Data handshake bit used in conjunction with HW_RDY

30 bit. 0 = De-asserted via the assertion event for HW_RDY bit 1 = When asserted by
RW software, results in de-assertion of HW_RDY bit

ENABLE_TIMEOUT_ENT: Enables timeout for slave response. When this bit is enabled
0b and the slave device response has exceeded the timeout period, the GMBUS Slave Stall
29
RW Timeout Error interrupt bit is set. 0 = disable timeout counter 1 = enable timeout
counter
0b
28 RESERVED: Reserved.
RW
BUS_CYCLE_SELECT: 000 = No GMBUS cycle is generated. 001 = GMBUS cycle is
generated without an INDEX, with no STOP, and ends with a WAIT 010 = Reserved 011
= GMBUS cycle is generated with an INDEX, with no STOP, and ends with a WAIT 100 =
Generates a STOP if currently in a WAIT or after the completion of the current byte if
active. 101 = GMBUS cycle is generated without an INDEX and with a STOP 110 =
Reserved 111 = GMBUS cycle is generated with an INDEX and with a STOP GMBUS cycle
0b will always consist of a START followed by Slave Address, followed by an optional read or
27:25 write data phase. A read cycle with an index will consist of a START followed by a Slave
RW Address a WRITE indication and the INDEX and then a RESTART with a Slave Address
and an optional read data phase. The GMBUS cycle will terminate either with a STOP or
by entering a wait state. The WAIT state is exited by generating a STOP or by starting
another GMBUS cycle. This can only cause a STOP to be generated if a GMBUS cycle is
generated, the GMBUS is currently in a data phase, or it is in a WAIT phase: Note that
the three bits can be decoded as follows: 27 = STOP generated 26 = INDEX used 25 =
cycle ends in a WAIT

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 Graphics, Video and Display

Bit Default &

Description
Range Access

TOTAL_BYTE_COUNT: (9-bits). This determines the total number of bytes to be

0b transferred during the DATA phase of a GMBUS cycle. The DATA phase can be
24:16
RW prematurely terminated by generating a STOP while in the DATA phase (see Bus Cycle
Select). Do not change the value of this field during GMBUS cycles transactions.
_8_BIT_GMBUS_SLAVE_REGISTER_INDEX_INDEX: This field specifies the 8-bits
0b of index to be used for the generated bus write transaction or the index used for the
15:8
RW WRITE portion of the WRITE/READ pair. It only has an effect if the enable Index bit is
set. Do not change this field during a GMBUS transaction.

_7_BIT_GMBUS_SLAVE_ADDRESS_SADDR: When a GMBUS cycle is to be

generated using the Bus Cycle Select field, this field specifies the value of the slave
address that is to be sent out. For use with 10-bit slave address devices, set this value
0b to 11110XXb (where the last two bits (xx) are the two MSBs of the 10-bit address) and
7:1 the slave direction bit to a write. This is followed by the first data byte being the 8 LSBs
RW of the 10-bit slave address. Special Slave Addresses 0000 000R = General Call Address
0000 000W = Start byte 0000 001x = CBUS Address 0000 010x = Reserved 0000 011x
= Reserved 0000 1xxx = Reserved 1111 1xxx = Reserved 1111 0xxx = 10-Bit
addressing

SLAVE_DIRECTION_BIT: When a GMBUS cycle is to be generated based on the Bus

0b Cycle Select, this bit determines if the operation will be a read or a write. A read
0 operation with the index enabled will perform a write with just the index followed by a
RW re-start and a read. 1 = Indicates that a Read from the slave device operation is to be
performed. 0 = Indicates that a Write to slave device operation is to be performed.

14.10.23 GMBUS2—Offset 5108h

GMBUS Status Register gmbus status (gmbus_register.v reg_gmbus2)

Access Method
Type: Memory Mapped I/O Register GMBUS2: [GTTMMADR_LSB + 2BF20h] + 5108h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000800h

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31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0

SLAVE_STALL_TIMEOUT_ERROR_READ_ONLY
HARDWARE_WAIT_PHASE_HW_WAIT_PHASE_READ_ONLY
RESERVED

INUSE

GMBUS_INTERRUPT_STATUS_READ_ONLY

GMBUS_ACTIVE_GA_READ_ONLY
HARDWARE_READY_HW_RDY_READ_ONLY
NAK_INDICATOR_READ_ONLY

CURRENT_BYTE_COUNT_READ_ONLY
Bit Default &
Description
Range Access

0b
31:16 RESERVED: Reserved.
RW
INUSE: 0 = read operation that contains a zero in this bit position indicates that the
GMBUS engine is now acquired and the subsequent reads of this register will now have
this bit set. Writing a 0 to this bit has no effect. 1 = read operation that contains a one
for this bit indicates that the GMBUS is currently allocated to someone else and In use .
Once set, a write of a 1 to this bit indicates that the software has relinquished the
0b GMBUS resource and will reset the value of this bit to a 0. Software wishing to arbitrate
15
RW/1C for the GMBUS resource can poll this bit until it reads a zero and will then own usage of
the GMBUS controller. This bit has no effect on the hardware, and is only used as
semaphore among various independent software threads that don t know how to
synchronize their use of this resource that may need to use the GMBUS logic. Writing a
one to this bit is software s indication that the software use of this resource is now
terminated and it is available for other clients. AccessType: One to clear
HARDWARE_WAIT_PHASE_HW_WAIT_PHASE_READ_ONLY: 0 = The GMBUS
engine is not in a wait phase. 1 = Set when GMBUS engine is in wait phase. Wait phase
0b is entered at the end of the current transaction when that transaction is selected not to
14
RO terminate with a STOP. Once in a WAIT_PHASE, the software can now choose to
generate a STOP cycle or a repeated start (RESTART) cycle followed by another GMBUS
transaction on the GMBUS. AccessType: Read Only

0b SLAVE_STALL_TIMEOUT_ERROR_READ_ONLY: This bit indicates that a slave stall

13 timeout has occurred. It is tied to the Enable Timeout (ENT) bit. 0 = No slave timeout
RO has occurred. 1 = A slave acknowledge timeout has occurred AccessType: Read Only
GMBUS_INTERRUPT_STATUS_READ_ONLY: This bit indicates that an event that
causes a GMBUS interrupt has occurred. 0 = The conditions that could cause a GMBUS
0b interrupt have not occurred or this bit has been cleared by software assertion of the
12
RO SW_CLR_INT bit. 1 = GMBUS interrupt event occurred. This interrupt must have been
one of the types enabled in the GMBUS4 register. [DevCDV, DevCTG]: Reserved
AccessType: Read Only

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Bit Default &

Description
Range Access

HARDWARE_READY_HW_RDY_READ_ONLY: This provides a method of detecting

when the current software client routine can proceed with the next step in a sequence of
GMBUS operations. This data handshake bit is used in conjunction with the SW_RDY bit.
When this bit is changed to asserted by the GMBUS controller, it results in the de-
assertion of the SW_RDY bit. 0 = Condition required for assertion has not occurred or
when this bit was a one and: SW_RDY bit has been asserted. During a GMBUS read
transaction, after the each read of the data register. During a GMBUS write transaction,
1b after each write of the data register. SW_CLR_INT bit has been cleared. 1 = This bit is
11
RO asserted under the following conditions: After a reset or when the transaction is aborted
by the setting of the SW_CLR_INT bit. When an active GMBUS cycle has terminated with
a STOP. When during a GMBUS write transaction, the data register needs and can accept
another four bytes of data. During a GMBUS read transaction, this bit is asserted when
the data register has four bytes of new data or the read transaction DATA phase is
complete and the data register contains the last few bytes of the read data. This bit
resumes to normal operation when the SW_CLR_INT bit is written to a 0. AccessType:
Read Only
NAK_INDICATOR_READ_ONLY: Was previously called Slave Acknowledge Timeout
0b Error SATOER. 0 = No bus error has been detected or SW_CLR_INT has been written as
10
RO a zero since the last bus error. 1 = Set by hardware if any expected device acknowledge
is not received from the slave within the timeout. AccessType: Read Only

GMBUS_ACTIVE_GA_READ_ONLY: This is a status bit that indicates whether the

0b GMBUS controller is in an IDLE state or not. 0 = The GMBUS controller is currently IDLE.
9
RO 1 = This indicates that the bus is in START, ADDRESS, INDEX, DATA, WAIT, or STOP
Phase. Set when GMBUS hardware is not IDLE. AccessType: Read Only
CURRENT_BYTE_COUNT_READ_ONLY: Can be used to determine the number of
bytes currently transmitted/received by the GMBUS controller hardware. Set to zero at
0b the start of a GMBUS transaction data transfer and incremented after the completion of
8:0
RO each byte of the data phase. Note that because reads have internal storage, the byte
count on a read operation may be ahead of the data that has been accepted from the
data register. AccessType: Read Only

14.10.24 GMBUS3—Offset 510Ch

GMBUS Data Buffer gmbus data buffer (gmbus_register.v reg_gmbus3)

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) GMBUS3: [GTTMMADR_LSB + 2BF20h] + 510Ch

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DATA_BYTE_3

DATA_BYTE_2

DATA_BYTE_1

DATA_BYTE_0

Bit Default &

Description
Range Access

0b
31:24 DATA_BYTE_3: gmbus data buffer DATA Byte 3
RW

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Bit Default &

Description
Range Access

0b
23:16 DATA_BYTE_2: gmbus data buffer DATA Byte 2
RW
0b
15:8 DATA_BYTE_1: gmbus data buffer DATA Byte 1
RW
0b
7:0 DATA_BYTE_0: gmbus data buffer DATA Byte 0
RW

14.10.25 GMBUS4—Offset 5110h

GMBUS Interrupt Mask gmbus interrupt mask (gmbus_register.v reg_gmbus4)

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) GMBUS4: [GTTMMADR_LSB + 2BF20h] + 5110h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED

INTERRUPT_MASK
Bit Default &
Description
Range Access

0b
31:5 RESERVED: Reserved.
RW
INTERRUPT_MASK: This field specifies which GMBUS interrupts events may contribute
to the setting of gmbus interrupt status bit in second level interrupt status register
0b PIPEASTAT. Bit 4: GMBUS Slave stall timeout Bit 3: GMBUS NAK Bit 2: GMBUS Idle Bit 1:
4:0
RW Hardware wait (GMBUS cycle without a stop has completed) Bit 0: Hardware ready
(Data has been transferred) 0 = Disable this type of GMBUS interrupt 1 = Enable this
type of GMBUS interrupt

14.10.26 GMBUS5—Offset 5120h

2 Byte Index Register gmbus index (gmbus_register.v reg_gmbus5)

Access Method
Type: Memory Mapped I/O Register
GMBUS5: [GTTMMADR_LSB + 2BF20h] + 5120h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

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 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

_2_BYTE_SLAVE_INDEX
_2_BYTE_INDEX_ENABLE

RESERVED

Bit Default &

Description
Range Access

_2_BYTE_INDEX_ENABLE: When this bit is asserted (1), then bits 15:00 are used as
0b the index. Bits 15:8 are used in the first byte which is the most significant index bits.
31
RW The slave index in the GMBUS1(15:8) are ignored. Bits 7:0 are used in the second byte
which is the least significant index bits.
0b
30:16 RESERVED: Reserved.
RW
0b _2_BYTE_SLAVE_INDEX: This is the 2 byte index used in all GMBUS accesses when
15:0
RW bit 31 is asserted (1).

14.10.27 GMBUS6—Offset 5130h

GMBUS Aksv Buffer Low [DevBLC, DevCTG, DevCDV] gmbus data buffer
(gmbus_register.v reg_gmbus6)

Access Method
Type: Memory Mapped I/O Register GMBUS6: [GTTMMADR_LSB + 2BF20h] + 5130h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DATA_BYTE_3

DATA_BYTE_2

DATA_BYTE_1

DATA_BYTE_0

Bit Default &

Description
Range Access

0b
31:24 DATA_BYTE_3: gmbus data buffer DATA Byte 3
WO
0b
23:16 DATA_BYTE_2: gmbus data buffer DATA Byte 2
WO
0b
15:8 DATA_BYTE_1: gmbus data buffer DATA Byte 1
WO

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Bit Default &

Description
Range Access

0b
7:0 DATA_BYTE_0: gmbus data buffer DATA Byte 0
WO

14.10.28 GMBUS7—Offset 5134h

GMBUS Aksv Buffer High [DevBLC, DevCTG, DevCDV] gmbus data buffer
(gmbus_register.v reg_gmbus7)

Access Method
Type: Memory Mapped I/O Register
GMBUS7: [GTTMMADR_LSB + 2BF20h] + 5134h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED

AKSV_SELECTION_BIT

DATA_BYTE_5
Bit Default &
Description
Range Access

0b
31:9 RESERVED: MBZ
WO
AKSV_SELECTION_BIT: [DevVLVP]:

• 0 = The fuse value of the Aksv is used.

0b • 1 = The register value of the Aksv is used.
8
WO Aksv Selection Bit [DevELK, DevCDV]:

• 0 = The register value of the Aksv is used.

• 1 = The fuse value of the Aksv is used. [DevBLC, DevCTG] Reserved
0b
7:0 DATA_BYTE_5: gmbus data buffer DATA Byte 5
WO

14.10.29 DPLLA_CTRL—Offset 6014h

DPLL A Control Register DPLL A Control (cpdmmreg.v reg03_lt)

Access Method
Type: Memory Mapped I/O Register DPLLA_CTRL: [GTTMMADR_LSB + 2BF20h] + 6014h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

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Default: 00002000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
DPLL_A_VCO_ENABLE

VGA_MODE_DISABLE

ENABLE_SINGLE_DPLLA_FREQUENCY_FOR_BOTH_PIPES

VCC_VOLTAGE_SELECT

DPIO_PHYSTATUS_READ_ONLY
DPLL_A_REFERENCE_INPUT_SELECT
DPLLA_EXTERNAL_CLOCK_BUFFER_ENABLE
REFA_CLOCK_ENABLE

RESERVED

DISPLAY_RATE_SWITCH_PIPEA
RESERVED_1

RESERVED_2

RESERVED_3
Bit Default &
Description
Range Access

0b DPLL_A_VCO_ENABLE: Disabling the PLLA will cause the display dot clock to stop. 0 =
31 DPLLA is disabled in its lowest power state (default) 1 = DPLLA is enabled and
RW operational (42usec until lock without calibration and 110usec for calibration)
DPLLA_EXTERNAL_CLOCK_BUFFER_ENABLE: [DevVLVP] 0 = Disable DPLLA clock
0b from being driven out 1 = Enable DPLLA clock to be drive out [DevCDV] Reserved DPLLA
30
RW Serial DVO High Speed IO clock Enable 0 = High Speed IO Clock Disabled (default) 1 =
High Speed IO Clock Enabled (must be set in Serial DVO and HDMI modes)
0b REFA_CLOCK_ENABLE: [DevCDV, DevVLVP]: Indicate the reference clock of PLL A is
29
RW enable 0 Disable (default) 1 Enable

VGA_MODE_DISABLE: When in native VGA modes, writes to the VGA MSR register
0b causes the value in the selected (by MSR bits) VGA clock control register to be loaded
28 into the active register. This allows the VGA clock select to select the pixel frequency
RW between the two standard VGA pixel frequencies. 0 = VGA MSR(3:2) Clock Control bits
select DPLL A Frequency 1 = Disable VGA Control
ENABLE_SINGLE_DPLLA_FREQUENCY_FOR_BOTH_PIPES: [DevVLVP] When two
pipes are enabled for eDP and both pipes can run with the same DP frequency either
162MHz or 270MHz. Setting this mode can allow using only DPLLA to feed both pipes.
0b DPLLB should be shutdown to save power. This control is double buffered. 00 = Disabled
27:26
RW 01 = Enabled 10 = Reserved 11 = Reserved [DevCDV] Reserved DPLLA Mode Select :
Configure the DPLLA for various supported Display Modes 00 = Reserved 01 = DPLLA in
DAC/Serial DVO/UDI/Integrated TV mode 10 = DPLLA in LVDS mode (Mobile devices
ONLY) otherwise RESERVED 11 = DP
RESERVED: [DevCDV, DevVLVP] FPA0/FPA1 P2 Clock Divide: 00 = Divide by 10. This is
0b used when Dot Clock =( 270MHz in sDVO, HDMI, or DAC modes 01 = Divide by 5. This
25:24 is used when Dot Clock )270MHz 10 = Reserved 11 = Reserved For DPLLA in LVDS
RW mode, BITS(27:26)=10 00 = Divide by 14. This is used in Single-Channel LVDS 01 =
Divide by 7. This is used in Dual-Channel LVDS 10 = Reserved 11 = Reserved

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352 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

RESERVED_1: [DevCDV, DevVLVP] FPA0/ FPA1 P1 Post Divisor: Writes to this byte
cause the staging register contents to be written into the active register when in the
0b VGA mode of operation. This will also occur when the VGA MSR register is written.
23:16 00000001b = Divide by one 00000010b = Divide by two 00000100b = Divide by three
RW 00001000b = Divide by four 00010000b = Divide by five 00100000b = Divide by six
01000000b = Divide by seven 10000000b = Divide by Eight All other values are illegal
and should not be used
0b RESERVED_2: Write as zero PLLA Lock [DevCDV, DevVLVP] (RO) 1 - PLLA Lock 0 PLLA
15
RW unlock

0b VCC_VOLTAGE_SELECT: [DevVLVP] This control selects the VCC voltage in DPLL 0 =

14
RW 1.0 V (default) 1 = voltage for LDO circuit (for TNG use) [DevCDV] Reserved

DPLL_A_REFERENCE_INPUT_SELECT: [DevVLVP] This control selects the integrated

core refclk or external OSC refclk as the input clock source to DPLL A. 0 = External
refclk pad (27MHz) 1 = Integrated core refclk (default is 100 MHz) [DevCDV] Reserved
1b PLL Reference Input Select: The PLL reference should be selected based on the display
13
RW device that is being driven. The standard reference clock is used for CRT modes using
the analog display port or LCD panels for both the sDVO connected transmitter or the
integrated LVDS. TV Clock in should be selected when driving an sDVO connected TV
encoder.
RESERVED_3: [DevCDV, DevVLVP] Parallel to Serial Load Pulse phase selection:
Programmable select bits to choose the relative phase of the high speed (10X) DPLL
clock used for generating the parallel to serial load pulse for digital display port on PCIe.
The relative phase is the number of flop delays (phase 0 represents 1 flop delay) of the
1X parallel data synchronization signal in the 10X clock domain. The earliest selectable
0b clock phase is 4. A phase selection of 10 or greater simply extends the flop delay count
12:9 to sample delayed data. 0100 = use clock phase-4 0101 = use clock phase-5 0110 =
RW use clock phase-6 (Default value) 0111 = use clock phase-7 1000 = use clock phase-8
1001 = use clock phase-9 1010 = use clock phase-10 1011 = use clock phase-11 1100
= use clock phase-12 1101 = use clock phase-13 Phases 0 through 3 are not available
for Load Pulse selection. [DevCL] The following programming is recommended for
Crestline based on PV timing analysis: 1101 use clock phase-13 [DevBLC, DevCTG]
Reserved. Programming for load pulse is in PXP AFE config space.
DISPLAY_RATE_SWITCH_PIPEA: [DevCTG, DevCDV, DevVLVP] Switching this bit
0b (transition 0 to 1 or 1 to 0) causes the DSP HW to disable and than enable the DPLL
8 during vblank (2 row) in order to switch the frequency at the DPLL (new dividers stored
RW at the DPIO which is double buffered) (This bit is only available when bits 17:16 of the
PIPEACONF register are 00) [DevBW, DevCL, DevBLC] Reserved
DPIO_PHYSTATUS_READ_ONLY: [DevVLVP] This field contains the two 4-bit ModPhy
lane status. One for PortB and one for PortC Bit 7:4 = Port C PhyStatus[3:0] Bit 3:0 =
Port B PhyStatus[3:0] [DevBW, DevCL, DevBLC, DevCDV] Reserved [DevCTG] FPA1 P1
0b Post Divisor: Writes to this byte cause the staging register contents to be written into
7:0 the active register when in the VGA mode of operation. This will also occur when the
RO VGA MSR register is written. 00000001b - Divide by one 00000010b - Divide by two
00000100b - Divide by three 00001000b - Divide by four 00010000b - Divide by five
00100000b - Divide by six 01000000b - Divide by seven 10000000b - Divide by Eight
All other values are illegal and should not be used AccessType: Read Only

14.10.30 DPLLB_CTRL—Offset 6018h

DPLL B Control Registers DPLL B Control (cpdmmreg.v reg04_lt)

Access Method
Type: Memory Mapped I/O Register DPLLB_CTRL: [GTTMMADR_LSB + 2BF20h] + 6018h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00006000h

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 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0

DPIO_COMMON_REGISTER_INTERFACE_CLOCK_SELECT_CRICLKSEL
DPLL_B_REFERENCE_INPUT_SELECT
DPLL_B_VCO_ENABLE

VGA_MODE_DISABLE

ENABLE_SINGLE_DPLLB_FREQUENCY_FOR_BOTH_PIPES

DISPLAY_RATE_SWITCH_PIPEB
DPLLB_EXTERNAL_CLOCK_BUFFER_ENABLE
REFB_CLOCK_ENABLE

RESERVED

RESERVED_1

RESERVED_2

RESERVED_3

RESERVED_4
Bit Default &
Description
Range Access

0b DPLL_B_VCO_ENABLE: Disabling the PLLB will cause the display dot clock to stop. 0 =
31 DPLLB is disabled in its lowest power state (default) 1 = DPLLB is enabled and
RW operational (42usec until lock without calibration and 110usec for calibration)

DPLLB_EXTERNAL_CLOCK_BUFFER_ENABLE: [DevVLVP] 0 = Disable DPLLB clock

0b from being driven out 1 = Enable DPLLB clock to be drive out [DevCDV] Reserved DPLLB
30
RW Serial DVO High Speed IO clock Enable 0 = High Speed IO Clock Disabled (default) 1 =
High Speed IO Clock Enabled (must be set in Serial DVO and HDMI modes)
0b REFB_CLOCK_ENABLE: [DevCDV, DevVLVP]: Indicate the reference clock of PLL A is
29
RW enable 0 Disable (default) 1 Enable

VGA_MODE_DISABLE: When in native VGA modes, writes to the VGA MSR register
0b causes the value in the selected (by MSR bits) VGA clock control register to be loaded
28 into the active register. This allows the VGA clock select to select the pixel frequency
RW between the two standard VGA pixel frequencies. 0 = VGA MSR(3:2) Clock Control bits
select DPLL A Frequency 1 = Disable VGA Control
ENABLE_SINGLE_DPLLB_FREQUENCY_FOR_BOTH_PIPES: [DevVLVP] When two
pipes are enabled for eDP and both pipes can run with the same DP frequency either
162MHz or 270MHz. Setting this mode can allow using only DPLLB to feed both pipes.
0b DPLLA should be shutdown to save power. 00 = Disabled 01 = Enabled 10 = Reserved
27:26
RW 11 = Reserved [DevCDV] Reserved DPLLB Mode Select : Configure the DPLLB for
various supported Display Modes 00 = Reserved 01 = DPLLA in DAC/Serial DVO/UDI/
Integrated TV mode 10 = DPLLA in LVDS mode (Mobile devices ONLY) otherwise
RESERVED 11 = DP

RESERVED: [DevCDV, DevVLVP] FPB0/FPB1 P2 Clock Divide: 00 = Divide by 10. This is

0b used when Dot Clock =( 270MHz in sDVO, HDMI, or DAC modes 01 = Divide by 5. This
25:24 is used when Dot Clock )270MHz 10 = Reserved 11 = Reserved For DPLLB in LVDS
RW mode, BITS(27:26)=10 00 = Divide by 14. This is used in Single-Channel LVDS 01 =
Divide by 7. This is used in Dual-Channel LVDS 10 = Reserved 11 = Reserved

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354 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

RESERVED_1: [DevCDV, DevVLVP] FPB0/ FPB1 P1 Post Divisor: Writes to this byte
cause the staging register contents to be written into the active register when in the
0b VGA mode of operation. This will also occur when the VGA MSR register is written.
23:16 00000001b = Divide by one 00000010b = Divide by two 00000100b = Divide by three
RW 00001000b = Divide by four 00010000b = Divide by five 00100000b = Divide by six
01000000b = Divide by seven 10000000b = Divide by Eight All other values are illegal
and should not be used
0b RESERVED_2: Write as zero PLLB Lock [DevCDV, DevVLVP] (RO) 1 - PLLB Lock 0 PLLB
15
RW unlock

1b DPIO_COMMON_REGISTER_INTERFACE_CLOCK_SELECT_CRICLKSEL:
14 [DevVLVP] This bit is to control the clock source for DPIO Common Register Interface 0
RW = Use external reclk pad 1 = Use integrated core refclk (default)
DPLL_B_REFERENCE_INPUT_SELECT: [DevVLVP] This control selects the integrated
core refclk or external OSC refclk as the input clock source to DPLL B. 0 = External
refclk pad (27MHz) 1 = Integrated core refclk (default is 100 MHz) [DevCDV] Reserved
1b PLL Reference Input Select: The PLL reference should be selected based on the display
13
RW device that is being driven. The standard reference clock is used for CRT modes using
the analog display port or LCD panels for both the sDVO connected transmitter or the
integrated LVDS. TV Clock in should be selected when driving an sDVO connected TV
encoder.
RESERVED_3: [DevCDV, DevVLVP] Parallel to Serial Load Pulse phase selection:
Programmable select bits to choose the relative phase of the high speed (10X) DPLL
clock used for generating the parallel to serial load pulse for digital display port on PCIe.
The relative phase is the number of flop delays (phase 0 represents 1 flop delay) of the
1X parallel data synchronization signal in the 10X clock domain. The earliest selectable
0b clock phase is 4. A phase selection of 10 or greater simply extends the flop delay count
12:9 to sample delayed data. 0100 = use clock phase-4 0101 = use clock phase-5 0110 =
RW use clock phase-6 (Default value) 0111 = use clock phase-7 1000 = use clock phase-8
1001 = use clock phase-9 1010 = use clock phase-10 1011 = use clock phase-11 1100
= use clock phase-12 1101 = use clock phase-13 Phases 0 through 3 are not available
for Load Pulse selection. [DevCL] The following programming is recommended for
Crestline based on PV timing analysis: 1101 use clock phase-13 [DevBLC, DevCTG]
Reserved. Programming for load pulse is in PXP AFE config space.
DISPLAY_RATE_SWITCH_PIPEB: [DevCTG, DevCDV, DevVLVP] Switching this bit
0b (transition 0 to 1 or 1 to 0) causes the DSP HW to disable and than enable the DPLL
8 during vblank (2 row) in order to switch the frequency at the DPLL (new dividers stored
RW at the DPIO which is double buffered) (This bit is only available when bits 17:16 of the
PIPEACONF register are 00) [DevBW, DevCL, DevBLC] Reserved
RESERVED_4: [DevBW, DevCL, DevBLC, DevCDV, DevVLVP] [DevCTG] FPB1 P1 Post
Divisor: Writes to this byte cause the staging register contents to be written into the
0b active register when in the VGA mode of operation. This will also occur when the VGA
7:0 MSR register is written. 00000001b - Divide by one 00000010b - Divide by two
RW 00000100b - Divide by three 00001000b - Divide by four 00010000b - Divide by five
00100000b - Divide by six 01000000b - Divide by seven 10000000b - Divide by Eight
All other values are illegal and should not be used

14.10.31 DPLLAMD—Offset 601Ch

DPLL A SDVO/HDMI Multiplier/Divisor Register Pipe A multiply (cpdmmreg.v reg15_lt)

Access Method
Type: Memory Mapped I/O Register
DPLLAMD: [GTTMMADR_LSB + 2BF20h] + 601Ch
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000003h

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 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1

DPLL_A_SDVO_HDMI_MULTIPLIER_HI_RES

DPLL_A_SDVO_HDMI_MULTIPLIER_VGA
DPLL_A_HDMI_DIVIDER_HI_RES

DPLL_A_HDMI_DIVIDER_VGA
RESERVED

RESERVED_1

RESERVED_2

RESERVED_3
Bit Default &
Description
Range Access

0b
31:30 RESERVED: Reserved.
RW
DPLL_A_HDMI_DIVIDER_HI_RES: When the source is high resolution, this field
determines the number of pixels to be included in the multiplied packet defined by the
SDVO/HDMI multiplier. For SDVO and CRT, the only valid setting is 1x. HDMI example: If
the pixel clock on the display should be 180MHz and the display PLL is set to 270MHz,
0b two pixels and one fill code must be sent over HDMI (fixed frequency mode only).
29:24 Therefore, the HDMI divider should be set to 2 and the SDVO/HDMI multiplier should be
RW set to 3, since 180 MHz (pixel clock) = 2/3*270MHz (link character clock) This divider
must be set to 1x for any mode except HDMI fixed frequency mode. Value in this
register = number of pixels per packet 1 Default: 0000 1 pixel per packet (Default
value, must be set to 1x for any mode except HDMI fixed frequency mode) Range: 0-63
(1 pixel per packet 64 pixels per packet)

0b
23:22 RESERVED_1: Reserved.
RW

0b DPLL_A_HDMI_DIVIDER_VGA: When the source is VGA, these bits specify the HDMI
21:16
RW divider. The format of this field is the same as that of the hi-res divider.

0b
15:14 RESERVED_2: Reserved.
RW
DPLL_A_SDVO_HDMI_MULTIPLIER_HI_RES: This field determines the data
multiplier for sDVO and is also applied to CRT. In order to keep the clock rate to a more
0b narrow range of rates, the multipler is set and the Display PLL programmed to a multiple
13:8
RW of the display mode s actual clock rate. This is unrelated to the pixel multiply that is
selectable per plane. 6x and higher multipliers can only be used for HDMI mode. Value
in this register = multiplication factor - 1 Default: 000000 (1X) Range: 0 63 (1X 64X)
0b
7:6 RESERVED_3: Reserved.
RW
DPLL_A_SDVO_HDMI_MULTIPLIER_VGA: When the source is VGA, these bits
000011b specify the HDMI multiplier. The format of this field is the same as that of the hi-res
5:0
RW multiplier. 6x and higher multipliers can only be used for HDMI mode. Value in this
register = multiplication factor - 1 Default: 000011 (4X) Range: 0 63 (1X 64X)

14.10.32 DPLLBMD—Offset 6020h

DPLL B SDVO/HDMI Multiplier/Divisor Register Pipe B multiplyer (cpdmmreg.v
reg16_lt)

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356 Datasheet
Graphics, Video and Display

Access Method
Type: Memory Mapped I/O Register
DPLLBMD: [GTTMMADR_LSB + 2BF20h] + 6020h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000003h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
DPLL_B_HDMI_DIVIDER_HI_RES

DPLL_B_HDMI_DIVIDER_VGA

DPLL_B_SDVO_HDMI_MULTIPLIER_VGA
RESERVED_1

RESERVED_2

RESERVED_3
RESERVED

Bit Default &

Description DPLL_B_SDVO_HDMI_MULTIPLIER_HI_RES
Range Access

0b
31:30 RESERVED: Reserved.
RW

DPLL_B_HDMI_DIVIDER_HI_RES: When the source is high resolution, this field

determines the number of pixels to be included in the multiplied packet defined by the
SDVO/HDMI multiplier. For SDVO and CRT, the only valid setting is 1x. HDMI example: If
the pixel clock on the display should be 180MHz and the display PLL is set to 270MHz,
0b two pixels and one fill code must be sent over HDMI (fixed frequency mode only).
29:24 Therefore, the HDMI divider should be set to 2 and the SDVO/HDMI multiplier should be
RW set to 3, since 180 MHz (pixel clock) = 2/3*270MHz (link character clock) This divider
must be set to 1x for any mode except HDMI fixed frequency mode. Value in this
register = number of pixels per packet 1 Default: 0000 1 pixel per packet (Default
value, must be set to 1x for any mode except HDMI fixed frequency mode) Range: 0-63
(1 pixel per packet 64 pixels per packet)

0b
23:22 RESERVED_1: Reserved.
RW

0b DPLL_B_HDMI_DIVIDER_VGA: When the source is VGA, these bits specify the HDMI
21:16
RW divider. The format of this field is the same as that of the hi-res divider.

0b
15:14 RESERVED_2: Reserved.
RW

DPLL_B_SDVO_HDMI_MULTIPLIER_HI_RES: This field determines the data

multiplier for sDVO and is also applied to CRT. In order to keep the clock rate to a more
0b narrow range of rates, the multipler is set and the Display PLL programmed to a multiple
13:8
RW of the display mode s actual clock rate. This is unrelated to the pixel multiply that is
selectable per plane. 6x and higher multipliers can only be used for HDMI mode. Value
in this register = multiplication factor - 1 Default: 000011 (4X) Range: 0 63 (1X 64X)

0b
7:6 RESERVED_3: Reserved.
RW

Bay Trail-I SoC

Datasheet 357
 Graphics, Video and Display

Bit Default &

Description
Range Access

DPLL_B_SDVO_HDMI_MULTIPLIER_VGA: When the source is VGA, these bits

000011b specify the HDMI multiplier. The format of this field is the same as that of the hi-res
5:0
RW multiplier. 6x and higher multipliers can only be used for HDMI mode. Value in this
register = multiplication factor - 1 Default: 000000 (1X) Range: 0 63 (1X 64X)

14.10.33 RAWCLK_FREQ—Offset 6024h

Rawclk Frequency

Access Method
Type: Memory Mapped I/O Register
RAWCLK_FREQ: [GTTMMADR_LSB + 2BF20h] + 6024h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 0000007Dh
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 1
RESERVED

RAWCLK_FREQUENCY
Bit Default &
Description
Range Access

0b
31:10 RESERVED: Project: All Format:
RW

000111110
1b RAWCLK_FREQUENCY: Project: All Format: Program this field with rawclk frequency.
9:0
This is used to generate a divided down clock for miscellaneous timers in display.
RW

14.10.34 D_STATE—Offset 6104h

D State Function Control Register Power state behaviour (cpdmmreg.v reg11_lt)

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) D_STATE: [GTTMMADR_LSB + 2BF20h] + 6104h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 20D00400h

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358 Datasheet
Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 1 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0

DPLL_LOCK_TIME

DOT_CLOCK_PLL_POWER_DOWN_IN_D3
RESERVED

DOT_CLOCK_GATING
DPLL_MIN_POWER_DOWN

RESERVED_1

RESERVED_2
RESERVED_3
Bit Default &
Description
Range Access

001000001 DPLL_LOCK_TIME: (DevCDV): This is the time required to the DPLL to relock. The
31:16 1010000b counter using the HRAW clk (5nsec) and resolution of 5nsec. (SEG DPLL lock time is
RW 42usec)

0b
15 RESERVED: : MBZ
RW

0000100b DPLL_MIN_POWER_DOWN: (DevCDV): This is the minimum time required the DPLL
14:8 to be power down until it is allowed to turn it on again. The HW counter using HRAW clk
RW (5nsec) and has resolution of 160nsec (SEG DPLL required time is 0.5usec)
0b
7:4 RESERVED_1: : MBZ
RW
DOT_CLOCK_PLL_POWER_DOWN_IN_D3: This bit determines whether the PCI
0b Power State Powers down the Dot Clock PLLs when in D3. A 0 on this bit does not power
3 down the DPLLs, requiring software to gate them if necessary. When this bit is a 1, the
RW dot PLLs are powered down when in D3. The PCI power state is determined by bits 1:0
of the PCI Power Management Control/Status register.

0b
2 RESERVED_2: Reserved.
RW
RESERVED_3: [DevCDV] Graphics Core Clock Gating: This bit determines whether the
PCI Power State gates the Graphics Core clocks when in the D3 state. A 0 on this bit
0b does not gate the clocks, requiring software to gate them if necessary. When this bit is a
1
RW 1, the graphics core clocks are gated at the outputs of the PLLs when in D3. The PCI
power state is determined by bits 1:0 of the PCI Power Management Control/Status
register. This register field has no use in current products.
DOT_CLOCK_GATING: This bit determines whether the PCI Power State gates the Dot
0b clocks when in the D3 state. A 0 on this bit does not gate the clocks, requiring software
0 to gate them if necessary. When this bit is a 1, the dot clocks are gated at the outputs of
RW the PLLs when in D3. The PCI power state is determined by bits 1:0 of the PCI Power
Management Control/Status register.

14.10.35 DSPCLK_GATE_D—Offset 6200h

Clock Gating Disable for Display Register clock gating (cpdmmreg.v reg12_lt)

Access Method

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Datasheet 359
 Graphics, Video and Display

Type: Memory Mapped I/O Register

DSPCLK_GATE_D: [GTTMMADR_LSB + 2BF20h] + 6200h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 10000000h
31 28 24 20 16 12 8 4 0

0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DPBUNIT_PIPE_B_CLOCK_GATING_DISABLE
DPUNIT_PIPEB_CLOCK_GATING_DISABLE

AUDUNIT_CLOCK_GATING_DISABLE
VSUNIT_PIPE_A_CLOCK_GATING_DISABLE

SPRITE_C_CLOCK_GATING_DISABLE

DPOUNIT_CLOCK_GATING_DISABLE
VRDUNIT_CLOCK_GATING_DISABLE

DPUNIT_PIPEA_CLOCK_GATING_DISABLE
DPCUNIT_CLOCK_GATING_DISABLE

SPRITE_B_CLOCK_GATING_DISABLE

DPBUNIT_PIPE_A_CLOCK_GATING_DISABLE

DPIOUNIT_CLOCK_GATING_DISABLE
OVFUNIT_CLOCK_GATING_DISABLE
OVBUNIT_CLOCK_GATING_DISABLE
VSUNIT_PIPE_B_CLOCK_GATING_DISABLE

DPLSUNIT_PIPE_A_CLOCK_GATING_DISABLE
VRHUNIT_CLOCK_GATING_DISABLE

SPRITE_D_CLOCK_GATING_DISABLE

DVSUNIT_SPRITE_A_CLOCK_GATING_DISABLE
DDBUNIT_CLOCK_GATING_DISABLE
GMBUSUNIT_CLOCK_GATING_DISABLE
DPRUNIT_CLOCK_GATING_DISABLE
DPFUNIT_CLOCK_GATING_DISABLE
DPLRUNIT_PIPE_A_CLOCK_GATING_DISABLE

DPTUNIT_CLOCK_GATING_DISABLE

DPGCUNIT_PIPE_B_CLOCK_GATING_DISABLE

DPLSUNIT_PIPE_B_CLOCK_GATING_DISABLE

DCUNIT_PIPE_B_CLOCK_GATING_DISABLE
DCUNIT_PIPE_A_CLOCK_GATING_DISABLE

DPGCUNIT_PIPE_A_CLOCK_GATING_DISABLE

DPLRUNIT_PIPE_B_CLOCK_GATING_DISABLE
HDCPUNIT_CLOCK_GATING_DISABLE

Bit Default &

Description
Range Access

0b HDCPUNIT_CLOCK_GATING_DISABLE: 0 = Clock gating controlled by unit enabling

31 logic 1 = Disable clock gating function [DevBW]: Reserved. MBZ. This bit is not
RW connected on [DevBW].
0b DPUNIT_PIPEB_CLOCK_GATING_DISABLE: 0 = Clock gating controlled by unit
30
RW enabling logic 1 = Disable clock gating function

0b VSUNIT_PIPE_A_CLOCK_GATING_DISABLE: [DevVLVP] (this bit used to be in PCI

29 space in Calistoga) 0 = Clock gating controlled by unit enabling logic 1 = Disable clock
RW gating function
VRHUNIT_CLOCK_GATING_DISABLE: 0 = Clock gating controlled by unit enabling
1b logicg 1 = Disable clock gating function Clock gating should not be enabled for this unit
28
RW (this bit should always be set to 1.) [DevBW]: Reserved. MBZ. This bit is not connected
on [DevBW].

0b VRDUNIT_CLOCK_GATING_DISABLE: 0 = Clock gating controlled by unit enabling

27
RW logic 1 = Disable clock gating function

0b AUDUNIT_CLOCK_GATING_DISABLE: 0 = Clock gating controlled by unit enabling

26 logic 1 = Disable clock gating function [DevBW]: Reserved. MBZ. This bit is not
RW connected on [DevBW].

0b DPUNIT_PIPEA_CLOCK_GATING_DISABLE: 0 = Clock gating controlled by unit

25
RW enabling logic 1 = Disable clock gating function

0b DPCUNIT_CLOCK_GATING_DISABLE: 0 = Clock gating controlled by unit enabling

24
RW logic 1 = Disable clock gating function

0b VSUNIT_PIPE_B_CLOCK_GATING_DISABLE: [DevVLVP] 0 = Clock gating

23 controlled by unit enabling logic 1 = Disable clock gating function [DevBW]: Reserved.
RW MBZ. This bit is not connected on [DevBW]. [DevCDV] and [DevVLVP]: Reserved

Bay Trail-I SoC

360 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

0b SPRITE_D_CLOCK_GATING_DISABLE: [DevVLVP] 0 = Clock gating controlled by

22 unit enabling logic 1 = Disable clock gating function [DevBW]: Reserved. MBZ. This bit
RW is not connected on [DevBW]. [DevCDV]: Reserved

0b SPRITE_C_CLOCK_GATING_DISABLE: [DevVLVP] 0 = Clock gating controlled by

21 unit enabling logic 1 = Disable clock gating function [DevBW]: Reserved. MBZ. This bit
RW is not connected on [DevBW]. [DevCDV]: Reserved

0b SPRITE_B_CLOCK_GATING_DISABLE: [DevVLVP] 0 = Clock gating controlled by

20 unit enabling logic 1 = Disable clock gating function [DevBW] and [DevBLC]: Reserved.
RW MBZ. This bit is not connected on [DevBW] and [DevBLC]. [DevCDV]: Reserved

0b DVSUNIT_SPRITE_A_CLOCK_GATING_DISABLE: [DevBW] and [DevCL] 0 = Clock

19 gating controlled by unit enabling logic 1 = Disable clock gating function [DevBLC] and
RW [DevCTG]: Reserved. MBZ. This bit is not connected on [DevBLC] and [DevCTG].
0b DDBUNIT_CLOCK_GATING_DISABLE: 0 = Clock gating controlled by unit enabling
18
RW logic 1 = Disable clock gating function [DevCTG] Always program this bit to 1

0b GMBUSUNIT_CLOCK_GATING_DISABLE: 0 = Clock gating controlled by unit

17
RW enabling logic 1 = Disable clock gating function

0b DPRUNIT_CLOCK_GATING_DISABLE: 0 = Clock gating controlled by unit enabling

16
RW logic 1 = Disable clock gating function

0b DPFUNIT_CLOCK_GATING_DISABLE: 0 = Clock gating controlled by unit enabling

15
RW logic 1 = Disable clock gating function

0b DPLRUNIT_PIPE_A_CLOCK_GATING_DISABLE: 0 = Clock gating controlled by unit

14 enabling logic 1 = Disable clock gating function [DevBW] and [DevBLC]: Reserved.
RW MBZ. This bit is not connected on [DevBW] and [DevBLC].

0b DPLSUNIT_PIPE_A_CLOCK_GATING_DISABLE: 0 = Clock gating controlled by unit

13 enabling logic 1 = Disable clock gating function [DevBW] and [DevBLC]: Reserved.
RW MBZ. This bit is not connected on [DevBW] and [DevBLC].
DPTUNIT_CLOCK_GATING_DISABLE: [DevVLVP] [DevCDV] Dplunit Clock Gating
0b Disable: 0 = Clock gating controlled by unit enabling logic 1 = Disable clock gating
12
RW function [DevBW] and [DevBLC]: Reserved. MBZ. This bit is not connected on [DevBW]
and [DevBLC].
0b DPOUNIT_CLOCK_GATING_DISABLE: 0 = Clock gating controlled by unit enabling
11
RW logic 1 = Disable clock gating function

0b DPBUNIT_PIPE_A_CLOCK_GATING_DISABLE: 0 = Clock gating controlled by unit

10
RW enabling logic 1 = Disable clock gating function

0b DCUNIT_PIPE_A_CLOCK_GATING_DISABLE: 0 = Clock gating controlled by unit

9
RW enabling logic 1 = Disable clock gating function

0b DPGCUNIT_PIPE_B_CLOCK_GATING_DISABLE: 0 = Clock gating controlled by unit

8
RW enabling logic 1 = Disable clock gating function

0b DPGCUNIT_PIPE_A_CLOCK_GATING_DISABLE: 0 = Clock gating controlled by unit

7
RW enabling logic 1 = Disable clock gating function

0b DPIOUNIT_CLOCK_GATING_DISABLE: 0 = Clock gating controlled by unit enabling

6
RW logic 1 = Disable clock gating function

0b OVFUNIT_CLOCK_GATING_DISABLE: [DevBW, DevCL, DevCDV] [DevCTG] DPFCunit

5 Clock Gating Disable: 0 = Clock gating controlled by unit enabling logic 1 = Disable
RW clock gating function

0b OVBUNIT_CLOCK_GATING_DISABLE: [DevBW, DevCL, DevCDV] [DevCTG]

4 DPFDunit Clock Gating Disable: 0 = Clock gating controlled by unit enabling logic 1 =
RW Disable clock gating function

0b
3 DPLRUNIT_PIPE_B_CLOCK_GATING_DISABLE: (not in CDV)
RW

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Datasheet 361
 Graphics, Video and Display

Bit Default &

Description
Range Access

0b
2 DPLSUNIT_PIPE_B_CLOCK_GATING_DISABLE: (not in CDV)
RW
DPBUNIT_PIPE_B_CLOCK_GATING_DISABLE: [DevVLVP] [DevBW, DevCL,
0b DevCDV] Ovuunit Clock Gating Disable: 0 = Clock gating controlled by unit enabling
1
RW logic 1 = Disable clock gating function [DevBLC] and [DevCTG]: Reserved. MBZ. This bit
is not connected on [DevBLC] and [DevCTG].
DCUNIT_PIPE_B_CLOCK_GATING_DISABLE: [DevVLVP] [DevBW, DevCL, DevCDV]
0b Ovlunit Clock Gating Disable: 0 = Clock gating controlled by unit enabling logic 1 =
0
RW Disable clock gating function [DevBLC] and [DevCTG]: Reserved. MBZ. This bit is not
connected on [DevBLC] and [DevCTG].

14.10.36 DPPSR_CGDIS—Offset 6204h

Panel Self Refresh Clock Gating Disable for Display PSR clock gating disable controls
(cpdmmreg.v)

Access Method
Type: Memory Mapped I/O Register DPPSR_CGDIS: [GTTMMADR_LSB + 2BF20h] + 6204h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000200h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
DISPLAY_PLANE_A_PSR_CLOCK_GATING_DISABLE

DISPLAY_BLENDER_A_PSR_CLOCK_GATING_DISABLE
DISPLAY_PLANE_B_PSR_CLOCK_GATING_DISABLE
SPRITE_A_PSR_CLOCK_GATING_DISABLE

SPRITE_D_PSR_CLOCK_GATING_DISABLE

DISPLAY_BLENDER_B_PSR_CLOCK_GATING_DISABLE

DPOUNIT_PSR_CLOCK_GATING_DISABLE
HDCPUNIT_PSR_CLOCK_GATING_DISABLE

DISPLAY_FUSE_WRAPPER_PSR_CLOCK_GATING_DISABLE
AUDFUNIT_PSR_CLOCK_GATING_DISABLE
DPIO_CLOCK_BUFFER_ENABLE_CLOCK_GATING_DISABLE

CURSOR_A_PSR_CLOCK_GATING_DISABLE

AUDBUNIT_PSR_CLOCK_GATING_DISABLE
CURSOR_B_PSR_CLOCK_GATING_DISABLE

CPDUNIT_PSR_CLOCK_GATING_DISABLE

DPFUNIT_PSR_CLOCK_GATING_DISABLE
DDBMUNIT_PSR_CLOCK_GATING_DISABLE

DPIOUNIT_PSR_CLOCK_GATING_DISABLE

VRDUNIT_PSR_CLOCK_GATING_DISABLE
LOW_POWER_SINGLE_PIPE_A_LPSSA_CLOCK_GATING_DISABLE

SPRITE_C_PSR_CLOCK_GATING_DISABLE

DISPLAY_GAMMA_CORRECTION_A_PSR_CLOCK_GATING_DISABLE
DISPLAY_GAMMA_CORRECTION_B_PSR_CLOCK_GATING_DISABLE

DISPLAYPORT_DPTUNIT_PSR_CLOCK_GATING_DISABLE
LOW_POWER_SINGLE_PIPE_B_LPSSA_CLOCK_GATING_DISABLE

DISPLAY_GCI_PSR_CLOCK_GATING_DISABLE

VRHUNIT_PSR_CLOCK_GATING_DISABLE
RESERVED

SPRITE_B_PSR_CLOCK_GATING_DISABLE

Bay Trail-I SoC

362 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

0b LOW_POWER_SINGLE_PIPE_A_LPSSA_CLOCK_GATING_DISABLE: 0 = clock
31 gating controlled by enabling logic. Pipe A shall be enabled 1 = Disable trunk clock
RW gating on pipe A even when LPSSA is on

0b LOW_POWER_SINGLE_PIPE_B_LPSSA_CLOCK_GATING_DISABLE: 0 = clock
30 gating controlled by enabling logic. Pipe B shall be enabled 1 = Disable trunk clock
RW gating on pipe B even when LPSSA is on
0b
29:26 RESERVED: Reserved.
RW

0b DPIO_CLOCK_BUFFER_ENABLE_CLOCK_GATING_DISABLE: 0 = clock gating

25 controlled by DPIO clock buffer enable 1=Disable clock gating function by DPIO clock
RW buffer enable
0b DISPLAY_PLANE_A_PSR_CLOCK_GATING_DISABLE: 0 = Clock gating controlled
24
RW by unit enabling logic 1 = Disable clock gating function

0b DISPLAY_PLANE_B_PSR_CLOCK_GATING_DISABLE: 0 = Clock gating controlled

23
RW by unit enabling logic 1 = Disable clock gating function

0b SPRITE_A_PSR_CLOCK_GATING_DISABLE: 0 = Clock gating controlled by unit

22
RW enabling logic 1 = Disable clock gating function

0b SPRITE_B_PSR_CLOCK_GATING_DISABLE: 0 = Clock gating controlled by unit

21
RW enabling logic 1 = Disable clock gating function

0b SPRITE_C_PSR_CLOCK_GATING_DISABLE: 0 = Clock gating controlled by unit

20
RW enabling logic 1 = Disable clock gating function

0b SPRITE_D_PSR_CLOCK_GATING_DISABLE: 0 = Clock gating controlled by unit

19
RW enabling logic 1 = Disable clock gating function

0b CURSOR_A_PSR_CLOCK_GATING_DISABLE: 0 = Clock gating controlled by unit

18
RW enabling logic 1 = Disable clock gating function

0b CURSOR_B_PSR_CLOCK_GATING_DISABLE: 0 = Clock gating controlled by unit

17
RW enabling logic 1 = Disable clock gating function

0b DISPLAY_BLENDER_A_PSR_CLOCK_GATING_DISABLE: 0 = Clock gating

16
RW controlled by unit enabling logic 1 = Disable clock gating function

0b DISPLAY_BLENDER_B_PSR_CLOCK_GATING_DISABLE: 0 = Clock gating

15
RW controlled by unit enabling logic 1 = Disable clock gating function

0b DISPLAY_GAMMA_CORRECTION_A_PSR_CLOCK_GATING_DISABLE: 0 = Clock
14
RW gating controlled by unit enabling logic 1 = Disable clock gating function

0b DISPLAY_GAMMA_CORRECTION_B_PSR_CLOCK_GATING_DISABLE: 0 = Clock
13
RW gating controlled by unit enabling logic 1 = Disable clock gating function

0b DISPLAY_GCI_PSR_CLOCK_GATING_DISABLE: 0 = Clock gating controlled by unit

12
RW enabling logic 1 = Disable clock gating function

0b AUDFUNIT_PSR_CLOCK_GATING_DISABLE: 0 = Clock gating controlled by unit

11
RW enabling logic 1 = Disable clock gating function(default)

0b AUDBUNIT_PSR_CLOCK_GATING_DISABLE: 0 = Clock gating controlled by unit

10
RW enabling logic 1 = Disable clock gating function

1b CPDUNIT_PSR_CLOCK_GATING_DISABLE: 0 = Clock gating controlled by unit

9
RW enabling logic 1 = Disable clock gating function (default)

0b DDBMUNIT_PSR_CLOCK_GATING_DISABLE: 0 = Clock gating controlled by unit

8
RW enabling logic 1 = Disable clock gating function

0b DPFUNIT_PSR_CLOCK_GATING_DISABLE: 0 = Clock gating controlled by unit

7
RW enabling logic 1 = Disable clock gating function

Bay Trail-I SoC

Datasheet 363
 Graphics, Video and Display

Bit Default &

Description
Range Access

0b DPIOUNIT_PSR_CLOCK_GATING_DISABLE: 0 = Clock gating controlled by unit

6
RW enabling logic 1 = Disable clock gating function

0b DISPLAYPORT_DPTUNIT_PSR_CLOCK_GATING_DISABLE: 0 = Clock gating

5
RW controlled by unit enabling logic 1 = Disable clock gating function

0b DPOUNIT_PSR_CLOCK_GATING_DISABLE: 0 = Clock gating controlled by unit

4
RW enabling logic 1 = Disable clock gating function

0b HDCPUNIT_PSR_CLOCK_GATING_DISABLE: 0 = Clock gating controlled by unit

3
RW enabling logic 1 = Disable clock gating function

0b VRDUNIT_PSR_CLOCK_GATING_DISABLE: 0 = Clock gating controlled by unit

2
RW enabling logic 1 = Disable clock gating function

0b VRHUNIT_PSR_CLOCK_GATING_DISABLE: 0 = Clock gating controlled by unit

1
RW enabling logic 1 = Disable clock gating function

0b DISPLAY_FUSE_WRAPPER_PSR_CLOCK_GATING_DISABLE: 0 = Clock gating

0
RW controlled by unit enabling logic 1 = Disable clock gating function

14.10.37 RAMCLK_GATE_D—Offset 6210h

GFX RAM Clock Gating Disable Register ([DevBLC, DevCTG, DevCDV, DevCL]) memory
clock gating (cpdmmreg.v gfxramcg2)

Access Method
Type: Memory Mapped I/O Register
RAMCLK_GATE_D: [GTTMMADR_LSB + 2BF20h] + 6210h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
AUDM_UNIT_RAM_CLOCK_GATING_DISABLE

DISPLAY_DATA_BUFFER1_RAM_CLOCK_GATING_DISABLE
HDCP_UNIT_RAM_CLOCK_GATING_DISABLE
CURSOR_DATA_BUFFER_RAM_CLOCK_GATING_DISABLE

DPTUNIT_RAM_CLOCK_GATING_DISABLE
PANEL_FITTER_RAM_CLOCK_GATING_DISABLE

RESERVED_25
RESERVED

RESERVED_1

RESERVED_2
RESERVED_3
RESERVED_4
RESERVED_5
RESERVED_6
RESERVED_7
RESERVED_8
RESERVED_9
RESERVED_10
RESERVED_11
RESERVED_12
RESERVED_13
RESERVED_14
RESERVED_15
RESERVED_16
RESERVED_17
RESERVED_18
RESERVED_19
RESERVED_20
RESERVED_21
RESERVED_22
RESERVED_23
RESERVED_24

Bay Trail-I SoC

364 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

0b RESERVED: [DevCDV] TVOUT RAM Clock Gating Disable: 0 = Enable RAM bank clock
31
RW gating function (default) 1 = Disable RAM bank clock gating function

0b PANEL_FITTER_RAM_CLOCK_GATING_DISABLE: 0 = Enable RAM bank clock

30
RW gating function (default) 1 = Disable RAM bank clock gating function

0b CURSOR_DATA_BUFFER_RAM_CLOCK_GATING_DISABLE: 0 = Enable RAM bank

29
RW clock gating function (default) 1 = Disable RAM bank clock gating function

0b AUDM_UNIT_RAM_CLOCK_GATING_DISABLE: [DevCTG, DevCDV] [DeBLC]

28 Reserved. [DevCL] WIZ Z coeff readback return FIFO Clock Gating Disable: 0 = Enable
RW RAM bank clock gating function (default) 1 = Disable RAM bank clock gating function

0b RESERVED_1: [DevCDV] [DevCTG] DPFC Unit RAM Clock Gating Disable: [DevBLC]
27 Reserved. [DevCL] Display Data Buffer2 (Overlay) Gating Disable: 0 = Enable RAM bank
RW clock gating function (default) 1 = Disable RAM bank clock gating function
0b DISPLAY_DATA_BUFFER1_RAM_CLOCK_GATING_DISABLE: 0 = Enable RAM
26
RW bank clock gating function (default) 1 = Disable RAM bank clock gating function

0b HDCP_UNIT_RAM_CLOCK_GATING_DISABLE: [DevBLC, DevCTG, DevCDV]

25 [DevCL] ME RAM Clock Gating Disable: 0 = Enable RAM bank clock gating function
RW (default) 1 = Disable RAM bank clock gating function
DPTUNIT_RAM_CLOCK_GATING_DISABLE: [DevVLVP] [DevCTG, DevCDV] DPIOM
0b Unit RAM Clock Gating Disable: [DevBLC] Reserved. [DevCL] WIZ polygon FIFO RAM
24
RW Clock Gating Disable: 0 = Enable RAM bank clock gating function (default) 1 = Disable
RAM bank clock gating function

0b RESERVED_2: [DevCDV] [DevBLC] and [DevCTG] Reserved. [DevCL] VF RAM Clock

23 Gating Disable: 0 = Enable RAM bank clock gating function (default) 1 = Disable RAM
RW bank clock gating function

0b RESERVED_3: [DevCDV] [DevBLC] and [DevCTG] Reserved. [DevCL] SF RAMClock

22 Gating Disable: 0 = Enable RAM bank clock gating function (default) 1 = Disable RAM
RW bank clock gating function

0b RESERVED_4: [DevCDV] [DevBLC] and [DevCTG] Reserved. [DevCL] WMIZ Latency

21 FIFO Clock Gating Disable: 0 = Enable RAM bank clock gating function (default) 1 =
RW Disable RAM bank clock gating function

0b RESERVED_5: [DevCDV] [DevBLC] and [DevCTG] Reserved. [DevCL] TC FIFO Clock

20 Gating Disable: 0 = Enable RAM bank clock gating function (default) 1 = Disable RAM
RW bank clock gating function

0b RESERVED_6: [DevBLC, DevCTG, DevCDV] [DevCL] SV FIFO Clock Gating Disable: 0 =

19 Enable RAM bank clock gating function (default) 1 = Disable RAM bank clock gating
RW function

0b RESERVED_7: [DevCDV] [DevBLC] and [DevCTG] BD Unit RAM Clock Gating Disable:
18 [DevCL] Latency FIFO Clock Gating Disable: 0 = Enable RAM bank clock gating function
RW (default) 1 = Disable RAM bank clock gating function

0b RESERVED_8: [DevCDV] [DevBLC] and [DevCTG] BF Unit RAM Clock Gating Disable:
17 [DevCL] URB Clock Gating Disable: 0 = Enable RAM bank clock gating function (default)
RW 1 = Disable RAM bank clock gating function

0b RESERVED_9: [DevCDV] [DevBLC] and [DevCTG] CS Unit RAM Clock Gating Disable:
16 [DevCL] L2 Instruction Tag RAM Clock Gating Disable: 0 = Enable RAM bank clock
RW gating function (default) 1 = Disable RAM bank clock gating function

0b RESERVED_10: [DevBLC, DevCDV] [DevCTG] FH Unit RAM Clock Gating Disable:

15 [DevCL] Data RAM Clock Gating Disable: 0 = Enable RAM bank clock gating function
RW (default) 1 = Disable RAM bank clock gating function

0b RESERVED_11: [DevCDV] [DevBLC] and [DevCTG] Reserved. [DevCL] TAG RAM Clock
14 Gating Disable: 0 = Enable RAM bank clock gating function (default) 1 = Disable RAM
RW bank clock gating function

0b RESERVED_12: [DevCDV] [DevBLC] and [DevCTG] Reserved. [DevCL] L2 Instruction

13 Cache Clock Gating Disable: 0 = Enable RAM bank clock gating function (default) 1 =
RW Disable RAM bank clock gating function

Bay Trail-I SoC

Datasheet 365
 Graphics, Video and Display

Bit Default &

Description
Range Access

0b RESERVED_13: [DevCDV] [DevBLC] and [DevCTG] Reserved. [DevCL] MRFRAM Clock

12 Gating Disable: 0 = Enable RAM bank clock gating function (default) 1 = Disable RAM
RW bank clock gating function

0b RESERVED_14: [DevCDV] [DevBLC] and [DevCTG] VFM Unit RAM Clock Gating
11 Disable: [DevCL] GRF RAM Clock Gating Disable: 0 = Enable RAM bank clock gating
RW function (default) 1 = Disable RAM bank clock gating function

0b RESERVED_15: [DevCDV] [DevBLC] and [DevCTG] SFM Unit RAM Clock Gating
10 Disable: [DevCL] Data Cache CAM Clock Gating Disable: 0 = Enable RAM bank clock
RW gating function (default) 1 = Disable RAM bank clock gating function

0b RESERVED_16: [DevCDV] [DevBLC] and [DevCTG] WIZM Unit RAM Clock Gating
9 Disable: [DevCL] Data Cache Gating Disable: 0 = Enable RAM bank clock gating
RW function (default) 1 = Disable RAM bank clock gating function

0b RESERVED_17: [DevCDV] [DevBLC] and [DevCTG] URB Unit RAM Clock Gating
8 Disable: [DevCL] Render Cache Latency FIFO Clock Gating Disable: 0 = Enable RAM
RW bank clock gating function (default) 1 = Disable RAM bank clock gating function

0b RESERVED_18: [DevCDV] [DevBLC] and [DevCTG] IC Unit RAM Clock Gating Disable:
7 [DevCL] Render PA Tag RAM (Z) Clock Gating Disable: 0 = Enable RAM bank clock
RW gating function (default) 1 = Disable RAM bank clock gating function

0b RESERVED_19: [DevCDV] [DevBLC] and [DevCTG] ISC Unit RAM Clock Gating
6 Disable: [DevCL] Render PA Tag RAM (Color) Clock Gating Disable: 0 = Enable RAM
RW bank clock gating function (default) 1 = Disable RAM bank clock gating function

0b RESERVED_20: [DevCDV] [DevBLC] and [DevCTG] GA Unit RAM Clock Gating Disable:
5 [DevCL] Render Cache Write Back FIFO Clock Gating Disable: 0 = Enable RAM bank
RW clock gating function (default) 1 = Disable RAM bank clock gating function

0b RESERVED_21: [DevCDV] [DevBLC] and [DevCTG] MS Unit RAM Clock Gating Disable:
4 [DevCL] Render Cache (Z) Clock Gating Disable: 0 = Enable RAM bank clock gating
RW function (default) 1 = Disable RAM bank clock gating function

0b RESERVED_22: [DevCDV] [DevBLC] and [DevCTG] RCBP Unit RAM Clock Gating
3 Disable: [DevCL] Render Cache (color) Clock Gating Disable: 0 = Enable RAM bank
RW clock gating function (default) 1 = Disable RAM bank clock gating function

0b RESERVED_23: [DevCDV] [DevBLC] and [DevCTG] RCC Unit RAM Clock Gating
2 Disable: [DevCL] L2 Mapping Cache CAM Clock Gating Disable: 0 = Enable RAM bank
RW clock gating function (default) 1 = Disable RAM bank clock gating function

0b RESERVED_24: [DevCDV] [DevBLC] and [DevCTG] RCZ Unit RAM Clock Gating
1 Disable: [DevCL] L2 Mapping Tag RAM Clock Gating Disable: 0 = Enable RAM bank clock
RW gating function (default) 1 = Disable RAM bank clock gating function

0b RESERVED_25: [DevCDV] [DevBLC] and [DevCTG] MT Unit RAM Clock Gating Disable:
0 [DevCL] L2 Mapping Cache Clock Gating Disable: 0 = Enable RAM bank clock gating
RW function (default) 1 = Disable RAM bank clock gating function

14.10.38 FW_BLC_SELF—Offset 6500h

Display FIFO Watermark

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) FW_BLC_SELF: [GTTMMADR_LSB + 2BF20h] + 6500h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

366 Datasheet
Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESERVED

CSPWRDWNEN

RESERVED_1
Bit Default &
Description
Range Access

0b
31:16 RESERVED: Reserved.
RW

0b CSPWRDWNEN: 1 = Dispaly FIFO can go into max_fifo configuration if only one plane
15 A/B is enabled and all other planes, including overlay, are off. 0 = Dont put display FIFO
RW in max_fifo configuration
0b
14:0 RESERVED_1: Reserved.
RW

14.10.39 MI_ARB—Offset 6504h

Display Arbiter

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) MI_ARB: [GTTMMADR_LSB + 2BF20h] + 6504h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DISPLAY_TRICKLE_FEED_DISABLE
RESERVED

RESERVED_1

Bit Default &

Description
Range Access

0b
31:3 RESERVED: Reserved.
RW

0b DISPLAY_TRICKLE_FEED_DISABLE: 1 Disable (Turn off trickle feed Display

2
RW request). 0 Enable (Default)

Bay Trail-I SoC

Datasheet 367
 Graphics, Video and Display

Bit Default &

Description
Range Access

0b
1:0 RESERVED_1: Reserved.
RW

14.10.40 CZCLK_CDCLK_FREQ_RATIO—Offset 6508h

Display CZCLK/CDCLK FREQ Ratio for RMBUS sync

Access Method
Type: Memory Mapped I/O Register CZCLK_CDCLK_FREQ_RATIO: [GTTMMADR_LSB + 2BF20h] +
(Size: 32 bits) 6508h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000077h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 1 1
RESERVED

DISPLAY_CDCLK_FREQUENCY_ENCODING

CORE_CLOCK_CZCLK_FREQUENCY_ENCODING

Bit Default &

Description
Range Access

0b
31:9 RESERVED: Reserved.
RO

Bay Trail-I SoC

368 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

DISPLAY_CDCLK_FREQUENCY_ENCODING: DISPLAY CDCLK FREQUENCY

ENCODING (* symbol frequencies are POR)
|_____________________________________________________________________
________________________________________________________| |=====CDCLK
FREQ.======|===CDCLK DEVIDE RATIO===|==CD REGISTER
ENCODING==|===SKU200==|===SKU266====|====SKU333===|====CD===
===|
|=====ENCODING=========|========================|=======(
DECIMAL)========|===VCO 800=|===VCO 1600==|====VCO
2000=|===QUAL GEN=|
|======================|========================|======
==================|====(MHz)==|===(MHz)=====|=====(MHz)===|
====RATIO===|
|_____________________________________________________________________
________________________________________________________|
|======5'b00001========|===========1============|=========
==1============|=====800===|====1600=====|====2000=====|==
====1=====|
|_____________________________________________________________________
________________________________________________________|
|======5'b00010========|=========1.5============|=========
==2============|=====533===|====1067=====|====1333=====|==
====2=====|
|_____________________________________________________________________
________________________________________________________|
|======5'b00011========|===========2============|=========
==3============|=====400===|=====800=====|====1000=====|==
====3=====|
|_____________________________________________________________________
________________________________________________________|
|======5'b00100========|=========2.5============|=========
==4============|=====320*==|=====640=====|=====800=====|==
====4=====|
|_____________________________________________________________________
________________________________________________________|
|======5'b00101========|===========3============|=========
==5============|=====267*==|=====533=====|=====667=====|==
====5=====|
|_____________________________________________________________________
________________________________________________________|
|======5'b00111========|===========4============|=========
==6============|=====200*==|=====400=====|=====500=====|==
====7=====|
|_____________________________________________________________________
________________________________________________________|
|======5'b01000========|=========4.5============|=========
00111b ==7============|=====178===|=====356=====|=====444=====|==
8:4 ====8=====|
RO |_____________________________________________________________________
________________________________________________________|
|======5'b01001========|===========5============|=========
==9============|=====160===|=====320*====|=====400=====|==
====9=====|
|_____________________________________________________________________
________________________________________________________|
|======5'b01011========|===========6============|=========
=11============|=====133===|=====267*====|=====300*====|==
===11=====|
|_____________________________________________________________________
________________________________________________________|
|======5'b01110========|=========7.5============|=========
=14============|=====107===|=====213=====|=====267*====|==
===14=====|
|_____________________________________________________________________
________________________________________________________|
|======5'b01111========|===========8============|=========
=15============|=====100===|=====200*====|=====250=====|==
===15=====|
|_____________________________________________________________________
________________________________________________________|
|======5'b10001========|===========9============|=========
=17============|======89===|=====178=====|=====222=====|==
===17=====|
Bay Trail-I SoC |_____________________________________________________________________
Datasheet ________________________________________________________| 369
|======5'b10011========|==========10============|=========
=19============|======80===|=====160=====|=====200*====|==
===19=====|
|_____________________________________________________________________
________________________________________________________|
|======5'b10111========|==========12============|=========
 Graphics, Video and Display

Bit Default &

Description
Range Access

CORE_CLOCK_CZCLK_FREQUENCY_ENCODING: CORE CLOCK (CZCLK) FREQUENCY

ENCODING (* synbol are POR freq for each SKU)
|_____________________________________________________________________
________________________________________________________| |=====CZCLK
FREQ.======|===CZCLK DEVIDE RATIO===|==CZ REGISTER
ENCODING==|===SKU200==|===SKU266====|====SKU333===|====CZ===
===|
|=====ENCODING=========|========================|=======(
DECIMAL)========|===VCO 800=|===VCO 1600==|====VCO
2000=|===QUAL GEN=|
|======================|========================|======
==================|====(MHz)==|===(MHz)=====|=====(MHz)===|
====RATIO===|
|_____________________________________________________________________
________________________________________________________|
|======5'b00001========|===========1============|=========
==1============|=====800===|====1600=====|====2000=====|==
====1=====|
|_____________________________________________________________________
________________________________________________________|
|======5'b00010========|=========1.5============|=========
==2============|=====533===|====1067=====|====1333=====|==
====2=====|
|_____________________________________________________________________
________________________________________________________|
|======5'b00011========|===========2============|=========
==3============|=====400===|=====800=====|====1000=====|==
====3=====|
|_____________________________________________________________________
________________________________________________________|
|======5'b00100========|=========2.5============|=========
==4============|=====320===|=====640=====|=====800=====|==
====4=====|
|_____________________________________________________________________
0111b ________________________________________________________|
3:0
RO |======5'b00101========|===========3============|=========
==5============|=====267===|=====533=====|=====667=====|==
====5=====|
|_____________________________________________________________________
________________________________________________________|
|======5'b00111========|===========4============|=========
==6============|=====200*==|=====400=====|=====500=====|==
====7=====|
|_____________________________________________________________________
________________________________________________________|
|======5'b01000========|=========4.5============|=========
==7============|=====178===|=====356=====|=====444=====|==
====8=====|
|_____________________________________________________________________
________________________________________________________|
|======5'b01001========|===========5============|=========
==9============|=====160===|=====320=====|=====400=====|==
====9=====|
|_____________________________________________________________________
________________________________________________________|
|======5'b01011========|===========6============|=========
=11============|=====133===|=====267*====|=====333*====|==
===11=====|
|_____________________________________________________________________
________________________________________________________|
|======5'b01110========|=========7.5============|=========
=14============|=====107===|=====213=====|=====267=====|==
===14=====|
|_____________________________________________________________________
________________________________________________________|
|======5'b01111========|===========8============|=========
=15============|=====100===|=====200*====|=====250=====|==
===15=====|
|_____________________________________________________________________
________________________________________________________|

Bay Trail-I SoC

370 Datasheet
Graphics, Video and Display

14.10.41 GCI_CONTROL—Offset 650Ch

GCI Control Register.

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) GCI_CONTROL: [GTTMMADR_LSB + 2BF20h] + 650Ch

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00004000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
AES_CLK_GATING_DISABLE
PFI_CREDIT_INFO_TO_BE_SENT_TO_PONDICHERRY_PFI

FORCE_AES_SESSION_KEYS_RESEND_TO_AES_BLOCK
FORCE_PFI_CREDIT_RESEND_TO_SSA

RESERVED_1

AES_DECRYPTION_BYPASS_ENABLE

HP_ARBITRATION_MODE
RESERVED

VGA_FAST_MODE_DISABLE

REQUEST_LATENCY_OVERRIDE

REQUEST_LATENCY_OVERRIDE_ENABLE
Bit Default &
Description
Range Access

PFI_CREDIT_INFO_TO_BE_SENT_TO_PONDICHERRY_PFI: Others = reserved

0b 0111 = 15 credits 0110 = 14 credits 0101 = 13 credits 0100 = 12 credits 0011 = 11
31:28 credits 0010 = 10 credits 0001 = 9 credits 0000 = 8 credits available to PND (default)
RW Based on the czclk/cdclk ratio, display driver has to determine the appropriate PFI
credits to be used
FORCE PFI CREDIT RESEND TO SSA (FORCE_PFI_CREDIT_RESEND_TO_SSA): 0
= Disable PFI credit to resend to SSA. Hardware is responsible to clear this bit after the
0b PFI credit initialization request is sent. 1 = Enable PFI credit to resend to SSA. When
27
RW driver sets this bit, Display PFI request engine will resend the new PFI credit bit [31:28]
to SSA. Hardware is responsible to clear this bit after the PFI credit initialization request
is sent.
0b
26:25 RESERVED: Reserved.
RW
0b AES_CLK_GATING_DISABLE: 0 = Enable clock gating for AES clock (default) 1 =
24
RW Disable clock gating for AES clock

0b
23:15 RESERVED_1: Reserved.
RW

Bay Trail-I SoC

Datasheet 371
 Graphics, Video and Display

Bit Default &

Description
Range Access

VGA_FAST_MODE_DISABLE: 0 = Fast Mode enabled. The Gfx mem arbiter can

accept a vga display read request every clock. Note that the HP Address
1b (G_HP_CONTROL[28:24]) and ID (G_HP_CONTROL[21:16]) FIFO depths must be set to
14
RW a value greater than 1 when Fast Mode is enabled. 1 = Fast Mode disabled. (default) The
Gfx mem arbiter can accept a vga display read request every other clock Programming
note: VGA FAST MODE is not supported in VLVP.
REQUEST_LATENCY_OVERRIDE: If bit 3 of this register is set, the 10-btt Request
Latency Override value programmed here is used as the latency offset from the global
timer for requests that win arbitration. If bit 3 is not set, normal request latency from
0b streamers is used. Programming note: This value should not be larger than the actual
13:4
RW required request latency. Otherwise, it will cause underrun. The guidline is to use
latency corresponds to low watermark level or even smaller. When this field is used, the
actual request latency is defeatured, either zero or a small value is used but still not
causing underrun.

0b REQUEST_LATENCY_OVERRIDE_ENABLE: 1 = Request Latency Override values in

3 bit[13:4] is used as the latency offset from global timer 0 = Request Latency Override
RW values is disabled. Normal request latency from streamer is used. (default)

0b AES_DECRYPTION_BYPASS_ENABLE: 0 = AES decryption engine is enabled

2
RW (Default) 1 = AES decryption engine is bypassed

FORCE_AES_SESSION_KEYS_RESEND_TO_AES_BLOCK: 0 = Disable sending AES

session keys to AES when going from Panel Self Refresh (PSR) inactive to PSR active
0b mode (Default). Hardware is responsible to clear this bit after this bit is set to resend
1 the session keys. 1 = Enable sending AES session keys to AES engine when going from
RW PSR inactive to PSR active mode. When driver sets this bit, PAVP engine will resend the
session keys to AES engine. Hardware is responsible to clear this bit after the session
keys are sent.
0b HP_ARBITRATION_MODE: 0 = Select hierarchical arbiter 1 = Select backup round
0
RW robin arbiter

14.10.42 GMBUSFREQ—Offset 6510h

GMBUS frequency binary encoding GMBUS Frequency Binary Encoding Register.

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) GMBUSFREQ: [GTTMMADR_LSB + 2BF20h] + 6510h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 000000A0h

Bay Trail-I SoC

372 Datasheet
Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0

RESERVED_

CMBUS_CDCLK_FREQUENCY_CDFREQ
Bit Default &
Description
Range Access

0b
31:10 RESERVED_: Reserved.
RW

001010000 CMBUS_CDCLK_FREQUENCY_CDFREQ: Programmng note: bit[9:2] should be

0b programmed to the number of cdclk that generates 4MHz reference clock freq which is
9:0
used to generate GMBus clock. This will vary with the cdclk freq. Programming note: For
RW hot plug detect on exact 100ms as long pulse, driver shall program [9:0] = cdclk_1.01

14.10.43 DPALETTE_A—Offset A000h

Pipe A Display Palette

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) DPALETTE_A: [GTTMMADR_LSB + 2BF20h] + A000h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PIPE_A_RED_PALETTE_ENTRY

PIPE_A_GREEN_PALETTE_ENTRY
RESERVED

PIPE_A_BLUE_PALETTE_ENTRY

Bay Trail-I SoC

Datasheet 373
 Graphics, Video and Display

Bit Default &

Description
Range Access

0b
31:24 RESERVED: (read only).
RW
0b
23:16 PIPE_A_RED_PALETTE_ENTRY: 8-bit entries per red color channel in the palette
RW
0b PIPE_A_GREEN_PALETTE_ENTRY: 8-bit entries per green color channel in the
15:8
RW palette

0b
7:0 PIPE_A_BLUE_PALETTE_ENTRY: 8-bit entries per blue color channel in the palette
RW

14.10.44 DPALETTE_B—Offset A800h

Pipe B Display Palette

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) DPALETTE_B: [GTTMMADR_LSB + 2BF20h] + A800h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PIPE_B_RED_PALETTE_ENTRY
RESERVED

PIPE_B_GREEN_PALETTE_ENTRY

PIPE_B_BLUE_PALETTE_ENTRY

Bit Default &

Description
Range Access

0b
31:24 RESERVED: Read Only.
RW
0b
23:16 PIPE_B_RED_PALETTE_ENTRY: 8-bit entries per red color channel in the palette
RW
0b PIPE_B_GREEN_PALETTE_ENTRY: 8-bit entries per green color channel in the
15:8
RW palette

0b
7:0 PIPE_B_BLUE_PALETTE_ENTRY: 8-bit entries per blue color channel in the palette
RW

14.10.45 MIPIA_DEVICE_READY_REG—Offset B000h

MIPI A Device Ready Register

Bay Trail-I SoC

374 Datasheet
Graphics, Video and Display

Access Method
Type: Memory Mapped I/O Register MIPIA_DEVICE_READY_REG: [GTTMMADR_LSB + 2BF20h] +
(Size: 32 bits) B000h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BUS_POSSESSION

DEVICE_READY_
RESERVED

ULPS_STATE
Bit Default &
Description
Range Access

0b
31:4 RESERVED: Reserved.
RW
0b
3 BUS_POSSESSION: BUS possession for mipiA
RW
0b
2:1 ULPS_STATE: ULPS state for mipi pipe A
RW
0b
0 DEVICE_READY_: Set by the processor to inform that device is ready
RW

14.10.46 MIPIA_INTR_STAT_REG—Offset B004h

interrupt stat reg for mipi pipe A

Access Method
Type: Memory Mapped I/O Register MIPIA_INTR_STAT_REG: [GTTMMADR_LSB + 2BF20h] + B004h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

Datasheet 375
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RXHS_RECEIVE_TIMEOUT_ERROR
GEN_READ_DATA_AVAIL
LP_GENERIC_WR_FIFO_FULL

RXDSI_VC_ID_INVALID
HS_GENERIC_WR_FIFO_FULL

TXDSI_VC_ID_INVALID
TXDSI_DATA_TYPE_NOT_RECOGNISED

RX_LP_TX_SYNC_ERROR
TEARING_EFFECT

ACK_WITH_NO_ERROR
TURN_AROUND_ACK_TIMEOUT
LP_RX_TIMEOUT

TXCHECKSUM_ERROR

TXECC_SINGLE_BIT_ERROR
TXFALSE_CONTROL_ERROR

RXDSI_DATA_TYPE_NOT_RECOGNISED

RXECC_SINGLE_BIT_ERROR
RXFALSE_CONTROL_ERROR

RXESCAPE_MODE_ENTRY_ERROR
RXEOTSYNCERROR
RXSOTSYNCERROR
RXSOTERROR
SPL_PKT_SENT_INTERRUPT

RX_INVALID_TX_LENGTH

HS_TX_TIMEOUT
DPI_FIFO_UNDERRUN

TXECC_MULTIBIT_ERROR

RXCHECKSUM_ERROR
RXECC_MULTIBIT_ERROR
RX_PROT_VIOLATION

LOW_CONTENTION
Bit Default & HIGH_CONTENTION
Description
Range Access

0b
31 TEARING_EFFECT: Set to indicate that tearing effect trigger message is Received
RW

0b SPL_PKT_SENT_INTERRUPT: Set to confirm the transmission of the DPI event

30
RW specific commands set in the dpi control and dpi data register

0b GEN_READ_DATA_AVAIL: Set to indicate that the requested data for a Generic Read
29 request is available in the buffer i.e., generic read response data is available in the read
RW FIFO

0b
28 LP_GENERIC_WR_FIFO_FULL: Set to indicate that the LP generic write fifo is full
RW

0b
27 HS_GENERIC_WR_FIFO_FULL: Set to indicate that the HS generic write fifo is full
RW

0b RX_PROT_VIOLATION: Set if DSI protocol violation error is reported in the

26
RW acknowledge packet by the display device

0b RX_INVALID_TX_LENGTH: Set if invalid transmission length error is reported in the

25
RW acknowledge packet by the display device

0b ACK_WITH_NO_ERROR: Set if acknowledge trigger message is received with out any

24
RW error

0b TURN_AROUND_ACK_TIMEOUT: Set if a turn around acknowledgement sequence is

23
RW not received from the display device

0b LP_RX_TIMEOUT: Set if a low power reception count expires this interrupt is

22
RW generated

0b HS_TX_TIMEOUT: Set if a high speed transmission prevails for more than the
21
RW expected count value this interrupt is raised

0b DPI_FIFO_UNDERRUN: Set to '1' if there is no data in the dpi fifo to make a in time
20
RW delivery of the pixel data to the DSI receiver

0b LOW_CONTENTION: Set to '1' if a LP low fault is registered by at the D-PHY

19
RW contention detector

0b HIGH_CONTENTION: Set to '1' if a LP high fault is registered by at the D-PHY

18
RW contention detector

0b
17 TXDSI_VC_ID_INVALID: Set to '1' if the received virtual channel ID is invalid
RW

Bay Trail-I SoC

376 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

0b TXDSI_DATA_TYPE_NOT_RECOGNISED: Set to '1' if the received data type is not

16
RW recognised

0b TXCHECKSUM_ERROR: Set to '1' if the computed CRC differs from the received CRC
15
RW value during the reception of packets by Arasan_DSI host.

0b TXECC_MULTIBIT_ERROR: Set to '1' if there is no ECC correction for the packet or

14
RW there are more than 2 bit errors in the packet received by Arasan_DSI_host

0b TXECC_SINGLE_BIT_ERROR: Set to '1' if ECC syndrome was computed and is

13
RW corrected for one bit error during the reception of packets by the Arasan_DSI_host

0b TXFALSE_CONTROL_ERROR: Set to '1' if a control error is observed on the lanes by

12
RW the Arasan_DSI_host

0b RXDSI_VC_ID_INVALID: Set to '1' if the virtual channel ID is invalid by the display

11
RW device is reported in the Acknowledge packet by the display device

0b RXDSI_DATA_TYPE_NOT_RECOGNISED: Set to '1' if the data type is not recognised

10
RW by the display device is reported in the Acknowledge packet by the display device

0b RXCHECKSUM_ERROR: Set to '1' if the computed CRC differs from the received CRC
9
RW value and is reported in the Acknowledge packet by the display device

0b RXECC_MULTIBIT_ERROR: Set to '1' if there is no ECC correction for the packet or

8 there are more than 2 bit errors in the packet is reported in the Acknowledge packet by
RW the display device
0b RXECC_SINGLE_BIT_ERROR: Set to '1' if ECC syndrome was computed and
7
RW corrected for one bit error is reported in the Acknowledge packet by the display device

0b RXFALSE_CONTROL_ERROR: Set to '1' if a control error is reported in the

6
RW Acknowledge packet by the display device

0b RXHS_RECEIVE_TIMEOUT_ERROR: Set to '1' if the high speed receive timer value

5 expires and data transfer lasts on the data lane is reported in the Acknowledge packet
RW by the display device
0b RX_LP_TX_SYNC_ERROR: Set to '1' if Low power transmission sync error occurs in
4
RW the display device and is reported in the Acknowledge packet by the display device

0b RXESCAPE_MODE_ENTRY_ERROR: Set to '1' if Escape Mode Entry command is not

3 understandable by the display device and is reported in the Acknowledge packet by the
RW display device
0b
2 RXEOTSYNCERROR: RX eot sync Error
RW
0b RXSOTSYNCERROR: Set to '1' if a start of transmission synchronisation error is
1
RW reported in the Acknowledge packet by the display device

0b RXSOTERROR: Set to '1' if a start of transmission error is reported in the Acknowledge

0
RW packet by the display device

14.10.47 MIPIA_INTR_EN_REG—Offset B008h

mipi pipe A interrupt enable register

Access Method
Type: Memory Mapped I/O Register MIPIA_INTR_EN_REG: [GTTMMADR_LSB + 2BF20h] + B008h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Bay Trail-I SoC

Datasheet 377
 Graphics, Video and Display

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RXHS_RECEIVE_TIMEOUT_ERROR
GEN_READ_DATA_AVAIL

TXDSI_VC_ID_INVALID
TXDSI_DATA_TYPE_NOT_RECOGNISED

RXDSI_VC_ID_INVALID

RX_LP_TX_SYNC_ERROR

RXSOTSYNC_ERROR
TXCHECKSUM_ERROR
RESERVED

TXFALSE_CONTROL_ERROR

RXDSI_DATA_TYPE_NOT_RECOGNISED
SPL_PKT_SENT_INTERRUPT

LP_GENERIC_WR_FIFO_FULL
HS_GENERIC_WR_FIFO_FULL

ACK_WITH_NO_ERROR
TURN_AROUND_ACK_TIMEOUT
LP_RX_TIMEOUT

TXECC_SINGLE_BIT_ERROR

RXECC_SINGLE_BIT_ERROR
RXFALSE_CONTROL_ERROR

RXESCAPE_MODE_ENTRY_ERROR
RXEOTSYNC_ERROR

RXSOT_ERROR
RX_INVALID_TX_LENGTH

HS_TX_TIMEOUT
DPI_FIFO_UNDERRUN

TXECC_MULTIBIT_ERROR

RXCHECKSUM_ERROR
RXECC_MULTIBIT_ERROR
RX_PROT_VIOLATION

LOW_CONTENTION
HIGH_CONTENTION
Bit Default &
Description
Range Access

0b
31 TEARING_EFFECT (RESERVED): set to enable tearing effect interrupt.
RW

0b SPL_PKT_SENT_INTERRUPT: Set to enable the confirmation of transmission of the

30
RW DPI event specific commands set in the dpi control and dpi data register

0b
29 GEN_READ_DATA_AVAIL: Set to enable Generic Read available interrupt
RW

0b
28 LP_GENERIC_WR_FIFO_FULL: Set to indicate that the LP generic write fifo is full
RW

0b
27 HS_GENERIC_WR_FIFO_FULL: Set to indicate that the HS generic write fifo is full
RW

0b
26 RX_PROT_VIOLATION: Set to enable protocol violation error
RW

0b
25 RX_INVALID_TX_LENGTH: Set to enable invalid transmission length error
RW
0b ACK_WITH_NO_ERROR: Set to enable acknowledge trigger message reception with
24
RW out any error

0b TURN_AROUND_ACK_TIMEOUT: Set to enable turn around acknowledgement

23
RW ,sequence timeout

0b
22 LP_RX_TIMEOUT: Set to enable low power reception count timeouts
RW
0b
21 HS_TX_TIMEOUT: Set to enable a high speed transmission timeout
RW
0b DPI_FIFO_UNDERRUN: Set to enable if there is no data in the dpi fifo to make a in
20
RW time delivery of the pixel data to the DSI receiver

0b
19 LOW_CONTENTION: Set to enable a LP low fault interrupt
RW
0b
18 HIGH_CONTENTION: Set to enable a LP high fault interrupt
RW
0b TXDSI_VC_ID_INVALID: Set to enable the interrupt if the received packets virtual
17
RW channel ID is invalid

Bay Trail-I SoC

378 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

0b TXDSI_DATA_TYPE_NOT_RECOGNISED: Set to enable the interrupt if the received

16
RW packets data type is not recognised

0b TXCHECKSUM_ERROR: Set to enable the interrupt if the computed CRC differs from
15
RW the received CRC value for the received packets

0b TXECC_MULTIBIT_ERROR: Set to enable the interrupt if there is no ECC correction

14 for the packet or there are more than 2 bit errors in the packet received by Arasan DSI
RW host

0b TXECC_SINGLE_BIT_ERROR: Set to enable the interrupt if ECC syndrome was

13 computed and is corrected for one bit error during the reception of packets by the
RW Arasan DSIhost
0b TXFALSE_CONTROL_ERROR: Set to enable the interrupt for the control
12
RW error.,observed on the lanes by the Arasan_DSI_host

0b RXDSI_VC_ID_INVALID: Set to enable the interrupt for invalid virtual channel ID in

11
RW the acknowledgment packet reports

0b RXDSI_DATA_TYPE_NOT_RECOGNISED: Set to enable the interrupt for the un

10
RW recognised data type in the acknowledgment packet reports

0b RXCHECKSUM_ERROR: Set to enable the interrupt for the computed CRC differs from
9
RW the received CRC value in the acknowledgment packet reports

0b RXECC_MULTIBIT_ERROR: Set to enable the interrupt for no ECC correction for the
8
RW packet or there are more than 2 bit errors reported in the acknowledgment packet

0b RXECC_SINGLE_BIT_ERROR: Set to enable the interrupt for ECC syndrome

7
RW computation and one bit error correction for the acknowledgment packet

0b RXFALSE_CONTROL_ERROR: Set to enable the interrupt for control error in the

6
RW acknowledgment packet reports

0b RXHS_RECEIVE_TIMEOUT_ERROR: Set to enable the interrupt for the high speed

5
RW receive timeout Error in the acknowledgment packet reports

0b RX_LP_TX_SYNC_ERROR: Set to enable the interrupt for Low power transmission

4
RW sync error in the acknowledgment packet reports

0b RXESCAPE_MODE_ENTRY_ERROR: Set to enable the interrupt for Escape Mode

3
RW Entry command error in the acknowledgment packet reports

0b RXEOTSYNC_ERROR: Set to enable the interrupt for End of transmission

2
RW synchronisation Error in the acknowledgement packet reports

0b RXSOTSYNC_ERROR: Set to enable the interrupt for start of transmission

1
RW synchronisation error in the acknowledgement packet reports

0b RXSOT_ERROR: Set to enable the interrupt for start of transmission error in the
0
RW acknowledgment packet reports

14.10.48 MIPIA_DSI_FUNC_PRG__REG—Offset B00Ch

mipi pipe A dsi function program register

Access Method
Type: Memory Mapped I/O Register MIPIA_DSI_FUNC_PRG__REG: [GTTMMADR_LSB + 2BF20h] +
(Size: 32 bits) B00Ch

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000001h

Bay Trail-I SoC

Datasheet 379
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

SUPPORTED_DATA_WIDTH_IN_COMMAND_MODE

CHANNEL_NUMBER_FOR_VIDEO_MODE
RESERVED

CHANNEL_NUMBER_FOR_COMMAND_MODE

DATA_LANES_PRG_R_EG
RESERVED_1

SUPPORTED_FORMAT_IN_VIDEO_MODE
Bit Default &
Description
Range Access

0b
31:16 RESERVED: Reserved.
RW

0b SUPPORTED_DATA_WIDTH_IN_COMMAND_MODE: 000 --) Reserved, 001 --) 16

15:13 bit data , 010 --) 9 bit data , 011 --) 8 bit data , 100 --) option 1 : 101 --) option 2 : 110
RW to 111 --) Reserved

0b
12:11 RESERVED_1: Reserved.
RW

0b SUPPORTED_FORMAT_IN_VIDEO_MODE: Supported colour format, 0001 --)

10:7
RW RGB565, 0010 --) RGB666, 0011 --) RGB 666 loosely packed format, 0100 --) RGB888

0b CHANNEL_NUMBER_FOR_COMMAND_MODE: Virtual channel number for command

6:5
RW mode is programmed by the processor

0b CHANNEL_NUMBER_FOR_VIDEO_MODE: Virtual channel number for command

4:3
RW mode is programmed by the processor

001b DATA_LANES_PRG_R_EG: Number of data lanes to be supported is programmed by

2:0
RW the processor

14.10.49 MIPIA_HS_TX_TIMEOUT_REG—Offset B010h

mipi piepe A HS TX timout register

Access Method
Type: Memory Mapped I/O Register MIPIA_HS_TX_TIMEOUT_REG: [GTTMMADR_LSB + 2BF20h] +
(Size: 32 bits) B010h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

380 Datasheet
Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

HIGH_SPEED_TX_TIMEOUT_COUNTER
RESERVED

Bit Default &

Description
Range Access

0b
31:24 RESERVED: Reserved.
RW

0b HIGH_SPEED_TX_TIMEOUT_COUNTER: The maximum duration allowed for the DSI

23:0 host ,to remain in high speed mode for a transmission. If the counter expires, HS mode
RW is terminated with EOT and the lanes enter stop state

14.10.50 MIPIA_LP_RX_TIMEOUT_REG—Offset B014h

mipi pipe A LP RX timeout register

Access Method
Type: Memory Mapped I/O Register MIPIA_LP_RX_TIMEOUT_REG: [GTTMMADR_LSB + 2BF20h] +
(Size: 32 bits) B014h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

Datasheet 381
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

LOW_POWER_RECEPTION_TIMEOUT_COUNTER
RESERVED

Bit Default &

Description
Range Access

0b
31:24 RESERVED: Reserved.
RW
0b LOW_POWER_RECEPTION_TIMEOUT_COUNTER: Timeout value to be checked for
23:0
RW received short packets .If the timer expires the DSI Host enters stop state

14.10.51 MIPIA_TURN_AROUND_TIMEOUT_REG—Offset B018h

mipi pipe A turn around timeout register

Access Method
Type: Memory Mapped I/O Register MIPIA_TURN_AROUND_TIMEOUT_REG: [GTTMMADR_LSB +
(Size: 32 bits) 2BF20h] + B018h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

382 Datasheet
Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESERVED

TURN_AROUND_TIMEOUT_REGISTER
Bit Default &
Description
Range Access

0b
31:6 RESERVED: Reserved.
RW

0b TURN_AROUND_TIMEOUT_REGISTER: Timeout value to be checked after the DSI

5:0 host makes a turn around in the direction of transfers. If the timer expires the DSI Host
RW enters stop state

14.10.52 MIPIA_DEVICE_RESET_TIMER—Offset B01Ch

mipi pipe A device reset timer

Access Method
Type: Memory Mapped I/O Register MIPIA_DEVICE_RESET_TIMER: [GTTMMADR_LSB + 2BF20h] +
(Size: 32 bits) B01Ch

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DEVICE_RESET_TIMER
RESERVED

Bit Default &

Description
Range Access

0b
31:16 RESERVED: Reserved.
RW

Bay Trail-I SoC

Datasheet 383
 Graphics, Video and Display

Bit Default &

Description
Range Access

0b DEVICE_RESET_TIMER: Timeout value to be checked for device to be reset after

15:0
RW issuing reset entry command. If the timer expires the DSI Host enters normal operation

14.10.53 MIPIA_DPI_RESOLUTION_REG—Offset B020h

mipi piepe A DPI Resolution reg

Access Method
Type: Memory Mapped I/O Register MIPIA_DPI_RESOLUTION_REG: [GTTMMADR_LSB + 2BF20h]
(Size: 32 bits) + B020h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VERTICAL_ADDRESS

HORIZONTAL_ADDRESS
Bit Default &
Description
Range Access

0b
31:16 VERTICAL_ADDRESS: Shows the vertical address count in lines
RW

0b
15:0 HORIZONTAL_ADDRESS: Shows the horizontal address count in pixels
RW

14.10.54 MIPIA_DBI_RESOLUTION_REG—Offset B024h

mipi A DBI resolution reg

Access Method
Type: Memory Mapped I/O Register MIPIA_DBI_RESOLUTION_REG: [GTTMMADR_LSB + 2BF20h]
(Size: 32 bits) + B024h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

384 Datasheet
Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESERVED

DBI_FIFO_THRTL
Bit Default &
Description
Range Access

0b
31:2 RESERVED: Reserved.
RW

0b DBI_FIFO_THRTL: DBI FIFO's watermark can be set using the following bits so as to
1:0 enable dbi_stall de-assertion whenever the below FIFO condition is reached: 00 - (1/2)
RW DBI fifo empty 01 - (1/4) DBI fifo empty 10 - 7 locations are empty 11 - Reserved

14.10.55 MIPIA_HORIZ_SYNC_PADDING_COUNT—Offset B028h

mipi A horizontal sync padding out

Access Method
Type: Memory Mapped I/O Register MIPIA_HORIZ_SYNC_PADDING_COUNT: [GTTMMADR_LSB +
(Size: 32 bits) 2BF20h] + B028h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED

HORIZONTAL_SYNC_PADDING_COUNT

Bit Default &

Description
Range Access

0b
31:16 RESERVED: Reserved.
RW

0b HORIZONTAL_SYNC_PADDING_COUNT: Shows the horizontal sync padding value in

15:0
RW terms of txbyteclkhs

Bay Trail-I SoC

Datasheet 385
 Graphics, Video and Display

14.10.56 MIPIA_HORIZ_BACK_PORCH_COUNT—Offset B02Ch

mipi pipe A horizontal back porch counter

Access Method
Type: Memory Mapped I/O Register MIPIA_HORIZ_BACK_PORCH_COUNT: [GTTMMADR_LSB +
(Size: 32 bits) 2BF20h] + B02Ch

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED

HORIZONTAL_BACK_PORCH_COUNT
Bit Default &
Description
Range Access

0b
31:16 RESERVED: Reserved.
RW
0b HORIZONTAL_BACK_PORCH_COUNT: Shows the horizontal back porch value in
15:0
RW terms of txbyteclkhs

14.10.57 MIPIA_HORIZ_FRONT_PORCH_COUNT—Offset B030h

mipi pipe A horizontal front porch counter

Access Method
Type: Memory Mapped I/O Register MIPIA_HORIZ_FRONT_PORCH_COUNT: [GTTMMADR_LSB +
(Size: 32 bits) 2BF20h] + B030h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

386 Datasheet
Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESERVED

HORIZONTAL_FRONT_PORCH_COUNT
Bit Default &
Description
Range Access

0b
31:16 RESERVED: Reserved.
RW
0b HORIZONTAL_FRONT_PORCH_COUNT: Shows the horizontal front porch value in
15:0
RW terms of txbyteclkhs

14.10.58 MIPIA_HORIZ_ACTIVE_AREA_COUNT—Offset B034h

mipi A horizontal active area counter

Access Method
Type: Memory Mapped I/O Register MIPIA_HORIZ_ACTIVE_AREA_COUNT: [GTTMMADR_LSB +
(Size: 32 bits) 2BF20h] + B034h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED

HORIZONTAL_ACTIVE_AREA_COUNT

Bay Trail-I SoC

Datasheet 387
 Graphics, Video and Display

Bit Default &

Description
Range Access

0b
31:16 RESERVED: Reserved.
RW
0b HORIZONTAL_ACTIVE_AREA_COUNT: Shows the horizontal active area value in
15:0
RW terms of txbyteclkhs

14.10.59 MIPIA_VERT_SYNC_PADDING_COUNT—Offset B038h

mipi pipe A vertical sync padding counter

Access Method
Type: Memory Mapped I/O Register MIPIA_VERT_SYNC_PADDING_COUNT: [GTTMMADR_LSB +
(Size: 32 bits) 2BF20h] + B038h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED

VERTICAL_SYNC_PADDING_COUNT

Bit Default &

Description
Range Access

0b
31:16 RESERVED: Reserved.
RW
0b VERTICAL_SYNC_PADDING_COUNT: Shows the vertical sync padding value in terms
15:0
RW of lines

14.10.60 MIPIA_VERT_BACK_PORCH_COUNT—Offset B03Ch

mipi pipe A vertical back portch counter

Access Method
Type: Memory Mapped I/O Register MIPIA_VERT_BACK_PORCH_COUNT: [GTTMMADR_LSB +
(Size: 32 bits) 2BF20h] + B03Ch

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Bay Trail-I SoC

388 Datasheet
Graphics, Video and Display

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESERVED

VERTICAL_BACK_PORCH_COUNT
Bit Default &
Description
Range Access

0b
31:16 RESERVED: Reserved.
RW

0b VERTICAL_BACK_PORCH_COUNT: Shows the vertical back porch value in terms of

15:0
RW lines

14.10.61 MIPIA_VERT_FRONT_PORCH_COUNT—Offset B040h

mipi pipe A vertical front portch counter

Access Method
Type: Memory Mapped I/O Register MIPIA_VERT_FRONT_PORCH_COUNT: [GTTMMADR_LSB +
(Size: 32 bits) 2BF20h] + B040h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VERTICAL_FRONT_PORCH_COUNT
RESERVED

Bay Trail-I SoC

Datasheet 389
 Graphics, Video and Display

Bit Default &

Description
Range Access

0b
31:16 RESERVED: Reserved.
RW
0b VERTICAL_FRONT_PORCH_COUNT: Shows the vertical front porch value in terms of
15:0
RW lines

14.10.62 MIPIA_HIGH_LOW_SWITCH_COUNT—Offset B044h

mipi A high low switch count

Access Method
Type: Memory Mapped I/O Register MIPIA_HIGH_LOW_SWITCH_COUNT: [GTTMMADR_LSB +
(Size: 32 bits) 2BF20h] + B044h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED

HIGH_SPEED_TO_LOW_POWER_OR_LOW_POWER_TO_HIGH_SPEED_SWITCH_COUNT

Bay Trail-I SoC

390 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

0b RESERVED: High speed to low power or Low power to high speed switching time in
31:16
RW terms of txbyteclkhs

0b HIGH_SPEED_TO_LOW_POWER_OR_LOW_POWER_TO_HIGH_SPEED_SWITCH
15:0 _COUNT: High speed to low power or Low power to high speed switching time in terms
RW of txbyteclkhs

14.10.63 MIPIA_DPI_CTRL_REG—Offset B048h

mipi A dpi ctrl register

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) MIPIA_DPI_CTRL_REG: [GTTMMADR_LSB + 2BF20h] + B048h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

HS_LP
BACK_LIGHT_OFF

SHUT_DOWN
RSTTRG

BACK_LIGHT_ON
COLOR_MODE_OFF
COLOR_MODE_ON
TURN_ON
RESERVED

Bit Default &

Description
Range Access

0b
31:8 RESERVED:
RW

0b
7 RSTTRG: mipi A dpi ctrl reg RSTTRG
RW

0b HS_LP: Set to '0' to indicate the special packets are sent through the DSI link using HS
6 transmission and set to '1' to indicate that the special packets are sent through the DSI
RW link using low power mode

0b BACK_LIGHT_OFF: Set to '1' to indicate a backlight OFF short packet has to be

5
RW packetised for the DPI's virtual channel

0b BACK_LIGHT_ON: Set to '1' to indicate a backlight ON short packet has to be

4
RW packetised for the DPI's virtual channel

0b COLOR_MODE_OFF: Set to '1' to indicate a color mode OFF short packet has to be
3
RW packetised for the DPI's virtual channel

0b COLOR_MODE_ON: Set to '1' to indicate a color mode ON short packet has to be

2
RW packetised for the DPI's virtual channel

0b TURN_ON: Set to '1' to indicate a turn on short packet has to be packetised for the
1
RW DPI's virtual channel

0b SHUT_DOWN: Set to '1' to indicate a shut down short packet has to be packetised for
0
RW the DPI's virtual channel

Bay Trail-I SoC

Datasheet 391
 Graphics, Video and Display

14.10.64 MIPIA_DPI_DATA_REGISTER—Offset B04Ch

mipi A dpi data register

Access Method
Type: Memory Mapped I/O Register MIPIA_DPI_DATA_REGISTER: [GTTMMADR_LSB + 2BF20h] +
(Size: 32 bits) B04Ch

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESERVED

COMMAND_BYTE
Bit Default &
Description
Range Access

0b
31:6 RESERVED: Reserved.
RW
COMMAND_BYTE: Command Byte to represent the new or not defined command bytes
0b usage for special features representation. [Like backlight ON and OFF]. This register
5:0
RW should be programmed before the DPI control register is being programmed for
backlight ON/OFF

14.10.65 MIPIA_INIT_COUNT_REGISTER—Offset B050h

mipi A init count register

Access Method
Type: Memory Mapped I/O Register MIPIA_INIT_COUNT_REGISTER: [GTTMMADR_LSB + 2BF20h]
(Size: 32 bits) + B050h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MASTER_INIT_TIMER
RESERVED

Bay Trail-I SoC

392 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

0b
31:16 RESERVED: Reserved.
RW
0b MASTER_INIT_TIMER: Counter value in terms of low power clock to initialise the DSI
15:0
RW Host IP [ TINT] that drives a stop state on the mipi's D-PHY bus

14.10.66 MIPIA_MAX_RETURN_PKT_SIZE_REGISTER—Offset B054h

mipi A max resturn pkt size register

Access Method
Type: Memory Mapped I/O Register MIPIA_MAX_RETURN_PKT_SIZE_REGISTER:
(Size: 32 bits) [GTTMMADR_LSB + 2BF20h] + B054h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED

MAX_RETURN_PKT_SIZE
Bit Default &
Description
Range Access

0b
31:10 RESERVED: Reserved.
RW
0b MAX_RETURN_PKT_SIZE: Set the count value in bytes to collect the return data
9:0
RW packet for reverse direction data flow in data lane0 in response to a DBI read operation

14.10.67 MIPIA_VIDEO_MODE_FORMAT_REGISTER—Offset B058h

mipi A video mode format register

Access Method
Type: Memory Mapped I/O Register MIPIA_VIDEO_MODE_FORMAT_REGISTER: [GTTMMADR_LSB
(Size: 32 bits) + 2BF20h] + B058h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

Datasheet 393
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RANDOM_DPI_DISPLAY_RESOLUTION_DEFEATURE

VIDEO_MODE_FMT
RESERVED

MIPIA_DISABLE_VIDEO_BTA
IP_TG_CONFIG
Bit Default &
Description
Range Access

0b
31:5 RESERVED: Reserved.
RW

0b RANDOM_DPI_DISPLAY_RESOLUTION_DEFEATURE: Set by the processor to

4 support random DPI display resolution 0 - random DPI display resolution support
RW disabled. 1 - random DPI display resolution support enabled.
MIPIA_DISABLE_VIDEO_BTA: Set by the processor to inform the DSI controller to
0b disable the BTA sent at the last blanking line of VFP. By default, this bit is set to 0.0 BTA
3
RW sending at the last blanking line of VFP is enabled. 1 BTA sentding at teh last blanking
line of VFP is disabeld.
IP_TG_CONFIG: Set by the processor to inform that the DSI controller should
discontinue the DPI transfer after the last line of the VFP after ip_tg_enable deassertion.
0b By default, this bit is set to 0. 0 - After ip_tg_enable deassertion, DSI Tx controller stops
2
RW the DPI transfer immediately after the current packet is transmitted. 1 - After
ip_tg_enable deassertion, DSI Tx controller discontinues the DPI transfer after the last
line of the VFP

VIDEO_MODE_FMT: Sets the Video mode format (packet sequence) to be supported

in DSI. In Non Burst Mode, in addition to programming this register the horizontal active
area count register value should also be programmed equal to RGB word count value In
0b Burst Mode, in addition to programming this register the horizontal active area count
1:0
RW register value should also be programmed greater than the RGB word count value,
leaving more time during a scan line for LP mode (saving power) or for multiplexing
other transmissions onto the DSI link. 00 Reserved 01 - Non Burst Mode with Sync Pulse
10 - Non Burst Mode with Sync events 11 - Burst Mode

14.10.68 MIPIA_EOT_DISABLE_REGISTER—Offset B05Ch

mipi A eot disable register

Access Method
Type: Memory Mapped I/O Register MIPIA_EOT_DISABLE_REGISTER: [GTTMMADR_LSB +
(Size: 32 bits) 2BF20h] + B05Ch

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Bay Trail-I SoC

394 Datasheet
Graphics, Video and Display

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

LOW_CONTENTION_RECOVERY_DISABLE
RESERVED

HS_TX_TIMEOUT_ERROR_RECOVERY_DISABLE

EOT_DIS
LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE

CLOCKSTOP
HIGH_CONTENTION_RECOVERY_DISABLE
TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE
TXECC_MULTIBIT_ERR_RECOVERY_DISABLE
Bit Default &
Description
Range Access

0b
31:8 RESERVED: Reserved.
RW

LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE: Set by the processor to enable or

disable the LP_Rx_timeout error recovery if the processor clears LP_Rx_timeout error
0b interrupt. 0 - LP_Rx_timeout error recovery action will be taken by the DSI Tx controller
7
RW if the processor clears the LP_Rx_timeout error interrupt. 1 - If the processor clears the
LP_Rx_timeout error interrupt, LP_Rx_timeout error recovery action will not happen in
DSI Tx contorller. LP Rx timeout error interrupt will act as an informative interrupt
HS_TX_TIMEOUT_ERROR_RECOVERY_DISABLE: Set by the processor to enable or
disable the HS_Tx_timeout error recovery if the processor clears HS_Tx_timeout
0b interrupt. 0 - HS_Tx_timeout error recovery action will be taken by the DSI Tx controller
6
RW if the processor clears the HS_Tx_timeout error interrupt. 1 - If the processor clears the
HS_Tx_timeout error interrupt, HS_Tx_timeout error recovery action will not happen in
DSI Tx contorller. HS Tx timeout error interrupt will act as an informative interrupt
LOW_CONTENTION_RECOVERY_DISABLE: Set by the processor to enable or
disable the contention recovery procedure if the processor clears Low contention
0b interrupt. 0 - Contention recovery will happen if the processor clears Low contention
5
RW interrupt. 1 - If the processor clears the low contention interrupt, contention recovery
procedure will not be initiated by the DSI Tx contorller. Low contention interrupt will act
as an informative interrupt
HIGH_CONTENTION_RECOVERY_DISABLE: Set by the processor to enable or
disable the contention recovery procedure if the processor clears High contention
0b interrupt. 0 - Contention recovery will happen if the processor clears High contention
4
RW interrupt. 1 - If the processor clears the high contention interrupt, contention recovery
procedure will not be initiated by the DSI Tx contorller. Ignore the High Contention
Interrupt in MIPI_INTR_STAT_REG

Bay Trail-I SoC

Datasheet 395
 Graphics, Video and Display

Bit Default &

Description
Range Access

TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE: Set by the

processor to enable or disable the error recovery action to be taken by the DSI Tx
0b controller if TxDSI data type not recognised error interrupt is cleared by the processor. 0
3 - Error recovery action will be taken if TxDSI data type not recognised error interrupt is
RW cleared by the processor. 1 - If TxDSI data type not recognised error interrupt is cleared
by the processor, error recovery action will not be taken by the DSI TX controller. Tx DSI
data type not recognized error interrupt will act as an informative interrupt
TXECC_MULTIBIT_ERR_RECOVERY_DISABLE: Set by the processor to enable or
disable the error recovery action to be taken by the DSI Tx controller if Tx ECC multibit
0b error interrupt is cleared by the processor. 0 - Error recovery action will be taken if Tx
2
RW ECC multibit error interrupt is cleared by the processor. 1 - If Tx ECC multibit error
interrupt is cleared by the processor, error recovery action will not be taken by the DSI
TX controller. Tx multibit error interrupt will act as an informative interrupt
CLOCKSTOP: Set by the processor to enable or disable clock stopping feature during
0b BLLP timing in a DPI transfer in dual channel mode or during DPI only mode and also
1
RW when there is no traffic in the DBI interface in DBI only enabled mode. By default this
register value is 0. 0 - clock stopping disabled 1 - clock stopping enabled

EOT_DIS: Set by the processor to enable or disable EOT short packet transmission. By
0b default this register value is 0. For backward comapatibility of earlier DSI systems, EOT
0
RW short packet transmission can be disabled. 0 - EOT short packet transmission enabled 1
- EOT short packet transmission disabled

14.10.69 MIPIA_LP_BYTECLK_REGISTER—Offset B060h

mipi A LP bytclk register

Access Method
Type: Memory Mapped I/O Register MIPIA_LP_BYTECLK_REGISTER: [GTTMMADR_LSB + 2BF20h]
(Size: 32 bits) + B060h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
LP_BYTECLK
RESERVED

Bit Default &

Description
Range Access

0b
31:16 RESERVED: Reserved.
RW

LP_BYTECLK: Low power clock equivalence in terms of byte clock. The value
0b programmed in this register is equal to the number of byte clocks occupied in one low
15:0
RW power clock. This value is based on the byte clock (txbyteclkhs) and low power clock
frequency (txclkesc)

14.10.70 MIPIA_LP_GEN_DATA_REGISTER—Offset B064h

mipi A LP gen DATA register

Bay Trail-I SoC

396 Datasheet
Graphics, Video and Display

Access Method
Type: Memory Mapped I/O Register MIPIA_LP_GEN_DATA_REGISTER: [GTTMMADR_LSB +
(Size: 32 bits) 2BF20h] + B064h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

LP_GEN_DATA
Bit Default &
Description
Range Access

0b
31:0 LP_GEN_DATA: Data port register used for generic data transfers in low power mode
RW

14.10.71 MIPIA_HS_GEN_DATA_REGISTER—Offset B068h

mipi A HS GEN data register

Access Method
Type: Memory Mapped I/O Register MIPIA_HS_GEN_DATA_REGISTER: [GTTMMADR_LSB +
(Size: 32 bits) 2BF20h] + B068h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HS_GEN_DATA

Bit Default &

Description
Range Access

0b
31:0 HS_GEN_DATA: Data port register used for generic data transfers in low power mode
RW

14.10.72 MIPIA_LP_GEN_CTRL_REGISTER—Offset B06Ch

mipi A LP Gen CTRL register

Access Method

Bay Trail-I SoC

Datasheet 397
 Graphics, Video and Display

Type: Memory Mapped I/O Register MIPIA_LP_GEN_CTRL_REGISTER: [GTTMMADR_LSB +

(Size: 32 bits) 2BF20h] + B06Ch

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

VIRTUAL_CHANNEL

DATA_TYPE
WORD_COUNT
RESERVED

Bit Default &

Description
Range Access

0b
31:24 RESERVED: Reserved.
WO

0b WORD_COUNT: Specifies the word count for generic long packet Specifies the
23:8 accompanied parameters for generic short packets. Note: Invalid parameters must be
WO set to 00h

0b VIRTUAL_CHANNEL: Used to specify the virtual channel for which the generic data
7:6
WO transmission is intended

DATA_TYPE: Used to specify the generic data types 03h - Generic short write, no
parameters 13h - Generic short write, 1 parameter 23h - Generic short write, 2
0b parameters 04h - Generic read, no parameters 14h - Generic read, 1 parameter 24h -
5:0
WO Generic read 2 parameter 29h - Generic long write 05h - Manufacturer DCS short write,
no parameter 15h - Manufacturer DCS short write , one parameter 06h - Manufacturer
DCS read, no parameter 39h - Manufacturer DCS long write

14.10.73 MIPIA_HS_GEN_CTRL_REGISTER—Offset B070h

mipi A HS GEN CTRL register

Access Method
Type: Memory Mapped I/O Register MIPIA_HS_GEN_CTRL_REGISTER: [GTTMMADR_LSB +
(Size: 32 bits) 2BF20h] + B070h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VIRTUAL_CHANNEL
RESERVED

WORD_COUNT

DATA_TYPE

Bay Trail-I SoC

398 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

0b
31:24 RESERVED: Reserved.
WO

0b WORD_COUNT: Specifies the word count for generic long packet Specifies the
23:8 accompanied parameters for generic short packets. Note: Invalid parameters must be
WO set to 00h
0b VIRTUAL_CHANNEL: Used to specify the virtual channel for which the generic data
7:6
WO transmission is intended

DATA_TYPE: Used to specify the generic data types 03h - Generic short write, no
parameters 13h - Generic short write, 1 parameter 23h - Generic short write, 2
0b parameters 04h - Generic read, no parameters 14h - Generic read, 1 parameter 24h -
5:0
WO Generic read 2 parameter 29h - Generic long write 05h - Manufacturer DCS short write,
no parameter 15h - Manufacturer DCS short write, one parameter 06h - Manufacturer
DCS read, no parameter 39h - Manufacturer DCS long write

14.10.74 MIPIA_GEN_FIFO_STAT_REGISTER—Offset B074h

mipi A gen fifo stat register

Access Method
Type: Memory Mapped I/O Register MIPIA_GEN_FIFO_STAT_REGISTER: [GTTMMADR_LSB +
(Size: 32 bits) 2BF20h] + B074h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 1E060606h
31 28 24 20 16 12 8 4 0

0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0
RESERVED

DPI_FIFO_EMPTY
DBI_FIFO_EMPTY
LP_CTRL_FIFO_EMPTY
LP_CTRL_FIFO_HALF_EMPTY

LP_DATA_FIFO_EMPTY
LP_DATA_FIFO_HALF_EMPTY

HS_DATA_FIFO_EMPTY
HS_DATA_FIFO_HALF_EMPTY
HS_CTRL_FIFO_EMPTY
HS_CTRL_FIFO_HALF_EMPTY

HS_DATA_FIFO_FULL
LP_CTRL_FIFO_FULL

LP_DATA_FIFO_FULL
HS_CTRL_FIFO_FULL
RESERVED_1

RESERVED_2

RESERVED_3

Bit Default &

Description
Range Access

0b
31:29 RESERVED: Reserved.
RO

1b
28 DPI_FIFO_EMPTY: Default 1
RO

1b
27 DBI_FIFO_EMPTY: Default 1
RO

1b
26 LP_CTRL_FIFO_EMPTY: Default 1
RO

Bay Trail-I SoC

Datasheet 399
 Graphics, Video and Display

Bit Default &

Description
Range Access

1b
25 LP_CTRL_FIFO_HALF_EMPTY: Default 1
RO
0b
24 LP_CTRL_FIFO_FULL: Default 0
RO
0b
23:19 RESERVED_1: Reserved.
RO
1b
18 HS_CTRL_FIFO_EMPTY: Default 1
RO
1b
17 HS_CTRL_FIFO_HALF_EMPTY: Default 1
RO
0b
16 HS_CTRL_FIFO_FULL: Default 0
RO
0b
15:11 RESERVED_2: Reserved.
RO
1b
10 LP_DATA_FIFO_EMPTY: Default 1
RO
1b
9 LP_DATA_FIFO_HALF_EMPTY: Default 1
RO
0b
8 LP_DATA_FIFO_FULL: Default 0
RO
0b
7:3 RESERVED_3: Reserved.
RO
1b
2 HS_DATA_FIFO_EMPTY: Default 1
RO
1b
1 HS_DATA_FIFO_HALF_EMPTY: Default 1
RO
0b
0 HS_DATA_FIFO_FULL: Default 0
RO

14.10.75 MIPIA_HS_LS_DBI_ENABLE_REG—Offset B078h

Note : dbi_hs_lp_switch_reg has to be written only if DBI FIFO is empty

Access Method
Type: Memory Mapped I/O Register MIPIA_HS_LS_DBI_ENABLE_REG: [GTTMMADR_LSB +
(Size: 32 bits) 2BF20h] + B078h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

400 Datasheet
Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESERVED

DBI_HS_LS_SWITCH_RE
Bit Default &
Description
Range Access

0b
31:1 RESERVED: Reserved.
RW

0b DBI_HS_LS_SWITCH_RE: Set to 1 if DBI packets have to be transmitted in Low

0
RW power mode Set to 0 if DBI packets have to be transmitted in High speed mode

14.10.76 MIPIA_RESERVED—Offset B07Ch

Reserved.

Access Method
Type: Memory Mapped I/O Register MIPIA_RESERVED: [GTTMMADR_LSB + 2BF20h] + B07Ch
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED

Bit Default &

Description
Range Access

0b
31:0 RESERVED: Reserved.
RO

14.10.77 MIPIA_DPHY_PARAM_REG—Offset B080h

mipi A dphy parameter register

Access Method

Bay Trail-I SoC

Datasheet 401
 Graphics, Video and Display

Type: Memory Mapped I/O Register MIPIA_DPHY_PARAM_REG: [GTTMMADR_LSB + 2BF20h] +

(Size: 32 bits) B080h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 0B061A04h
31 28 24 20 16 12 8 4 0

0 0 0 0 1 0 1 1 0 0 0 0 0 1 1 0 0 0 0 1 1 0 1 0 0 0 0 0 0 1 0 0

PREPARE_COUNT
RESERVED_1

RESERVED_2
RESERVED

EXIT_ZERO_COUNT

TRAIL_COUNT

CLK_ZERO_COUNT
Bit Default &
Description
Range Access

0b
31:30 RESERVED: Reserved.
RW
001011b EXIT_ZERO_COUNT: THS_0_TIM_UI_CNT and THS_EXIT_TIM_UI_CNT for dphy are
29:24
RW programmed as exit zero count by the processor

0b
23:21 RESERVED_1: Reserved.
RW
00110b TRAIL_COUNT: TCLK_POST_TIM_UI_CNT and TCLK_TRAIL_TIM_UI_CNT for dphy are
20:16
RW programmed as trail count by the processor

00011010b CLK_ZERO_COUNT: TCLK_0_TIM_UI_CNT for dphy is programmed as clk zero count

15:8
RW by the processor

0b
7:6 RESERVED_2: Reserved.
RW
000100b PREPARE_COUNT: TCLK_PREP_TIM_UI_CNT and THS_PREP_TIM_UI_CNT for dphy are
5:0
RW programmed as prepare count by the processor

14.10.78 MIPIA_DBI_BW_CTRL_REG—Offset B084h

mipi A DBI BW ctrl register

Access Method
Type: Memory Mapped I/O Register MIPIA_DBI_BW_CTRL_REG: [GTTMMADR_LSB + 2BF20h] +
(Size: 32 bits) B084h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

402 Datasheet
Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BANDWIDTH_TIMER
Bit Default &
Description
Range Access

BANDWIDTH_TIMER: DBI Bandwidth control Register. The bandwidth essential for

transmitting 16 long packets containing 252 bytes meant for DCS write memory
0b command is programmed in this register in terms of byte clocks. Based on the DSI
31:0 transfer rate and the number of lanes configured the time taken to transmit 16 long
RW packets in a DSI stream varies. Note: The value programmed in this timer must be
greater than the actual time taken to carryout 16 long packets transmission in DSI
stream plus the time taken to transmit two blanking packets

14.10.79 MIPIA_CLK_LANE_SWITCHING_TIME_CNT—Offset B088h

mipi A clk clane switching time counter

Access Method
Type: Memory Mapped I/O Register MIPIA_CLK_LANE_SWITCHING_TIME_CNT:
(Size: 32 bits) [GTTMMADR_LSB + 2BF20h] + B088h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HS_LS_PWR_SW_CNT
LS_HS_SSW_CNT

Bit Default &

Description
Range Access

LS_HS_SSW_CNT: Low power to high speed switching time in terms byte clock
0b (txbyteclkhs). This value is based on the byte clock (txbyteclkhs) and low power clock
31:16 frequency (txclkesc). Typical value - Number of byte clocks required to switch from low
RW power mode to high speed mode after txrequesths_clk is asserted. Current Value is ah
= 10 txbyteclkhs

HS_LS_PWR_SW_CNT: High speed to low power switching time in terms byte clock
0b (txbyteclkhs). This value is based on the byte clock (txbyteclkhs) and low power clock
15:0 frequency (txclkesc). Typical value - Number of byte clocks request to switch from high
RW speed mode to low power mode after txrequesths_clk is de-asserted. Current Value is
14h = 20 txbyteclkhs

Bay Trail-I SoC

Datasheet 403
 Graphics, Video and Display

14.10.80 MIPIA_STOP_STATE_STALL—Offset B08Ch

mipi A stop state stall

Access Method
Type: Memory Mapped I/O Register MIPIA_STOP_STATE_STALL: [GTTMMADR_LSB + 2BF20h] +
(Size: 32 bits) B08Ch

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESERVED

MIPIA_STOP_STATE_STALL_COUNTER
Bit Default &
Description
Range Access

0b
31:8 RESERVED: reserved
RW
MIPIA_STOP_STATE_STALL_COUNTER: Delay between (stall the stop state signal)
the data transfer is increased based on this counter value. This counter is calculated
from txclkesc. Note: If processor programs this register then it needs to reprogram the
0b high_low_ switch counter in B044h and lp_equivalent_byteclk reg in B060h to
7:0 compensate this delay. High_low_switch_count B044h: High to low switch counter =
RW Actual High to low switch + stop_sta_stall_reg value * Low power clock equivalence
value in terms of byte clock LP equivalent byteclk register B060h: LP equivalent byteclk
value = txclkesc time/ txbyteclk time * (105 + stop_sta_stall_reg value) / 105 Minimum
time of Low Power short packet transfer = 105 txclkesc

14.10.81 MIPIA_INTR_STAT_REG_1—Offset B090h

mipi A interrupt state register 1

Access Method
Type: Memory Mapped I/O Register MIPIA_INTR_STAT_REG_1: [GTTMMADR_LSB + 2BF20h] +
(Size: 32 bits) B090h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

404 Datasheet
Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESERVED

MIPIA_RX_CONNECTION_DETECTED
Bit Default &
Description
Range Access

0b
31:1 RESERVED: reserved
RW

0b MIPIA_RX_CONNECTION_DETECTED: Set to 1'b1 if the contention detected in the

0
RW display device and is reported in the Acknowledge packet by the display device

14.10.82 MIPIA_INTR_EN_REG_1—Offset B094h

mipi A interrupt enable register 1

Access Method
Type: Memory Mapped I/O Register MIPIA_INTR_EN_REG_1: [GTTMMADR_LSB + 2BF20h] +
(Size: 32 bits) B094h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MIPIA_ENABLE_RX_CONNECTION_DETECTED
RESERVED

Bay Trail-I SoC

Datasheet 405
 Graphics, Video and Display

Bit Default &

Description
Range Access

0b
31:1 RESERVED: reserved
RW
0b MIPIA_ENABLE_RX_CONNECTION_DETECTED: Set to enable the interrupt for
0
RW contention detected error in the acknowledgement packet reports

14.10.83 MIPIA_DBI_TYPEC_CTRL—Offset B100h

mipi A Dbit typeC ctrl

Access Method
Type: Memory Mapped I/O Register MIPIA_DBI_TYPEC_CTRL: [GTTMMADR_LSB + 2BF20h] +
(Size: 32 bits) B100h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OVERRIDE
STATUS

FREQ

RESERVED
OPTION
VAL

OVERRIDE_COUNTER
Bit Default &
Description
Range Access

0b VAL: 0= disable DBI TYPE-C interface (default) 1= enable DBI TYPE-C interface Driver
31
RW to make sure that the command and data buffers are cleared before this bit is changed

0b STATUS: command and data buffer empty and link completed sending out all serialized
30
RW data and IDLE 0 = IDLE 1 = work in progress

0b OPTION: TYPE-C option selection 00 option 1 01 option 2 10 option 3 11 no defined

29:28
RW functionality

FREQ: Type-C clock frequency ; A counter based onczclk is used to generate the TYPE-C
0b Clock. So based on the czclk, a frequency close to the specified below will be generated.
27:24
RW Not the exact frequency. ( TBD we may just support a subset frequencies ) 0000 1Mhz
(default) 0001 1Mhz 0010 2Mhz 1111 15Mhz
0b
23:9 RESERVED: Reserved.
RW
0b
8 OVERRIDE: Use override counter value to derive the TYPE-C clock frequency
RW
0b
7:0 OVERRIDE_COUNTER: Override counter value to generate the TYPE-C clock
RW

Bay Trail-I SoC

406 Datasheet
Graphics, Video and Display

14.10.84 MIPIA_CTRL—Offset B104h

MIPI adapter has a control register with options to control width of the dbi bus and the
divide value of the clock that needs to be supplied to the Clocks module so that a 2x
divided clock can be provided to the MIPI D-PHY IP. Self refresh capability is in DCS
commands. The other 3 controls bits (SD, CM and back light control) are now moved to
MIPI IP registers.

Access Method
Type: Memory Mapped I/O Register
MIPIA_CTRL: [GTTMMADR_LSB + 2BF20h] + B104h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0
NAME_BITS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

STATUS
ESCAPE_CLOCK_DIVIDER

RGB_FLIP

MIPI_2X_CLOCK_DIVIDER
Bit Default &
Description
Range Access

0b
31:7 NAME_BITS: Reserved
RW

ESCAPE_CLOCK_DIVIDER: Read Only Escape clock divider select for Pipe A and Pipe
0b C Escape clock is shared by both Pipe A and Pipe C so it cant be set different. 00= 1 X
6:5
RW (20 Mhz) (default) 01= X (10Mhz) 10= X (5Mhz) Changing this register can only be
done when the MIPI device_ready is turned OFF
0b
4:3 STATUS: 2'b00: low priority on read requests to G-unit 2'b11 : high priority
RW
0b RGB_FLIP: 1'b0 : RGB data from disp2d is reverted to BGR 1'b1 : RGB data from
2
RW disp2d is passed as is to MIPI IP

0b
1:0 MIPI_2X_CLOCK_DIVIDER: Reserved
RW

14.10.85 MIPIA_DATA_ADD—Offset B108h

mipi A data ADD

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) MIPIA_DATA_ADD: [GTTMMADR_LSB + 2BF20h] + B108h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Bay Trail-I SoC

Datasheet 407
 Graphics, Video and Display

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DATA_MEM_ADDR

DATA_VALID
DATA_MEM_ADDR_1
Bit Default &
Description
Range Access

0b DATA_MEM_ADDR: When there is updated data for the display panel, S/W programs
31:5
RW this register with the memory address to read from

0b
4:1 DATA_MEM_ADDR_1: Reserved
RW

0b DATA_VALID: This bit is set by S/W when the mem_addr is written and is cleared by
0
RW H/W when done reading the data from memory

14.10.86 MIPIA_DATA_LEN—Offset B10Ch

mipiA data length

Access Method
Type: Memory Mapped I/O Register MIPIA_DATA_LEN: [GTTMMADR_LSB + 2BF20h] + B10Ch
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DATA_LENGTH
RESERVED

Bit Default &

Description
Range Access

0b
31:20 RESERVED: Reserved.
RW

0b DATA_LENGTH: This field shows the remaining length of data that needs to be read
19:0
RW from memory, Initially set by S/W and is decremented by H/W as reads are issued

14.10.87 MIPIA_CMD_ADD—Offset B110h

mipi A cmd ADD

Access Method

Bay Trail-I SoC

408 Datasheet
Graphics, Video and Display

Type: Memory Mapped I/O Register

MIPIA_CMD_ADD: [GTTMMADR_LSB + 2BF20h] + B110h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

COMMAND_MEM_ADDR

COMMAND_DATA_MODE
MIPIA_AUTO_PWG_ENABLE

COMMAND_VALID
RESERVED
Bit Default &
Description
Range Access

0b COMMAND_MEM_ADDR: When there are new commands that need to be sent to the
31:5 display panel, S/W programs this register with the memory address to read the
RW commands from
0b
4:3 RESERVED: MBZ
RW
0b MIPIA_AUTO_PWG_ENABLE: Idle state: SW driver writes to this bit to enable auto
2
RW power gating for MIPIA controller 0: default 1: auto power gate is enabled

0b COMMAND_DATA_MODE: 0: data for memory write command from system buffer

1 that is specified by MIPI data address register 1: data for memory write command from
RW pipe A rendering
0b COMMAND_VALID: This bit is set by S/W when the mem_addr is written and is
0
RW cleared by H/W when done reading the data from memory

14.10.88 MIPIA_CMD_LEN—Offset B114h

mipi A clm length

Access Method
Type: Memory Mapped I/O Register MIPIA_CMD_LEN: [GTTMMADR_LSB + 2BF20h] + B114h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
COMMAND_3

COMMAND_2

COMMAND_1

COMMAND_0

Bay Trail-I SoC

Datasheet 409
 Graphics, Video and Display

Bit Default &

Description
Range Access

0b
31:24 COMMAND_3: This is command 3 length (command + parameters) in bytes
RW
0b
23:16 COMMAND_2: This is command 2 length (command + parameters) in bytes
RW
0b
15:8 COMMAND_1: This is command 1 length (command + parameters) in bytes
RW
0b
7:0 COMMAND_0: This is command 0 length (command + parameters) in bytes
RW

14.10.89 MIPIA_RD_DATA_RETURN0—Offset B118h

In addition to the command and data registers, adapter provides 8 read only registers
for S/W to read the return data from the panel. At this time the usage case for the read
path from the panel is for configuration reads only. Hence, more than 4 bytes of read
are not allowed. Maximum read return size in the MIPI IP should be no greater than 32
bytes.

Access Method
Type: Memory Mapped I/O Register MIPIA_RD_DATA_RETURN0: [GTTMMADR_LSB + 2BF20h] +
(Size: 32 bits) B118h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RD_DATA_RETURN_PANEL

Bit Default &

Description
Range Access

0b
31:0 RD_DATA_RETURN_PANEL: This is the configuration data returned from the panel
RO

14.10.90 MIPIA_RD_DATA_RETURN1—Offset B11Ch

Refer to the description of MIPIA_RD_DATA_RETURN0.

Access Method

Bay Trail-I SoC

410 Datasheet
Graphics, Video and Display

Type: Memory Mapped I/O Register MIPIA_RD_DATA_RETURN1: [GTTMMADR_LSB + 2BF20h] +

(Size: 32 bits) B11Ch

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RD_DATA_RETURN_PANEL
Bit Default &
Description
Range Access

0b
31:0 RD_DATA_RETURN_PANEL: This is the configuration data returned from the panel
RO

14.10.91 MIPIA_RD_DATA_RETURN2—Offset B120h

Refer to the description of MIPIA_RD_DATA_RETURN0.

Access Method
Type: Memory Mapped I/O Register MIPIA_RD_DATA_RETURN2: [GTTMMADR_LSB + 2BF20h] +
(Size: 32 bits) B120h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RD_DATA_RETURN_PANEL

Bit Default &

Description
Range Access

0b
31:0 RD_DATA_RETURN_PANEL: This is the configuration data returned from the panel
RO

Bay Trail-I SoC

Datasheet 411
 Graphics, Video and Display

14.10.92 MIPIA_RD_DATA_RETURN3—Offset B124h

Refer to the description of MIPIA_RD_DATA_RETURN0.

Access Method
Type: Memory Mapped I/O Register MIPIA_RD_DATA_RETURN3: [GTTMMADR_LSB + 2BF20h] +
(Size: 32 bits) B124h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RD_DATA_RETURN_PANEL

Bit Default &

Description
Range Access

0b
31:0 RD_DATA_RETURN_PANEL: This is the configuration data returned from the panel
RO

14.10.93 MIPIA_RD_DATA_RETURN4—Offset B128h

Refer to the description of MIPIA_RD_DATA_RETURN0.

Access Method
Type: Memory Mapped I/O Register MIPIA_RD_DATA_RETURN4: [GTTMMADR_LSB + 2BF20h] +
(Size: 32 bits) B128h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RD_DATA_RETURN_PANEL

Bay Trail-I SoC

412 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

0b
31:0 RD_DATA_RETURN_PANEL: This is the configuration data returned from the panel
RO

14.10.94 MIPIA_RD_DATA_RETURN5—Offset B12Ch

Refer to the description of MIPIA_RD_DATA_RETURN0.

Access Method
Type: Memory Mapped I/O Register MIPIA_RD_DATA_RETURN5: [GTTMMADR_LSB + 2BF20h] +
(Size: 32 bits) B12Ch

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RD_DATA_RETURN_PANEL

Bit Default &

Description
Range Access

0b
31:0 RD_DATA_RETURN_PANEL: This is the configuration data returned from the panel
RO

14.10.95 MIPIA_RD_DATA_RETURN6—Offset B130h

Refer to the description of MIPIA_RD_DATA_RETURN0.

Access Method
Type: Memory Mapped I/O Register MIPIA_RD_DATA_RETURN6: [GTTMMADR_LSB + 2BF20h] +
(Size: 32 bits) B130h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

Datasheet 413
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RD_DATA_RETURN_PANEL
Bit Default &
Description
Range Access

0b
31:0 RD_DATA_RETURN_PANEL: This is the configuration data returned from the panel
RO

14.10.96 MIPIA_RD_DATA_RETURN7—Offset B134h

Refer to the description of MIPIA_RD_DATA_RETURN0.

Access Method
Type: Memory Mapped I/O Register MIPIA_RD_DATA_RETURN7: [GTTMMADR_LSB + 2BF20h] +
(Size: 32 bits) B134h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RD_DATA_RETURN_PANEL

Bit Default &

Description
Range Access

0b
31:0 RD_DATA_RETURN_PANEL: This is the configuration data returned from the panel
RO

14.10.97 MIPIA_RD_DATA_VALID—Offset B138h

Refer to the description of MIPIA_RD_DATA_RETURN1.

Access Method

Bay Trail-I SoC

414 Datasheet
Graphics, Video and Display

Type: Memory Mapped I/O Register MIPIA_RD_DATA_VALID: [GTTMMADR_LSB + 2BF20h] +

(Size: 32 bits) B138h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

READ_DATA_VALID
RESERVED

Bit Default &

Description
Range Access

0b
31:8 RESERVED: Reserved.
RW

READ_DATA_VALID: Each bit corresponds to presence of valid data in the registers

0b above. When data is returned from the panel, H/W will write into these registers in
7:0
RW sequence, and set the corresponding valid bit. When S/W issues a write '1 to the
registers, this bit is cleared

14.10.98 MIPIC_DEVICE_READY_REG—Offset B800h

MIPI C Device Ready Register

Access Method
Type: Memory Mapped I/O Register MIPIC_DEVICE_READY_REG: [GTTMMADR_LSB + 2BF20h] +
(Size: 32 bits) B800h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ULPS_STATE
RESERVED

BUS_POSSESSION

DEVICE_READY_

Bit Default &

Description
Range Access

0b
31:4 RESERVED: Reserved.
RW

Bay Trail-I SoC

Datasheet 415
 Graphics, Video and Display

Bit Default &

Description
Range Access

0b
3 BUS_POSSESSION: mipi C Bus Possession
RW
0b
2:1 ULPS_STATE: mipi C ULPS state
RW
0b
0 DEVICE_READY_: Set by the processor to inform that device is ready
RW

14.10.99 MIPIC_INTR_STAT_REG—Offset B804h

mipi C intrrupt state registr

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) MIPIC_INTR_STAT_REG: [GTTMMADR_LSB + 2BF20h] + B804h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RX_INVALID_TX_LENGTH
SPL_PKT_SENT_INTERRUPT
GEN_READ_DATA_AVAIL

DPI_FIFO_UNDERRUN
LP_GENERIC_WR_FIFO_FULL

LOW_CONTENTION

TXDSI_VC_ID_INVALID

RXDSI_VC_ID_INVALID
HS_GENERIC_WR_FIFO_FULL

TXECC_MULTIBIT_ERROR
RX_PROT_VIOLATION

ACK_WITH_NO_ERROR

HIGH_CONTENTION

TXFALSE_CONTROL_ERROR

RXFALSE_CONTROL_ERROR

RX_LP_TX_SYNC_ERROR
TURN_AROUND_ACK_TIMEOUT
LP_RX_TIMEOUT
HS_TX_TIMEOUT

TXCHECKSUM_ERROR

RXCHECKSUM_ERROR
RXECC_MULTIBIT_ERROR

RXSOTERROR
RXECC_SINGLE_BIT_ERROR

RXHS_RECEIVE_TIMEOUT_ERROR
TEARING_EFFECT

TXECC_SINGLE_BIT_ERROR

RXDSI_DATA_TYPE_NOT_RECOGNISED

RXESCAPE_MODE_ENTRY_ERROR
RXEOTSYNCERROR
RXSOTSYNCERROR
TXDSI_DATA_TYPE_NOT_RECOGNISED

Bit Default &

Description
Range Access

0b
31 TEARING_EFFECT: Set to indicate that tearing effect trigger message is received
RW
0b SPL_PKT_SENT_INTERRUPT: Set to confirm the transmission of the DPI event
30
RW specific commands set in the dpi control and dpi data register

0b GEN_READ_DATA_AVAIL: Set to indicate that the requested data for a Generic Read
29 request is available in the buffer i.e., generic read response data is available in the read
RW FIFO
0b
28 LP_GENERIC_WR_FIFO_FULL: Set to indicate that the LP generic write fifo is full
RW
0b
27 HS_GENERIC_WR_FIFO_FULL: Set to indicate that the HS generic write fifo is full
RW

Bay Trail-I SoC

416 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

0b RX_PROT_VIOLATION: Set if DSI protocol violation error is reported in the

26
RW acknowledge packet by the display device

0b RX_INVALID_TX_LENGTH: Set if invalid transmission length error is reported in the

25
RW acknowledge packet by the display device

0b ACK_WITH_NO_ERROR: Set if acknowledge trigger message is received with out any

24
RW error

0b TURN_AROUND_ACK_TIMEOUT: Set if a turn around acknowledgement sequence is

23
RW not received from the display device

0b LP_RX_TIMEOUT: Set if a low power reception count expires this interrupt is

22
RW generated

0b HS_TX_TIMEOUT: Set if a high speed transmission prevails for more than the
21
RW expected count value this interrupt is raised

0b DPI_FIFO_UNDERRUN: Set to '1' if there is no data in the dpi fifo to make a in time
20
RW delivery of the pixel data to the DSI receiver

0b LOW_CONTENTION: Set to '1' if a LP low fault is registered by at the D-PHY

19
RW contention detector

0b HIGH_CONTENTION: Set to '1' if a LP high fault is registered by at the D-PHY

18
RW contention detector

0b
17 TXDSI_VC_ID_INVALID: Set to '1' if the received virtual channel ID is invalid
RW
0b TXDSI_DATA_TYPE_NOT_RECOGNISED: Set to '1' if the received data type is not
16
RW recognised

0b TXCHECKSUM_ERROR: Set to '1' if the computed CRC differs from the received CRC
15
RW value during the reception of packets by Arasan_DSI host.

0b TXECC_MULTIBIT_ERROR: Set to '1' if there is no ECC correction for the packet or

14
RW there are more than 2 bit errors in the packet received by Arasan_DSI_host

0b TXECC_SINGLE_BIT_ERROR: Set to '1' if ECC syndrome was computed and is

13
RW corrected for one bit error during the reception of packets by the Arasan_DSI_host

0b TXFALSE_CONTROL_ERROR: Set to '1' if a control error is observed on the lanes by

12
RW the Arasan_DSI_host

0b RXDSI_VC_ID_INVALID: Set to '1' if the virtual channel ID is invalid by the display

11
RW device is reported in the Acknowledge packet by the display device

0b RXDSI_DATA_TYPE_NOT_RECOGNISED: Set to '1' if the data type is not recognised

10
RW by the display device is reported in the Acknowledge packet by the display device

0b RXCHECKSUM_ERROR: Set to '1' if the computed CRC differs from the received CRC
9
RW value and is reported in the Acknowledge packet by the display device

0b RXECC_MULTIBIT_ERROR: Set to '1' if there is no ECC correction for the packet or

8 there are more than 2 bit errors in the packet is reported in the Acknowledge packet by
RW the display device
0b RXECC_SINGLE_BIT_ERROR: Set to '1' if ECC syndrome was computed and
7
RW corrected for one bit error is reported in the Acknowledge packet by the display device

0b RXFALSE_CONTROL_ERROR: Set to '1' if a control error is reported in the

6
RW Acknowledge packet by the display device

0b RXHS_RECEIVE_TIMEOUT_ERROR: Set to '1' if the high speed receive timer value

5 expires and data transfer lasts on the data lane is reported in the Acknowledge packet
RW by the display device

Bay Trail-I SoC

Datasheet 417
 Graphics, Video and Display

Bit Default &

Description
Range Access

0b RX_LP_TX_SYNC_ERROR: Set to '1' if Low power transmission sync error occurs in

4
RW the display device and is reported in the Acknowledge packet by the display device

0b RXESCAPE_MODE_ENTRY_ERROR: Set to '1' if Escape Mode Entry command is not

3 understandable by the display device and is reported in the Acknowledge packet by the
RW display device
0b
2 RXEOTSYNCERROR: mipi C RX eot synce error
RW
0b RXSOTSYNCERROR: Set to '1' if a start of transmission synchronisation error is
1
RW reported in the Acknowledge packet by the display device

0b RXSOTERROR: Set to '1' if a start of transmission error is reported in the Acknowledge

0
RW packet by the display device

14.10.100 MIPIC_INTR_EN_REG—Offset B808h

mipi C intrrupt En reg

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) MIPIC_INTR_EN_REG: [GTTMMADR_LSB + 2BF20h] + B808h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GEN_READ_DATA_AVAIL

RX_INVALID_TX_LENGTH
SPL_PKT_SENT_INTERRUPT

DPI_FIFO_UNDERRUN
LP_GENERIC_WR_FIFO_FULL

TXDSI_VC_ID_INVALID
HS_GENERIC_WR_FIFO_FULL

LOW_CONTENTION

TXECC_MULTIBIT_ERROR

RXDSI_VC_ID_INVALID
RX_PROT_VIOLATION

ACK_WITH_NO_ERROR

RXFALSE_CONTROL_ERROR
RXHS_RECEIVE_TIMEOUT_ERROR
RX_LP_TX_SYNC_ERROR

RXSOT_ERROR
RESERVED

TURN_AROUND_ACK_TIMEOUT
LP_RX_TIMEOUT
HS_TX_TIMEOUT

HIGH_CONTENTION

TXDSI_DATA_TYPE_NOT_RECOGNISED
TXCHECKSUM_ERROR

TXFALSE_CONTROL_ERROR
TXECC_SINGLE_BIT_ERROR

RXCHECKSUM_ERROR
RXECC_MULTIBIT_ERROR
RXDSI_DATA_TYPE_NOT_RECOGNISED

RXECC_SINGLE_BIT_ERROR

RXESCAPE_MODE_ENTRY_ERROR
RXEOTSYNC_ERROR
RXSOTSYNC_ERROR

Bit Default &

Description
Range Access

0b
31 TEARING_EFFECT (RESERVED): Set to eanble tearing effect
RW
0b SPL_PKT_SENT_INTERRUPT: Set to enable the confirmation of transmission of the
30
RW DPI event specific commands set in the dpi control and dpi data register

0b
29 GEN_READ_DATA_AVAIL: Set to enable Generic Read available interrupt
RW

Bay Trail-I SoC

418 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

0b
28 LP_GENERIC_WR_FIFO_FULL: Set to indicate that the LP generic write fifo is full
RW
0b
27 HS_GENERIC_WR_FIFO_FULL: Set to indicate that the HS generic write fifo is full
RW
0b
26 RX_PROT_VIOLATION: Set to enable protocol violation error
RW
0b
25 RX_INVALID_TX_LENGTH: Set to enable invalid transmission length error
RW
0b ACK_WITH_NO_ERROR: Set to enable acknowledge trigger message reception with
24
RW out any error

0b TURN_AROUND_ACK_TIMEOUT: Set to enable turn around acknowledgement

23
RW ,sequence timeout

0b
22 LP_RX_TIMEOUT: Set to enable low power reception count timeouts
RW
0b
21 HS_TX_TIMEOUT: Set to enable a high speed transmission timeout
RW
0b DPI_FIFO_UNDERRUN: Set to enable if there is no data in the dpi fifo to make a in
20
RW time delivery of the pixel data to the DSI receiver

0b
19 LOW_CONTENTION: Set to enable a LP low fault interrupt
RW
0b
18 HIGH_CONTENTION: Set to enable a LP high fault interrupt
RW
0b TXDSI_VC_ID_INVALID: Set to enable the interrupt if the received packets virtual
17
RW channel ID is invalid

0b TXDSI_DATA_TYPE_NOT_RECOGNISED: Set to enable the interrupt if the received

16
RW packets data type is not recognised

0b TXCHECKSUM_ERROR: Set to enable the interrupt if the computed CRC differs from
15
RW the received CRC value for the received packets

0b TXECC_MULTIBIT_ERROR: Set to enable the interrupt if there is no ECC correction

14 for the packet or there are more than 2 bit errors in the packet received by Arasan DSI
RW host

0b TXECC_SINGLE_BIT_ERROR: Set to enable the interrupt if ECC syndrome was

13 computed and is corrected for one bit error during the reception of packets by the
RW Arasan DSIhost
0b TXFALSE_CONTROL_ERROR: Set to enable the interrupt for the control
12
RW error.,observed on the lanes by the Arasan_DSI_host

0b RXDSI_VC_ID_INVALID: Set to enable the interrupt for invalid virtual channel ID in

11
RW the acknowledgment packet reports

0b RXDSI_DATA_TYPE_NOT_RECOGNISED: Set to enable the interrupt for the un

10
RW recognised data type in the acknowledgment packet reports

0b RXCHECKSUM_ERROR: Set to enable the interrupt for the computed CRC differs from
9
RW the received CRC value in the acknowledgment packet reports

0b RXECC_MULTIBIT_ERROR: Set to enable the interrupt for no ECC correction for the
8
RW packet or there are more than 2 bit errors reported in the acknowledgment packet

0b RXECC_SINGLE_BIT_ERROR: Set to enable the interrupt for ECC syndrome

7
RW computation and one bit error correction for the acknowledgment packet

Bay Trail-I SoC

Datasheet 419
 Graphics, Video and Display

Bit Default &

Description
Range Access

0b RXFALSE_CONTROL_ERROR: Set to enable the interrupt for control error in the

6
RW acknowledgment packet reports

0b RXHS_RECEIVE_TIMEOUT_ERROR: Set to enable the interrupt for the high speed

5
RW receive timeout Error in the acknowledgment packet reports

0b RX_LP_TX_SYNC_ERROR: Set to enable the interrupt for Low power transmission

4
RW sync error in the acknowledgment packet reports

0b RXESCAPE_MODE_ENTRY_ERROR: Set to enable the interrupt for Escape Mode

3
RW Entry command error in the acknowledgment packet reports

0b RXEOTSYNC_ERROR: Set to enable the interrupt for End of transmission

2
RW synchronisation Error in the acknowledgement packet reports

0b RXSOTSYNC_ERROR: Set to enable the interrupt for start of transmission

1
RW synchronisation error in the acknowledgement packet reports

0b RXSOT_ERROR: Set to enable the interrupt for start of transmission error in the
0
RW acknowledgment packet reports

14.10.101 MIPIC_DSI_FUNC_PRG__REG—Offset B80Ch

mipi C DSI func prg reg

Access Method
Type: Memory Mapped I/O Register MIPIC_DSI_FUNC_PRG__REG: [GTTMMADR_LSB + 2BF20h] +
(Size: 32 bits) B80Ch

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000001h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
SUPPORTED_FORMAT_IN_VIDEO_MODE
SUPPORTED_DATA_WIDTH_IN_COMMAND_MODE

CHANNEL_NUMBER_FOR_COMMAND_MODE

DATA_LANES_PRG_R_EG
CHANNEL_NUMBER_FOR_VIDEO_MODE
RESERVED

RESERVED_1

Bay Trail-I SoC

420 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

0b
31:16 RESERVED: Reserved.
RW

0b SUPPORTED_DATA_WIDTH_IN_COMMAND_MODE: 000 --) Reserved, 001 --) 16

15:13 bit data , 010 --) 9 bit data , 011 --) 8 bit data , 100 --) option 1 : 101 --) option 2 : 110
RW to 111 --) Reserved
0b
12:11 RESERVED_1: Reserved.
RW
0b SUPPORTED_FORMAT_IN_VIDEO_MODE: Supported colour format, 0001 --)
10:7
RW RGB565, 0010 --) RGB666, 0011 --) RGB 666 loosely packed format, 0100 --) RGB888

0b CHANNEL_NUMBER_FOR_COMMAND_MODE: Virtual channel number for command

6:5
RW mode is programmed by the processor

0b CHANNEL_NUMBER_FOR_VIDEO_MODE: Virtual channel number for command

4:3
RW mode is programmed by the processor

001b DATA_LANES_PRG_R_EG: Number of data lanes to be supported is programmed by

2:0
RW the processor

14.10.102 MIPIC_HS_TX_TIMEOUT_REG—Offset B810h

mipi C HS TX timeout reg

Access Method
Type: Memory Mapped I/O Register MIPIC_HS_TX_TIMEOUT_REG: [GTTMMADR_LSB + 2BF20h] +
(Size: 32 bits) B810h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED

HIGH_SPEED_TX_TIMEOUT_COUNTER

Bit Default &

Description
Range Access

0b
31:24 RESERVED: Reserved.
RW

Bay Trail-I SoC

Datasheet 421
 Graphics, Video and Display

Bit Default &

Description
Range Access

0b HIGH_SPEED_TX_TIMEOUT_COUNTER: The maximum duration allowed for the DSI

23:0 host ,to remain in high speed mode for a transmission. If the counter expires, HS mode
RW is terminated with EOT and the lanes enter stop state

14.10.103 MIPIC_LP_RX_TIMEOUT_REG—Offset B814h

mipi C LP RX timeout reg

Access Method
Type: Memory Mapped I/O Register MIPIC_LP_RX_TIMEOUT_REG: [GTTMMADR_LSB + 2BF20h] +
(Size: 32 bits) B814h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED

LOW_POWER_RECEPTION_TIMEOUT_COUNTER

Bit Default &

Description
Range Access

0b
31:24 RESERVED: Reserved.
RW
0b LOW_POWER_RECEPTION_TIMEOUT_COUNTER: Timeout value to be checked for
23:0
RW received short packets .If the timer expires the DSI Host enters stop state

14.10.104 MIPIC_TURN_AROUND_TIMEOUT_REG—Offset B818h

mipi C Turn Arounf timeout reg

Access Method

Bay Trail-I SoC

422 Datasheet
Graphics, Video and Display

Type: Memory Mapped I/O Register MIPIC_TURN_AROUND_TIMEOUT_REG: [GTTMMADR_LSB +

(Size: 32 bits) 2BF20h] + B818h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TURN_AROUND_TIMEOUT_REGISTER
RESERVED

Bit Default &

Description
Range Access

0b
31:6 RESERVED: Reserved.
RW

0b TURN_AROUND_TIMEOUT_REGISTER: Timeout value to be checked after the DSI

5:0 host makes a turn around in the direction of transfers. If the timer expires the DSI Host
RW enters stop state

14.10.105 MIPIC_DEVICE_RESET_TIMER—Offset B81Ch

mipi C Device reset timer

Access Method
Type: Memory Mapped I/O Register MIPIC_DEVICE_RESET_TIMER: [GTTMMADR_LSB + 2BF20h] +
(Size: 32 bits) B81Ch

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED

DEVICE_RESET_TIMER

Bay Trail-I SoC

Datasheet 423
 Graphics, Video and Display

Bit Default &

Description
Range Access

0b
31:16 RESERVED: Reserved.
RW
0b DEVICE_RESET_TIMER: Timeout value to be checked for device to be reset after
15:0
RW issuing reset entry command. If the timer expires the DSI Host enters normal operation

14.10.106 MIPIC_DPI_RESOLUTION_REG—Offset B820h

mipi C dpi Resolution reg

Access Method
Type: Memory Mapped I/O Register MIPIC_DPI_RESOLUTION_REG: [GTTMMADR_LSB + 2BF20h]
(Size: 32 bits) + B820h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VERTICAL_ADDRESS

HORIZONTAL_ADDRESS

Bit Default &

Description
Range Access

0b
31:16 VERTICAL_ADDRESS: Shows the vertical address count in lines
RW

0b
15:0 HORIZONTAL_ADDRESS: Shows the horizontal address count in pixels
RW

14.10.107 MIPIC_DBI_RESOLUTION_REG—Offset B824h

mipi C DBI resolution reg

Access Method
Type: Memory Mapped I/O Register MIPIC_DBI_RESOLUTION_REG: [GTTMMADR_LSB + 2BF20h]
(Size: 32 bits) + B824h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

424 Datasheet
Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESERVED

DBI_FIFO_THRTL
Bit Default &
Description
Range Access

0b
31:2 RESERVED: Reserved.
RW

0b DBI_FIFO_THRTL: DBI FIFO's watermark can be set using the following bits so as to
1:0 enable dbi_stall de-assertion whenever the below FIFO condition is reached: 00 - (1/2)
RW DBI fifo empty 01 - (1/4) DBI fifo empty 10 - 7 locations are empty 11 - Reserved

14.10.108 MIPIC_HORIZ_SYNC_PADDING_COUNT—Offset B828h

mipi C horizxontal sync padding out

Access Method
Type: Memory Mapped I/O Register MIPIC_HORIZ_SYNC_PADDING_COUNT: [GTTMMADR_LSB +
(Size: 32 bits) 2BF20h] + B828h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED

HORIZONTAL_SYNC_PADDING_COUNT

Bit Default &

Description
Range Access

0b
31:16 RESERVED: Reserved.
RW

0b HORIZONTAL_SYNC_PADDING_COUNT: Shows the horizontal sync padding value in

15:0
RW terms of txbyteclkhs

Bay Trail-I SoC

Datasheet 425
 Graphics, Video and Display

14.10.109 MIPIC_HORIZ_BACK_PORCH_COUNT—Offset B82Ch

mipi C horizontal back portch counter

Access Method
Type: Memory Mapped I/O Register MIPIC_HORIZ_BACK_PORCH_COUNT: [GTTMMADR_LSB +
(Size: 32 bits) 2BF20h] + B82Ch

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED

HORIZONTAL_BACK_PORCH_COUNT
Bit Default &
Description
Range Access

0b
31:16 RESERVED: Reserved.
RW
0b HORIZONTAL_BACK_PORCH_COUNT: Shows the horizontal back porch value in
15:0
RW terms of txbyteclkhs

14.10.110 MIPIC_HORIZ_FRONT_PORCH_COUNT—Offset B830h

mipi C horizontal front Porch counter

Access Method
Type: Memory Mapped I/O Register MIPIC_HORIZ_FRONT_PORCH_COUNT: [GTTMMADR_LSB +
(Size: 32 bits) 2BF20h] + B830h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

426 Datasheet
Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESERVED

HORIZONTAL_FRONT_PORCH_COUNT
Bit Default &
Description
Range Access

0b
31:16 RESERVED: Reserved.
RW
0b HORIZONTAL_FRONT_PORCH_COUNT: Shows the horizontal front porch value in
15:0
RW terms of txbyteclkhs

14.10.111 MIPIC_HORIZ_ACTIVE_AREA_COUNT—Offset B834h

mipi C horizontal active area count

Access Method
Type: Memory Mapped I/O Register MIPIC_HORIZ_ACTIVE_AREA_COUNT: [GTTMMADR_LSB +
(Size: 32 bits) 2BF20h] + B834h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED

HORIZONTAL_ACTIVE_AREA_COUNT

Bay Trail-I SoC

Datasheet 427
 Graphics, Video and Display

Bit Default &

Description
Range Access

0b
31:16 RESERVED: Reserved.
RW
0b HORIZONTAL_ACTIVE_AREA_COUNT: Shows the horizontal active area value in
15:0
RW terms of txbyteclkhs

14.10.112 MIPIC_VERT_SYNC_PADDING_COUNT—Offset B838h

mipi C vertical sync padding count

Access Method
Type: Memory Mapped I/O Register MIPIC_VERT_SYNC_PADDING_COUNT: [GTTMMADR_LSB +
(Size: 32 bits) 2BF20h] + B838h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED

VERTICAL_SYNC_PADDING_COUNT

Bit Default &

Description
Range Access

0b
31:16 RESERVED: Reserved.
RW
0b VERTICAL_SYNC_PADDING_COUNT: Shows the vertical sync padding value in terms
15:0
RW of lines

14.10.113 MIPIC_VERT_BACK_PORCH_COUNT—Offset B83Ch

mipic Vertical back porch count

Access Method
Type: Memory Mapped I/O Register MIPIC_VERT_BACK_PORCH_COUNT: [GTTMMADR_LSB +
(Size: 32 bits) 2BF20h] + B83Ch

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Bay Trail-I SoC

428 Datasheet
Graphics, Video and Display

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESERVED

VERTICAL_BACK_PORCH_COUNT
Bit Default &
Description
Range Access

0b
31:16 RESERVED: Reserved.
RW

0b VERTICAL_BACK_PORCH_COUNT: Shows the vertical back porch value in terms of

15:0
RW lines

14.10.114 MIPIC_VERT_FRONT_PORCH_COUNT—Offset B840h

mipi C vertical front porch count

Access Method
Type: Memory Mapped I/O Register MIPIC_VERT_FRONT_PORCH_COUNT: [GTTMMADR_LSB +
(Size: 32 bits) 2BF20h] + B840h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VERTICAL_FRONT_PORCH_COUNT
RESERVED

Bay Trail-I SoC

Datasheet 429
 Graphics, Video and Display

Bit Default &

Description
Range Access

0b
31:16 RESERVED: Reserved.
RW
0b VERTICAL_FRONT_PORCH_COUNT: Shows the vertical front porch value in terms of
15:0
RW lines

14.10.115 MIPIC_HIGH_LOW_SWITCH_COUNT—Offset B844h

mipi C high low switch count

Access Method
Type: Memory Mapped I/O Register MIPIC_HIGH_LOW_SWITCH_COUNT: [GTTMMADR_LSB +
(Size: 32 bits) 2BF20h] + B844h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED

HIGH_SPEED_TO_LOW_POWER_OR_LOW_POWER_TO_HIGH_SPEED_SWITCH_COUNT

Bay Trail-I SoC

430 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

0b RESERVED: High speed to low power or Low power to high speed switching time in
31:16
RW terms of txbyteclkhs

0b HIGH_SPEED_TO_LOW_POWER_OR_LOW_POWER_TO_HIGH_SPEED_SWITCH
15:0 _COUNT: High speed to low power or Low power to high speed switching time in terms
RW of txbyteclkhs

14.10.116 MIPIC_DPI_CTRL_REG—Offset B848h

mipi C dpi ctrl reg

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) MIPIC_DPI_CTRL_REG: [GTTMMADR_LSB + 2BF20h] + B848h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

HS_LP
BACK_LIGHT_OFF

SHUT_DOWN
RSTTRG

BACK_LIGHT_ON
COLOR_MODE_OFF
COLOR_MODE_ON
TURN_ON
RESERVED

Bit Default &

Description
Range Access

0b
31:8 RESERVED: Reserved.
RW

0b
7 RSTTRG: mipi C dpi ctrl Reg RSTTRG
RW

0b HS_LP: Set to '0' to indicate the special packets are sent through the DSI link using HS
6 transmission and set to '1' to indicate that the special packets are sent through the DSI
RW link using low power mode

0b BACK_LIGHT_OFF: Set to '1' to indicate a backlight OFF short packet has to be

5
RW packetised for the DPI's virtual channel

0b BACK_LIGHT_ON: Set to '1' to indicate a backlight ON short packet has to be

4
RW packetised for the DPI's virtual channel

0b COLOR_MODE_OFF: Set to '1' to indicate a color mode OFF short packet has to be
3
RW packetised for the DPI's virtual channel

0b COLOR_MODE_ON: Set to '1' to indicate a color mode ON short packet has to be

2
RW packetised for the DPI's virtual channel

0b TURN_ON: Set to '1' to indicate a turn on short packet has to be packetised for the
1
RW DPI's virtual channel

0b SHUT_DOWN: Set to '1' to indicate a shut down short packet has to be packetised for
0
RW the DPI's virtual channel

Bay Trail-I SoC

Datasheet 431
 Graphics, Video and Display

14.10.117 MIPIC_DPI_DATA_REGISTER—Offset B84Ch

mipiC dpi data register

Access Method
Type: Memory Mapped I/O Register MIPIC_DPI_DATA_REGISTER: [GTTMMADR_LSB + 2BF20h] +
(Size: 32 bits) B84Ch

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESERVED

COMMAND_BYTE
Bit Default &
Description
Range Access

0b
31:6 RESERVED: Reserved.
RW
COMMAND_BYTE: Command Byte to represent the new or not defined command bytes
0b usage for special features representation. [Like backlight ON and OFF]. This register
5:0
RW should be programmed before the DPI control register is being programmed for
backlight ON/OFF

14.10.118 MIPIC_INIT_COUNT_REGISTER—Offset B850h

mipi C init counter register

Access Method
Type: Memory Mapped I/O Register MIPIC_INIT_COUNT_REGISTER: [GTTMMADR_LSB + 2BF20h]
(Size: 32 bits) + B850h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MASTER_INIT_TIMER
RESERVED

Bay Trail-I SoC

432 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

0b
31:16 RESERVED: Reserved.
RW
0b MASTER_INIT_TIMER: Counter value in terms of low power clock to initialise the DSI
15:0
RW Host IP [ TINT] that drives a stop state on the mipi's D-PHY bus

14.10.119 MIPIC_MAX_RETURN_PKT_SIZE_REGISTER—Offset B854h

mipi C max return PKT size register

Access Method
Type: Memory Mapped I/O Register MIPIC_MAX_RETURN_PKT_SIZE_REGISTER:
(Size: 32 bits) [GTTMMADR_LSB + 2BF20h] + B854h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED

MAX_RETURN_PKT_SIZE
Bit Default &
Description
Range Access

0b
31:10 RESERVED: Reserved.
RW
0b MAX_RETURN_PKT_SIZE: Set the count value in bytes to collect the return data
9:0
RW packet for reverse direction data flow in data lane0 in response to a DBI read operation

14.10.120 MIPIC_VIDEO_MODE_FORMAT_REGISTER—Offset B858h

mipi C video mode format register

Access Method
Type: Memory Mapped I/O Register MIPIC_VIDEO_MODE_FORMAT_REGISTER: [GTTMMADR_LSB
(Size: 32 bits) + 2BF20h] + B858h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

Datasheet 433
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RANDOM_DPI_DISPLAY_RESOLUTION_DEFEATURE

VIDEO_MODE_FMT
RESERVED

MIPIC_DISABLE_VIDEO_BTA
IP_TG_CONFIG
Bit Default &
Description
Range Access

0b
31:5 RESERVED: Reserved.
RW

0b RANDOM_DPI_DISPLAY_RESOLUTION_DEFEATURE: Set by the processor to

4 support random DPI display resolution 0 - random DPI display resolution support
RW disabled. 1 - random DPI display resolution support enabled.
MIPIC_DISABLE_VIDEO_BTA: Set by the processor to inform the DSI controller to
0b disable the BTA sent at the last blanking line of VFP. By default, this bit is set to 0. 0-
3
RW BTA sending at the last blanking line of VFP is enabled. 1 - BTA sentding at teh last
blanking line of VFP is disabeld.
IP_TG_CONFIG: Set by the processor to inform that the DSI controller should
discontinue the DPI transfer after the last line of the VFP after ip_tg_enable deassertion.
0b By default, this bit is set to 0. 0 - After ip_tg_enable deassertion, DSI Tx controller stops
2
RW the DPI transfer immediately after the current packet is transmitted. 1 - After
ip_tg_enable deassertion, DSI Tx controller discontinues the DPI transfer after the last
line of the VFP

VIDEO_MODE_FMT: Sets the Video mode format (packet sequence) to be supported

in DSI. In Non Burst Mode, in addition to programming this register the horizontal active
area count register value should also be programmed equal to RGB word count value In
0b Burst Mode, in addition to programming this register the horizontal active area count
1:0
RW register value should also be programmed greater than the RGB word count value,
leaving more time during a scan line for LP mode (saving power) or for multiplexing
other transmissions onto the DSI link. 00 Reserved 01 - Non Burst Mode with Sync Pulse
10 - Non Burst Mode with Sync events 11 - Burst Mode

14.10.121 MIPIC_EOT_DISABLE_REGISTER—Offset B85Ch

mipi C EOT disable register

Access Method
Type: Memory Mapped I/O Register MIPIC_EOT_DISABLE_REGISTER: [GTTMMADR_LSB +
(Size: 32 bits) 2BF20h] + B85Ch

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Bay Trail-I SoC

434 Datasheet
Graphics, Video and Display

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

LOW_CONTENTION_RECOVERY_DISABLE
RESERVED

HS_TX_TIMEOUT_ERROR_RECOVERY_DISABLE

EOT_DIS
LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE

CLOCKSTOP
HIGH_CONTENTION_RECOVERY_DISABLE
TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE
TXECC_MULTIBIT_ERR_RECOVERY_DISABLE
Bit Default &
Description
Range Access

0b
31:8 RESERVED: Reserved.
RW

LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE: Set by the processor to enable or

disable the LP_Rx_timeout error recovery if the processor clears LP_Rx_timeout error
0b interrupt. 0 - LP_Rx_timeout error recovery action will be taken by the DSI Tx controller
7
RW if the processor clears the LP_Rx_timeout error interrupt. 1 - If the processor clears the
LP_Rx_timeout error interrupt, LP_Rx_timeout error recovery action will not happen in
DSI Tx contorller. LP Rx timeout error interrupt will act as an informative interrupt
HS_TX_TIMEOUT_ERROR_RECOVERY_DISABLE: Set by the processor to enable or
disable the HS_Tx_timeout error recovery if the processor clears HS_Tx_timeout
0b interrupt. 0 - HS_Tx_timeout error recovery action will be taken by the DSI Tx controller
6
RW if the processor clears the HS_Tx_timeout error interrupt. 1 - If the processor clears the
HS_Tx_timeout error interrupt, HS_Tx_timeout error recovery action will not happen in
DSI Tx contorller. HS Tx timeout error interrupt will act as an informative interrupt
LOW_CONTENTION_RECOVERY_DISABLE: Set by the processor to enable or
disable the contention recovery procedure if the processor clears Low contention
0b interrupt. 0 - Contention recovery will happen if the processor clears Low contention
5
RW interrupt. 1 - If the processor clears the low contention interrupt, contention recovery
procedure will not be initiated by the DSI Tx contorller. Low contention interrupt will act
as an informative interrupt
HIGH_CONTENTION_RECOVERY_DISABLE: Set by the processor to enable or
disable the contention recovery procedure if the processor clears High contention
0b interrupt. 0 - Contention recovery will happen if the processor clears High contention
4
RW interrupt. 1 - If the processor clears the high contention interrupt, contention recovery
procedure will not be initiated by the DSI Tx contorller. Ignore the High Contention
Interrupt in MIPI_INTR_STAT_REG

Bay Trail-I SoC

Datasheet 435
 Graphics, Video and Display

Bit Default &

Description
Range Access

TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE: Set by the

processor to enable or disable the error recovery action to be taken by the DSI Tx
0b controller if TxDSI data type not recognised error interrupt is cleared by the processor. 0
3 - Error recovery action will be taken if TxDSI data type not recognised error interrupt is
RW cleared by the processor. 1 - If TxDSI data type not recognised error interrupt is cleared
by the processor, error recovery action will not be taken by the DSI TX controller. Tx DSI
data type not recognized error interrupt will act as an informative interrupt
TXECC_MULTIBIT_ERR_RECOVERY_DISABLE: Set by the processor to enable or
disable the error recovery action to be taken by the DSI Tx controller if Tx ECC multibit
0b error interrupt is cleared by the processor. 0 - Error recovery action will be taken if Tx
2
RW ECC multibit error interrupt is cleared by the processor. 1 - If Tx ECC multibit error
interrupt is cleared by the processor, error recovery action will not be taken by the DSI
TX controller. Tx multibit error interrupt will act as an informative interrupt
CLOCKSTOP: Set by the processor to enable or disable clock stopping feature during
0b BLLP timing in a DPI transfer in dual channel mode or during DPI only mode and also
1
RW when there is no traffic in the DBI interface in DBI only enabled mode. By default this
register value is 0. 0 - clock stopping disabled 1 - clock stopping enabled

EOT_DIS: Set by the processor to enable or disable EOT short packet transmission. By
0b default this register value is 0. For backward comapatibility of earlier DSI systems, EOT
0
RW short packet transmission can be disabled. 0 - EOT short packet transmission enabled 1
- EOT short packet transmission disabled

14.10.122 MIPIC_LP_BYTECLK_REGISTER—Offset B860h

mipi C LP byteclk register

Access Method
Type: Memory Mapped I/O Register MIPIC_LP_BYTECLK_REGISTER: [GTTMMADR_LSB + 2BF20h]
(Size: 32 bits) + B860h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
LP_BYTECLK
RESERVED

Bit Default &

Description
Range Access

0b
31:16 RESERVED: Reserved.
RW

LP_BYTECLK: Low power clock equivalence in terms of byte clock. The value
0b programmed in this register is equal to the number of byte clocks occupied in one low
15:0
RW power clock. This value is based on the byte clock (txbyteclkhs) and low power clock
frequency (txclkesc)

14.10.123 MIPIC_LP_GEN_DATA_REGISTER—Offset B864h

mipi C LP gen DATA register

Bay Trail-I SoC

436 Datasheet
Graphics, Video and Display

Access Method
Type: Memory Mapped I/O Register MIPIC_LP_GEN_DATA_REGISTER: [GTTMMADR_LSB +
(Size: 32 bits) 2BF20h] + B864h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

LP_GEN_DATA
Bit Default &
Description
Range Access

0b
31:0 LP_GEN_DATA: Data port register used for generic data transfers in low power mode
RW

14.10.124 MIPIC_HS_GEN_DATA_REGISTER—Offset B868h

mipi C HS Gen data register

Access Method
Type: Memory Mapped I/O Register MIPIC_HS_GEN_DATA_REGISTER: [GTTMMADR_LSB +
(Size: 32 bits) 2BF20h] + B868h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HS_GEN_DATA

Bit Default &

Description
Range Access

0b
31:0 HS_GEN_DATA: Data port register used for generic data transfers in low power mode
RW

14.10.125 MIPIC_LP_GEN_CTRL_REGISTER—Offset B86Ch

mipi C LP Gen ctrl register

Access Method

Bay Trail-I SoC

Datasheet 437
 Graphics, Video and Display

Type: Memory Mapped I/O Register MIPIC_LP_GEN_CTRL_REGISTER: [GTTMMADR_LSB +

(Size: 32 bits) 2BF20h] + B86Ch

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

VIRTUAL_CHANNEL

DATA_TYPE
WORD_COUNT
RESERVED

Bit Default &

Description
Range Access

0b
31:24 RESERVED: Reserved.
WO

0b WORD_COUNT: Specifies the word count for generic long packet Specifies the
23:8 accompanied parameters for generic short packets. Note: Invalid parameters must be
WO set to 00h

0b VIRTUAL_CHANNEL: Used to specify the virtual channel for which the generic data
7:6
WO transmission is intended

DATA_TYPE: Used to specify the generic data types 03h - Generic short write, no
parameters 13h - Generic short write, 1 parameter 23h - Generic short write, 2
0b parameters 04h - Generic read, no parameters 14h - Generic read, 1 parameter 24h -
5:0
WO Generic read 2 parameter 29h - Generic long write 05h - Manufacturer DCS short write,
no parameter 15h - Manufacturer DCS short write, one parameter 06h - Manufacturer
DCS read, no parameter 39h - Manufacturer DCS long write

14.10.126 MIPIC_HS_GEN_CTRL_REGISTER—Offset B870h

mipiC HS

Access Method
Type: Memory Mapped I/O Register MIPIC_HS_GEN_CTRL_REGISTER: [GTTMMADR_LSB +
(Size: 32 bits) 2BF20h] + B870h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VIRTUAL_CHANNEL
RESERVED

WORD_COUNT

DATA_TYPE

Bay Trail-I SoC

438 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

0b
31:24 RESERVED: Reserved.
WO

0b WORD_COUNT: Specifies the word count for generic long packet Specifies the
23:8 accompanied parameters for generic short packets. Note: Invalid parameters must be
WO set to 00h
0b VIRTUAL_CHANNEL: Used to specify the virtual channel for which the generic data
7:6
WO transmission is intended

DATA_TYPE: Used to specify the generic data types 03h - Generic short write, no
parameters 13h - Generic short write, 1 parameter 23h - Generic short write, 2
0b parameters 04h - Generic read, no parameters 14h - Generic read, 1 parameter 24h -
5:0
WO Generic read 2 parameter 29h - Generic long write 05h - Manufacturer DCS short write,
no parameter 15h - Manufacturer DCS short write, one parameter 06h - Manufacturer
DCS read, no parameter 39h - Manufacturer DCS long write

14.10.127 MIPIC_GEN_FIFO_STAT_REGISTER—Offset B874h

mipi C gen fifo stat register

Access Method
Type: Memory Mapped I/O Register MIPIC_GEN_FIFO_STAT_REGISTER: [GTTMMADR_LSB +
(Size: 32 bits) 2BF20h] + B874h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 1E060606h
31 28 24 20 16 12 8 4 0

0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0
RESERVED

DPI_FIFO_EMPTY
DBI_FIFO_EMPTY
LP_CTRL_FIFO_EMPTY
LP_CTRL_FIFO_HALF_EMPTY

LP_DATA_FIFO_EMPTY
LP_DATA_FIFO_HALF_EMPTY

HS_DATA_FIFO_EMPTY
HS_DATA_FIFO_HALF_EMPTY
HS_CTRL_FIFO_EMPTY
HS_CTRL_FIFO_HALF_EMPTY

HS_DATA_FIFO_FULL
LP_CTRL_FIFO_FULL

LP_DATA_FIFO_FULL
HS_CTRL_FIFO_FULL
RESERVED_1

RESERVED_2

RESERVED_3

Bit Default &

Description
Range Access

0b
31:29 RESERVED: Reserved.
RO

1b
28 DPI_FIFO_EMPTY: Default 1
RO

1b
27 DBI_FIFO_EMPTY: Default 1
RO

1b
26 LP_CTRL_FIFO_EMPTY: Default 1
RO

Bay Trail-I SoC

Datasheet 439
 Graphics, Video and Display

Bit Default &

Description
Range Access

1b
25 LP_CTRL_FIFO_HALF_EMPTY: Default 1
RO
0b
24 LP_CTRL_FIFO_FULL: Default 0
RO
0b
23:19 RESERVED_1: Reserved.
RO
1b
18 HS_CTRL_FIFO_EMPTY: Default 1
RO
1b
17 HS_CTRL_FIFO_HALF_EMPTY: Default 1
RO
0b
16 HS_CTRL_FIFO_FULL: Default 0
RO
0b
15:11 RESERVED_2: Reserved.
RO
1b
10 LP_DATA_FIFO_EMPTY: Default 1
RO
1b
9 LP_DATA_FIFO_HALF_EMPTY: Default 1
RO
0b
8 LP_DATA_FIFO_FULL: Default 0
RO
0b
7:3 RESERVED_3: Reserved.
RO
1b
2 HS_DATA_FIFO_EMPTY: Default 1
RO
1b
1 HS_DATA_FIFO_HALF_EMPTY: Default 1
RO
0b
0 HS_DATA_FIFO_FULL: Default 0
RO

14.10.128 MIPIC_HS_LS_DBI_ENABLE_REG—Offset B878h

Note : dbi_hs_lp_switch_reg has to be written only if DBI FIFO is empty

Access Method
Type: Memory Mapped I/O Register MIPIC_HS_LS_DBI_ENABLE_REG: [GTTMMADR_LSB +
(Size: 32 bits) 2BF20h] + B878h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

440 Datasheet
Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESERVED

DBI_HS_LS_SWITCH_RE
Bit Default &
Description
Range Access

0b
31:1 RESERVED: Reserved.
RW

0b DBI_HS_LS_SWITCH_RE: Set to 1 if DBI packets have to be transmitted in Low

0
RW power mode Set to 0 if DBI packets have to be transmitted in High speed mode

14.10.129 MIPIC_RESERVED—Offset B87Ch

Reserved.

Access Method
Type: Memory Mapped I/O Register MIPIC_RESERVED: [GTTMMADR_LSB + 2BF20h] + B87Ch
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED

Bit Default &

Description
Range Access

0b
31:0 RESERVED: Reserved.
RO

14.10.130 MIPIC_DPHY_PARAM_REG—Offset B880h

mipi C dphy param reg

Access Method

Bay Trail-I SoC

Datasheet 441
 Graphics, Video and Display

Type: Memory Mapped I/O Register MIPIC_DPHY_PARAM_REG: [GTTMMADR_LSB + 2BF20h] +

(Size: 32 bits) B880h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 0B061A04h
31 28 24 20 16 12 8 4 0

0 0 0 0 1 0 1 1 0 0 0 0 0 1 1 0 0 0 0 1 1 0 1 0 0 0 0 0 0 1 0 0

PREPARE_COUNT
RESERVED_1

RESERVED_2
RESERVED

EXIT_ZERO_COUNT

TRAIL_COUNT

CLK_ZERO_COUNT
Bit Default &
Description
Range Access

0b
31:30 RESERVED: Reserved.
RW
001011b EXIT_ZERO_COUNT: THS_0_TIM_UI_CNT and THS_EXIT_TIM_UI_CNT for dphy are
29:24
RW programmed as exit zero count by the processor

0b
23:21 RESERVED_1: Reserved.
RW
00110b TRAIL_COUNT: TCLK_POST_TIM_UI_CNT and TCLK_TRAIL_TIM_UI_CNT for dphy are
20:16
RW programmed as trail count by the processor

00011010b CLK_ZERO_COUNT: TCLK_0_TIM_UI_CNT for dphy is programmed as clk zero count

15:8
RW by the processor

0b
7:6 RESERVED_2: Reserved.
RW
000100b PREPARE_COUNT: TCLK_PREP_TIM_UI_CNT and THS_PREP_TIM_UI_CNT for dphy are
5:0
RW programmed as prepare count by the processor

14.10.131 MIPIC_DBI_BW_CTRL_REG—Offset B884h

mipi C DBI BW ctrl reg

Access Method
Type: Memory Mapped I/O Register MIPIC_DBI_BW_CTRL_REG: [GTTMMADR_LSB + 2BF20h] +
(Size: 32 bits) B884h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

442 Datasheet
Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BANDWIDTH_TIMER
Bit Default &
Description
Range Access

BANDWIDTH_TIMER: DBI Bandwidth control Register. The bandwidth essential for

transmitting 16 long packets containing 252 bytes meant for DCS write memory
0b command is programmed in this register in terms of byte clocks. Based on the DSI
31:0 transfer rate and the number of lanes configured the time taken to transmit 16 long
RW packets in a DSI stream varies. Note: The value programmed in this timer must be
greater than the actual time taken to carryout 16 long packets transmission in DSI
stream plus the time taken to transmit two blanking packets

14.10.132 MIPIC_CLK_LANE_SWITCHING_TIME_CNT—Offset B888h

mipi C clk lane switching time count

Access Method
Type: Memory Mapped I/O Register MIPIC_CLK_LANE_SWITCHING_TIME_CNT: [GTTMMADR_LSB
(Size: 32 bits) + 2BF20h] + B888h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HS_LS_PWR_SW_CNT
LS_HS_SSW_CNT

Bit Default &

Description
Range Access

LS_HS_SSW_CNT: Low power to high speed switching time in terms byte clock
0b (txbyteclkhs). This value is based on the byte clock (txbyteclkhs) and low power clock
31:16 frequency (txclkesc). Typical value - Number of byte clocks required to switch from low
RW power mode to high speed mode after txrequesths_clk is asserted. Current Value is ah
= 10 txbyteclkhs

HS_LS_PWR_SW_CNT: High speed to low power switching time in terms byte clock
0b (txbyteclkhs). This value is based on the byte clock (txbyteclkhs) and low power clock
15:0 frequency (txclkesc). Typical value - Number of byte clocks request to switch from high
RW speed mode to low power mode after txrequesths_clk is de-asserted. Current Value is
14h = 20 txbyteclkhs

Bay Trail-I SoC

Datasheet 443
 Graphics, Video and Display

14.10.133 MIPIC_STOP_STATE_STALL—Offset B88Ch

mipi C stop state stall

Access Method
Type: Memory Mapped I/O Register MIPIC_STOP_STATE_STALL: [GTTMMADR_LSB + 2BF20h] +
(Size: 32 bits) B88Ch

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESERVED

MIPIC_STOP_STATE_STALL_COUNTER
Bit Default &
Description
Range Access

0b
31:8 RESERVED: reserved
RW
MIPIC_STOP_STATE_STALL_COUNTER: Delay between (stall the stop state signal)
the data transfer is increased based on this counter value. This counter is calculated
from txclkesc. Note: If processor programs this register then it needs to reprogram the
0b high_low_ switch counter in B844h and lp_equivalent_byteclk reg in B860h to
7:0 compensate this delay. High_low_switch_count B844h: High to low switch counter =
RW Actual High to low switch + stop_sta_stall_reg value * Low power clock equivalence
value in terms of byte clock LP equivalent byteclk register B860h: LP equivalent byteclk
value = txclkesc time/ txbyteclk time * (105 + stop_sta_stall_reg value) / 105 Minimum
time of Low Power short packet transfer = 105 txclkesc

14.10.134 MIPIC_INTR_STAT_REG_1—Offset B890h

mipi C intrrupt stat register 1

Access Method
Type: Memory Mapped I/O Register MIPIC_INTR_STAT_REG_1: [GTTMMADR_LSB + 2BF20h] +
(Size: 32 bits) B890h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

444 Datasheet
Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESERVED

MIPIC_RX_CONNECTION_DETECTED
Bit Default &
Description
Range Access

0b
31:1 RESERVED: reserved
RW

0b MIPIC_RX_CONNECTION_DETECTED: Set to 1'b1 if the contention detected in the

0
RW display device and is reported in the Acknowledge packet by the display device

14.10.135 MIPIC_INTR_EN_REG_1—Offset B894h

mipic interrupt enable register

Access Method
Type: Memory Mapped I/O Register MIPIC_INTR_EN_REG_1: [GTTMMADR_LSB + 2BF20h] +
(Size: 32 bits) B894h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED

MIPIC_ENABLE_RX_CONNECTION_DETECTED

Bay Trail-I SoC

Datasheet 445
 Graphics, Video and Display

Bit Default &

Description
Range Access

0b
31:1 RESERVED: reserved
RW
0b MIPIC_ENABLE_RX_CONNECTION_DETECTED: Set to enable the interrupt for
0
RW contention detected error in the acknowledgement packet reports

14.10.136 MIPIC_CTRL—Offset B904h

mipi ctrl reg

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) MIPIC_CTRL: [GTTMMADR_LSB + 2BF20h] + B904h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RGB_FLIP

MIPI_2X_CLOCK_DIVIDER
NAME_BITS

STATUS
Bit Default &
Description
Range Access

0b
31:5 NAME_BITS: Reserved
RW
0b
4:3 STATUS: 2'b00: low priority on read requests to G-unit 2'b11 : high priority
RW
0b RGB_FLIP: 1'b0 : RGB data from disp2d is reverted to BGR 1'b1 : RGB data from
2
RW disp2d is passed as is to MIPI IP

0b
1:0 MIPI_2X_CLOCK_DIVIDER: Reserved
RW

14.10.137 MIPIC_DATA_ADD—Offset B908h

mipi C data ADD

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) MIPIC_DATA_ADD: [GTTMMADR_LSB + 2BF20h] + B908h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Bay Trail-I SoC

446 Datasheet
Graphics, Video and Display

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DATA_MEM_ADDR

DATA_VALID
DATA_MEM_ADDR_1
Bit Default &
Description
Range Access

0b DATA_MEM_ADDR: When there is updated data for the display panel, S/W programs
31:5
RW this register with the memory address to read from

0b
4:1 DATA_MEM_ADDR_1: Reserved
RW

0b DATA_VALID: This bit is set by S/W when the mem_addr is written and is cleared by
0
RW H/W when done reading the data from memory

14.10.138 MIPIC_DATA_LEN—Offset B90Ch

mipiC data length

Access Method
Type: Memory Mapped I/O Register MIPIC_DATA_LEN: [GTTMMADR_LSB + 2BF20h] + B90Ch
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DATA_LENGTH
RESERVED

Bit Default &

Description
Range Access

0b
31:20 RESERVED: Reserved.
RW

0b DATA_LENGTH: This field shows the remaining length of data that needs to be read
19:0
RW from memory, Initially set by S/W and is decremented by H/W as reads are issued

14.10.139 MIPIC_CMD_ADD—Offset B910h

mipiC command add

Access Method

Bay Trail-I SoC

Datasheet 447
 Graphics, Video and Display

Type: Memory Mapped I/O Register

MIPIC_CMD_ADD: [GTTMMADR_LSB + 2BF20h] + B910h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

COMMAND_MEM_ADDR

COMMAND_DATA_MODE
MIPIC_AUTO_PWG_ENABLE

COMMAND_VALID
RESERVED
Bit Default &
Description
Range Access

0b COMMAND_MEM_ADDR: When there are new commands that need to be sent to the
31:5 display panel, S/W programs this register with the memory address to read the
RW commands from
0b
4:3 RESERVED: MBZ
RW
0b MIPIC_AUTO_PWG_ENABLE: Idle state: SW driver writes to this bit to enable auto
2
RW power gating for MIPIC controller 0: default 1: auto power gate is enabled

0b COMMAND_DATA_MODE: 0: data for memory write command from system buffer

1 that is specified by MIPI data address register 1: data for memory write command from
RW pipe A rendering
0b COMMAND_VALID: This bit is set by S/W when the mem_addr is written and is
0
RW cleared by H/W when done reading the data from memory

14.10.140 MIPIC_CMD_LEN—Offset B914h

mipiC commanf Length

Access Method
Type: Memory Mapped I/O Register MIPIC_CMD_LEN: [GTTMMADR_LSB + 2BF20h] + B914h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
COMMAND_3

COMMAND_2

COMMAND_1

COMMAND_0

Bay Trail-I SoC

448 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

0b
31:24 COMMAND_3: This is command 3 length (command + parameters) in bytes
RW
0b
23:16 COMMAND_2: This is command 2 length (command + parameters) in bytes
RW
0b
15:8 COMMAND_1: This is command 1 length (command + parameters) in bytes
RW
0b
7:0 COMMAND_0: This is command 0 length (command + parameters) in bytes
RW

14.10.141 MIPIC_RD_DATA_RETURN0—Offset B918h

mipi C Read data return 0

Access Method
Type: Memory Mapped I/O Register MIPIC_RD_DATA_RETURN0: [GTTMMADR_LSB + 2BF20h] +
(Size: 32 bits) B918h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RD_DATA_RETURN_PANEL

Bit Default &

Description
Range Access

0b
31:0 RD_DATA_RETURN_PANEL: This is the configuration data returned from the panel
RO

14.10.142 MIPIC_RD_DATA_RETURN1—Offset B91Ch

mipi C read data return 1

Access Method
Type: Memory Mapped I/O Register MIPIC_RD_DATA_RETURN1: [GTTMMADR_LSB + 2BF20h] +
(Size: 32 bits) B91Ch

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

Datasheet 449
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RD_DATA_RETURN_PANEL
Bit Default &
Description
Range Access

0b
31:0 RD_DATA_RETURN_PANEL: This is the configuration data returned from the panel
RO

14.10.143 MIPIC_RD_DATA_RETURN2—Offset B920h

mipi C read data return 2

Access Method
Type: Memory Mapped I/O Register MIPIC_RD_DATA_RETURN2: [GTTMMADR_LSB + 2BF20h] +
(Size: 32 bits) B920h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RD_DATA_RETURN_PANEL

Bit Default &

Description
Range Access

0b
31:0 RD_DATA_RETURN_PANEL: This is the configuration data returned from the panel
RO

14.10.144 MIPIC_RD_DATA_RETURN3—Offset B924h

mipi C read data return 3

Access Method

Bay Trail-I SoC

450 Datasheet
Graphics, Video and Display

Type: Memory Mapped I/O Register MIPIC_RD_DATA_RETURN3: [GTTMMADR_LSB + 2BF20h] +

(Size: 32 bits) B924h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RD_DATA_RETURN_PANEL
Bit Default &
Description
Range Access

0b
31:0 RD_DATA_RETURN_PANEL: This is the configuration data returned from the panel
RO

14.10.145 MIPIC_RD_DATA_RETURN4—Offset B928h

mipi C read data return 4

Access Method
Type: Memory Mapped I/O Register MIPIC_RD_DATA_RETURN4: [GTTMMADR_LSB + 2BF20h] +
(Size: 32 bits) B928h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RD_DATA_RETURN_PANEL

Bit Default &

Description
Range Access

0b
31:0 RD_DATA_RETURN_PANEL: This is the configuration data returned from the panel
RO

Bay Trail-I SoC

Datasheet 451
 Graphics, Video and Display

14.10.146 MIPIC_RD_DATA_RETURN5—Offset B92Ch

mipi C read data return 5

Access Method
Type: Memory Mapped I/O Register MIPIC_RD_DATA_RETURN5: [GTTMMADR_LSB + 2BF20h] +
(Size: 32 bits) B92Ch

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RD_DATA_RETURN_PANEL

Bit Default &

Description
Range Access

0b
31:0 RD_DATA_RETURN_PANEL: This is the configuration data returned from the panel
RO

14.10.147 MIPIC_RD_DATA_RETURN6—Offset B930h

mipi C read data return 6

Access Method
Type: Memory Mapped I/O Register MIPIC_RD_DATA_RETURN6: [GTTMMADR_LSB + 2BF20h] +
(Size: 32 bits) B930h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RD_DATA_RETURN_PANEL

Bay Trail-I SoC

452 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

0b
31:0 RD_DATA_RETURN_PANEL: This is the configuration data returned from the panel
RO

14.10.148 MIPIC_RD_DATA_RETURN7—Offset B934h

mipi C read data return 7

Access Method
Type: Memory Mapped I/O Register MIPIC_RD_DATA_RETURN7: [GTTMMADR_LSB + 2BF20h] +
(Size: 32 bits) B934h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RD_DATA_RETURN_PANEL

Bit Default &

Description
Range Access

0b
31:0 RD_DATA_RETURN_PANEL: This is the configuration data returned from the panel
RO

14.10.149 MIPIC_RD_DATA_VALID—Offset B938h

mipi C read data valid

Access Method
Type: Memory Mapped I/O Register MIPIC_RD_DATA_VALID: [GTTMMADR_LSB + 2BF20h] +
(Size: 32 bits) B938h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

Datasheet 453
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

READ_DATA_VALID
RESERVED
Bit Default &
Description
Range Access

0b
31:8 RESERVED: Reserved.
RW
READ_DATA_VALID: Each bit corresponds to presence of valid data in the registers
0b above. When data is returned from the panel, H/W will write into these registers in
7:0
RW sequence, and set the corresponding valid bit. When S/W issues a write '1 to the
registers, this bit is cleared

14.10.150 HTOTAL_A—Offset 60000h

Pipe A Horizontal Total Register

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) HTOTAL_A: [GTTMMADR_LSB + 2BF20h] + 60000h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED

RESERVED_1

PIPE_A_HORIZONTAL_ACTIVE_DISPLAY_END_PIXELS
PIPE_A_HORIZONTAL_TOTAL_DISPLAY_CLOCKS

Bay Trail-I SoC

454 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

0b
31:29 RESERVED: Write as zero.
RW
PIPE_A_HORIZONTAL_TOTAL_DISPLAY_CLOCKS: This 13-bit field provides
Horizontal Total up to 8192 pixels encompassing the Horizontal Active Display period,
front/back border and retrace period. Any pending event (HSYNC, ACTIVE, HBLANK) is
0b reset at HTOTAL and the programmed sequence begins again. This field is programmed
28:16
RW to the number of clocks desired minus one. This number of clocks needs to be a multiple
of two when driving data out the digital port out the LVDS port in two channel mode.
This value should always be equal or greater to the sum of the horizontal active and the
horizontal blank, and border region sizes.
0b
15:12 RESERVED_1: Write as zero.
RW
PIPE_A_HORIZONTAL_ACTIVE_DISPLAY_END_PIXELS: This 12-bit field provides
Horizontal Active Display resolutions up to 4096 pixels. Note that the first horizontal
active display pixel is considered pixel number 0. The value programmed should be the
(active pixels/line 1). The number of active pixels will be limited to multiples of two
0b pixels when driving the integrated LVDS port in two channel mode. For proper results
11:0
RW during VGA centering mode this value needs to be large enough to fit the largest VGA
mode supported, this should be at least 720/1440 pixels for standard VGA type modes
or 640/1280 pixels if the nine-dot disable bit in the VGA control register is set. When
using the internal panel fitting logic, the minimum horizontal size allowed will be three
pixels.

14.10.151 HBLANK_A—Offset 60004h

Pipe A Horizontal Blank Register

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) HBLANK_A: [GTTMMADR_LSB + 2BF20h] + 60004h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED

PIPE_A_HORIZONTAL_BLANK_END

RESERVED_1

PIPE_A_HORIZONTAL_BLANK_START

Bay Trail-I SoC

Datasheet 455
 Graphics, Video and Display

Bit Default &

Description
Range Access

0b
31:29 RESERVED: Read Only.
RW
PIPE_A_HORIZONTAL_BLANK_END: This 13-bit field specifies the position of
Horizontal Blank End expressed in terms of the absolute pixel number relative to the
horizontal active display start. The value programmed should be the HBLANK End pixel
position, where the first active pixel is considered position 0; the second active pixel is
0b considered position 1, etc. Horizontal blank ending at the same point as the horizontal
28:16 total indicates that there is no left hand border area. HBLANK size has a minimum value
RW of 32 clocks. The number of clocks within blank needs to be a multiple of two when
driving data out LVDS in two channel mode. The value loaded in the register would be
equal to RightBorder+Active+HBlank-1. If this pipe is connected to the TVout port or
Panel Fitter 2 the border must be zero. In that case this register is programmed to the
same value as the HTOTAL register.
0b
15:13 RESERVED_1: Read Only.
RW
PIPE_A_HORIZONTAL_BLANK_START: This 13-bit field specifies the Horizontal
Blank Start position expressed in terms of the absolute pixel number relative to the
horizontal active display start. The value programmed should be the HBLANK Start pixel
position, where the first active pixel is considered position 0; the second active pixel is
0b considered position 1, etc. The number of clocks for both left and right borders need to
12:0
RW be a multiple of two when driving data out the LVDS port in two channel mode.
Horizontal blank should only start after the end of the horizontal active region. The
value loaded in the register would be equal to RightBorder+Active-1. If this pipe is
connected to the TVout port or Panel Fitter 2 the border must be zero. In that case this
register is programmed to the same value as the HACTIVE register.

14.10.152 HSYNC_A—Offset 60008h

Pipe A Horizontal Sync Register

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) HSYNC_A: [GTTMMADR_LSB + 2BF20h] + 60008h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED

PIPE_A_HORIZONTAL_SYNC_END

RESERVED_1

PIPE_A_HORIZONTAL_SYNC_START

Bay Trail-I SoC

456 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

0b
31:29 RESERVED: Write as zero.
RW
PIPE_A_HORIZONTAL_SYNC_END: This 13-bit field specifies the horizontal Sync
End position expressed in terms of the absolute pixel number relative to the horizontal
active display start. The value programmed should be the HSYNC End pixel position,
0b where the first active pixel is considered position 0; the second active pixel is considered
28:16
RW position 1, etc. The number of clocks in the sync period needs to be a multiple of two
when driving data out the LVDS port in two channel mode. This value should be greater
than the horizontal sync start position and would be loaded with the
Active+RightBorder+FrontPorch+Sync-1.
0b
15:13 RESERVED_1: Read Only.
RW
PIPE_A_HORIZONTAL_SYNC_START: This 13-bit field specifies the horizontal Sync
Start position expressed in terms of the absolute pixel number relative to the horizontal
active display start. The value programmed should be the HSYNC Start pixel position,
where the first active pixel is considered position 0; the second active pixel is considered
0b position 1, etc. Note that when HSYNC Start is programmed equal to HBLANK Start,
12:0
RW both HSYNC and HBLANK will be asserted on the same pixel clock. It should never be
programmed to less than HBLANK start. The number of cycles from the beginning of the
line needs to be a multiple of two when driving data out the LVDS port in two channel
mode. This register should not be less than the horizontal active end. This register
should be loaded with the Active+RightBorder+FrontPorch-1.

14.10.153 VTOTAL_A—Offset 6000Ch

Pipe A Vertical Total Register

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) VTOTAL_A: [GTTMMADR_LSB + 2BF20h] + 6000Ch

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PIPE_A_VERTICAL_ACTIVE_DISPLAY_LINES
PIPE_A_VERTICAL_TOTAL_DISPLAY_LINES
RESERVED

RESERVED_1

Bay Trail-I SoC

Datasheet 457
 Graphics, Video and Display

Bit Default &

Description
Range Access

0b
31:29 RESERVED: Read Only.
RW
PIPE_A_VERTICAL_TOTAL_DISPLAY_LINES: This 13 bit field provides Vertical Total
up to 8192 lines encompassing the Vertical Active Display Lines, top/bottom border and
retrace period. The value programmed should be the number of lines required minus
0b one. Vertical total needs to be large enough to be greater than the sum of the vertical
28:16
RW active, vertical border, and the vertical blank regions. The vertical counter is
incremented on the leading edge of the horizontal sync. For interlaced display modes,
this indicates the total number of lines in both fields. In interlaced modes, hardware
automatically divides this number by 2 to get the number of lines in each field.
0b
15:12 RESERVED_1: Read Only.
RW
PIPE_A_VERTICAL_ACTIVE_DISPLAY_LINES: This 12-bit field provides vertical
active display resolutions up to 4096 lines. It should be programmed with the desired
0b number of lines minus one. When using the internal panel fitting logic, the minimum
11:0
RW vertical active area must be three lines. For interlaced display modes, this indicates the
total number of lines in both fields. In interlaced modes, hardware automatically divides
this number by 2 to get the number of lines in each field.

14.10.154 VBLANK_A—Offset 60010h

Pipe A Vertical Blank Register

Access Method
Type: Memory Mapped I/O Register
VBLANK_A: [GTTMMADR_LSB + 2BF20h] + 60010h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PIPE_A_VERTICAL_BLANK_START
PIPE_A_VERTICAL_BLANK_END
RESERVED

RESERVED_1

Bit Default &

Description
Range Access

0b
31:29 RESERVED: Read Only.
RW

Bay Trail-I SoC

458 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

PIPE_A_VERTICAL_BLANK_END: This 13-bit field specifies the Vertical Blank End

position expressed in terms of the absolute Line number relative to the vertical active
display start. The value programmed should be the VBLANK End line position, where the
first active line is considered line 0, the second active line is considered line 1, etc. The
0b end of vertical blank should be after the start of vertical blank and before or equal to the
28:16 vertical total. This register should be loaded with the Vactive+BottomBorder+VBlank-1.
RW For interlaced display modes, hardware automatically divides this number by 2 to get
the vertical blank end in each field. It does not count the two half lines that get added
when operating in modes with half lines. If this pipe is connected to the TVout port or
Panel Fitter 2 the border must be zero. In that case this register is programmed to the
same value as the VTOTAL register.

0b
15:13 RESERVED_1: Read Only.
RW

PIPE_A_VERTICAL_BLANK_START: This 13-bit field specifies the Vertical Blank Start

expressed in terms of the absolute line number relative to the vertical active display
start. The value programmed should be the VBLANK Start line position, where the first
active line is considered line 0, the second active line is considered line 1, etc. Minimum
0b vertical blank size is required to be at least three lines. Blank should start after the end
12:0 of active. This register is loaded with the Vactive+BottomBorder-1. For interlaced
RW display modes, hardware automatically divides this number by 2 to get the vertical
blank start in each field. It does not count the two half lines that get added when
operating in modes with half lines. If this pipe is connected to the TVout port or Panel
Fitter 2 the border must be zero. In that case this register is programmed to the same
value as the VACTIVE register.

14.10.155 VSYNC_A—Offset 60014h

Pipe A Vertical Sync Register

Access Method
Type: Memory Mapped I/O Register VSYNC_A: [GTTMMADR_LSB + 2BF20h] + 60014h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PIPE_A_VERTICAL_SYNC_END

RESERVED_1

PIPE_A_VERTICAL_SYNC_START
RESERVED

Bit Default &

Description
Range Access

0b
31:29 RESERVED: Read Only.
RW

Bay Trail-I SoC

Datasheet 459
 Graphics, Video and Display

Bit Default &

Description
Range Access

PIPE_A_VERTICAL_SYNC_END: This 13-bit field specifies the Vertical Sync End

position expressed in terms of the absolute Line number relative to the vertical active
display start. The value programmed should be the VSYNC End line position, where the
0b first active line is considered line 0, the second active line is considered line 1, etc. This
28:16
RW register should be loaded with Vactive+BottomBorder+FrontPorch+Sync-1. For
interlaced display modes, hardware automatically divides this number by 2 to get the
vertical sync end in each field. It does not count the two half lines that get added when
operating in modes with half lines.

0b
15:13 RESERVED_1: Read Only.
RW

PIPE_A_VERTICAL_SYNC_START: This 13-bit field specifies the Vertical Sync Start

position expressed in terms of the absolute line number relative to the vertical active
display start. The value programmed should be the VSYNC Start line position, where the
0b first active line is considered line 0, the second active line is considered line 1, etc. This
12:0
RW register would be loaded with Vactive+BottomBorder+FrontPorch-1. For interlaced
display modes, hardware automatically divides this number by 2 to get the vertical sync
start in each field. It does not count the two half lines that get added when operating in
modes with half lines.

14.10.156 PIPESRCA—Offset 6001Ch

Pipe A Source Image Size

Access Method
Type: Memory Mapped I/O Register PIPESRCA: [GTTMMADR_LSB + 2BF20h] + 6001Ch
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED_1

PIPE_A_VERTICAL_SOURCE_IMAGE_SIZE
RESERVED

PIPE_A_HORIZONTAL_SOURCE_IMAGE_SIZE

Bit Default &

Description
Range Access

0b
31:28 RESERVED: Write as zero
RW

Bay Trail-I SoC

460 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

PIPE_A_HORIZONTAL_SOURCE_IMAGE_SIZE: This 12-bit field specifies Horizontal

source image size up to 4096. This determines the size of the image created by the
display planes sent to the blender. The value programmed should be the source image
size minus one. The actual source size must be two times the programmed value in the
0b pixel multiply mode. It must represent a size that is a multiple of two (even numbers)
27:16
RW when driving the LVDS port in two channel mode. This implies that for this mode, the
value programmed will always be an odd number. Except in the case of panel fitting
internal or in an external device, this register field would be programmed to a value
identical to the horizontal active. This is the only register of the timing registers that is
allowed to be programmed while the pipe is enabled.
0b
15:12 RESERVED_1: Write as zero
RW
PIPE_A_VERTICAL_SOURCE_IMAGE_SIZE: This 12-bit field specifies the vertical
source image size up to 4096 lines. This determines the size of the image created by the
display planes sent to the blender. The value programmed should be the source image
0b size minus one. Note that the actual number of lines needs to be at least twice the
11:0 planes programmed value when in the pixel multiply mode. Except in the case of panel
RW fitting internal or in an external device, this register field would be programmed to a
value identical to the vertical active. For interlaced display modes, hardware
automatically divides this number by 2 to get the vertical source image size in each
field.

14.10.157 BCLRPAT_A—Offset 60020h

Pipe A Border Color Pattern Register

Access Method
Type: Memory Mapped I/O Register BCLRPAT_A: [GTTMMADR_LSB + 2BF20h] + 60020h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PIPE_A_BORDER_RED_CHANNEL_VALUE

PIPE_A_BORDER_GREEN_CHANNEL_VALUE

PIPE_A_BORDER_BLUE_CHANNEL_VALUE
RESERVED

Bay Trail-I SoC

Datasheet 461
 Graphics, Video and Display

Bit Default &

Description
Range Access

0b
31:24 RESERVED: Reserved.
RW
0b
23:16 PIPE_A_BORDER_RED_CHANNEL_VALUE: pipeA border red channel values
RW
0b
15:8 PIPE_A_BORDER_GREEN_CHANNEL_VALUE: pipeA border green channel values
RW
0b
7:0 PIPE_A_BORDER_BLUE_CHANNEL_VALUE: pipeA border blue channel values
RW

14.10.158 VSYNCSHIFT_A—Offset 60028h

Vertical Sync Shift Register

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) VSYNCSHIFT_A: [GTTMMADR_LSB + 2BF20h] + 60028h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PIPE_A_SECOND_FIELD_VERTICAL_SYNC_SHIFT
RESERVED

Bit Default &

Description
Range Access

0b
31:13 RESERVED: Write as zero.
RW

Bay Trail-I SoC

462 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

PIPE_A_SECOND_FIELD_VERTICAL_SYNC_SHIFT: This value specifies the vertical

sync alignment for the start of the interlaced second field expressed in terms of the
absolute pixel number relative to the horizontal active display start. This value will only
be used if the PIPEACONF is programmed to an interlaced mode using vsync shift.
0b Otherwise a legacy value of floor[htotal / 2] will be used. Typically, the interlaced second
12:0 field vertical sync should start one pixel after the point halfway between successive
RW horizontal syncs, so the value of this register should be programmed to: (horizontal
sync start - floor[horizontal total / 2]) (use the actual horizontal sync start and
horizontal total values and not the minus one values programmed into registers). This
vertical sync shift only occurs during the interlaced second field. In all other cases the
vertical sync start position is aligned with horizontal sync start.

14.10.159 TRANSADATAM1—Offset 60030h

Pipe A Data M value 1

Access Method
Type: Memory Mapped I/O Register
TRANSADATAM1: [GTTMMADR_LSB + 2BF20h] + 60030h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 7E000000h
31 28 24 20 16 12 8 4 0

0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0PIPE_A_DATA_M1_VALUE 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED

TU1_SIZE

RESERVED_1

Bit Default &

Description
Range Access

0b
31 RESERVED: Project: All Format: MBZ
RW
111111b
30:25 TU1_SIZE: Project: All This field is the size of the transfer unit for DP, minus one.
RW
0b
24 RESERVED_1: Project: All Format: MBZ
RW
0b PIPE_A_DATA_M1_VALUE: Project: All This field is the M1 value for internal use of
23:0
RW the DDA.

14.10.160 TRANSADATAN1—Offset 60034h

Pipe A Data N value 1

Access Method

Bay Trail-I SoC

Datasheet 463
 Graphics, Video and Display

Type: Memory Mapped I/O Register

TRANSADATAN1: [GTTMMADR_LSB + 2BF20h] + 60034h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED

PIPE_A_DATA_N1_VALUE
Bit Default &
Description
Range Access

0b
31:24 RESERVED: Project: All Format: MBZ
RW
0b PIPE_A_DATA_N1_VALUE: Project: All This field is the N1 value for internal use of
23:0
RW the DDA.

14.10.161 TRANSADATAM2—Offset 60038h

Pipe A Data M value 2

Access Method
Type: Memory Mapped I/O Register
TRANSADATAM2: [GTTMMADR_LSB + 2BF20h] + 60038h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 7E000000h
31 28 24 20 16 12 8 4 0

0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PIPE_A_DATA_M2_VALUE
TU2_SIZE
RESERVED

RESERVED_1

Bay Trail-I SoC

464 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

0b
31 RESERVED: Project: All Format: MBZ
RW
111111b TU2_SIZE: Project: All Default Value: ;111111b 64 This field is the size of the transfer
30:25
RW unit for DP, minus one.

0b
24 RESERVED_1: Project: All Format: MBZ
RW
0b PIPE_A_DATA_M2_VALUE: Project: All This field is the M2 value for internal use of
23:0
RW the DDA.

14.10.162 TRANSADATAN2—Offset 6003Ch

Pipe A Data N value 2

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) TRANSADATAN2: [GTTMMADR_LSB + 2BF20h] + 6003Ch

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PIPE_A_DATA_N2_VALUE
RESERVED

Bit Default &

Description
Range Access

0b
31:24 RESERVED: Project: All Format: MBZ
RW

0b PIPE_A_DATA_N2_VALUE: Project: All This field is the N2 value for internal use of
23:0
RW the DDA.

14.10.163 TRANSADPLINKM1—Offset 60040h

Pipe A Link M value 1

Access Method
Type: Memory Mapped I/O Register TRANSADPLINKM1: [GTTMMADR_LSB + 2BF20h] + 60040h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Bay Trail-I SoC

Datasheet 465
 Graphics, Video and Display

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PIPE_A_LINK_M1_VALUE
RESERVED

Bit Default &

Description
Range Access

0b
31:24 RESERVED: Project: All Format: MBZ
RW
0b PIPE_A_LINK_M1_VALUE: Project: All This field is the M1 value for external
23:0
RW transmission in the Main Stream Attributes.

14.10.164 TRANSADPLINKN1—Offset 60044h

Pipe A Link N value 1

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) TRANSADPLINKN1: [GTTMMADR_LSB + 2BF20h] + 60044h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED

PIPE_A_LINK_N1_VALUE

Bit Default &

Description
Range Access

0b
31:24 RESERVED: Project: All Format: MBZ
RW
0b PIPE_A_LINK_N1_VALUE: Project: All This field is the N1 value for external
23:0
RW transmission in the Main Stream Attributes and VB-ID.

Bay Trail-I SoC

466 Datasheet
Graphics, Video and Display

14.10.165 TRANSADPLINKM2—Offset 60048h

Pipe A Link M value 2

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) TRANSADPLINKM2: [GTTMMADR_LSB + 2BF20h] + 60048h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED

PIPE_A_LINK_M2_VALUE
Bit Default &
Description
Range Access

0b
31:24 RESERVED: Project: All Format: MBZ
RW

0b PIPE_A_LINK_M2_VALUE: Project: All This field is the M2 value for external

23:0
RW transmission in the Main Stream Attributes.

14.10.166 TRANSADPLINKN2—Offset 6004Ch

Pipe A Link N value 2

Access Method
Type: Memory Mapped I/O Register TRANSADPLINKN2: [GTTMMADR_LSB + 2BF20h] + 6004Ch
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED

PIPE_A_LINK_N2_VALUE

Bay Trail-I SoC

Datasheet 467
 Graphics, Video and Display

Bit Default &

Description
Range Access

0b
31:24 RESERVED: Project: All Format: MBZ
RW
0b PIPE_A_LINK_N2_VALUE: Project: All This field is the N2 value for external
23:0
RW transmission in the Main Stream Attributes and VB-ID.

14.10.167 CRCCTRLREDA—Offset 60050h

Pipe A CRC Color Channel Control Register (Red)

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) CRCCTRLREDA: [GTTMMADR_LSB + 2BF20h] + 60050h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENABLE_COLOR_CRC

RESERVED
CRC_SOURCE_SELECT

EXPECTED_CRC_VALUE

Bit Default &

Description
Range Access

ENABLE_COLOR_CRC: Enables the CRC calculations. After being enabled for the first
0b time, you need to wait for two VBLANK events for a valid CRC result. After that, a CRC
31
RW will be generated each frame. 0 = CRC Calculations are disabled 1 = CRC Calculations
are enabled
CRC_SOURCE_SELECT: These bits select the source of the data to put into the CRC
logic. 0000: Pipe A (Not available when DisplayPort or TV is enabled on this pipe)
[DevVLVP] 0001: sDVOB/HDMIB (30 bit format. Only select when HDMIB is set to
pipeA) [DevVLVP] 0010: sDVOC/HDMIC (30 bit format. Only select when HDMIC is set
0b to pipeA) [DevVLVP] 0011: DisplayPort D (40 bit format) [DevCTG] 0100: TV Encoder
30:27
RW outputs (30 bit format) 0101: TV filter outputs (30 bit format) 0110: DisplayPort B (40
bit format) [DevCTG, DevCDV, DevVLVP] 0111: DisplayPort C (40 bit format) [DevCTG,
DevCDV, DevVLVP] 1000: Audio DP (Audio for DisplayPort (pcdclk). Only select when
Audio is on DisplayPort on Pipe A) [DevVLVP] 1001: Audio HDMI (Audio for HDMI
(dotclock) Only select when Audio is on HDMI on Pipe A) Others: Reserved
0b
26:23 RESERVED: Write as zero
RW
EXPECTED_CRC_VALUE: Expected CRC Value for Color Channel. This is the value used
0b to generate the CRC error status and interrupt. Resultant CRC values are compared to
22:0
RW this register after the completion of a CRC calculation. Status indications are in the
PIPEASTAT register.

Bay Trail-I SoC

468 Datasheet
Graphics, Video and Display

14.10.168 CRCCTRLGREENA—Offset 60054h

Pipe A CRC Color Channel Control Register (, Residual)

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) CRCCTRLGREENA: [GTTMMADR_LSB + 2BF20h] + 60054h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED

EXPECTED_CRC_VALUE
Bit Default &
Description
Range Access

0b
31:23 RESERVED: Write as zero
RW
EXPECTED_CRC_VALUE: Expected CRC Value for Color Channel. This is the value used
0b to generate the CRC error status and interrupt. Resultant CRC values are compared to
22:0
RW this register after the completion of a CRC calculation. Status indications are in the
PIPEASTAT register.

14.10.169 CRCCTRLBLUEA—Offset 60058h

Pipe A CRC Color Channel Control Register

Access Method
Type: Memory Mapped I/O Register CRCCTRLBLUEA: [GTTMMADR_LSB + 2BF20h] + 60058h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

Datasheet 469
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESERVED

EXPECTED_CRC_VALUE
Bit Default &
Description
Range Access

0b
31:23 RESERVED: Write as zero
RW
EXPECTED_CRC_VALUE: Expected CRC Value for Color Channel. This is the value used
0b to generate the CRC error status and interrupt. Resultant CRC values are compared to
22:0
RW this register after the completion of a CRC calculation. Status indications are in the
PIPEASTAT register.

14.10.170 CRCCTRLALPHAA—Offset 6005Ch

Pipe A CRC Color Channel Control Register

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) CRCCTRLALPHAA: [GTTMMADR_LSB + 2BF20h] + 6005Ch

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED

EXPECTED_CRC_VALUE

Bit Default &

Description
Range Access

0b
31:23 RESERVED: Write as zero
RW

EXPECTED_CRC_VALUE: Expected CRC Value for Color Channel. This is the value used
0b to generate the CRC error status and interrupt. Resultant CRC values are compared to
22:0
RW this register after the completion of a CRC calculation. Status indications are in the
PIPEASTAT register.

Bay Trail-I SoC

470 Datasheet
Graphics, Video and Display

14.10.171 CRCRESREDA—Offset 60060h

Pipe A A CRC Color Channel Result Register

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) CRCRESREDA: [GTTMMADR_LSB + 2BF20h] + 60060h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED

COLOR_CHANNEL_CRC_RESULT_VALUE

Bit Default &

Description
Range Access

0b
31:23 RESERVED: Read only
RO

0b COLOR_CHANNEL_CRC_RESULT_VALUE: This field contains the resultant CRC value

22:0 for the particular Color Channel at the end of a frame. A status bit can be used as an
RO indication that the data is the valid result of a CRC calculation.

14.10.172 CRCRESGREENA—Offset 60064h

Pipe A A CRC Color Channel Result Register

Access Method
Type: Memory Mapped I/O Register CRCRESGREENA: [GTTMMADR_LSB + 2BF20h] + 60064h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

Datasheet 471
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESERVED

COLOR_CHANNEL_CRC_RESULT_VALUE
Bit Default &
Description
Range Access

0b
31:23 RESERVED: Read only
RO

0b COLOR_CHANNEL_CRC_RESULT_VALUE: This field contains the resultant CRC value

22:0 for the particular Color Channel at the end of a frame. A status bit can be used as an
RO indication that the data is the valid result of a CRC calculation.

14.10.173 CRCRESBLUEA—Offset 60068h

Pipe A A CRC Color Channel Result Register

Access Method
Type: Memory Mapped I/O Register
CRCRESBLUEA: [GTTMMADR_LSB + 2BF20h] + 60068h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
COLOR_CHANNEL_CRC_RESULT_VALUE
RESERVED

Bay Trail-I SoC

472 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

0b
31:23 RESERVED: Read only
RO

0b COLOR_CHANNEL_CRC_RESULT_VALUE: This field contains the resultant CRC value

22:0 for the particular Color Channel at the end of a frame. A status bit can be used as an
RO indication that the data is the valid result of a CRC calculation.

14.10.174 CRCRESALPHAA—Offset 6006Ch

Pipe A A CRC Color Channel Result Register

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) CRCRESALPHAA: [GTTMMADR_LSB + 2BF20h] + 6006Ch

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED

COLOR_CHANNEL_CRC_RESULT_VALUE

Bit Default &

Description
Range Access

0b
31:23 RESERVED: Read only
RO

0b COLOR_CHANNEL_CRC_RESULT_VALUE: This field contains the resultant CRC value

22:0 for the particular Color Channel at the end of a frame. A status bit can be used as an
RO indication that the data is the valid result of a CRC calculation.

14.10.175 CRCCTRLRESIDUE2A—Offset 60070h

Pipe A CRC Color Channel Control Register

Access Method

Bay Trail-I SoC

Datasheet 473
 Graphics, Video and Display

Type: Memory Mapped I/O Register

CRCCTRLRESIDUE2A: [GTTMMADR_LSB + 2BF20h] + 60070h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED

EXPECTED_CRC_VALUE
Bit Default &
Description
Range Access

0b
31:23 RESERVED: Write as zero
RW
EXPECTED_CRC_VALUE: Expected CRC Value for Color Channel. This is the value used
0b to generate the CRC error status and interrupt. Resultant CRC values are compared to
22:0
RW this register after the completion of a CRC calculation. Status indications are in the
PIPEASTAT register.

14.10.176 CRCRESRESIDUE2A—Offset 60080h

Pipe A CRC Color Channel Result Register

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) CRCRESRESIDUE2A: [GTTMMADR_LSB + 2BF20h] + 60080h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

474 Datasheet
Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESERVED

COLOR_CHANNEL_CRC_RESULT_VALUE
Bit Default &
Description
Range Access

0b
31:23 RESERVED: Read only
RO

0b COLOR_CHANNEL_CRC_RESULT_VALUE: This field contains the resultant CRC value

22:0 for the particular Color Channel at the end of a frame. A status bit can be used as an
RO indication that the data is the valid result of a CRC calculation.

14.10.177 PSRCTLA—Offset 60090h

Pipe A Panel Self Refresh Control

Access Method
Type: Memory Mapped I/O Register
PSRCTLA: [GTTMMADR_LSB + 2BF20h] + 60090h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

Datasheet 475
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DPLLA_POWER_DOWN_DELAY
IDENTICAL_FRAME_THRESHOLD

SOURCE_TRANSMITTER_STATE_IN_PSR_ACTIVE
DOUBLE_FRAMES_IN_PSR_ACTIVE_ENTRY

PSR_SINGLE_FRAME_UPDATE

PSR_ENABLE
RESERVED

PSR_ACTIVE_ENTRY

PSR_MODE

PSR_RESET
RESERVED_1
Bit Default &
Description
Range Access

0b
31:24 RESERVED: Reserved.
RW
0b IDENTICAL_FRAME_THRESHOLD: : Number of identical frames that display
23:16
RW controller needs to exceed in order to transition to PSR active state in HW timer mode

0b DPLLA_POWER_DOWN_DELAY: programmable delay from main link powerdown to

15:11
RW DPLLA powerdown. The delay is in number of cdclk clocks.

0b DOUBLE_FRAMES_IN_PSR_ACTIVE_ENTRY: . If asserted, HW will send two frames

10 with same SDP active setting when entry PSR active state. This bit is set if the vertical
RW blanking time is less than 330us.
SOURCE_TRANSMITTER_STATE_IN_PSR_ACTIVE: . If asserted, HW will keep
0b transmitter active during PSR active state and sends only idle symbols. If deasserted,
9
RW HW will turn off transmitter during PSR active state. Display driver will keep this bit
consistent with Source transmitter state in PSR active bit in DPCD register of the sink.
PSR_ACTIVE_ENTRY: This bit is only valid in PSR_mode is SW timer mode. If it is
0b asserted, HW will transition into PSR_active state. If it is deasserted, HW will transition
8
RW to PSR_inactive state. SW should not set or clear this bit more than once within one
vblank period.
PSR_SINGLE_FRAME_UPDATE: In PSR persistent mode, SW set this bit before
writing registers for a flip. After HW finishes signle frame update, it goes back to PSR
0b active ? no RFB state. SW driver may send new single frame update request.
7 Programming note: Reading this bit is updated at the next vblank. Writing this bit to 1
RW will cause PSR FSM to perform single frame update automatically, no vblank is required.
When single frame update is done, it will automatically go back to PSR active ? no RFB
update. 60094[2:0] = 3b011.

0b
6:5 RESERVED_1: Reserved.
RW

PSR_MODE: b011-111: reserved. b010: PSR with HW timer. HW timer decides PSR
active entry point. PSR active state exits upon MMIO write registers that may change
0b the frame buffer. b001: PSR with SW timer. In this mode, SW will keep track of idle
4:2 frames and buffer modification in the driver and explicitly specify the entry and exit PSR
RW active state point. b000: PSR manual (debug) mode. All of PSR state transitions and
SDP content is managed by SW driver. SW is responsible to change SDP content for
every frame with appropriate values to keep PSR panel in synchronized states.

Bay Trail-I SoC

476 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

0b PSR_RESET: If assert all PSR functions are reset back to PSR inactive state. When it
1 needs to resynchronize source and sync, SW writes 0x2 to DPCD register 600h and to
RW this bit to get system back to PSR active states. This bit is self clear.
0b PSR_ENABLE: Panel Self-refresh is enabled. When it is asserted PSR is enabled and
0
RW operate in one of the mode that specified by PSR mode.

14.10.178 PSRSTATA—Offset 60094h

Pipe A PSR status register

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) PSRSTATA: [GTTMMADR_LSB + 2BF20h] + 60094h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DISPLAY_LOCAL_STANDBY_STATE

REPEAT_FRAME_COUNTER

PSR_IN_TRANSITION
RESERVED_1

SDP_SENT

RESERVED_2

PSR_LAST_STATE
RESERVED

PSR_CURRENT_STATE
Bit Default &
Description
Range Access

0b DISPLAY_LOCAL_STANDBY_STATE: :00: D0 idle state, fetch frame buffer from

31:30 system memory 01: D0i1 not defined in VLVP 02: D0i2 PSR is active, display controller
RO is trunk gated 03: D0i3 PSR is active, display controller is power gated
0b
29:24 RESERVED: Reserved.
RO
0b REPEAT_FRAME_COUNTER: : Number of identical frames has been sent by display
23:16
RO controller. Value is not roll over at 255.

0b
15:9 RESERVED_1: Reserved.
RO
0b
8 SDP_SENT: it indicates if SDP packet has been sent in current frame.
RO

0b PSR_IN_TRANSITION: There is a period that source already committed to PSR active

7 but sink did not. SW should not change the source state at this time but wait until this
RO status bit is clear. The wait time should in the range of 120-250us in the worst case.
0b
6 RESERVED_2: Reserved.
RO

Bay Trail-I SoC

Datasheet 477
 Graphics, Video and Display

Bit Default &

Description
Range Access

0b PSR_LAST_STATE: indicate last source state that VLVP PSR state machine were in
5:3 (debug) 000: PSR_disabled 001: PSR_inactive 010: PSR_transition_to_active 011:
RO PSR_active no RFB update 100: PSR_active single frame update 101: PSR_exit

0b PSR_CURRENT_STATE: indicate current source state that VLVP PSR state machine are
2:0 in 000: PSR_disabled 001: PSR_inactive 010: PSR_transition_to_active 011: PSR_active
RO no RFB update 100: PSR_active single frame update 101: PSR_exit

14.10.179 PSRCRC1A—Offset 60098h

Pipe A PSR CRC1 register

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) PSRCRC1A: [GTTMMADR_LSB + 2BF20h] + 60098h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CRC_VALUE_BITS_15_0_OF_R_COMPONENT

RESERVED

CRC_VALID

Bit Default &

Description
Range Access

0b CRC_VALUE_BITS_15_0_OF_R_COMPONENT: crc values bits 15 to 0 of Red

31:16
RO component

0b
15:1 RESERVED: Reserved.
RO

0b
0 CRC_VALID: CRC calculation complete and valid for previous frame.
RO

14.10.180 PSRCRC2A—Offset 6009Ch

Pipe A PSR CRC2 register

Access Method

Bay Trail-I SoC

478 Datasheet
Graphics, Video and Display

Type: Memory Mapped I/O Register

PSRCRC2A: [GTTMMADR_LSB + 2BF20h] + 6009Ch
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CRC_VALUE_BITS_15_0_OF_B_COMPONENT

CRC_VALUE_BITS_15_0_OF_G_COMPONENT
Bit Default &
Description
Range Access

0b CRC_VALUE_BITS_15_0_OF_B_COMPONENT: crc values bits 15 to 0 of Blue

31:16
RO component

0b CRC_VALUE_BITS_15_0_OF_G_COMPONENT: crc values bits 15 to 0 of green

15:0
RO component

14.10.181 VSCSDPA—Offset 600A0h

Pipe A VSC SDP register

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) VSCSDPA: [GTTMMADR_LSB + 2BF20h] + 600A0h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

Datasheet 479
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SDP_SEND_FREQUENCY

RESERVED

DB1

DB0
Bit Default &
Description
Range Access

SDP_SEND_FREQUENCY: 00: off, not sending 01: send one every frame 10: send
0b once 11: reserved Programming note: This field shall be programmed either send once
31:30 or send one every frame when SW driver sets PSR active entry bit. When PSR is
RW enabling this field is ignored. One SDP is sent in every frame until source is in PSR active
state
0b
29:16 RESERVED: Reserved.
RW
0b DB1: : Programmed by display driver in manual mode, auto-generate by display
15:8
RW controller in all other modes

0b DB0: : Bits 7:4: Stereo Interface Method Specific ParameterBits 3:0: Stereo Interface
7:0
RW Method Code. This field is programmed by display driver for stereo display configuration

14.10.182 PIPEAWIDEGAMUTCOLORCORRECTIONC01_C00COEFFICIENTS
—Offset 600B0h
When color correction matrix enable bit is set in PIPEACONF register, each of pixels in
the pipe is multiplied with this matrix. Color matrix is used to convert pixels from one
RGB color space to another RGB color space. There are many applications for the use of
this matrix like gamut mapping between 72 percent color gamut to 92 percent color
gamut. Each coefficient is a 12-bit signed fixed-point number. The application of
coefficients are as follows:

Access Method
Type: Memory Mapped I/O Register PIPEAWIDEGAMUTCOLORCORRECTIONC01_C00COEFFICIE
(Size: 32 bits) NTS: [GTTMMADR_LSB + 2BF20h] + 600B0h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
C01_COEFFICIENT

C00_COEFFICIENT
RESERVED

RESERVED_1

Bay Trail-I SoC

480 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

0b
31:28 RESERVED: Reserved.
RW
0b C01_COEFFICIENT: 12-bit 2 s complement signed value that is programmed for linea.
27:16
RW The range of the value can be from -1.999 to +1.999.

0b
15:12 RESERVED_1: Reserved.
RW
0b C00_COEFFICIENT: 12-bit 2 s complement signed value that is programmed for linea.
11:0
RW The range of the value can be from -1.999 to +1.999.

14.10.183 PIPEAWIDEGAMUTCOLORCORRECTIONC02COEFFICIENT—
Offset 600B4h
Refer to the description of the Pipe A Wide Gamut Color Correction C01_C00 register.

Access Method
Type: Memory Mapped I/O Register PIPEAWIDEGAMUTCOLORCORRECTIONC02COEFFICIENT:
(Size: 32 bits) [GTTMMADR_LSB + 2BF20h] + 600B4h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

C02_COEFFICIENT
RESERVED

Bit Default &

Description
Range Access

0b
31:12 RESERVED: Reserved.
RW
0b C02_COEFFICIENT: 12-bit 2 s complement signed value that is programmed for linea.
11:0
RW The range of the value can be from -1.999 to +1.999.

14.10.184 PIPEAWIDEGAMUTCOLORCORRECTIONC11_C10COEFFICIENTS
—Offset 600B8h
Refer to the description of the Pipe A Wide Gamut Color Correction C01_C00 register.

Access Method

Bay Trail-I SoC

Datasheet 481
 Graphics, Video and Display

Type: Memory Mapped I/O Register PIPEAWIDEGAMUTCOLORCORRECTIONC11_C10COEFFICIE

(Size: 32 bits) NTS: [GTTMMADR_LSB + 2BF20h] + 600B8h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

C11_COEFFICIENT

C10_COEFFICIENT
RESERVED

RESERVED_1
Bit Default &
Description
Range Access

0b
31:28 RESERVED: Reserved.
RW

0b C11_COEFFICIENT: 12-bit 2 s complement signed value that is programmed for linea.

27:16
RW The range of the value can be from -1.999 to +1.999.

0b
15:12 RESERVED_1: Reserved.
RW

0b C10_COEFFICIENT: 12-bit 2 s complement signed value that is programmed for linea.

11:0
RW The range of the value can be from -1.999 to +1.999.

14.10.185 PIPEAWIDEGAMUTCOLORCORRECTIONC12COEFFICIENT—
Offset 600BCh
Refer to the description of the Pipe A Wide Gamut Color Correction C01_C00 register.

Access Method
Type: Memory Mapped I/O Register PIPEAWIDEGAMUTCOLORCORRECTIONC12COEFFICIENT:
(Size: 32 bits) [GTTMMADR_LSB + 2BF20h] + 600BCh

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED

C12_COEFFICIENT

Bay Trail-I SoC

482 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

0b
31:12 RESERVED: Reserved.
RW
0b C12_COEFFICIENT: 12-bit 2 s complement signed value that is programmed for linea.
11:0
RW The range of the value can be from -1.999 to +1.999.

14.10.186 PIPEAWIDEGAMUTCOLORCORRECTIONC21_C20COEFFICIENTS
—Offset 600C0h
Refer to the description of the Pipe A Wide Gamut Color Correction C01_C00 register.

Access Method
Type: Memory Mapped I/O Register PIPEAWIDEGAMUTCOLORCORRECTIONC21_C20COEFFICIE
(Size: 32 bits) NTS: [GTTMMADR_LSB + 2BF20h] + 600C0h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED

C21_COEFFICIENT

C20_COEFFICIENT
RESERVED_1

Bit Default &

Description
Range Access

0b
31:28 RESERVED: Reserved.
RW
0b C21_COEFFICIENT: 12-bit 2 s complement signed value that is programmed for linea.
27:16
RW The range of the value can be from -1.999 to +1.999.

0b
15:12 RESERVED_1: Reserved.
RW
0b C20_COEFFICIENT: 12-bit 2 s complement signed value that is programmed for linea.
11:0
RW The range of the value can be from -1.999 to +1.999.

14.10.187 PIPEAWIDEGAMUTCOLORCORRECTIONC22COEFFICIENT—
Offset 600C4h
Refer to the description of the Pipe A Wide Gamut Color Correction C01_C00 register.

Access Method

Bay Trail-I SoC

Datasheet 483
 Graphics, Video and Display

Type: Memory Mapped I/O Register PIPEAWIDEGAMUTCOLORCORRECTIONC22COEFFICIENT:

(Size: 32 bits) [GTTMMADR_LSB + 2BF20h] + 600C4h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

C22_COEFFICIENT
RESERVED

Bit Default &

Description
Range Access

0b
31:12 RESERVED: Reserved.
RW

0b C22_COEFFICIENT: 12-bit 2 s complement signed value that is programmed for linea.

11:0
RW The range of the value can be from -1.999 to +1.999.

14.10.188 VIDEO_DIP_CTL_A—Offset 60200h

Video DIP Control for Pipe A

Access Method
Type: Memory Mapped I/O Register VIDEO_DIP_CTL_A: [GTTMMADR_LSB + 2BF20h] + 60200h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 20200900h
31 28 24 20 16 12 8 4 0

0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0
DATA_ISLAND_PACKET_TYPE_ENABLE
ENABLE_GRAPHICS_DATA_ISLAND_PACKET

PORT_SELECT

VIDEO_DIP_TRANSMISSION_FREQUENCY

VIDEO_DIP_RAM_ACCESS_ADDRESS
GCP_DIP_ENABLE

DIP_BUFFER_INDEX

VIDEO_DIP_BUFFER_SIZE
RESERVED

RESERVED_1

RESERVED_2

RESERVED_3

Bay Trail-I SoC

484 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

0b ENABLE_GRAPHICS_DATA_ISLAND_PACKET: mode (bit #9 of port control register)

31
RW overrides this behavior.

PORT_SELECT: Project: All Default Value: 01b Digital Port B This selects which port is
01b to transmit the data island. This field must not be changed while data island
30:29 transmission is enabled. Value Name Description Project 00b Reserved Reserved All 01b
RW Digital Port B Digital Port B (Default) All 10b Digital Port C Digital Port C All 11b
Reserved Reserved All
0b
28:26 RESERVED: Project: All Format:
RW
GCP_DIP_ENABLE: Project: All Default Value: 0b This bit enables the output of the
General Control Packet. GCP is different from other DIPs in that much of the payload is
0b automatically reflected in the packet, and therefore a DIP buffer for GCP is not needed.
25 Please refer to the GCP payload register for payload details. Writes to this bit take effect
RW immediately. This bit should not be enabled for 8bpc mode if at least one of the other
HDMI ports is enabled in 12bpc mode. Value Name Description Project 0b Disable GCP
DIP disabled All 1b Enable GCP DIP enabled All
DATA_ISLAND_PACKET_TYPE_ENABLE: Project: All Default Value: 0001b Enable
AVI DIP These bits enable the output of a given data island packet (DIP) type. It can be
updated while the port is enabled and is immediately updated (not double-buffered).
0001b Within 2 vblank periods, the DIP is guaranteed to have been transmitted. Value Name
24:21
RW Description Project XXX1b Enable AVI Enable AVI DIP (Default = enabled) All XX1Xb
Enable Vendor Enable Vendor-specific DIP (Default = disabled) All X1XXb Enable Gamut
Enable Gamut Metadata Packet (Default = disabled) All 1XXXb Enable Source Enable
Source Product Description DIP (Default = disabled) All
DIP_BUFFER_INDEX: Project: All Default Value: 00b This field is used during
programming of different DIPs. These bits are used as an index to their respective DIP
0b buffers. The transmission frequency must also be written when programming the buffer.
20:19
RW Value Name Description Project 00b AVI AVI DIP (31 bytes of space available) All 01b
Vendor-specific Vendor-specific DIP All 10b Reserved Reserved All 11b Source Product
Source Product Description DIP All
0b
18 RESERVED_1: Project: All Format:
RW
VIDEO_DIP_TRANSMISSION_FREQUENCY: Project: All Default Value: 00b These
bits dictate the frequency of Video DIP transmission for the DIP buffer index designated
in bits 20:19. When writing Video DIP data, this value is also latched when the first DW
0b of the Video DIP is written. When read, this value reflects the Video DIP transmission
17:16
RW frequency for the Video DIP buffer designated in bits 20:19. This field shall be ignored
for Gamut Metadata Packet transmission. Value Name Description Project 00b Send
Once Send Once All 01b Every VSync Send Every VSync (Default for AVI) All 10b Every
Other Vsync Send at least every other VSync All 11b Reserved Reserved All
0b
15:12 RESERVED_2: Project: All Format: MBZ
RW
VIDEO_DIP_BUFFER_SIZE: Project: All AccessType: Read Only Default Value: ;1001b
1001b This reflects the buffer size in dwords available for the type of Video DIP being indexed
11:8 by bits 20:19 of this register, including the header. It is hardwired to the maximum size
RO of a Video DIP, 36 bytes. Please note that this count includes ECC bytes, which are not
writable by software. These bits are immediately valid after write of the DIP index.

0b
7:4 RESERVED_3: Project: All Format: MBZ
RW

VIDEO_DIP_RAM_ACCESS_ADDRESS: Project: All AccessType: Read Only Selects

the DWORD address for access to the Video DIP buffers. This value is automatically
0b incremented after each read or write of the Video DIP Data Register. The value wraps
3:0
RO back to zero when it autoincrements past the max address value of 0xF. This field
change takes effect immediately after being written. The read value indicates the
current access address.

Bay Trail-I SoC

Datasheet 485
 Graphics, Video and Display

14.10.189 VIDEO_DIP_DATA_A—Offset 60208h

Video Data Island Packet Data for Pipe A

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) VIDEO_DIP_DATA_A: [GTTMMADR_LSB + 2BF20h] + 60208h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

VIDEO_DIP_DATA

Bit Default &

Description
Range Access

VIDEO_DIP_DATA: Project: All When read, this returns the current value at the
location specified in the Video DIP buffer index select and Video DIP RAM access address
0b fields. The index used to address the RAM is incremented after each read or write of this
31:0
RW register. DIP data can be read at any time. Data should be loaded into the RAM before
enabling the transmission through the DIP type enable bit. Accesses to this register are
on a per-DWORD basis.

14.10.190 VIDEO_DIP_GDCP_PAYLOAD_A—Offset 60210h

Video Data Island Payload for Pipe A

Access Method
Type: Memory Mapped I/O Register VIDEO_DIP_GDCP_PAYLOAD_A: [GTTMMADR_LSB + 2BF20h]
(Size: 32 bits) + 60210h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

486 Datasheet
Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GCP_DEFAULT_PHASE_ENABLE
RESERVED

GCP_AV_MUTE
GCP_COLOR_INDICATION
Bit Default &
Description
Range Access

0b
31:3 RESERVED: Project: All Format: MBZ
RW
GCP_COLOR_INDICATION: Project: All Default Value: 0b This bit must be set when in
deep color mode. It may optionally be set for 24-bit mode. It must be set if the sink
0b attached to Pipe A can receive GCP data. Value Name Description Project 0b Dont
2
RW Indicate Dont indicate color depth. CD and PP bits in GCP set to zero All 1b Indicate
Indicate color depth using CD bits in GCP. It will be set depending on programmed pixel
depth in port control register All
GCP_DEFAULT_PHASE_ENABLE: Project: All Default Value: 0b Indicates the video
timings meet alignment requirements such that the following conditions are met: Htotal
0b is an even number Hactive is an even number Hsync is an even number Front and back
1 porches for Hsync are even numbers Vsync always starts on an even-numbered pixel
RW within a line in interlaced modes (starting counting with 0) Value Name Description
Project 0b Clear Default phase bit in GCP is cleared All 1b Require Met Default phase bit
in GCP is set. All requirements must be met before setting this bit All

GCP_AV_MUTE: Project: All Default Value: 0b Set AV mute bit in GCP Value Name
0b Description Project 0b Clear AV mute bit in GCP is cleared. When this bit transitions to 0,
0
RW the AV mute clear flag is sent in the next GCP packet All 1b Set AV mute bit in GCP is
set. When this bit transitions to 1, the AV mute set flag is sent in the next GCP packet All

14.10.191 HTOTAL_B—Offset 61000h

Pipe B Horizontal Total Register

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) HTOTAL_B: [GTTMMADR_LSB + 2BF20h] + 61000h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

Datasheet 487
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PIPE_B_HORIZONTAL_ACTIVE_DISPLAY
RESERVED

PIPE_B_HORIZONTAL_TOTAL_DISPLAY

RESERVED_1
Bit Default &
Description
Range Access

0b
31:29 RESERVED: Write as zero.
RW

0b
28:16 PIPE_B_HORIZONTAL_TOTAL_DISPLAY: See pipe A description.
RW

0b
15:12 RESERVED_1: Write as zero.
RW

0b
11:0 PIPE_B_HORIZONTAL_ACTIVE_DISPLAY: See pipe A description
RW

14.10.192 HBLANK_B—Offset 61004h

Pipe B Horizontal Blank Register

Access Method
Type: Memory Mapped I/O Register HBLANK_B: [GTTMMADR_LSB + 2BF20h] + 61004h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

488 Datasheet
Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PIPE_B_HORIZONTAL_BLANK_START
PIPE_B_HORIZONTAL_BLANK_END
RESERVED

RESERVED_1
Bit Default &
Description
Range Access

0b
31:29 RESERVED: . Write as zero.
RW
0b
28:16 PIPE_B_HORIZONTAL_BLANK_END: See pipe A description
RW
0b
15:13 RESERVED_1: Write as zero.
RW
0b
12:0 PIPE_B_HORIZONTAL_BLANK_START: See pipe A description.
RW

14.10.193 HSYNC_B—Offset 61008h

Pipe B Horizontal Sync Register

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) HSYNC_B: [GTTMMADR_LSB + 2BF20h] + 61008h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

Datasheet 489
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESERVED

PIPE_B_HORIZONTAL_SYNC_START
PIPE_B_HORIZONTAL_SYNC_END

RESERVED_1
Bit Default &
Description
Range Access

0b
31:29 RESERVED: Write as zero.
RW

0b
28:16 PIPE_B_HORIZONTAL_SYNC_END: See pipe A description.
RW

0b
15:13 RESERVED_1: Write as zero.
RW

0b
12:0 PIPE_B_HORIZONTAL_SYNC_START: See pipe A description
RW

14.10.194 VTOTAL_B—Offset 6100Ch

Pipe B Vertical Total Register

Access Method
Type: Memory Mapped I/O Register VTOTAL_B: [GTTMMADR_LSB + 2BF20h] + 6100Ch
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

490 Datasheet
Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PIPE_B_VERTICAL_TOTAL_DISPLAY

PIPE_B_VERTICAL_ACTIVE_DISPLAY
RESERVED

RESERVED_1
Bit Default &
Description
Range Access

0b
31:29 RESERVED: Write as zero.
RW

0b
28:16 PIPE_B_VERTICAL_TOTAL_DISPLAY: See pipe A description.
RW

0b
15:12 RESERVED_1: Write as zero.
RW

0b
11:0 PIPE_B_VERTICAL_ACTIVE_DISPLAY: See pipe A description.
RW

14.10.195 VBLANK_B—Offset 61010h

Pipe B Vertical Blank Register

Access Method
Type: Memory Mapped I/O Register VBLANK_B: [GTTMMADR_LSB + 2BF20h] + 61010h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED

PIPE_B_VERTICAL_BLANK_END

PIPE_B_VERTICAL_BLANK_START
RESERVED_1

Bay Trail-I SoC

Datasheet 491
 Graphics, Video and Display

Bit Default &

Description
Range Access

0b
31:29 RESERVED: Write as zero.
RW
0b
28:16 PIPE_B_VERTICAL_BLANK_END: See pipe A description.
RW
0b
15:13 RESERVED_1: Write as zero.
RW
0b
12:0 PIPE_B_VERTICAL_BLANK_START: See pipe A description.
RW

14.10.196 VSYNC_B—Offset 61014h

Pipe B Vertical Sync Register

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) VSYNC_B: [GTTMMADR_LSB + 2BF20h] + 61014h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED_1

PIPE_B_VERTICAL_SYNC_START
RESERVED

PIPE_B_VERTICAL_SYNC_END

Bit Default &

Description
Range Access

0b
31:29 RESERVED: Write as zero.
RW
0b
28:16 PIPE_B_VERTICAL_SYNC_END: See pipe A description.
RW
0b
15:13 RESERVED_1: Write as zero.
RW
0b
12:0 PIPE_B_VERTICAL_SYNC_START: See pipe A description.
RW

14.10.197 PIPEBSRC—Offset 6101Ch

Pipe B Source Image Size

Bay Trail-I SoC

492 Datasheet
Graphics, Video and Display

Access Method
Type: Memory Mapped I/O Register
PIPEBSRC: [GTTMMADR_LSB + 2BF20h] + 6101Ch
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PIPE_B_VERTICAL_SOURCE_IMAGE_SIZE
RESERVED

PIPE_B_HORIZONTAL_SOURCE_IMAGE_SIZE

RESERVED_1

Bit Default &

Description
Range Access

0b
31:28 RESERVED: Write as zero
RW
0b
27:16 PIPE_B_HORIZONTAL_SOURCE_IMAGE_SIZE: See pipe A description.
RW
0b
15:12 RESERVED_1: Write as zero
RW

0b
11:0 PIPE_B_VERTICAL_SOURCE_IMAGE_SIZE: See pipe A description.
RW

14.10.198 BCLRPAT_B—Offset 61020h

Pipe B Border Color Pattern Register

Access Method
Type: Memory Mapped I/O Register BCLRPAT_B: [GTTMMADR_LSB + 2BF20h] + 61020h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

Datasheet 493
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PIPE_B_BLUE_CHANNEL_COLOR_VALUE
RESERVED

PIPE_B_RED_CHANNEL_COLOR_VALUE

PIPE_B_GREEN_CHANNEL_COLOR_VALUE
Bit Default &
Description
Range Access

0b
31:24 RESERVED: Reserved.
RW
0b
23:16 PIPE_B_RED_CHANNEL_COLOR_VALUE: pipeB red color channel values
RW
0b
15:8 PIPE_B_GREEN_CHANNEL_COLOR_VALUE: pipeB green color channel values
RW
0b
7:0 PIPE_B_BLUE_CHANNEL_COLOR_VALUE: pipeB blue color channel values
RW

14.10.199 VSYNCSHIFT_B—Offset 61028h

Vertical Sync Shift Register

Access Method
Type: Memory Mapped I/O Register VSYNCSHIFT_B: [GTTMMADR_LSB + 2BF20h] + 61028h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

494 Datasheet
Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESERVED

PIPE_B_SECOND_FIELD_VERTICAL_SYNC_SHIFT
Bit Default &
Description
Range Access

0b
31:13 RESERVED: Write as zero.
RW
PIPE_B_SECOND_FIELD_VERTICAL_SYNC_SHIFT: This value specifies the vertical
sync alignment for the start of the interlaced second field expressed in terms of the
absolute pixel number relative to the horizontal active display start. This value will only
be used if the PIPEBCONF is programmed to an interlaced mode using vsync shift.
0b Otherwise a legacy value of floor[htotal / 2] will be used. Typically, the interlaced second
12:0 field vertical sync should start one pixel after the point halfway between successive
RW horizontal syncs, so the value of this register should be programmed to: (horizontal
sync start - floor[horizontal total / 2]) (use the actual horizontal sync start and
horizontal total values and not the minus one values programmed into registers). This
vertical sync shift only occurs during the interlaced second field. In all other cases the
vertical sync start position is aligned with horizontal sync start.

14.10.200 TRANSBDATAM1—Offset 61030h

Pipe B Data M value 1

Access Method
Type: Memory Mapped I/O Register
TRANSBDATAM1: [GTTMMADR_LSB + 2BF20h] + 61030h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 7E000000h

Bay Trail-I SoC

Datasheet 495
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED

TU1_SIZE

PIPE_B_DATA_M1_VALUE
RESERVED_1

Bit Default &

Description
Range Access

0b
31 RESERVED: Project: All Format: MBZ
RW
111111b
30:25 TU1_SIZE: Project: All Default Value: ;111111b 64 See Pipe A description.
RW
0b
24 RESERVED_1: Project: All Format: MBZ
RW
0b
23:0 PIPE_B_DATA_M1_VALUE: Project: All See Pipe A description.
RW

14.10.201 TRANSBDATAN1—Offset 61034h

Pipe B Data N value 1

Access Method
Type: Memory Mapped I/O Register
TRANSBDATAN1: [GTTMMADR_LSB + 2BF20h] + 61034h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PIPE_B_DATA_N1_VALUE
RESERVED

Bit Default &

Description
Range Access

0b
31:24 RESERVED: Project: All Format: MBZ
RW

Bay Trail-I SoC

496 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

0b
23:0 PIPE_B_DATA_N1_VALUE: Project: All See Pipe A description.
RW

14.10.202 TRANSBDATAM2—Offset 61038h

Pipe B Data M value 2

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) TRANSBDATAM2: [GTTMMADR_LSB + 2BF20h] + 61038h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 7E000000h
31 28 24 20 16 12 8 4 0

0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PIPE_B_DATA_M2_VALUE
RESERVED

RESERVED_1
TU2_SIZE

Bit Default &

Description
Range Access

0b
31 RESERVED: Project: All Format: MBZ
RW

111111b
30:25 TU2_SIZE: Project: All Default Value: ;111111b 64 See Pipe A description.
RW

0b
24 RESERVED_1: Project: All Format: MBZ
RW

0b
23:0 PIPE_B_DATA_M2_VALUE: Project: All See Pipe A description.
RW

14.10.203 TRANSBDATAN2—Offset 6103Ch

Pipe B Data N value 2

Access Method
Type: Memory Mapped I/O Register TRANSBDATAN2: [GTTMMADR_LSB + 2BF20h] + 6103Ch
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

Datasheet 497
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESERVED

PIPE_B_DATA_N2_VALUE
Bit Default &
Description
Range Access

0b
31:24 RESERVED: Project: All Format: MBZ
RW
0b
23:0 PIPE_B_DATA_N2_VALUE: Project: All See Pipe A description.
RW

14.10.204 TRANSBDPLINKM1—Offset 61040h

Pipe B Link M value 1

Access Method
Type: Memory Mapped I/O Register
TRANSBDPLINKM1: [GTTMMADR_LSB + 2BF20h] + 61040h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PIPE_B_LINK_M1_VALUE
RESERVED

Bit Default &

Description
Range Access

0b
31:24 RESERVED: Project: All Format: MBZ
RW

0b
23:0 PIPE_B_LINK_M1_VALUE: Project: All See Pipe A description.
RW

14.10.205 TRANSBDPLINKN1—Offset 61044h

Pipe B Link N value 1

Bay Trail-I SoC

498 Datasheet
Graphics, Video and Display

Access Method
Type: Memory Mapped I/O Register
TRANSBDPLINKN1: [GTTMMADR_LSB + 2BF20h] + 61044h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PIPE_B_LINK_N1_VALUE
RESERVED

Bit Default &

Description
Range Access

0b
31:24 RESERVED: Project: All Format: MBZ
RW
0b
23:0 PIPE_B_LINK_N1_VALUE: Project: All See Pipe A description.
RW

14.10.206 TRANSBDPLINKM2—Offset 61048h

Pipe B Link M value 2

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) TRANSBDPLINKM2: [GTTMMADR_LSB + 2BF20h] + 61048h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PIPE_B_LINK_M2_VALUE
RESERVED

Bay Trail-I SoC

Datasheet 499
 Graphics, Video and Display

Bit Default &

Description
Range Access

0b
31:24 RESERVED: Project: All Format: MBZ
RW
0b
23:0 PIPE_B_LINK_M2_VALUE: Project: All See Pipe A description.
RW

14.10.207 TRANSBDPLINKN2—Offset 6104Ch

Pipe B Link N value 2

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) TRANSBDPLINKN2: [GTTMMADR_LSB + 2BF20h] + 6104Ch

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED

PIPE_B_LINK_N2_VALUE

Bit Default &

Description
Range Access

0b
31:24 RESERVED: Project: All Format: MBZ
RW
0b
23:0 PIPE_B_LINK_N2_VALUE: Project: All See Pipe A description.
RW

Bay Trail-I SoC

500 Datasheet
Graphics, Video and Display

Bay Trail-I SoC

Datasheet 501
 Graphics, Video and Display

14.11 Memory Mapped Registers (2 of 2)

Table 160. Summary of Display Memory Mapped I/O Registers—GTTMMADR_LSB

Default
Offset Size Register ID—Description
Value

61050h 4 “CRCCTRLREDB—Offset 61050h” on page 511 00000000h

61054h 4 “CRCCTRLGREENB—Offset 61054h” on page 512 00000000h

61058h 4 “CRCCTRLBLUEB—Offset 61058h” on page 513 00000000h
6105Ch 4 “CRCCTRLALPHAB—Offset 6105Ch” on page 514 00000000h

61060h 4 “CRCRESREDB—Offset 61060h” on page 514 00000000h

61064h 4 “CRCRESGREENB—Offset 61064h” on page 515 00000000h
61068h 4 “CRCRESBLUEB—Offset 61068h” on page 516 00000000h

6106Ch 4 “CRCRESALPHAB—Offset 6106Ch” on page 516 00000000h

61070h 4 “CRCCTRLRESIDUE2B—Offset 61070h” on page 517 00000000h
61080h 4 “CRCRESRESIDUAL2B—Offset 61080h” on page 518 00000000h

61090h 4 “PSRCTLB—Offset 61090h” on page 519 00000000h

61094h 4 “PSRSTATB—Offset 61094h” on page 520 00000000h
61098h 4 “PSRCRC1B—Offset 61098h” on page 521 00000000h

6109Ch 4 “PSRCRC2B—Offset 6109Ch” on page 522 00000000h

610A0h 4 “VSCSDPB—Offset 610A0h” on page 523 00000000h
“PIPEBWIDEGAMUTCOLORCORRECTIONC01_C00COEFFICIENTS—Offset 610B0h”
610B0h 4 00000000h
on page 524
“PIPEBWIDEGAMUTCOLORCORRECTIONC02COEFFICIENT—Offset 610B4h” on
610B4h 4 00000000h
page 525

“PIPEBWIDEGAMUTCOLORCORRECTIONC11_C10COEFFICIENTS—Offset 610B8h”
610B8h 4 00000000h
on page 525
“PIPEBWIDEGAMUTCOLORCORRECTIONC12COEFFICIENT—Offset 610BCh” on
610BCh 4 00000000h
page 526
“PIPEBWIDEGAMUTCOLORCORRECTIONC21_C20COEFFICIENTS—Offset 610C0h”
610C0h 4 00000000h
on page 527
“PIPEBWIDEGAMUTCOLORCORRECTIONC22COEFFICIENT—Offset 610C4h” on
610C4h 4 00000000h
page 527

61100h 4 “ADPA—Offset 61100h” on page 528 00040000h

61104h 4 “CRTIO_DFX—Offset 61104h” on page 530 00008000h
61110h 4 “PORT_HOTPLUG_EN—Offset 61110h” on page 530 00000020h

61114h 4 “PORT_HOTPLUG_STAT—Offset 61114h” on page 533 00000000h

61140h 4 “SDVOHDMIB—Offset 61140h” on page 536 00000018h
61154h 4 “SDVOHDMIB—Offset 61140h” on page 536 00000000h

61160h 4 “HDMIC—Offset 61160h” on page 540 00000018h

“DISPLAY_DIGITAL_PORT_HOT_PLUG_CONTROL_REGISTER—Offset 61164h” on
61164h 4 00000000h
page 543

61168h 4 “DV_DETERM—Offset 61168h” on page 546 00000000h

61170h 4 “VIDEO_DIP_CTL_B—Offset 61170h” on page 547 20200900h
61174h 4 “VIDEO_DIP_DATA_B—Offset 61174h” on page 548 00000000h

Bay Trail-I SoC

502 Datasheet
Graphics, Video and Display

Table 160. Summary of Display Memory Mapped I/O Registers—GTTMMADR_LSB

Default
Offset Size Register ID—Description
Value

61178h 4 “VIDEO_DIP_GDCP_PAYLOAD_B—Offset 61178h” on page 549 00000000h

61190h 4 “MIPIA_PORT_CTRL—Offset 61190h” on page 550 00000000h
61194h 4 “MIPIA_TEARING_CTR—Offset 61194h” on page 553 00000000h

61198h 4 “DPA_PIX_GEN_CTRL—Offset 61198h” on page 553 00000000h

611A0h 4 “MIPIA_AUTOPWG—Offset 611A0h” on page 554 00000000h
611B0h 4 “DPB_PIX_GEN_CTRL—Offset 611B0h” on page 555 00000000h

61200h 4 “PIPEA_PP_STATUS—Offset 61200h” on page 556 08000000h

61204h 4 “PIPEA_PP_CONTROL—Offset 61204h” on page 558 00000000h
61208h 4 “PIPEA_PP_ON_DELAYS—Offset 61208h” on page 559 00000000h

6120Ch 4 “PIPEA_PP_OFF_DELAYS—Offset 6120Ch” on page 560 00000000h

61210h 4 “PIPEA_PP_DIVISOR—Offset 61210h” on page 561 00270F04h
61230h 4 “PFIT_CONTROL—Offset 61230h” on page 562 20000000h

61234h 4 “PFIT_PGM_RATIOS—Offset 61234h” on page 564 00000000h

“RESERVEDUSEDTOBEAUTOSCALINGRATIOSREADBACK—Offset 61238h” on
61238h 4 00000000h
page 564

6123Ch 4 “RESERVEDUSEDTOBESCALINGINITIALPHASE—Offset 6123Ch” on page 565 00000000h

61250h 4 “PIPEA_BLC_PWM_CLT2—Offset 61250h” on page 565 00000000h
61254h 4 “PIPEA_BLC_PWM_CTL—Offset 61254h” on page 567 00000000h

61260h 4 “PIPEA_BLM_HIST_CTL—Offset 61260h” on page 567 00000000h

“PIPEA_IMAGE_ENHANCEMENT_BIN_DATA_REGISTER—Offset 61264h” on
61264h 4 00000000h
page 569

“PIPEAHISTOGRAMTHRESHOLDGUARDBANDREGISTER—Offset 61268h” on
61268h 4 00000000h
page 570
61300h 4 “PIPEB_PP_STATUS—Offset 61300h” on page 571 08000000h

61304h 4 “PIPEB_PP_CONTROL—Offset 61304h” on page 572 00000000h

61308h 4 “PIPEB_PP_ON_DELAYS—Offset 61308h” on page 573 00000000h

6130Ch 4 “PIPEB_PP_OFF_DELAYS—Offset 6130Ch” on page 574 00000000h

61310h 4 “PIPEB_PP_DIVISOR—Offset 61310h” on page 575 00270F04h
61350h 4 “PIPEB_BLC_PWM_CLT2—Offset 61350h” on page 576 00000000h

61354h 4 “PIPEB_BLC_PWM_CTL—Offset 61354h” on page 577 00000000h

61360h 4 “PIPEB_BLM_HIST_CTL—Offset 61360h” on page 578 00000000h
“PIPEB_IMAGE_ENHANCEMENT_BIN_DATA_REGISTER—Offset 61364h” on
61364h 4 00000000h
page 580
“PIPEBHISTOGRAMTHRESHOLDGUARDBANDREGISTER—Offset 61368h” on
61368h 4 00000000h
page 581

61700h 4 “MIPIC_PORT_CTRL—Offset 61700h” on page 582 00000000h

61704h 4 “MIPIC_TEARING_CTR—Offset 61704h” on page 583 00000000h
62000h 4 “AUD_CONFIG_A—Offset 62000h” on page 583 00000000h

62010h 4 “AUD_MISC_CTRL_A—Offset 62010h” on page 584 00000044h

62020h 4 “AUD_VID_DID—Offset 62020h” on page 585 80862882h
62024h 4 “AUD_RID—Offset 62024h” on page 586 00100000h

Bay Trail-I SoC

Datasheet 503
 Graphics, Video and Display

Table 160. Summary of Display Memory Mapped I/O Registers—GTTMMADR_LSB

Default
Offset Size Register ID—Description
Value

62028h 4 “AUD_CTS_ENABLE_A—Offset 62028h” on page 587 00000000h

6204Ch 4 “AUD_PWRST—Offset 6204Ch” on page 587 00FFFFFFh
62050h 4 “AUD_HDMIW_HDMIEDID_A—Offset 62050h” on page 589 00000000h

62054h 4 “AUD_HDMIW_INFOFR_A—Offset 62054h” on page 589 00000000h

6207Ch 4 “AUD_PORT_EN_HD_CFG—Offset 6207Ch” on page 590 00077003h
62080h 4 “AUD_OUT_DIG_CNVT_A—Offset 62080h” on page 591 00000000h

62084h 4 “AUD_OUT_STR_DESC_A—Offset 62084h” on page 593 00000032h

62088h 4 “AUD_OUT_CH_STR—Offset 62088h” on page 594 00000000h
620A8h 4 “AUD_PINW_CONNLNG_LIST—Offset 620A8h” on page 595 00030202h

620ACh 4 “AUD_PINW_CONNLNG_SEL—Offset 620ACh” on page 596 00000000h

620B4h 4 “AUD_CNTL_ST_A—Offset 620B4h” on page 596 00005400h
620C0h 4 “AUD_CNTL_ST2—Offset 620C0h” on page 598 00000000h

620D4h 4 “AUD_HDMIW_STATUS—Offset 620D4h” on page 599 00000000h

62100h 4 “AUD_CONFIG_B—Offset 62100h” on page 600 00000000h
62110h 4 “AUD_MISC_CTRL_B—Offset 62110h” on page 601 00000044h

62128h 4 “AUD_CTS_ENABLE_B—Offset 62128h” on page 602 00000000h

62150h 4 “AUD_HDMIW_HDMIEDID_B—Offset 62150h” on page 603 00000000h
62154h 4 “AUD_HDMIW_INFOFR_B—Offset 62154h” on page 603 00000000h

62180h 4 “AUD_OUT_DIG_CNVT_B—Offset 62180h” on page 604 00000000h

62184h 4 “AUD_OUT_STR_DESC_B—Offset 62184h” on page 605 00000032h
621B4h 4 “AUD_CNTL_ST_B—Offset 621B4h” on page 607 00005400h

62F00h 4 “AUD_SSID_DBG—Offset 62F00h” on page 608 80860101h

62F04h 4 “AUD_PWST1_DBG—Offset 62F04h” on page 608 00000C0Fh
62F08h 4 “AUD_OUT_STR_DESC_A_DBG—Offset 62F08h” on page 609 00000032h

62F0Ch 4 “AUD_OUT_DIG_CNVT_A_DBG—Offset 62F0Ch” on page 611 00000001h

62F14h 4 “AUD_PWST2_DBG—Offset 62F14h” on page 612 0000000Fh

62F18h 4 “AUD_OUT_STR_DESC_B_DBG—Offset 62F18h” on page 613 00000032h

62F1Ch 4 “AUD_OUT_DIG_CNVT_B_DBG—Offset 62F1Ch” on page 614 00000001h
62F20h 4 “AUD_PORT_EN_B_DBG—Offset 62F20h” on page 615 00000003h

62F24h 4 “AUD_PWST3_DBG—Offset 62F24h” on page 616 00000003h

62F28h 4 “AUD_PORT_EN_C_DBG—Offset 62F28h” on page 617 00000003h
62F2Ch 4 “AUD_PORT_EN_D_DBG—Offset 62F2Ch” on page 618 00000003h

62F38h 4 “AUD_CHICKENBIT_REG—Offset 62F38h” on page 619 00000001h

62F40h 4 “AUD_OUT_DIG_CNVTA_DBG—Offset 62F40h” on page 620 00000000h
62F44h 4 “AUD_OUT_DIG_CNVTB_DBG—Offset 62F44h” on page 621 00000000h

62F60h 4 “AUD_CNTL_ST_B_DBG—Offset 62F60h” on page 622 00000000h

62F64h 4 “AUD_HDMIW_INFOFR_B_DBG—Offset 62F64h” on page 623 00000000h
62F70h 4 “AUD_CNTL_ST_C_DBG—Offset 62F70h” on page 624 00000000h

62F74h 4 “AUD_HDMIW_INFOFR_C_DBG—Offset 62F74h” on page 625 00000000h

Bay Trail-I SoC

504 Datasheet
Graphics, Video and Display

Table 160. Summary of Display Memory Mapped I/O Registers—GTTMMADR_LSB

Default
Offset Size Register ID—Description
Value

62F80h 4 “AUD_CNTL_ST_D_DBG—Offset 62F80h” on page 626 00000000h

62F84h 4 “AUD_HDMIW_INFOFR_D_DBG—Offset 62F84h” on page 627 00000000h
62F88h 4 “AUD_CONFIG_DEFAULT2_REG_PORTB—Offset 62F88h” on page 628 00000000h

62F8Ch 4 “AUD_CONFIG_DEFAULT2_REG_PORTC—Offset 62F8Ch” on page 628 00000000h

62F90h 4 “AUD_CONFIG_DEFAULT2_REG_PORTD—Offset 62F90h” on page 629 00000000h
62F94h 4 “AUD_MCTSA—Offset 62F94h” on page 629 00000000h

62F98h 4 “AUD_MCTSB—Offset 62F98h” on page 630 00000000h

64100h 4 “DP_B—Offset 64100h” on page 631 00000018h
64110h 4 “DPB_AUX_CH_CTL—Offset 64110h” on page 633 00050000h

64114h 4 “DPB_AUX_CH_DATA1—Offset 64114h” on page 635 00000000h

64118h 4 “DPB_AUX_CH_DATA2—Offset 64118h” on page 635 00000000h
6411Ch 4 “DPB_AUX_CH_DATA3—Offset 6411Ch” on page 636 00000000h

64120h 4 “DPB_AUX_CH_DATA4—Offset 64120h” on page 637 00000000h

64124h 4 “DPB_AUX_CH_DATA5—Offset 64124h” on page 637 00000000h
64130h 4 “DP_AUX_CH_AKSV_HI—Offset 64130h” on page 638 00000000h

64134h 4 “DP_AUX_CH_AKSV_LO—Offset 64134h” on page 638 00000000h

64150h 4 “DPB_AUX_TST—Offset 64150h” on page 639 00000000h
64200h 4 “DP_C—Offset 64200h” on page 641 00000018h

64210h 4 “DPC_AUX_CH_CTL—Offset 64210h” on page 643 00050000h

64214h 4 “DPC_AUX_CH_DATA1—Offset 64214h” on page 644 00000000h
64218h 4 “DPC_AUX_CH_DATA2—Offset 64218h” on page 645 00000000h

6421Ch 4 “DPC_AUX_CH_DATA3—Offset 6421Ch” on page 645 00000000h

64220h 4 “DPC_AUX_CH_DATA4—Offset 64220h” on page 646 00000000h
64224h 4 “DPC_AUX_CH_DATA5—Offset 64224h” on page 646 00000000h

64228h 4 “DPC_AUX_TST—Offset 64228h” on page 647 00000000h

65000h 4 “STREAM_A_LPE_AUD_CONFIG—Offset 65000h” on page 649 00000280h

65008h 4 “STREAM_A_LPE_AUD_CH_STATUS_0—Offset 65008h” on page 651 00000000h

6500Ch 4 “STREAM_A_LPE_AUD_CH_STATUS_1—Offset 6500Ch” on page 651 00000000h
65010h 4 “STREAM_A_LPE_AUD_HDMI_CTS_DP_MAUD—Offset 65010h” on page 652 00000000h

65014h 4 “STREAM_A_LPE_AUD_HDMI_N_DP_NAUD—Offset 65014h” on page 653 00000000h

65020h 4 “STREAM_A_LPE_AUD_BUFFER_CONFIG—Offset 65020h” on page 653 00000100h
65024h 4 “STREAM_A_LPE_AUD_BUF_CH_SWP—Offset 65024h” on page 654 00FAC688h

65040h 4 “STREAM_A_LPE_AUD_BUF_A_ADDR—Offset 65040h” on page 656 00000000h

65044h 4 “STREAM_A_LPE_AUD_BUF_A_LENGTH—Offset 65044h” on page 656 00000000h
65048h 4 “STREAM_A_LPE_AUD_BUF_B_ADDR—Offset 65048h” on page 657 00000000h

6504Ch 4 “STREAM_A_LPE_AUD_BUF_B_LENGTH—Offset 6504Ch” on page 658 00000000h

65050h 4 “STREAM_A_LPE_AUD_BUF_C_ADDR—Offset 65050h” on page 658 00000000h
65054h 4 “STREAM_A_LPE_AUD_BUF_C_LENGTH—Offset 65054h” on page 659 00000000h

65058h 4 “STREAM_A_LPE_AUD_BUF_D_ADDR—Offset 65058h” on page 659 00000000h

Bay Trail-I SoC

Datasheet 505
 Graphics, Video and Display

Table 160. Summary of Display Memory Mapped I/O Registers—GTTMMADR_LSB

Default
Offset Size Register ID—Description
Value

6505Ch 4 “STREAM_A_LPE_AUD_BUF_D_LENGTH—Offset 6505Ch” on page 660 00000000h

65060h 4 “STREAM_A_LPE_AUD_CNTL_ST—Offset 65060h” on page 661 00000000h
65064h 4 “STREAM_A_LPE_AUD_HDMI_STATUS—Offset 65064h” on page 662 00000000h

65068h 4 “STREAM_A_LPE_AUD_HDMIW_INFOFR—Offset 65068h” on page 664 00000000h

65800h 4 “STREAM_B_LPE_AUD_CONFIG—Offset 65800h” on page 664 00000280h
65808h 4 “STREAM_B_LPE_AUD_CH_STATUS_0—Offset 65808h” on page 666 00000000h

6580Ch 4 “STREAM_B_LPE_AUD_CH_STATUS_1—Offset 6580Ch” on page 667 00000000h

65810h 4 “STREAM_B_LPE_AUD_HDMI_CTS_DP_MAUD—Offset 65810h” on page 668 00000000h
65814h 4 “STREAM_B_LPE_AUD_HDMI_N_DP_NAUD—Offset 65814h” on page 668 00000000h

65820h 4 “STREAM_B_LPE_AUD_BUFFER_CONFIG—Offset 65820h” on page 669 00000100h

65824h 4 “STREAM_B_LPE_AUD_BUF_CH_SWP—Offset 65824h” on page 670 00FAC688h
65840h 4 “STREAM_B_LPE_AUD_BUF_A_ADDR—Offset 65840h” on page 671 00000000h

65844h 4 “STREAM_B_LPE_AUD_BUF_A_LENGTH—Offset 65844h” on page 672 00000000h

65848h 4 “STREAM_B_LPE_AUD_BUF_B_ADDR—Offset 65848h” on page 672 00000000h
6584Ch 4 “STREAM_B_LPE_AUD_BUF_B_LENGTH—Offset 6584Ch” on page 673 00000000h

65850h 4 “STREAM_B_LPE_AUD_BUF_C_ADDR—Offset 65850h” on page 674 00000000h

65854h 4 “STREAM_B_LPE_AUD_BUF_C_LENGTH—Offset 65854h” on page 674 00000000h
65858h 4 “STREAM_B_LPE_AUD_BUF_D_ADDR—Offset 65858h” on page 675 00000000h

6585Ch 4 “STREAM_B_LPE_AUD_BUF_D_LENGTH—Offset 6585Ch” on page 676 00000000h

65860h 4 “STREAM_B_LPE_AUD_CNTL_ST—Offset 65860h” on page 676 00000000h
65864h 4 “STREAM_B_LPE_AUD_HDMI_STATUS—Offset 65864h” on page 678 00000000h

65868h 4 “STREAM_B_LPE_AUD_HDMIW_INFOFR—Offset 65868h” on page 680 00000000h

70000h 4 “PIPEA_DSL—Offset 70000h” on page 680 00000000h
70004h 4 “PIPEA_SLC—Offset 70004h” on page 681 00000000h

70008h 4 “PIPEACONF—Offset 70008h” on page 682 00000000h

70010h 4 “PIPEAGCMAXRED—Offset 70010h” on page 688 00010000h

70014h 4 “PIPEAGCMAXGREEN—Offset 70014h” on page 688 00010000h

70018h 4 “PIPEAGCMAXBLUE—Offset 70018h” on page 689 00010000h
70024h 4 “PIPEASTAT—Offset 70024h” on page 690 00000000h

70028h 4 “DPFLIPSTAT—Offset 70028h” on page 693 00000000h

7002Ch 4 “DPINVGTT—Offset 7002Ch” on page 695 00000000h
70030h 4 “DSPARB—Offset 70030h” on page 697 80008000h

70034h 4 “FW1—Offset 70034h” on page 698 3F8F0F0Fh

70038h 4 “FW2—Offset 70038h” on page 699 0B0F0F0Fh
7003Ch 4 “FW3—Offset 7003Ch” on page 700 00000000h

70040h 4 “PIPEAFRAMECOUNT—Offset 70040h” on page 702 00000000h

70044h 4 “PIPEAFLIPCOUNT—Offset 70044h” on page 702 00000000h
70048h 4 “PIPEAMSAMISC—Offset 70048h” on page 703 00000000h

70050h 4 “DDL1—Offset 70050h” on page 704 00000000h

Bay Trail-I SoC

506 Datasheet
Graphics, Video and Display

Table 160. Summary of Display Memory Mapped I/O Registers—GTTMMADR_LSB

Default
Offset Size Register ID—Description
Value

70054h 4 “DDL2—Offset 70054h” on page 705 00000000h

70060h 4 “DSPARB2—Offset 70060h” on page 706 00001111h
70064h 4 “DSPHOWM—Offset 70064h” on page 707 00000000h

70068h 4 “DSPHOWM1—Offset 70068h” on page 709 00000000h

70070h 4 “FW4—Offset 70070h” on page 711 00040404h
70074h 4 “FW5—Offset 70074h” on page 712 04040404h

70078h 4 “FW6—Offset 70078h” on page 713 00000078h

7007Ch 4 “FW7—Offset 7007Ch” on page 714 040F040Fh
70080h 4 “CURACNTR—Offset 70080h” on page 715 00000000h

70084h 4 “CURABASE—Offset 70084h” on page 716 00000000h

70088h 4 “CURAPOS—Offset 70088h” on page 717 00000000h
70090h 4 “CURAPALET_0—Offset 70090h” on page 719 00000000h

70094h 4 “CURAPALET_1—Offset 70094h” on page 719 00000000h

70098h 4 “CURAPALET_2—Offset 70098h” on page 720 00000000h
7009Ch 4 “CURAPALET_3—Offset 7009Ch” on page 721 00000000h

700ACh 4 “CURALIVEBASE—Offset 700ACh” on page 722 00000000h

700C0h 4 “CURBCNTR—Offset 700C0h” on page 722 00000000h
700C4h 4 “CURBBASE—Offset 700C4h” on page 723 00000000h

700C8h 4 “CURBPOS—Offset 700C8h” on page 725 00000000h

700D0h 4 “CURBPALET_0—Offset 700D0h” on page 726 00000000h
700D4h 4 “CURBPALET_1—Offset 700D4h” on page 727 00000000h

700D8h 4 “CURBPALET_2—Offset 700D8h” on page 728 00000000h

700DCh 4 “CURBPALET_3—Offset 700DCh” on page 728 00000000h
700ECh 4 “CURBLIVEBASE—Offset 700ECh” on page 729 00000000h

7017Ch 4 “DSPAADDR—Offset 7017Ch” on page 731 00000000h

70180h 4 “DSPACNTR—Offset 70180h” on page 732 00000000h

70184h 4 “DSPALINOFF—Offset 70184h” on page 734 00000000h

70188h 4 “DSPASTRIDE—Offset 70188h” on page 734 00000000h
70194h 4 “DSPAKEYVAL—Offset 70194h” on page 735 00000000h

70198h 4 “DSPAKEYMSK—Offset 70198h” on page 736 00000000h

7019Ch 4 “DSPASURF—Offset 7019Ch” on page 736 00000000h
701A4h 4 “DSPATILEOFF—Offset 701A4h” on page 737 00000000h

701ACh 4 “DSPASURFLIVE—Offset 701ACh” on page 738 00000000h

70400h 4 “CBR1—Offset 70400h” on page 739 00000000h
70404h 4 “CBR2—Offset 70404h” on page 741 00000000h

70408h 4 “CCBR—Offset 70408h” on page 743 00000000h

7040Ch 4 “CBR3—Offset 7040Ch” on page 744 00000000h
70410h 4 “SWF00—Offset 70410h” on page 745 00000000h

70414h 4 “SWF01—Offset 70414h” on page 746 00000000h

Bay Trail-I SoC

Datasheet 507
 Graphics, Video and Display

Table 160. Summary of Display Memory Mapped I/O Registers—GTTMMADR_LSB

Default
Offset Size Register ID—Description
Value

70418h 4 “SWF02—Offset 70418h” on page 746 00000000h

7041Ch 4 “SWF03—Offset 7041Ch” on page 747 00000000h
70420h 4 “SWF04—Offset 70420h” on page 747 00000000h

70424h 4 “SWF05—Offset 70424h” on page 748 00000000h

70428h 4 “SWF06—Offset 70428h” on page 748 00000000h
7042Ch 4 “SWF07—Offset 7042Ch” on page 749 00000000h

70430h 4 “SWF08—Offset 70430h” on page 749 00000000h

70434h 4 “SWF09—Offset 70434h” on page 750 00000000h
70438h 4 “SWF0A—Offset 70438h” on page 750 00000000h

7043Ch 4 “SWF0B—Offset 7043Ch” on page 751 00000000h

70440h 4 “SWF0C—Offset 70440h” on page 751 00000000h
70444h 4 “SWF0D—Offset 70444h” on page 752 00000000h

70448h 4 “SWF0E—Offset 70448h” on page 752 00000000h

7044Ch 4 “SWF0F—Offset 7044Ch” on page 753 00000000h
70450h 4 “CBR4—Offset 70450h” on page 753 00000000h

71000h 4 “PIPEB_DSL—Offset 71000h” on page 755 00000000h

71004h 4 “PIPEB_SLC—Offset 71004h” on page 756 00000000h
71008h 4 “PIPEBCONF—Offset 71008h” on page 757 00000000h

71010h 4 “PIPEBGCMAXRED—Offset 71010h” on page 759 00010000h

71014h 4 “PIPEBGCMAXGREEN—Offset 71014h” on page 760 00010000h
71018h 4 “PIPEBGCMAXBLUE—Offset 71018h” on page 761 00010000h

71024h 4 “PIPEBSTAT—Offset 71024h” on page 762 00000000h

71040h 4 “PIPEBFRAMECOUNT—Offset 71040h” on page 765 00000000h
71044h 4 “PIPEBFLIPCOUNT—Offset 71044h” on page 766 00000000h

71048h 4 “PIPEBMSAMISC—Offset 71048h” on page 766 00000000h

7117Ch 4 “DSPBADDR—Offset 7117Ch” on page 767 00000000h

71180h 4 “DSPBCNTR—Offset 71180h” on page 768 01000000h

71184h 4 “DSPBLINOFFSET—Offset 71184h” on page 770 00000000h
71188h 4 “DSPBSTRIDE—Offset 71188h” on page 771 00000000h

71194h 4 “DSPBKEYVAL—Offset 71194h” on page 772 00000000h

71198h 4 “DSPBKEYMSK—Offset 71198h” on page 772 00000000h
7119Ch 4 “DSPBSURF—Offset 7119Ch” on page 773 00000000h

711A4h 4 “DSPBTILEOFF—Offset 711A4h” on page 774 00000000h

711ACh 4 “DSPBSURFLIVE—Offset 711ACh” on page 775 00000000h
71200h 4 “DSPBFLPQSTAT—Offset 71200h” on page 776 00000000h

71400h 4 “VGACNTRL—Offset 71400h” on page 777 00000000h

71410h 4 “SWF10—Offset 71410h” on page 779 00000000h
71414h 4 “SWF11—Offset 71414h” on page 780 00000000h

71418h 4 “SWF12—Offset 71418h” on page 780 00000000h

Bay Trail-I SoC

508 Datasheet
Graphics, Video and Display

Table 160. Summary of Display Memory Mapped I/O Registers—GTTMMADR_LSB

Default
Offset Size Register ID—Description
Value

7141Ch 4 “SWF13—Offset 7141Ch” on page 780 00000000h

71420h 4 “SWF14—Offset 71420h” on page 781 00000000h
71424h 4 “SWF15—Offset 71424h” on page 781 00000000h

71428h 4 “SWF16—Offset 71428h” on page 782 00000000h

7142Ch 4 “SWF17—Offset 7142Ch” on page 782 00000000h
71430h 4 “SWF18—Offset 71430h” on page 783 00000000h

71434h 4 “SWF19—Offset 71434h” on page 783 00000000h

71438h 4 “SWF1A—Offset 71438h” on page 784 00000000h
7143Ch 4 “SWF1B—Offset 7143Ch” on page 784 00000000h

71440h 4 “SWF1C—Offset 71440h” on page 785 00000000h

71444h 4 “SWF1D—Offset 71444h” on page 785 00000000h
71448h 4 “SWF1E—Offset 71448h” on page 786 00000000h

7144Ch 4 “SWF1F—Offset 7144Ch” on page 786 00000000h

72180h 4 “SPACNTR—Offset 72180h” on page 787 00000000h
72184h 4 “SPALINOFF—Offset 72184h” on page 789 00000000h

72188h 4 “SPASTRIDE—Offset 72188h” on page 790 00000000h

7218Ch 4 “SPAPOS—Offset 7218Ch” on page 791 00000000h
72190h 4 “SPASIZE—Offset 72190h” on page 791 00000000h

72194h 4 “SPAKEYMINVAL—Offset 72194h” on page 792 00000000h

72198h 4 “SPAKEYMSK—Offset 72198h” on page 793 00000000h
7219Ch 4 “SPASURF—Offset 7219Ch” on page 793 00000000h

721A0h 4 “SPAKEYMAXVAL—Offset 721A0h” on page 794 00000000h

721A4h 4 “SPATILEOFF—Offset 721A4h” on page 795 00000000h
721A8h 4 “SPACONTALPHA—Offset 721A8h” on page 796 00000000h

721ACh 4 “SPALIVESURF—Offset 721ACh” on page 797 00000000h

721D0h 4 “SPACLRC0—Offset 721D0h” on page 798 01000000h

721D4h 4 “SPACLRC1—Offset 721D4h” on page 799 00000080h

721E0h 4 “SPAGAMC5—Offset 721E0h” on page 800 00C0C0C0h
721E4h 4 “SPAGAMC4—Offset 721E4h” on page 801 00808080h

721E8h 4 “SPAGAMC3—Offset 721E8h” on page 801 00404040h

721ECh 4 “SPAGAMC2—Offset 721ECh” on page 802 00202020h
721F0h 4 “SPAGAMC1—Offset 721F0h” on page 803 00101010h

721F4h 4 “SPAGAMC0—Offset 721F4h” on page 803 00080808h

72280h 4 “SPBCNTR—Offset 72280h” on page 804 00000000h
72284h 4 “SPBLINOFF—Offset 72284h” on page 806 00000000h

72288h 4 “SPBSTRIDE—Offset 72288h” on page 807 00000000h

7228Ch 4 “SPBPOS—Offset 7228Ch” on page 807 00000000h
72290h 4 “SPBSIZE—Offset 72290h” on page 808 00000000h

72294h 4 “SPBKEYMINVAL—Offset 72294h” on page 809 00000000h

Bay Trail-I SoC

Datasheet 509
 Graphics, Video and Display

Table 160. Summary of Display Memory Mapped I/O Registers—GTTMMADR_LSB

Default
Offset Size Register ID—Description
Value

72298h 4 “SPBKEYMSK—Offset 72298h” on page 809 00000000h

7229Ch 4 “SPBSURF—Offset 7229Ch” on page 810 00000000h
722A0h 4 “SPBKEYMAXVAL—Offset 722A0h” on page 811 00000000h

722A4h 4 “SPBTILEOFF—Offset 722A4h” on page 812 00000000h

722A8h 4 “SPBCONTALPHA—Offset 722A8h” on page 813 00000000h
722ACh 4 “SPBLIVESURF—Offset 722ACh” on page 814 00000000h

722D0h 4 “SPBCLRC0—Offset 722D0h” on page 814 01000000h

722D4h 4 “SPBCLRC1—Offset 722D4h” on page 815 00000080h
722E0h 4 “SPBGAMC5—Offset 722E0h” on page 816 00C0C0C0h

722E4h 4 “SPBGAMC4—Offset 722E4h” on page 817 00808080h

722E8h 4 “SPBGAMC3—Offset 722E8h” on page 817 00404040h
722ECh 4 “SPBGAMC2—Offset 722ECh” on page 818 00202020h

722F0h 4 “SPBGAMC1—Offset 722F0h” on page 819 00101010h

722F4h 4 “SPBGAMC0—Offset 722F4h” on page 819 00080808h
72380h 4 “SPCCNTR—Offset 72380h” on page 820 00000000h

72384h 4 “SPCLINOFF—Offset 72384h” on page 822 00000000h

72388h 4 “SPCSTRIDE—Offset 72388h” on page 823 00000000h
7238Ch 4 “SPCPOS—Offset 7238Ch” on page 823 00000000h

72390h 4 “SPCSIZE—Offset 72390h” on page 824 00000000h

72394h 4 “SPCKEYMINVAL—Offset 72394h” on page 825 00000000h
72398h 4 “SPCKEYMSK—Offset 72398h” on page 825 00000000h

7239Ch 4 “SPCSURF—Offset 7239Ch” on page 826 00000000h

723A0h 4 “SPCKEYMAXVAL—Offset 723A0h” on page 827 00000000h
723A4h 4 “SPCTILEOFF—Offset 723A4h” on page 828 00000000h

723A8h 4 “SPCCONTALPHA—Offset 723A8h” on page 829 00000000h

723ACh 4 “SPCLIVESURF—Offset 723ACh” on page 830 00000000h

723D0h 4 “SPCCLRC0—Offset 723D0h” on page 830 01000000h

723D4h 4 “SPCCLRC1—Offset 723D4h” on page 831 00000080h
723E0h 4 “SPCGAMC5—Offset 723E0h” on page 832 00C0C0C0h

723E4h 4 “SPCGAMC4—Offset 723E4h” on page 833 00808080h

723E8h 4 “SPCGAMC3—Offset 723E8h” on page 833 00404040h
723ECh 4 “SPCGAMC2—Offset 723ECh” on page 834 00202020h

723F0h 4 “SPCGAMC1—Offset 723F0h” on page 835 00101010h

723F4h 4 “SPCGAMC0—Offset 723F4h” on page 835 00080808h
72414h 4 “SWF30—Offset 72414h” on page 836 00000000h

72418h 4 “SWF31—Offset 72418h” on page 836 00000000h

7241Ch 4 “SWF32—Offset 7241Ch” on page 837 00000000h
72480h 4 “SPDCNTR—Offset 72480h” on page 837 00000000h

72484h 4 “SPDLINOFF—Offset 72484h” on page 839 00000000h

Bay Trail-I SoC

510 Datasheet
Graphics, Video and Display

Table 160. Summary of Display Memory Mapped I/O Registers—GTTMMADR_LSB

Default
Offset Size Register ID—Description
Value

72488h 4 “SPDSTRIDE—Offset 72488h” on page 840 00000000h

7248Ch 4 “SPDPOS—Offset 7248Ch” on page 841 00000000h
72490h 4 “SPDSIZE—Offset 72490h” on page 842 00000000h

72494h 4 “SPDKEYMINVAL—Offset 72494h” on page 842 00000000h

72498h 4 “SPDKEYMSK—Offset 72498h” on page 843 00000000h
7249Ch 4 “SPDSURF—Offset 7249Ch” on page 844 00000000h

724A0h 4 “SPDKEYMAXVAL—Offset 724A0h” on page 845 00000000h

724A4h 4 “SPDTILEOFF—Offset 724A4h” on page 845 00000000h
724A8h 4 “SPDCONTALPHA—Offset 724A8h” on page 846 00000000h

724ACh 4 “SPDLIVESURF—Offset 724ACh” on page 847 00000000h

724D0h 4 “SPDCLRC0—Offset 724D0h” on page 848 01000000h
724D4h 4 “SPDCLRC1—Offset 724D4h” on page 849 00000080h

724E0h 4 “SPDGAMC5—Offset 724E0h” on page 850 00C0C0C0h

724E4h 4 “SPDGAMC4—Offset 724E4h” on page 851 00808080h
724E8h 4 “SPDGAMC3—Offset 724E8h” on page 851 00404040h

724ECh 4 “SPDGAMC2—Offset 724ECh” on page 852 00202020h

724F0h 4 “SPDGAMC1—Offset 724F0h” on page 853 00101010h
724F4h 4 “SPDGAMC0—Offset 724F4h” on page 853 00080808h

73000h 4 “PCSRC—Offset 73000h” on page 854 00000000h

73004h 4 “PCSTAT—Offset 73004h” on page 855 00000000h
73008h 4 “PCSRC2—Offset 73008h” on page 857 00000000h

7300Ch 4 “PCSTAT2—Offset 7300Ch” on page 858 00000000h

14.11.1 CRCCTRLREDB—Offset 61050h

Pipe B CRC Color Control Register (Red)

Access Method
Type: Memory Mapped I/O Register CRCCTRLREDB: [GTTMMADR_LSB + 2BF20h] + 61050h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

Datasheet 511
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESERVED
CRC_SOURCE_SELECT

EXPECTED_CRC_VALUE
ENABLE_COLOR_CHANNEL_CRC

Bit Default &

Description
Range Access

0b ENABLE_COLOR_CHANNEL_CRC: After being enabled for the first time, you need to
31 wait for two VBLANK events for a valid CRC result. After that, a CRC will be generated
RW each frame. 0 = CRC Calculations are disabled 1 = CRC Calculations are enabled
CRC_SOURCE_SELECT: These bits select the source of the data to put into the CRC
logic. 0000: Pipe B (Not available when DisplayPort or TV is enabled on this pipe)
[DevVLVP] 0001: sDVOB/HDMIB (30 bit format. Only select when HDMIB is set to pipe
B) [DevVLVP] 0010: sDVOC/HDMIC (30 bit format. Only select when HDMIC is set to
0b pipe B) [DevVLVP] 0011: DisplayPort D (40 bit format) [DevCTG] 0100: TV Encoder
30:27
RW outputs (30 bit format) 0101: TV filter outputs (30 bit format) 0110: DisplayPort B (40
bit format) [DevCTG, DevCDV, DevVLVP] 0111: DisplayPort C (40 bit format) [DevCTG,
DevCDV, DevVLVP] 1000: Audio DP (Audio for DisplayPort (pcdclk). Only select when
Audio is on DisplayPort on Pipe B) [DevVLVP] 1001: Audio HDMI (Audio for HDMI
(dotclock) Only select when Audio is on HDMI on Pipe B) Others: Reserved
0b
26:23 RESERVED: Write as zero
RW
EXPECTED_CRC_VALUE: Expected CRC Value for the Color Channel. This is the value
0b used to generate the CRC error status and interrupt. Resultant CRC values are
22:0
RW compared to this register after the completion of a CRC calculation. The status bit is in
the PIPEBSTAT register.

14.11.2 CRCCTRLGREENB—Offset 61054h

Pipe B CRC Color Control Register

Access Method
Type: Memory Mapped I/O Register
CRCCTRLGREENB: [GTTMMADR_LSB + 2BF20h] + 61054h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

512 Datasheet
Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESERVED

EXPECTED_CRC_VALUE
Bit Default &
Description
Range Access

0b
31:23 RESERVED: Write as zero
RW
EXPECTED_CRC_VALUE: Expected CRC Value for the Color Channel. This is the value
0b used to generate the CRC error status and interrupt. Resultant CRC values are
22:0
RW compared to this register after the completion of a CRC calculation. The status bit is in
the PIPEBSTAT register.

14.11.3 CRCCTRLBLUEB—Offset 61058h

Pipe B CRC Color Control Register

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) CRCCTRLBLUEB: [GTTMMADR_LSB + 2BF20h] + 61058h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED

EXPECTED_CRC_VALUE

Bit Default &

Description
Range Access

0b
31:23 RESERVED: Write as zero
RW

EXPECTED_CRC_VALUE: Expected CRC Value for the Color Channel. This is the value
0b used to generate the CRC error status and interrupt. Resultant CRC values are
22:0
RW compared to this register after the completion of a CRC calculation. The status bit is in
the PIPEBSTAT register.

Bay Trail-I SoC

Datasheet 513
 Graphics, Video and Display

14.11.4 CRCCTRLALPHAB—Offset 6105Ch

Pipe B CRC Color Control Register

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) CRCCTRLALPHAB: [GTTMMADR_LSB + 2BF20h] + 6105Ch

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED

EXPECTED_CRC_VALUE
Bit Default &
Description
Range Access

0b
31:23 RESERVED: Write as zero
RW
EXPECTED_CRC_VALUE: Expected CRC Value for the Color Channel. This is the value
0b used to generate the CRC error status and interrupt. Resultant CRC values are
22:0
RW compared to this register after the completion of a CRC calculation. The status bit is in
the PIPEBSTAT register.

14.11.5 CRCRESREDB—Offset 61060h

Pipe B CRC Result Register

Access Method
Type: Memory Mapped I/O Register CRCRESREDB: [GTTMMADR_LSB + 2BF20h] + 61060h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

514 Datasheet
Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESERVED

COLOR_CHANNEL_CRC_RESULT_VALUE
Bit Default &
Description
Range Access

0b
31:23 RESERVED: Read only
RO
COLOR_CHANNEL_CRC_RESULT_VALUE: This field contains the resultant CRC value
0b for the Color Channel at the end of a frame. A status bit can be used as an indication
22:0
RO that the data is the valid result of a CRC calculation. The result of a CRC on an empty
frame will be 7FFFFFh.

14.11.6 CRCRESGREENB—Offset 61064h

Pipe B CRC Result Register

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) CRCRESGREENB: [GTTMMADR_LSB + 2BF20h] + 61064h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED

COLOR_CHANNEL_CRC_RESULT_VALUE

Bay Trail-I SoC

Datasheet 515
 Graphics, Video and Display

Bit Default &

Description
Range Access

0b
31:23 RESERVED: Read only
RO
COLOR_CHANNEL_CRC_RESULT_VALUE: This field contains the resultant CRC value
0b for the Color Channel at the end of a frame. A status bit can be used as an indication
22:0
RO that the data is the valid result of a CRC calculation. The result of a CRC on an empty
frame will be 7FFFFFh.

14.11.7 CRCRESBLUEB—Offset 61068h

Pipe B CRC Result Register

Access Method
Type: Memory Mapped I/O Register CRCRESBLUEB: [GTTMMADR_LSB + 2BF20h] + 61068h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

COLOR_CHANNEL_CRC_RESULT_VALUE
RESERVED

Bit Default &

Description
Range Access

0b
31:23 RESERVED: Read only
RO
COLOR_CHANNEL_CRC_RESULT_VALUE: This field contains the resultant CRC value
0b for the Color Channel at the end of a frame. A status bit can be used as an indication
22:0
RO that the data is the valid result of a CRC calculation. The result of a CRC on an empty
frame will be 7FFFFFh.

14.11.8 CRCRESALPHAB—Offset 6106Ch

Pipe B CRC Result Register

Access Method

Bay Trail-I SoC

516 Datasheet
Graphics, Video and Display

Type: Memory Mapped I/O Register

CRCRESALPHAB: [GTTMMADR_LSB + 2BF20h] + 6106Ch
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED

COLOR_CHANNEL_CRC_RESULT_VALUE
Bit Default &
Description
Range Access

0b
31:23 RESERVED: Read only
RO
COLOR_CHANNEL_CRC_RESULT_VALUE: This field contains the resultant CRC value
0b for the Color Channel at the end of a frame. A status bit can be used as an indication
22:0
RO that the data is the valid result of a CRC calculation. The result of a CRC on an empty
frame will be 7FFFFFh.

14.11.9 CRCCTRLRESIDUE2B—Offset 61070h

Pipe B CRC Color Control Register

Access Method
Type: Memory Mapped I/O Register CRCCTRLRESIDUE2B: [GTTMMADR_LSB + 2BF20h] + 61070h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

Datasheet 517
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESERVED

EXPECTED_CRC_VALUE
Bit Default &
Description
Range Access

0b
31:23 RESERVED: Write as zero
RW
EXPECTED_CRC_VALUE: Expected CRC Value for the Color Channel. This is the value
0b used to generate the CRC error status and interrupt. Resultant CRC values are
22:0
RW compared to this register after the completion of a CRC calculation. The status bit is in
the PIPEBSTAT register.

14.11.10 CRCRESRESIDUAL2B—Offset 61080h

Pipe B CRC Result Register

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) CRCRESRESIDUAL2B: [GTTMMADR_LSB + 2BF20h] + 61080h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED

COLOR_CHANNEL_CRC_RESULT_VALUE

Bit Default &

Description
Range Access

0b
31:23 RESERVED: Read only
RO

Bay Trail-I SoC

518 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

COLOR_CHANNEL_CRC_RESULT_VALUE: This field contains the resultant CRC value

0b for the Color Channel at the end of a frame. A status bit can be used as an indication
22:0
RO that the data is the valid result of a CRC calculation. The result of a CRC on an empty
frame will be 7FFFFFh.

14.11.11 PSRCTLB—Offset 61090h

Pipe B Panel Self Refresh Control

Access Method
Type: Memory Mapped I/O Register
PSRCTLB: [GTTMMADR_LSB + 2BF20h] + 61090h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DPLLB_POWER_DOWN_DELAY

DOUBLE_FRAMES_IN_PSR_ACTIVE_ENTRY
SOURCE_TRANSMITTER_STATE_IN_PSR_ACTIVE

PSR_SINGLE_FRAME_UPDATE

RESERVED_1

PSR_MODE

PSR_RESET
PSR_ENABLE
RESERVED

IDENTICAL_FRAME_THRESHOLD

PSR_ACTIVE_ENTRY

Bit Default &

Description
Range Access

0b
31:24 RESERVED: Reserved.
RW
0b IDENTICAL_FRAME_THRESHOLD: : Number of identical frames that display
23:16
RW controller needs to exceed in order to transition to PSR active state in HW timer mode

0b DPLLB_POWER_DOWN_DELAY: programmable delay from main link powerdown to

15:11
RW DPLLB powerdown. The delay is in number of cdclk clocks.

0b DOUBLE_FRAMES_IN_PSR_ACTIVE_ENTRY: . If asserted, HW will send two frames

10 with same SDP active setting when entry PSR active state. This bit is set if the vertical
RW blanking time is less than 330us.
SOURCE_TRANSMITTER_STATE_IN_PSR_ACTIVE: . If asserted, HW will keep
0b transmitter active during PSR active state and sends only idle symbols. If deasserted,
9
RW HW will turn off transmitter during PSR active state. Display driver will keep this bit
consistent with Source transmitter state in PSR active bit in DPCD register of the sink.

Bay Trail-I SoC

Datasheet 519
 Graphics, Video and Display

Bit Default &

Description
Range Access

PSR_ACTIVE_ENTRY: This bit is only valid in PSR_mode is SW timer mode. If it is

0b asserted, HW will transition into PSR_active state. If it is deasserted, HW will transition
8
RW to PSR_inactive state. SW should not set or clear this bit more than once within one
vblank period.
PSR_SINGLE_FRAME_UPDATE: In PSR SW or HW mode, SW set this bit before
writing registers for a flip. After HW finishes signle frame update, it goes back to PSR
0b active ? no RFB state. SW driver may send new single frame update request.
7 Programming note: Reading this bit is updated at the next vblank. Writing this bit to 1
RW will cause PSR FSM to perform single frame update automatically, no vblank is required.
When single frame update is done, it will automatically go back to PSR active ? no RFB
update. 61094[2:0] = 3b011.

0b
6:5 RESERVED_1: Reserved.
RW

PSR_MODE: b011-111: reserved. b010: PSR with HW timer. HW timer decides PSR
active entry point. PSR active state exits upon MMIO write registers that may change
0b the frame buffer. b001: PSR with SW timer. In this mode, SW will keep track of idle
4:2 frames and buffer modification in the driver and explicitly specify the entry and exit PSR
RW active state point. b000: PSR manual (debug) mode. All of PSR state transitions and
SDP content is managed by SW driver. SW is responsible to change SDP content for
every frame with appropriate values to keep PSR panel in synchronized states.

0b PSR_RESET: If assert all PSR functions are reset back to PSR inactive state. When it
1 needs to resynchronize source and sync, SW writes 0x2 to DPCD register 600h and to
RW this bit to get system back to PSR active states. This bit is self clear.
0b PSR_ENABLE: Panel Self-refresh is enabled. When it is asserted PSR is enabled and
0
RW operate in one of the mode that specified by PSR mode.

14.11.12 PSRSTATB—Offset 61094h

Pipe B PSR status register

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) PSRSTATB: [GTTMMADR_LSB + 2BF20h] + 61094h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DISPLAY_LOCAL_STANDBY_STATE

PSR_IN_TRANSITION
REPEAT_FRAME_COUNTER
RESERVED

RESERVED_1

SDP_SENT

PSR_LAST_STATE
RESERVED_2

PSR_CURRENT_STATE

Bay Trail-I SoC

520 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

0b DISPLAY_LOCAL_STANDBY_STATE: :00: D0 idle state, fetch frame buffer from

31:30 system memory 01: D0i1 not defined in VLVP 02: D0i2 PSR is active, display controller
RO is trunk gated 03: D0i3 PSR is active, display controller is power gated
0b
29:24 RESERVED: Reserved.
RO
0b REPEAT_FRAME_COUNTER: : Number of identical frames has been sent by display
23:16
RO controller. Value is not roll over at 255.

0b
15:9 RESERVED_1: Reserved.
RO
0b
8 SDP_SENT: it indicates if SDP packet has been sent in current frame.
RO

0b PSR_IN_TRANSITION: There is a period that source already committed to PSR active

7 but sink did not. SW should not change the source state at this time but wait until this
RO status bit is clear. The wait time should in the range of 120-250us in the worst case.
0b
6 RESERVED_2: Reserved.
RO

0b PSR_LAST_STATE: indicate last source state that VLVP PSR state machine were in
5:3 (debug) 000: PSR_disabled 001: PSR_inactive 010: PSR_transition_to_active 011:
RO PSR_active no RFB update 100: PSR_active single frame update 101: PSR_exit

0b PSR_CURRENT_STATE: indicate current source state that VLVP PSR state machine are
2:0 in 000: PSR_disabled 001: PSR_inactive 010: PSR_transition_to_active 011: PSR_active
RO no RFB update 100: PSR_active single frame update 101: PSR_exit

14.11.13 PSRCRC1B—Offset 61098h

Pipe B PSR CRC1 register

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) PSRCRC1B: [GTTMMADR_LSB + 2BF20h] + 61098h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

Datasheet 521
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CRC_VALUE_BITS_15_0_OF_R_COMPONENT

RESERVED

CRC_VALID
Bit Default &
Description
Range Access

0b CRC_VALUE_BITS_15_0_OF_R_COMPONENT: crc values bits 15 to 0 of Red

31:16
RO component

0b
15:1 RESERVED: Reserved.
RO
0b
0 CRC_VALID: CRC calculation complete and valid for previous frame.
RO

14.11.14 PSRCRC2B—Offset 6109Ch

Pipe B PSR CRC2 register

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) PSRCRC2B: [GTTMMADR_LSB + 2BF20h] + 6109Ch

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

522 Datasheet
Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CRC_VALUE_BITS_15_0_OF_B_COMPONENT

CRC_VALUE_BITS_15_0_OF_G_COMPONENT
Bit Default &
Description
Range Access

0b CRC_VALUE_BITS_15_0_OF_B_COMPONENT: crc values bits 15 to 0 of blue

31:16
RO component

0b CRC_VALUE_BITS_15_0_OF_G_COMPONENT: crc values bits 15 to 0 of green

15:0
RO component

14.11.15 VSCSDPB—Offset 610A0h

Pipe B VSC SDP register

Access Method
Type: Memory Mapped I/O Register
VSCSDPB: [GTTMMADR_LSB + 2BF20h] + 610A0h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SDP_SEND_FREQUENCY

DB1

DB0
RESERVED

Bay Trail-I SoC

Datasheet 523
 Graphics, Video and Display

Bit Default &

Description
Range Access

SDP_SEND_FREQUENCY: 00: off, not sending 01: send one every frame 10: send
0b once 11: reserved Programming note: This field shall be programmed either send once
31:30 or send one every frame when SW driver sets PSR active entry bit. When PSR is
RW enabling this field is ignored. One SDP is sent in every frame until source is in PSR active
state
0b
29:16 RESERVED: Reserved.
RW
0b DB1: Programmed by display driver in manual mode, auto-generate by display
15:8
RW controller in all other modes

0b DB0: Bits 7:4: Stereo Interface Method Specific Parameter Bits 3:0: Stereo Interface
7:0
RW Method Code. This field is programmed by display driver for stereo display configuration

14.11.16 PIPEBWIDEGAMUTCOLORCORRECTIONC01_C00COEFFICIENTS—
Offset 610B0h
When color correction matrix enable bit is set in PIPEBCONF register, each of pixels in
the pipe is multiplied with this matrix. Color matrix is used to convert pixels from one
RGB color space to another RGB color space. There are many applications for the use of
this matrix like gamut mapping between 72 percent color gamut to 92 percent color
gamut. Each coefficient is a 12-bit signed fixed-point number. The application of
coefficients are as follows:

Access Method
Type: Memory Mapped I/O Register PIPEBWIDEGAMUTCOLORCORRECTIONC01_C00COEFFICIE
(Size: 32 bits) NTS: [GTTMMADR_LSB + 2BF20h] + 610B0h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
C01_COEFFICIENT

C00_COEFFICIENT
RESERVED

RESERVED_1

Bit Default &

Description
Range Access

0b
31:28 RESERVED: Reserved.
RW
0b C01_COEFFICIENT: 12-bit 2 s complement signed value that is programmed for linea.
27:16
RW The range of the value can be from -1.999 to +1.999.

0b
15:12 RESERVED_1: Reserved.
RW
0b C00_COEFFICIENT: 12-bit 2 s complement signed value that is programmed for linea.
11:0
RW The range of the value can be from -1.999 to +1.999.

Bay Trail-I SoC

524 Datasheet
Graphics, Video and Display

14.11.17 PIPEBWIDEGAMUTCOLORCORRECTIONC02COEFFICIENT—
Offset 610B4h
Refer to the description of register
PIPEBWIDEGAMUTCOLORCORRECTIONC01_C00COEFFICIENTS.

Access Method
Type: Memory Mapped I/O Register PIPEBWIDEGAMUTCOLORCORRECTIONC02COEFFICIENT:
(Size: 32 bits) [GTTMMADR_LSB + 2BF20h] + 610B4h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

C02_COEFFICIENT
RESERVED

Bit Default &

Description
Range Access

0b
31:12 RESERVED: Reserved.
RW

0b C02_COEFFICIENT: 12-bit 2 s complement signed value that is programmed for linea.

11:0
RW The range of the value can be from -1.999 to +1.999.

14.11.18 PIPEBWIDEGAMUTCOLORCORRECTIONC11_C10COEFFICIENTS—
Offset 610B8h
Refer to the description of register
PIPEBWIDEGAMUTCOLORCORRECTIONC01_C00COEFFICIENTS.

Access Method
Type: Memory Mapped I/O Register PIPEBWIDEGAMUTCOLORCORRECTIONC11_C10COEFFICIE
(Size: 32 bits) NTS: [GTTMMADR_LSB + 2BF20h] + 610B8h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

Datasheet 525
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESERVED

C11_COEFFICIENT

C10_COEFFICIENT
RESERVED_1
Bit Default &
Description
Range Access

0b
31:28 RESERVED: Reserved.
RW
0b C11_COEFFICIENT: 12-bit 2 s complement signed value that is programmed for linea.
27:16
RW The range of the value can be from -1.999 to +1.999.

0b
15:12 RESERVED_1: Reserved.
RW
0b C10_COEFFICIENT: 12-bit 2 s complement signed value that is programmed for linea.
11:0
RW The range of the value can be from -1.999 to +1.999.

14.11.19 PIPEBWIDEGAMUTCOLORCORRECTIONC12COEFFICIENT—
Offset 610BCh
Refer to the description of register
PIPEBWIDEGAMUTCOLORCORRECTIONC01_C00COEFFICIENTS.

Access Method
Type: Memory Mapped I/O Register PIPEBWIDEGAMUTCOLORCORRECTIONC12COEFFICIENT:
(Size: 32 bits) [GTTMMADR_LSB + 2BF20h] + 610BCh

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED

C12_COEFFICIENT

Bit Default &

Description
Range Access

0b
31:12 RESERVED: Reserved.
RW

0b C12_COEFFICIENT: 12-bit 2 s complement signed value that is programmed for linea.

11:0
RW The range of the value can be from -1.999 to +1.999.

Bay Trail-I SoC

526 Datasheet
Graphics, Video and Display

14.11.20 PIPEBWIDEGAMUTCOLORCORRECTIONC21_C20COEFFICIENTS—
Offset 610C0h
Refer to the description of register
PIPEBWIDEGAMUTCOLORCORRECTIONC01_C00COEFFICIENTS.

Access Method
Type: Memory Mapped I/O Register PIPEBWIDEGAMUTCOLORCORRECTIONC21_C20COEFFICIE
(Size: 32 bits) NTS: [GTTMMADR_LSB + 2BF20h] + 610C0h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
C21_COEFFICIENT

RESERVED_1

C20_COEFFICIENT
RESERVED

Bit Default &

Description
Range Access

0b
31:28 RESERVED: Reserved.
RW

0b C21_COEFFICIENT: 12-bit 2 s complement signed value that is programmed for linea.

27:16
RW The range of the value can be from -1.999 to +1.999.

0b
15:12 RESERVED_1: Reserved.
RW

0b C20_COEFFICIENT: 12-bit 2 s complement signed value that is programmed for linea.

11:0
RW The range of the value can be from -1.999 to +1.999.

14.11.21 PIPEBWIDEGAMUTCOLORCORRECTIONC22COEFFICIENT—
Offset 610C4h
Refer to the description of register
PIPEBWIDEGAMUTCOLORCORRECTIONC01_C00COEFFICIENTS.

Access Method
Type: Memory Mapped I/O Register PIPEBWIDEGAMUTCOLORCORRECTIONC22COEFFICIENT:
(Size: 32 bits) [GTTMMADR_LSB + 2BF20h] + 610C4h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

Datasheet 527
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESERVED

C22_COEFFICIENT
Bit Default &
Description
Range Access

0b
31:12 RESERVED: Reserved.
RW
0b C22_COEFFICIENT: 12-bit 2 s complement signed value that is programmed for linea.
11:0
RW The range of the value can be from -1.999 to +1.999.

14.11.22 ADPA—Offset 61100h

Analog Display Port Register CRT port control (dprrega.v adp_Q)

Access Method
Type: Memory Mapped I/O Register
ADPA: [GTTMMADR_LSB + 2BF20h] + 61100h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00040000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CRT_Hot_Plug_Detection_Channel_Status

CRT_Hot_Plug_Voltage_Compare_Value
Analog_DisplayPort_Enable

Reserved

CRT_Hot_Plug_Detect_Warmup_Time

CRT_Hot_Plug_Reference_Voltage
Force_CRT_Hot_Plug_Detect_Trigger
CRT_Hot_Plug_Detect_Sampling_Period
Pipe_Select

CRT_Hot_Plug_Detection_Enable

Reserved_1

CRTFullScaleOutputVoltageTrimmingControl

VSYNC_Polarity_Control
HSYNC_Polarity_Control
Reserved_2
Reserved_3
Reserved_4
CRT_Hot_Plug_Circuit_Activation_Period

Bit Default &

Description
Range Access

Analog_DisplayPort_Enable: Project: All Default Value: 0b This bit enables or

0b disables the analog port CRT DAC and syncs outputs. Value Name Description Project 0b
31
RW Disable Disable the analog port DAC and disable output of syncs All 1b Enable Enable
the analog port DAC and enable output of syncs All

Bay Trail-I SoC

528 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

0b Pipe_Select: Project: All Default Value: 0b Determines which pipe output will feed this
30
RW DAC port. Value Name Description Project 0b Pipe A Pipe A All 1b Pipe B Pipe B All

0b
29:26 Reserved: Project: All Format:
RW
CRT_Hot_Plug_Detection_Channel_Status: Project: All AccessType: Read Only
Default Value: 00b These bits are set when a CRT hot plug or unplug event has been
0b detected and indicate which color channels were attached. Write a one to these bits to
25:24 clear the status. The rising or falling edges of these bits are ORed together to go to the
RO main ISR CRT hot plug register bit. Value Name Description Project 00b None No
channels attached All 01b Blue Blue channel only is attached All 10b Green Green
channel only is attached All 11b Both Both blue and green channel attached All
CRT_Hot_Plug_Detection_Enable: Project: All Default Value: 0b Hot plug detection
0b is used to set status bits or an interrupt on the connection or disconnection of a CRT to
23
RW the analog display port. Value Name Description Project 0b Disable CRT hot plug
detection is disabled All 1b Enable CRT hot plug detection is enabled All

0b CRT_Hot_Plug_Circuit_Activation_Period: Project: All Default Value: 0b This bit

22 sets the activation period for the CRT hot plug circuit. Value Name Description Project 0b
RW 64 cdclk 64 cdclk periods All 1b 128 cdclk 128 cdclk periods All

CRT_Hot_Plug_Detect_Warmup_Time: Project: All Default Value: 0b This bit sets

0b the warmup time for the CRT hot plug circuit. Value Name Description Project 0b 2M
21
RW pcdclks 2M pcdclks warmup (approximately 5ms) All 1b 4M pcdclks 4M pcdclks warmup
(approximately 10ms) All
CRT_Hot_Plug_Detect_Sampling_Period: Project: All Default Value: 0b This bit
0b determines the length of time between sampling periods when the transcoder is
20
RW disabled. Value Name Description Project 0b 1G pcdclks 1G pcdclks (approximately 2
seconds) All 1b 2G pcdclks 2G pcdclks (approximately 4 seconds) All
CRT_Hot_Plug_Voltage_Compare_Value: Project: All Default Value: 01b A0
01b Compare value for Vref to determine whether the analog port is connected to a CRT.
19:18
RW Value Name Description Project 00b 80 80 All 01b A0 A0 (Default) All 10b C0 C0 All 11b
E0 E0 (bit 17 must be = 1) All

0b CRT_Hot_Plug_Reference_Voltage: Project: All Default Value: 0b Value Name

17
RW Description Project 0b 325mv 325mv All 1b 475mv 475mv (bits 19:18 must be = 11) All

Force_CRT_Hot_Plug_Detect_Trigger: Project: All Default Value: 0b Triggers a CRT

hotplug/unplug detection cycle independent of the hot plug detection enable bit. This bit
0b is automatically cleared after the detection is completed. The result of this trigger is
16
RW reflected in the CRT Hot Plug Detection Status. Software must reset status after a force
CRT detect trigger. Value Name Description Project 0b No Trigger No Trigger All 1b Force
Trigger Force Trigger All
0b
15:10 Reserved_1: Project: All Format:
RW
0b CRTFullScaleOutputVoltageTrimmingControl: Project: All Default Value: 0b This
9:5
RW controls CRT output voltage trimming to ensure the output voltage is withing VESA spec.

VSYNC_Polarity_Control: Project: All Default Value: 0b The output VSYNC polarity is

0b controlled by this bit. This is used to implement display modes that require inverted
4
RW polarity syncs and to set the disabled state of the VSYNC signal. Value Name Description
Project 0b Low Active Low All 1b High Active High All
HSYNC_Polarity_Control: Project: All Default Value: 0b The output HSYNC polarity is
0b controlled by this bit. This is used to implement display modes that require inverted
3
RW polarity syncs and to set the disabled state of the HSYNC signal. Value Name Description
Project 0b Low Active Low All 1b High Active High All

0b
2 Reserved_2: Project: All Forma
RW

Reserved_3: Project: All Forma Monochrome Enable: [DevVLVP] If the CRT display is a
0b monochrom type, SW driver shall set this bit to enable the CRT circuit to drive only the
1
RW green channel to CRT and gate off the red and blue channels. 0 = Monochrome disabled
(default) 1 = Monochrome enabled

Bay Trail-I SoC

Datasheet 529
 Graphics, Video and Display

Bit Default &

Description
Range Access

Reserved_4: Project: All Forma Monochrome Enable: [DevVLVP] If the CRT display is a
0b monochrom type, SW driver shall set this bit to enable the CRT circuit to drive only the
0 green channel to CRT and gate off the red and blue channels. 0 = Monochrome disabled
RW (default) 1 = Monochrome enabled 0 = 1.35V is used for analog supply voltage (default)
1 = 1.25V is used for analog supply voltage

14.11.23 CRTIO_DFX—Offset 61104h

CRT port control (dprrega.v crt_dfx)

Access Method
Type: Memory Mapped I/O Register
CRTIO_DFX: [GTTMMADR_LSB + 2BF20h] + 61104h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00008000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DIAGNOSTIC_RO
RESERVED

BONUS_FOR_CRT

MODESEL_DFX_MODE_
CHOPPING_ENABLE

BONUS_FOR_DPR

Bit Default &

Description
Range Access

0b
31:24 RESERVED: read as zero
RW
0b
23:16 BONUS_FOR_CRT: bonus for CRT port control
RW
1b
15 CHOPPING_ENABLE: Chopping enable (for BG circuit)
RW
0b
14:12 BONUS_FOR_DPR: bonus for DPR crt port control
RW
0b
11:8 MODESEL_DFX_MODE_: ModeSel (DFx mode)
RW
0b
7:0 DIAGNOSTIC_RO: Observe signals at CRTIO AccessType: Read Only
RO

14.11.24 PORT_HOTPLUG_EN—Offset 61110h

DPD enable control (dprrega.v ql_hotplugen_Q)

Access Method

Bay Trail-I SoC

530 Datasheet
Graphics, Video and Display

Type: Memory Mapped I/O Register

PORT_HOTPLUG_EN: [GTTMMADR_LSB + 2BF20h] + 61110h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000020h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0
DISPLAYPORT_HDMI_D_HOT_PLUG_INTERRUPT_DETECT_ENABLE
SDVOB_HOT_PLUG_INTERRUPT_DETECT_ENABLE
RESERVED

DISPLAYPORT_HDMI_B_HOT_PLUG_INTERRUPT_DETECT_ENABLE
DISPLAYPORT_HDMI_C_HOT_PLUG_INTERRUPT_DETECT_ENABLE

SDVOC_HOT_PLUG_INTERRUPT_DETECT_ENABLE

PIPE_B_AUDIO_INTERRUPT_DETECT_ENABLE
PIPE_A_AUDIO_INTERRUPT_DETECT_ENABLE

RESERVED_1

RESERVED_2

DP_HOTPLUG_SHORT_PULSE_DURATION

RESERVED_3

RESERVED_4
RESERVED_5
RESERVED_6

RESERVED_7

RESERVED_8
RESERVED_9
RESERVED_10

RESERVED_11
Bit Default &
Description
Range Access

0b
31:30 RESERVED: mbz
RW
DISPLAYPORT_HDMI_B_HOT_PLUG_INTERRUPT_DETECT_ENABLE: [DevCDV,
DevCTG, DevELK] This will enable the consideration of the hot plug interrupt status bit
0b for DisplayPort B in the Port Hotplug Status register, offset 61114h. Please note that
29 software must set this bit at boot in order to detect the HPD input buffer live state.
RW Since setting this bit may generate an interrupt, it must not be cleared and reset as part
of interrupt processing. 0 = DisplayPort or HDMIB Hot Plug Detect Disabled (Default) 1
= DisplayPort or HDMIB Hot Plug Detect Enabled

DISPLAYPORT_HDMI_C_HOT_PLUG_INTERRUPT_DETECT_ENABLE: [DevCDV,
DevCTG, DevELK] This will enable the consideration of the hot plug interrupt status bit
0b for DisplayPort C in the Port Hotplug Status register, offset 61114h. Please note that
28 software must set this bit at boot in order to detect the HPD input buffer live state.
RW Since setting this bit may generate an interrupt, it must not be cleared and reset as part
of interrupt processing. 0 = DisplayPort or HDMIC Hot Plug Detect Disabled (Default) 1
= DisplayPort or HDMIC Hot Plug Detect Enabled
DISPLAYPORT_HDMI_D_HOT_PLUG_INTERRUPT_DETECT_ENABLE: [DevCTG]
This will enable the consideration of the hot plug interrupt status bit for DisplayPort D in
0b the Port Hotplug Status register, offset 61114h. Please note that software must set this
27 bit at boot in order to detect the HPD input buffer live state. Since setting this bit may
RW generate an interrupt, it must not be cleared and reset as part of interrupt processing. 0
= DisplayPort or HDMID Hot Plug Detect Disabled (Default) 1 = DisplayPort or HDMID
Hot Plug Detect Enabled

Bay Trail-I SoC

Datasheet 531
 Graphics, Video and Display

Bit Default &

Description
Range Access

SDVOB_HOT_PLUG_INTERRUPT_DETECT_ENABLE: [DevCTG] This will enable the

0b consideration of the hot plug interrupt status bit in the Port Hotplug Status register,
26
RW offset 61114h. This bit enables detection on the SDVOB interrupt input pin pair. 0 =
SDVOB Hot Plug Detect Disabled (Default) 1 = SDVOB Hot Plug Detect Enabled
SDVOC_HOT_PLUG_INTERRUPT_DETECT_ENABLE: [DevCTG] This will enable the
0b consideration of the hot plug interrupt status bit in the Port Hotplug Status register,
25
RW offset 61114h. This bit enables detection on the SDVOC interrupt input pin pair. 0 =
SDVOC Hot Plug Detect Disabled (Default) 1 = SDVOC Hot Plug Detect Enabled

PIPE_A_AUDIO_INTERRUPT_DETECT_ENABLE: [DevCDV, DevCL, DevCTG,

DevVLVP ] This bit enables consideration of the pipe A audio interrupt status bit in the
0b Port Hotplug Status Register, offset 61114h. It relates to the HDMI port that has audio
24
RW enabled and can only be used in combination with TMDS encoding. This bit is only to be
used for integrated HDMI. 0 = Audio interrupt detect disabled (Default) 1 = Audio
interrupt detect enabled

PIPE_B_AUDIO_INTERRUPT_DETECT_ENABLE: [DevVLVP ] This bit enables

0b consideration of the pipe B audio interrupt status bit in the Port Hotplug Status Register,
23 offset 61114h. It relates to the HDMI port that has audio enabled and can only be used
RW in combination with TMDS encoding. This bit is only to be used for integrated HDMI. 0 =
Audio interrupt detect disabled (Default) 1 = Audio interrupt detect enabled
0b
22:19 RESERVED_1: mbz
RW
RESERVED_2: [DevVLVP] MBZ TV Hot Plug Detect Interrupt Enable: [DevCL, DevCTG]
0b This will enable the consideration of the TV hot plug interrupt status bit. 0 = TV Hot Plug
18
RW Detect Disabled (bit 10 of the port hotplug status register no longer detects interrupts,
Default) 1 = TV Hot Plug Detect Enabled

DP_HOTPLUG_SHORT_PULSE_DURATION: [DevCDV, DevCTG, DevELK] These bits

0b define the duration of the pulse defined as a short pulse for DisplayPort ports. Pulse less
17:16 than this value is detected short pulse. Pulse larger than this value is detected long
RW pulse. For DP, this shall use 2ms as threshold. 00 = 2mS (Default) 01 = 4.5mS 10 =
6mS 11 = 100mS
0b
15:10 RESERVED_3: mbz
RW
RESERVED_4: [DevVLVP] MBZ. This bit is the same as bit 23 in 61100h [DevCDV,
0b DevCTG, DevBW, DevCL, DevBLC] CRT Hot plug Interrupt Enable: Hotplug detection is
9 used to cause an interrupt or status bit based on the connection or disconnection of a
RW CRT to the analog video connection. 0 = No hot plug interrupt is enabled (Default) 1 =
Hot plug detection is enabled
RESERVED_5: [DevVLVP] MBZ. This bit is the same as bit 22 in 61100h [DevCDV,
0b DevCTG] CRT Hot plug Circuit Activation Period: This bit sets the activation period for
8
RW the CRT hot plug circuit detection. Setting this bit to 1 is required for the correct
operation of CRT DAC detection. 0 = 32 cdclk periods (Default) 1 = 64 cdclk periods

RESERVED_6: [DevVLVP] MBZ. This bit is the same as bit 21 in 61100h [DevCDV,
0b DevCTG, DevBW, DevCL, DevBLC] CRT DAC on time Value: Powerup time for 0 = CRT
7
RW DAC requires 2M cdclks for warmup (Default) 1 = CRT DAC requires 4M cdclks for
warmup
RESERVED_7: [DevVLVP] MBZ. This bit is the same as bit 19:18 in 61100h [DevCDV,
01b DevCTG, DevBW, DevCL, DevBLC] CRT Hot plug Voltage Compare Value: Compare value
6:5 for CRT hotplug detect Vref to determine whether the analog port is connected to a CRT.
RW The voltage is forced at the beginning of the active region of the screen every 2
seconds. 00 = A0, 01 = B0, (Default) 10 = C0 11 = D0

RESERVED_8: [DevVLVP] MBZ. This bit is the same as bit 20 in 61100h [DevCDV,
0b DevCTG, DevBW, DevCL, DevBLC] CRT Hot Plug Detect Delay: This bit determines the
4
RW length of time between polling periods when the DAC/pipe are disabled 0 = 1G cdclks
(default) 1 = 2G cdclks

Bay Trail-I SoC

532 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

RESERVED_9: [DevVLVP] MBZ [DevCDV, DevCTG, DevBW, DevCL, DevBLC] Force CRT
detect trigger: Triggers a CRT hotplug/unplug detection cycle independent of the
interrupt enable bit. Bits 5:8 of this register must be correctly programmed when
0b forcing a trigger. This bit is automatically cleared after the detection is completed. The
3
RW result of this trigger is reflected in bits 9:8 of the port hotplug interrupt status register.
The CRT interrupt status bit #11 in the hot plug status register (61114) will get set the
first time Force CRC detect trigger is used after reset. Software must reset status after a
force CRT detect trigger. 0 = No trigger (Default) 1 = Trigger

0b RESERVED_10: [DevVLVP] MBZ. This bit is the same as bit 17 in 61100h [DevCTG-B]
2 CRT DAC hot plug detection reference voltage selection: 0 = 325mv, bits[6:5] should be
RW set to 01 (Default) 1 = 475mv, bits[6:5] should be set to 11

0b
1:0 RESERVED_11: mbz
RW

14.11.25 PORT_HOTPLUG_STAT—Offset 61114h

CRT port control (dprrega.v porthotst_aR)

Access Method
Type: Memory Mapped I/O Register
PORT_HOTPLUG_STAT: [GTTMMADR_LSB + 2BF20h] + 61114h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DISPLAYPORT_B_HOT_PLUG_INTERRUPT_DETECT_STATUS
DISPLAYPORT_HDMIB_HOT_PLUG_INPUT_BUFFER_LIVE_STATE
DISPLAYPORT_HDMIC_HOT_PLUG_INPUT_BUFFER_LIVE_STATE
DISPLAYPORTD_HOT_PLUG_INPUT_BUFFER_LIVE_STATE
RESERVED

PIPE_A_AUDIO_INTERRUPT_DETECT_STATUS
PIPE_B_AUDIO_INTERRUPT_DETECT_STATUS
PIPE_B_AUDIO_INTERRUPT_LIVE_STATE

DISPLAYPORT_B_AUX_INTERRUPT_STATUS
SDVO_C_HOT_PLUG_INTERRUPT_DETECT_STATUS
DISPLAYPORT_D_HOT_PLUG_INTERRUPT_DETECT_STATUS

DISPLAYPORT_C_HOT_PLUG_INTERRUPT_DETECT_STATUS

PIPE_A_AUDIO_INTERRUPT_LIVE_STATE

SDVO_B_HOT_PLUG_INTERRUPT_DETECT_STATUS
DIGITAL_PORT_B_AUDIO_REQUEST_LIVE_STATE

TV_HOT_PLUG_INTERRUPT_STATUS

DISPLAYPORT_D_AUX_INTERRUPT_STATUS
DIGITAL_PORT_C_AUDIO_REQUEST_LIVE_STATE

CRT_HOT_PLUG_INTERRUPT_STATUS

DISPLAYPORT_C_AUX_INTERRUPT_STATUS
RESERVED_1

RESERVED_2

RESERVED_3

RESERVED_4

Bay Trail-I SoC

Datasheet 533
 Graphics, Video and Display

Bit Default &

Description
Range Access

0b
31:30 RESERVED: mbz
RW
DISPLAYPORT_HDMIB_HOT_PLUG_INPUT_BUFFER_LIVE_STATE: [DevCDV,
DevCTG, DevELK] This bit is read-only. It reflects the real-time state of the of the hot
0b plug input (HPD pin) on DisplayPort or HDMI B when bit 29 of the hotplug enable
29 register, offset 61110h is set. This pin signal is active high. This does not feed into the
RO first line interrupt status register. This bit should be read to confirm cable connection
prior to attempting EDID read. 1 = HPD detected active 0 = HPD detected inactive
AccessType: Read Only

DISPLAYPORT_HDMIC_HOT_PLUG_INPUT_BUFFER_LIVE_STATE: [DevCDV,
DevCTG, DevELK] This bit is read-only. It reflects the real-time state of the of the hot
0b plug input (HPD pin) on DisplayPortC when bit of this register is set. This pin signal is
28
RO active high. This does not feed into the first line interrupt status register. This bit should
be read to confirm cable connection prior to attempting EDID read. 1 = HPD detected
high 0 = HPD detected low AccessType: Read Only

DISPLAYPORTD_HOT_PLUG_INPUT_BUFFER_LIVE_STATE: [DevCTG] This bit is

read-only. It reflects the real-time state of the of the hot plug input (HPD pin) on
0b DisplayPortD when bit of this register is set. This pin signal is active high. This does not
27 feed into the first line interrupt status register. Please note that port D is intended for
RO LFP use and therefore HPD may not be present. Bit 2 of the DPD control register must
therefore be read to determine whether DPD is used in the system. 1 = HPD detected
high 0 = HPD detected low AccessType: Read Only
0b
26:24 RESERVED_1: mbz
RW
PIPE_B_AUDIO_INTERRUPT_LIVE_STATE: [DevVLVP] This read-only bit is used
0b only in ports that use TMDS encoding. It reflects the state of the pipe B audio interrupt
23 request for HDCP when bit 1 of this register is set. This pin signal is active high. It does
RO not feed into the first line interrupt status register. 1 = HDCP invocation requested from
audio 0 = HDCP disable requested from audio AccessType: Read Only

DISPLAYPORT_D_HOT_PLUG_INTERRUPT_DETECT_STATUS: [DevCTG] This

reflects hot plug interrupt status on DisplayPort D. Graphics software must write a one
0b to these bits to clear the status. This bit is used for either monitor hotplug/unplug or for
22:21 notification of a sink event. This bit feeds into the first line interrupt status register when
RW/1C bit 27 of the hotplug enable status register is set. 00 = DisplayPort D Hot Plug event not
detected 1x = DisplayPort D long pulse Hot Plug event detected X1 = DisplayPort D
short pulse Hot Plug event detected AccessType: One to Clear
DISPLAYPORT_C_HOT_PLUG_INTERRUPT_DETECT_STATUS: [DevCDV, DevCTG,
DevELK] This reflects hot plug interrupt status on DisplayPort or HDMI C. Graphics
software must write a one to these bits to clear the status. This bit is used for either
monitor hotplug/unplug or for notification of a sink event. This bit feeds into the first line
0b interrupt status register when bit 28 of the hotplug enable status register is set. Please
20:19
RW/1C note that these bits should be considered in conjunction with bit 28, the hot plug input
buffer live state, when determining further action: if bit 28 = 0, the bits should be
cleared and the port must be disabled. 00 = DisplayPort/HDMI C Hot Plug event not
detected 1x = DisplayPort/HDMI C long pulse Hot Plug event detected X1 = DisplayPort
C short pulse Hot Plug event detected AccessType: One to Clear

DISPLAYPORT_B_HOT_PLUG_INTERRUPT_DETECT_STATUS: [DevCDV, DevCTG,

DevELK] This reflects hot plug interrupt status on DisplayPort B. Graphics software must
write a one to these bits to clear the status. This bit is used for either monitor hotplug/
unplug or for notification of a sink event. This bit feeds into the first line interrupt status
0b register when bit 29 of the hotplug enable status register is set. Please note that these
18:17
RW/1C bits should be considered in conjunction with bit 29, the hot plug input buffer live state,
when determining further action: if bit 29 = 0, the bits should be cleared and the port
must be disabled. 00 = DisplayPort/HDMI B Hot Plug event not detected 1x =
DisplayPort/HDMI B long pulse Hot Plug event detected X1 = DisplayPort B short pulse
Hot Plug event detected AccessType: One to Clear

Bay Trail-I SoC

534 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

PIPE_A_AUDIO_INTERRUPT_LIVE_STATE: [DevCDV, DevCTG, DevCL] This read-

only bit is used only in ports that use TMDS encoding. It reflects the state of the pipe A
0b audio interrupt request for HDCP when bit 1 of this register is set. This pin signal is
16
RO active high. It does not feed into the first line interrupt status register. 1 = HDCP
invocation requested from audio 0 = HDCP disable requested from audio AccessType:
Read Only
DIGITAL_PORT_B_AUDIO_REQUEST_LIVE_STATE: [DevCDV, DevCTG, DevCL]
This read-only bit is only used on ports using audio. It reflects the state of audio HDCP
0b request when bit 17 of this register is set if audio is enabled on this port. This pin signal
15
RO is active high. This does not feed into the first line interrupt status register. 1 = HDCP
invocation requested from audio 0 = HDCP disable requested from audio AccessType:
Read Only
DIGITAL_PORT_C_AUDIO_REQUEST_LIVE_STATE: [DevCDV, DevCTG, DevCL]
This read-only bit is only used on ports using audio. It reflects the state of audio HDCP
0b request when bit 19 of this register is set if audio is enabled on this port. This pin signal
14
RO is active high. This does not feed into the first line interrupt status register. 1 = HDCP
invocation requested from audio 0 = HDCP disable requested from audio AccessType:
Read Only
0b
13:12 RESERVED_2: mbz
RW
CRT_HOT_PLUG_INTERRUPT_STATUS: [DevCDV, DevCTG, DevBW, DevCL, DevBLC]
This bit is set when a CRT hot plug or unplug event has been detected. A hot plug or
unplug event is defined as the change in connection state of the CRT as determined by
the hardware CRT detect sequence which is enabled through bit #9 (CRT hot plug
0b interrupt enable) or bit #3 (Force CRT detect trigger) in the Port_HotPlug_En register
11
RW/1C 0x61110. After reset, the CRT is considered unconnected even if physically connected
until the first detect sequence occurs. Physically plugging or unplugging the CRT device
will also be detected as a change of connection state. Writing a 1 to this bit clears it. 0
=CRT Interrupt has not occurred 1 = CRT Interrupt has occurred AccessType: One to
Clear
TV_HOT_PLUG_INTERRUPT_STATUS: [DevCTG, DevBW, DevCL, DevBLC] This bit is
0b set when a TV hot plug or unplug event has been detected. Reflects the state of bit 31 of
10 the TV DAC state register, offset 68004-68007h. Software must write a one to these bits
RW/1C to clear the status. 0 =TV Interrupt has not occurred 1 = TV Interrupt has occurred
AccessType: One to Clear
RESERVED_3: [DevVLVP] MBZ. These info are recorded in 61100h ADPA
register[25:24] [DevCDV, DevCTG, DevBW, DevCL, DevBLC] CRT Hot Plug Detection
0b Status (read only): These bits are set when a CRT hot plug or unplug event has been
9:8
RW/1C detected. 00 = No channels attached (default) 01 = Blue channel only is attached 10 =
Green channel only is attached 11 = Both blue and green channel attached AccessType:
One to Clear
0b
7 RESERVED_4: mbz
RW
DISPLAYPORT_D_AUX_INTERRUPT_STATUS: [DevCTG] This bit is set when a
0b transaction on AUX channel D has completed or timed out. This bit feeds into the first
6 line interrupt status register when bit 29 of the AUX channel D control register is set.
RW/1C Writing a 1 to this bit clears it. 0 = AUX channel D Interrupt has not occurred 1 = AUX
channel D Interrupt has occurred AccessType: One to Clear
DISPLAYPORT_C_AUX_INTERRUPT_STATUS: [DevCTG, DevCDV] This bit is set
0b when a transaction on AUX channel C has completed or timed out. This bit feeds into the
5 first line interrupt status register when bit 29 of the AUX channel C control register is
RW/1C set. Writing a 1 to this bit clears it. 0 = AUX channel C Interrupt has not occurred 1 =
AUX channel C Interrupt has occurred AccessType: One to Clear

DISPLAYPORT_B_AUX_INTERRUPT_STATUS: [DevCTG, DevCDV] This bit is set

0b when a transaction on AUX channel B has completed or timed out. This bit feeds into the
4 first line interrupt status register when bit 29 of the AUX channel B control register is
RW/1C set. Writing a 1 to this bit clears it. 0 = AUX channel B Interrupt has not occurred 1 =
AUX channel B Interrupt has occurred AccessType: One to Clear

Bay Trail-I SoC

Datasheet 535
 Graphics, Video and Display

Bit Default &

Description
Range Access

SDVO_C_HOT_PLUG_INTERRUPT_DETECT_STATUS: [DevCTG, DevCDV] This

reflects hot plug interrupt status on SDVO port C. Graphics software must write a one to
0b these bits to clear the status. This bit is used for either monitor hotplug/unplug or for
3 notification of an HDCP state change request from the audio driver over SDVO only. This
RW/1C bit feeds into the first line interrupt status register when bit 25 of the hotplug enable
status register is set. 0 = SDVO Hot Plug event not detected 1 = SDVO Hot Plug event
detected AccessType: One to Clear
SDVO_B_HOT_PLUG_INTERRUPT_DETECT_STATUS: [DevCTG, DevCDV] This
reflects hot plug interrupt status on SDVO port B. Graphics software must write a one to
0b these bits to clear the status. This bit is used for either monitor hotplug/unplug or for
2 notification of an HDCP state change request from the audio driver over SDVO only. This
RW/1C bit feeds into the first line interrupt status register when bit 26 of the hotplug enable
status register is set. 0 = SDVO Hot Plug event not detected 1 = SDVO Hot Plug event
detected AccessType: One to Clear

PIPE_A_AUDIO_INTERRUPT_DETECT_STATUS: [DevCTG, DevCDV, DevCL] This

reflects a request for integrated HDCP state change set by audio driver and propagated
through the audio hardware. The graphics software must write a one to this bit to clear
0b the status. Upon clearing this bit, the audio ready bit is cleared in the audio registers.
1 The graphics software then must reset audio ready bit 14 in the audio control register,
RW/1C offset 620B4h to 1 when the HDCP interrupt has been serviced. This bit feeds into the
first line interrupt status register when bit 24 of the hotplug enable status register is set
0 = Audio interrupt event not detected 1 = Audio interrupt event detected AccessType:
One to Clear

PIPE_B_AUDIO_INTERRUPT_DETECT_STATUS: [DevCTG, DevCDV, DevCL] This

reflects a request for integrated HDCP state change set by audio driver and propagated
through the audio hardware. The graphics software must write a one to this bit to clear
0b the status. Upon clearing this bit, the audio ready bit is cleared in the audio registers.
0 The graphics software then must reset audio ready bit 14 in the audio control register,
RW/1C offset 620B4h to 1 when the HDCP interrupt has been serviced. This bit feeds into the
first line interrupt status register when bit 23 of the hotplug enable status register is set
0 = Audio interrupt event not detected 1 = Audio interrupt event detected AccessType:
One to Clear

14.11.26 SDVOHDMIB—Offset 61140h

Digital Display Port B Control Register HDMIB port control (dprrega.v sdvo_bQ)

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) SDVOHDMIB: [GTTMMADR_LSB + 2BF20h] + 61140h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000018h

Bay Trail-I SoC

536 Datasheet
Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0

NULL_PACKETS_ENABLED_DURING_VSYNC
SDVO_HDMIB_ENABLE_DIGITAL_DISPLAY_PORT_B_ENABLE
PIPE_SELECT

COLOR_FORMAT
RESERVED

COLOR_RANGE_SELECT

DIGITAL_PORT_B_DETECTED
AUDIO_OUTPUT_ENABLE
SDVO_HDMIB_CLOCK_OUTPUT_INVERSION_TEST_MODE

SYMBOL_CLOCK_DUTY_CYCLE

HDCP_PORT_SELECT

SYNC_POLARITY
ENCODING
RESERVED_1

RESERVED_2
RESERVED_3
RESERVED_4
RESERVED_5

RESERVED_6

RESERVED_7
Bit Default &
Description
Range Access

SDVO_HDMIB_ENABLE_DIGITAL_DISPLAY_PORT_B_ENABLE: Disabling this port

will put it in its lowest power state. Port enable takes place on the Vblank after being
written. Both this bit and bit 6 of this register must be enabled to send audio over this
port. This port must not be enabled simultaneously with DisplayPort B. [DevIBX] When
disabling the port, software must temporarily enable the port with transcoder select (bit
0b #30) cleared to 0 after disabling the port. This is workaround for hardware issue where
31 the transcoder select set to 1 will prevent DisplayPortB from being enabled on
RW transcoder A. [DevIBX] Software must write this bit twice when enabling the port
(setting to 1 ) as a workaround for hardware issue that may result in first write getting
masked. [DevIBX] Toggle this bit off then on at the end of mode set sequence when
enabling HDMI 12-bit per color with pixel repeat 1 = Enable. This bit enables the Digital
Display Port B interface for HDMI or SDVO modes. 0 = Disable and tristates the Digital
Display Port B interface for HDMI or SDVO modes.

0b PIPE_SELECT: This bit determines from which display pipe the source data will
30 originate. This only applies to devices with dual display pipes. Pipe selection takes place
RW on the Vblank after being written 0 = Pipe A 1 = Pipe B
RESERVED: [DevCDV]: [DevCTG, DevBW, DevCL, DevBLC] Stall Select: This bit selects
stall for external scaling functionality only on SDVO. Programming notes: It is only valid
to have a single stall indication to a particular pipe. In cases where two ports are being
0b driven from a single pipe, one of the ports must set this bit to 0. Only sDVOB or sDVOC
29
RW can select the stall function, as only a single stall input is available between the two
interfaces. Set the stall input to unused before programming the external device
creating the stall. 0 = Stall input signal is unused on this port 1 = Stall input signal is
used to stall the pipe attached to this port
COLOR_FORMAT: This field selects the number of bits per color sent to a receiver
device connected to this port. Color format takes place on the Vblank after being
0b written. Color format change must be done as a part of mode set since different color
28:26 depths require different pixel clock settings. Selecting a pixel color depth higher or lower
RW than the pixel color depth of the frame buffer results in dithering the output stream. 000
= 8 bits per color (Default, x3 mode) 001 = RESERVED for 10 bits per color 010 =
RESERVED for 6 bits per color 011 = RESERVED 1xx = RESERVED
0b
25:19 RESERVED_1: Reserved.
RW

Bay Trail-I SoC

Datasheet 537
 Graphics, Video and Display

Bit Default &

Description
Range Access

0b SDVO_HDMIB_CLOCK_OUTPUT_INVERSION_TEST_MODE: Please note that this

18 applies to all modes and is instantly updated. 1 = sDVO/HDMIB Clock output is inverted
RW 0 = sDVO/HDMIB Clock output is NOT inverted (DEFAULT)
SYMBOL_CLOCK_DUTY_CYCLE: [DevCDV, DevCTG, DevCL] These bits control the
output clock duty cycle to enable EMI mitigation on the external UDI link. 10/90 cycle
0b has been measured to have ~13dB EMI improvement over a 50/50 duty cycle. 00 =
17:16
RW (Default) 50/50 duty cycle: Clock output is 0000011111 01 = 10/90 duty cycle: Clock
output is 0111111111 followed by 0000000001 10 = 20/80 duty cycle: Clock output is
0011111111 followed by 0000000011 11 = Reserved
RESERVED_2: [DevCDV, DevVLVP]: [DevBW, DevCL, DevBLC] Port Lane Reversal: This
0b bit reverses the order of the 4 lanes within the port. Port lane reversal takes place on
15
RW the Vblank after being written. It is an OEM configurable feature. 0 = (Default) Not
reversed 1 = Reversed
0b
14 RESERVED_3: Reserved.
RW

0b RESERVED_4: [DevCDV, DevVLVP]: [DevBW, DevCL, DevBLC] Clock Output Disable:

13 This bit disables the clock output on the digital output port. For 8b/10b modes the clock
RW output should be disabled. 0 = (Default) Clock output enabled 1 = Clock output disabled
RESERVED_5: [DevCDV, DevVLVP]: [DevBW, DevCL, DevBLC, DevCDV] Scrambling
0b enable: This bit enables scrambling for UDI-related modes using ANSI 8b/10b or TMDS
12 encoding. It is not used with SDVO encoding. Software must set this bit appropriately
RW when enabling the port. Scrambling is reset at the beginning of horizontal sync. 0 =
Scrambling disabled (Default) 1 = Scrambling enabled
ENCODING: [DevCDV, DevCTG, DevCL] These bits select among encoding types. It is
set as part of the display detection process. Control codes for ANSI 8b/10b and TMDS
encoding must be programmed using these bits. Please note that ANSI 8b/10b and
0b TMDS encoding can only be enabled on one port at a time, as only one HPD pin is
11:10 available for use between ports B and C. 00 = Reserved 01 = Reserved 10 = TMDS
RW encoding ([DevCL, DevCTG, DevCDV, DevVLVP] external link and HDMI only) See the
HDMI specification for control codes. In this mode, the external HPD pin is used to
generate hotplug. In fixed frequency mode, start of fill and end of fill values for TMDS
must be programmed using register 6114C. 11 = Reserved
NULL_PACKETS_ENABLED_DURING_VSYNC: This bit enables a null packet (32
bytes of a value of 0) to be sent when Vsync=1 on this port, required for HDMI
0b operation. It also enables preambles and guardbands prior to the null packets, in
9
RW accordance with the HDMI specification. It is only valid for modes that use TMDS
encoding. 0 = Disable null infoframe packets when Vsync=1 on this port. (Default) 1 =
Enable null infoframe packets when Vsync=1 on this port.
COLOR_RANGE_SELECT: [DevCDV, DevCTG, DevCL] This bit is used to select the
0b color range of RBG outputs in HDMI mode. It is only valid when using TMDS encoding
8
RW and 8 bit per color mode. 0 = Apply full 0-255 color range to the output (Default) 1 =
Apply 16-235 color range to the output

RESERVED_6: [DevCDV]: [DevCTG, DevBW, DevCL, DevBLC] sDVOB Border Enable:

This bit determines if the border data from native VGA or the timing generator is to be
0b considered valid pixel data at the external component. 1 = Border to the sDVOB encoder
7
RW is enabled. Blank# is used to generate the DE output (used in all cases except when the
external scaler is used in a DVI panel, over SDVO) . 0 = Border to the sDVOB encoder is
disabled. DE (Display Enable) is used

AUDIO_OUTPUT_ENABLE: [DevCDV, DevCTG, DevCL] This bit directs audio to this

0b port. When enabled and audio data is available, the audio data will be combined with
6 the video data and sent over this port. The audio unit uses the status of this bit to
RW indicate presence of the HDMI output to the audio driver. 0 = (Default) No audio output
on this port 1 = Enable audio on this port
HDCP_PORT_SELECT: [DevCDV, DevCTG, DevCL] This bit directs HDCP to this port.
0b When enabled, the information sent on this port will be encrypted using HDCP. Please
5 note that this bit does not enable encryption on its own, but must be used in conjunction
RW with HDCP registers. 0 = (Default) No HDCP encryption on this port 1 = Enable HDCP on
this port

Bay Trail-I SoC

538 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

SYNC_POLARITY: Please note that sync polarity does not apply to ANSI coding.
Indicates the polarity of Hsync and Vsync. Inverted polarity is transmitted as SYNC-
BLANK-SYNC and standard polarity is transmitted as BLANK-SYNC-BLANK. For example,
11b if Vsync is not inverted and Hsync is inverted, an Hsync period transmitted during Vsync
4:3 would be transmitted as BLANK+VS+HS BLANK+VS BLANK+VS+HS. Please note that in
RW native VGA modes, these bits have no effect. In native VGA modes, sync polarity is
determined by VRshr3c2d76b[7:6], the VGA polarity bits in VGA control. 00 = VS and
HS are active low (inverted) 01 = VS is active low (inverted), HS is active high 10 = VS
is active high, HS is active low (inverted) 11 = (Default) VS and HS are active high
DIGITAL_PORT_B_DETECTED: Read-only bit indicating whether a digital port B was
0b detected during initialization. It signifies the level of the GMBUS port 4 (sDVO B/C) data
2 line at boot. This bit is valid regardless of whether the port is enabled. 0 = Digital Port B
RO not detected during initialization 1 = Digital Port B detected during initialization
AccessType: Read Only

0b
1:0 RESERVED_7: MBZ
RW

14.11.27 SDVO—Offset 61154h

DP2 - Digital Port DFT Register ;

Access Method
Type: Memory Mapped I/O Register
SDVO: [GTTMMADR_LSB + 2BF20h] + 61154h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PORTC_AUX_LEAKAGE_ENABLE

SCRAMBLER_RESET_ONCE_A_FRAME_ON_TRANSCODE_A
PORTB_AUX_LEAKAGE_ENABLE

SCRAMBLED_0S_ON_TRANSCODE_A
SDVO_DC_BALANCE_RESET

TEST_PATTERN_8_BIT_PROGRAMMED_INPUT_ON_TRANSCODE_A

PRBS7_TEST_PATTERN_ON_TRANSCODE_A
SCRAMBLED_1S_ON_PIPE_A

IDLE_TIME_SPEEDUP_ON_PIPE_A

SCRAMBLED_0S_ON_TRANSCODE_B
SCRAMBLED_1S_ON_PIPE_B

PRBS7_TEST_PATTERN_ON_TRANSCODE_B

SCRAMBLER_RESET_ONCE_A_FRAME_ON_TRANSCODE_B
RESERVED

TEST_PATTERN_8_BIT_PROGRAMMED_INPUT_ON_TRANSCODE_B
IDLE_TIME_SPEEDUP_ON_PIPE_B

Bay Trail-I SoC

Datasheet 539
 Graphics, Video and Display

Bit Default &

Description
Range Access

0b SDVO_DC_BALANCE_RESET: Project: All Format: Value Name Description Project 0b

31 Not Reset DC Balance circuitry will not be reset on every frame All 1b Reset DC Balance
RW circuitry will be reset on every frame All
0b
30:14 RESERVED: Project: All Format: MBZ
RW
0b
13 PORTC_AUX_LEAKAGE_ENABLE: Project: All Format:
RW
0b
12 PORTB_AUX_LEAKAGE_ENABLE: Project: All Format:
RW
0b SCRAMBLED_1S_ON_PIPE_B: Project: All Format: Value Name Description Project
11
RW 0b Disable Disable scrambled 1s All 1b Enable Enable scrambled 1s All

0b SCRAMBLED_1S_ON_PIPE_A: Project: All Format: Value Name Description Project

10
RW 0b Disable Disable scrambled 1s All 1b Enable Enable scrambled 1s All

0b IDLE_TIME_SPEEDUP_ON_PIPE_B: Project: All Format: Value Name Description

9
RW Project 0b Normal Normal idle time All 1b Speedup Speedup idle time All

0b IDLE_TIME_SPEEDUP_ON_PIPE_A: Project: All Format: Value Name Description

8
RW Project 0b Normal Normal idle time All 1b Speedup Speedup idle time All

0b TEST_PATTERN_8_BIT_PROGRAMMED_INPUT_ON_TRANSCODE_B: Project: All

7 Format: Value Name Description Project 0b Disable Disable the test pattern All 1b
RW Enable Enable the test pattern All

0b TEST_PATTERN_8_BIT_PROGRAMMED_INPUT_ON_TRANSCODE_A: Project: All

6 Format: Value Name Description Project 0b Disable Disable the test pattern All 1b
RW Enable Enable the test pattern All
0b SCRAMBLED_0S_ON_TRANSCODE_B: Project: All Format: Value Name Description
5
RW Project 0b Disable Disable the scramble 0s All 1b Enable Enable the scramble 0s All

0b SCRAMBLED_0S_ON_TRANSCODE_A: Project: All Format: Value Name Description

4
RW Project 0b Disable Disable the scramble 0s All 1b Enable Enable the scramble 0s All

0b PRBS7_TEST_PATTERN_ON_TRANSCODE_B: Project: All Format: Value Name

3 Description Project 0b Disable Disable the test pattern All 1b Enable Enable the test
RW pattern All

0b PRBS7_TEST_PATTERN_ON_TRANSCODE_A: Project: All Format: Value Name

2 Description Project 0b Disable Disable the test pattern All 1b Enable Enable the test
RW pattern All

0b SCRAMBLER_RESET_ONCE_A_FRAME_ON_TRANSCODE_B: Project: All Format:

1 Value Name Description Project 0b Disable Disable the scrambler reset once a frame All
RW 1b Enable Enable the scrambler reset once a frame All

0b SCRAMBLER_RESET_ONCE_A_FRAME_ON_TRANSCODE_A: All Format: Value

0 Name Description Project 0b Disable Disable the scrambler reset once a frame All 1b
RW Enable Enable the scrambler reset once a frame All

14.11.28 HDMIC—Offset 61160h

Digital Display Port C Register HDMIC port control (dprrega.v sdvo_cQ)

Access Method
Type: Memory Mapped I/O Register HDMIC: [GTTMMADR_LSB + 2BF20h] + 61160h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Bay Trail-I SoC

540 Datasheet
Graphics, Video and Display

Default: 00000018h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0
SDVO_HDMIC_ENABLE_DIGITAL_DISPLAY_PORT_C_ENABLE

NULL_PACKETS_ENABLED_DURING_VSYNC

DIGITAL_PORT_C_DETECTED
DDI2_PORT_DETECTED
PIPE_SELECT

COLOR_FORMAT
RESERVED

SYMBOL_CLOCK_DUTY_CYCLE

COLOR_RANGE_SELECT
SDVOC_BORDER_ENABLE
AUDIO_OUTPUT_ENABLE
HDCP_PORT_SELECT

SYNC_POLARITY
RESERVED_1

SDVO_HDMIC_CLOCK_OUTPUT_INVERSION_TEST_MODE

ENCODING
RESERVED_2
RESERVED_3
RESERVED_4
RESERVED_5

RESERVED_6
Bit Default &
Description
Range Access

SDVO_HDMIC_ENABLE_DIGITAL_DISPLAY_PORT_C_ENABLE: Disabling this port

will put it in its lowest power state. Port enable takes place on the Vblank after being
written. Both this bit and bit 6 of this register must be enabled to send audio over this
port in HDMI. This port must not be enabled simultaneously with DisplayPort C.
[DevIBX] When disabling the port, software must temporarily enable the port with
0b transcoder select (bit #30) cleared to 0 after disabling the port. This is workaround for
31 hardware issue where the transcoder select set to 1 will prevent DPC from being
RW enabled on transcoder A. [DevIBX] Software must write this bit twice when enabling the
port (setting to 1 ) as a workaround for hardware issue that may result in first write
getting masked. [DevIBX] Toggle this bit off then on at the end of mode set sequence
when enabling HDMI 12-bit per color with pixel repeat. 1 = Enable. This bit enables the
Digital Display Port C interface for HDMI or DVI modes. 0 = Disable and tristates the
Digital Display Port C interface for HDMI or DVI modes.

0b PIPE_SELECT: This bit determines from which display pipe the source data will
30 originate. This only applies to devices with dual display pipes. Pipe selection takes place
RW on the Vblank after being written 0 = Pipe A 1 = Pipe B
RESERVED: [DevCDV]: stall Select: This bit selects stall for external scaling
functionality only on SDVO. Programming notes: It is only valid to have a single stall
indication to a particular pipe. In cases where two ports are being driven from a single
0b pipe, one of the ports must set this bit to 0. Only sDVOB or sDVOC can select the stall
29
RW function, as only a single stall input is available between the two interfaces. Set the stall
input to unused before programming the external device creating the stall. 0 = Stall
input signal is unused on this port 1 = Stall input signal is used to stall the pipe attached
to this port
COLOR_FORMAT: This field selects the number of bits per color sent to a receiver
device connected to this port. Color format takes place on the Vblank after being
0b written. Color format change must be done as a part of mode set since different color
28:26 depths require different pixel clock settings. Selecting a pixel color depth higher or lower
RW than the pixel color depth of the frame buffer results in dithering the output stream. 000
= 8 bits per color (Default) 001 = RESERVED for 10 bits per color 010 = RESERVED for
6 bits per color 011 = RESERVED 1xx = RESERVED

Bay Trail-I SoC

Datasheet 541
 Graphics, Video and Display

Bit Default &

Description
Range Access

0b
25:19 RESERVED_1: Reserved.
RW

0b SDVO_HDMIC_CLOCK_OUTPUT_INVERSION_TEST_MODE: Please note that this

18 applies to all modes and is instantly updated. 1 = sDVO/HDMIB Clock output is inverted
RW 0 = sDVO/HDMIB Clock output is NOT inverted (DEFAULT)
SYMBOL_CLOCK_DUTY_CYCLE: These bits control the output clock duty cycle to
enable EMI mitigation on the external HDMI link. 10/90 cycle has been measured to
0b have ~13dB EMI improvement over a 50/50 duty cycle. 00 = (Default) 50/50 duty
17:16 cycle: Clock output is 0000011111 01 = 10/90 duty cycle: Clock output is 0111111111
RW followed by 0000000001 ([DevCL, DevCTG, DevCDV] HDMI only) 10 = 20/80 duty
cycle: Clock output is 0011111111 followed by 0000000011 ([DevCL, DevCTG,
DevCDV] HDMI only) 11 = Reserved
RESERVED_2: [DevCTG, DevCDV, DevVLVP] Port Lane Reversal: This bit reverses the
0b order of the 4 lanes within the port. Port lane reversal takes place on the Vblank after
15
RW being written. It is an OEM configurable feature. 0 = (Default) Not reversed 1 =
Reversed

0b
14 RESERVED_3: Reserved.
RW

0b RESERVED_4: [DevCTG, DevCDV, DevVLVP] Clock Output Disable: This bit disables the
13 clock output on the digital output port. For 8b/10b modes the clock output should be
RW disabled. 0 = (Default) Clock output enabled 1 = Clock output disabled ([DevCL] only)

RESERVED_5: [DevCTG, DevCDV, DevVLVP]: Scrambling enable: This bit enables

0b scrambling for UDI-related modes using ANSI 8b/10b or TMDS encoding. It is not used
12 with SDVO encoding. Software must set this bit appropriately when enabling the port.
RW Scrambling is reset at the beginning of horizontal sync. 0 Scrambling disabled (Default)
1 = Scrambling enabled ([DevCL] only)
ENCODING: These bits select among encoding types. It is set as part of the display
detection process. Control codes for ANSI 8b/10b and TMDS encoding must be
programmed using these bits. Please note that ANSI 8b/10b and TMDS encoding can
0b only be enabled on one port at a time, as only one HPD pin is available for use between
11:10 ports B and C. 00 = Reserved 01 = Reserved 10 = TMDS encoding ([DevCL, DevCTG,
RW DevCDV, DevVLVP] external link and HDMI only) See the HDMI specification for control
codes. In this mode, the external HPD pin is used to generate hotplug. In fixed
frequency mode, start of fill and end of fill values for TMDS must be programmed using
register 6114C. 11 = Reserved
NULL_PACKETS_ENABLED_DURING_VSYNC: This bit enables a null packet (32
bytes of a value of 0) to be sent when Vsync=1 on this port, required for HDMI
0b operation. It also enables preambles and guardbands prior to the null packets, in
9
RW accordance with the HDMI specification. It is only valid for modes that use TMDS
encoding. 0 = Disable null infoframe packets when Vsync=1 on this port. (Default) 1 =
Enable null infoframe packets when Vsync=1 on this port.

COLOR_RANGE_SELECT: This bit is used to select the color range of RBG outputs in
0b HDMI mode. It is only valid when using TMDS encoding and 8 bit per color mode. 0 =
8
RW Apply full 0-255 color range to the output (Default) 1 = Apply 16-235 color range to the
output ([DevCL and DevCTG] only)
SDVOC_BORDER_ENABLE: This bit determines if the border data from native VGA or
0b the timing generator is to be considered valid pixel data at the external component. 1 =
7 Border to the sDVOC encoder is enabled. Blank# is used to generate the DE output
RW (used in all cases except when the external scaler is used in a DVI panel, over SDVO) .
0 = Border to the sDVOC encoder is disabled. DE (Display Enable) is used

AUDIO_OUTPUT_ENABLE: ([DevCL, DevCTG, DevCDV]): This bit directs audio to this

0b port. When enabled and audio data is available, the audio data will be combined with
6 the video data and sent over this port. The audio unit uses the status of this bit to
RW indicate presence of the HDMI output to the audio driver. 0 = (Default) No audio output
on this port 1 = Enable audio on this port ([DevCL, DevCTG, DevCDV] only)

Bay Trail-I SoC

542 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

HDCP_PORT_SELECT: This bit directs HDCP to this port. When enabled, the
0b information sent on this port will be encrypted using HDCP. Please note that this bit does
5 not enable encryption on its own, but must be used in conjunction with HDCP registers.
RW 0 = (Default) No HDCP encryption on this port 1 = Enable HDCP on this port ([DevCL,
DevCTG, DevCDV] only)

SYNC_POLARITY: Please note that sync polarity does not apply to ANSI coding.
Indicates the polarity of Hsync and Vsync. Inverted polarity is transmitted as SYNC-
BLANK-SYNC and standard polarity is transmitted as BLANK-SYNC-BLANK. For example,
11b if Vsync is not inverted and Hsync is inverted, an Hsync period transmitted during Vsync
4:3 would be transmitted as BLANK+VS+HS BLANK+VS BLANK+VS+HS. Please note that in
RW native VGA modes, these bits have no effect. In native VGA modes, sync polarity is
determined by VRshr3c2d76b[7:6], the VGA polarity bits in VGA control. 00 = VS and
HS are active low (inverted) 01 = VS is active low (inverted), HS is active high 10 = VS
is active high, HS is active low (inverted) 11 = (Default) VS and HS are active high

DIGITAL_PORT_C_DETECTED: Read-only bit indicating whether a digital port C was

0b detected during initialization. It signifies the level of the GMBUS port 3 (port C) data line
2 at boot. This bit is valid regardless of whether the port is enabled. 0 = Digital Port C not
RO detected during initialization 1 = Digital Port C detected during initialization (default)
AccessType: Read Only
DDI2_PORT_DETECTED: Read-only bit indicating whether the DDI2 port was detected
0b during initialization. It signifies the level of the GMBUS port 1 data line at boot. This bit
1 is valid regardless of whether the port is enabled. 0 = DDI2 Port not detected during
RO initialization 1 = DDI2 Port detected during initialization (default) AccessType: Read
Only
0b
0 RESERVED_6: MBZ
RW

14.11.29 DISPLAY_DIGITAL_PORT_HOT_PLUG_CONTROL_REGISTER—
Offset 61164h
display digital poty hot plug control register

Access Method
Type: Memory Mapped I/O Register DISPLAY_DIGITAL_PORT_HOT_PLUG_CONTROL_REGISTER
(Size: 32 bits) : [GTTMMADR_LSB + 2BF20h] + 61164h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

Datasheet 543
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DIGITAL_PORT_B_HOT_PLUG_INTERRUPT_DETECT_STATUS
DIGITAL_PORT_D_HOT_PLUG_INTERRUPT_DETECT_STATUS

DIGITAL_PORT_C_HOT_PLUG_INTERRUPT_DETECT_STATUS
RESERVED

DIGITAL_PORT_D_HOT_PLUG_DETECT_INPUT_ENABLE

DIGITAL_PORT_C_HOT_PLUG_DETECT_INPUT_ENABLE

DIGITAL_PORT_B_HOT_PLUG_DETECT_INPUT_ENABLE
DIGITAL_PORT_D_HOT_PLUG_SHORT_PULSE_DURATION

RESERVED_1

DIGITAL_PORT_C_HOT_PLUG_SHORT_PULSE_DURATION

RESERVED_2

DIGITAL_PORT_B_HOT_PLUG_SHORT_PULSE_DURATION
Bit Default &
Description
Range Access

0b
31:21 RESERVED: Project: All Format:
RW

DIGITAL_PORT_D_HOT_PLUG_DETECT_INPUT_ENABLE: Project: All Default

Value: 0b
Controls the state of the HPD buffer for the digital port. The buffer state is independent
of whether the port is enabled or not.
0b
20
RW
• Value / Name / Description / Project
• 0 / Disable / Buffer disabled /All
• 1 / Enable / Buffer enabled. Hot plugs bit reflect the electrical state of the HPD pin /
All
DIGITAL_PORT_D_HOT_PLUG_SHORT_PULSE_DURATION: Project: All Default
Value: 0b
These bits define the duration of the pulse defined as a short pulse.
0b
19:18 • Value / Name / Description / Project
RW • 00 / 2ms / 2ms / All
• 01 / 4.5ms / 4.5ms / All
• 10 / 6ms / 6ms / All
• 11 / 100ms / 100ms / All
DIGITAL_PORT_D_HOT_PLUG_INTERRUPT_DETECT_STATUS: Project: All
Default Value: 0b AccessType: One to Clear
This reflects hot plug detect status on the digital port. Graphics software must write a
one to these bits to clear the status. This bit is used for either monitor hotplug/unplug or
for notification of a sink event. When either a long or short pulse is detected, one of
0b these bits will set. These bits are ORed together to go to the main ISR hotplug register
17:16 bit.
RW/1C

• Value / Name / Description / Project

• 00 / No Detect / Digital port hot plug event not detected / All
• X1 / Short Detect / Digital port short pulse hot plug event detected / All
• 1X / Long Detect / Digital port long pulse hot plug event detected / All

Bay Trail-I SoC

544 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

0b
15:13 RESERVED_1: Project: All Format:
RW
DIGITAL_PORT_C_HOT_PLUG_DETECT_INPUT_ENABLE: Project: All Default
Value: 0b
Controls the state of the HPD buffer for the digital port. The buffer state is independent
of whether the port is enabled or not.
0b
12
RW
• Value / Name / Description / Project
• 0 / Disable / Buffer disabled / All
• 1 / Enable / Buffer enabled. Hot plugs bit reflect the electrical state of the HPD pin /
All
DIGITAL_PORT_C_HOT_PLUG_SHORT_PULSE_DURATION: Project: All Default
Value: 0b
These bits define the duration of the pulse defined as a short pulse.
0b
11:10
RW • Value / Name / Description / Project
• 00 / 2ms / 2ms / All
• 01 / 4.5ms / 4.5mS / All
• 10 / 6ms / 6mS / All
• 11 / 100ms / 100mS / All

DIGITAL_PORT_C_HOT_PLUG_INTERRUPT_DETECT_STATUS: Project: All Default

Value: 0b AccessType: One to Clear
This reflects hot plug detect status on the digital port. Graphics software must write a
one to these bits to clear the status. This bit is used for either monitor hotplug/unplug or
for notification of a sink event. When either a long or short pulse is detected, one of
0b these bits will set. These bits are ORed together to go to the main ISR hotplug register
9:8 bit.
RW/1C

• Value / Name / Description / Project

• 00 / No Detect / Digital port hot plug event not detected / All
• X1 / Short Detect / Digital port short pulse hot plug event detected / All
• 1X / Long Detect / Digital port long pulse hot plug event detected / All
0b
7:5 RESERVED_2: Project: All Format:
RW
DIGITAL_PORT_B_HOT_PLUG_DETECT_INPUT_ENABLE: Project: All Default
Value: 0b
Controls the state of the HPD buffer for the digital port. The buffer state is independent
of whether the port is enabled or not.
0b
4
RW
• Value / Name / Description / Project
• 0 / Disable / Buffer disabled / All
• 1 / Enable / Buffer enabled. Hot plugs bit reflect the electrical state of the HPD pin /
All

DIGITAL_PORT_B_HOT_PLUG_SHORT_PULSE_DURATION: Project: All Default

Value: 0b
These bits define the duration of the pulse defined as a short pulse.
0b
3:2
RW • Value / Name / Description / Project
• 00 / 2ms / 2ms / All
• 01 / 4.5ms / 4.5ms / All
• 10 / 6ms / 6ms / All
• 11 / 100ms / 100ms / All

Bay Trail-I SoC

Datasheet 545
 Graphics, Video and Display

Bit Default &

Description
Range Access

DIGITAL_PORT_B_HOT_PLUG_INTERRUPT_DETECT_STATUS: Project: All Default

Value: 0b AccessType: One to Clear
This reflects hot plug detect status on the digital port. Graphics software must write a
one to these bits to clear the status. This bit is used for either monitor hotplug/unplug or
for notification of a sink event. When either a long or short pulse is detected, one of
0b these bits will set. These bits are ORed together to go to the main ISR hotplug register
1:0 bit.
RW/1C

• Value / Name / Description / Project

• 00 / No Detect / Digital port hot plug event not detected / All
• X1 / Short Detect / Digital port short pulse hot plug event detected / All
• 1X / Long Detect / Digital port long pulse hot plug event detected / All

14.11.30 DV_DETERM—Offset 61168h

DV Determinism Mode Register

Access Method
Type: Memory Mapped I/O Register DV_DETERM: [GTTMMADR_LSB + 2BF20h] + 61168h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CRT_LVDS_PIPE_ENABLE_OVERRIDE_FOR_DISPLAY_PIPE_B
DISPLAYPORT_D_PORT_ENABLE_OVERRIDE

DP_SDVO_HDMI_PIPE_ENABLE_OVERRIDE_FOR_DISPLAY_PIPE_B
DISPLAYPORT_C_PORT_ENABLE_OVERRIDE
DISPLAYPORT_B_PORT_ENABLE_OVERRIDE

DP_SDVO_HDMI_PIPE_ENABLE_OVERRIDE_FOR_DISPLAY_PIPE_A

CRT_LVDS_PIPE_ENABLE_OVERRIDE_FOR_DISPLAY_PIPE_A
RESERVED

Bay Trail-I SoC

546 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

0b
31:7 RESERVED: Project: All Format:
RW
DISPLAYPORT_D_PORT_ENABLE_OVERRIDE: Project: All Default Value: 0b
0b • Value / Name / Description / Project
6 • 0b / Normal / Normal operation / All
RW
• 1b / Override / DisplayPort D port enable override (controlled from
sml0alertb_gp60_mgpio4 pin) / All

0b DISPLAYPORT_C_PORT_ENABLE_OVERRIDE: Project: All Default Value: 0b Value

5 Name Description Project 0b Normal Normal operation All 1b Override DisplayPort C port
RW enable override (controlled from sus_statb_gp61 pin) All

0b DISPLAYPORT_B_PORT_ENABLE_OVERRIDE: Project: All Default Value: 0b Value

4 Name Description Project 0b Normal Normal operation All 1b Override DisplayPort B port
RW enable override (controlled from gp57_mgpio5 pin) All

DP_SDVO_HDMI_PIPE_ENABLE_OVERRIDE_FOR_DISPLAY_PIPE_B: Project: All

0b Default Value: 0b Value Name Description Project 0b Normal Normal operation All 1b
3
RW Override DP/SDVO/HDMI pipe enable override for display pipe B (controlled from
gp74_batlowb pin) All
DP_SDVO_HDMI_PIPE_ENABLE_OVERRIDE_FOR_DISPLAY_PIPE_A: Project: All
0b Default Value: 0b Value Name Description Project 0b Normal Normal operation All 1b
2
RW Override DP/SDVO/HDMI pipe enable override for display pipe A (controlled from
slp_s4b pin) All
CRT_LVDS_PIPE_ENABLE_OVERRIDE_FOR_DISPLAY_PIPE_B: Project: All
0b Default Value: 0b Value Name Description Project 0b Normal Normal operation All 1b
1
RW Override CRT/LVDS pipe enable override for display pipe B (controlled from susclk_gp62
pin) All

CRT_LVDS_PIPE_ENABLE_OVERRIDE_FOR_DISPLAY_PIPE_A: Project: All

0b Default Value: 0b Value Name Description Project 0b Normal Normal operation All 1b
0
RW Override CRT/LVDS pipe enable override for display pipe A (controlled from slp_mb pin)
All

14.11.31 VIDEO_DIP_CTL_B—Offset 61170h

Video DIP Control for Pipe B

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) VIDEO_DIP_CTL_B: [GTTMMADR_LSB + 2BF20h] + 61170h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 20200900h

Bay Trail-I SoC

Datasheet 547
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0

DATA_ISLAND_PACKET_TYPE_ENABLE
GCP_DIP_ENABLE

VIDEO_DIP_TRANSMISSION_FREQUENCY
DIP_BUFFER_INDEX

VIDEO_DIP_BUFFER_SIZE

VIDEO_DIP_RAM_ACCESS_ADDRESS
ENABLE_GRAPHICS_DATA_ISLAND_PACKET

PORT_SELECT

RESERVED

RESERVED_1

RESERVED_2

RESERVED_3
Bit Default &
Description
Range Access

0b
31 ENABLE_GRAPHICS_DATA_ISLAND_PACKET: Project: All See Pipe A description.
RW
01b
30:29 PORT_SELECT: Project: All See Pipe A description.
RW
0b
28:26 RESERVED: Project: All Format:
RW
0b GCP_DIP_ENABLE: Project: All See Pipe A description. This bit should not be enabled
25
RW for 8bpc mode if at least one of the other HDMI ports is enabled in 12bpc mode.

0001b
24:21 DATA_ISLAND_PACKET_TYPE_ENABLE: Project: All See Pipe A description.
RW
0b
20:19 DIP_BUFFER_INDEX: Project: All See Pipe A description.
RW
0b
18 RESERVED_1: Project: All Format:
RW
0b
17:16 VIDEO_DIP_TRANSMISSION_FREQUENCY: Project: All See Pipe A description.
RW
0b
15:12 RESERVED_2: Project: All Format: MBZ
RW
1001b VIDEO_DIP_BUFFER_SIZE: Project: All AccessType: Read Only Default Value: ;1001b
11:8
RO See Pipe A description.

0b
7:4 RESERVED_3: Project: All Format: MBZ
RW
0b VIDEO_DIP_RAM_ACCESS_ADDRESS: Project: All AccessType: Read only See Pipe A
3:0
RO description.

14.11.32 VIDEO_DIP_DATA_B—Offset 61174h

Video Data Island Packet Data for Pipe B

Access Method

Bay Trail-I SoC

548 Datasheet
Graphics, Video and Display

Type: Memory Mapped I/O Register

VIDEO_DIP_DATA_B: [GTTMMADR_LSB + 2BF20h] + 61174h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

VIDEO_DIP_DATA
Bit Default &
Description
Range Access

0b
31:0 VIDEO_DIP_DATA: Project: All Format: See Pipe A description.
RW

14.11.33 VIDEO_DIP_GDCP_PAYLOAD_B—Offset 61178h

Video Data Island Payload for Pipe B

Access Method
Type: Memory Mapped I/O Register VIDEO_DIP_GDCP_PAYLOAD_B: [GTTMMADR_LSB + 2BF20h]
(Size: 32 bits) + 61178h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GCP_AV_MUTE
RESERVED

GCP_DEFAULT_PHASE_ENABLE
GCP_COLOR_INDICATION

Bit Default &

Description
Range Access

0b
31:3 RESERVED: Project: All Format: MBZ
RW

Bay Trail-I SoC

Datasheet 549
 Graphics, Video and Display

Bit Default &

Description
Range Access

0b
2 GCP_COLOR_INDICATION: Project: All See Pipe A description.
RW
0b
1 GCP_DEFAULT_PHASE_ENABLE: Project: All See Pipe A description.
RW
0b
0 GCP_AV_MUTE: All See Pipe A description.
RW

14.11.34 MIPIA_PORT_CTRL—Offset 61190h

mipi A port ctrl

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) MIPIA_PORT_CTRL: [GTTMMADR_LSB + 2BF20h] + 61190h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

550 Datasheet
Datasheet
Bay Trail-I SoC
0
31

EN
0
0

ADJDLY_HSTX
0
28

0
Graphics, Video and Display

MIPI_DUAL_LINK_MODE_APPLICABLE_ONLY_IF_MIPI_DUAL_LINK_MODE_IS_ENABLED_THROUGH_MIPI_LANES_CONFIGURATION_BITS
0

DITHER
0
24

RESERVED
0

SELFLOPPED_HSTX
0

RESERVED_1
0
0
20

FLISDSI_ADJDLY_HSTX_MIPIA
0
0
0

AFE_LATCHOUT
0
16

LPOUTPUT_HOLD
0

FLISDSI_ADJDLYY_HSTX_MIPIC_HIGH_ORDER
0
0

MIPI4DPHY_AdjDly_HSTX_MIPI_C
0
12

0
0

CSB
0
8

CB
0
0

FLISDSI_AdjDly_HSTX_MIPI_C_LOWER_ORDER
0
4

DELAY
0

EFFECT
0
0

MIPI_LANES_CONFIGURATION
0

551
 Graphics, Video and Display

Bit Default &

Description
Range Access

EN: When this bit is disabled the MIPI DPI (video mode) is inactive and in it's low power
0b state. When it is enable it starts to generate timing for this MIPI port 0 = The port is
31
RW disabled and all MIPI DPI interface are disable (timing generator is off) 1 = The port is
enabled

ADJDLY_HSTX: These four bits act as an encoded count of the number of buffer delays
0b to insert on the ckdsi2x clock going to the six flops that are storing the HS TX data and
30:27 clock signals. Default is 4'b0000 which is the equivalent of 1 buffer delay. Will need to
RW set these bits to a value determined by clock timing team before using the MIPI DSI HS
TX feature

0b MIPI_DUAL_LINK_MODE_APPLICABLE_ONLY_IF_MIPI_DUAL_LINK_MODE_IS
26 _ENABLED_THROUGH_MIPI_LANES_CONFIGURATION_BITS: 0 = Front-Back
RW mode (default) 1 = Pixel alternative mode

0b DITHER: This bit enables or disables (bypassing) 8-6-bit color dithering function. The
25 usage of this bit would be on for 18-bpp panels and off for 24-bpp panels. 0 = disabled
RW 1 = enabled
0b
24 RESERVED: Reserved.
RW
SELFLOPPED_HSTX: This bit will be used to mux between the flopped (new) and
0b unflopped (original) versions of the TX HS clock and data. Default 0 = pass through
23 original unflopped version, if set to 1 = pass through the new flopped version of these
RW signals. We probably need to enable validation to always set these to 1 during startup so
we're fully testing this logic as it is the intended way we will run A0
0b
22 RESERVED_1: Reserved.
RW
FLISDSI_ADJDLY_HSTX_MIPIA: These four bits act as an encoded count of the
0b number of buffer delays to insert on the ckdsi2x clock going to the six flops that are
21:18 storing the HS TX data and clock signals. Default is 4'b0000 which is the equivalent of 1
RW buffer delay. Will need to set these bits to a value determined by clock timing team
before using the MIPI DSI HS TX feature

AFE_LATCHOUT: This bit reflect the value of the output latch of CLK A lane in DSI AFE
0b b1 = current value of output latch is 1 (D-PHY is in LP11 state) b0 = current value of
17
RW output latch is 0 (D-PHY is in LP00 state) The software driver can read this bit to see if
the hold value (LP11 or LP00) to initialize from a sleep state (s0i1 or S0i3) correctly
0b LPOUTPUT_HOLD: 0= disable transparent latche inside DSI AFE. Output are driven by
16
RW latch value. 1= enable transparent latch inside DSI AFE so data are driven by DSI DPHY

FLISDSI_ADJDLYY_HSTX_MIPIC_HIGH_ORDER: The fourth bit of four bits act as

0b an encoded count of the number of buffer delays to insert on the ckdsi2x clock going to
15 the six flops that are storing the HS TX data and clock signals. Default is 1'b0 which is
RW the equivalent of 1 buffer delay. Will need to set these bits to a value determined by
clock timing team before using the MIPI DSI HS TX feature
MIPI4DPHY_AdjDly_HSTX_MIPI_C: These four bits act as an encoded count of the
0b number of buffer delays to insert on the ckdsi2x clock going to the six flops that are
14:11 storing the HS TX data and clock signals.[Br] Default is 4'b0000 which is the equivalent
RW of 1 buffer delay. Will need to set these bits to a value determined by clock timing team
before using the MIPI DSI HS TX feature

0b CSB: Clock input for bandgap voltage sample and hold circuit. Final setting will be based
10:9 silicon characterization. 00b = 20mhz clock 01b = 10mhz clock 10b = 40mhz clock 11b
RW = reserved

0b
8 CB: Bandgap chicken bit 0 = using Penwell band gap circuit 1 = back to LNC circuit
RW

FLISDSI_AdjDly_HSTX_MIPI_C_LOWER_ORDER: The lower 3-bit of four bits act

0b as an encoded count of the number of buffer delays to insert on the ckdsi2x clock going
7:5 to the six flops that are storing the HS TX data and clock signals. Default is 3'b000
RW which is the equivalent of 1 buffer delay. Will need to set these bits to a value
determined by clock timing team before using the MIPI DSI HS TX feature

Bay Trail-I SoC

552 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

0b
4 DELAY: When set, the TE counter will be count down until
RW

0b EFFECT: 00: No tearing effect required - memory write start as soon as write data is
3:2 available 01: TE trigger by MIPI DPHY and DSI protocol 10: TE trigger by GPIO pin 11:
RW Reserved
MIPI_LANES_CONFIGURATION: 00: All 4 MIPI A lanes are assigned to pipe A. All 4
0b MIPI C lanes are assigned to pipe B. 01: MIPI dual-link mode with data from pipe A 10:
1:0 MIPI dual-link mode with data from pipe B 11: Reserved Programming note: when MIPI
RW dual-link mode is enabled, the port enable bits in both MIPI A control register and MIPI
C control register shall be enabled.

14.11.35 MIPIA_TEARING_CTR—Offset 61194h

mipi A tearing CTR

Access Method
Type: Memory Mapped I/O Register
MIPIA_TEARING_CTR: [GTTMMADR_LSB + 2BF20h] + 61194h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED

TE

Bit Default &

Description
Range Access

0b
31:16 RESERVED: Reserved.
RW

0b
15:0 TE: Number of delay clocks from TE trigger to start sending data to DSI controller
RW

14.11.36 DPA_PIX_GEN_CTRL—Offset 61198h

Display Pipe A Pixel Generator Control

Access Method
Type: Memory Mapped I/O Register DPA_PIX_GEN_CTRL: [GTTMMADR_LSB + 2BF20h] + 61198h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

Datasheet 553
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BIT_35_32_OF_DISPLAY_PIPE_A_PROGRAMMABLE_PIXEL_DATA_REGISTER_4

BIT_35_32_OF_DISPLAY_PIPE_A_PROGRAMMABLE_PIXEL_DATA_REGISTER_3

BIT_35_32_OF_DISPLAY_PIPE_A_PROGRAMMABLE_PIXEL_DATA_REGISTER_2

BIT_35_32_OF_DISPLAY_PIPE_A_PROGRAMMABLE_PIXEL_DATA_REGISTER_1

RESERVED

MODE_SELECT
PIXEL_GENERATOR_ENABLE
Bit Default &
Description
Range Access

0b BIT_35_32_OF_DISPLAY_PIPE_A_PROGRAMMABLE_PIXEL_DATA_REGISTER_
31:28
RW 4: Project: All Default Value: 0b

0b BIT_35_32_OF_DISPLAY_PIPE_A_PROGRAMMABLE_PIXEL_DATA_REGISTER_
27:24
RW 3: Project: All Default Value: 0b

0b BIT_35_32_OF_DISPLAY_PIPE_A_PROGRAMMABLE_PIXEL_DATA_REGISTER_
23:20
RW 2: Project: All Default Value: 0b

0b BIT_35_32_OF_DISPLAY_PIPE_A_PROGRAMMABLE_PIXEL_DATA_REGISTER_
19:16
RW 1: Project: All Default Value: 0b

0b
15:2 RESERVED: Project: All Format:
RW

0b MODE_SELECT: Project: All Default Value: 0b Pixel generator mode select Value Name
1 Description Project 0b LFSR LFSR All 1b Programmable Programmable pixel data
RW register. Setting mode select to 1 will also start the 2-bit counter. All

0b
0 PIXEL_GENERATOR_ENABLE: All
RW

14.11.37 MIPIA_AUTOPWG—Offset 611A0h

mipi A autopowergating

Access Method

Bay Trail-I SoC

554 Datasheet
Graphics, Video and Display

Type: Memory Mapped I/O Register

MIPIA_AUTOPWG: [GTTMMADR_LSB + 2BF20h] + 611A0h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESERVED
Bit Default &
Description
Range Access

0b
31:0 RESERVED: Reserved.
RW

14.11.38 DPB_PIX_GEN_CTRL—Offset 611B0h

Display Pipe B Pixel Generator Control

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) DPB_PIX_GEN_CTRL: [GTTMMADR_LSB + 2BF20h] + 611B0h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

Datasheet 555
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BIT_35_32_OF_DISPLAY_PIPE_B_PROGRAMMABLE_PIXEL_DATA_REGISTER_4

BIT_35_32_OF_DISPLAY_PIPE_B_PROGRAMMABLE_PIXEL_DATA_REGISTER_3

BIT_35_32_OF_DISPLAY_PIPE_B_PROGRAMMABLE_PIXEL_DATA_REGISTER_2

BIT_35_32_OF_DISPLAY_PIPE_B_PROGRAMMABLE_PIXEL_DATA_REGISTER_1

RESERVED

MODE_SELECT
PIXEL_GENERATOR_ENABLE
Bit Default &
Description
Range Access

0b BIT_35_32_OF_DISPLAY_PIPE_B_PROGRAMMABLE_PIXEL_DATA_REGISTER_
31:28
RW 4: Project: All Default Value: 0b

0b BIT_35_32_OF_DISPLAY_PIPE_B_PROGRAMMABLE_PIXEL_DATA_REGISTER_
27:24
RW 3: Project: All Default Value: 0b Address: GraphicsAddress[35:32]

0b BIT_35_32_OF_DISPLAY_PIPE_B_PROGRAMMABLE_PIXEL_DATA_REGISTER_
23:20
RW 2: Project: All Default Value: 0b

0b BIT_35_32_OF_DISPLAY_PIPE_B_PROGRAMMABLE_PIXEL_DATA_REGISTER_
19:16
RW 1: Project: All Default Value: 0b

0b
15:2 RESERVED: Project: All Format:
RW

0b MODE_SELECT: Project: All Default Value: 0b Pixel generator mode select Value Name
1 Description Project 0b LFSR LFSR All 1b Programmable Programmable pixel data
RW register. Setting mode select to 1 will also start the 2-bit counter. All

0b
0 PIXEL_GENERATOR_ENABLE: All Format: Enable
RW

14.11.39 PIPEA_PP_STATUS—Offset 61200h

PipeA Panel Power Status Register ([DevCL, DevCTG, DevCDV]) PP Status (dplrreg.v
panel_pwr_sr)

Bay Trail-I SoC

556 Datasheet
Graphics, Video and Display

Access Method
Type: Memory Mapped I/O Register
PIPEA_PP_STATUS: [GTTMMADR_LSB + 2BF20h] + 61200h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 08000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

INTERNAL_SEQUENCE_STATE_FOR_TEST_DEBUG
PANEL_POWER_ON_STATUS
REQUIRE_ASSET_STATUS

POWER_SEQUENCE_PROGRESS

POWER_CYCLE_DELAY_ACTIVE

RESERVED

Bit Default &

Description
Range Access

PANEL_POWER_ON_STATUS: 0 = Indicates that the panel power down sequencing

has completed. A power cycle delay may be currently active. It is safe and allowed to
program pipe timing and DPLL registers. If this bit is not a zero, it activates the register
write protect and writes to those registers will be ignored unless the write protect key
value is set in the panel sequencing control register. 1 = In conjunction with bits Power
0b Sequence Progress field and Power Cycle Delay Active, this bit set to a one indicates
31 that the panel is currently powered up or is currently in the power down sequence and it
RO is unsafe to change the pipe timing and DPLL registers for the pipe that is assigned to
the embedded panel output. If the embedded panel port is selected as the target for the
panel control, Software is responsible for enabling the LCD display by writing a 1 to the
port enable bit only after all pipe timing, DPLL registers are properly programmed, and
the PLL has locked to the reference signal. This bit is cleared (set to 0) only after the
panel power down sequencing is completed.

REQUIRE_ASSET_STATUS: This bit indicates the status of programming of the display

PLL and the selected display port. This a power on cycle will not be allowed unless this
status indicates that the required assets are programmed and ready for use. 0 = All
0b required assets are not properly programmed. 1 = All required assets are ready for the
30 driving of a panel. The following conditions determine that the assets are ready: 1)
RO Display Pipe PLL Enabled and frequency locked (bit-31 of DPLL Control Register for the
pipe attached to the embedded panel port). 2) Display Pipe Enabled (bit-31 of PIPECONF
Pipe Configuration Register. For the pipe attached to the embedded panel port) 3)
Embedded Panel Port is Programmed Enabled

0b POWER_SEQUENCE_PROGRESS: 00 = Indicates that the panel is not in a power

29:28 sequence 01 = Indicates that the panel is in a power up sequence (may include power
RO cycle delay) 10 = Indicates that the panel is in a power down sequence 11 = Reserved

POWER_CYCLE_DELAY_ACTIVE: Power cycle delays occur after a panel power down

1b sequence or after a hardware reset. On reset, a power cycle delay will occur using the
27
RO default value for the timing. 0 = A power cycle delay is not currently active 1 = A power
cycle delay (T4) is currently active

Bay Trail-I SoC

Datasheet 557
 Graphics, Video and Display

Bit Default &

Description
Range Access

0b
26:4 RESERVED: Reserved.
RO
INTERNAL_SEQUENCE_STATE_FOR_TEST_DEBUG: 0000 = Power Off Idle (S0.0)
0001 = Power Off, Wait for cycle delay (S0.1) 0010 = Power Off (S0.2) 0011 = Power
0b Off (S0.3) 0100 = Reserved 0101 = Reserved 0110 = Reserved 0111 = Reserved 1000
3:0
RO = Power On Idle (S1.0) 1001 = Power On, (S1.1) 1010 = Power On, (S1.2) 1011 =
Power On, Wait for cycle delay (S1.3) 1100 = Reserved 1101 = Reserved 1110 =
Reserved 1111 = Reset

14.11.40 PIPEA_PP_CONTROL—Offset 61204h

PipeA Panel Power Control Register ([DevCL, DevCTG, DevCDV]) PP Control (dplrreg.v
pnl_pwr_cntl)

Access Method
Type: Memory Mapped I/O Register
PIPEA_PP_CONTROL: [GTTMMADR_LSB + 2BF20h] + 61204h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

POWER_STATE_TARGET
RESERVED

EDP_PANEL_VDD_ENABLE

POWER_DOWN_ON_RESET
BACKLIGHT_ENABLE
WRITE_PROTECT_KEY

Bit Default &

Description
Range Access

WRITE_PROTECT_KEY: ABCD Write protect off When this field is programmed to

anything except the write protect off setting and the panel is either powered up or in the
process of a power up sequence, a set of registers involved in generation of panel timing
or control become write protected. Any write cycles to those write protected registers,
while they will complete as normal, will not change the value of the register when write
protected. When this register field contains the write protect off key value, write protect
will be unconditionally disabled. In situations where the embedded panel port is unused,
the port should remain powered down and the write protect will be inactive. This field in
0b normal operation should be left to all zeros and never programmed with the key value.
31:16 It exists only to allow testing and workarounds. List of Write protected registers: (LVDS
RW and Panel sequencing Registers): LVDS Digital Display Port Control Address: 61180h
61183h Pipe A Panel power on sequencing delays - Address: 61208-6120Bh Pipe A
Panel power off sequencing delays Address: 6120Ch 6120Fh Pipe A Panel power cycle
delay and Reference Divisor Address: 61210h 61213 (DPLL registers): DPLL Control
Registers FPA0 DPLL Divisor Register FPA1 DPLL Divisor Register 1 FPB0 DPLL Divisor
Register FPB1 DPLL Divisor Register 1 (Display Pipe timing registers except source size)
HTOTAL Horizontal Total Register HBLANK Horizontal Blank Register HSYNC_ Horizontal
Sync Register VTOTAL_ Vertical Total Register VBLANK_ Vertical Blank Register VSYNC_
Vertical Sync Register

Bay Trail-I SoC

558 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

0b
15:4 RESERVED: Reserved.
RW
EDP_PANEL_VDD_ENABLE: [DevCDV]: Enabling this bit enables the panel vdd if the
0b embedded panel is DisplayPort, as indicated in bits 31:30 of the panel power on
3 sequencing. Software must enable this bit for eDP link training. After eDP link training is
RW done, software must disable it and let the normal panel power sequencing to take
control. 0 = eDP panel Vdd disabled 1 = eDP panel Vdd enabled [DevCLN] Reserved

BACKLIGHT_ENABLE: [DevCTG, DevCDV]: Enabling this bit enables the panel

0b backlight if the embedded panel is DisplayPort, as indicated in bits 31:30 of the panel
2 power on sequencing. Software must enable this bit after training the link, and disable it
RW when disabling the panel power state target. 0 = Backlight disabled 1 = Backlight
enabled [DevCL] Reserved
POWER_DOWN_ON_RESET: Enabling this bit causes the panel to power down when a
reset warning comes to the GMCH from the ICH. When system reset is initiated, the
0b embedded panel port automatically begins the panel power down sequence. If the panel
1
RW is not on during a reset event, this bit is ignored. 0 = Do not run panel power down
sequence when reset is detected 1 = Run panel power down sequence when system is
reset
POWER_STATE_TARGET: Writing this bit can occur any time, it will only be used at
the completion of any current power cycle. 0 = The panel power state target is off, if the
panel is either on or in a power on sequence, a power off sequence is started as soon as
the panel reaches the power on state. This may include a power cycle delay. If the panel
0b is currently off, there is no change of the power state or sequencing done. 1= The panel
0
RW power state target is on, if the panel is in either the off state or a power off sequence, if
all pre-conditions are met, a power on sequence is started as soon as the panel reaches
the power off state. This may include a power cycle delay. If the panel is currently off,
there is no change of the power state or sequencing done. While the panel is on or in a
power on sequence, the register write lock will be enabled.

14.11.41 PIPEA_PP_ON_DELAYS—Offset 61208h

PipeA Panel Power on Sequencing Delays ([DevCL, DevCTG, DevCDV]) PP On Delay
values (dplrreg.v DPLRppon_sd)

Access Method
Type: Memory Mapped I/O Register PIPEA_PP_ON_DELAYS: [GTTMMADR_LSB + 2BF20h] +
(Size: 32 bits) 61208h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

Datasheet 559
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

POWER_ON_TO_BACKLIGHT_ENABLE_DELAY
PANEL_CONTROL_PORT_SELECT

RESERVED

POWER_UP_DELAY

RESERVED_1
Bit Default &
Description
Range Access

PANEL_CONTROL_PORT_SELECT: These bits define to which port the embedded

panel is connected. This is used for automatic control of the panel power. If the selected
0b port is disabled or if the port is not on pipe-B, then, the power sequence will not allow a
31:30 panel power up. 00 = Reserved 01 = Panel is connected to the embedded DisplayPort B
RW 10 = Panel is connected to the embedded DisplayPort C 11 = Reserved The selection of
non-existent ports are not allowed. This programming will disable panel power
sequencing logic.
0b
29 RESERVED: Reserved.
RW

0b POWER_UP_DELAY: Programmable value of panel power sequencing delay during

28:16 panel power up. This provides the time delay for the T1+T2 time sequence. The time
RW unit used is the 100us timer.
0b
15:13 RESERVED_1: Reserved.
RW

0b POWER_ON_TO_BACKLIGHT_ENABLE_DELAY: Programmable value of panel power

12:0 sequencing delay during panel power up. This provides the time delay for the T5 (T3 for
RW DisplayPort) time sequence. The time unit used is the 100us timer.

14.11.42 PIPEA_PP_OFF_DELAYS—Offset 6120Ch

PipeA Panel Power off Sequencing Delays ([DevCL, DevCTG, DevCDV]) PP Delay Off
values (dplrreg.v DPLRppoff_sd)

Access Method
Type: Memory Mapped I/O Register PIPEA_PP_OFF_DELAYS: [GTTMMADR_LSB + 2BF20h] +
(Size: 32 bits) 6120Ch

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

560 Datasheet
Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

POWER_BACKLIGHT_OFF_TO_POWER_DOWN_DELAY
RESERVED

POWER_DOWN_DELAY

RESERVED_1
Bit Default &
Description
Range Access

0b
31:29 RESERVED: Reserved.
RW

0b POWER_DOWN_DELAY: Programmable value of panel power sequencing delay during

28:16 power up. This provides the time delay for the T3 (T5 for DisplayPort) time sequence.
RW The time unit used is the 100us timer.
0b
15:13 RESERVED_1: Reserved.
RW

0b POWER_BACKLIGHT_OFF_TO_POWER_DOWN_DELAY: Programmable value of

12:0 panel power sequencing delay during power down. This provides the time delay for the
RW Tx (T4 for DisplayPort) time sequence. The time unit used is the 100us timer.

14.11.43 PIPEA_PP_DIVISOR—Offset 61210h

PipeA Panel Power Cycle Delay and Reference Divisor ([DevCL, DevCTG, DevCDV]) PP
Divisor (dplrreg.v DPLRrefdiv_pp_cd)

Access Method
Type: Memory Mapped I/O Register
PIPEA_PP_DIVISOR: [GTTMMADR_LSB + 2BF20h] + 61210h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00270F04h

Bay Trail-I SoC

Datasheet 561
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 0 0

REFERENCE_DIVIDER

RESERVED

POWER_CYCLE_DELAY
Bit Default &
Description
Range Access

REFERENCE_DIVIDER: This field provides the value of the divider used for the
creation of the panel timer reference clock. The output of the divider is used as the
000000000 fastest of the three time bases (100us) for all other timers. The other time bases are
010011100 divided from this frequency. The value of zero should not be used. When it is desired to
31:8 001111b divide by N, the actual value to be programmed is (N/2)-1. The value should be
(100*RefinMHz/2)-1. The default value assumes the default value for the display core
RW clock that is for [DevCL and DevCTG] a 200MHz reference value. The following are
examples for other memory speeds. Display Core Frequency Value of Field 233MHz
2D81h 200MHz 270Fh 133MHz 19F9h
0b
7:5 RESERVED: Reserved.
RW
POWER_CYCLE_DELAY: Programmable value of time panel must remain in a powered
down state after powering down. For devices coming out of reset, the default values will
define how much time must pass before a power on sequence can be started. This field
uses the .1 S time base unit from the divider. If the panel power on sequence is
attempted during this delay, the power on sequence will commence once the power
00100b cycle delay is complete. Writing a value of 0 selects no delay or is used to abort the
4:0 delay if it is active. During the initial power up reset, a D3 cold power cycle, or a user
RW instigated system reset, the timer will be set to the default value and the count down
will begin after the de-assertion of reset. Writing this field to a zero while the count is
active will abort this portion of the sequence. This corresponds to the T4 of the SPWG
specification. Note: Even if the panel is not enabled, the T4 count happens after reset.
This register needs to be programmed to a +1 value. For instance for meeting the SPWG
specification of 400mS, program 5 to achieve at least 400mS delay prior to powerup.

14.11.44 PFIT_CONTROL—Offset 61230h

Panel Fitting Controls

Access Method
Type: Memory Mapped I/O Register
PFIT_CONTROL: [GTTMMADR_LSB + 2BF20h] + 61230h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 20000000h

Bay Trail-I SoC

562 Datasheet
Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DEBUG_FORCE_THREE_PIXEL_MODE_WHEN_IN_TWO_LINE_MODE
SCALING_MODE

FILTER_COEFFICIENT_SELECT
PANEL_FITTING_ENABLED

PIPE_SELECT

DEBUG_FORCE_TWO_LINE_MODE

DEBUG_CREATE_EXTRA_STALLS_IN_VGA_MODE

RESERVED

RESERVED_1
RESERVED_2

RESERVED_3
Bit Default &
Description
Range Access

PANEL_FITTING_ENABLED: Disables the panel fitting function by forcing pixels to

0b bypass. Panel fitting must be disabled when running VGA native modes or interlaced
31 modes on the same pipe. Panel fitting should be enabled or disabled before the pipe is
RW enabled. 0 = Bypass the panel fitting (1:1 ratio) 1 = Enable panel fitting (Ratios include
1:1)

01b PIPE_SELECT: Indicates the pipe attached to the panel fitter 00 = Panel fitter is
30:29 attached to Display Pipe A. 01 = Panel fitter is attached to Display Pipe B. This is the
RW default after reset. 10 = Reserved for pipe C 11 = Reserved for pipe D

SCALING_MODE: 000 = Auto-scale (source and destination should have the same
aspect ratios) 001 = Programmed scaling: Values in register 61234h will be used for
0b horizontal and vertical scaling factors 010 = Pillarbox (example: 4:3 to 16:9 auto
28:26
RW conversion) use only when destination has wider aspect ratio than source 011 =
Letterbox (example: 16:9 to 4:3 auto conversion) use only when destination has taller
aspect ratio than source 1xx = Reserved

0b FILTER_COEFFICIENT_SELECT: Selects the set of predefined filter coefficients to use

25:24 for panel fitting 00 = Fuzzy filtering 01 = Crisp edge enhancing filtering 10 = Median
RW between fuzzy and crisp filtering 11 = Reserved

0b
23 DEBUG_FORCE_TWO_LINE_MODE: debug for two line mode
RW

0b DEBUG_FORCE_THREE_PIXEL_MODE_WHEN_IN_TWO_LINE_MODE: debug
22
RW force three pixel mode when in two line mode

0b DEBUG_CREATE_EXTRA_STALLS_IN_VGA_MODE: 000 = No stall 001 = 33% stall

21:19 010 = 50% stall 011 = 66% stall 100 = 75% stall 101 = 80% stall 110 = 90% stall 111
RW = Reserved

0b
18:5 RESERVED: Reserved.
RW

Bay Trail-I SoC

Datasheet 563
 Graphics, Video and Display

Bit Default &

Description
Range Access

0b
4 RESERVED_1: (was Force One Line Mode) write as zero
RW
0b
3 RESERVED_2: (was Dither Enable which moved to register 61180h)
RW
0b
2:0 RESERVED_3: Reserved.
RW

14.11.45 PFIT_PGM_RATIOS—Offset 61234h

Programmed Panel Fitting Ratios

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) PFIT_PGM_RATIOS: [GTTMMADR_LSB + 2BF20h] + 61234h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED_

PANEL_FITTING_VERTICAL_RATIO

RESERVED__1

PANEL_FITTING_HORIZONTAL_RATIO

Bit Default &

Description
Range Access

0b
31:29 RESERVED_: Reads as zeros
RW
0b
28:16 PANEL_FITTING_VERTICAL_RATIO: Vertical scaling ratio for panel fitting.
RW
0b
15:13 RESERVED__1: Reads as zeros
RW
0b
12:0 PANEL_FITTING_HORIZONTAL_RATIO: Horizontal scaling ratio for panel fitting.
RW

14.11.46 RESERVEDUSEDTOBEAUTOSCALINGRATIOSREADBACK—Offset
61238h
Reserved.

Bay Trail-I SoC

564 Datasheet
Graphics, Video and Display

Access Method
Type: Memory Mapped I/O Register RESERVEDUSEDTOBEAUTOSCALINGRATIOSREADBACK:
(Size: 32 bits) [GTTMMADR_LSB + 2BF20h] + 61238h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESERVED
Bit Default &
Description
Range Access

0b
31:0 RESERVED: Reserved.
RO

14.11.47 RESERVEDUSEDTOBESCALINGINITIALPHASE—Offset 6123Ch

Reserved.

Access Method
Type: Memory Mapped I/O Register RESERVEDUSEDTOBESCALINGINITIALPHASE:
(Size: 32 bits) [GTTMMADR_LSB + 2BF20h] + 6123Ch

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED

Bit Default &

Description
Range Access

0b
31:0 RESERVED: Reserved.
RW

14.11.48 PIPEA_BLC_PWM_CLT2—Offset 61250h

PipeA Backlight PWM Control Register 2

Access Method

Bay Trail-I SoC

Datasheet 565
 Graphics, Video and Display

Type: Memory Mapped I/O Register PIPEA_BLC_PWM_CLT2: [GTTMMADR_LSB + 2BF20h] +

(Size: 32 bits) 61250h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BACKLIGHT_POLARITY
PWM_ENABLE
RESERVED__MBZ
RESERVED_

PHASE_IN_INTERRUPT_STATUS

PHASE_IN_INTERRUPT_ENABLE

PHASE_IN_COUNT
RESERVED

PHASE_IN_ENABLE

PHASE_IN_INCREMENT
PHASE_IN_TIME_BASE

Bit Default &

Description
Range Access

0b PWM_ENABLE: This bit enables the PWM counter logic 0 = PWM disabled (drives 0
31
RW always) 1 = PWM enabled

0b
30 RESERVED__MBZ: Reserved.
RW
0b
29 RESERVED_: Reserved.
RW
0b BACKLIGHT_POLARITY: This field controls the polarity of the PWM signal. 0 = Active
28
RW High 1 = Active Low

0b
27 RESERVED: MBZ
RW

0b PHASE_IN_INTERRUPT_STATUS: This bit will be set by hardware when a Phase-In

26 interrupt has occurred. Software will clear this bit by writing a 1 , which will reset the
RW/1C interrupt generation. [DevCL-A,B] Reserved AccessType: One to Clear

0b PHASE_IN_ENABLE: Setting this bit enables a PWM phase in based on the

25 programming of the Phase In registers below. This bit clears itself when the phase in is
RW completed.
0b PHASE_IN_INTERRUPT_ENABLE: Setting this bit enables an interrupt to be
24
RW generated when the PWM phase in is completed.

0b PHASE_IN_TIME_BASE: This field determines the number of VBLANK events that

23:16
RW pass before one increment occurs. 0 = invalid 1 = 1 vblank 2 = 2 vblanks etc.

PHASE_IN_COUNT: This field determines the number of increment events in this

phase in. Writes to this register should only occur when hardware-phase-ins are
0b disabled. Reads to this register can occur any time, where the value in this field
15:8 indicates the number of increment events remaining to fully apply a phase-in request as
RW hardware automatically decrements this value. A value of 0 is invalid. In order to write
the same value to this field for the second time, one must write a dummy value to this
field, for example, 0 , before writing the real value for the second time.

0b PHASE_IN_INCREMENT: This field indicates the amount to adjust the PWM duty cycle
7:0
RW register on each increment event. This is a two s complement number.

Bay Trail-I SoC

566 Datasheet
Graphics, Video and Display

14.11.49 PIPEA_BLC_PWM_CTL—Offset 61254h

PipeA Backlight PWM Control Register

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) PIPEA_BLC_PWM_CTL: [GTTMMADR_LSB + 2BF20h] + 61254h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BACKLIGHT_DUTY_CYCLE
BACKLIGHT_MODULATION_FREQUENCY

Bit Default &

Description
Range Access

BACKLIGHT_MODULATION_FREQUENCY: This field determines the number of time

base events in total for a complete cycle of modulated backlight control. This field is
0b normally set once during initialization based on the frequency of the clock that is being
31:16
RW used and the desired PWM frequency. This value represents the period of the PWM
stream in display core clocks ([DevCTG] 100MHz HRAW clocks) multiplied by 128 or
25MHz S0IX clocks multipled by 16.

BACKLIGHT_DUTY_CYCLE: This field determines the number of time base events for
the active portion of the PWM backlight control. This should never be larger than the
frequency field. A value of zero will turn the backlight off. A value equal to the backlight
0b modulation frequency field will be full on. This field gets updated when it is desired to
15:0
RW change the intensity of the backlight, it will take affect at the end of the current PWM
cycle. This value represents the active time of the PWM stream in display core clock
([DevCTG] HRAW clock) periods multiplied by 128 or 25MHz S0IX clocks multipled by
16.

14.11.50 PIPEA_BLM_HIST_CTL—Offset 61260h

PipeA Image Enhancement Histogram Control Register

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) PIPEA_BLM_HIST_CTL: [GTTMMADR_LSB + 2BF20h] + 61260h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Bay Trail-I SoC

Datasheet 567
 Graphics, Video and Display

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESERVED_MBZ_IMAGE_ENHANCEMENT_PIPE_ASSIGNMENT
IMAGE_ENHANCEMENT_MODIFICATION_TABLE_ENABLED

BIN_REGISTER_FUNCTION_SELECT
IMAGE_ENHANCEMENT_HISTOGRAM_ENABLED

RESERVED

SYNC_TO_PHASE_IN_COUNT

BIN_REGISTER_INDEX_READ_ONLY
HISTOGRAM_MODE_SELECT

ENHANCEMENT_MODE
RESERVED_1

RESERVED_2
SYNC_TO_PHASE_IN

Bit Default &

Description
Range Access

IMAGE_ENHANCEMENT_HISTOGRAM_ENABLED: This bit enables the Image

0b Enhancement histogram logic to collect data. 0 = Image histogram is disabled 1 = The
31
RW Image histogram is enabled. When this bit is changed from a zero to a one, histogram
calculations will begin after the next VBLANK of the assigned pipe.
IMAGE_ENHANCEMENT_MODIFICATION_TABLE_ENABLED: This bit enables the
0b Image Enhancement modification table. 0 = disabled 1 = enabled. When this bit is
30
RW changed from a zero to a one, modifications begin after the next VBLANK of the
assigned pipe.

0b RESERVED_MBZ_IMAGE_ENHANCEMENT_PIPE_ASSIGNMENT: Each pipe has its

29
RW own IE function

0b
28:25 RESERVED: Always write as 0 s.
RW

0b HISTOGRAM_MODE_SELECT: 0: YUV Luma Mode 1: HSV Intensity Mode - Reserved

24
RW on [DevCL]

0b SYNC_TO_PHASE_IN_COUNT: This field indicates the phase in count number on

23:16
RW which the Image Enhancement table will be loaded if the Sync to Phase in is enabled.

0b
15 RESERVED_1: Always write as 0.
RW

0b ENHANCEMENT_MODE: 00: Direct look up mode 01: Additive mode 10: Multiplicative
14:13
RW mode - Reserved on [DevCL] 11: Reserved

0b SYNC_TO_PHASE_IN: Setting this bit enables the double buffered registers to be

12
RW loaded on the phase in count value specified instead of the next vblank.

BIN_REGISTER_FUNCTION_SELECT: This field indicates what data is being written

0b to or read from the bin data register. 0 = Bin Threshold Count. A read from the bin data
11 register returns that bin s threshold value from the most recent vblank load event
RW (guardband threshold trip). Valid range for the Bin Index is 0 to 31. 1 = Bin Image
Enhancement Value. Valid range for the Bin Index is 0 to 32

Bay Trail-I SoC

568 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

0b
10:7 RESERVED_2: Always write as 0's.
RW

0b BIN_REGISTER_INDEX_READ_ONLY: This field indicates the bin number whose

6:0 data can be accessed through the bin data register. This value is automatically
RW incremented by a read or a write to the bin data register if the busy bit is not set.

14.11.51 PIPEA_IMAGE_ENHANCEMENT_BIN_DATA_REGISTER—Offset
61264h
PIPEA_IMAGE_ENHANCEMENT_BIN_DATA_REGISTER index registers

Access Method
Type: Memory Mapped I/O Register PIPEA_IMAGE_ENHANCEMENT_BIN_DATA_REGISTER:
(Size: 32 bits) [GTTMMADR_LSB + 2BF20h] + 61264h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PIPEA_IMAGE_ENHANCEMENT_BIN_DATA_REGISTER_REGISTER_DESCRIPTIONS

Bay Trail-I SoC

Datasheet 569
 Graphics, Video and Display

Bit Default &

Description
Range Access

0b PIPEA_IMAGE_ENHANCEMENT_BIN_DATA_REGISTER_REGISTER_DESCRIPTI
31:0 ONS: PIPEA_IMAGE_ENHANCEMENT_BIN_DATA_REGISTER indexed register
RW descriptions

14.11.52 PIPEAHISTOGRAMTHRESHOLDGUARDBANDREGISTER—Offset
61268h
pipeA histrogram threshhold gurband register

Access Method
Type: Memory Mapped I/O Register PIPEAHISTOGRAMTHRESHOLDGUARDBANDREGISTER:
(Size: 32 bits) [GTTMMADR_LSB + 2BF20h] + 61268h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HISTOGRAM_EVENT_STATUS_READ_ONLY

THRESHOLD_GUARDBAND
HISTOGRAM_INTERRUPT_ENABLE

GUARDBAND_INTERRUPT_DELAY

Bit Default &

Description
Range Access

0b HISTOGRAM_INTERRUPT_ENABLE: 0 = Disabled 1 = Enabled. This generates a

31
RW histogram interrupt once a Histogram event occurs.

HISTOGRAM_EVENT_STATUS_READ_ONLY: When a Histogram event has occured,

0b this will get set by the hardware. For any more Histogram events to occur, the software
30
RO needs to clear this bit by writing a '1'. The default state for this bit is '0'. 0 = Histogram
event has not occurred. 1 = Histogram event has occurred. AccessType: Read Only

0b GUARDBAND_INTERRUPT_DELAY: An interrupt is generated after this many

29:22 consecutive frames of the guardband threshold being surpassed. This value is double
RW buffered on start of vblank. A value of 0 is invalid.

0b THRESHOLD_GUARDBAND: This value is used to determine the guardband for the

21:0 threshold interrupt generation. This single value is used for all the segments. This value
RW is double buffered on start of vblank

Bay Trail-I SoC

570 Datasheet
Graphics, Video and Display

14.11.53 PIPEB_PP_STATUS—Offset 61300h

PipeB Panel Power Status Register ([DevVLVP]) PP Status (dplrreg.v panel_pwr_sr)

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) PIPEB_PP_STATUS: [GTTMMADR_LSB + 2BF20h] + 61300h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 08000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
REQUIRE_ASSET_STATUS

INTERNAL_SEQUENCE_STATE_FOR_TEST_DEBUG
PANEL_POWER_ON_STATUS

POWER_SEQUENCE_PROGRESS

RESERVED
POWER_CYCLE_DELAY_ACTIVE

Bit Default &

Description
Range Access

PANEL_POWER_ON_STATUS: 0 = Indicates that the panel power down sequencing

has completed. A power cycle delay may be currently active. It is safe and allowed to
program pipe timing and DPLL registers. If this bit is not a zero, it activates the register
write protect and writes to those registers will be ignored unless the write protect key
value is set in the panel sequencing control register. 1 = In conjunction with bits Power
0b Sequence Progress field and Power Cycle Delay Active, this bit set to a one indicates
31 that the panel is currently powered up or is currently in the power down sequence and it
RO is unsafe to change the pipe timing and DPLL registers for the pipe that is assigned to
the embedded panel output. If the embedded panel port is selected as the target for the
panel control, Software is responsible for enabling the LCD display by writing a 1 to the
port enable bit only after all pipe timing, DPLL registers are properly programmed, and
the PLL has locked to the reference signal. This bit is cleared (set to 0) only after the
panel power down sequencing is completed.
REQUIRE_ASSET_STATUS: This bit indicates the status of programming of the display
PLL and the selected display port. This a power on cycle will not be allowed unless this
status indicates that the required assets are programmed and ready for use. 0 = All
0b required assets are not properly programmed. 1 = All required assets are ready for the
30 driving of a panel. The following conditions determine that the assets are ready: 1)
RO Display Pipe PLL Enabled and frequency locked (bit-31 of DPLL Control Register for the
pipe attached to the embedded panel port). 2) Display Pipe Enabled (bit-31 of PIPECONF
Pipe Configuration Register. For the pipe attached to the embedded panel port) 3)
Embedded Panel Port is Programmed Enabled

0b POWER_SEQUENCE_PROGRESS: 00 = Indicates that the panel is not in a power

29:28 sequence 01 = Indicates that the panel is in a power up sequence (may include power
RO cycle delay) 10 = Indicates that the panel is in a power down sequence 11 = Reserved

Bay Trail-I SoC

Datasheet 571
 Graphics, Video and Display

Bit Default &

Description
Range Access

POWER_CYCLE_DELAY_ACTIVE: Power cycle delays occur after a panel power down

1b sequence or after a hardware reset. On reset, a power cycle delay will occur using the
27
RO default value for the timing. 0 = A power cycle delay is not currently active 1 = A power
cycle delay (T4) is currently active
0b
26:4 RESERVED: Reserved.
RO
INTERNAL_SEQUENCE_STATE_FOR_TEST_DEBUG: 0000 = Power Off Idle (S0.0)
0001 = Power Off, Wait for cycle delay (S0.1) 0010 = Power Off (S0.2) 0011 = Power
0b Off (S0.3) 0100 = Reserved 0101 = Reserved 0110 = Reserved 0111 = Reserved 1000
3:0
RO = Power On Idle (S1.0) 1001 = Power On, (S1.1) 1010 = Power On, (S1.2) 1011 =
Power On, Wait for cycle delay (S1.3) 1100 = Reserved 1101 = Reserved 1110 =
Reserved 1111 = Reset

14.11.54 PIPEB_PP_CONTROL—Offset 61304h

PipeB Panel Power Control Register ([DevVLVP]) PP Control (dplrreg.v pnl_pwr_cntl)

Access Method
Type: Memory Mapped I/O Register PIPEB_PP_CONTROL: [GTTMMADR_LSB + 2BF20h] + 61304h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EDP_PANEL_VDD_ENABLE
BACKLIGHT_ENABLE

POWER_STATE_TARGET
WRITE_PROTECT_KEY

RESERVED

POWER_DOWN_ON_RESET

Bay Trail-I SoC

572 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

WRITE_PROTECT_KEY: ABCD Write protect off When this field is programmed to

anything except the write protect off setting and the panel is either powered up or in the
process of a power up sequence, a set of registers involved in generation of panel timing
or control become write protected. Any write cycles to those write protected registers,
while they will complete as normal, will not change the value of the register when write
protected. When this register field contains the write protect off key value, write protect
will be unconditionally disabled. In situations where the embedded panel port is unused,
the port should remain powered down and the write protect will be inactive. This field in
0b normal operation should be left to all zeros and never programmed with the key value.
31:16
RW It exists only to allow testing and workarounds. List of Write protected registers: (Panel
sequencing Registers): Pipe B Panel power on sequencing delays - Address: 61308-
6130Bh Pipe B Panel power off sequencing delays Address: 6130Ch 6130Fh Pipe B Panel
power cycle delay and Reference Divisor Address: 61310h 61313 (DPLL registers): DPLL
Control Registers FPA0 DPLL Divisor Register FPA1 DPLL Divisor Register 1 FPB0 DPLL
Divisor Register FPB1 DPLL Divisor Register 1 (Display Pipe timing registers except
source size) HTOTAL Horizontal Total Register HBLANK Horizontal Blank Register
HSYNC_ Horizontal Sync Register VTOTAL_ Vertical Total Register VBLANK_ Vertical
Blank Register VSYNC_ Vertical Sync Register
0b
15:4 RESERVED: Reserved.
RW
EDP_PANEL_VDD_ENABLE: [DevCDV]: Enabling this bit enables the panel vdd if the
0b embedded panel is DisplayPort, as indicated in bits 31:30 of the panel power on
3 sequencing. Software must enable this bit for eDP link training. After eDP link training is
RW done, software must disable it and let the normal panel power sequencing to take
control. 0 = eDP panel Vdd disabled 1 = eDP panel Vdd enabled [DevCLN] Reserved
BACKLIGHT_ENABLE: [DevCTG, DevCDV]: Enabling this bit enables the panel
0b backlight if the embedded panel is DisplayPort, as indicated in bits 31:30 of the panel
2 power on sequencing. Software must enable this bit after training the link, and disable it
RW when disabling the panel power state target. 0 = Backlight disabled 1 = Backlight
enabled [DevCL] Reserved

POWER_DOWN_ON_RESET: Enabling this bit causes the panel to power down when a
reset warning comes to the GMCH from the ICH. When system reset is initiated, the
0b embedded panel port automatically begins the panel power down sequence. If the panel
1
RW is not on during a reset event, this bit is ignored. 0 = Do not run panel power down
sequence when reset is detected 1 = Run panel power down sequence when system is
reset

POWER_STATE_TARGET: Writing this bit can occur any time, it will only be used at
the completion of any current power cycle. 0 = The panel power state target is off, if the
panel is either on or in a power on sequence, a power off sequence is started as soon as
the panel reaches the power on state. This may include a power cycle delay. If the panel
0b is currently off, there is no change of the power state or sequencing done. 1= The panel
0
RW power state target is on, if the panel is in either the off state or a power off sequence, if
all pre-conditions are met, a power on sequence is started as soon as the panel reaches
the power off state. This may include a power cycle delay. If the panel is currently off,
there is no change of the power state or sequencing done. While the panel is on or in a
power on sequence, the register write lock will be enabled.

14.11.55 PIPEB_PP_ON_DELAYS—Offset 61308h

PipeB Panel Power on Sequencing Delays ([DevVLVP]) PP On Delay values (dplrreg.v
DPLRppon_sd)

Access Method
Type: Memory Mapped I/O Register PIPEB_PP_ON_DELAYS: [GTTMMADR_LSB + 2BF20h] +
(Size: 32 bits) 61308h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

Datasheet 573
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

POWER_ON_TO_BACKLIGHT_ENABLE_DELAY
PANEL_CONTROL_PORT_SELECT

RESERVED

POWER_UP_DELAY

RESERVED_1
Bit Default &
Description
Range Access

PANEL_CONTROL_PORT_SELECT: These bits define to which port the embedded

panel is connected. This is used for automatic control of the panel power. If the selected
0b port is disabled or if the port is not on pipe-B, then, the power sequence will not allow a
31:30 panel power up. 00 = Reserved 01 = Panel is connected to the embedded DisplayPort B
RW 10 = Panel is connected to the embedded DisplayPort C 11 = Reserved The selection of
non-existent ports are not allowed. This programming will disable panel power
sequencing logic.
0b
29 RESERVED: Reserved.
RW

0b POWER_UP_DELAY: Programmable value of panel power sequencing delay during

28:16 panel power up. This provides the time delay for the T1+T2 time sequence. The time
RW unit used is the 100us timer.
0b
15:13 RESERVED_1: Reserved.
RW

0b POWER_ON_TO_BACKLIGHT_ENABLE_DELAY: Programmable value of panel power

12:0 sequencing delay during panel power up. This provides the time delay for the T5 (T3 for
RW DisplayPort) time sequence. The time unit used is the 100us timer.

14.11.56 PIPEB_PP_OFF_DELAYS—Offset 6130Ch

PipeB Panel Power off Sequencing Delays ([DevVLVP]) PP Delay Off values (dplrreg.v
DPLRppoff_sd)

Access Method
Type: Memory Mapped I/O Register PIPEB_PP_OFF_DELAYS: [GTTMMADR_LSB + 2BF20h] +
(Size: 32 bits) 6130Ch

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

574 Datasheet
Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

POWER_BACKLIGHT_OFF_TO_POWER_DOWN_DELAY
RESERVED

POWER_DOWN_DELAY

RESERVED_1
Bit Default &
Description
Range Access

0b
31:29 RESERVED: Reserved.
RW

0b POWER_DOWN_DELAY: Programmable value of panel power sequencing delay during

28:16 power up. This provides the time delay for the T3 (T5 for DisplayPort) time sequence.
RW The time unit used is the 100us timer.
0b
15:13 RESERVED_1: Reserved.
RW

0b POWER_BACKLIGHT_OFF_TO_POWER_DOWN_DELAY: Programmable value of

12:0 panel power sequencing delay during power down. This provides the time delay for the
RW Tx (T4 for DisplayPort) time sequence. The time unit used is the 100us timer.

14.11.57 PIPEB_PP_DIVISOR—Offset 61310h

PipeB Panel Power Cycle Delay and Reference Divisor ([DevVLVP]) PP Divisor (dplrreg.v
DPLRrefdiv_pp_cd)

Access Method
Type: Memory Mapped I/O Register
PIPEB_PP_DIVISOR: [GTTMMADR_LSB + 2BF20h] + 61310h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00270F04h

Bay Trail-I SoC

Datasheet 575
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 0 0

REFERENCE_DIVIDER

RESERVED

POWER_CYCLE_DELAY
Bit Default &
Description
Range Access

REFERENCE_DIVIDER: This field provides the value of the divider used for the
creation of the panel timer reference clock. The output of the divider is used as the
000000000 fastest of the three time bases (100us) for all other timers. The other time bases are
010011100 divided from this frequency. The value of zero should not be used. When it is desired to
31:8 001111b divide by N, the actual value to be programmed is (N/2)-1. The value should be
(100*RefinMHz/2)-1. The default value assumes the default value for the display core
RW clock that is for [DevCL and DevCTG] a 200MHz reference value. The following are
examples for other memory speeds. Display Core Frequency Value of Field 233MHz
2D81h 200MHz 270Fh 133MHz 19F9h
0b
7:5 RESERVED: Reserved.
RW
POWER_CYCLE_DELAY: Programmable value of time panel must remain in a powered
down state after powering down. For devices coming out of reset, the default values will
define how much time must pass before a power on sequence can be started. This field
uses the .1 S time base unit from the divider. If the panel power on sequence is
attempted during this delay, the power on sequence will commence once the power
00100b cycle delay is complete. Writing a value of 0 selects no delay or is used to abort the
4:0 delay if it is active. During the initial power up reset, a D3 cold power cycle, or a user
RW instigated system reset, the timer will be set to the default value and the count down
will begin after the de-assertion of reset. Writing this field to a zero while the count is
active will abort this portion of the sequence. This corresponds to the T4 of the SPWG
specification. Note: Even if the panel is not enabled, the T4 count happens after reset.
This register needs to be programmed to a +1 value. For instance for meeting the SPWG
specification of 400mS, program 5 to achieve at least 400mS delay prior to powerup.

14.11.58 PIPEB_BLC_PWM_CLT2—Offset 61350h

PipeB Backlight PWM Control Register 2

Access Method
Type: Memory Mapped I/O Register PIPEB_BLC_PWM_CLT2: [GTTMMADR_LSB + 2BF20h] +
(Size: 32 bits) 61350h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

576 Datasheet
Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PWM_ENABLE

PHASE_IN_TIME_BASE
BACKLIGHT_POLARITY
RESERVED

PHASE_IN_INTERRUPT_STATUS
PHASE_IN_ENABLE

PHASE_IN_COUNT
PHASE_IN_INTERRUPT_ENABLE

PHASE_IN_INCREMENT
RESERVED_1

RESERVED_2

Bit Default &

Description
Range Access

0b PWM_ENABLE: This bit enables the PWM counter logic 0 = PWM disabled (drives 0
31
RW always) 1 = PWM enabled

0b
30 RESERVED: MBZ
RW
0b
29 RESERVED_1: Reserved.
RW
0b BACKLIGHT_POLARITY: This field controls the polarity of the PWM signal. 0 = Active
28
RW High 1 = Active Low

0b
27 RESERVED_2: MBZ
RW

0b PHASE_IN_INTERRUPT_STATUS: This bit will be set by hardware when a Phase-In

26 interrupt has occurred. Software will clear this bit by writing a 1 , which will reset the
RW/1C interrupt generation. [DevCL-A,B] Reserved AccessType: One to Clear

0b PHASE_IN_ENABLE: Setting this bit enables a PWM phase in based on the

25 programming of the Phase In registers below. This bit clears itself when the phase in is
RW completed.
0b PHASE_IN_INTERRUPT_ENABLE: Setting this bit enables an interrupt to be
24
RW generated when the PWM phase in is completed.

0b PHASE_IN_TIME_BASE: This field determines the number of VBLANK events that

23:16
RW pass before one increment occurs. 0 = invalid 1 = 1 vblank 2 = 2 vblanks etc.

PHASE_IN_COUNT: This field determines the number of increment events in this

phase in. Writes to this register should only occur when hardware-phase-ins are
0b disabled. Reads to this register can occur any time, where the value in this field
15:8 indicates the number of increment events remaining to fully apply a phase-in request as
RW hardware automatically decrements this value. A value of 0 is invalid. In order to write
the same value to this field for the second time, one must write a dummy value to this
field, for example, 0 , before writing the real value for the second time.
0b PHASE_IN_INCREMENT: This field indicates the amount to adjust the PWM duty cycle
7:0
RW register on each increment event. This is a two s complement number.

14.11.59 PIPEB_BLC_PWM_CTL—Offset 61354h

PipeB Backlight PWM Control Register

Access Method

Bay Trail-I SoC

Datasheet 577
 Graphics, Video and Display

Type: Memory Mapped I/O Register

PIPEB_BLC_PWM_CTL: [GTTMMADR_LSB + 2BF20h] + 61354h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BACKLIGHT_MODULATION_FREQUENCY

BACKLIGHT_DUTY_CYCLE
Bit Default &
Description
Range Access

BACKLIGHT_MODULATION_FREQUENCY: This field determines the number of time

base events in total for a complete cycle of modulated backlight control. This field is
0b normally set once during initialization based on the frequency of the clock that is being
31:16
RW used and the desired PWM frequency. This value represents the period of the PWM
stream in display core clocks ([DevCTG] HRAW clocks) multiplied by 128 or 25MHz S0IX
clocks multipled by 16.
BACKLIGHT_DUTY_CYCLE: This field determines the number of time base events for
the active portion of the PWM backlight control. This should never be larger than the
frequency field. A value of zero will turn the backlight off. A value equal to the backlight
0b modulation frequency field will be full on. This field gets updated when it is desired to
15:0
RW change the intensity of the backlight, it will take affect at the end of the current PWM
cycle. This value represents the active time of the PWM stream in display core clock
([DevCTG] HRAW clock) periods multiplied by 128 or 25MHz S0IX clocks multipled by
16.

14.11.60 PIPEB_BLM_HIST_CTL—Offset 61360h

PipeB Image Enhancement Histogram Control Register

Access Method
Type: Memory Mapped I/O Register
PIPEB_BLM_HIST_CTL: [GTTMMADR_LSB + 2BF20h] + 61360h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

578 Datasheet
Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESERVED_MBZ_IMAGE_ENHANCEMENT_PIPE_ASSIGNMENT
IMAGE_ENHANCEMENT_MODIFICATION_TABLE_ENABLED

HISTOGRAM_MODE_SELECT

BIN_REGISTER_FUNCTION_SELECT
IMAGE_ENHANCEMENT_HISTOGRAM_ENABLED

RESERVED

BIN_REGISTER_INDEX_READ_ONLY
SYNC_TO_PHASE_IN_COUNT

ENHANCEMENT_MODE
RESERVED_1

RESERVED_2
Bit Default &
Description SYNC_TO_PHASE_IN
Range Access

IMAGE_ENHANCEMENT_HISTOGRAM_ENABLED: This bit enables the Image

0b Enhancement histogram logic to collect data. 0 = Image histogram is disabled 1 = The
31
RW Image histogram is enabled. When this bit is changed from a zero to a one, histogram
calculations will begin after the next VBLANK of the assigned pipe.
IMAGE_ENHANCEMENT_MODIFICATION_TABLE_ENABLED: This bit enables the
0b Image Enhancement modification table. 0 = disabled 1 = enabled. When this bit is
30
RW changed from a zero to a one, modifications begin after the next VBLANK of the
assigned pipe.

0b RESERVED_MBZ_IMAGE_ENHANCEMENT_PIPE_ASSIGNMENT: Each pipe has its

29
RW own dedicated IE function.

0b
28:25 RESERVED: Always write as 0 s.
RW

0b HISTOGRAM_MODE_SELECT: 0: YUV Luma Mode 1: HSV Intensity Mode - Reserved

24
RW on [DevCL]

0b SYNC_TO_PHASE_IN_COUNT: This field indicates the phase in count number on

23:16
RW which the Image Enhancement table will be loaded if the Sync to Phase in is enabled.

0b
15 RESERVED_1: Always write as 0.
RW

0b ENHANCEMENT_MODE: 00: Direct look up mode 01: Additive mode 10: Multiplicative
14:13
RW mode - Reserved on [DevCL] 11: Reserved

0b SYNC_TO_PHASE_IN: Setting this bit enables the double buffered registers to be

12
RW loaded on the phase in count value specified instead of the next vblank.

BIN_REGISTER_FUNCTION_SELECT: This field indicates what data is being written

0b to or read from the bin data register. 0 = Bin Threshold Count. A read from the bin data
11 register returns that bin s threshold value from the most recent vblank load event
RW (guardband threshold trip). Valid range for the Bin Index is 0 to 31. 1 = Bin Image
Enhancement Value. Valid range for the Bin Index is 0 to 32

Bay Trail-I SoC

Datasheet 579
 Graphics, Video and Display

Bit Default &

Description
Range Access

0b
10:7 RESERVED_2: Always write as 0's.
RW
BIN_REGISTER_INDEX_READ_ONLY: This field indicates the bin number whose
0b data can be accessed through the bin data register. This value is automatically
6:0
RO incremented by a read or a write to the bin data register if the busy bit is not set.
AccessType: Read Only

14.11.61 PIPEB_IMAGE_ENHANCEMENT_BIN_DATA_REGISTER—Offset
61364h
PIPEB_IMAGE_ENHANCEMENT_BIN_DATA_REGISTER index registers

Access Method
Type: Memory Mapped I/O Register PIPEB_IMAGE_ENHANCEMENT_BIN_DATA_REGISTER:
(Size: 32 bits) [GTTMMADR_LSB + 2BF20h] + 61364h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PIPEB_IMAGE_ENHANCEMENT_BIN_DATA_REGISTER_REGISTER_DESCRIPTIONS

Bay Trail-I SoC

580 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

0b PIPEB_IMAGE_ENHANCEMENT_BIN_DATA_REGISTER_REGISTER_DESCRIPTI
31:0 ONS: PIPEB_IMAGE_ENHANCEMENT_BIN_DATA_REGISTER indexed register
RW descriptions

14.11.62 PIPEBHISTOGRAMTHRESHOLDGUARDBANDREGISTER—Offset
61368h
pipe B histogram threshhold gurband register

Access Method
Type: Memory Mapped I/O Register PIPEBHISTOGRAMTHRESHOLDGUARDBANDREGISTER:
(Size: 32 bits) [GTTMMADR_LSB + 2BF20h] + 61368h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HISTOGRAM_EVENT_STATUS_READ_ONLY

THRESHOLD_GUARDBAND
HISTOGRAM_INTERRUPT_ENABLE

GUARDBAND_INTERRUPT_DELAY

Bit Default &

Description
Range Access

0b HISTOGRAM_INTERRUPT_ENABLE: 0 = Disabled 1 = Enabled. This generates a

31
RW histogram interrupt once a Histogram event occurs.

HISTOGRAM_EVENT_STATUS_READ_ONLY: When a Histogram event has occured,

0b this will get set by the hardware. For any more Histogram events to occur, the software
30
RO needs to clear this bit by writing a '1'. The default state for this bit is '0'. 0 = Histogram
event has not occurred. 1 = Histogram event has occurred. AccessType: Read Only

0b GUARDBAND_INTERRUPT_DELAY: An interrupt is generated after this many

29:22 consecutive frames of the guardband threshold being surpassed. This value is double
RW buffered on start of vblank. A value of 0 is invalid.

0b THRESHOLD_GUARDBAND: This value is used to determine the guardband for the

21:0 threshold interrupt generation. This single value is used for all the segments. This value
RW is double buffered on start of vblank

Bay Trail-I SoC

Datasheet 581
 Graphics, Video and Display

14.11.63 MIPIC_PORT_CTRL—Offset 61700h

mipi C port ctrl

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) MIPIC_PORT_CTRL: [GTTMMADR_LSB + 2BF20h] + 61700h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EN

DITHER

RESERVED_1

RESERVED_2
RESERVED_3
RESERVED_4

RESERVED_5

RESERVED_6

RESERVED_7
RESERVED

DELAY

RESERVED_8
EFFECT
Bit Default &
Description
Range Access

EN: When this bit is disabled the MIPI DPI (video mode) is inactive and in it's low power
0b state. When it is enable it starts to generate timing for this MIPI port 0 = The port is
31
RW disabled and all MIPI DPI interface are disable (timing generator is off) 1 = The port is
enabled
0b
30:26 RESERVED: Reserved.
RW

0b DITHER: This bit enables or disables (bypassing) 8-6-bit color dithering function. The
25 usage of this bit would be on for 18-bpp panels and off for 24-bpp panels. 0 = disabled
RW 1 = enabled
0b
24:22 RESERVED_1: Reserved.
RW
0b
21 RESERVED_2: Reserved.
RW
0b
20 RESERVED_3: Reserved.
RW
0b
19 RESERVED_4: Reserved.
RW
0b
18:16 RESERVED_5: Reserved.
RW
0b
15 RESERVED_6: Reserved.
RW
0b
14:5 RESERVED_7: Reserved.
RW
0b
4 DELAY: When set, the TE counter will be count down until
RW

0b EFFECT: 00: No tearing effect required - memory write start as soon as write data is
3:2 available 01: TE trigger by MIPI DPHY and DSI protocol 10: TE trigger by GPIO pin 11:
RW Reserved
0b
1:0 RESERVED_8: Reserved.
RW

Bay Trail-I SoC

582 Datasheet
Graphics, Video and Display

14.11.64 MIPIC_TEARING_CTR—Offset 61704h

mipi C tearing ctr

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) MIPIC_TEARING_CTR: [GTTMMADR_LSB + 2BF20h] + 61704h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED

TE
Bit Default &
Description
Range Access

0b
31:16 RESERVED: Reserved.
RW

0b
15:0 TE: Number of delay clocks from TE trigger to start sending data to DSI controller
RW

14.11.65 AUD_CONFIG_A—Offset 62000h

Audio Configuration Pipe A

Access Method
Type: Memory Mapped I/O Register AUD_CONFIG_A: [GTTMMADR_LSB + 2BF20h] + 62000h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
N_PROGRAMMING_ENABLE_TESTMODE

PIXEL_CLOCK_HDMI
N_VALUE_INDEX

UPPER_N_VALUE_TESTMODE

LOWER_N_VALUE_TESTMODE

DISABLE_NCTS
RESERVED

RESERVED_1

Bay Trail-I SoC

Datasheet 583
 Graphics, Video and Display

Bit Default &

Description
Range Access

0b
31:30 RESERVED: Project: All Format:
RW
N_VALUE_INDEX: Project: All Default Value: 0b Value Name Description Project 0b
HDMI N value read on bits 27:20 and 15:4 reflects HDMI N value. Bits 27:20 and 15:4
0b are is programmable to any N value - default h7FA6. All 1b DP N value read on bits
29
RW 27:20 and 15:4 reflects DP N value. Set this bit to 1 before programming N value
register. When this is set to 1, 27:20 and 15:4 will reflect the current N value default
h8000. All

0b N_PROGRAMMING_ENABLE_TESTMODE: Project: All Security: Test This bit enables

28 programming of N values for non-CEA modes. Please note that the Pipe to which audio
RW is attached must be disabled when changing this field.
UPPER_N_VALUE_TESTMODE: Project: All Security: Test These are bits [19:12] of
programmable N values for non-CEA modes. Bit 25 of this register must also be written
0b in order to enable programming. Please note that the Pipe to which audio is attached
27:20
RW must be disabled when changing this field. This register can also be used to program N
value for DP for a specific Port. Default value on this register when bit 29 is set to 1 is
h7FA6
PIXEL_CLOCK_HDMI: Project: All Default Value: 0b This is the target frequency of the
CEA/HDMI video mdoe to which the audio stream is added. This value is used for
generating N_CTS packets. This refers to only HDMI Pixel clock and does not refer to DP
Link clock. DP Link clock does not require this programming. Note: The Pipe on which
0b audio is attached must be disabled when changing this field. Value Name Description
19:16 Project 0000b 25.2 / 1.001 MHz 25.2 / 1.001 MHz All 0001b 25.2 MHz 25.2 MHz
RW Program this value for pixel clocks not listed in this field All 0010b 27 MHz 27 MHz All
0011b 27 * 1.001 MHz 27 * 1.001 MHz All 0100b 54 MHz 54 MHz All 0101b 54 * 1.001
MHz 54 * 1.001 MHz All 0110b 74.25 / 1.001 MHz 74.25 / 1.001 MHz All 0111b 74.25
MHz 74.25 MHz All 1000b 148.5 / 1.001 MHz 148.5 / 1.001 MHz All 1001b 148.5 MHz
148.5 MHz All Others Reserved Reserved All
LOWER_N_VALUE_TESTMODE: Project: All Security: Test These are bits [11:0] of
programmable N values for non-CEA modes. Bit 25 of this register must also be written
0b in order to enable programming. Please note that the Pipe to which audio is attached
15:4
RW must be disabled when changing this field. This register can also be used to program N
value for DP for a specific Port. Default value on this register when bit 29 is set to 1 is
h7FA6
0b DISABLE_NCTS: Project: All Set this bit to disable N and CTS or M generation for CTM
3
RW modes. This is to enable prediction of CRC in CTM modes.

0b
2:0 RESERVED_1: Project: All Format:
RW

14.11.66 AUD_MISC_CTRL_A—Offset 62010h

Audio MISC Control for Pipe A

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) AUD_MISC_CTRL_A: [GTTMMADR_LSB + 2BF20h] + 62010h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000044h

Bay Trail-I SoC

584 Datasheet
Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0

SAMPLE_PRESENT_DISABLE

OUTPUT_DELAY
RESERVED

PRO_ALLOWED
SAMPLE_FABRICATION_EN_BIT
RESERVED_1

RESERVED_2
Bit Default &
Description
Range Access

0b
31:9 RESERVED: Project: All Format: MBZ
RW

0b SAMPLE_PRESENT_DISABLE: Project: All Security: Debug This bit is used to Disable

8
RW sample present for HDMI or DP (Chicken Bit)

0100b OUTPUT_DELAY: Project: All Default Value: 0100b The number of samples between
7:4 when the sample is received from the HD Audio link and when it appears as an analog
RW signal at the pin.

0b
3 RESERVED_1: Project: All Format: MBZ
RW

SAMPLE_FABRICATION_EN_BIT: Project: All Access: R/W Default Value: ;1b This bit
1b indicates whether internal fabrication of audio samples is enabled during a link
2
RW underrun. Value Name Description Project 0b Disable Audio fabrication disabled All 1b
Enable Audio fabrication enabled All
PRO_ALLOWED: Project: All Access: R/W Default Value: 0b By default, the audio
device is configured to consumer mode and does not allow the mode to be changed to
professional mode by an HD Audio verb. When Pro is allowed by setting this
0b configuration bit, the HD Audio codec allows a verb to set the device into professional
1
RW mode. Note: Setting this configuration bit does not change the default Pro bit value to
be 1. Pro must be set to 1 through the normal process, using a verb. Value Name
Description Project 0b Consumer Consumer use only All 1b Professional Professional use
allowed All
0b
0 RESERVED_2: All Format: MBZ
RW

14.11.67 AUD_VID_DID—Offset 62020h

Audio Vendor ID / Device ID

Access Method
Type: Memory Mapped I/O Register
AUD_VID_DID: [GTTMMADR_LSB + 2BF20h] + 62020h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 80862882h

Bay Trail-I SoC

Datasheet 585
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

1 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 0 1 0 0 0 1 0 0 0 0 0 1 0

VENDOR_ID

DEVICE_ID
Bit Default &
Description
Range Access

100000001
VENDOR_ID: Project: All Format: U16 Used to identify the codec within the PnP
31:16 0000110b
system. This field is hardwired within the device. Value = 0x8086
RO
001010001
DEVICE_ID: Project: All Format: U16 Constant used to identify the codec within the
15:0 0000010b
PnP system. This field is set by the device hardware. Value = 0x2882 [Valleyview2]
RO

14.11.68 AUD_RID—Offset 62024h

Audio Revision ID

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) AUD_RID: [GTTMMADR_LSB + 2BF20h] + 62024h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00100000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MINOR_REVISION
MAJOR_REVISION
RESERVED

REVISION_ID

STEPPING_ID

Bit Default &

Description
Range Access

0b
31:24 RESERVED: Project: All Format:
RO

0001b MAJOR_REVISION: Project: All Default Value: 0001b The major revision number (left
23:20 of the decimal) of the HD Audio Spec to which the codec is fully compliant. This field is
RO hardwired within the device. Value = 0x1

0b MINOR_REVISION: Project: All The minor revision number (rights of the decimal) or
19:16 dot number of the HD Audio Spec to which the codec is fully compliant. This field is
RO hardwired within the device. Value = 0x0
0b REVISION_ID: Project: All The vendors revision number for this given Device ID. This
15:8
RO field is hardwired within the device. Value = 0x0

0b STEPPING_ID: Project: All An optional vendor stepping number within the given
7:0
RO Revision ID. This field is hardwired within the device. Value = 0x0

Bay Trail-I SoC

586 Datasheet
Graphics, Video and Display

14.11.69 AUD_CTS_ENABLE_A—Offset 62028h

Audio CTS Programming Enable Pipe A

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) AUD_CTS_ENABLE_A: [GTTMMADR_LSB + 2BF20h] + 62028h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ENABLE_CTS_OR_M_PROGRAMMING
CTS_M_VALUE_INDEX

CTS_PROGRAMMING
RESERVED

Bit Default &

Description
Range Access

0b
31:22 RESERVED: Project: All Format:
RW

CTS_M_VALUE_INDEX: Project: All Default Value: 0b Value Name Description Project

0b 0b CTS CTS value read on bits 23:4 reflects CTS value. Bit 23:4 is programmable to any
21 CTS value. default is 0 All 1b M M value read on bits 21:4 reflects DP M value. Set this
RW bit to 1 before programming M value register. When this is set to 1 23:4 will reflect the
current N value All

0b ENABLE_CTS_OR_M_PROGRAMMING: Project: All When set will enable CTS or M

20
RW programming.

CTS_PROGRAMMING: Project: All These are bits [19:0] of programmable CTS values
0b for non-CEA modes. Bit 21 of this register must also be written in order to enable
19:0
RW programming. Please note that the Pipe to which audio is attached must be disabled
when changing this field.

14.11.70 AUD_PWRST—Offset 6204Ch

Audio Power State (Function Group, Convertor, Pin Widget)

Access Method
Type: Memory Mapped I/O Register
AUD_PWRST: [GTTMMADR_LSB + 2BF20h] + 6204Ch
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00FFFFFFh

Bay Trail-I SoC

Datasheet 587
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

CONVERTORA_WIDGET_POWER_STATE_REQUSTED

PINC_WIDGET_POWER_STATE_SET
RESERVED

CONVERTORB_WIDGET_POWER_STATE_CURRENT

CONVERTORB_WIDGET_POWER_STATE_REQUESTED

PIND_WIDGET_POWER_STATE_CURRENT
CONVERTORA_WIDGET_POWER_STATE_CURRENT

PINC_WIDGET_POWER_STATE_CURRENT

PINB_WIDGET_POWER_STATE_CURRENT
FUNCTION_GROUP_DEVICE_POWER_STATE_CURRENT

PIND_WIDGET_POWER_STATE_SET

PINB_WIDGET_POWER_STATE_SET
FUNCTION_GROUP_DEVICE_POWER_STATE_SET

Bit Default &

Description
Range Access

0b
31:24 RESERVED: Project: All Format:
RO

FUNCTION_GROUP_DEVICE_POWER_STATE_CURRENT: Project: All Format:

11b Audio Power State Format Current power state Project: All Default Value: ;11b D3 Value
23:22
RO Name Description Project 00b D0 D0 All 01b,10b Unsupported Unsupported All 11b D3
D3 All
FUNCTION_GROUP_DEVICE_POWER_STATE_SET: Project: All Format: Audio
11b Power State Format Power state that was set Project: All Default Value: ;11b D3 Value
21:20
RO Name Description Project 00b D0 D0 All 01b,10b Unsupported Unsupported All 11b D3
D3 All

11b CONVERTORB_WIDGET_POWER_STATE_CURRENT: Project: All Format: Audio

19:18 Power State Format Current power state Project: All Default Value: ;11b D3 Value Name
RO Description Project 00b D0 D0 All 01b,10b Unsupported Unsupported All 11b D3 D3 All

CONVERTORB_WIDGET_POWER_STATE_REQUESTED: Project: All Format: Audio

11b Power State Format Power state that was requested by audio software Project: All
17:16
RO Default Value: ;11b D3 Value Name Description Project 00b D0 D0 All 01b,10b
Unsupported Unsupported All 11b D3 D3 All

11b CONVERTORA_WIDGET_POWER_STATE_CURRENT: Project: All Format: Audio

15:14 Power State Format Current power state Project: All Default Value: ;11b D3 Value Name
RO Description Project 00b D0 D0 All 01b,10b Unsupported Unsupported All 11b D3 D3 All
CONVERTORA_WIDGET_POWER_STATE_REQUSTED: Project: All Format: Audio
11b Power State Format Power state that was requested by audio software Project: All
13:12
RO Default Value: ;11b D3 Value Name Description Project 00b D0 D0 All 01b,10b
Unsupported Unsupported All 11b D3 D3 All

11b PIND_WIDGET_POWER_STATE_CURRENT: Project: All Format: Audio Power State

11:10 Format Current power state Project: All Default Value: ;11b D3 Value Name Description
RO Project 00b D0 D0 All 01b,10b Unsupported Unsupported All 11b D3 D3 All

11b PIND_WIDGET_POWER_STATE_SET: Project: All Format: Audio Power State Format

9:8 Power state that was set Project: All Default Value: ;11b D3 Value Name Description
RO Project 00b D0 D0 All 01b,10b Unsupported Unsupported All 11b D3 D3 All

Bay Trail-I SoC

588 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

11b PINC_WIDGET_POWER_STATE_CURRENT: Project: All Format: Audio Power State

7:6 Format Current power state Project: All Default Value: ;11b D3 Value Name Description
RO Project 00b D0 D0 All 01b,10b Unsupported Unsupported All 11b D3 D3 All

11b PINC_WIDGET_POWER_STATE_SET: Project: All Format: Audio Power State Format

5:4 Power state that was set Project: All Default Value: ;11b D3 Value Name Description
RO Project 00b D0 D0 All 01b,10b Unsupported Unsupported All 11b D3 D3 All
11b PINB_WIDGET_POWER_STATE_CURRENT: Project: All Format: Audio Power State
3:2
RO Current power state

11b PINB_WIDGET_POWER_STATE_SET: Project: All Format: Audio Power State Format

1:0 Power state that was set Project: All Default Value: ;11b D3 Value Name Description
RO Project 00b D0 D0 All 01b,10b Unsupported Unsupported All 11b D3 D3 All

14.11.71 AUD_HDMIW_HDMIEDID_A—Offset 62050h

HDMI Data EDID Block Pipe A

Access Method
Type: Memory Mapped I/O Register AUD_HDMIW_HDMIEDID_A: [GTTMMADR_LSB + 2BF20h] +
(Size: 32 bits) 62050h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EDID_HDMI_DATA_BLOCK

Bit Default &

Description
Range Access

0b EDID_HDMI_DATA_BLOCK: Project: All Format: Please note that the contents of this
31:0 buffer are not cleared when ELD is disabled. The contents of this buffer are cleared
RW during gfx reset

14.11.72 AUD_HDMIW_INFOFR_A—Offset 62054h

Audio Widget Data Island Packet Pipe A

Access Method

Bay Trail-I SoC

Datasheet 589
 Graphics, Video and Display

Type: Memory Mapped I/O Register AUD_HDMIW_INFOFR_A: [GTTMMADR_LSB + 2BF20h] +

(Size: 32 bits) 62054h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DATA_ISLAND_PACKET_DATA
Bit Default &
Description
Range Access

0b DATA_ISLAND_PACKET_DATA: Project: All Format: This reflects the contents of the

31:0 DIP indexed by the DIP access address. The contents of this buffer are cleared during
RO function reset or HD audio link reset.

14.11.73 AUD_PORT_EN_HD_CFG—Offset 6207Ch

Audio Port Enable HDAudio Config

Access Method
Type: Memory Mapped I/O Register AUD_PORT_EN_HD_CFG: [GTTMMADR_LSB + 2BF20h] +
(Size: 32 bits) 6207Ch

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00077003h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1
PORT_D_AMP_MUTE_STATUS

PORT_B_AMP_MUTE_STATUS
PORT_C_AMP_MUTE_STATUS

CONVERTOR_B_DIGEN
CONVERTOR_A_DIGEN
RESERVED

RESERVED_1
PORT_D_OUT_ENABLE
PORT_C_OUT_ENABLE
PORT_B_OUT_ENABLE

CONVERTORB_STREAM_ID

CONVERTORA_STREAM_ID

RESERVED_2

Bay Trail-I SoC

590 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

0b
31:19 RESERVED: Project: All Format:
RO

1b PORT_D_AMP_MUTE_STATUS: Project: All Default Value: ;1b Amp muted This read-
18 only bit reflects the mute status of the amplifier Value Name Description Project 0b Amp
RO not muted Amp not muted All 1b Amp muted Amp muted All

1b PORT_C_AMP_MUTE_STATUS: Project: All Default Value: ;1b Amp muted This read-
17 only bit reflects the mute status of the amplifier Value Name Description Project 0b Amp
RO not muted Amp not muted All 1b Amp muted Amp muted All

1b PORT_B_AMP_MUTE_STATUS: Project: All Default Value: ;1b Amp muted This read-
16 only bit reflects the mute status of the amplifier Value Name Description Project 0b Amp
RO not muted Amp not muted All 1b Amp muted Amp muted All
0b
15 RESERVED_1: Project: All Format:
RO

1b PORT_D_OUT_ENABLE: Project: All Default Value: ;1b Audio is Enabled This bit
14 reflects the state of the output path of the Pin Widget. Value Name Description Project
RO 0b Disable Audio is Disabled All 1b Enable Audio is Enabled All

1b PORT_C_OUT_ENABLE: Project: All Default Value: ;1b Audio is Enabled This bit
13 reflects the state of the output path of the Pin Widget. Value Name Description Project
RO 0b Disable Audio is Disabled All 1b Enable Audio is Enabled All

1b PORT_B_OUT_ENABLE: Project: All Default Value: ;1b Audio is Enabled This bit
12 reflects the state of the output path of the Pin Widget. Value Name Description Project
RO 0b Disable Audio is Disabled All 1b Enable Audio is Enabled All

0b CONVERTORB_STREAM_ID: Project: All Format: Represents the link stream used by

11:8 the converter for data input or output. This value is set in the Channel ID and Stream ID
RO through the Set Audio Output Converter Widget command. Default = 0 (stream 0)

0b CONVERTORA_STREAM_ID: Project: All Format: Represents the link stream used by

7:4 the converter for data input or output. This value is set in the Channel ID and Stream ID
RO through the Set Audio Output Converter Widget command. Default = 0 (stream 0)
0b
3:2 RESERVED_2: Project: All Format:
RO
CONVERTOR_B_DIGEN: Project: All Default Value: ;1b Digital Transmission Enabled
1b Enables digital transmission through this node. This value is set in the Digital Converter
1 2 through the Set Audio Output Converter Widget command. Value Name Description
RO Project 0b Block Digital data is blocked from passing through the node, regardless of the
state All 1b Pass Digital data can pass through the node (Default) All
CONVERTOR_A_DIGEN: Project: All Default Value: ;1b Digital Transmission Enabled
1b Enables digital transmission through this node. This value is set in the Digital Converter
0 2 through the Set Audio Output Converter Widget command. Value Name Description
RO Project 0b Block Digital data is blocked from passing through the node, regardless of the
state All 1b Pass Digital data can pass through the node (Default) All

14.11.74 AUD_OUT_DIG_CNVT_A—Offset 62080h

Audio Digital Converter Conv A

Access Method
Type: Memory Mapped I/O Register AUD_OUT_DIG_CNVT_A: [GTTMMADR_LSB + 2BF20h] +
(Size: 32 bits) 62080h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

Datasheet 591
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

LOWEST_CHANNEL_NUMBER
RESERVED

LEVEL

NON_AUDIO
CATEGORY_CODE

PRO

COPY

V
STREAM_ID

PRE
RESERVED_1

VCFG

RESERVED_2
Bit Default &
Description
Range Access

0b
31:24 RESERVED: Project: All Format:
RO

0b STREAM_ID: Project: All Format: Represents the link stream used by the converter for
23:20 data input or output. This value is set in the Channel ID and Stream ID through the Set
RO Audio Output Converter Widget command. Default = 0 (stream 0)

0b LOWEST_CHANNEL_NUMBER: Project: All Format: Represents the lowest channel

19:16 used by the converter. This value is set in the Channel ID and Stream ID through the
RO Set Audio Output Converter Widget command. Default = 0

0b
15 RESERVED_1: Project: All Format:
RO

0b CATEGORY_CODE: Project: All Format: S/PDIF IEC Category Code. This value is set in
14:8 the Digital Converter 1 through the Set Audio Output Converter Widget command.
RO Default = 0

0b LEVEL: Project: All Format: S/PDIF IEC Generation Level. This value is set in the Digital
7
RO Converter 2 through the Set Audio Output Converter Widget command. Default = 0

PRO: Project: All Default Value: 0b This bit indicates professional or consumer use of
0b channel. This value is set in the Digital Converter 2 through the Set Audio Output
6 Converter Widget command. This value can only be set to 1 if the Pro Allowed bit is set
RO in the audio configuration register. Value Name Description Project 0b Consumer
Consumer use All 1b Professional Professional use All

NON_AUDIO: Project: All Default Value: 0b Data is non PCM format. This value is set in
0b the Digital Converter 2 through the Set Audio Output Converter Widget command. Value
5
RO Name Description Project 0b PCM Data is PCM All 1b Non PCM Data is non PCM format
All
COPY: Project: All Default Value: 0b Copyright asserted. This value is set in the Digital
0b Converter 2 through the Set Audio Output Converter Widget command. Value Name
4
RO Description Project 0b Not Asserted Copyright is not asserted All 1b Asserted Copyright
is asserted All
PRE: Project: All Default Value: 0b Filter preemphasis. This value is set in the Digital
0b Converter 2 through the Set Audio Output Converter Widget command. Value Name
3
RO Description Project 0b Disabled Preemphasis is disabled All 1b Enabled Filter
preemphasis is enabled All

0b VCFG: Project: All Format: Validity Configuration. Determines S/PDIF transmitter

2 behavior when data is not being transmitted. This value is set in the Digital Converter 2
RO through the Set Audio Output Converter Widget command. Default = 0

V: Project: All Format: Affects the validity flag transmitted in each subframe, and
0b enables the S/PDIF transmitter to maintain connection during error or mute conditions.
1
RO This value is set in the Digital Converter 2 through the Set Audio Output Converter
Widget command. Default = 0
0b
0 RESERVED_2: All Format: MBZ
RO

Bay Trail-I SoC

592 Datasheet
Graphics, Video and Display

14.11.75 AUD_OUT_STR_DESC_A—Offset 62084h

Audio Stream Descriptor Format Conv A

Access Method
Type: Memory Mapped I/O Register AUD_OUT_STR_DESC_A: [GTTMMADR_LSB + 2BF20h] +
(Size: 32 bits) 62084h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000032h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0

SAMPLE_BASE_RATE_MULT
SAMPLE_BASE_RATE
RESERVED

HBR_ENABLE

BITS_PER_SAMPLE
CONVERTOR_CHANNEL_COUNT
RESERVED_1

RESERVED_2

SAMPLE_BASE_RATE_DIVISOR

RESERVED_3

NUMBER_OF_CHANNELS_IN_A_STREAM
Bit Default &
Description
Range Access

0b
31:29 RESERVED: Project: All Format:
RO
0b
28:27 HBR_ENABLE: Project: All Format: This reflects the current HBR settings.
RO

0b
26:21 RESERVED_1: Project: All Format:
RO

0b CONVERTOR_CHANNEL_COUNT: Project: All Format: This reflects the Convertor

20:16
RO Channel Count programmed through HDAudio.

0b
15 RESERVED_2: Project: All Format:
RO

0b SAMPLE_BASE_RATE: Project: All Default Value: 0b 48 kHz Sampling base rate of

14 audio stream. Value Name Description Project 0b 48 kHz 48 kHz All 1b 44.1 kHz 44.1
RO kHz All

SAMPLE_BASE_RATE_MULT: Project: All Default Value: 000b 48 kHz Audio stream

0b sample base rate multiple. Value Name Description Project 000b x1 x1 (48 kHz/44.1
13:11
RO kHz or less) All 001b x2 x2 (96 kHz, 88.2 kHz, 32 kHz) All 010b x3 x3 (144 kHz) All
011b x4 x4 (192 kHz, 176.4 kHz) All 1XXb Reserved Reserved All
SAMPLE_BASE_RATE_DIVISOR: Project: All Default Value: 000b 48 kHz Audio
stream sample base rate divisor. Value Name Description Project 000b Div 1 Divide by 1
0b (48 kHz, 44.1 kHz) All 001b Div 2 Divide by 2 (24 kHz, 22.05 kHz) All 010b Div 3 Divide
10:8
RO by 3 (16 kHz, 32 kHz) All 011b Div 4 Divide by 4 (11.025 kHz) All 100b Div 5 Divide by
5 (9.6 kHz) All 101b Div 6 Divide by 6 (8 kHz) All 110b Div 7 Divide by 7 All 111b Div 8
Divide by 8 (6 kHz) All

Bay Trail-I SoC

Datasheet 593
 Graphics, Video and Display

Bit Default &

Description
Range Access

0b
7 RESERVED_3: Project: All Format: MBZ
RO
BITS_PER_SAMPLE: Project: All Default Value: 011b 32 bits Value Name Description
Project 000b 8 bit The data will be packed in memory in 8 bit containers on 16 bit
011b boundaries All 001b 16 bits The data will be packed in memory in 16 bit containers on
6:4 16 bit boundaries All 100b 20 bits The data will be packed in memory in 20 bit
RO containers on 32 bit boundaries All 010b 24 bits The data will be packed in memory in
32 bit containers on 32 bit boundaries All 011b 32 bits The data will be packed in
memory in 32 bit containers on 32 bit boundaries All Others Reserved Reserved All

0010b NUMBER_OF_CHANNELS_IN_A_STREAM: Project: All Default Value: 0010b 3

3:0 channels in each frame Format: U4+1 Binary value plus 1. 0000 = 1, 1111= 16 Number
RO of channels in each frame of the stream.

14.11.76 AUD_OUT_CH_STR—Offset 62088h

Audio Channel ID and Stream ID

Access Method
Type: Memory Mapped I/O Register AUD_OUT_CH_STR: [GTTMMADR_LSB + 2BF20h] + 62088h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DIGITAL_DISPLAY_AUDIO_INDEX_PORTD

HDMI_INDEX_PORTB
RESERVED

CONVERTER_CHANNEL_MAP_PORTD

HDMI_INDEX_PORTC

CONVERTER_CHANNEL_MAP_PORTB
CONVERTER_CHANNEL_MAP_PORTC

Bit Default &

Description
Range Access

0b
31:24 RESERVED: Project: All Format:
RO

0b CONVERTER_CHANNEL_MAP_PORTD: Project: All The number in this field reflects

23:20 the HD audio channel to which the Digital Display Audio channel in bits 19:16 is
RO mapped. This field is read only

DIGITAL_DISPLAY_AUDIO_INDEX_PORTD: Project: All This field is the Digital

0b Display Audio channel number. When these bits are written, the audio channel number
19:16
RO assigned to the Digital Display Audio channel number are reflected in bits 20:23 of this
register.

Bay Trail-I SoC

594 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

0b CONVERTER_CHANNEL_MAP_PORTC: Project: All The number in this field reflects

15:12 the HD audio channel to which the Digital Display Audio channel in bits 11:8 is mapped.
RO This field is read only

0b HDMI_INDEX_PORTC: Project: All This field is the Digital Display Audio channel
11:8 number. When these bits are written, the audio channel number assigned to the Digital
RO Display Audio channel number are reflected in bits 12:15 of this register.

0b CONVERTER_CHANNEL_MAP_PORTB: Project: All The number in this field reflects

7:4 the HD audio channel to which the Digital Display Audio channel in bits 3:0 is mapped.
RO This field is read only

0b HDMI_INDEX_PORTB: Project: All This field is the Digital Display Audio channel
3:0 number. When these bits are written, the audio channel number assigned to the Digital
RO Display Audio channel number are reflected in bits 4:7 of this register.

14.11.77 AUD_PINW_CONNLNG_LIST—Offset 620A8h

Audio Connection List

Access Method
Type: Memory Mapped I/O Register AUD_PINW_CONNLNG_LIST: [GTTMMADR_LSB + 2BF20h] +
(Size: 32 bits) 620A8h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00030202h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0
RESERVED

CONNECTION_LIST_ENTRY

LONG_FORM

CONNECTION_LIST_LENGTH

Bit Default &

Description
Range Access

0b
31:24 RESERVED: Project: All Format:
RO
000000110
CONNECTION_LIST_ENTRY: Project: All Default Value: 0000001100000010b
23:8 0000010b
Connection to Convertor Widget Node 0x0302
RO

0b LONG_FORM: Project: All Default Value: 0b This bit indicates whether the items in the
7 connection list are long form or short form. This bit is hardwired to 0 (items in
RO connection list are short form)

CONNECTION_LIST_LENGTH: Project: All Default Value: 02h This field indicates the
10b number of items in the connection list. If this field is 2, there is only one hardwired input
6:0
RO possible, which is read from the Connection List, and there is no Connection Select
Control.

Bay Trail-I SoC

Datasheet 595
 Graphics, Video and Display

14.11.78 AUD_PINW_CONNLNG_SEL—Offset 620ACh

Audio Connection Select

Access Method
Type: Memory Mapped I/O Register AUD_PINW_CONNLNG_SEL: [GTTMMADR_LSB + 2BF20h] +
(Size: 32 bits) 620ACh

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CONNECTION_SELECT_CONTROL_D
RESERVED

CONNECTION_SELECT_CONTROL_B
CONNECTION_SELECT_CONTROL_C

Bit Default &

Description
Range Access

0b
31:24 RESERVED: Project: All Format:
RO
0b CONNECTION_SELECT_CONTROL_D: Project: All Format: Connection Index
23:16
RO Currently Set [Default 0x00], Port D Widget is set to 0x00

0b CONNECTION_SELECT_CONTROL_C: Project: All Format: Connection Index

15:8
RO Currently Set [Default 0x00], Port C Widget is set to 0x00

0b CONNECTION_SELECT_CONTROL_B: Project: All Format: Connection Index

7:0
RO Currently Set [Default 0x00], Port B Widget is set to 0x00

14.11.79 AUD_CNTL_ST_A—Offset 620B4h

Audio Control State Register Pipe A

Access Method
Type: Memory Mapped I/O Register AUD_CNTL_ST_A: [GTTMMADR_LSB + 2BF20h] + 620B4h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00005400h

Bay Trail-I SoC

596 Datasheet
Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0

DIP_PORT_SELECT

DIP_BUFFER_INDEX
RESERVED

DIP_TYPE_ENABLE_STATUS

DIP_TRANSMISSION_FREQUENCY

ELD_BUFFER_SIZE

ELD_ACCESS_ADDRESS

ELD_ACK

DIP_RAM_ACCESS_ADDRESS
RESERVED_1

RESERVED_2
Bit Default &
Description
Range Access

0b
31 RESERVED: Project: All Format: MBZ
RW

DIP_PORT_SELECT: Project: All AccessType: Read Only Default Value: 00b This read-
only bit reflects which port is used to transmit the DIP data. This can only change when
0b DIP is disabled. If one or more audio-related DIP packets is enabled and audio is
30:29
RO enabled on a digital port, these bits will reflect the digital port to which audio is directed.
Value Name Description Project 00b Reserved Reserved All 01b Digital Port B Digital Port
B All 10b Digital Port C Digital Port C All 11b Digital Port D Digital Port D All

0b
28:25 RESERVED_1: Project: All Format: MBZ
RW

DIP_TYPE_ENABLE_STATUS: Project: All AccessType: Read Only Default Value:

0000b These bits reflect the DIP types enabled. It can be updated while the port is
enabled. Within 2 vblank periods, the DIP is guaranteed to have been transmitted.
0b Disabling a DIP type results in setting the contents of that DIP buffer to zero. A reserved
24:21 setting reflects a disabled DIP. Value Name Description Project XXX0b Disable Audio DIP
RO disabled All XXX1b Enable Audio DIP enabled All XX0Xb Disable Generic 1 (ACP) DIP
disabled All XX1Xb Enable Generic 1 (ACP) DIP enabled All X0XXb Disable Generic 2 DIP
disabled All X1XXb Enable Generic 2 DIP enabled, can be used by ISRC1 or ISRC2 All
1XXXb Reserved Reserved All

DIP_BUFFER_INDEX: Project: All Default Value: 0000b This field is used during read
of different DIPs, and during read or write of ELD data. These bits are used as an index
to their respective DIP or ELD buffers. When the index is not valid, the contents of the
0b DIP will return all 0s. Value Name Description Project 000b Audio Audio DIP (31 bytes of
20:18 address space, 31 bytes of data) All 001b Gen 1 Generic 1 (ACP) Data Island Packet (31
RW bytes of address space, 31 bytes of data) All 010b Gen 2 Generic 2 (ISRC1) Data Island
Packet (31 bytes of address space, 31 bytes of data) All 011b Gen 3 Generic 3 (ISRC2)
Data Island Packet (31 bytes of address space, 31 bytes of data) All 1XXb Reserved
Reserved All
DIP_TRANSMISSION_FREQUENCY: Project: All AccessType: Read Only Default
Value: 00b These bits reflect the frequency of DIP transmission for the DIP buffer type
0b designated in bits 20:18. When writing DIP data, this value is also latched when the first
17:16 DW of the DIP is written. When read, this value reflects the DIP transmission frequency
RO for the DIP buffer designated in bits 20:18. Value Name Description Project 00b Disable
Disabled All 01b Reserved Reserved All 10b Send Once Send Once All 11b Best Effort
Best effort (Send at least every other vsync) All
0b
15 RESERVED_2: Project: All Format: MBZ
RW
10101b ELD_BUFFER_SIZE: Project: All AccessType: Read only 10101 = This field reflects the
14:10
RO size of the ELD buffer in DWORDs (84 Bytes of ELD)

Bay Trail-I SoC

Datasheet 597
 Graphics, Video and Display

Bit Default &

Description
Range Access

ELD_ACCESS_ADDRESS: Project: All Selects the DWORD address for access to the
0b ELD buffer (84 bytes). The value wraps back to zero when incremented past the max
9:5
RW addressing value 0x1F. This field change takes effect immediately after being written.
The read value indicates the current access address.
0b ELD_ACK: Project: All AccessType: Read Only Acknowledgement from the audio driver
4
RO that ELD read has been completed

DIP_RAM_ACCESS_ADDRESS: Project: All AccessType: Read Only Selects the

0b DWORD address for access to the DIP buffers. The value wraps back to zero when it
3:0
RO incremented past the max addressing value of 0xF. This field change takes effect
immediately after being written. The read value indicates the current access address.

14.11.80 AUD_CNTL_ST2—Offset 620C0h

Audio Control State 2

Access Method
Type: Memory Mapped I/O Register
AUD_CNTL_ST2: [GTTMMADR_LSB + 2BF20h] + 620C0h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ELD_VALIDD
RESERVED

CP_READYD

ELD_VALIDC
CP_READYC
RESERVED_1

RESERVED_2

ELD_VALIDB
CP_READYB
Bit Default &
Description
Range Access

0b
31:10 RESERVED: Project: All Format:
RW

CP_READYD: Project: All Default Value: 0b This R/W bit reflects the state of CP request
0b from the audio unit. When an audio CP request has been serviced, it must be reset to 1
9 by the video software to indicate that the CP request has been serviced. Value Name
RW Description Project 0b Pending or Not Ready CP request pending or not ready to receive
requests All 1b Ready CP request ready All
ELD_VALIDD: Project: All Default Value: 0b This R/W bit reflects the state of the ELD
data written to the ELD RAM. After writing the ELD data, the video software must set
0b this bit to 1 to indicate that the ELD data is valid. At audio codec initialization, or on a
8 hotplug event, this bit is set to 0 by the video software. This bit is reflected in the audio
RW pin complex widget as the ELD valid status bit. Value Name Description Project 0b
Invalid ELD data invalid (default, when writing ELD data, set 0 by software) All 1b Valid
ELD data valid (Set by video software only) All

0b
7:6 RESERVED_1: Project: All Format:
RW

0b CP_READYC: Project: All Default Value: 0b See CP_ReadyD description. Value Name
5 Description Project 0b Not Ready CP request pending or not ready to receive requests
RW All 1b Ready CP request ready All

Bay Trail-I SoC

598 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

0b ELD_VALIDC: Project: All Default Value: 0b See ELD_validD descripion. Value Name
4 Description Project 0b Invalid ELD data invalid (default, when writing ELD data, set 0 by
RW software) All 1b Valid ELD data valid (Set by video software only) All
0b
3:2 RESERVED_2: Project: All Format:
RW

0b CP_READYB: Project: All Default Value: 0b See CP_ReadyD description. Value Name
1 Description Project 0b Not Ready CP request pending or not ready to receive requests
RW All 1b Ready CP request ready All

0b ELD_VALIDB: Project: All Default Value: 0b See ELD_validD descripion. Value Name
0 Description Project 0b Invalid ELD data invalid (default, when writing ELD data, set 0 by
RW software) All 1b Valid ELD data valid (Set by video software only) All

14.11.81 AUD_HDMIW_STATUS—Offset 620D4h

Audio HDMI Status

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) AUD_HDMIW_STATUS: [GTTMMADR_LSB + 2BF20h] + 620D4h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CONV_B_CDCLK_DOTCLK_FIFO_UNDERRUN
CONV_B_CDCLK_DOTCLK_FIFO_OVERRUN
CONV_A_CDCLK_DOTCLK_FIFO_UNDERRUN
CONV_A_CDCLK_DOTCLK_FIFO_OVERRUN

BCLK_CDCLK_FIFO_OVERRUN
RESERVED

FUNCTION_RESET

RESERVED_1

Bit Default &

Description
Range Access

0b CONV_B_CDCLK_DOTCLK_FIFO_UNDERRUN: Project: All This bit indicates an

31 underrun in the FIFO inside the clock crossing logic between CDCLK and DOTCLK.
RW Clearing this status bit is accomplished by writing a 1 to this bit through MMIO.

0b CONV_B_CDCLK_DOTCLK_FIFO_OVERRUN: Project: All This bit indicates an

30 overrun in the FIFO inside the clock crossing logic between CDCLK and DOTCLK.
RW Clearing this status bit is accomplished by writing a 1 to this bit through MMIO.

Bay Trail-I SoC

Datasheet 599
 Graphics, Video and Display

Bit Default &

Description
Range Access

0b CONV_A_CDCLK_DOTCLK_FIFO_UNDERRUN: Project: All This bit indicates an

29 underrun in the FIFO inside the clock crossing logic between CDCLK and DOTCLK.
RW Clearing this status bit is accomplished by writing a 1 to this bit through MMIO.

0b CONV_A_CDCLK_DOTCLK_FIFO_OVERRUN: Project: All This bit indicates an

28 overrun in the FIFO inside the clock crossing logic between CDCLK and DOTCLK.
RW Clearing this status bit is accomplished by writing a 1 to this bit through MMIO.
0b
27:26 RESERVED: Project: All Format:
RW

0b BCLK_CDCLK_FIFO_OVERRUN: Project: All This bit indicates an overrun in the FIFO

25 inside the clock crossing logic between BCLK and CDCLK. Clearing this status bit is
RW accomplished by writing a 1 to this bit through MMIO.

0b FUNCTION_RESET: Project: All Security: Debug This bit indicates that an audio
24 function reset occurred through the reset signal on the HD audio bus. Clearing this
RW status bit is accomplished by writing a 1 to this bit through MMIO.
0b
23:0 RESERVED_1: Project: All Format:
RW

14.11.82 AUD_CONFIG_B—Offset 62100h

Audio Configuration Pipe B

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) AUD_CONFIG_B: [GTTMMADR_LSB + 2BF20h] + 62100h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PIXEL_CLOCK_HDMI

LOWER_N_VALUE_TESTMODE
RESERVED

N_PROGRAMMING_ENABLE_TESTMODE

DISABLE_NCTS

RESERVED_1
N_VALUE_INDEX

UPPER_N_VALUE_TESTMODE

Bit Default &

Description
Range Access

0b
31:30 RESERVED: Project: All Format:
RW

Bay Trail-I SoC

600 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

N_VALUE_INDEX: Project: All Default Value: 0b Value Name Description Project 0b

HDMI N value read on bits 27:20 and 15:4 reflects HDMI N value. Bits 27:20 and 15:4
0b are is programmable to any N value - default h7FA6. All 1b DP N value read on bits
29
RW 27:20 and 15:4 reflects DP N value. Set this bit to 1 before programming N value
register. When this is set to 1, 27:20 and 15:4 will reflect the current N value default
h8000. All
0b N_PROGRAMMING_ENABLE_TESTMODE: Project: All Security: Test See Pipe A
28
RW description.

0b
27:20 UPPER_N_VALUE_TESTMODE: Project: All Security: Test See Pipe A description
RW
PIXEL_CLOCK_HDMI: Project: All Default Value: 0b See Pipe A description. Value
Name Description Project 0000b 25.2 / 1.001 MHz 25.2 / 1.001 MHz All 0001b 25.2 MHz
0b 25.2 MHz Program this value for pixel clocks not listed in this field All 0010b 27 MHz 27
19:16 MHz All 0011b 27 * 1.001 MHz 27 * 1.001 MHz All 0100b 54 MHz 54 MHz All 0101b 54
RW * 1.001 MHz 54 * 1.001 MHz All 0110b 74.25 / 1.001 MHz 74.25 / 1.001 MHz All 0111b
74.25 MHz 74.25 MHz All 1000b 148.5 / 1.001 MHz 148.5 / 1.001 MHz All 1001b 148.5
MHz 148.5 MHz All others Reserved Reserved All
0b
15:4 LOWER_N_VALUE_TESTMODE: Project: All Security: Test See Pipe A description
RW
0b
3 DISABLE_NCTS: Project: All See Pipe A description
RW
0b
2:0 RESERVED_1: Project: All Format:
RW

14.11.83 AUD_MISC_CTRL_B—Offset 62110h

Audio MISC Control for Pipe B

Access Method
Type: Memory Mapped I/O Register AUD_MISC_CTRL_B: [GTTMMADR_LSB + 2BF20h] + 62110h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000044h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0
SAMPLE_PRESENT_DISABLE

OUTPUT_DELAY

PRO_ALLOWED
RESERVED

SAMPLE_FABRICATION_EN_BIT
RESERVED_1

RESERVED_2

Bay Trail-I SoC

Datasheet 601
 Graphics, Video and Display

Bit Default &

Description
Range Access

0b
31:9 RESERVED: Project: All Format: MBZ
RW
0b
8 SAMPLE_PRESENT_DISABLE: Project: All Security: Debug See Pipe A description
RW
0100b
7:4 OUTPUT_DELAY: Project: All Default Value: 0100b See Pipe A description.
RW
0b
3 RESERVED_1: Project: All Format: MBZ
RW

1b SAMPLE_FABRICATION_EN_BIT: Project: All Access: R/W Default Value: ;1b See

2 Pipe A description. Value Name Description Project 0b Disable Audio fabrication disabled
RW All 1b Enable Audio fabrication enabled All

0b PRO_ALLOWED: Project: All Access: R/W Default Value: 0b See Pipe A description.
1 Value Name Description Project 0b Consumer Consumer use only All 1b Professional
RW Professional use allowed All
0b
0 RESERVED_2: All Format: MBZ
RW

14.11.84 AUD_CTS_ENABLE_B—Offset 62128h

Audio CTS Programming Enable Pipe B

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) AUD_CTS_ENABLE_B: [GTTMMADR_LSB + 2BF20h] + 62128h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENABLE_CTS_OR_M_PROGRAMMING

CTS_PROGRAMMING
CTS_M_VALUE_INDEX
RESERVED

Bit Default &

Description
Range Access

0b
31:22 RESERVED: Project: All Format:
RW

Bay Trail-I SoC

602 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

CTS_M_VALUE_INDEX: Project: All Default Value: 0b Value Name Description Project

0b 0b CTS CTS value read on bits 23:4 reflects CTS value. Bit 23:4 is programmable to any
21 CTS value. default is 0 All 1b M M value read on bits 21:4 reflects DP M value. Set this
RW bit to 1 before programming M value register. When this is set to 1 23:4 will reflect the
current N value All

0b
20 ENABLE_CTS_OR_M_PROGRAMMING: Project: All See Pipe A description.
RW

0b
19:0 CTS_PROGRAMMING: Project: All See Pipe A description.
RW

14.11.85 AUD_HDMIW_HDMIEDID_B—Offset 62150h

HDMI Data EDID Block Pipe B

Access Method
Type: Memory Mapped I/O Register AUD_HDMIW_HDMIEDID_B: [GTTMMADR_LSB + 2BF20h] +
(Size: 32 bits) 62150h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EDID_HDMI_DATA_BLOCK

Bit Default &

Description
Range Access

0b
31:0 EDID_HDMI_DATA_BLOCK: Project: All Format: See Pipe A description
RW

14.11.86 AUD_HDMIW_INFOFR_B—Offset 62154h

Audio Widget Data Island Packet Pipe B

Access Method
Type: Memory Mapped I/O Register AUD_HDMIW_INFOFR_B: [GTTMMADR_LSB + 2BF20h] +
(Size: 32 bits) 62154h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

Datasheet 603
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DATA_ISLAND_PACKET_DATA
Bit Default &
Description
Range Access

0b
31:0 DATA_ISLAND_PACKET_DATA: Project: All Format: See Pipe A description.
RO

14.11.87 AUD_OUT_DIG_CNVT_B—Offset 62180h

Audio Digital Converter Conv B

Access Method
Type: Memory Mapped I/O Register AUD_OUT_DIG_CNVT_B: [GTTMMADR_LSB + 2BF20h] +
(Size: 32 bits) 62180h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
STREAM_ID

LOWEST_CHANNEL_NUMBER

RESERVED_1

RESERVED_2
CATEGORY_CODE

LEVEL

NON_AUDIO
RESERVED

PRO

COPY
PRE

V
VCFG

Bit Default &

Description
Range Access

0b
31:24 RESERVED: Project: All Format:
RO

0b
23:20 STREAM_ID: Project: All Format: See Conv A description.
RO

0b
19:16 LOWEST_CHANNEL_NUMBER: Project: All Format: See Conv A description
RO

Bay Trail-I SoC

604 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

0b
15 RESERVED_1: Project: All Format:
RO
0b
14:8 CATEGORY_CODE: Project: All Format: See Conv A description
RO
0b
7 LEVEL: Project: All Format: See Conv A description
RO
0b PRO: Project: All Default Value: 0b See Conv A description Value Name Description
6
RO Project 0b Consumer Consumer use All 1b Professional Professional use All

0b NON_AUDIO: Project: All Default Value: 0b See Conv A description. Value Name
5
RO Description Project 0b PCM Data is PCM All 1b Non PCM Data is non PCM format All

0b COPY: Project: All Default Value: 0b See Conv A description Value Name Description
4 Project 0b Not Asserted Copyright is not asserted All 1b Asserted Copyright is asserted
RO All

0b PRE: Project: All Default Value: 0b See Conv A description Value Name Description
3 Project 0b Disabled Preemphasis is disabled All 1b Enabled Filter preemphasis is enabled
RO All
0b
2 VCFG: Project: All Format: See Conv A description
RO
0b
1 V: Project: All Format: See Conv A description
RO
0b
0 RESERVED_2: All Format: MBZ
RO

14.11.88 AUD_OUT_STR_DESC_B—Offset 62184h

Audio Stream Descriptor Format Conv B

Access Method
Type: Memory Mapped I/O Register AUD_OUT_STR_DESC_B: [GTTMMADR_LSB + 2BF20h] +
(Size: 32 bits) 62184h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000032h

Bay Trail-I SoC

Datasheet 605
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0

SAMPLE_BASE_RATE_DIVISOR
SAMPLE_BASE_RATE
RESERVED

HBR_ENABLE

BITS_PER_SAMPLE
CONVERTOR_CHANNEL_COUNT

SAMPLE_BASE_RATE_MULT
RESERVED_1

RESERVED_2

RESERVED_3

NUMBER_OF_CHANNELS_IN_A_STREAM
Bit Default &
Description
Range Access

0b
31:29 RESERVED: Project: All Format:
RO
0b
28:27 HBR_ENABLE: Project: All Format: See Conv A description.
RO
0b
26:21 RESERVED_1: Project: All Format:
RO
0b
20:16 CONVERTOR_CHANNEL_COUNT: Project: All Format: See Conv A description.
RO
0b
15 RESERVED_2: Project: All Format:
RO
0b SAMPLE_BASE_RATE: Project: All Default Value: 0b 48 kHz See Conv A description.
14
RO Value Name Description Project 0b 48 kHz 48 kHz All 1b 44.1 kHz 44.1 kHz All

SAMPLE_BASE_RATE_MULT: Project: All Default Value: 000b 48 kHz See Conv A

0b description. Value Name Description Project 000b x1 x1 (48 kHz/44.1 kHz or less) All
13:11
RO 001b x2 x2 (96 kHz, 88.2 kHz, 32 kHz) All 010b x3 x3 (144 kHz) All 011b x4 x4 (192
kHz, 176.4 kHz) All 1XXb Reserved Reserved All
SAMPLE_BASE_RATE_DIVISOR: Project: All Default Value: 000b 48 kHz See Conv A
description. Value Name Description Project 000b Div 1 Divide by 1 (48 kHz, 44.1 kHz)
0b All 001b Div 2 Divide by 2 (24 kHz, 22.05 kHz) All 010b Div 3 Divide by 3 (16 kHz, 32
10:8
RO kHz) All 011b Div 4 Divide by 4 (11.025 kHz) All 100b Div 5 Divide by 5 (9.6 kHz) All
101b Div 6 Divide by 6 (8 kHz) All 110b Div 7 Divide by 7 All 111b Div 8 Divide by 8 (6
kHz) All
0b
7 RESERVED_3: Project: All Format: MBZ
RO
BITS_PER_SAMPLE: Project: All Default Value: 011b 32 bits Value Name Description
Project 000b 8 bit The data will be packed in memory in 8 bit containers on 16 bit
011b boundaries All 001b 16 bits The data will be packed in memory in 16 bit containers on
6:4 16 bit boundaries All 100b 20 bits The data will be packed in memory in 20 bit
RO containers on 32 bit boundaries All 010b 24 bits The data will be packed in memory in
24 bit containers on 32 bit boundaries All 011b 32 bits The data will be packed in
memory in 32 bit containers on 32 bit boundaries All others Res. Reserved All

0010b NUMBER_OF_CHANNELS_IN_A_STREAM: Project: All Default Value: 0010b 3

3:0 channels in each frame Format: U4+1 Binary value plus 1. 0000 = 1, 1111= 16 See
RO Conv A description.

Bay Trail-I SoC

606 Datasheet
Graphics, Video and Display

14.11.89 AUD_CNTL_ST_B—Offset 621B4h

Audio Control State Register Pipe B

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) AUD_CNTL_ST_B: [GTTMMADR_LSB + 2BF20h] + 621B4h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00005400h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0

DIP_BUFFER_INDEX

DIP_RAM_ACCESS_ADDRESS
RESERVED_1

DIP_TYPE_ENABLE_STATUS

RESERVED_2

ELD_ACCESS_ADDRESS
RESERVED

DIP_PORT_SELECT

DIP_TRANSMISSION_FREQUENCY

ELD_BUFFER_SIZE

ELD_ACK
Bit Default &
Description
Range Access

0b
31 RESERVED: Project: All Format: MBZ
RW

0b DIP_PORT_SELECT: Project: All AccessType: Read Only Default Value: 00b See Pipe A
30:29 description. Value Name Description Project 00b Reserved Reserved All 01b Digital Port
RO B Digital Port B All 10b Digital Port C Digital Port C All 11b Digital Port D Digital Port D All
0b
28:25 RESERVED_1: Project: All Format: MBZ
RW
DIP_TYPE_ENABLE_STATUS: Project: All AccessType: Read Only Default Value:
0000b See Pipe A description. Value Name Description Project XXX0b Disable Audio DIP
0b disabled (Default) All XXX1b Enable Audio DIP enabled All XX0Xb Disable Generic 1
24:21
RO (ACP) DIP disabled All XX1Xb Enable Generic 1 (ACP) DIP enabled All X0XXb Disable
Generic 2 DIP disabled All X1XXb Enable Generic 2 DIP enabled, can be used by ISRC1
or ISRC2 All 1XXXb Reserved Reserved All
DIP_BUFFER_INDEX: Project: All Default Value: 000b See Pipe A description. Value
Name Description Project 000b Audio Audio DIP (31 bytes of address space, 31 bytes of
0b data) All 001b Gen 1 Generic 1 (ACP) Data Island Packet (31 bytes of address space, 11
20:18
RW bytes of data) All 010b Gen 2 Generic 2 (ISRC1) Data Island Packet (31 bytes of address
space, 31 bytes of data) All 011b Gen 3 Generic 3 (ISRC2) Data Island Packet (31 bytes
of address space, 31 bytes of data) All 1XXb Reserved Reserved All
DIP_TRANSMISSION_FREQUENCY: Project: All AccessType: Read Only Default
0b Value: 00b See Pipe A description Value Name Description Project 00b Disable Disabled
17:16
RO All 01b Reserved Reserved All 10b Send Once Send Once All 11b Best Effort Best effort
(Send at least every other vsync) All

0b
15 RESERVED_2: Project: All Format: MBZ
RW

10101b ELD_BUFFER_SIZE: Project: All AccessType: Read Only 10101 = This field reflects the
14:10
RO size of the ELD buffer in DWORDs (84 Bytes of ELD)

Bay Trail-I SoC

Datasheet 607
 Graphics, Video and Display

Bit Default &

Description
Range Access

0b
9:5 ELD_ACCESS_ADDRESS: Project: All See Pipe A description.
RW
0b
4 ELD_ACK: Project: All AccessType: Read Only See Pipe A description.
RO
0b DIP_RAM_ACCESS_ADDRESS: Project: All AccessType: Read only See Pipe A
3:0
RO description.

14.11.90 AUD_SSID_DBG—Offset 62F00h

audio SSID debug

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) AUD_SSID_DBG: [GTTMMADR_LSB + 2BF20h] + 62F00h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 80860101h
31 28 24 20 16 12 8 4 0

1 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1
SUB_SYSTEM_ID

Bit Default &

Description
Range Access

100000001
000011000
31:0 000001000 SUB_SYSTEM_ID: Project: All
00001b
WO

14.11.91 AUD_PWST1_DBG—Offset 62F04h

audion pwst1 debug

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) AUD_PWST1_DBG: [GTTMMADR_LSB + 2BF20h] + 62F04h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000C0Fh

Bay Trail-I SoC

608 Datasheet
Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 1 1

RESERVED

CONVERTORA_WIDGET_POWER_STATE
FUNCTION_GROUP_DEVICE_POWER_STATE

RESERVED_1

PINB_WIDGET_POWER_STATE
Bit Default &
Description
Range Access

0b
31:12 RESERVED: Project: All Format: MBZ
WO

11b FUNCTION_GROUP_DEVICE_POWER_STATE: Project: All Default Value: ;11b D3

11:10 Power state that was set Value Name Description Project 00b D0 D0 All 01b, 10b
WO Unsupported Unsupported All 11b D3 D3 (Default)
0b
9:4 RESERVED_1: Project: All Format: MBZ
WO

11b CONVERTORA_WIDGET_POWER_STATE: Project: All Default Value: ;11b D3 Power

3:2 state that was requested by audio software Value Name Description Project 00b D0 D0
WO All 01b, 10b Unsupported Unsupported All 11b D3 D3 (Default)

11b PINB_WIDGET_POWER_STATE: Project: All Default Value: ;11b D3 Power state that
1:0 was set Value Name Description Project 00b D0 D0 All 01b, 10b Unsupported
WO Unsupported All 11b D3 D3 (Default)

14.11.92 AUD_OUT_STR_DESC_A_DBG—Offset 62F08h

These values are returned from the device as the Stream Descriptor Format response
to a Get Audio Output Converter Widget command.

Access Method
Type: Memory Mapped I/O Register AUD_OUT_STR_DESC_A_DBG: [GTTMMADR_LSB + 2BF20h] +
(Size: 32 bits) 62F08h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000032h

Bay Trail-I SoC

Datasheet 609
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0

SAMPLE_BASE_RATE_DIVISOR
SAMPLE_BASE_RATE
RESERVED

HBR_ENABLE

BITS_PER_SAMPLE
CONVERTOR_CHANNEL_COUNT

SAMPLE_BASE_RATE_MULT
RESERVED_1

RESERVED_2

RESERVED_3

NUMBER_OF_CHANNELS_IN_A_STREAM
Bit Default &
Description
Range Access

0b
31:29 RESERVED: Project: All Format: MBZ
WO
0b
28:27 HBR_ENABLE: Project: All This reflects the current HBR settings
WO
0b
26:22 RESERVED_1: Project: All Format: MBZ
WO
0b CONVERTOR_CHANNEL_COUNT: Project: All This reflects the Convertor Channel
21:16
WO Count programmed through HDAudio.

0b
15 RESERVED_2: Project: All Format: MBZ
WO

0b SAMPLE_BASE_RATE: Project: All Default Value: 0b (48 KHz) Sampling base rate of
14 audio stream Value Name Description Project 0b 48 kHz 48 kHz All 1b 44.1 kHz 44.1
WO kHz All
SAMPLE_BASE_RATE_MULT: Project: All Default Value: 000b (48 KHz) Audio stream
0b sample base rate multiple Value Name Description Project 000b 1x 48 kHz/44.1 kHz or
13:11
WO less All 001b 2x x2 (96 kHz, 88.2 kHz, 32 kHz) All 010b 3x x3 (144 kHz) All 011b 4x x4
(192 kHz, 176.4 kHz) All 1XXb Reserved Reserved
SAMPLE_BASE_RATE_DIVISOR: Project: All Default Value: 000b (indicates divide by
1 which results in 48 KHz) Audio stream sample base rate divisor Value Name
0b Description Project 000b Divide by 1 Divide by 1 (48 kHz, 44.1 kHz) All 001b Divide by
10:8 2 Divide by 2 (24 kHz, 22.05 kHz) All 010b Divide by 3 Divide by 3 (16 kHz, 32 kHz) All
WO 011b Divide by 4 Divide by 4 (11.025 kHz) All 100b Divide by 5 Divide by 5 (9.6 kHz) All
101b Divide by 6 Divide by 6 (8 kHz) All 110b Divide by 7 Divide by 7 All 111b Divide by
Divide by 8 (6 kHz) All
0b
7 RESERVED_3: Project: All Format: MBZ
WO
BITS_PER_SAMPLE: Project: All Default Value: 011b (Indicates 24 bits) Audio stream
sample base rate multiple Value Name Description Project 000b 8 bits The data will be
packed in memory in 8 bit containers on 16 bit boundaries All 001b 16 bits The data will
011b be packed in memory in 16 bit containers on 16 bit boundaries All 010b 24 bits The data
6:4
WO will be packed in memory in 32 bit containers on 32 bit boundaries All 011b 32 bits The
data will be packed in memory in 32 bit containers on 32 bit boundaries All 100b 20 bits
The data will be packed in memory in 32 bit containers on 32 bit boundaries All Others
Reserved Reserved
0010b NUMBER_OF_CHANNELS_IN_A_STREAM: Project: All Format: U4+1 Default Value:
3:0
WO 0010b (3 channels in each frame) Number of channels in each frame of the stream

Bay Trail-I SoC

610 Datasheet
Graphics, Video and Display

14.11.93 AUD_OUT_DIG_CNVT_A_DBG—Offset 62F0Ch

These values are returned from the device as the Digital Converter response to a Get
Audio Output Converter Widget command.

Access Method
Type: Memory Mapped I/O Register AUD_OUT_DIG_CNVT_A_DBG: [GTTMMADR_LSB + 2BF20h] +
(Size: 32 bits) 62F0Ch

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000001h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

LOWEST_CHANNEL_NUMBER
STREAM_ID

LEVEL

DIGEN
RESERVED_1

NON_AUDIO
RESERVED

CATEGORY_CODE

PRO

COPY
PRE

V
VCFG
Bit Default &
Description
Range Access

0b
31:24 RESERVED: Project: All Format: MBZ
WO

0b STREAM_ID: Project: All Represents the link stream used by the converter for data
23:20 input or output. This value is set in the Channel ID and Stream ID through the Set Audio
WO Output Converter Widget command. Default = 0 (stream 0)

0b LOWEST_CHANNEL_NUMBER: Project: All Represents the lowest channel used by the

19:16 converter. This value is set in the Channel ID and Stream ID through the Set Audio
WO Output Converter Widget command. Default = 0

0b
15 RESERVED_1: Project: All Format: MBZ
WO

0b CATEGORY_CODE: Project: All S/PDIF IEC Category Code. This value is set in the
14:8 Digital Converter 1 through the Set Audio Output Converter Widget command. Default =
WO 0

0b LEVEL: Project: All S/PDIF IEC Generation Level. This value is set in the Digital
7
WO Converter 2 through the Set Audio Output Converter Widget command. Default = 0

PRO: Project: All This bit indicates professional or consumer use of channel. This value
0b is set in the Digital Converter 2 through the Set Audio Output Converter Widget
6 command. This value can only be set to 1 if the Pro Allowed bit is set in the audio
WO configuration register. Value Name Description Project 0b Consumer Consumer use.
Default (Consumer) All 1b Professional Professional use All
NON_AUDIO: Project: All Data is non PCM format. This value is set in the Digital
0b Converter 2 through the Set Audio Output Converter Widget command. Value Name
5
WO Description Project 0b PCM Data is PCM (Default) All 1b Non-PCM Data is non PCM
format All

Bay Trail-I SoC

Datasheet 611
 Graphics, Video and Display

Bit Default &

Description
Range Access

COPY: Project: All Copyright asserted. This value is set in the Digital Converter 2
0b through the Set Audio Output Converter Widget command. Value Name Description
4
WO Project 0b Not Asserted Copyright is not asserted All 1b Asserted Copyright is asserted
All

0b PRE: Project: All Filter preemphasis. This value is set in the Digital Converter 2 through
3 the Set Audio Output Converter Widget command. Value Name Description Project 0b
WO None Pre-emphasis is non All 1b Enabled Filter pre-emphasis is enabled All

0b VCFG: Project: All Validity Configuration. Determines S/PDIF transmitter behavior when
2 data is not being transmitted. This value is set in the Digital Converter 2 through the Set
WO Audio Output Converter Widget command. Default = 0
V: Project: All Affects the validity flag transmitted in each subframe, and enables the S/
0b PDIF transmitter to maintain connection during error or mute conditions. This value is
1
WO set in the Digital Converter 2 through the Set Audio Output Converter Widget command.
Default = 0

DIGEN: All Filter preemphasis. This value is set in the Digital Converter 2 through the
1b Set Audio Output Converter Widget command. Value Name Description Project 0b
0
WO Blocked Digital data is blocked from passing through the node, regardless of the state
All 1b Passed Digital data can pass through the node (Default = 1, enabled) All

14.11.94 AUD_PWST2_DBG—Offset 62F14h

audio pwst2 debug

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) AUD_PWST2_DBG: [GTTMMADR_LSB + 2BF20h] + 62F14h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 0000000Fh
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1

CONVERTORB_WIDGET_POWER_STATE
RESERVED

PINC_WIDGET_POWER_STATE

Bit Default &

Description
Range Access

0b
31:4 RESERVED: Project: All Format: MBZ
WO

Bay Trail-I SoC

612 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

11b CONVERTORB_WIDGET_POWER_STATE: Project: All Default Value: ;11b D3 Power

3:2 state that was requested by audio software Value Name Description Project 00b D0 D0
WO All 01b, 10b Unsupported Unsupported All 11b D3 D3 (Default)

11b PINC_WIDGET_POWER_STATE: Project: All Default Value: ;11b D3 Power state that
1:0 was set Value Name Description Project 00b D0 D0 All 01b, 10b Unsupported
WO Unsupported All 11b D3 D3 (Default)

14.11.95 AUD_OUT_STR_DESC_B_DBG—Offset 62F18h

HDAudio Verb: Converter Widget 2/72D These values are returned from the device as
the Stream Descriptor Format response to a Get Audio Output Converter Widget
command.

Access Method
Type: Memory Mapped I/O Register AUD_OUT_STR_DESC_B_DBG: [GTTMMADR_LSB + 2BF20h] +
(Size: 32 bits) 62F18h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000032h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0

SAMPLE_BASE_RATE_DIVISOR

NUMBER_OF_CHANNELS_IN_A_STREAM
RESERVED_1

RESERVED_2

SAMPLE_BASE_RATE_MULT

RESERVED_3
RESERVED

BITS_PER_SAMPLE
SAMPLE_BASE_RATE
HBR_ENABLE

CONVERTOR_CHANNEL_COUNT

Bit Default &

Description
Range Access

0b
31:29 RESERVED: Project: All Format: MBZ
WO
0b
28:27 HBR_ENABLE: Project: All This reflects the current HBR settings
WO
0b
26:22 RESERVED_1: Project: All Format: MBZ
WO
0b CONVERTOR_CHANNEL_COUNT: Project: All This reflects the Convertor Channel
21:16
WO Count programmed through HDAudio.

0b
15 RESERVED_2: Project: All Format: MBZ
WO

Bay Trail-I SoC

Datasheet 613
 Graphics, Video and Display

Bit Default &

Description
Range Access

0b SAMPLE_BASE_RATE: Project: All Default Value: 0b (48 KHz) Sampling base rate of
14 audio stream Value Name Description Project 0b 48 kHz 48 kHz All 1b 44.1 kHz 44.1
WO kHz All
SAMPLE_BASE_RATE_MULT: Project: All Default Value: 000b (48 KHz) Audio stream
0b sample base rate multiple Value Name Description Project 000b 1x 48 kHz/44.1 kHz or
13:11
WO less All 001b 2x x2 (96 kHz, 88.2 kHz, 32 kHz) All 010b 3x x3 (144 kHz) All 011b 4x x4
(192 kHz, 176.4 kHz) All 1XXb Reserved Reserved
SAMPLE_BASE_RATE_DIVISOR: Project: All Default Value: 000b (indicates divide by
1 which results in 48 KHz) Audio stream sample base rate divisor Value Name
0b Description Project 000b Divide by 1 Divide by 1 (48 kHz, 44.1 kHz) All 001b Divide by
10:8 2 Divide by 2 (24 kHz, 22.05 kHz) All 010b Divide by 3 Divide by 3 (16 kHz, 32 kHz) All
WO 011b Divide by 4 Divide by 4 (11.025 kHz) All 100b Divide by 5 Divide by 5 (9.6 kHz) All
101b Divide by 6 Divide by 6 (8 kHz) All 110b Divide by 7 Divide by 7 All 111b Divide by
Divide by 8 (6 kHz) All

0b
7 RESERVED_3: Project: All Format: MBZ
WO

BITS_PER_SAMPLE: Project: All Default Value: 011b (Indicates 24 bits) Audio stream
sample base rate multiple Value Name Description Project 000b 8 bits The data will be
packed in memory in 8 bit containers on 16 bit boundaries All 001b 16 bits The data will
011b be packed in memory in 16 bit containers on 16 bit boundaries All 010b 24 bits The data
6:4
WO will be packed in memory in 32 bit containers on 32 bit boundaries All 011b 32 bits The
data will be packed in memory in 32 bit containers on 32 bit boundaries All 100b 20 bits
The data will be packed in memory in 32 bit containers on 32 bit boundaries All Others
Reserved Reserved
0010b NUMBER_OF_CHANNELS_IN_A_STREAM: Project: All Format: U4+1 Default Value:
3:0
WO 0010b (3 channels in each frame) Number of channels in each frame of the stream

14.11.96 AUD_OUT_DIG_CNVT_B_DBG—Offset 62F1Ch

HDAudio Verb: Converter Widget 70D/70E/73E/73F/706 These values are returned
from the device as the Digital Converter response to a Get Audio Output Converter
Widget command.

Access Method
Type: Memory Mapped I/O Register AUD_OUT_DIG_CNVT_B_DBG: [GTTMMADR_LSB + 2BF20h] +
(Size: 32 bits) 62F1Ch

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000001h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
LOWEST_CHANNEL_NUMBER

CATEGORY_CODE

LEVEL

NON_AUDIO
RESERVED

STREAM_ID

PRO

COPY
PRE

V
RESERVED_1

VCFG

DIGEN

Bay Trail-I SoC

614 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

0b
31:24 RESERVED: Project: All Format: MBZ
WO

0b STREAM_ID: Project: All Represents the link stream used by the converter for data
23:20 input or output. This value is set in the Channel ID and Stream ID through the Set Audio
WO Output Converter Widget command. Default = 0 (stream 0)

0b LOWEST_CHANNEL_NUMBER: Project: All Represents the lowest channel used by the

19:16 converter. This value is set in the Channel ID and Stream ID through the Set Audio
WO Output Converter Widget command. Default = 0
0b
15 RESERVED_1: Project: All Format: MBZ
WO

0b CATEGORY_CODE: Project: All S/PDIF IEC Category Code. This value is set in the
14:8 Digital Converter 1 through the Set Audio Output Converter Widget command. Default =
WO 0
0b LEVEL: Project: All S/PDIF IEC Generation Level. This value is set in the Digital
7
WO Converter 2 through the Set Audio Output Converter Widget command. Default = 0

PRO: Project: All This bit indicates professional or consumer use of channel. This value
0b is set in the Digital Converter 2 through the Set Audio Output Converter Widget
6 command. This value can only be set to 1 if the Pro Allowed bit is set in the audio
WO configuration register. Value Name Description Project 0b Consumer Consumer use.
Default (Consumer) All 1b Professional Professional use All
NON_AUDIO: Project: All Data is non PCM format. This value is set in the Digital
0b Converter 2 through the Set Audio Output Converter Widget command. Value Name
5
WO Description Project 0b PCM Data is PCM (Default) All 1b Non-PCM Data is non PCM
format All
COPY: Project: All Copyright asserted. This value is set in the Digital Converter 2
0b through the Set Audio Output Converter Widget command. Value Name Description
4
WO Project 0b Not Asserted Copyright is not asserted All 1b Asserted Copyright is asserted
All

0b PRE: Project: All Filter preemphasis. This value is set in the Digital Converter 2 through
3 the Set Audio Output Converter Widget command. Value Name Description Project 0b
WO None Pre-emphasis is non All 1b Enabled Filter pre-emphasis is enabled All

0b VCFG: Project: All Validity Configuration. Determines S/PDIF transmitter behavior when
2 data is not being transmitted. This value is set in the Digital Converter 2 through the Set
WO Audio Output Converter Widget command. Default = 0

V: Project: All Affects the validity flag transmitted in each subframe, and enables the S/
0b PDIF transmitter to maintain connection during error or mute conditions. This value is
1
WO set in the Digital Converter 2 through the Set Audio Output Converter Widget command.
Default = 0
DIGEN: All Filter preemphasis. This value is set in the Digital Converter 2 through the
1b Set Audio Output Converter Widget command. Value Name Description Project 0b
0
WO Blocked Digital data is blocked from passing through the node, regardless of the state
All 1b Passed Digital data can pass through the node (Default = 1, enabled) All

14.11.97 AUD_PORT_EN_B_DBG—Offset 62F20h

HDAudio Verb: PinWidget 707/3/734/701 These values are returned from the device as
the Digital Converter response to a Get Audio Output Converter Widget command.

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) AUD_PORT_EN_B_DBG: [GTTMMADR_LSB + 2BF20h] + 62F20h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Bay Trail-I SoC

Datasheet 615
 Graphics, Video and Display

Default: 00000003h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1

CONNECTION_SELECT_CONTROL_B

CONVERTER_CHANNEL_MAP_PORT_B

PORT_B_AMP_MUTE_STATUS
RESERVED

PORT_B_OUT_ENABLE
INDEX_2_0

HDMI_INDEX_PORT_B
TAG_7_3

MLP_STREAM
Bit Default &
Description
Range Access

0b TAG_7_3: Project: All This represents the SSID that will go in the lower 5 bits of the
31:27
WO SSID

0b INDEX_2_0: Project: All This is used as a pointer to program multiple SSID (only 0 is
26:24
WO supported for Cantiga)

0b CONNECTION_SELECT_CONTROL_B: Access Read Only Project: All This is used as a

23:16
WO pointer to program multiple SSID (only 0 is supported for Cantiga)

0b CONVERTER_CHANNEL_MAP_PORT_B: Access Read Only Project: All The number in

15:12 this field reflects the HD audio channel to which the HDMI channel is mapped. This field
WO is read only

0b HDMI_INDEX_PORT_B: Project: All This is used as a pointer to program multiple

11:8
WO SSID (only 0 is supported for Cantiga)

0b
7:5 RESERVED: Project: All Format: MBZ
WO

0b MLP_STREAM: Project: All Default Value: 000b Default Value Name Description Project
4:2
WO 000b Default Default All 011b MLP Stream MLP Stream All Others Reserved Reserved All

PORT_B_AMP_MUTE_STATUS: Access Read Only Project: All Project: All Default

1b Value: ;1b Amp muted This read-only bit reflects the mute status of the amplifier Value
1
WO Name Description Project 0b Amp not muted Amp not muted All 1b Amp muted Amp
muted All
1b PORT_B_OUT_ENABLE: All This bit reflects the state of the output path of the Pin
0
WO Widget. When 0, audio is disabled . Default = 1

14.11.98 AUD_PWST3_DBG—Offset 62F24h

HDAudio Verb: Pin Widget 705

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) AUD_PWST3_DBG: [GTTMMADR_LSB + 2BF20h] + 62F24h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000003h

Bay Trail-I SoC

616 Datasheet
Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1

RESERVED

PIND_WIDGET_POWER_STATE
Bit Default &
Description
Range Access

0b
31:2 RESERVED: Project: All Format: MBZ
WO

11b PIND_WIDGET_POWER_STATE: Project: All Default Value: ;11b D3 Power state that
1:0 was set Value Name Description Project 00b D0 D0 All 01b, 10b Unsupported
WO Unsupported All 11b D3 D3 (Default)

14.11.99 AUD_PORT_EN_C_DBG—Offset 62F28h

HDAudio Verb: PinWidget 707/3/734/701 These values are returned from the device as
the Digital Converter response to a Get Audio Output Converter Widget command.

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) AUD_PORT_EN_C_DBG: [GTTMMADR_LSB + 2BF20h] + 62F28h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000003h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
CONNECTION_SELECT_CONTROL_C

MLP_STREAM
TAG_7_3

INDEX_2_0

CONVERTER_CHANNEL_MAP_PORT_C

HDMI_INDEX_PORT_C

PORT_C_AMP_MUTE_STATUS
RESERVED

PORT_C_OUT_ENABLE

Bay Trail-I SoC

Datasheet 617
 Graphics, Video and Display

Bit Default &

Description
Range Access

0b TAG_7_3: Project: All This represents the SSID that will go in the lower 5 bits of the
31:27
WO SSID

0b INDEX_2_0: Project: All This is used as a pointer to program multiple SSID (only 0 is
26:24
WO supported for Cantiga)

0b CONNECTION_SELECT_CONTROL_C: Access Read Only Project: All This is used as a

23:16
WO pointer to program multiple SSID (only 0 is supported for Cantiga)

0b CONVERTER_CHANNEL_MAP_PORT_C: Access Read Only Project: All The number in

15:12 this field reflects the HD audio channel to which the HDMI channel is mapped. This field
WO is read only
0b HDMI_INDEX_PORT_C: Project: All This is used as a pointer to program multiple
11:8
WO SSID (only 0 is supported for Cantiga)

0b
7:5 RESERVED: Project: All Format: MBZ
WO
0b MLP_STREAM: Project: All Default Value: 000b Default Value Name Description Project
4:2
WO 000b Default Default All 011b MLP Stream MLP Stream All Others Reserved Reserved All

PORT_C_AMP_MUTE_STATUS: Access Read Only Project: All Project: All Default

1b Value: ;1b Amp muted This read-only bit reflects the mute status of the amplifier Value
1
WO Name Description Project 0b Amp not muted Amp not muted All 1b Amp muted Amp
muted All

1b PORT_C_OUT_ENABLE: All This bit reflects the state of the output path of the Pin
0
WO Widget. When 0, audio is disabled . Default = 1

14.11.100 AUD_PORT_EN_D_DBG—Offset 62F2Ch

HDAudio Verb: PinWidget 707/3/734/701 These values are returned from the device as
the Digital Converter response to a Get Audio Output Converter Widget command.

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) AUD_PORT_EN_D_DBG: [GTTMMADR_LSB + 2BF20h] + 62F2Ch

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000003h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
MLP_STREAM
TAG_7_3

INDEX_2_0

HDMI_INDEX_PORT_D

PORT_D_AMP_MUTE_STATUS
RESERVED

PORT_D_OUT_ENABLE
CONNECTION_SELECT_CONTROL_D

CONVERTER_CHANNEL_MAP_PORT_D

Bay Trail-I SoC

618 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

0b TAG_7_3: Project: All This represents the SSID that will go in the lower 5 bits of the
31:27
WO SSID

0b INDEX_2_0: Project: All This is used as a pointer to program multiple SSID (only 0 is
26:24
WO supported for Cantiga)

0b CONNECTION_SELECT_CONTROL_D: Access Read Only Project: All This is used as a

23:16
WO pointer to program multiple SSID (only 0 is supported for Cantiga)

0b CONVERTER_CHANNEL_MAP_PORT_D: Access Read Only Project: All The number in

15:12 this field reflects the HD audio channel to which the HDMI channel is mapped. This field
WO is read only
0b HDMI_INDEX_PORT_D: Project: All This is used as a pointer to program multiple
11:8
WO SSID (only 0 is supported for Cantiga)

0b
7:5 RESERVED: Project: All Format: MBZ
WO
0b MLP_STREAM: Project: All Default Value: 000b Default Value Name Description Project
4:2
WO 000b Default Default All 011b MLP Stream MLP Stream All Others Reserved Reserved All

PORT_D_AMP_MUTE_STATUS: Access Read Only Project: All Project: All Default

1b Value: ;1b Amp muted This read-only bit reflects the mute status of the amplifier Value
1
WO Name Description Project 0b Amp not muted Amp not muted All 1b Amp muted Amp
muted All

1b PORT_D_OUT_ENABLE: All This bit reflects the state of the output path of the Pin
0
WO Widget. When 0, audio is disabled . Default = 1

14.11.101 AUD_CHICKENBIT_REG—Offset 62F38h

audio chickenbit register

Access Method
Type: Memory Mapped I/O Register AUD_CHICKENBIT_REG: [GTTMMADR_LSB + 2BF20h] +
(Size: 32 bits) 62F38h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000001h

Bay Trail-I SoC

Datasheet 619
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

RESERVED

PLACE_HOLDER_FOR_ECC_CHICKEN_BIT_PIPE_A
ENABLE_MMIO_HDMI_AUDIO_VERB_PROGRAMMING
Bit Default &
Description
Range Access

0b
31:2 RESERVED: Project: All Format: MBZ
WO

0b PLACE_HOLDER_FOR_ECC_CHICKEN_BIT_PIPE_A: Project: All

1
WO audr_ecc_flip_chicken_bit

ENABLE_MMIO_HDMI_AUDIO_VERB_PROGRAMMING: All Project: All Default

1b Value: ;1b Amp muted This read-only bit reflects the mute status of the amplifier Value
0
WO Name Description Project 0b HDAudio Programming through HDAudio Azalia All 1b
MMIO Programming through MMIO Debug registers All

14.11.102 AUD_OUT_DIG_CNVTA_DBG—Offset 62F40h

HDAudio Verb: Converter Widget 70E/73E These values are returned from the device
as the Digital Converter response to a Get Audio Output Converter Widget command.

Access Method
Type: Memory Mapped I/O Register AUD_OUT_DIG_CNVTA_DBG: [GTTMMADR_LSB + 2BF20h] +
(Size: 32 bits) 62F40h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

620 Datasheet
Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESERVED

IEC_CODING_TYPE

RSVD_FOR_DIGITAL__CONVERTER_2A
Bit Default &
Description
Range Access

0b
31:12 RESERVED: Project: All Format: MBZ
WO
0b
11:8 IEC_CODING_TYPE: Project: All
WO
0b
7:0 RSVD_FOR_DIGITAL__CONVERTER_2A: Project: All
WO

14.11.103 AUD_OUT_DIG_CNVTB_DBG—Offset 62F44h

HDAudio Verb: Converter Widget 70E/73E These values are returned from the device
as the Digital Converter response to a Get Audio Output Converter Widget command.

Access Method
Type: Memory Mapped I/O Register AUD_OUT_DIG_CNVTB_DBG: [GTTMMADR_LSB + 2BF20h] +
(Size: 32 bits) 62F44h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

Datasheet 621
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESERVED

RSVD_FOR_DIGITAL__CONVERTER_2B
IEC_CODING_TYPE
Bit Default &
Description
Range Access

0b
31:12 RESERVED: Project: All Format: MBZ
WO
0b
11:8 IEC_CODING_TYPE: Project: All
WO
0b
7:0 RSVD_FOR_DIGITAL__CONVERTER_2B: Project: All
WO

14.11.104 AUD_CNTL_ST_B_DBG—Offset 62F60h

HDAudio Verb: Pin Widget 730/732

Access Method
Type: Memory Mapped I/O Register
AUD_CNTL_ST_B_DBG: [GTTMMADR_LSB + 2BF20h] + 62F60h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

622 Datasheet
Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

INFOFRAME_PACKET_INDEX
RESERVED

INFOFRAME_CONTROL_FOR_CURRENTLY_INDEXED_FRAME

BYTE_OFFSET_INDEX_POINTER_LOCATION_5_BITS
Bit Default &
Description
Range Access

0b
31:10 RESERVED: Project: All Format: MBZ
WO

0b INFOFRAME_CONTROL_FOR_CURRENTLY_INDEXED_FRAME: Project: All Default

9:8 Value: 00b disable xmit Value Name Description Project 00b Disable xmit Disable xmit
WO All 01b Reserved Reserved All 10b Xmit once Xmit once All 11b Best Effort Best Effort All

0b INFOFRAME_PACKET_INDEX: Project: All Default Value: 00b Audio Value Name

7:5 Description Project 000b Audio Audio All 001b GP GP All 010b GP2 GP2 All 011b GP3
WO GP3 All 100b GP4 GP4 All Others Reserved Reserved All

0b
4:0 BYTE_OFFSET_INDEX_POINTER_LOCATION_5_BITS: Project: All
WO

14.11.105 AUD_HDMIW_INFOFR_B_DBG—Offset 62F64h

HDAudio Verb: Pin Widget 731

Access Method
Type: Memory Mapped I/O Register AUD_HDMIW_INFOFR_B_DBG: [GTTMMADR_LSB + 2BF20h] +
(Size: 32 bits) 62F64h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

Datasheet 623
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DATA_ISLAND_PACKET_DATA
RESERVED
Bit Default &
Description
Range Access

0b
31:8 RESERVED: Project: All Format: MBZ
WO

0b DATA_ISLAND_PACKET_DATA: Project: All This reflects the contents of the DIP

7:0 indexed by the DIP access address. The contents of this buffer are cleared during
WO function reset or HD audio link reset.

14.11.106 AUD_CNTL_ST_C_DBG—Offset 62F70h

HDAudio Verb: Pin Widget 730/732

Access Method
Type: Memory Mapped I/O Register
AUD_CNTL_ST_C_DBG: [GTTMMADR_LSB + 2BF20h] + 62F70h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

624 Datasheet
Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

INFOFRAME_PACKET_INDEX
RESERVED

INFOFRAME_CONTROL_FOR_CURRENTLY_INDEXED_FRAME

BYTE_OFFSET_INDEX_POINTER_LOCATION_5_BITS
Bit Default &
Description
Range Access

0b
31:10 RESERVED: Project: All Format: MBZ
WO

0b INFOFRAME_CONTROL_FOR_CURRENTLY_INDEXED_FRAME: Project: All Default

9:8 Value: 00b disable xmit Value Name Description Project 00b Disable xmit Disable xmit
WO All 01b Reserved Reserved All 10b Xmit once Xmit once All 11b Best Effort Best Effort All

0b INFOFRAME_PACKET_INDEX: Project: All Default Value: 00b Audio Value Name

7:5 Description Project 000b Audio Audio All 001b GP GP All 010b GP2 GP2 All 011b GP3
WO GP3 All 100b GP4 GP4 All Others Reserved Reserved All

0b
4:0 BYTE_OFFSET_INDEX_POINTER_LOCATION_5_BITS: Project: All
WO

14.11.107 AUD_HDMIW_INFOFR_C_DBG—Offset 62F74h

HDAudio Verb: Pin Widget 731

Access Method
Type: Memory Mapped I/O Register AUD_HDMIW_INFOFR_C_DBG: [GTTMMADR_LSB + 2BF20h] +
(Size: 32 bits) 62F74h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

Datasheet 625
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DATA_ISLAND_PACKET_DATA
RESERVED
Bit Default &
Description
Range Access

0b
31:8 RESERVED: Project: All Format: MBZ
WO

0b DATA_ISLAND_PACKET_DATA: Project: All This reflects the contents of the DIP

7:0 indexed by the DIP access address. The contents of this buffer are cleared during
WO function reset or HD audio link reset.

14.11.108 AUD_CNTL_ST_D_DBG—Offset 62F80h

HDAudio Verb: Pin Widget 730/732

Access Method
Type: Memory Mapped I/O Register
AUD_CNTL_ST_D_DBG: [GTTMMADR_LSB + 2BF20h] + 62F80h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

626 Datasheet
Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

INFOFRAME_PACKET_INDEX
RESERVED

INFOFRAME_CONTROL_FOR_CURRENTLY_INDEXED_FRAME

BYTE_OFFSET_INDEX_POINTER_LOCATION_5_BITS
Bit Default &
Description
Range Access

0b
31:10 RESERVED: Project: All Format: MBZ
WO

0b INFOFRAME_CONTROL_FOR_CURRENTLY_INDEXED_FRAME: Project: All Default

9:8 Value: 00b disable xmit Value Name Description Project 00b Disable xmit Disable xmit
WO All 01b Reserved Reserved All 10b Xmit once Xmit once All 11b Best Effort Best Effort All

0b INFOFRAME_PACKET_INDEX: Project: All Default Value: 00b Audio Value Name

7:5 Description Project 000b Audio Audio All 001b GP GP All 010b GP2 GP2 All 011b GP3
WO GP3 All 100b GP4 GP4 All Others Reserved Reserved All

0b
4:0 BYTE_OFFSET_INDEX_POINTER_LOCATION_5_BITS: Project: All
WO

14.11.109 AUD_HDMIW_INFOFR_D_DBG—Offset 62F84h

HDAudio Verb: Pin Widget 731

Access Method
Type: Memory Mapped I/O Register AUD_HDMIW_INFOFR_D_DBG: [GTTMMADR_LSB + 2BF20h] +
(Size: 32 bits) 62F84h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

Datasheet 627
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DATA_ISLAND_PACKET_DATA
RESERVED
Bit Default &
Description
Range Access

0b
31:8 RESERVED: Project: All Format: MBZ
WO

0b DATA_ISLAND_PACKET_DATA: Project: All This reflects the contents of the DIP

7:0 indexed by the DIP access address. The contents of this buffer are cleared during
WO function reset or HD audio link reset.

14.11.110 AUD_CONFIG_DEFAULT2_REG_PORTB—Offset 62F88h

HDAudio Verb: Pin Widget 738..73B

Access Method
Type: Memory Mapped I/O Register AUD_CONFIG_DEFAULT2_REG_PORTB: [GTTMMADR_LSB +
(Size: 32 bits) 2BF20h] + 62F88h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
READ_BACK

Bit Default &

Description
Range Access

0b READ_BACK: Project: All Config Default 2 values of port B rgars being written using the
31:0
WO 738/739/73A/73B

14.11.111 AUD_CONFIG_DEFAULT2_REG_PORTC—Offset 62F8Ch

HDAudio Verb: Pin Widget 738..73B

Access Method

Bay Trail-I SoC

628 Datasheet
Graphics, Video and Display

Type: Memory Mapped I/O Register AUD_CONFIG_DEFAULT2_REG_PORTC: [GTTMMADR_LSB +

(Size: 32 bits) 2BF20h] + 62F8Ch

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

READ_BACK
Bit Default &
Description
Range Access

0b READ_BACK: Project: All Config Default 2 values of port C rgars being written using the
31:0
WO 738/739/73A/73B

14.11.112 AUD_CONFIG_DEFAULT2_REG_PORTD—Offset 62F90h

HDAudio Verb: Pin Widget 738..73B

Access Method
Type: Memory Mapped I/O Register AUD_CONFIG_DEFAULT2_REG_PORTD: [GTTMMADR_LSB +
(Size: 32 bits) 2BF20h] + 62F90h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
READ_BACK

Bit Default &

Description
Range Access

0b READ_BACK: Project: All Config Default 2 values of port D rgars being written using
31:0
WO the 738/739/73A/73B

14.11.113 AUD_MCTSA—Offset 62F94h

Audio M or CTS Pipe A Values Readback Register

Access Method

Bay Trail-I SoC

Datasheet 629
 Graphics, Video and Display

Type: Memory Mapped I/O Register

AUD_MCTSA: [GTTMMADR_LSB + 2BF20h] + 62F94h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BIT_23_0_OF_AUDIO_M_OR_CTS__VALUES_TO_PIPE_A
RESERVED

Bit Default &

Description
Range Access

0b
31:24 RESERVED: Project: All Format: MBZ
RO

0b
23:0 BIT_23_0_OF_AUDIO_M_OR_CTS__VALUES_TO_PIPE_A: Project: All
RO

14.11.114 AUD_MCTSB—Offset 62F98h

Audio M or CTS Pipe B Values Readback Register

Access Method
Type: Memory Mapped I/O Register AUD_MCTSB: [GTTMMADR_LSB + 2BF20h] + 62F98h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

630 Datasheet
Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BIT_23_0_OF_AUDIO_M_OR_CTS__VALUES_TO_PIPE_B
RESERVED

Bit Default &

Description
Range Access

0b
31:24 RESERVED: Project: All Format: MBZ
RO
0b
23:0 BIT_23_0_OF_AUDIO_M_OR_CTS__VALUES_TO_PIPE_B: Project: All
RO

14.11.115 DP_B—Offset 64100h

DisplayPort B Control Register [DevCTG, DevCDV] Display Port B control (dprrega_b0.v
ql_displayb1)

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) DP_B: [GTTMMADR_LSB + 2BF20h] + 64100h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000018h

Bay Trail-I SoC

Datasheet 631
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0

DIGITAL_DISPLAY_B_DETECTED

DISABLE_FRAMESTART_STALL
DISPLAYPORT_B_ENABLE

LINK_TRAINING_PATTERN_ENABLE
PIPE_SELECT

SCRAMBLING_DISABLE
RESERVED

ENHANCED_FRAMING_ENABLE

ASR_ENABLE

AUDIO_OUTPUT_ENABLE
HDCP_PORT_SELECT

SYNC_POLARITY
RESERVED_1

RESERVED_2

RESERVED_3

RESERVED_4

RESERVED_5
PORT_WIDTH_SELECTION
Bit Default &
Description
Range Access

0b DISPLAYPORT_B_ENABLE: Disabling this port will put it in its lowest power state.
31 Port enable takes place on the Vblank after being written. 1 = Enable. This bit enables
RW the Display Port B interface. 0 = Disable and tristates the Display Port B interface.

0b PIPE_SELECT: This bit determines from which display pipe the source data will
30 originate. Pipe selection takes place on the Vblank after being written 0 = Pipe A 1 =
RW Pipe B
LINK_TRAINING_PATTERN_ENABLE: These bits are used for link initialization as
defined in the DisplayPort specification. Please note that the link must first be
configured prior to sending training patterns. 00 Pattern 1 enabled: Repetition of D10.2
0b characters Default. 01 Pattern 2 enabled: Repetition of K28.5, D11.6, K28.5, D11.6,
29:28 D10.2, D10.2, D10.2, D10.2, D10.2, D10.2. Please note that the entire pattern must
RW complete before another pattern is sent. Scrambling initialization and disparity init
commence at the end of the last iteration of pattern 2. 10 Idle Pattern enabled: Transmit
BS followed by VB-ID with NoVideoStream_flag set to 1, five times 11 Link not in
training: Send normal pixels
RESERVED: [DevCDV]: Voltage swing level set: [DevCTG]: These bits are used for
0b setting the voltage swing for pattern 1, defined as Vdiff_pp in the DisplayPort
27:25 specification. They mirror registers in the PCI express configuration (At CDV moved to
RW register at the DPIO) 000 0.4V (DEFAULT) 001 0.6V 010 0.8V 011 1.2V RESERVED 1xx
RESERVED
RESERVED_1: [DevCDV]: Pre-emphasis level set [DevCTG]: These bits are used for
0b setting link pre-emphasis for pattern 2, as defined in the DisplayPort specification. They
24:22 mirror registers in the PCI express configuration. At CDV this field move to register in
RW the DPIO. 000 no pre-emphasis (default) 001 3.5dB pre-emphasis (1.5x) 010 6dB pre-
emphasis (2x) 011 9.5dB pre-emphasis (3x) RESERVED 1xx RESERVED
PORT_WIDTH_SELECTION: This bit selects the number of lanes to be enabled on the
0b DisplayPort link. Port width selection takes place on the Vblank after being written. Port
21:19
RW width change must be done as a part of mode set. 000 = x1 Mode (Default) 001 = x2
Mode. 010 = RESERVED 011 = x4 Mode. 1xx = RESERVED
ENHANCED_FRAMING_ENABLE: This bit selects enhanced framing. It must be set
0b when HDCP will be used invoked. 0 (Default) Enhanced framing disabled 1 Enhanced
18
RW framing enabled. Locked once port is enabled. Updates when the port is disabled then
re-enabled

0b
17:16 RESERVED_2: MBZ
RW

0b RESERVED_3: [DevCDV]: Port reversal [DevCTG]: Locked once port is enabled.

15
RW Updates when the port is disabled then re-enabled

0b
14:9 RESERVED_4: MBZ
RW

Bay Trail-I SoC

632 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

0b ASR_ENABLE: [DevVLV2]: this bit enables the Alternate Scrammbler Reset capability
8 for eDP port to use alternate scrambler reset value of FFFEh 1 - ASR enable 0 ASR
RW disable

0b SCRAMBLING_DISABLE: [DevCTG, B-step only, DevCDV]: This bit disables

7 scrambling for this port. 0 = Scrambling enabled (Default) 1 = Scrambling disabled, no
RW SR after initialization at loop 2 of training

0b AUDIO_OUTPUT_ENABLE: This bit enables audio on this output port. It may be

6 enabled or disabled only when the link training is complete and set to Normal 0 = Audio
RW output disabled 1 = Audio output enabled
HDCP_PORT_SELECT: This bit directs HDCP to this port. When enabled, the
0b information sent on this port will be encrypted using HDCP. Please note that this bit does
5
RW not enable encryption on its own, but must be used in conjunction with HDCP registers.
0 = (Default) No HDCP encryption on this port 1 = Enable HDCP on this port
SYNC_POLARITY: Indicates the polarity of Hsync and Vsync. Please note that in native
11b VGA modes, these bits have no effect. In native VGA modes, sync polarity is determined
4:3 by VRshr3c2d76b[7:6], the VGA polarity bits in VGA control. 00 = VS and HS are active
RW low (inverted) 01 = VS is active low (inverted), HS is active high 10 = VS is active high,
HS is active low (inverted) 11 = (Default) VS and HS are active high
DIGITAL_DISPLAY_B_DETECTED: Read-only bit indicating whether a digital display
0b was detected during initialization. It signifies the level of the GMBUS port 4 (port B) data
2
RO line at boot. 0 = digital display not detected during initialization (Default) 1 = digital
display detected during initialization AccessType: Read Only
0b
1 RESERVED_5: MBZ
RW
DISABLE_FRAMESTART_STALL: This bit, when set, will disable the framestart
0b window to stall DP AV mixer from sending audio samples before framestart. This applies
0
RW to BOTH pipes. 0 = Enable framestart window to stall audio samples. (default) 1 =
Disable framestart window to stall audio samples.

14.11.116 DPB_AUX_CH_CTL—Offset 64110h

Display Port B AUX Channel Control [DevCDV] AuxB control (dprrega_b0.v
auxb_ctl_rdback)

Access Method
Type: Memory Mapped I/O Register DPB_AUX_CH_CTL: [GTTMMADR_LSB + 2BF20h] + 64110h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00050000h

Bay Trail-I SoC

Datasheet 633
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

AUX_AKSV_BUFFER_SELECT

_2X_BIT_CLOCK_DIVIDER
INVERT_MANCHESTER_TEST_MODE
SEND_BUSY

TIME_OUT_ERROR

MESSAGE_SIZE

SYNC_ONLY_CLOCK_RECOVERY_TEST_MODE
DISABLE_DE_GLITCH_TEST_MODE
RECEIVE_ERROR

DOUBLE_PRECHARGE_TEST_MODE
DONE
INTERRUPT_ON_DONE

TIME_OUT_TIMER_VALUE

PRECHARGE_TIME

Bit Default &

Description
Range Access

SEND_BUSY: Setting this bit to a one initiates the transaction, when read this bit will
0b be a 1 until the transmission completes. The transaction is completed when the
31
RW response is received or when a timeout occurs. Do not write a 1 again until transaction
completes. Writes of 0 will be ignored.

0b DONE: A sticky bit that indicates the transaction has completed. SW must write a 1 to
30
RW/1C this bit to clear the event. AccessType: One to Clear

0b INTERRUPT_ON_DONE: Enable an interrupt in the hotplug status register when the

29
RW transaction completes or times out.

0b TIME_OUT_ERROR: A sticky bit that indicates the transaction has timed out. SW must
28
RW/1C write a 1 to this bit to clear the event. AccessType: One to Clear

0b TIME_OUT_TIMER_VALUE: 00: 400us (default) 01: 600us 10: 800us 11: 1600us The
27:26
RW time count depends on the 2X bit clock divider (bits 10:0) being programmed for 2MHz.

0b RECEIVE_ERROR: A sticky bit that indicates that the data received was corrupted, not
25 in multiples of a full byte, or more than 20 bytes. SW must write a 1 to this bit to clear
RW/1C the event. AccessType: One to Clear
MESSAGE_SIZE: This field is used to indicate the total number bytes to transmit
(including the header). It also indicates the number of bytes received in a transaction
0b (including the header). This field is valid only only when the done bit is set and timeout
24:20
RW or receive error has not occurred. Sync/Stop are not part of the message or the
message size. Reads of this field will give the response message size. The read value will
not be valid while Busy bit 31 is asserted. Message sizes of 0 or )20 are not allowed.
PRECHARGE_TIME: Used to determine the precharge time for the Aux Channel
0101b drivers. The value is the number of microseconds times 2. This depends on the 2X bit
19:16
RW clock divider (bits 10:0) being programmed for 2MHz. Default is 5 decimal which gives
10us of precharge. Example: For 12us precharge, program 6 (12us/2us).
AUX_AKSV_BUFFER_SELECT: This bit selects whether some of the data to be written
over Display Port AUX comes from the Aksv buffer for HDCP authentication, or all from
the AUX Data registers. Set this bit before initiating a transaction to write Aksv to the
0b Display Port sink. All AUX protocol must be followed and Message Size set to 9 bytes.
15 The first DWord transmitted will be from the AUX Data Register 1 for the header, then
RW the DP_AUX_CH_AKSV_HI, then the last byte from DP_AUX_CH_AKSV_LO. The sink
response is read back as usual from the AUX Data registers. More than one AUX channel
can select to use the Aksv buffer simultaneously. 0 (Default) Use AUX Data registers for
regular data transmission 1 Use Aksv Buffer for part of the data transmission.

Bay Trail-I SoC

634 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

0b INVERT_MANCHESTER_TEST_MODE: 1 = Manchester code rising edge mid-clk

14 signifies one (test mode) 0 = Manchester code rising edge mid-clk signifies zero
RW (default)
0b SYNC_ONLY_CLOCK_RECOVERY_TEST_MODE: 1 = Only recover clock during sync
13
RW pattern (test mode) 0 = Recover clock during sync pattern and data phase (default)

0b DISABLE_DE_GLITCH_TEST_MODE: 1 = Disable serial input de-glitch logic (test

12
RW mode) 0 = Enable serial input de-glitch logic (default)

0b DOUBLE_PRECHARGE_TEST_MODE: 1 = Precharge time is doubled 0 = Precharge

11
RW time is as programmed

_2X_BIT_CLOCK_DIVIDER: Used to determine the 2X bit clock the Aux Channel logic
0b runs on. This value divides the input clock frequency down to 2X bit clock rate. The 2X
10:0 bit clock rate is ideally 2MHz (0.5us). [DevCTG-A] the input clock is cdclk. [DevCTG-B,
RW DevCDV] the input clock is hrawclk (200MHz) Example: For 300MHz input clock and
desired 2MHz 2X bit clock, program 150 (300MHz/2MHz).

14.11.117 DPB_AUX_CH_DATA1—Offset 64114h

Display Port B AUX Data Register 1 [DevCTG, DevCDV]

Access Method
Type: Memory Mapped I/O Register
DPB_AUX_CH_DATA1: [GTTMMADR_LSB + 2BF20h] + 64114h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
AUX_CH_DATA1_31

Bit Default &

Description
Range Access

0b AUX_CH_DATA1_31: 0]: The first Dword of the message. The Msbyte is transmitted
31:0
RW first. Reads will give the response data after transaction complete.

14.11.118 DPB_AUX_CH_DATA2—Offset 64118h

Display Port B AUX Data Register 2 [DevCTG, DevCDV] AuxB Data2 (dprrega_b0.v
auxb_dpr_data2, ql_auxb_d2)

Access Method

Bay Trail-I SoC

Datasheet 635
 Graphics, Video and Display

Type: Memory Mapped I/O Register

DPB_AUX_CH_DATA2: [GTTMMADR_LSB + 2BF20h] + 64118h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

AUX_CH_DATA2_31
Bit Default &
Description
Range Access

0b AUX_CH_DATA2_31: 0]: The second Dword of the message. The Msbyte is

31:0 transmitted first. Only used if the message size is greater than 4. Reads will give the
RW response data after transaction complete.

14.11.119 DPB_AUX_CH_DATA3—Offset 6411Ch

Display Port B AUX Data Register 3 [DevCTG, DevCDV] AuxB Data3 (dprrega_b0.v
auxb_dpr_data3, ql_auxb_d3)

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) DPB_AUX_CH_DATA3: [GTTMMADR_LSB + 2BF20h] + 6411Ch

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
AUX_CH_DATA3_31

Bit Default &

Description
Range Access

0b AUX_CH_DATA3_31: 0]: The third Dword of the message. The Msbyte is transmitted
31:0 first. Only used if the message size is greater than 8. Reads will give the response data
RW after transaction complete.

Bay Trail-I SoC

636 Datasheet
Graphics, Video and Display

14.11.120 DPB_AUX_CH_DATA4—Offset 64120h

Display Port B AUX Data Register 4 [DevCTG, DevCDV] AuxB Data4 (dprrega_b0.v
auxb_dpr_data4, ql_auxb_d4)

Access Method
Type: Memory Mapped I/O Register
DPB_AUX_CH_DATA4: [GTTMMADR_LSB + 2BF20h] + 64120h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

AUX_CH_DATA4_31

Bit Default &

Description
Range Access

0b AUX_CH_DATA4_31: 0]: The fourth Dword of the message. The Msbyte is transmitted
31:0 first. Only used if the message size is greater than 12. Reads will give the response data
RW after transaction complete.

14.11.121 DPB_AUX_CH_DATA5—Offset 64124h

Display Port B AUX Data Register 5 [DevCTG, DevCDV] AuxB Data5 (dprrega_b0.v
auxb_dpr_data5, ql_auxb_d5)

Access Method
Type: Memory Mapped I/O Register DPB_AUX_CH_DATA5: [GTTMMADR_LSB + 2BF20h] + 64124h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
AUX_CH_DATA5_31

Bay Trail-I SoC

Datasheet 637
 Graphics, Video and Display

Bit Default &

Description
Range Access

0b AUX_CH_DATA5_31: 0]: The fifth Dword of the message. The Msbyte is transmitted
31:0 first. Only used if the message size is greater than 16. Reads will give the response data
RW after transaction complete.

14.11.122 DP_AUX_CH_AKSV_HI—Offset 64130h

Display Port AUX Aksv Buffer High [DevCTG-B, DevCDV] AuxB AKSV High
(dprrega_b0.v dpr_aux_aksv_hi)

Access Method
Type: Memory Mapped I/O Register
DP_AUX_CH_AKSV_HI: [GTTMMADR_LSB + 2BF20h] + 64130h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
AKSV_BITS_7

AKSV_BITS_15

AKSV_BITS_23

AKSV_BITS_31
Bit Default &
Description
Range Access

0b
31:24 AKSV_BITS_7: 0]
WO
0b
23:16 AKSV_BITS_15: 8]
WO
0b
15:8 AKSV_BITS_23: 16]
WO
0b
7:0 AKSV_BITS_31: 24]
WO

14.11.123 DP_AUX_CH_AKSV_LO—Offset 64134h

Display Port AUX Aksv Buffer Low [DevCTG-B, DevCDV] AuxB AKSV High
(dprrega_b0.v dpr_aux_aksv_lo)

Access Method
Type: Memory Mapped I/O Register
DP_AUX_CH_AKSV_LO: [GTTMMADR_LSB + 2BF20h] + 64134h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

638 Datasheet
Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESERVED

AKSV_BITS_39
Bit Default &
Description
Range Access

0b
31:8 RESERVED: MBZ
WO
0b
7:0 AKSV_BITS_39: 32]
WO

14.11.124 DPB_AUX_TST—Offset 64150h

Display Port B AUX Test Register

Access Method
Type: Memory Mapped I/O Register
DPB_AUX_TST: [GTTMMADR_LSB + 2BF20h] + 64150h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DPB_AUX_BUFFER_LOOPBACK_TEST_DONE
DPB_AUX_BUFFER_LOOPBACK_TEST_RESULT
DPB_AUX_FULL_TEST_ENABLE

DPB_AUX_DEBUG_STATUS_READBACK
DPB_AUX_BUFFER_LOOPBACK_TEST_ENABLE

DEGLITCH_AMOUNT

DPB_AUX_MULTIPLE_RECEIVED_EDGES_ERROR_ENABLE
DPB_AUX_SHORT_SYNC
DPB_AUX_CONSTANT_0S_TEST_PATTERN
DPB_AUX_TIGHTEN_FREQUENCY_WINDOW
RESERVED

DPB_AUX_LESS_GOOD_SYNC_0S_REQUIRED

RESERVED_1

RESERVED_2

Bay Trail-I SoC

Datasheet 639
 Graphics, Video and Display

Bit Default &

Description
Range Access

DPB_AUX_BUFFER_LOOPBACK_TEST_ENABLE: Project: All Default Value: 0b

Enables test for the DPB-AUX I/O buffer. A 16 cycle clock pattern is output to the I/O
buffer and compared against the looped back buffer output. The input clock is cdclk.
0b With input clock at 512MHz the pattern will bea 1 MHz clock. It scales down with lower
31 clock frequencies. The result is found in DP-AUX Buffer Loopback Test Result after DP-
RW AUX Buffer Loopback Test Done is set. Clear this bit to 0 after test is done to return DP-
AUX to normal operation. Loopback Test can be run simultaneously on all AUX buffers.
Do not enable DP-AUX Buffer Loopback Test and DP-AUX Full Test simultaneously. Value
Name Description Project 0b Disable Test disabled All 1b Enable Enable test. All
DPB_AUX_BUFFER_LOOPBACK_TEST_DONE: Project: All Default Value: 0b
0b AccessType: Read Only DPB-AUX Buffer Loopback Test has been run and completed.
30 This is not the done for the DP-AUX Full Test. Value Name Description Project 0b Not
RO Done Test not done. DP-AUX Buffer Loopback Test Result is not valid All 1b Done Test
done. DP-AUX Buffer Loopback Test Result is now valid All
DPB_AUX_BUFFER_LOOPBACK_TEST_RESULT: Project: All Default Value: 0b
0b AccessType: Read Only Result of the DPB-AUX Buffer Loopback Test. Value is only valid
29
RO after a DP-AUX Loopback Test Done is 1. This is not the result of the DP-AUX Full Test.
Value Name Description Project 0b Pass Pass All 1b Fail All
DPB_AUX_FULL_TEST_ENABLE: Project: All Default Value: 0b Enables test for the
DPB-AUX core logic transmit and receive functions through the DPB-AUX and DPC-AUX
buffers. DPB-AUX and DPC-AUX are interconnected through I/O buffer loopbacks. DPB-
AUX is programmed as source to output a 20 byte test pattern. DPC-AUX is programmed
as sink to receive the test pattern and reply with a different 20 byte test pattern. Test
pattern 1 = 0xA55CC33E E770080C 0E0F0F8F CFEFF81C 3E77E3C8 Test pattern 2 =
0X183C7EE7 C381FF7F 3F1F0F07 030100EE 77CC33A5 Programming sequence: 1. Set
DPB-AUX Full Test Enable to 1. 2. Program DPB_AUX_CH_DATA[1-5] with test pattern 1
to transmit as the source. 3. Program DPC_AUX_CH_DATA[1-5] with test pattern 2 to
0b reply with as the sink. 4. Program all DPC_AUX_CH_CTL fields and set Send to 1. 5.
28 Program all DPB_AUX_CH_CTL fields and set Send to 1. Then the test will start. Results
RW checking sequence: 1. Poll DPB_AUX_CH_CTL for Done. To pass, Done must be set
within 500us. 2. Read DPB_AUX_CH_CTL register. To pass, Timeout Error and Receive
Error must be 0. 3. Read DPC_AUX_CH_CTL register. To pass, Receive Error must be 0.
4. Read DPB_AUX_CH_DATA[1-5] registers. To pass, they must contain test pattern 2.
5. Read DPC_AUX_CH_DATA[1-5] registers. To pass, they must contain test pattern 1.
Clear this bit to 0 after test is done to return DP-AUX to normal operation. Test must be
repeated with and without lane reversal to verify DPB-AUX buffer combinations. Only
enable one DP-AUX Full Test at a time. To abort a test in progress, write the
AUX_CH_CTL Send bits to 0 and Full Test Enable to 0. Value Name Description Project
0b Disable Test disabled All 1b Enable Enable test All
0b
27:16 RESERVED: Project: All Format:
RW

0b DPB_AUX_SHORT_SYNC: Project: All Output just 16 manchester 0s for sync

15
RW (otherwise 26)

0b DPB_AUX_CONSTANT_0S_TEST_PATTERN: Project: All Output neverending

14
RW Manchester encoded 0s for electrical testing

0b DPB_AUX_TIGHTEN_FREQUENCY_WINDOW: Project: All Tighten the window of

13
RW allowable receive frequencies

0b DPB_AUX_LESS_GOOD_SYNC_0S_REQUIRED: Project: All Check for only 8 good

12
RW sync 0s instead of 12 when receiving

DEGLITCH_AMOUNT: Project: All Default Value: 0b Select clock count for deglitch
0b Value Name Description Project 00b 50 ns 25 clocks - GMBUS type - 50ns at 500MHz
11:10 cdclk All 01b 125 ns 1/4 2X bit clock divider value - 125ns All 10b 62.5 ns 1/8 2X bit
RW clock divider value - 62.5ns All 11b 31.125 ns 1/16 2X bit clock divider value - 31.125ns
All
0b
9 RESERVED_1: Project: All Format:
RW

0b DPB_AUX_MULTIPLE_RECEIVED_EDGES_ERROR_ENABLE: Project: All Default

8 Value: 0b Value Name Description Project 0b Okay Multiple edges in window is okay All
RW 1b Error Multiple edges in window is an error All

Bay Trail-I SoC

640 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

DPB_AUX_DEBUG_STATUS_READBACK: Readback of bit clock divide field gives the

error type io_aux_data_syncro and aux_io_data and sm_noa[3:0] and
0b clkregen_baddatastop and mdec_toomuchdata and mdec_notbytealign and
7:6
RW mdec_multiedgeinwin and Input data Output data Control state machine Error - bad
STOP at end of data Error - too much data Error - data not byte aligned Error - multiple
edges inside of window Error - multiple edges outside of window All
0b
5:0 RESERVED_2: Project: All Format:
RW

14.11.125 DP_C—Offset 64200h

Display Port C Control Register [DevCTG, DevCDV,DevVLV] Display Port C control
(dprrega_b0.v ql_displayc1)

Access Method
Type: Memory Mapped I/O Register
DP_C: [GTTMMADR_LSB + 2BF20h] + 64200h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000018h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0

DIGITAL_DISPLAY_C_DETECTED
DISPLAYPORT_C_ENABLE

SCRAMBLING_DISABLE
LINK_TRAINING_PATTERN_ENABLE
PIPE_SELECT

RESERVED

ASR_ENABLE

AUDIO_OUTPUT_ENABLE
ENHANCED_FRAMING_ENABLE

HDCP_PORT_SELECT

SYNC_POLARITY
RESERVED_1

RESERVED_2

RESERVED_3

RESERVED_4

RESERVED_5
PORT_WIDTH_SELECTION

Bit Default &

Description
Range Access

DISPLAYPORT_C_ENABLE: Disabling this port will put it in its lowest power state.
0b Port enable takes place on the Vblank after being written. Both this bit and bit 6 of this
31
RW register must be enabled to send audio over this port. 1 = Enable. This bit enables the
Display Port C interface. 0 = Disable and tristates the Display Port C interface.

0b PIPE_SELECT: This bit determines from which display pipe the source data will
30 originate. Pipe selection takes place on the Vblank after being written 0 = Pipe A 1 =
RW Pipe B

Bay Trail-I SoC

Datasheet 641
 Graphics, Video and Display

Bit Default &

Description
Range Access

LINK_TRAINING_PATTERN_ENABLE: These bits are used for link initialization as

defined in the DisplayPort specification. Please note that the link must first be
configured prior to sending training patterns. 00 Pattern 1 enabled: Repetition of D10.2
0b characters Default. 01 Pattern 2 enabled: Repetition of K28.5, D11.6, K28.5, D11.6,
29:28 D10.2, D10.2, D10.2, D10.2, D10.2, D10.2. Please note that the entire pattern must
RW complete before another pattern is sent. Scrambling initialization and disparity init
commence at the end of the last iteration of pattern 2. 10 Idle Pattern enabled: Transmit
BS followed by VB-ID with NoVideoStream_flag set to 1, five times 11 Link not in
training: Send normal pixels
RESERVED: [DevCDV]: Voltage swing level set [DevCTG]: These bits are used for
0b setting the voltage swing for pattern 1, defined as Vdiff_pp in the DisplayPort
27:25
RW specification. They mirror registers in the PCI express configuration. 000 0.4V
(DEFAULT) 001 0.6V 010 0.8V 011 1.2V RESERVED 1xx RESERVED
RESERVED_1: [DevCDV]: Pre-emphasis level set [DevCTG]: These bits are used for
0b setting link pre-emphasis for pattern 2, as defined in the DisplayPort specification. They
24:22 mirror registers in the PCI express configuration. 000 no pre-emphasis (default) 001
RW 3.5dB pre-emphasis (1.5x) 010 6dB pre-emphasis (2x) 011 9.5dB pre-emphasis (3x)
RESERVED 1xx RESERVED
PORT_WIDTH_SELECTION: This bit selects the number of lanes to be enabled on the
0b DisplayPort link. Port width selection takes place on the Vblank after being written. Port
21:19
RW width change must be done as a part of mode set. 000 = x1 Mode (Default) 001 = x2
Mode. 010 = RESERVED 011 = x4 Mode. 1xx = RESERVED
ENHANCED_FRAMING_ENABLE: This bit selects enhanced framing. It must be set
0b when HDCP will be used invoked. 0 (Default) Enhanced framing disabled 1 Enhanced
18
RW framing enabled. Locked once port is enabled. Updates when the port is disabled then
re-enabled

0b
17:16 RESERVED_2: MBZ
RW

0b RESERVED_3: [DevCDV]: Port reversal [DevCTG]: Locked once port is enabled.

15
RW Updates when the port is disabled then re-enabled

0b
14:9 RESERVED_4: MBZ
RW

0b ASR_ENABLE: [DevVLV2]: this bit enables the Alternate Scrammbler Reset capability
8 for eDP port to use alternate scrambler reset value of FFFEh 1 - ASR enable 0 ASR
RW disable

0b SCRAMBLING_DISABLE: [DevCTG, B-step only, DevCDV]: This bit disables

7 scrambling for this port. 0 = Scrambling enabled (Default) 1 = Scrambling disabled, no
RW SR after initialization at loop 2 of training

0b AUDIO_OUTPUT_ENABLE: This bit enables audio on this output port. It may be

6 enabled or disabled only when the link training is complete and set to Normal 0 = Audio
RW output disabled 1 = Audio output enabled
HDCP_PORT_SELECT: This bit directs HDCP to this port. When enabled, the
0b information sent on this port will be encrypted using HDCP. Please note that this bit does
5
RW not enable encryption on its own, but must be used in conjunction with HDCP registers.
0 = (Default) No HDCP encryption on this port 1 = Enable HDCP on this port
SYNC_POLARITY: Indicates the polarity of Hsync and Vsync. Please note that in native
11b VGA modes, these bits have no effect. In native VGA modes, sync polarity is determined
4:3 by VRshr3c2d76b[7:6], the VGA polarity bits in VGA control. 00 = VS and HS are active
RW low (inverted) 01 = VS is active low (inverted), HS is active high 10 = VS is active high,
HS is active low (inverted) 11 = (Default) VS and HS are active high
DIGITAL_DISPLAY_C_DETECTED: Read-only bit indicating whether a digital display
0b was detected during initialization. It signifies the level of the GMBUS port (sDVO B/C)
2
RO data line at boot. 0 = digital display not detected during initialization (Default) 1 =
digital display detected during initialization AccessType: Read only
0b
1:0 RESERVED_5: MBZ
RW

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642 Datasheet
Graphics, Video and Display

14.11.126 DPC_AUX_CH_CTL—Offset 64210h

Display Port C AUX Channel Control [DevCTG] AuxC Data1 (dprrega_b0.v
auxc_dpr_data1, ql_auxc_d1)

Access Method
Type: Memory Mapped I/O Register
DPC_AUX_CH_CTL: [GTTMMADR_LSB + 2BF20h] + 64210h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00050000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

AUX_AKSV_BUFFER_SELECT

SYNC_ONLY_CLOCK_RECOVERY_TEST_MODE
INVERT_MANCHESTER_TEST_MODE
SEND_BUSY

MESSAGE_SIZE

DISABLE_DE_GLITCH_TEST_MODE
DOUBLE_PRECHARGE_TEST_MODE
DONE
INTERRUPT_ON_DONE

TIME_OUT_TIMER_VALUE

_2X_BIT_CLOCK_DIVIDER
PRECHARGE_TIME
TIME_OUT_ERROR

RECEIVE_ERROR

Bit Default &

Description
Range Access

SEND_BUSY: Setting this bit to a one initiates the transaction, when read this bit will
0b be a 1 until the transmission completes. The transaction is completed when the
31
RW response is received or when a timeout occurs. Do not write a 1 again until transaction
completes. Writes of 0 will be ignored.
0b DONE: A sticky bit that indicates the transaction has completed. SW must write a 1 to
30
RW/1C this bit to clear the event. AccessType: One to Clear

0b INTERRUPT_ON_DONE: Enable an interrupt in the hotplug status register when the

29
RW transaction completes or times out.

0b TIME_OUT_ERROR: A sticky bit that indicates the transaction has timed out. SW must
28
RW/1C write a 1 to this bit to clear the event. AccessType: One to Clear

0b TIME_OUT_TIMER_VALUE: 00: 400us (default) 01: 600us 10: 800us 11: 1600us The
27:26
RW time count depends on the 2X bit clock divider (bits 10:0) being programmed for 2MHz.

0b RECEIVE_ERROR: A sticky bit that indicates that the data received was corrupted, not
25 in multiples of a full byte, or more than 20 bytes. SW must write a 1 to this bit to clear
RW/1C the event. AccessType: One to Clear
MESSAGE_SIZE: This field is used to indicate the total number bytes to transmit
(including the header). It also indicates the number of bytes received in a transaction
0b (including the header). This field is valid only only when the done bit is set and timeout
24:20
RW or receive error has not occurred. Sync/Stop are not part of the message or the
message size. Reads of this field will give the response message size. The read value will
not be valid while Busy bit 31 is asserted. Message sizes of 0 or )20 are not allowed.

Bay Trail-I SoC

Datasheet 643
 Graphics, Video and Display

Bit Default &

Description
Range Access

PRECHARGE_TIME: Used to determine the precharge time for the Aux Channel
0101b drivers. The value is the number of microseconds times 2. This depends on the 2X bit
19:16
RW clock divider (bits 10:0) being programmed for 2MHz. Default is 5 decimal which gives
10us of precharge. Example: For 12us precharge, program 6 (12us/2us).
AUX_AKSV_BUFFER_SELECT: This bit selects whether some of the data to be written
over Display Port AUX comes from the Aksv buffer for HDCP authentication, or all from
the AUX Data registers. Set this bit before initiating a transaction to write Aksv to the
0b Display Port sink. All AUX protocol must be followed and Message Size set to 9 bytes.
15 The first DWord transmitted will be from the AUX Data Register 1 for the header, then
RW the DP_AUX_CH_AKSV_HI, then the last byte from DP_AUX_CH_AKSV_LO. The sink
response is read back as usual from the AUX Data registers. More than one AUX channel
can select to use the Aksv buffer simultaneously. 0 (Default) Use AUX Data registers for
regular data transmission 1 Use Aksv Buffer for part of the data transmission.

0b INVERT_MANCHESTER_TEST_MODE: 1 = Manchester code rising edge mid-clk

14 signifies one (test mode) 0 = Manchester code rising edge mid-clk signifies zero
RW (default)
0b SYNC_ONLY_CLOCK_RECOVERY_TEST_MODE: 1 = Only recover clock during sync
13
RW pattern (test mode) 0 = Recover clock during sync pattern and data phase (default)

0b DISABLE_DE_GLITCH_TEST_MODE: 1 = Disable serial input de-glitch logic (test

12
RW mode) 0 = Enable serial input de-glitch logic (default)

0b DOUBLE_PRECHARGE_TEST_MODE: 1 = Precharge time is doubled 0 = Precharge

11
RW time is as programmed

_2X_BIT_CLOCK_DIVIDER: Used to determine the 2X bit clock the Aux Channel logic
0b runs on. This value divides the input clock frequency down to 2X bit clock rate. The 2X
10:0 bit clock rate is ideally 2MHz (0.5us). [DevCTG-A] the input clock is cdclk. [DevCTG-B]
RW the input clock is hrawclk. Example: For 300MHz input clock and desired 2MHz 2X bit
clock, program 150 (300MHz/2MHz).

14.11.127 DPC_AUX_CH_DATA1—Offset 64214h

Display Port C AUX Data Register 1 [DevCTG, DevCDV] AuxC Data1 (dprrega_b0.v
auxc_dpr_data1, ql_auxc_d1)

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) DPC_AUX_CH_DATA1: [GTTMMADR_LSB + 2BF20h] + 64214h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
AUX_CH_DATA1_31

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644 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

0b AUX_CH_DATA1_31: 0]: The first DWord of the message. The MSbyte is transmitted
31:0
RW first. Reads will give the response data after transaction complete.

14.11.128 DPC_AUX_CH_DATA2—Offset 64218h

Display Port C AUX Data Register 2 [DevCTG, DevCDV] AuxC Data2 (dprrega_b0.v
auxc_dpr_data2, ql_auxc_d2)

Access Method
Type: Memory Mapped I/O Register
DPC_AUX_CH_DATA2: [GTTMMADR_LSB + 2BF20h] + 64218h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
AUX_CH_DATA2_31

Bit Default &

Description
Range Access

0b AUX_CH_DATA2_31: 0]: The second DWord of the message. The MSbyte is

31:0 transmitted first. Only used if the message size is greater than 4. Reads will give the
RW response data after transaction complete.

14.11.129 DPC_AUX_CH_DATA3—Offset 6421Ch

Display Port C AUX Data Register 3 [DevCTG, DevCDV] AuxC Data3 (dprrega_b0.v
auxc_dpr_data3, ql_auxc_d3)

Access Method
Type: Memory Mapped I/O Register DPC_AUX_CH_DATA3: [GTTMMADR_LSB + 2BF20h] + 6421Ch
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

Datasheet 645
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

AUX_CH_DATA3_31
Bit Default &
Description
Range Access

0b AUX_CH_DATA3_31: 0]: The third DWord of the message. The MSbyte is transmitted
31:0 first. Only used if the message size is greater than 8. Reads will give the response data
RW after transaction complete.

14.11.130 DPC_AUX_CH_DATA4—Offset 64220h

Display Port C AUX Data Register 4 [DevCTG, DevCDV] AuxC Data4 (dprrega_b0.v
auxc_dpr_data4, ql_auxc_d4)

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) DPC_AUX_CH_DATA4: [GTTMMADR_LSB + 2BF20h] + 64220h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
AUX_CH_DATA4_31

Bit Default &

Description
Range Access

0b AUX_CH_DATA4_31: 0]: The fourth DWord of the message. The MSbyte is

31:0 transmitted first. Only used if the message size is greater than 12. Reads will give the
RW response data after transaction complete.

14.11.131 DPC_AUX_CH_DATA5—Offset 64224h

Display Port C AUX Data Register 5 [DevCTG, DevCDV] AuxC Data5 (dprrega_b0.v
auxc_dpr_data5, ql_auxc_d5)

Access Method

Bay Trail-I SoC

646 Datasheet
Graphics, Video and Display

Type: Memory Mapped I/O Register

DPC_AUX_CH_DATA5: [GTTMMADR_LSB + 2BF20h] + 64224h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

AUX_CH_DATA5_31
Bit Default &
Description
Range Access

0b AUX_CH_DATA5_31: 0]: The fifth DWord of the message. The MSbyte is transmitted
31:0 first. Only used if the message size is greater than 16. Reads will give the response data
RW after transaction complete.

14.11.132 DPC_AUX_TST—Offset 64228h

Display Port C AUX Test Register

Access Method
Type: Memory Mapped I/O Register DPC_AUX_TST: [GTTMMADR_LSB + 2BF20h] + 64228h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

Datasheet 647
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DPC_AUX_BUFFER_LOOPBACK_TEST_DONE

DPC_AUX_DEBUG_STATUS_READBACK
DPC_AUX_BUFFER_LOOPBACK_TEST_ENABLE

DPC_AUX_BUFFER_LOOPBACK_TEST_RESULT

DPC_AUX_LESS_GOOD_SYNC_0S_REQUIRED
DPC_AUX_FULL_TEST_ENABLE

RESERVED

DPC_AUX_CONSTANT_0S_TEST_PATTERN

DPC_AUX_DEGLITCH_AMOUNT

DPC_AUX_MULTIPLE_RECEIVED_EDGES_ERROR_ENABLE
DPC_AUX_SHORT_SYNC

RESERVED_1

RESERVED_2
DPC_AUX_TIGHTEN_FREQUENCY_WINDOW
Bit Default &
Description
Range Access

0b DPC_AUX_BUFFER_LOOPBACK_TEST_ENABLE: Project: All Default Value: 0b See

31 DPB description. Value Name Description Project 0b Disable Test disabled All 1b Enable
RW Enable test. All
DPC_AUX_BUFFER_LOOPBACK_TEST_DONE: Project: All Default Value: 0b
0b AccessType: Read Only See DPB description. Value Name Description Project 0b Not
30
RO Done Test not done. DP-AUX Buffer Loopback Test Result is not valid All 1b Done Test
done. DP-AUX Buffer Loopback Test Result is now valid All

0b DPC_AUX_BUFFER_LOOPBACK_TEST_RESULT: Project: All Default Value: 0b

29 AccessType: Read Only See description for DPB-AUX Buffer Loopback Test Result Value
RO Name Description Project 0b Pass Pass All 1b Fail Fail All

0b DPC_AUX_FULL_TEST_ENABLE: Project: All Default Value: 0b See DPB description.

28
RW Value Name Description Project 0b Disable Test disabled All 1b Enable Enable test All

0b
27:16 RESERVED: Project: All Format:
RW
0b
15 DPC_AUX_SHORT_SYNC: Project: All See DPB description.
RW
0b
14 DPC_AUX_CONSTANT_0S_TEST_PATTERN: Project: All See DPB description.
RW
0b
13 DPC_AUX_TIGHTEN_FREQUENCY_WINDOW: Project: All See DPB description.
RW
0b
12 DPC_AUX_LESS_GOOD_SYNC_0S_REQUIRED: Project: All See DPB description.
RW
DPC_AUX_DEGLITCH_AMOUNT: Project: All Default Value: 0b See DPB description.
0b Value Name Description Project 00b 50 ns 25 clocks - GMBUS type - 50ns at 500MHz
11:10 cdclk All 01b 125 ns 1/4 2X bit clock divider value - 125ns All 10b 62.5 ns 1/8 2X bit
RW clock divider value - 62.5ns All 11b 31.125 ns 1/16 2X bit clock divider value - 31.125ns
All

0b
9 RESERVED_1: Project: All Format:
RW

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648 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

0b DPC_AUX_MULTIPLE_RECEIVED_EDGES_ERROR_ENABLE: Project: All Default

8 Value: 0b Value Name Description Project 0b Okay Multiple edges in window is okay All
RW 1b Error Multiple edges in window is an error All
DPC_AUX_DEBUG_STATUS_READBACK: Project: All Default Value: 0b Value Name
0b Description Project 00b Program Readback of bit clock divide field gives the
7:6 programmed clock frequency All 01b Recover Readback of bit clock divide field gives the
RW recovered clock frequency All 10b Error Type Readback of bit clock divide field gives the
error type All

0b
5:0 RESERVED_2: Project: All Format:
RW

14.11.133 STREAM_A_LPE_AUD_CONFIG—Offset 65000h

LPE Audio Configuration

Access Method
Type: Memory Mapped I/O Register STREAM_A_LPE_AUD_CONFIG: [GTTMMADR_LSB + 2BF20h] +
(Size: 32 bits) 65000h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000280h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0

SET_BLOCK_BEGIN_FOR_ALL_SUB_PACKETS
BOGUS_SAMPLE_DISABLE_FOR_ODD_CHANNEL

_16_BIT_CONTAINER
LPE_HDMI_DP_MODE_ON_STREAM_A

SAMPLE_FLAT_BIT
LPE_STREAM_A_PAUSE_RESUME

LEFT_ALIGNMENT

UNDERRUN_PACKET_BIT_SILENT_STREAM_ENABLE

VALIDITY_BIT_V

NUM_AUDIO_CHANNELS

FORMAT

LAYOUT
AUDIO_ENABLE
RESERVED

USER_BIT_U

Bit Default &

Description
Range Access

0b
31:17 RESERVED: Reserved.
RW

Bay Trail-I SoC

Datasheet 649
 Graphics, Video and Display

Bit Default &

Description
Range Access

LPE_STREAM_A_PAUSE_RESUME: DMA pause fetching at the boundary of buffers

when this bit is set, and resume fetching when this bit is cleared. 1- DMA stop
0b requesting more audio sample from buffer A,B,C,D after reading and depleting all data
16 from current buffer 0- DMA resume requesting data from the next available buffer
RW (A,B,C,D). Programming note: this bit should not be used by SW driver. When SW driver
wants to pause audio, it shall invalidate the two newest allocated audio buffers. When
the current audio buffers are processed, silent stream is sent automatically
0b
15 LPE_HDMI_DP_MODE_ON_STREAM_A: 1 = DP mode 0 = HDMI mode (default)
RW
BOGUS_SAMPLE_DISABLE_FOR_ODD_CHANNEL: When number of channels in a
0b sample is odd (3, 5, or 7) source application may pad a bogus sample to the next even
14 number of channels. If this bit is set there is no padding in input buffer1= No bogus
RW sample present in buffer for odd number of channels 0= Bogus sample present in buffer
for odd number of channels (default)
LEFT_ALIGNMENT: When input buffer is in 32-bit container mode. If this bit is set the
0b MSB of audio sample is aligned bit 31 of the container if this bit is clear MSB of audio
13
RW sample is aligned with bit 23 of the container.1= MSB is bit 31 of 32-bit container 0=
MSB is bit 23 of 32-bit container (default)

0b _16_BIT_CONTAINER: When this bit is set 16-bit sample is stored in 16-bit container
12 format. When it is clear container is 32-bit for each sample regardless of valid bits
RW (default)1= 16-bit container 0= 32-bit container
UNDERRUN_PACKET_BIT_SILENT_STREAM_ENABLE: Set this bit will enble HW to
send valid zero-filled packet with Sample flat bit set when no sample buffer is available,
0b NCTS packets (or Timesstamp packet) are sent to keep sink in sync even no audio
11 sound will heard.1= send underrun packets (silent stream) 0= send null packets
RW (default) Programming note: SW driver shall always set silent stream bit. When SW
driver wants to pause audio, it shall invalidate the two newest allocated audio buffers.
When the current audio buffers are processed, silent stream is sent automatically.

0b USER_BIT_U: HW will clear this bit ineach sub-frames it sends, But this bit allows to
10 overwrite hardware setting for special operation like debug or testing for compliance 1=
RW sey U bit in sub-frame 0= clear U bit in sub-frame (default)

VALIDITY_BIT_V: HW will set this bit in both each sub-frames it sends. But this bit
1b allows to overwrite hardware setting for special operation like debug or testing for
9
RW compliance 1= Set V bit in sub-frame (default) 0= clear V bit in sub-frame. For debug or
testing
0b SAMPLE_FLAT_BIT: When set the sample flat bit will be set in all HDMI sub-packets.
8
RW 1= flat bit is set for valid sample 0= flat bit is not set for valid sample (default)

SET_BLOCK_BEGIN_FOR_ALL_SUB_PACKETS: Controls the B bit in the header of

1b only the first Audio Packet /frame of a 192 frame 60958 block in Layout 1 mode. This bit
7
RW only applies to LPE HDMI mode. 0: The B bit will be set only for sub-packet 0 1: The B
bit in the Audio sample packet header will be set for all valid sub-packets. (default)

NUM_AUDIO_CHANNELS: 000: 2 channels (stereo) 001: 3 channels 010: 4 channels

011: 5 channels 100: 6 channels 101: 7 channels 110: 8 channels Note: When
0b disable_bogus sample bit is clear HW will always treat odd number of channels similar to
6:4 the next higher even number. Thus 3 is similar to 4, 5 to 6 and 7 to 8. This is because
RW SW ensures that an even number of samples are packed in the audio buffers.
Programming note: Bit 6 of of this field is a write only bit. When reads back, it always
returns zero. Ensure to write bit 6 to 1?b1 when programming for 6/7/8 audio channels.

0b FORMAT: 00: L-PCM or IEC 61937 01: High Bit Rate IEC 61937 stream packet (not
3:2 supported) 10: One Bit Audio Sample packet (not supported) 11: DST Audio Sample
RW packet (not supported)
0b LAYOUT: 0: Layout 0 (2-ch) 1: Layout 1 (3-8 ch) Note: Layout bit doesn t matter for
1
RW HBR

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650 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

AUDIO_ENABLE: Controls generation of N/CTS and transmission of audio sample

packets. 0: Audio sample packets are not transmitted, CTS calculation/transmission is
0b disabled 1: Audio sample packets are transmitted and CTS calculation is enabled When
0
RW enable audio unit will wait until the next vertical blank period before sending out the
audio packets. When disable, audio unit may continue to send audio packet until the end
of current active video frame before stopping.

14.11.134 STREAM_A_LPE_AUD_CH_STATUS_0—Offset 65008h

Audio Channel Status Attributes 0

Access Method
Type: Memory Mapped I/O Register STREAM_A_LPE_AUD_CH_STATUS_0: [GTTMMADR_LSB +
(Size: 32 bits) 2BF20h] + 65008h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CHANNEL_STATUS_REGISTER_0

Bit Default &

Description
Range Access

0b CHANNEL_STATUS_REGISTER_0: . These bits are transmitted as attributes of audio

31:0
RW packets

14.11.135 STREAM_A_LPE_AUD_CH_STATUS_1—Offset 6500Ch

Audio Channel Status Attributes 1

Access Method
Type: Memory Mapped I/O Register STREAM_A_LPE_AUD_CH_STATUS_1: [GTTMMADR_LSB +
(Size: 32 bits) 2BF20h] + 6500Ch

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

Datasheet 651
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESERVED

CHANNEL_STATUS_REGISTER_1
Bit Default &
Description
Range Access

0b
31:8 RESERVED: Reserved.
RW

0b CHANNEL_STATUS_REGISTER_1: . These bits are transmitted as attributes of audio

7:0
RW packets. There is only 8 bits valid in this register.

14.11.136 STREAM_A_LPE_AUD_HDMI_CTS_DP_MAUD—Offset 65010h

Audio HDMI CTS Register (DP Maud)

Access Method
Type: Memory Mapped I/O Register STREAM_A_LPE_AUD_HDMI_CTS_DP_MAUD:
(Size: 32 bits) [GTTMMADR_LSB + 2BF20h] + 65010h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENABLE_CTS_M_PROGRAMMING

HDMI_CTS_VALUES
RESERVED

Bit Default &

Description
Range Access

0b
31:25 RESERVED: Reserved.
RW

Bay Trail-I SoC

652 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

0b ENABLE_CTS_M_PROGRAMMING: 1 = Enable CTS/M programming 0 = Disable CTS/

24
RW M programming

HDMI_CTS_VALUES: These are bits [23:0] of programmable HDMI CTS values (or DP
0b Maud) that is pre-calculated to achieve desired audio sample rates with a particular
23:0
RW pixel clocks configuration. Audio function must be disabled when changing this field. Bit
24 also need to write to 1 to enable this field.

14.11.137 STREAM_A_LPE_AUD_HDMI_N_DP_NAUD—Offset 65014h

Audio HDMI N Register (DP Naud)

Access Method
Type: Memory Mapped I/O Register STREAM_A_LPE_AUD_HDMI_N_DP_NAUD: [GTTMMADR_LSB
(Size: 32 bits) + 2BF20h] + 65014h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENABLE_N_PROGRAMMING

HDMI_N_VALUES
RESERVED

Bit Default &

Description
Range Access

0b
31:25 RESERVED: Reserved.
RW
0b
24 ENABLE_N_PROGRAMMING: 1 = Enable N programming 0 = Disable N programming
RW
HDMI_N_VALUES: These are bits [23:0] of programmable HDMI N (or DP Naud)
0b values that is pre-calculated to achieve desired audio sample rates with a particular
23:0
RW pixel clocks configuration. Audio function must be disabled when changing this field. Bit
24 also need to write to 1 to enable this field.

14.11.138 STREAM_A_LPE_AUD_BUFFER_CONFIG—Offset 65020h

LPE Audio buffer config

Access Method

Bay Trail-I SoC

Datasheet 653
 Graphics, Video and Display

Type: Memory Mapped I/O Register STREAM_A_LPE_AUD_BUFFER_CONFIG: [GTTMMADR_LSB +

(Size: 32 bits) 2BF20h] + 65020h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000100h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0

AUDIO_BUFFER_DELAY

AUDF_FIFO_WATERMARK
RESERVED

RESERVED_1

DMA_FIFO_WATERMARK
Bit Default &
Description
Range Access

0b
31:24 RESERVED: Reserved.
RW

0b AUDIO_BUFFER_DELAY: This field specifies a delay in number of video frames that

23:16 the audio controller will count off when audio enable bit is set before start transmitting
RW audio sample.

0b
15:11 RESERVED_1: Reserved.
RW

DMA_FIFO_WATERMARK: Audio unit has a 8x64 bytes fifo for pre-fetching and
staging audio samples. This register provides a watermark value in SWORDs (64B).
001b When enable and sample buffer is available audio unit will fetch samples until this FIFO
10:8
RW is full then it waits until HDMI/DP packet assembler drains the samples to a level less or
equal the watermark setting then it will start fetching the samples again. Default value
is 1 cacheline (SW).

AUDF_FIFO_WATERMARK: Audio unit has a 96x8 bytes fifo for pre-fetching and
staging audio samples. This register provides a watermark value in DWORDs. When
0b enable and sample buffer is available audio unit will fetch samples until this FIFO
7:0
RW occupancy is above the watermark then it waits until HDMI packet assembler drains the
samples to a level less or equal the watermark setting then it will start fetching the
samples again

14.11.139 STREAM_A_LPE_AUD_BUF_CH_SWP—Offset 65024h

Audio Sample Swapping

Access Method
Type: Memory Mapped I/O Register STREAM_A_LPE_AUD_BUF_CH_SWP: [GTTMMADR_LSB +
(Size: 32 bits) 2BF20h] + 65024h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00FAC688h

Bay Trail-I SoC

654 Datasheet
Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0

RESERVED

SAMPLE_INDEX_FOR_FIRST_CHANNEL_OF_SUBPACKET_3

SAMPLE_INDEX_FOR_FIRST_CHANNEL_OF_SUBPACKET_2

SAMPLE_INDEX_FOR_FIRST_CHANNEL_OF_SUBPACKET_1

SAMPLE_INDEX_FOR_FIRST_CHANNEL_OF_SUBPACKET_0
SAMPLE_INDEX_FOR_SECOND_CHANNEL_OF_SUBPACKET_3

SAMPLE_INDEX_FOR_SECOND_CHANNEL_OF_SUBPACKET_2

SAMPLE_INDEX_FOR_SECOND_CHANNEL_OF_SUBPACKET_1

SAMPLE_INDEX_FOR_SECOND_CHANNEL_OF_SUBPACKET_0
Bit Default &
Description
Range Access

0b
31:24 RESERVED: Reserved.
RO

111b SAMPLE_INDEX_FOR_SECOND_CHANNEL_OF_SUBPACKET_3: This field has the

23:21 index of 32-byte buffer block that will be send out as the second channel sample of
RO subpacket 3 in a HDMI audio packet

110b SAMPLE_INDEX_FOR_FIRST_CHANNEL_OF_SUBPACKET_3: This field has the

20:18 index of 32-byte buffer block that will be send out as the first channel sample of
RO subpacket 1 in a HDMI audio packet

101b SAMPLE_INDEX_FOR_SECOND_CHANNEL_OF_SUBPACKET_2: This field has the

17:15 index of 32-byte buffer block that will be send out as the second channel sample of
RO subpacket 0 in a HDMI audio packet

100b SAMPLE_INDEX_FOR_FIRST_CHANNEL_OF_SUBPACKET_2: This field has the

14:12 index of 32-byte buffer block that will be send out as the first channel sample of
RO subpacket 0 in a HDMI audio packet

011b SAMPLE_INDEX_FOR_SECOND_CHANNEL_OF_SUBPACKET_1: This field has the

11:9 index of 32-byte buffer block that will be send out as the second channel sample of
RO subpacket 1 in a HDMI audio packet

010b SAMPLE_INDEX_FOR_FIRST_CHANNEL_OF_SUBPACKET_1: This field has the

8:6 index of 32-byte buffer block that will be send out as the first channel sample of
RO subpacket 1 in a HDMI audio packet

001b SAMPLE_INDEX_FOR_SECOND_CHANNEL_OF_SUBPACKET_0: This field has the

5:3 index of 32-byte buffer block that will be send out as the second channel sample of
RO subpacket 0 in a HDMI audio packet

0b SAMPLE_INDEX_FOR_FIRST_CHANNEL_OF_SUBPACKET_0: This field has the

2:0 index of 32-byte buffer block that will be send out as the first channel sample of
RO subpacket 0 in a HDMI audio packet

Bay Trail-I SoC

Datasheet 655
 Graphics, Video and Display

14.11.140 STREAM_A_LPE_AUD_BUF_A_ADDR—Offset 65040h

Address for Audio Buffer A

Access Method
Type: Memory Mapped I/O Register STREAM_A_LPE_AUD_BUF_A_ADDR: [GTTMMADR_LSB +
(Size: 32 bits) 2BF20h] + 65040h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BUFFER_VALID
BUFFER_ADDRESS

RESERVED

INTERRUPT_ENABLE
Bit Default &
Description
Range Access

0b BUFFER_ADDRESS: . This is physical address of audio sample buffer A, need to 64-

31:6
RW byte aligned.

0b
5:2 RESERVED: Reserved.
RW

0b INTERRUPT_ENABLE: If enable hardware will generate an interrupt when it is done

1
RW fetching this buffer

0b BUFFER_VALID: . This bit is set by S/W when the mem_addr is written and is cleared
0
RW by H/W when done reading the data from memory

14.11.141 STREAM_A_LPE_AUD_BUF_A_LENGTH—Offset 65044h

Length for Audio Buffer A

Access Method
Type: Memory Mapped I/O Register STREAM_A_LPE_AUD_BUF_A_LENGTH: [GTTMMADR_LSB +
(Size: 32 bits) 2BF20h] + 65044h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

656 Datasheet
Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESERVED

BUFFER_LENGTH_
Bit Default &
Description
Range Access

0b
31:20 RESERVED: Reserved.
RW
BUFFER_LENGTH_: This field shows the remaining length of data that needs to be
0b read from memory; Initially set by S/W for total of bytes that are valid and is
19:0
RW decremented by H/W as reads are issued. Software must end buffer at the boundary of
a audio sample with all of channel values of that sample are valid.

14.11.142 STREAM_A_LPE_AUD_BUF_B_ADDR—Offset 65048h

Address for Audio Buffer B

Access Method
Type: Memory Mapped I/O Register STREAM_A_LPE_AUD_BUF_B_ADDR: [GTTMMADR_LSB +
(Size: 32 bits) 2BF20h] + 65048h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BUFFER_ADDRESS

BUFFER_VALID
RESERVED

INTERRUPT_ENABLE

Bit Default &

Description
Range Access

0b BUFFER_ADDRESS: . This is physical address of audio sample buffer A, need to 64-

31:6
RW byte aligned.

0b
5:2 RESERVED: Reserved.
RW
0b INTERRUPT_ENABLE: If enable hardware will generate an interrupt when it is done
1
RW fetching this buffer

0b BUFFER_VALID: . This bit is set by S/W when the mem_addr is written and is cleared
0
RW by H/W when done reading the data from memory

Bay Trail-I SoC

Datasheet 657
 Graphics, Video and Display

14.11.143 STREAM_A_LPE_AUD_BUF_B_LENGTH—Offset 6504Ch

Length for Audio Buffer B

Access Method
Type: Memory Mapped I/O Register STREAM_A_LPE_AUD_BUF_B_LENGTH: [GTTMMADR_LSB +
(Size: 32 bits) 2BF20h] + 6504Ch

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED

BUFFER_LENGTH_
Bit Default &
Description
Range Access

0b
31:20 RESERVED: Reserved.
RW
BUFFER_LENGTH_: This field shows the remaining length of data that needs to be
0b read from memory; Initially set by S/W for total of bytes that are valid and is
19:0
RW decremented by H/W as reads are issued. Software must end buffer at the boundary of
a audio sample with all of channel values of that sample are valid.

14.11.144 STREAM_A_LPE_AUD_BUF_C_ADDR—Offset 65050h

Address for Audio Buffer C

Access Method
Type: Memory Mapped I/O Register STREAM_A_LPE_AUD_BUF_C_ADDR: [GTTMMADR_LSB +
(Size: 32 bits) 2BF20h] + 65050h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BUFFER_ADDRESS

BUFFER_VALID
RESERVED

INTERRUPT_ENABLE

Bay Trail-I SoC

658 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

0b BUFFER_ADDRESS: . This is physical address of audio sample buffer A, need to 64-

31:6
RW byte aligned.

0b
5:2 RESERVED: Reserved.
RW
0b INTERRUPT_ENABLE: If enable hardware will generate an interrupt when it is done
1
RW fetching this buffer

0b BUFFER_VALID: . This bit is set by S/W when the mem_addr is written and is cleared
0
RW by H/W when done reading the data from memory

14.11.145 STREAM_A_LPE_AUD_BUF_C_LENGTH—Offset 65054h

Length for Audio Buffer C

Access Method
Type: Memory Mapped I/O Register STREAM_A_LPE_AUD_BUF_C_LENGTH: [GTTMMADR_LSB +
(Size: 32 bits) 2BF20h] + 65054h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED

BUFFER_LENGTH_

Bit Default &

Description
Range Access

0b
31:20 RESERVED: Reserved.
RW

BUFFER_LENGTH_: This field shows the remaining length of data that needs to be
0b read from memory; Initially set by S/W for total of bytes that are valid and is
19:0
RW decremented by H/W as reads are issued. Software must end buffer at the boundary of
a audio sample with all of channel values of that sample are valid.

14.11.146 STREAM_A_LPE_AUD_BUF_D_ADDR—Offset 65058h

Address for Audio Buffer D

Access Method
Type: Memory Mapped I/O Register STREAM_A_LPE_AUD_BUF_D_ADDR: [GTTMMADR_LSB +
(Size: 32 bits) 2BF20h] + 65058h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Bay Trail-I SoC

Datasheet 659
 Graphics, Video and Display

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BUFFER_VALID
BUFFER_ADDRESS

RESERVED

INTERRUPT_ENABLE
Bit Default &
Description
Range Access

0b BUFFER_ADDRESS: . This is physical address of audio sample buffer A, need to 64-

31:6
RW byte aligned.

0b
5:2 RESERVED: Reserved.
RW

0b INTERRUPT_ENABLE: If enable hardware will generate an interrupt when it is done

1
RW fetching this buffer

0b BUFFER_VALID: . This bit is set by S/W when the mem_addr is written and is cleared
0
RW by H/W when done reading the data from memory

14.11.147 STREAM_A_LPE_AUD_BUF_D_LENGTH—Offset 6505Ch

Length for Audio Buffer D

Access Method
Type: Memory Mapped I/O Register STREAM_A_LPE_AUD_BUF_D_LENGTH: [GTTMMADR_LSB +
(Size: 32 bits) 2BF20h] + 6505Ch

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BUFFER_LENGTH_
RESERVED

Bit Default &

Description
Range Access

0b
31:20 RESERVED: Reserved.
RW
BUFFER_LENGTH_: This field shows the remaining length of data that needs to be
0b read from memory; Initially set by S/W for total of bytes that are valid and is
19:0
RW decremented by H/W as reads are issued. Software must end buffer at the boundary of
a audio sample with all of channel values of that sample are valid.

Bay Trail-I SoC

660 Datasheet
Graphics, Video and Display

14.11.148 STREAM_A_LPE_AUD_CNTL_ST—Offset 65060h

LPE Audio Control State Register

Access Method
Type: Memory Mapped I/O Register STREAM_A_LPE_AUD_CNTL_ST: [GTTMMADR_LSB + 2BF20h]
(Size: 32 bits) + 65060h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DIP_TYPE_ENABLE_STATUS_READ_ONLY
RESERVED

DIP_BUFFER_INDEX_R_W

CP_READY

DIP_RAM_ACCESS_ADDRESS_R_W
RESERVED_1

RESERVED_

DIP_TRANSMISSION_FREQUENCY_R_W

RESERVED_2

RESERVED__1

RESERVED_3
RESERVED_R_W

Bit Default &

Description
Range Access

0b
31 RESERVED: Reserved.
RW

0b
30:29 RESERVED_1: Reserved.
RW
0b
28:25 RESERVED_: for later DIP type if needed: Must be 0.
RW
DIP_TYPE_ENABLE_STATUS_READ_ONLY: These bits reflects the DIP types
enabled. It can be updated while the port is enabled. Within 2 vblank periods, the DIP is
0b guaranteed to have been transmitted. Disabling an DIP type results in setting the
24:21 contents of that DIP buffer to zero. A reserved setting reflects a disabled DIP. XXX1 =
RW Audio DIP enable status (Default = disabled) XX1X = Generic 1 (ACP) DIP enable status
(Default = disabled) X1XX = Generic 2 DIP enable status, can be used by ISRC1 or
ISRC2 (Default = disabled) 1XXX = Reserved
DIP_BUFFER_INDEX_R_W: This field is used during read or write of different DIPs,
and during read or write of ELD data. These bits are used as an index to their respective
DIP or ELD buffers. When the index is not valid, the contents of the DIP will return all 0
0b s. 000 = (Default) Audio DIP (31 bytes of address space, 13 bytes of data) 001 =
20:18
RW Generic 1 (ACP) Data Island Packet (31 bytes of address space, 11 bytes of data) 010 =
Generic 2 (ISRC1) Data Island Packet (31 bytes of address space, 31 bytes of data) 011
= Generic 3 (ISRC2) Data Island Packet (31 bytes of address space, 31 bytes of data)
1XX = reserved

Bay Trail-I SoC

Datasheet 661
 Graphics, Video and Display

Bit Default &

Description
Range Access

DIP_TRANSMISSION_FREQUENCY_R_W: These bits reflect the frequency of DIP

transmission for the DIP buffer type designated in bits 20:18. When writing DIP data,
0b this value is also latched when the first DW of the DIP is written.When read, this value
17:16
RW reflects the DIP transmission frequency for the DIP buffer designated in bits 20:18. 00 =
Disabled (Default) 01 = once per frame 10 = Send once 11 = Best effort (Send at least
every other vsync)
CP_READY: This R/W bit reflects the state of CP request from the audio unit. When an
audio CP request has been serviced, it must be reset to 1 by the video software to
0b indicate that the CP request has been serviced. 0 = CP request pending or not ready to
15
RW receive requests (default) 1 = CP request ready CP_ready bit is programmable through
Bit 14 for [DevCL, DevBLC]. CP_ready bit is programmable through Bit 15 for [DevCTG].
Bit 15 Reserved for [DevCL, DevBLC].
RESERVED_R_W: ELD valid: This bit reflects the state of the ELD data written to the
ELD RAM. After writing the ELD data, the video software must set this bit to 1 to indicate
that the ELD data is valid. At audio codec initialization, or on a hotplug event, this bit is
0b set to 0 by the video software. This bit is reflected in the audio pin complex widget as
14
RW the ELD valid status bit.0 = ELD data invalid (default, when writing ELD data, set 0 by
software) 1 = ELD data valid (Set by video software only) ELD bit is programmable
through Bit 13 for [DevCL, DevBLC]. ELD bit is programmable through Bit 14 for
[DevCTG].

0b RESERVED_2: ELD buffer size (read only)10000 = This field reflects the size of the ELD
13:9 buffer in DWORDs 13:9 reflects ELD buffer size for [DevCTG]. 12:9 reflects ELD buffer
RW size for [DevCL, DevBLC].

RESERVED__1: ELD access address (R/W): Selects the DWORD address for access to
0b the ELD buffer (48 bytes). The value wraps back to zero when incremented past the
8:5
RW max addressing value 0xF. This field change takes effect immediately after being
written. The read value indicates the current access address.
0b RESERVED_3: ELD ACK: Acknowledgement from the audio driver that ELD read has
4
RW been completed

DIP_RAM_ACCESS_ADDRESS_R_W: Selects the DWORD address for access to the

0b DIP buffers. The value wraps back to zero when it incremented past the max addressing
3:0
RW value of 0xF. This field change takes effect immediately after being written. The read
value indicates the current access address.

14.11.149 STREAM_A_LPE_AUD_HDMI_STATUS—Offset 65064h

LPE Audio Status

Access Method
Type: Memory Mapped I/O Register STREAM_A_LPE_AUD_HDMI_STATUS: [GTTMMADR_LSB +
(Size: 32 bits) 2BF20h] + 65064h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

662 Datasheet
Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

LPE_AUDIO_BUFFER_DONE_STATUS

AUDIO_BANDWIDTH_UNDERRUN_INTERRUPT_ENABLE

AZALIA_COMPATIBLE_MODE
SAMPLE_BUFFER_UNDERRUN

RESERVED

SAMPLE_BUFFER_UNDERRUN_INTERRUPT_ENABLE
NUMBER_OF_SAMPLES_BEHIND_DEBUG

AUDIO_SAMPLE_RUN_RATE_DEBUG
FUNCTION_RESET_R_W_ONLY
AUDIO_BANDWIDTH_UNDERRUN_DEBUG

RESERVED_1
Bit Default &
Description
Range Access

SAMPLE_BUFFER_UNDERRUN: This bit indicates an underrun in the sample buffer to

0b HDMI controller when it needs to send. This bit is set at the last line of active video
31 when there are no more sample in any valid buffers and HDMI audio unit has not
RW/1C satisfied number of audio samples intended in that video frame. Clearing this status bit
is accomplished by writing a 1 to this bit through MMIO. AccessType: One to Clear

AUDIO_BANDWIDTH_UNDERRUN_DEBUG: This bit indicates an underrun of audio

samples at HDMI audio packet assembly even there is still available sample buffers.
Audio bandwidth underrun should not happen in normal functionality but it may happen
0b when audio setting is unappropriate and/or memory bus was blocked by other clients,
30
RW/1C etc... This bit is set at the last line of active video when there is valid samples in a valid
buffer and HDMI audio unit has not satisfied number of audio samples intended in that
video frame Clearing this status bit is accomplished by writing a 1 to this bit through
MMIO. AccessType: One to Clear

0b LPE_AUDIO_BUFFER_DONE_STATUS: This bit is set when a LPE audio buffer is

29 completed transferred all of its data to LPE audio unit. This bit is clear when write 1 to it
RW/1C AccessType: One to Clear

0b
28:24 RESERVED: Reserved.
RW

0b NUMBER_OF_SAMPLES_BEHIND_DEBUG: This field is read only to get the number

23:16 of audio samples that controller needs to load and send at the time of reading.
RO AccessType: Read Only

SAMPLE_BUFFER_UNDERRUN_INTERRUPT_ENABLE: This bit is to enable the first

0b line buffer underrun interrupt when sample buffer underrun status is detected 0 = LPE
15
RW sample Buffer Underrun Interrupt Disabled 1 = LPE sample Buffer Underrun Interrupt
Enabled
AUDIO_BANDWIDTH_UNDERRUN_INTERRUPT_ENABLE: This bit is to enable the
0b first line bandwidth underrun interrupt when bandwidth underrun status is detected 0 =
14
RW LPE Bandwidth Underrun Interrupt Disabled 1 = LPE Bandwidth Underrun Interrupt
Enabled
0b
13:3 RESERVED_1: Reserved.
RW

Bay Trail-I SoC

Datasheet 663
 Graphics, Video and Display

Bit Default &

Description
Range Access

0b AZALIA_COMPATIBLE_MODE: This bit is to enable the vucp, PR, ECC to be generated

2 in the Azalia way 0 = Disable Azalia compatible mode on vucp, PR, ECC 1 = Enable
RW Azalia compatible mode on vucp, PR, ECC
0b AUDIO_SAMPLE_RUN_RATE_DEBUG: When set it allows to fetch sample 128 times
1
RW than the real sample rate to allow a faster drain of sample bufferes.

FUNCTION_RESET_R_W_ONLY: Write 1 to this bit will reset hardware within audio

0b unit without needs of reset the full display controller. The FIFO and pointers will be reset
0
RW and audio registers will be reset to default values. Write 0 will put the unit back to idle
and ready to be programmed again.

14.11.150 STREAM_A_LPE_AUD_HDMIW_INFOFR—Offset 65068h

Audio HDMI Data Island Packet Data

Access Method
Type: Memory Mapped I/O Register STREAM_A_LPE_AUD_HDMIW_INFOFR: [GTTMMADR_LSB +
(Size: 32 bits) 2BF20h] + 65068h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DATA_ISLAND_PACKET_DATA

Bit Default &

Description
Range Access

DATA_ISLAND_PACKET_DATA: When read, this returns the current value at the

location specified in the Video DIP buffer index select and Video DIP RAM access address
0b fields. The index used to address the RAM is incremented after each read or write of this
31:0
RW register. DIP data can be read at any time. Data should be loaded into the RAM before
enabling the transmission through the DIP type enable bit. Accesses to this register are
on a per-DWORD basis

14.11.151 STREAM_B_LPE_AUD_CONFIG—Offset 65800h

LPE Audio Configuration

Access Method

Bay Trail-I SoC

664 Datasheet
Graphics, Video and Display

Type: Memory Mapped I/O Register STREAM_B_LPE_AUD_CONFIG: [GTTMMADR_LSB + 2BF20h] +

(Size: 32 bits) 65800h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000280h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0

SET_BLOCK_BEGIN_FOR_ALL_SUB_PACKETS
LPE_HDMI_DP_MODE_ON_STREAM_B
BOGUS_SAMPLE_DISABLE_FOR_ODD_CHANNEL

UNDERRUN_PACKET_BIT_SILENT_STREAM_ENABLE
USER_BIT_U
_16_BIT_CONTAINER

NUM
LPE_STREAM_B_PAUSE_RESUME

LEFT_ALIGNMENT

VALIDITY_BIT_V
SAMPLE_FLAT_BIT

FORMAT

LAYOUT
AUDIO_ENABLE
RESERVED

Bit Default &

Description
Range Access

0b
31:17 RESERVED: Reserved.
RW
LPE_STREAM_B_PAUSE_RESUME: DMA pause fetching at the boundary of buffers
when this bit is set, and resume fetching when this bit is cleared. 1- DMA stop
0b requesting more audio sample from buffer A,B,C,D after reading and depleting all data
16 from current buffer 0- DMA resume requesting data from the next available buffer
RW (A,B,C,D). Programming note: this bit should not be used by SW driver. When SW driver
wants to pause audio, it shall invalidate the two newest allocated audio buffers. When
the current audio buffers are processed, silent stream is sent automatically.
0b
15 LPE_HDMI_DP_MODE_ON_STREAM_B: 1= DP mode 0 = HDMI mode (default)
RW
BOGUS_SAMPLE_DISABLE_FOR_ODD_CHANNEL: When number of channels in a
0b sample is odd (3, 5, or 7) source application may pad a bogus sample to the next even
14 number of channels. If this bit is set there is no padding in input buffer1= No bogus
RW sample present in buffer for odd number of channels 0= Bogus sample present in buffer
for odd number of channels (default)

LEFT_ALIGNMENT: When input buffer is in 32-bit container mode. If this bit is set the
0b MSB of audio sample is aligned bit 31 of the container if this bit is clear MSB of audio
13
RW sample is aligned with bit 23 of the container.1= MSB is bit 31 of 32-bit container 0=
MSB is bit 23 of 32-bit container (default)

0b _16_BIT_CONTAINER: When this bit is set 16-bit sample is stored in 16-bit container
12 format. When it is clear container is 32-bit for each sample regardless of valid bits
RW (default)1= 16-bit container 0= 32-bit container

Bay Trail-I SoC

Datasheet 665
 Graphics, Video and Display

Bit Default &

Description
Range Access

UNDERRUN_PACKET_BIT_SILENT_STREAM_ENABLE: Set this bit will enble HW to

send valid zero-filled packet with Sample flat bit set when no sample buffer is available,
0b NCTS packets (or Timesstamp packet) are sent to keep sink in sync even no audio
11 sound will heard.1= send underrun packets (silent stream) 0= send null packets
RW (default) Programming note: SW driver shall always set silent stream bit. When SW
driver wants to pause audio, it shall invalidate the two newest allocated audio buffers.
When the current audio buffers are processed, silent stream is sent automatically.

0b USER_BIT_U: HW will clear this bit ineach sub-frames it sends, But this bit allows to
10 overwrite hardware setting for special operation like debug or testing for compliance 1=
RW sey U bit in sub-frame 0= clear U bit in sub-frame (default)
VALIDITY_BIT_V: HW will set this bit in both each sub-frames it sends. But this bit
1b allows to overwrite hardware setting for special operation like debug or testing for
9
RW compliance 1= Set V bit in sub-frame (default) 0= clear V bit in sub-frame. For debug or
testing

0b SAMPLE_FLAT_BIT: When set the sample flat bit will be set in all HDMI sub-packets.
8
RW 1= flat bit is set for valid sample 0= flat bit is not set for valid sample (default)

SET_BLOCK_BEGIN_FOR_ALL_SUB_PACKETS: Controls the B bit in the header of

1b only the first Audio Packet /frame of a 192 frame 60958 block in Layout 1 mode. This bit
7
RW only applies to LPE HDMI mode. 0: The B bit will be set only for sub-packet 0 1: The B
bit in the Audio sample packet header will be set for all valid sub-packets. (default)
NUM: audio Channels 000: 2 channels (stereo) 001: 3 channels 010: 4 channels 011: 5
channels 100: 6 channels 101: 7 channels 110: 8 channels Note: When disable_bogus
0b sample bit is clear HW will always treat odd number of channels similar to the next
6:4 higher even number. Thus 3 is similar to 4, 5 to 6 and 7 to 8. This is because SW
RW ensures that an even number of samples are packed in the audio buffers. Programming
note: Bit 6 of of this field is a write only bit. When reads back, it always returns zero.
Ensure to write bit 6 to 1?b1 when programming for 6/7/8 audio channels.

0b FORMAT: 00: L-PCM or IEC 61937 01: High Bit Rate IEC 61937 stream packet (not
3:2 supported) 10: One Bit Audio Sample packet (not supported) 11: DST Audio Sample
RW packet (not supported)
0b LAYOUT: 0: Layout 0 (2-ch) 1: Layout 1 (3-8 ch) Note: Layout bit doesn t matter for
1
RW HBR

AUDIO_ENABLE: Controls generation of N/CTS and transmission of audio sample

packets. 0: Audio sample packets are not transmitted, CTS calculation/transmission is
0b disabled 1: Audio sample packets are transmitted and CTS calculation is enabled When
0
RW enable audio unit will wait until the next vertical blank period before sending out the
audio packets. When disable, audio unit may continue to send audio packet until the end
of current active video frame before stopping.

14.11.152 STREAM_B_LPE_AUD_CH_STATUS_0—Offset 65808h

Audio Channel Status Attributes 0

Access Method
Type: Memory Mapped I/O Register STREAM_B_LPE_AUD_CH_STATUS_0: [GTTMMADR_LSB +
(Size: 32 bits) 2BF20h] + 65808h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

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666 Datasheet
Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CHANNEL_STATUS_REGISTER_0
Bit Default &
Description
Range Access

0b CHANNEL_STATUS_REGISTER_0: . These bits are transmitted as attributes of audio

31:0
RW packets

14.11.153 STREAM_B_LPE_AUD_CH_STATUS_1—Offset 6580Ch

Audio Channel Status Attributes 1

Access Method
Type: Memory Mapped I/O Register STREAM_B_LPE_AUD_CH_STATUS_1: [GTTMMADR_LSB +
(Size: 32 bits) 2BF20h] + 6580Ch

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED

CHANNEL_STATUS_REGISTER_1

Bit Default &

Description
Range Access

0b
31:8 RESERVED: Reserved.
RW
0b CHANNEL_STATUS_REGISTER_1: . These bits are transmitted as attributes of audio
7:0
RW packets. There is only 8 bits valid in this register.

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Datasheet 667
 Graphics, Video and Display

14.11.154 STREAM_B_LPE_AUD_HDMI_CTS_DP_MAUD—Offset 65810h

Audio HDMI CTS Register (DP Maud)

Access Method
Type: Memory Mapped I/O Register STREAM_B_LPE_AUD_HDMI_CTS_DP_MAUD:
(Size: 32 bits) [GTTMMADR_LSB + 2BF20h] + 65810h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED

HDMI_CTS_VALUES
ENABLE_CTS_M_PROGRAMMING

Bit Default &

Description
Range Access

0b
31:25 RESERVED: Reserved.
RW
0b ENABLE_CTS_M_PROGRAMMING: 1 = Enable CTS/M programming 0 = Disable CTS/
24
RW M programming

HDMI_CTS_VALUES: These are bits [23:0] of programmable HDMI CTS values (or DP
0b Maud) that is pre-calculated to achieve desired audio sample rates with a particular
23:0
RW pixel clocks configuration. Audio function must be disabled when changing this field. Bit
24 also need to write to 1 to enable this field.

14.11.155 STREAM_B_LPE_AUD_HDMI_N_DP_NAUD—Offset 65814h

Audio HDMI N Register (DP Naud)

Access Method
Type: Memory Mapped I/O Register STREAM_B_LPE_AUD_HDMI_N_DP_NAUD: [GTTMMADR_LSB
(Size: 32 bits) + 2BF20h] + 65814h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

668 Datasheet
Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESERVED

HDMI_N_VALUES
ENABLE_N_PROGRAMMING

Bit Default &

Description
Range Access

0b
31:25 RESERVED: Reserved.
RW

0b
24 ENABLE_N_PROGRAMMING: 1 = Enable N programming 0 = Disable N programming
RW

HDMI_N_VALUES: These are bits [23:0] of programmable HDMI N (or DP Naud)

0b values that is pre-calculated to achieve desired audio sample rates with a particular
23:0
RW pixel clocks configuration. Audio function must be disabled when changing this field. Bit
24 also need to write to 1 to enable this field.

14.11.156 STREAM_B_LPE_AUD_BUFFER_CONFIG—Offset 65820h

LPE Audio buffer config

Access Method
Type: Memory Mapped I/O Register STREAM_B_LPE_AUD_BUFFER_CONFIG: [GTTMMADR_LSB +
(Size: 32 bits) 2BF20h] + 65820h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000100h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
AUDIO_BUFFER_DELAY

DMA_FIFO_WATERMARK

FIFO_WATERMARK
RESERVED

RESERVED_1

Bit Default &

Description
Range Access

0b
31:24 RESERVED: Reserved.
RW

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Datasheet 669
 Graphics, Video and Display

Bit Default &

Description
Range Access

0b AUDIO_BUFFER_DELAY: This field specifies a delay in number of video frames that

23:16 the audio controller will count off when audio enable bit is set before start transmitting
RW audio sample.
0b
15:11 RESERVED_1: Reserved.
RW
DMA_FIFO_WATERMARK: Audio unit has a 8x64 bytes fifo for pre-fetching and
staging audio samples. This register provides a watermark value in SWORDs (64B).
001b When enable and sample buffer is available audio unit will fetch samples until this FIFO
10:8
RW is full then it waits until HDMI/DP packet assembler drains the samples to a level less or
equal the watermark setting then it will start fetching the samples again. Default value
is 1 cacheline (SW).
FIFO_WATERMARK: Audio unit has a 96x8 bytes fifo for pre-fetching and staging
0b audio samples. This register provides a watermark value in DWORDs. When enable and
7:0 sample buffer is available audio unit will fetch samples until this FIFO occupancy is
RW above the watermark then it waits until HDMI packet assembler drains the samples to a
level less or equal the watermark setting then it will start fetching the samples again

14.11.157 STREAM_B_LPE_AUD_BUF_CH_SWP—Offset 65824h

Audio Sample Swapping

Access Method
Type: Memory Mapped I/O Register STREAM_B_LPE_AUD_BUF_CH_SWP: [GTTMMADR_LSB +
(Size: 32 bits) 2BF20h] + 65824h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00FAC688h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0
SAMPLE_INDEX_FOR_SECOND_CHANNEL_OF_SUBPACKET_3

SAMPLE_INDEX_FOR_SECOND_CHANNEL_OF_SUBPACKET_2

SAMPLE_INDEX_FOR_SECOND_CHANNEL_OF_SUBPACKET_1

SAMPLE_INDEX_FOR_SECOND_CHANNEL_OF_SUBPACKET_0
SAMPLE_INDEX_FOR_FIRST_CHANNEL_OF_SUBPACKET_3

SAMPLE_INDEX_FOR_FIRST_CHANNEL_OF_SUBPACKET_2

SAMPLE_INDEX_FOR_FIRST_CHANNEL_OF_SUBPACKET_1

SAMPLE_INDEX_FOR_FIRST_CHANNEL_OF_SUBPACKET_0
RESERVED

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670 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

0b
31:24 RESERVED: Reserved.
RO

111b SAMPLE_INDEX_FOR_SECOND_CHANNEL_OF_SUBPACKET_3: This field has the

23:21 index of 32-byte buffer block that will be send out as the second channel sample of
RO subpacket 3 in a HDMI audio packet

110b SAMPLE_INDEX_FOR_FIRST_CHANNEL_OF_SUBPACKET_3: This field has the

20:18 index of 32-byte buffer block that will be send out as the first channel sample of
RO subpacket 1 in a HDMI audio packet

101b SAMPLE_INDEX_FOR_SECOND_CHANNEL_OF_SUBPACKET_2: This field has the

17:15 index of 32-byte buffer block that will be send out as the second channel sample of
RO subpacket 0 in a HDMI audio packet

100b SAMPLE_INDEX_FOR_FIRST_CHANNEL_OF_SUBPACKET_2: This field has the

14:12 index of 32-byte buffer block that will be send out as the first channel sample of
RO subpacket 0 in a HDMI audio packet

011b SAMPLE_INDEX_FOR_SECOND_CHANNEL_OF_SUBPACKET_1: This field has the

11:9 index of 32-byte buffer block that will be send out as the second channel sample of
RO subpacket 1 in a HDMI audio packet

010b SAMPLE_INDEX_FOR_FIRST_CHANNEL_OF_SUBPACKET_1: This field has the

8:6 index of 32-byte buffer block that will be send out as the first channel sample of
RO subpacket 1 in a HDMI audio packet

001b SAMPLE_INDEX_FOR_SECOND_CHANNEL_OF_SUBPACKET_0: This field has the

5:3 index of 32-byte buffer block that will be send out as the second channel sample of
RO subpacket 0 in a HDMI audio packet

0b SAMPLE_INDEX_FOR_FIRST_CHANNEL_OF_SUBPACKET_0: This field has the

2:0 index of 32-byte buffer block that will be send out as the first channel sample of
RO subpacket 0 in a HDMI audio packet

14.11.158 STREAM_B_LPE_AUD_BUF_A_ADDR—Offset 65840h

Address for Audio Buffer A

Access Method
Type: Memory Mapped I/O Register STREAM_B_LPE_AUD_BUF_A_ADDR: [GTTMMADR_LSB +
(Size: 32 bits) 2BF20h] + 65840h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BUFFER_ADDRESS

INTERRUPT_ENABLE
BUFFER_VALID
RESERVED

Bay Trail-I SoC

Datasheet 671
 Graphics, Video and Display

Bit Default &

Description
Range Access

0b BUFFER_ADDRESS: . This is physical address of audio sample buffer A, need to 64-

31:6
RW byte aligned.

0b
5:2 RESERVED: Reserved.
RW
0b INTERRUPT_ENABLE: If enable hardware will generate an interrupt when it is done
1
RW fetching this buffer

0b BUFFER_VALID: . This bit is set by S/W when the mem_addr is written and is cleared
0
RW by H/W when done reading the data from memory

14.11.159 STREAM_B_LPE_AUD_BUF_A_LENGTH—Offset 65844h

Length for Audio Buffer A

Access Method
Type: Memory Mapped I/O Register STREAM_B_LPE_AUD_BUF_A_LENGTH: [GTTMMADR_LSB +
(Size: 32 bits) 2BF20h] + 65844h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED

BUFFER_LENGTH_

Bit Default &

Description
Range Access

0b
31:20 RESERVED: Reserved.
RW

BUFFER_LENGTH_: This field shows the remaining length of data that needs to be
0b read from memory; Initially set by S/W for total of bytes that are valid and is
19:0
RW decremented by H/W as reads are issued. Software must end buffer at the boundary of
a audio sample with all of channel values of that sample are valid.

14.11.160 STREAM_B_LPE_AUD_BUF_B_ADDR—Offset 65848h

Address for Audio Buffer B

Access Method
Type: Memory Mapped I/O Register STREAM_B_LPE_AUD_BUF_B_ADDR: [GTTMMADR_LSB +
(Size: 32 bits) 2BF20h] + 65848h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

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672 Datasheet
Graphics, Video and Display

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BUFFER_VALID
BUFFER_ADDRESS

RESERVED

INTERRUPT_ENABLE
Bit Default &
Description
Range Access

0b BUFFER_ADDRESS: . This is physical address of audio sample buffer A, need to 64-

31:6
RW byte aligned.

0b
5:2 RESERVED: Reserved.
RW

0b INTERRUPT_ENABLE: If enable hardware will generate an interrupt when it is done

1
RW fetching this buffer

0b BUFFER_VALID: . This bit is set by S/W when the mem_addr is written and is cleared
0
RW by H/W when done reading the data from memory

14.11.161 STREAM_B_LPE_AUD_BUF_B_LENGTH—Offset 6584Ch

Length for Audio Buffer B

Access Method
Type: Memory Mapped I/O Register STREAM_B_LPE_AUD_BUF_B_LENGTH: [GTTMMADR_LSB +
(Size: 32 bits) 2BF20h] + 6584Ch

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BUFFER_LENGTH_
RESERVED

Bit Default &

Description
Range Access

0b
31:20 RESERVED: Reserved.
RW
BUFFER_LENGTH_: This field shows the remaining length of data that needs to be
0b read from memory; Initially set by S/W for total of bytes that are valid and is
19:0
RW decremented by H/W as reads are issued. Software must end buffer at the boundary of
a audio sample with all of channel values of that sample are valid.

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Datasheet 673
 Graphics, Video and Display

14.11.162 STREAM_B_LPE_AUD_BUF_C_ADDR—Offset 65850h

Address for Audio Buffer C

Access Method
Type: Memory Mapped I/O Register STREAM_B_LPE_AUD_BUF_C_ADDR: [GTTMMADR_LSB +
(Size: 32 bits) 2BF20h] + 65850h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BUFFER_VALID
BUFFER_ADDRESS

RESERVED

INTERRUPT_ENABLE
Bit Default &
Description
Range Access

0b BUFFER_ADDRESS: . This is physical address of audio sample buffer A, need to 64-

31:6
RW byte aligned.

0b
5:2 RESERVED: Reserved.
RW

0b INTERRUPT_ENABLE: If enable hardware will generate an interrupt when it is done

1
RW fetching this buffer

0b BUFFER_VALID: . This bit is set by S/W when the mem_addr is written and is cleared
0
RW by H/W when done reading the data from memory

14.11.163 STREAM_B_LPE_AUD_BUF_C_LENGTH—Offset 65854h

Length for Audio Buffer C

Access Method
Type: Memory Mapped I/O Register STREAM_B_LPE_AUD_BUF_C_LENGTH: [GTTMMADR_LSB +
(Size: 32 bits) 2BF20h] + 65854h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

674 Datasheet
Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESERVED

BUFFER_LENGTH_
Bit Default &
Description
Range Access

0b
31:20 RESERVED: Reserved.
RW
BUFFER_LENGTH_: This field shows the remaining length of data that needs to be
0b read from memory; Initially set by S/W for total of bytes that are valid and is
19:0
RW decremented by H/W as reads are issued. Software must end buffer at the boundary of
a audio sample with all of channel values of that sample are valid.

14.11.164 STREAM_B_LPE_AUD_BUF_D_ADDR—Offset 65858h

Address for Audio Buffer D

Access Method
Type: Memory Mapped I/O Register STREAM_B_LPE_AUD_BUF_D_ADDR: [GTTMMADR_LSB +
(Size: 32 bits) 2BF20h] + 65858h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BUFFER_ADDRESS

BUFFER_VALID
RESERVED

INTERRUPT_ENABLE

Bit Default &

Description
Range Access

0b BUFFER_ADDRESS: . This is physical address of audio sample buffer A, need to 64-

31:6
RW byte aligned.

0b
5:2 RESERVED: Reserved.
RW
0b INTERRUPT_ENABLE: If enable hardware will generate an interrupt when it is done
1
RW fetching this buffer

0b BUFFER_VALID: . This bit is set by S/W when the mem_addr is written and is cleared
0
RW by H/W when done reading the data from memory

Bay Trail-I SoC

Datasheet 675
 Graphics, Video and Display

14.11.165 STREAM_B_LPE_AUD_BUF_D_LENGTH—Offset 6585Ch

Length for Audio Buffer D

Access Method
Type: Memory Mapped I/O Register STREAM_B_LPE_AUD_BUF_D_LENGTH: [GTTMMADR_LSB +
(Size: 32 bits) 2BF20h] + 6585Ch

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED

BUFFER_LENGTH_
Bit Default &
Description
Range Access

0b
31:20 RESERVED: Reserved.
RW
BUFFER_LENGTH_: This field shows the remaining length of data that needs to be
0b read from memory; Initially set by S/W for total of bytes that are valid and is
19:0
RW decremented by H/W as reads are issued. Software must end buffer at the boundary of
a audio sample with all of channel values of that sample are valid.

14.11.166 STREAM_B_LPE_AUD_CNTL_ST—Offset 65860h

LPE Audio Control State Register

Access Method
Type: Memory Mapped I/O Register STREAM_B_LPE_AUD_CNTL_ST: [GTTMMADR_LSB + 2BF20h]
(Size: 32 bits) + 65860h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

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676 Datasheet
Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESERVED_FOR_LATER_DIP_TYPE_IF_NEEDED

DIP_TYPE_ENABLE_STATUS_READ_ONLY
RESERVED

DIP_BUFFER_INDEX_R_W

CP_READY
RESERVED_1

DIP_TRANSMISSION_FREQUENCY_R_W

DIP_RAM_ACCESS_ADDRESS_R_W
RESERVED_2

RESERVED_3

RESERVED_

RESERVED_4
Bit Default &
Description
Range Access

0b
31 RESERVED: Reserved.
RW
0b
30:29 RESERVED_1: Reserved.
RW
0b
28:25 RESERVED_FOR_LATER_DIP_TYPE_IF_NEEDED: Must be 0.
RW
DIP_TYPE_ENABLE_STATUS_READ_ONLY: These bits reflects the DIP types
enabled. It can be updated while the port is enabled. Within 2 vblank periods, the DIP is
0b guaranteed to have been transmitted. Disabling an DIP type results in setting the
24:21 contents of that DIP buffer to zero. A reserved setting reflects a disabled DIP. XXX1 =
RO Audio DIP enable status (Default = disabled) XX1X = Generic 1 (ACP) DIP enable status
(Default = disabled) X1XX = Generic 2 DIP enable status, can be used by ISRC1 or
ISRC2 (Default = disabled) 1XXX = Reserved AccessType: Read Only

DIP_BUFFER_INDEX_R_W: This field is used during read or write of different DIPs,

and during read or write of ELD data. These bits are used as an index to their respective
DIP or ELD buffers. When the index is not valid, the contents of the DIP will return all 0
0b s. 000 = (Default) Audio DIP (31 bytes of address space, 13 bytes of data) 001 =
20:18
RW Generic 1 (ACP) Data Island Packet (31 bytes of address space, 11 bytes of data) 010 =
Generic 2 (ISRC1) Data Island Packet (31 bytes of address space, 31 bytes of data) 011
= Generic 3 (ISRC2) Data Island Packet (31 bytes of address space, 31 bytes of data)
1XX = reserved

DIP_TRANSMISSION_FREQUENCY_R_W: These bits reflect the frequency of DIP

transmission for the DIP buffer type designated in bits 20:18. When writing DIP data,
0b this value is also latched when the first DW of the DIP is written.When read, this value
17:16
RW reflects the DIP transmission frequency for the DIP buffer designated in bits 20:18. 00 =
Disabled (Default) 01 = once per frame 10 = Send once 11 = Best effort (Send at least
every other vsync)

CP_READY: This R/W bit reflects the state of CP request from the audio unit. When an
audio CP request has been serviced, it must be reset to 1 by the video software to
0b indicate that the CP request has been serviced. 0 = CP request pending or not ready to
15
RW receive requests (default) 1 = CP request ready CP_ready bit is programmable through
Bit 14 for [DevCL, DevBLC]. CP_ready bit is programmable through Bit 15 for [DevCTG].
Bit 15 Reserved for [DevCL, DevBLC].

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Datasheet 677
 Graphics, Video and Display

Bit Default &

Description
Range Access

RESERVED_2: ELD valid: This R/W bit reflects the state of the ELD data written to the
ELD RAM. After writing the ELD data, the video software must set this bit to 1 to indicate
that the ELD data is valid. At audio codec initialization, or on a hotplug event, this bit is
0b set to 0 by the video software. This bit is reflected in the audio pin complex widget as
14
RW the ELD valid status bit. 0 = ELD data invalid (default, when writing ELD data, set 0 by
software) 1 = ELD data valid (Set by video software only) ELD bit is programmable
through Bit 13 for [DevCL, DevBLC]. ELD bit is programmable through Bit 14 for
[DevCTG].

0b RESERVED_3: ELD buffer size (read only)10000 = This field reflects the size of the ELD
13:9 buffer in DWORDs 13:9 reflects ELD buffer size for [DevCTG]. 12:9 reflects ELD buffer
RW size for [DevCL, DevBLC].

RESERVED_: ELD access address (R/W): Selects the DWORD address for access to the
0b ELD buffer (48 bytes). The value wraps back to zero when incremented past the max
8:5
RW addressing value 0xF. This field change takes effect immediately after being written. The
read value indicates the current access address.
0b RESERVED_4: ELD ACK: Acknowledgement from the audio driver that ELD read has
4
RW been completed

DIP_RAM_ACCESS_ADDRESS_R_W: Selects the DWORD address for access to the

0b DIP buffers. The value wraps back to zero when it incremented past the max addressing
3:0
RW value of 0xF. This field change takes effect immediately after being written. The read
value indicates the current access address.

14.11.167 STREAM_B_LPE_AUD_HDMI_STATUS—Offset 65864h

LPE Audio Status

Access Method
Type: Memory Mapped I/O Register STREAM_B_LPE_AUD_HDMI_STATUS: [GTTMMADR_LSB +
(Size: 32 bits) 2BF20h] + 65864h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

678 Datasheet
Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SAMPLE_BUFFER_UNDERRUN_STATUS
AUDIO_BANDWIDTH_UNDERRUN_DEBUG_STATUS
LPE_AUDIO_BUFFER_DONE_STATUS

AUDIO_BANDWIDTH_UNDERRUN_INTERRUPT_ENABLE

AZALIA_COMPATIBLE_MODE
RESERVED

SAMPLE_BUFFER_UNDERRUN_INTERRUPT_ENABLE
NUMBER_OF_SAMPLES_BEHIND_DEBUG

AUDIO_SAMPLE_RUN_RATE_DEBUG
FUNCTION_RESET_R_W_ONLY
RESERVED_1
Bit Default &
Description
Range Access

SAMPLE_BUFFER_UNDERRUN_STATUS: This bit indicates an underrun in the

sample buffer to HDMI/DP controller when it needs to send. This bit is set at the last line
0b of active video when there are no more sample in any valid buffers and HDMI/DP audio
31
RW/1C unit has not satisfied number of audio samples intended in that video frame. Clearing
this status bit is accomplished by writing a 1 to this bit through MMIO. AccessType: One
to Clear
AUDIO_BANDWIDTH_UNDERRUN_DEBUG_STATUS: This bit indicates an underrun
of audio samples at HDMI audio packet assembly even there is still available sample
buffers. Audio bandwidth underrun should not happen in normal functionality but it may
0b happen when audio setting is unappropriate and/or memory bus was blocked by other
30
RW/1C clients, etc... This bit is set at the last line of active video when there is valid samples in
a valid buffer and HDMI audio unit has not satisfied number of audio samples intended
in that video frame Clearing this status bit is accomplished by writing a 1 to this bit
through MMIO. AccessType: One to Clear

0b LPE_AUDIO_BUFFER_DONE_STATUS: This bit is set when a LPE audio buffer is

29 completed transferred all of its data to LPE audio unit. This bit is clear when write 1 to it
RW/1C AccessType: One to Clear
0b
28:24 RESERVED: Reserved.
RW

0b NUMBER_OF_SAMPLES_BEHIND_DEBUG: This field is read only to get the number

23:16 of audio samples that controller needs to load and send at the time of reading.
RO AccessType: Read Only
SAMPLE_BUFFER_UNDERRUN_INTERRUPT_ENABLE: This bit is to enable the first
0b line buffer underrun interrupt when sample buffer underrun status is detected 0 = LPE
15
RW sample Buffer Underrun Interrupt Disabled 1 = LPE sample Buffer Underrun Interrupt
Enabled
AUDIO_BANDWIDTH_UNDERRUN_INTERRUPT_ENABLE: This bit is to enable the
0b first line bandwidth underrun interrupt when bandwidth underrun status is detected 0 =
14
RW LPE Bandwidth Underrun Interrupt Disabled 1 = LPE Bandwidth Underrun Interrupt
Enabled

0b
13:3 RESERVED_1: Reserved.
RW

Bay Trail-I SoC

Datasheet 679
 Graphics, Video and Display

Bit Default &

Description
Range Access

0b AZALIA_COMPATIBLE_MODE: This bit is to enable the vucp, PR, ECC to be generated

2 in the Azalia way 0 = Disable Azalia compatible mode on vucp, PR, ECC 1 = Enable
RW Azalia compatible mode on vucp, PR, ECC
0b AUDIO_SAMPLE_RUN_RATE_DEBUG: When set it allows to fetch sample 128 times
1
RW than the real sample rate to allow a faster drain of sample bufferes.

FUNCTION_RESET_R_W_ONLY: Write 1 to this bit will reset hardware within audio

0b unit without needs of reset the full display controller. The FIFO and pointers will be reset
0
RW and audio registers will be reset to default values. Write 0 will put the unit back to idle
and ready to be programmed again.

14.11.168 STREAM_B_LPE_AUD_HDMIW_INFOFR—Offset 65868h

Audio HDMI Data Island Packet Data

Access Method
Type: Memory Mapped I/O Register STREAM_B_LPE_AUD_HDMIW_INFOFR: [GTTMMADR_LSB +
(Size: 32 bits) 2BF20h] + 65868h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DATA_ISLAND_PACKET_DATA

Bit Default &

Description
Range Access

DATA_ISLAND_PACKET_DATA: When read, this returns the current value at the

location specified in the Video DIP buffer index select and Video DIP RAM access address
0b fields. The index used to address the RAM is incremented after each read or write of this
31:0
RW register. DIP data can be read at any time. Data should be loaded into the RAM before
enabling the transmission through the DIP type enable bit. Accesses to this register are
on a per-DWORD basis

14.11.169 PIPEA_DSL—Offset 70000h

Pipe A Display Scan Line

Access Method

Bay Trail-I SoC

680 Datasheet
Graphics, Video and Display

Type: Memory Mapped I/O Register

PIPEA_DSL: [GTTMMADR_LSB + 2BF20h] + 70000h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESERVED
CURRENT_FIELD

LINE_COUNTER_FOR_DISPLAY_12
Bit Default &
Description
Range Access

CURRENT_FIELD: [DevBLC, DevCTG, DevCDV] Provides read back of the current field
0b being displayed on display pipe A. Non-TV mode: 0 = first field (odd field) 1 = second
31
RO field (even field) TV mode: 1 = first field (odd field) 0 = second field (even field)
[DevBW] and [DevCL] Reserved: Read only.

0b
30:13 RESERVED: Read only.
RO

0b LINE_COUNTER_FOR_DISPLAY_12: 0]: Provides read back of the display pipe A

12:0 vertical line counter. This is an indication of the current display scan line to be used by
RO software to synchronize with the display.

14.11.170 PIPEA_SLC—Offset 70004h

Pipe A Display Scan Line Count Range Compare

Access Method
Type: Memory Mapped I/O Register
PIPEA_SLC: [GTTMMADR_LSB + 2BF20h] + 70004h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

Datasheet 681
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

START_SCAN_LINE_NUMBER

END_SCAN_LINE_NUMBER
INCLUSIVE_EXCLUSIVE

RESERVED

RESERVED_1
Bit Default &
Description
Range Access

0b INCLUSIVE_EXCLUSIVE: 1 = Inclusive: within the range. 0 = Exclusive: outside of

31
RW the range.

0b
30:29 RESERVED: Read only.
RW

START_SCAN_LINE_NUMBER: [DevBLC, DevCTG, DevCDV] This field specifies the

starting scan line number of the Scan Line Window. Format = U16 in scan lines, where
0b scan line 0 is the first line of the display frame. Range = [0,Display Buffer height in
28:16
RW lines-1]. [DevBW, DevCL] End Scan Line Number: This field specifies the ending scan
line number of the Scan Line Window. Format = U16 in scan lines, where scan line 0 is
the first line of the display frame. Range = [0, Display Buffer height in lines-1].

0b
15:13 RESERVED_1: Read only.
RW

END_SCAN_LINE_NUMBER: [DevBLC, DevCTG, DevCDV] This field specifies the

ending scan line number of the Scan Line Window. Format = U16 in scan lines, where
0b scan line 0 is the first line of the display frame. Range = [0, Display Buffer height in
12:0
RW lines-1]. [DevBW] and [DevCL] Start Scan Line Number: This field specifies the starting
scan line number of the Scan Line Window. Format = U16 in scan lines, where scan line
0 is the first line of the display frame. Range = [0,Display Buffer height in lines-1].

14.11.171 PIPEACONF—Offset 70008h

Pipe A Configuration Register

Access Method
Type: Memory Mapped I/O Register
PIPEACONF: [GTTMMADR_LSB + 2BF20h] + 70008h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

682 Datasheet
Graphics, Video and Display

Bay Trail-I SoC

Datasheet 683
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bay Trail-I SoC

684 Datasheet
 Datasheet
Bay Trail-I SoC
PIPE_A_ENABLE
PIPE_STATE
DSI_PLL_LOCK_LOCK

FRAME_START_DELAY
Graphics, Video and Display

DISPLAY_PORT_AUDIO_ONLY_MODE
FORCE_BORDER
PIPE_A_GAMMA_UNIT_MODE

INTERLACED_MODE

MIPI_DISPLAY_SELF_REFRESH_MODE_FOR_MIPI_A_REFRESH
DISPLAY_OVERLAY_PLANES_OFF
CURSOR_PLANES_OFF

REFRESH_RATE_CXSR_MODE_ASSOCIATION

TION_MATRIX_ENABLE_ON_PIPE_A_1_COLOR_CORRECTION_COEFFICIENTS_ARE_ENABLED_TO_PERFORM_COLOR_CORRECTION_0_COLOR_CORRECTION_COEFFICIENTS_ARE_DISABLED_
DISPLAYPORT_POWER_MODE_SWITCH_DEVVLVP
COLOR_RANGE_SELECT
S3D_SPRITE_ORDER

S3D_SPRITE_INTERLEAVING_FORMAT

RESERVED

BITS_PER_COLOR

DITHERING_ENABLE

DITHERING_TYPE

DDA_RESET_TEST_MODE
RESERVED_1

685
 Graphics, Video and Display

Bit Default &

Description
Range Access

PIPE_A_ENABLE: Setting this bit to the value of one, turns on pipe A. This must be
done before any planes are enabled on this pipe. Changing it to a zero should only be
done when all planes that are assigned to this pipe have been disabled. Turning the pipe
0b enable bit off disables the timing generator in this pipe. Plane disable occurs after the
31 next VBLANK event after the plane is disabled. Synchronization pulses to the display are
RW not maintained if the timing generator is disabled. Power consumption will be at it s
lowest state when disabled. A separate bit controls the DPLL enable for this pipe. Pipe
timing registers should contain valid values before this bit is enabled. 0 = Disable 1 =
Enable

0b PIPE_STATE: This bit indicates the actual state of the pipe. Since there can be some
30 delay between disabling the pipe and the pipe actually shutting off, this bit indicates the
RO true current state of the pipe. 0 = Disabled 1 = Enabled AccessType: Read Only
0b DSI_PLL_LOCK_LOCK: This bit indicates the clocks from DSI PLL are locked. 0 =
29
RO Unlocked 1 = Locked AccessType: Read only

FRAME_START_DELAY: (TEST MODE) Used to delay the frame start signal that is sent
to the display planes. Normal operation uses the default 00 value and test modes can
use the delayed frame start to shorten the test time. Care must be taken to insure that
0b there are enough lines during VBLANK to support this setting. 00 = Frame Start occurs
28:27
RW on the first HBLANK after the start of VBLANK 01 = Frame Start occurs on the second
HBLANK after the start of VBLANK 10 = Frame Start occurs on the third HBLANK after
the start of VBLANK 11 = Frame Start occurs on the forth HBLANK after the start of
VBLANK

0b DISPLAY_PORT_AUDIO_ONLY_MODE: [DevVLVP] Setting this bit to 1 indicates the

26 DisplayPort will output audio only. 0 = DisplayPort will output Video or Video and Audio
RW 1 = DisplayPort will output Audio only
0b FORCE_BORDER: : (TEST MODE)0 = Normal Operation 1 = Color information is
25
RW ignored and border color is substituted during active region

PIPE_A_GAMMA_UNIT_MODE: This bit selects which mode the pipe gamma

correction logic works in. In the palette mode, it behaves as a 3X256x8 RAM lookup.
0b VGA and indexed mode operation should use the palette in 8-bit mode. In the 10-bit
24
RW gamma mode, it will act as a piecewise linear interpolation. Other gamma units such as
in the overlay or sprite are unaffected by this bit. 0 = 8-bit Palette Mode 1 = 10-bit
Gamma Mode
INTERLACED_MODE: These bits are used for software control of interlaced behavior.
They are updated immediately if the pipe is off, or in the vertical blank after
programming if pipe is enabled. 0xx = Progressive 100 = Interlaced embedded panel
using programmable vertical sync shift. (2x) 101 = Interlaced using vertical sync shift.
0b Backup option to 110 setting. (2x) 110 = Interlaced with VSYNC/HSYNC Field Indication
23:21
RW using legacy vertical sync shift. Used for SDVO. 111 = Interlaced with Field 0 Only using
legacy vertical sync shift. Not used Note: VGA display modes, sDVO line stall, and Panel
fitting do not work while in interlaced modes Setting the Interlaced embedded panel
mode causes hardware to automatically modify the output to match the specifications of
panels that support interlaced mode.

MIPI_DISPLAY_SELF_REFRESH_MODE_FOR_MIPI_A_REFRESH: 0 = Normal
0b Operation, display controller generate timing and refresh display panel at refresh rate 1
20
RW = Display self-refresh mode. Display controller update frame buffer in display module on
demand only
DISPLAY_OVERLAY_PLANES_OFF: This bit when set will cause all enabled Display
and overlay planes that are assigned to this pipe to be disabled by overriding the
0b current setting of the plane enable bit, at the next VBLANK. Timing signals continue as
19
RW they were but the screen becomes blank. Setting the bit back to a zero will then allow
the display and overlay planes to resume on the following VBLANK. 0 = Normal
Operation 1 = Planes assigned to this pipe are disabled.
CURSOR_PLANES_OFF: This bit when set will cause all enabled cursor planes that are
assigned to this pipe to be disabled by overriding the current setting of the plane enable
0b bit, at the next VBLANK. Timing signals continue as they were but the cursor(s) no
18
RW longer appear on the screen. Setting the bit back to a zero will then allow the cursor
planes to resume on the following VBLANK. 0 = Normal Operation 1 = Planes assigned
to this pipe are disabled.

Bay Trail-I SoC

686 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

REFRESH_RATE_CXSR_MODE_ASSOCIATION: These bits select how refresh rates

are tied to big FIFO mode on pipe A. When they are set to anything other than 00, bits
23:21 of this register must be programmed to 0xx. Switching between 01 and 10
settings directly is not allowed. Software must program this field to 00 before switching.
Software is responsible for enabling this mode only for integrated dispay panels that
0b support corresponding mode. 00 Default no dynamic refresh rate change enabled.
17:16
RW Software control only. 01 Progressive-to-progressive refresh rate change enabled and
tied to big FIFO mode. Pixel clock values set in FPA0/FPA1 settings in the DPLLA control
register and FPA0/FPA1 divider registers. FPA0 is tied to non-big-FIFO mode 10
Progressive-to-interlaced refresh rate change enabled and tied to big FIFO mode. Pixel
clock value does not change in this case. Scaling must be disabled in this mode. Uses
programmable VS shift 11 Reserved
COLOR_CORRECTION_MATRIX_ENABLE_ON_PIPE_A_1_COLOR_CORRECTION
_COEFFICIENTS_ARE_ENABLED_TO_PERFORM_COLOR_CORRECTION_0_COLO
0b R_CORRECTION_COEFFICIENTS_ARE_DISABLED_:
15
RW
• 1 = Color Correction Coefficients are enabled to perform color correction
• 0 = Color Correction Coefficients are disabled
DISPLAYPORT_POWER_MODE_SWITCH_DEVVLVP: This bit selects the software
controlled progressive to progressive power saving mode (software controlled DRRS).
0b Hardware Controlled Refresh Rate Select must be disabled when enabling this. Link and
14
RW data M/N 1 values are used for normal settings, M/N 2 values are used for low power
settings. 0 Normal progressive refresh rate (default) 1 Low Power progressive refresh
rate

0b COLOR_RANGE_SELECT: [DevVLVP]: This bit is used to select the color range of RBG
13 outputs. 0 = Apply full 0-255 color range to the output (Default) 1 = Apply 16-235 color
RW range to the output

0b S3D_SPRITE_ORDER: This bit controls the blending order of the sprite planes for S3D
12 support: 0 = Sprite A first. The first line or pixel comes from Sprite A (default) 1 =
RW Sprite B first. The first line or pixel comes from Sprite B

0b S3D_SPRITE_INTERLEAVING_FORMAT: These bits control the Sprite A/B

11:10 interleaving format in S3D mode 00 = No interleaving 01 = Line interleaving 10 = Pixel
RW interleaving 11 = Reserved
RESERVED: [DevCDV, DevVLVP] MBZ Scrambling enable [DevCTG]: This bit enables
0b scrambling for DisplayPort. Software must set this bit appropriately when enabling a
9:8 DisplayPort output. 00 = Scrambling disabled (Default) 01 = Scrambling enabled, no SR
RW after initialization at loop 2 of training 10 - RESERVED 11 = Scrambling and SR enabled.
Scrambling is reset every 512 BS symbols.
BITS_PER_COLOR: [DevCTG, DevCDV, DevVLVP]: This field selects the number of bits
per color sent to a receiver device connected to this port. Color format takes place on
the Vblank after being written. Color format change can be done independent of a pixel
0b clock change in DisplayPort. Selecting a pixel color depth higher or lower than the pixel
7:5
RW color depth of the frame buffer results in dithering the output stream. For further details
on Display Port fixed frequency programming to accommodate these formats refer to DP
Frequency Programming in DPLL section of Bspec. 000 = 8 bits per color (Default) 001
= 10 bits per color 010 = 6 bits per color 011 = RESERVED 1xx = RESERVED

0b DITHERING_ENABLE: [DevCTG, DevCDV]: This bit enables dithering for DisplayPort

4 6bpc or 8bpc modes 0 Dithering disabled (Default) 1 Dithering enabled Programming
RW note: Dithering should only be enabled for 8 bpc or 6 bpc.

0b DITHERING_TYPE: [DevCTG, DevCDV]: This bit selects dithering type for DisplayPort
3:2 6bpc or 8bpc modes 00 - Spatial only (default) 01- Spatio-Temporal 1 10- Spatio-
RW Temporal 2 (testmode) 11- Temporal only (testmode)
0b DDA_RESET_TEST_MODE: [DevCTG, DevCDV]: 0 Do not reset DDA 1 Reset DDA
1
RW every 8th display frame

0b
0 RESERVED_1: Write as zero
RW

Bay Trail-I SoC

Datasheet 687
 Graphics, Video and Display

14.11.172 PIPEAGCMAXRED—Offset 70010h

Pipe A Gamma Correction Max Red

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) PIPEAGCMAXRED: [GTTMMADR_LSB + 2BF20h] + 70010h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00010000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MAX_RED_GAMMA_CORRECTION_POINT
RESERVED

Bit Default &

Description
Range Access

0b
31:17 RESERVED: Reserved.
RW
100000000 MAX_RED_GAMMA_CORRECTION_POINT: 129th reference point for red channel of
16:0 00000000b the pipe piecewise linear gamma correction. The value should always be programmed to
RW be less than or equal to 1024.0. Format: 11.6 Default: 0x10000

14.11.173 PIPEAGCMAXGREEN—Offset 70014h

Pipe A Gamma Correction Max Green

Access Method
Type: Memory Mapped I/O Register PIPEAGCMAXGREEN: [GTTMMADR_LSB + 2BF20h] + 70014h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00010000h

Bay Trail-I SoC

688 Datasheet
Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESERVED

MAX_GREEN_GAMMA_CORRECTION_POINT
Bit Default &
Description
Range Access

0b
31:17 RESERVED: Reserved.
RW

100000000 MAX_GREEN_GAMMA_CORRECTION_POINT: 129th reference point for green

16:0 00000000b channel of the pipe piecewise linear gamma correction. The value should always be
RW programmed to be less than or equal to 1024.0. Format: 11.6 Default: 0x10000

14.11.174 PIPEAGCMAXBLUE—Offset 70018h

Pipe A Gamma Correction Max Blue

Access Method
Type: Memory Mapped I/O Register
PIPEAGCMAXBLUE: [GTTMMADR_LSB + 2BF20h] + 70018h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00010000h

Bay Trail-I SoC

Datasheet 689
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESERVED

MAX_BLUE_GAMMA_CORRECTION_POINT
Bit Default &
Description
Range Access

0b
31:17 RESERVED: Reserved.
RW

100000000 MAX_BLUE_GAMMA_CORRECTION_POINT: 129th reference point for blue channel

16:0 00000000b of the pipe piecewise linear gamma correction. The value should always be programmed
RW to be less than or equal to 1024.0. Format: 11.6 Default: 0x10000

14.11.175 PIPEASTAT—Offset 70024h

Pipe A Display Status

Access Method
Type: Memory Mapped I/O Register
PIPEASTAT: [GTTMMADR_LSB + 2BF20h] + 70024h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

690 Datasheet
Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ODD_FIELD_INTERRUPT_STATUS

START_OF_VERTICAL_BLANK_INTERRUPT_STATUS
GMBUS_INTERRUPT_STATUS
START_OF_VERTICAL_BLANK_INTERRUPT_ENABLE

PLANE_A_FLIP_DONE_INTERRUPT_STATUS
FIFO_A_UNDER_RUN_STATUS
SPRITE_B_FLIP_DONE_INTERRUPT_ENABLE

SPRITE_A_FLIP_DONE_INTERRUPT_ENABLE

SPRITE_B_FLIP_DONE_INTERRUPT_STATUS
CRC_ERROR_ENABLE
CRC_DONE_ENABLE
GMBUS_EVENT_ENABLE
PLANE_A_FLIP_DONE_INTERRUPT_ENABLE

DISPLAY_LINE_COMPARE_ENABLE

ODD_FIELD_INTERRUPT_EVENT_ENABLE

SPRITE_A_FLIP_DONE_INTERRUPT_STATUS

VERTICAL_SYNC_INTERRUPT_STATUS
DISPLAY_LINE_COMPARE_INTERRUPT_STATUS

PIPE_A_PANEL_SELF_REFRESH_STATUS

EVEN_FIELD_INTERRUPT_STATUS
DPST_EVENT_ENABLE

PIPE_A_HORIZONTAL_BLANK_INTERRUPT_ENABLE

CRC_ERROR_INTERRUPT_STATUS
CRC_DONE_INTERRUPT_STATUS

FRAMESTART_INTERRUPT_STATUS
DPST_EVENT_STATUS

PERFORMANCE_MONITOR_EVENT_INTERRUPT

PIPE_A_HORIZONTAL_BLANK_STATUS
EVEN_FIELD_INTERRUPT_EVENT_ENABLE
PERFORMANCE_COUNTER_EVENT_ENABLE
VERTICAL_SYNC_INTERRUPT_ENABLE

FRAMESTART_INTERRUPT_ENABLE

Bit Default &

Description
Range Access

FIFO_A_UNDER_RUN_STATUS: Set when a pipe A FIFO under-run occurs, cleared by

a write of a 1. An underrun has occurred on an attempt to pop an empty FIFO. This does
0b not feed into the first line interrupt status register. This will occur naturally during mode
31
RW/1C changes, to be useful, it should be cleared after a mode change has occurred. This bit is
only valid after Pipe A has been completely configured. 1 = FIFO A Underflow occurred 0
= FIFO A Underflow did not occur AccessType: One to Clear

0b SPRITE_B_FLIP_DONE_INTERRUPT_ENABLE: This will enable the consideration of

30 the Sprite B flip done interrupt status bit in the first line interrupt logic 0 = Sprite B Flip
RW Done Interrupt Disabled 1 = Sprite B Flip Done Interrupt Enabled

0b CRC_ERROR_ENABLE: This will enable the consideration of the CRC error status bit in
29 the first line interrupt/status logic. 0 = CRC Error Detect Disabled 1 = CRC Error Detect
RW Enabled

0b CRC_DONE_ENABLE: This will enable the consideration of the CRC error status bit in
28 the first line interrupt/status logic. 0 = CRC Done Detect Disabled 1 = CRC Done Detect
RW Enabled

0b GMBUS_EVENT_ENABLE: This will enable the use of the GMBUS interrupt status bit in
27 the first line interrupt/status logic. 0 = No GMBUS event enabled 1 = GMBUS event
RW enabled

0b PLANE_A_FLIP_DONE_INTERRUPT_ENABLE: This will enable the consideration of

26 the Plane A flip done interrupt status bit in the first line interrupt logic 0 = Plane A flip
RW done Interrupt/Status Disabled 1 = Plane A flip done Interrupt/Status Enabled

0b VERTICAL_SYNC_INTERRUPT_ENABLE: This will enable the consideration of the

25 vertical sync interrupt status bit in the first line interrupt logic. 0 = Vertical Sync
RW Interrupt/Status Disabled 1 = Vertical Sync Interrupt/Status Enabled

0b DISPLAY_LINE_COMPARE_ENABLE: This will enable the consideration of the line

24 compare interrupt status bit in the first line interrupt/status logic. 0 = Display Line
RW Compare Interrupt/Status Disabled 1 = Display Line Compare Interrupt/Status Enabled
0b DPST_EVENT_ENABLE: [DevCL, DevCTG, DevCDV]: This interrupt is generated by the
23
RW DPST logic. 0 = No DPST event enabled 1 = DPST event enabled

0b SPRITE_A_FLIP_DONE_INTERRUPT_ENABLE: This will enable the consideration of

22 the Sprite A flip done interrupt status bit in the first line interrupt logic 0 = Sprite A Flip
RW Done Interrupt Disabled 1 = Sprite A Flip Done Interrupt Enabled

Bay Trail-I SoC

Datasheet 691
 Graphics, Video and Display

Bit Default &

Description
Range Access

0b ODD_FIELD_INTERRUPT_EVENT_ENABLE: This bit should only be used when this

21 pipe is in an interlaced display timing. 0 = Odd Field Event disable 1 = Odd Field Event
RW enable

0b EVEN_FIELD_INTERRUPT_EVENT_ENABLE: This bit should only be used when this

20 pipe is in an interlaced display timing. 0 = Even field Event disable 1 = Even field Event
RW enable
0b
19 PERFORMANCE_COUNTER_EVENT_ENABLE: perfomance counter event enable
RW
START_OF_VERTICAL_BLANK_INTERRUPT_ENABLE: This will enable the
0b consideration of the start of vertical blank interrupt status bit in the first line interrupt/
18
RW status logic. 0 = Start of Vertical Blank Interrupt/Status Disabled 1 = Start of Vertical
Blank Interrupt/Status Enabled

0b FRAMESTART_INTERRUPT_ENABLE: This will enable the consideration of the vertical

17 blank interrupt status bit in the first line interrupt/status logic. 0 = Vertical Blank
RW Interrupt/Status Disabled 1 = Vertical Blank Interrupt/Status Enabled
PIPE_A_HORIZONTAL_BLANK_INTERRUPT_ENABLE: : This will enable the
0b consideration of the start of horizontal blank interrupt status bit in the first line
16
RW interrupt/status logic0 = Start of Horizontal Blank Interrupt/Status Disabled 1 = Start of
Horizontal Blank Interrupt/Status Enabled

0b SPRITE_B_FLIP_DONE_INTERRUPT_STATUS: MMIO Flip Event is completed on

15
RW/1C Sprite B 0 = Sprite B Flip Not Done 1 = Sprite B Flip Done AccessType: One to Clear

0b SPRITE_A_FLIP_DONE_INTERRUPT_STATUS: MMIO Flip Event is completed on

14
RW/1C Sprite A 0 = Sprite A Flip Not Done 1 = Sprite A Flip Done AccessType: One to Clear

CRC_ERROR_INTERRUPT_STATUS: This sticky status bit is set when a Pipe A CRC

0b error is detected. It is cleared by a write of a one. For this bit to be meaningful, the pipe
13
RW/1C and pixel clock should be enabled and running. 0 = No CRC error has occurred 1 = CRC
Error Detected AccessType: One to Clear
CRC_DONE_INTERRUPT_STATUS: This sticky status bit is set when Pipe A CRC
0b calculation and compare are complete. It is cleared by a write of a one. For this bit to be
12
RW/1C meaningful, the pipe and pixel clock should be enabled and running. 0 = CRC Not Done
1 = CRC Done AccessType: One to Clear
GMBUS_INTERRUPT_STATUS: This status bit will be set on a GMBUS event. To use
0b this bit in a polling manner, clear the bit by writing a one to it followed by the polling
11
RW/1C loop waiting for it to become set. 0 = GMBUS event has not occurred 1 = GMBUS event
has occurred AccessType: One to Clear

0b PLANE_A_FLIP_DONE_INTERRUPT_STATUS: Async/Sync Flip Event is completed

10 on Display Plane A 0 = Plane A Flip Not Done 1 = Plane A Flip Done AccessType: One to
RW/1C Clear
VERTICAL_SYNC_INTERRUPT_STATUS: This bit provides a sticky status that is set
0b when a pipe A vertical sync occurs, cleared by a write of a 1. For interlaced timing
9 modes, this occurs once per field, when in progressive, it occurs once per frame. For this
RW/1C bit to be meaningful, the pipe and pixel clock should be enabled and running. 0 =
Vertical Sync has not occurred 1 = Vertical Sync has occurred AccessType: One to Clear

0b DISPLAY_LINE_COMPARE_INTERRUPT_STATUS: Set when a pipe A compare

8 match occurs, cleared by a write of a 1. 0 = Display Line Compare has not been satisfied
RW/1C 1 = Display Line Compare has been satisfied AccessType: One to Clear

DPST_EVENT_STATUS: [DevCL, DevCTG, DevCDV]: This bit is cleared when a write to

this register occurs with this bit as a one. Writes with this bit as a zero has no effect on
0b the value of the bit. Multiple DPST events (Histogram or Phase In) can cause this bit to
7
RW/1C be asserted, determination of which event occurred is done in the DPST registers. 0 =
DPST Interrupt has not occurred on pipe A 1 = DPST Interrupt has occurred on pipe A
AccessType: One to Clear

Bay Trail-I SoC

692 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

PIPE_A_PANEL_SELF_REFRESH_STATUS: This bit indicates interrupt is generated

by the PSR controller and intends to send interrupt to SW driver when the PSR interrupt
0b enable bit (70028h bit 22) is set. This is cleared when a write to this register occurs with
6
RW/1C this bit as a one. Write with this bit as a zero has no effect on the value of the bit. 0 =
PSR Interrupt has not occurred on pipe A 1 = PSR interrupt has occurred on pipe A
AccessType: One to Clear
ODD_FIELD_INTERRUPT_STATUS: This status bit will be set on a Odd field VBLANK
event. This bit should only be used when this pipe is in an interlaced display timing. For
synchronization with register updates, the actual event will occur one line after the start
0b of VBLANK. To use this bit in a polling manner, clear the bit by writing a one to it
5
RW/1C followed by the polling loop waiting for it to become set. Note: This bit will not be set
when pipe is in Interlaced with Field 0 Only using legacy vertical sync shift mode. 0 =
Odd Field Vertical Blank has not occurred 1 = Odd Field Vertical Blank has occurred
AccessType: One to Clear

EVEN_FIELD_INTERRUPT_STATUS: This status bit will be set on a even field

VBLANK event. This bit should only be used when this pipe is in an interlaced display
timing. For synchronization with register updates, the actual event will occur one line
0b after the start of VBLANK. To use this bit in a polling manner, clear the bit by writing a
4
RW/1C one to it followed by the polling loop waiting for it to become set. Note: This bit will not
be set when pipe is in Interlaced with Field 0 Only using legacy vertical sync shift mode.
0 = Even Field Vertical Blank has not occurred 1 = Even Field Vertical Blank has
occurred AccessType: One to Clear
0b
3 PERFORMANCE_MONITOR_EVENT_INTERRUPT: AccessType: One to Clear
RW/1C
START_OF_VERTICAL_BLANK_INTERRUPT_STATUS: This status bit will be set at
the beginning of a VBLANK event. At this point, the double buffered display registers
0b flip, taking their new values. To use this bit in a polling manner, clear the bit by writing a
2
RW/1C one to it followed by the polling loop waiting for it to become set. In MIPI DSR mode,
GPIO TE trigger sets the Vblank Interrupt status 0 = Start of Vertical Blank has not
occurred 1 = Start of Vertical Blank has occurred AccessType: One to Clear
FRAMESTART_INTERRUPT_STATUS: This status bit will be set on a VBLANK event,
when the frame start occurs. The display registers are updated at the start of vertical
0b blank, but the new register data is not utilized by the display pipeline until the point in
1 the vertical blank period when the frame start occurs, which is the event that triggers
RW/1C this bit. To use this bit in a polling manner, clear the bit by writing a one to it followed by
the polling loop waiting for it to become set. 0 = Vertical Blank has not occurred 1 =
Vertical Blank has occurred AccessType: One to Clear

0b PIPE_A_HORIZONTAL_BLANK_STATUS: 0 = Pipe A Horizontal Blank has not

0
RW/1C occurred 1 = Pipe A Horizontal Blank has occurred AccessType: One to Clear

14.11.176 DPFLIPSTAT—Offset 70028h

Display FLIP Status Register

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) DPFLIPSTAT: [GTTMMADR_LSB + 2BF20h] + 70028h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

Datasheet 693
694
0
31

RESERVED
0
0

DISPLAY_PIPE_B_LINE_COMPARE_INTERRUPT_STATUS_ENABLE
0
28

PIPE_B_HORIZONTAL_BLANK_INTERRUPT_ENABLE
0

PIPE_B_VERTICAL_BLANK_INTERRUPT_ENABLE
0

SPRITE_D_FLIP_DONE_INTERRUPT_ENABLE
0

SPRITE_C_FLIP_DONE_INTERRUPT_ENABLE
0
24

PLANE_B_FLIP_DONE_INTERRUPT_ENABLE
0

RESERVED_1
0

PANEL_SELF_REFRESH_PSR_INTERRUPT_ENABLE_ON_PIPE_A_0_PSR_INTERRUPT_DISABLED_ON_PIPE_A_1_PSR_INTERRUPT_ENABLED_ON_PIPE_A
0

DISPLAY_PIPE_A_LINE_COMPARE_INTERRUPT_STATUS_ENABLE
0
20

PIPE_A_HORIZONTAL_BLANK_INTERRUPT_ENABLE
0

PIPE_A_VERTICAL_BLANK_INTERRUPT_ENABLE
0

SPRITE_B_FLIP_DONE_INTERRUPT_ENABLE
0

SPRITE_A_FLIP_DONE_INTERRUPT_ENABLE
0
16

PLANE_A_FLIP_DONE_INTERRUPT_ENABLE
0
0
0
0
12

0
0
0
8

RESERVED_2
0
0
0
4

0
0
0
0
0

0
Graphics, Video and Display

Datasheet
Bay Trail-I SoC
Graphics, Video and Display

Bit Default &

Description
Range Access

0b
31:30 RESERVED: MBZ
RW

0b DISPLAY_PIPE_B_LINE_COMPARE_INTERRUPT_STATUS_ENABLE: 0 = Display
29 Pipe B Line Compare Interrupt Disabled 1 = Display Pipe B Line Compare Interrupt
RW Enabled
0b PIPE_B_HORIZONTAL_BLANK_INTERRUPT_ENABLE: 0 = Pipe B Horizontal Blank
28
RW Interrupt Disabled 1 = Pipe B Horizontal Blank Interrupt Enabled

0b PIPE_B_VERTICAL_BLANK_INTERRUPT_ENABLE: 0 = Pipe B Vertical Blank

27
RW Interrupt Disabled 1 = Pipe B Vertical Blank Interrupt Enabled

0b SPRITE_D_FLIP_DONE_INTERRUPT_ENABLE: 0 = Sprite D Flip Done Interrupt

26
RW Disabled 1 = Sprite D Flip Done Interrupt Enabled

0b SPRITE_C_FLIP_DONE_INTERRUPT_ENABLE: 0 = Sprite C Flip Done Interrupt

25
RW Disabled 1 = Sprite C Flip Done Interrupt Enabled

0b PLANE_B_FLIP_DONE_INTERRUPT_ENABLE: 0 = Plane B Flip Done Interrupt

24
RW Disabled 1 = Plane B Flip Done Interrupt Enabled

0b
23 RESERVED_1: Reserved.
RW
PANEL_SELF_REFRESH_PSR_INTERRUPT_ENABLE_ON_PIPE_A_0_PSR_INTER
0b RUPT_DISABLED_ON_PIPE_A_1_PSR_INTERRUPT_ENABLED_ON_PIPE_A:
22
RW • 0 = PSR interrupt Disabled on Pipe A
• 1 = PSR Interrupt Enabled on Pipe A

0b DISPLAY_PIPE_A_LINE_COMPARE_INTERRUPT_STATUS_ENABLE: 0 = Display
21 Pipe A Line Compare Interrupt Disabled 1 = Display Pipe A Line Compare Interrupt
RW Enabled
0b PIPE_A_HORIZONTAL_BLANK_INTERRUPT_ENABLE: 0 = Pipe A Horizontal Blank
20
RW Interrupt Disabled 1 = Pipe A Horizontal Blank Interrupt Enabled

0b PIPE_A_VERTICAL_BLANK_INTERRUPT_ENABLE: 0 = Pipe A Vertical Blank

19
RW Interrupt Disabled 1 = Pipe A Vertical Blank Interrupt Enabled

0b SPRITE_B_FLIP_DONE_INTERRUPT_ENABLE: 0 = Sprite B Flip Done Interrupt

18
RW Disabled 1 = Sprite B Flip Done Interrupt Enabled

0b SPRITE_A_FLIP_DONE_INTERRUPT_ENABLE: 0 = Sprite A Flip Done Interrupt

17
RW Disabled 1 = Sprite A Flip Done Interrupt Enabled

0b PLANE_A_FLIP_DONE_INTERRUPT_ENABLE: 0 = Plane A Flip Done Interrupt

16
RW Disabled 1 = Plane A Flip Done Interrupt Enabled

0b
15:0 RESERVED_2: MBZ
RW

14.11.177 DPINVGTT—Offset 7002Ch

Display Invalid GTT PTE Status Register

Access Method
Type: Memory Mapped I/O Register DPINVGTT: [GTTMMADR_LSB + 2BF20h] + 7002Ch
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

Datasheet 695
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PLANE_B_INVALID_GTT_PTE_STATUS
CURSOR_B_INVALID_GTT_PTE_INTERRUPT_ENABLE

SPRITE_D_INVALID_GTT_PTE_INTERRUPT_ENABLE

SPRITE_B_INVALID_GTT_PTE_INTERRUPT_ENABLE
CURSOR_A_INVALID_GTT_PTE_INTERRUPT_ENABLE

PLANE_A_INVALID_GTT_PTE_INTERRUPT_ENABLE
PLANE_B_INVALID_GTT_PTE_INTERRUPT_ENABLE

SPRITE_A_INVALID_GTT_PTE_INTERRUPT_ENABLE

CURSOR_A_INVALID_GTT_PTE_STATUS

SPRITE_C_INVALID_GTT_PTE_STATUS

SPRITE_A_INVALID_GTT_PTE_STATUS
PLANE_A_INVALID_GTT_PTE_STATUS
RESERVED

CURSOR_B_INVALID_GTT_PTE_STATUS
SPRITE_C_INVALID_GTT_PTE_INTERRUPT_ENABLE

SPRITE_D_INVALID_GTT_PTE_STATUS

SPRITE_B_INVALID_GTT_PTE_STATUS
RESERVED_1
Bit Default &
Description
Range Access

0b
31:24 RESERVED: MBZ
RW
0b CURSOR_B_INVALID_GTT_PTE_INTERRUPT_ENABLE: 0 = Cursor B Invalid GTT
23
RW PTE Interrupt Disabled 1 = Cursor B Invalid GTT PTE Interrupt Enabled

0b CURSOR_A_INVALID_GTT_PTE_INTERRUPT_ENABLE: 0 = Cursor A Invalid GTT

22
RW PTE Interrupt Disabled 1 = Cursor A Invalid GTT PTE Interrupt Enabled

0b SPRITE_D_INVALID_GTT_PTE_INTERRUPT_ENABLE: 0 = Sprite D Invalid GTT

21
RW PTE Interrupt Disabled 1 = Sprite D Invalid GTT PTE Interrupt Enabled

0b SPRITE_C_INVALID_GTT_PTE_INTERRUPT_ENABLE: 0 = Sprite C Invalid GTT PTE

20
RW Interrupt Disabled 1 = Sprite C Invalid GTT PTE Interrupt Enabled

0b PLANE_B_INVALID_GTT_PTE_INTERRUPT_ENABLE: 0 = Plane B Invalid GTT PTE

19
RW Interrupt Disabled 1 = Plane B Invalid GTT PTE Interrupt Enabled

0b SPRITE_B_INVALID_GTT_PTE_INTERRUPT_ENABLE: 0 = Sprite B Invalid GTT PTE

18
RW Interrupt Disabled 1 = Sprite B Invalid GTT PTE Interrupt Enabled

0b SPRITE_A_INVALID_GTT_PTE_INTERRUPT_ENABLE: 0 = Sprite A Invalid GTT PTE

17
RW Interrupt Disabled 1 = Sprite A Invalid GTT PTE Interrupt Enabled

0b PLANE_A_INVALID_GTT_PTE_INTERRUPT_ENABLE: 0 = Plane A Invalid GTT PTE

16
RW Interrupt Disabled 1 = Plane A Invalid GTT PTE Interrupt Enabled

0b
15:8 RESERVED_1: MBZ
RW

0b CURSOR_B_INVALID_GTT_PTE_STATUS: 0 = Cursor B encountered an invalid GTT

7 PTE has not occurred 1 = Cursor B encountered an invalid GTT PTE has occurred
RW/1C AccessType: One to Clear

0b CURSOR_A_INVALID_GTT_PTE_STATUS: 0 = Cursor A encountered an invalid GTT

6 PTE has not occurred 1 = Cursor A encountered an invalid GTT PTE has occurred
RW/1C AccessType: One to Clear

0b SPRITE_D_INVALID_GTT_PTE_STATUS: 0 = Sprite D encountered an invalid GTT

5 PTE has not occurred 1 = Sprite D encountered an invalid GTT PTE has occurred.
RW/1C AccessType: One to Clear

Bay Trail-I SoC

696 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

0b SPRITE_C_INVALID_GTT_PTE_STATUS: 0 = Sprite C encountered an invalid GTT

4 PTE has not occurred 1 = Sprite C encountered an invalid GTT PTE has occurred.
RW/1C AccessType: One to Clear

0b PLANE_B_INVALID_GTT_PTE_STATUS: 0 = Plane B encountered an invalid GTT PTE

3 has not occurred 1 = Plane B encountered an invalid GTT PTE has occurred. AccessType:
RW/1C One to Clear

0b SPRITE_B_INVALID_GTT_PTE_STATUS: 0 = Sprite B encountered an invalid GTT

2 PTE has not occurred 1 = Sprite B encountered an invalid GTT PTE has occurred.
RW/1C AccessType: One to Clear

0b SPRITE_A_INVALID_GTT_PTE_STATUS: 0 = Sprite A encountered an invalid GTT

1 PTE has not occurred 1 = Sprite A encountered an invalid GTT PTE has occurred.
RW/1C AccessType: One to Clear

0b PLANE_A_INVALID_GTT_PTE_STATUS: 0 = Plane A encountered an invalid GTT PTE

0 has not occurred 1 = Plane A encountered an invalid GTT PTE has occurred. AccessType:
RW/1C One to Clear

14.11.178 DSPARB—Offset 70030h

Display Arbitration Control

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) DSPARB: [GTTMMADR_LSB + 2BF20h] + 70030h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 80008000h
31 28 24 20 16 12 8 4 0

1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPRITE_D_START

SPRITE_BSTART
SPRITE_CSTART

SPRITE_ASTART

Bit Default &

Description
Range Access

SPRITE_D_START: This field selects the end of the ram used for Sprite C and the start
of the RAM for Sprite D. If sprite C is unused, this field can be set to the same value as
10000000b Sprite C START. If Sprite D is unused, this field can be set to TOTALSIZE-1. It must be
31:24 programmed to a number greater than or equal to the value in Sprite C START and less
RW than the total size of the RAM (TOTALSIZE). The size of the Sprite C FIFO will be (Sprite
D START-Sprite C START)*64. The size of the Sprite D FIFO will be (TOTALSIZE-Sprite D
START-1) *64 bytes. [DevBLC and DevCTG]: Reserved: Write as zero.
SPRITE_CSTART: This field selects the end of the ram used for display B and the start
0b of the RAM for Sprite C. If display B is unused, this field can be set to zero. The value
23:16
RW should never exceed the size of the RAM (TOTALSIZE). The size of the display B FIFO
will be (Sprite C START)*64 bytes.

Bay Trail-I SoC

Datasheet 697
 Graphics, Video and Display

Bit Default &

Description
Range Access

SPRITE_BSTART: This field selects the end of the ram used for Sprite A and the start
of the RAM for Sprite B. If sprite A is unused, this field can be set to the same value as
10000000b Sprite A START. If Sprite B is unused, this field can be set to TOTALSIZE-1. It must be
15:8 programmed to a number greater than or equal to the value in Sprite A START and less
RW than the total size of the RAM (TOTALSIZE). The size of the Sprite A FIFO will be (Sprite
B START-Sprite A START)*64. The size of the Sprite B FIFO will be (TOTALSIZE-Sprite B
START-1) *64 bytes. [DevBLC and DevCTG]: Reserved: Write as zero.
SPRITE_ASTART: This field selects the end of the ram used for display A and the start
0b of the RAM for Sprite A. If display A is unused, this field can be set to zero. The value
7:0
RW should never exceed the size of the RAM (TOTALSIZE). The size of the display A FIFO
will be (Sprite A START)*64 bytes.

14.11.179 FW1—Offset 70034h

Display FIFO Watermark Control 1

Access Method
Type: Memory Mapped I/O Register
FW1: [GTTMMADR_LSB + 2BF20h] + 70034h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 3F8F0F0Fh
31 28 24 20 16 12 8 4 0

0 0 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
DISPLAY_PLANE_B_FIFO_WATERMARK

DISPLAY_PLANE_A_FIFO_WATERMARK
DISPLAY_FIFO_SELF_REFRESH_WATERMARK_PROGRAMMING

RESERVED_

CURSOR_B_FIFO_WATERMARK_

Bay Trail-I SoC

698 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

DISPLAY_FIFO_SELF_REFRESH_WATERMARK_PROGRAMMING: This register

defines the value of the watermark used by the Display streamer in case the CPU is in
001111111 C2/C3/C4 and the memory has entered self refresh. Number in 64Bs of space in FIFO
b above which the Display Stream will generate requests to Memory (Value should be as
31:23
recommended in the high priority bandwidth analysis spreadsheet).Note [DevCL,
RW DevCTG, DevCDV]: When calculating watermark values for 15/16bpp display formats,
assume 32bpp for purposes of calculation using the high priority bandwidth analysis
spreadsheet.
0b
22 RESERVED_: MBZ
RW
CURSOR_B_FIFO_WATERMARK_: Number in 64Bs of space in the Cursor B FIFO
001111b above which the Cursor B Stream will generate requests to Memory (Value should be as
21:16
RW recommended in the high priority bandwidth analysis spreadsheet). DevBW, DevCL,
DevCDV] Always program to 8.
DISPLAY_PLANE_B_FIFO_WATERMARK: Number in 64Bs of space in FIFO above
00001111b which the Display B Stream will generate requests to Memory (Value should be as
15:8
RW recommended in the high priority bandwidth analysis spreadsheet). [DevBW, DevCL,
DevCDV] Always program to 8.

DISPLAY_PLANE_A_FIFO_WATERMARK: Number in 64Bs of space in FIFO above

00001111b which the Display A Stream will generate requests to Memory (Value should be as
7:0
RW recommended in the high priority bandwidth analysis spreadsheet). [DevBW, DevCL,
DevCDV] Always program to 8.

14.11.180 FW2—Offset 70038h

Display FIFO Watermark Control 2

Access Method
Type: Memory Mapped I/O Register
FW2: [GTTMMADR_LSB + 2BF20h] + 70038h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 0B0F0F0Fh

Bay Trail-I SoC

Datasheet 699
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 1 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
RESERVED

DEVBLKC_DEVCTG_DISPLAY_PLANE_SPRITE_A_FIFO_WATERMARK
RESERVED_1

RESERVED_2

RESERVED_3

RESERVED_4

CURSOR_A_FIFO_WATERMARK_
Bit Default &
Description
Range Access

0b RESERVED: [DevCDV]: [DevCTG] FBC SR Watermark Enable: Enables the FBC

31
RW watermarks to be used in the fetch calculation 0: disabled 1: enabled

0b RESERVED_1: [DevCDV]: [DevCTG] FBC SR Watermark: Number of equivalent lines of

30:28
RW the primary display SR watermark

1011b RESERVED_2: [DevCDV] [DevCTG] FBC SR HPLL Watermark: Number of equivalent

27:24
RW lines of the primary display SR HPLL watermark.

RESERVED_3: [DevCDV]: [DevBLKC, DevCTG] Display Plane Sprite B FIFO Watermark

00001111b Number in 64Bs of space in FIFO above which the Display Sprite B Stream will generate
23:16
RW requests to Memory (Value should be as recommended in the high priority bandwidth
analysis spreadsheet).
0b
15:14 RESERVED_4: : MBZ
RW
CURSOR_A_FIFO_WATERMARK_: Number in 64Bs of space in the Cursor A FIFO
001111b above which the Cursor A Stream will generate requests to Memory (Value should be as
13:8
RW recommended in the high priority bandwidth analysis spreadsheet). DevBW, DevCL,
DevCDV] Always program to 8.

DEVBLKC_DEVCTG_DISPLAY_PLANE_SPRITE_A_FIFO_WATERMARK: Number in
64Bs of space in FIFO above which the Display Sprite A Stream will generate requests to
00001111b Memory DevBW, DevCL] Display Plane C FIFO Watermark. Number in 64Bs of space in
7:0
RW FIFO above which the Display C Stream will generate requests to Memory (Value should
be as recommended in the high priority bandwidth analysis spreadsheet). [DevBW,
DevCL, DevCDV] Always program to 8.

14.11.181 FW3—Offset 7003Ch

Display FIFO Watermark Control 3

Bay Trail-I SoC

700 Datasheet
Graphics, Video and Display

Access Method
Type: Memory Mapped I/O Register
FW3: [GTTMMADR_LSB + 2BF20h] + 7003Ch
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENABLE_HPLL_OFF_DURING_SELF_REFRESH

CURSOR_FIFO_SELF_REFRESH_WATERMARK

HPLL_SELF_REFRESH_CURSOR_WATERMARK

HPLL_SELF_REFRESH_DISPLAY_WATERMARK
RESERVED_1

RESERVED_
RESERVED

Bit Default &

Description
Range Access

ENABLE_HPLL_OFF_DURING_SELF_REFRESH: . 0 = Disabled 1 = Enabled [DevCL]

This bit may be enabled only if the BLC_PWM_CTL duty cycle register offset (0x61254)
is programmed to 100% and non-legacy backlight is enabled. This restriction does not
0b apply when I2C is used for back light modulation. [DevCL] When one or more display
31 pipes are enabled, this bit should be disabled before accessing the 6XXXh MMIO register
RW address space. Software must follow these steps: disable this bit (if enabled and one
display pipe is enabled) wait for next vblank (switch from hrawclk back to cdclk will
occur) access the 6XXXh address space as needed re-enable this bit Note that the wait
on next vblank step requires an enabled display pipe.

0b
30 RESERVED: : MBZ
RW

CURSOR_FIFO_SELF_REFRESH_WATERMARK: . Number in 64Bs of space in the

0b Cursor FIFO above which the Cursor Stream will generate requests to Memory during
29:24
RW self -refresh. (Value should be as recommended in the high priority bandwidth analysis
spreadsheet).
0b
23:22 RESERVED_1: : MBZ
RW
HPLL_SELF_REFRESH_CURSOR_WATERMARK: . Number in 64Bs of space in the
0b Cursor FIFO above which the Cursor Stream will generate requests to Memory during
21:16
RW HPLL self -refresh. (Value should be as recommended in the high priority bandwidth
analysis spreadsheet).
0b
15:9 RESERVED_: MBZ
RW
HPLL_SELF_REFRESH_DISPLAY_WATERMARK: . Number in 64Bs of space in the
0b FIFO above which the Display Stream will generate requests to Memory during HPLL self
8:0
RW -refresh. (Value should be as recommended in the high priority bandwidth analysis
spreadsheet).

Bay Trail-I SoC

Datasheet 701
 Graphics, Video and Display

14.11.182 PIPEAFRAMECOUNT—Offset 70040h

Pipe A Frame Counter

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) PIPEAFRAMECOUNT: [GTTMMADR_LSB + 2BF20h] + 70040h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PIPE_A_FRAME_COUNT

Bit Default &

Description
Range Access

0b PIPE_A_FRAME_COUNT: Provides read back of the display pipe frame counter. This
31:0 counter increments on every start of vertical blank and rolls over back to 0 after 2^32
RO frames

14.11.183 PIPEAFLIPCOUNT—Offset 70044h

Pipe A Flip Counter

Access Method
Type: Memory Mapped I/O Register PIPEAFLIPCOUNT: [GTTMMADR_LSB + 2BF20h] + 70044h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PIPE_A_FLIP_COUNTER

Bay Trail-I SoC

702 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

PIPE_A_FLIP_COUNTER: Provides read back of the display pipe flip counter. This
0b counter increments on each flip of the surface of the primary plane on this pipe. This
31:0
RO includes command streamer asynchronous and synchronous flips and any MMIO writes
to the primary plane surface address. It rolls over back to 0 after 2^32 flips

14.11.184 PIPEAMSAMISC—Offset 70048h

Pipe A MSA MISC

Access Method
Type: Memory Mapped I/O Register
PIPEAMSAMISC: [GTTMMADR_LSB + 2BF20h] + 70048h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HARDWARE_DRIVE_MSA_MISC1_ENABLE

MSA_MISC1_FIELD_S3D
RESERVED

Bit Default &

Description
Range Access

HARDWARE_DRIVE_MSA_MISC1_ENABLE: This bit enables hardware to drive MSA

MISC1 bit3:1 with the stero 3D left/right eye field indication. Hardware will drive 000
when S3D mode is disabled, 001 when enabled and the upcoming video frame is right
0b eye, 011 when enabled and the upcoming video frame is left eye. When this bit is
31
RW disabled, software may manually program the MSA MISC1 Field S3D field in bit 2:0 in
this register to set MISC1 bit 3:1 0 = Disable hardware driving MSA MISC1 bit 3:1. Allow
software to manually program MSA MISC1 bit3:1 through MSA_MISC1_FIELD_S3D
(default) 1 = Enable hardware to drive MSA MISC1 bit3:1 for S3D
0b
30:3 RESERVED: Reserved.
RW
MSA_MISC1_FIELD_S3D: This field provides software to manually program MSC1
stero video attribute for DisplayPort: 000 = No stereo video transported 001 = For
0b progressive video, the next (upcoming) video frame is RIGHT eye 010 = Reserved 011
2:0 = For progressive video, the next (upcoming) video frame is LEFT eye 100 = Stacked
RW top and bottom top half represents left-eye view and bottom half represents right-eye
view 101 = Stacked top and bottom top half represents right-eye view and bottom half
represents left-eye view

Bay Trail-I SoC

Datasheet 703
 Graphics, Video and Display

14.11.185 DDL1—Offset 70050h

Display FIFO Drain Latency 1

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) DDL1: [GTTMMADR_LSB + 2BF20h] + 70050h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DISPLAY_PLANE_A_DRAIN_LATENCY_PRECISION_SELECT
SPRITE_B_DRAIN_LATENCY_VALUE

DISPLAY_SPRITE_A_DRAIN_LATENCY_PRECISION_SELECT

DISPLAY_PLANE_A_DRAIN_LATENCY_VALUE
DISPLAY_CURSOR_A_DRAIN_LATENCY_PRECISION_SELECT

CURSOR_A_DRAIN_LATENCY_VALUE

DISPLAY_SPRITE_B_DRAIN_LATENCY_PRECISION_SELECT

SPRITE_A_DRAIN_LATENCY_VALUE

Bit Default &

Description
Range Access

DISPLAY_CURSOR_A_DRAIN_LATENCY_PRECISION_SELECT: [DevVLVP] 1 use

0b 64 as precision multipler to increase precision to be stored in 7-bit Cursor A drain
31
RW latency value 0 use 32 as precision multipler to increase percision to be stored in 7-bit
Cursor A drain latency value

0b CURSOR_A_DRAIN_LATENCY_VALUE: [DevVLVP] For cursor latency, 4 BPP is

30:24 assumed for all cursor formats. : Programmable drain latency value in time ticks per
RW 64B FIFO entry
DISPLAY_SPRITE_B_DRAIN_LATENCY_PRECISION_SELECT: [DevVLVP] 1 use 64
0b as precision multipler to increase precision to be stored in 7-bit Sprite B drain latency
23
RW value 0 use 32 as precision multipler to increase percision to be stored in 7-bit Sprite B
drain latency value
0b SPRITE_B_DRAIN_LATENCY_VALUE: [DevVLVP] Programmable drain latency value
22:16
RW in time ticks per 64B FIFO entry

DISPLAY_SPRITE_A_DRAIN_LATENCY_PRECISION_SELECT: [DevVLVP] 1 use 64

0b as precision multipler to increase precision to be stored in 7-bit Sprite A drain latency
15
RW value 0 use 32 as precision multipler to increase percision to be stored in 7-bit Sprite A
drain latency value

Bay Trail-I SoC

704 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

0b SPRITE_A_DRAIN_LATENCY_VALUE: [DevVLVP] Programmable drain latency value

14:8
RW in time ticks per 64B FIFO entry

DISPLAY_PLANE_A_DRAIN_LATENCY_PRECISION_SELECT: [DevVLVP] 1 use 64

0b as precision multipler to increase precision to be stored in 7-bit Plane A drain latency
7
RW value 0 use 32 as precision multipler to increase percision to be stored in 7-bit Plane A
drain latency value
0b DISPLAY_PLANE_A_DRAIN_LATENCY_VALUE: [DevVLVP] Programmable drain
6:0
RW latency value in time ticks per 64B FIFO entry

14.11.186 DDL2—Offset 70054h

Display FIFO Drain Latency 2

Access Method
Type: Memory Mapped I/O Register DDL2: [GTTMMADR_LSB + 2BF20h] + 70054h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DISPLAY_PLANE_B_DRAIN_LATENCY_VALUE
DISPLAY_CURSOR_B_DRAIN_LATENCY_PRECISION_SELECT

DISPLAY_SPRITE_D_DRAIN_LATENCY_PRECISION_SELECT

DISPLAY_SPRITE_C_DRAIN_LATENCY_PRECISION_SELECT
SPRITE_D_DRAIN_LATENCY_VALUE

SPRITE_C_DRAIN_LATENCY_VALUE

DISPLAY_PLANE_B_DRAIN_LATENCY_PRECISION_SELECT
CURSOR_B_DRAIN_LATENCY_VALUE

Bit Default &

Description
Range Access

DISPLAY_CURSOR_B_DRAIN_LATENCY_PRECISION_SELECT: [DevVLVP] 1 use

0b 64 as precision multipler to increase precision to be stored in 7-bit Cursor B drain
31
RW latency value 0 use 32 as precision multipler to increase percision to be stored in 7-bit
Cursor B drain latency value

Bay Trail-I SoC

Datasheet 705
 Graphics, Video and Display

Bit Default &

Description
Range Access

0b CURSOR_B_DRAIN_LATENCY_VALUE: [DevVLVP] For cursor latency, 4 BPP is

30:24
RW assumed for all cursor formats

DISPLAY_SPRITE_D_DRAIN_LATENCY_PRECISION_SELECT: [DevVLVP] 1 use 64

0b as precision multipler to increase precision to be stored in 7-bit Sprite D drain latency
23
RW value 0 use 32 as precision multipler to increase percision to be stored in 7-bit Sprite D
drain latency value
0b
22:16 SPRITE_D_DRAIN_LATENCY_VALUE: [DevVLVP]
RW
DISPLAY_SPRITE_C_DRAIN_LATENCY_PRECISION_SELECT: [DevVLVP] 1 use 64
0b as precision multipler to increase precision to be stored in 7-bit Sprite C drain latency
15
RW value 0 use 32 as precision multipler to increase percision to be stored in 7-bit Sprite C
drain latency value

0b
14:8 SPRITE_C_DRAIN_LATENCY_VALUE: [DevVLVP]
RW

DISPLAY_PLANE_B_DRAIN_LATENCY_PRECISION_SELECT: [DevVLVP] 1 use 64

0b as precision multipler to increase precision to be stored in 7-bit Plane B drain latency
7
RW value 0 use 32 as precision multipler to increase percision to be stored in 7-bit Plane B
drain latency value
0b
6:0 DISPLAY_PLANE_B_DRAIN_LATENCY_VALUE: [DevVLVP]
RW

14.11.187 DSPARB2—Offset 70060h

Display Arbitration Control 2

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) DSPARB2: [GTTMMADR_LSB + 2BF20h] + 70060h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00001111h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1
SPRITE_CSTART_HIGH_ORDER

RESERVED_MBZ

RESERVED_MBZ_1

SPRITE_A_START_HIGH_ORDER
RESERVED

RESERVED_1
SPRITE_D_START_HIGH_ORDER

SPRITE_B_START_HIGH_ORDER

Bit Default &

Description
Range Access

0b
31:13 RESERVED: Reserved.
RW

Bay Trail-I SoC

706 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

SPRITE_D_START_HIGH_ORDER: This field is the high order bits for Sprite D Start
pointer. Combinbed with lower order 8-bit Sprite D Start pointer, this field selects the
end of the ram used for Sprite C and the start of the RAM for Sprite D. If sprite C is
1b unused, this field can be set to the same value as Sprite C START. If Sprite D is unused,
12 this field can be set to TOTALSIZE-1. It must be programmed to a number greater than
RW or equal to the value in Sprite C START and less than the total size of the RAM
(TOTALSIZE). The size of the Sprite C FIFO will be (Sprite D START-Sprite C START)*64.
The size of the Sprite D FIFO will be (TOTALSIZE-Sprite D START-1) *64 bytes. [DevBLC
and DevCTG]: Reserved: Write as zero.
0b
11:9 RESERVED_1: Reserved.
RW
SPRITE_CSTART_HIGH_ORDER: This field is the high order bits for Sprite C Start
1b pointer. Combinbed with lower order 8-bit Sprite C Start pointer, this field selects the
8 end of the ram used for display B and the start of the RAM for Sprite C. If display B is
RW unused, this field can be set to zero. The value should never exceed the size of the RAM
(TOTALSIZE). The size of the display B FIFO will be (Sprite C START)*64 bytes.

0b
7:5 RESERVED_MBZ: Reserved.
RW

SPRITE_B_START_HIGH_ORDER: This field is the high order bits for Sprite B Start
pointer. Combinbed with lower order 8-bit Sprite B Start pointer, this field selects the
end of the ram used for Sprite A and the start of the RAM for Sprite B. If sprite A is
1b unused, this field can be set to the same value as Sprite A START. If Sprite B is unused,
4 this field can be set to TOTALSIZE-1. It must be programmed to a number greater than
RW or equal to the value in Sprite A START and less than the total size of the RAM
(TOTALSIZE). The size of the Sprite A FIFO will be (Sprite B START-Sprite A START)*64.
The size of the Sprite B FIFO will be (TOTALSIZE-Sprite B START-1) *64 bytes. [DevBLC
and DevCTG]: Reserved: Write as zero.

0b
3:1 RESERVED_MBZ_1: Reserved.
RW

SPRITE_A_START_HIGH_ORDER: This field is the high order bits for Sprite A Start
1b pointer. Combinbed with lower order 8-bit Sprite A Start pointer, this field selects the
0 end of the ram used for display A and the start of the RAM for Sprite A. If display A is
RW unused, this field can be set to zero. The value should never exceed the size of the RAM
(TOTALSIZE). The size of the display A FIFO will be (Sprite A START)*64 bytes.

14.11.188 DSPHOWM—Offset 70064h

Display FIFO WM High Order

Access Method
Type: Memory Mapped I/O Register DSPHOWM: [GTTMMADR_LSB + 2BF20h] + 70064h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

Datasheet 707
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SPRITE_D_FIFO_WATERMARK_HIGH_ORDER

SPRITE_B_FIFO_WATERMARK_HIGH_ORDER

SPRITE_A_FIFO_WATERMARK_HIGH_ORDER
SPRITE_C_FIFO_WATERMARK_HIGH_ORDER

DISPLAY_PLANE_B_FIFO_WATERMARK_HIGH_ORDER

DISPLAY_PLANE_A_FIFO_WATERMARK_HIGH_ORDER
RESERVED

DISPLAY_FIFO_SELF_REFRESH_WATERMARK_HIGH_ORDER_PROGRAMMING

RESERVED_1

RESERVED_2

RESERVED_3

RESERVED_4

RESERVED_5

RESERVED_6
Bit Default &
Description
Range Access

0b
31:25 RESERVED: Reserved.
RW

DISPLAY_FIFO_SELF_REFRESH_WATERMARK_HIGH_ORDER_PROGRAMMING:
This field is the high order bit for the SR WM pointer . Combined with the lower order 9-
bit SR FIFO WM pointer, it forms a 10-bit SR FIFO WM pointer. This register defines the
0b value of the watermark used by the Display streamer in case the CPU is in C2/C3/C4
24 and the memory has entered self refresh. Number in 64Bs of space in FIFO above which
RW the Display Stream will generate requests to Memory (Value should be as recommended
in the high priority bandwidth analysis spreadsheet).Note [DevCL, DevCTG, DevCDV]:
When calculating watermark values for 15/16bpp display formats, assume 32bpp for
purposes of calculation using the high priority bandwidth analysis spreadsheet.

0b
23:21 RESERVED_1: Reserved.
RW

SPRITE_D_FIFO_WATERMARK_HIGH_ORDER: This field is the high order bit for

0b Sprite D FIFO WM. Combined with lower order 8-bit Sprite D FIFO WM, it forms a 9-bit
20 Sprite D FIFO WM pointer. Number in 64Bs of space in FIFO above which the Display A
RW Stream will generate requests to Memory (Value should be as recommended in the high
priority bandwidth analysis spreadsheet).
0b
19:17 RESERVED_2: Reserved.
RW
SPRITE_C_FIFO_WATERMARK_HIGH_ORDER: This field is the high order bit for
0b Sprite C FIFO WM. Combined with lower order 8-bit Sprite C FIFO WM, it forms a 9-bit
16 Sprite C FIFO WM pointer. Number in 64Bs of space in FIFO above which the Display A
RW Stream will generate requests to Memory (Value should be as recommended in the high
priority bandwidth analysis spreadsheet).

Bay Trail-I SoC

708 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

0b
15:13 RESERVED_3: Reserved.
RW
DISPLAY_PLANE_B_FIFO_WATERMARK_HIGH_ORDER: This field is the high
0b order bit for Display B FIFO WM. Combined with lower order 8-bit Display B FIFO WM, it
12 forms a 9-bit Display B FIFO WM pointer. Number in 64Bs of space in FIFO above which
RW the Display A Stream will generate requests to Memory (Value should be as
recommended in the high priority bandwidth analysis spreadsheet).

0b
11:9 RESERVED_4: Reserved.
RW

SPRITE_B_FIFO_WATERMARK_HIGH_ORDER: This field is the high order bit for

0b Sprite B FIFO WM. Combined with lower order 8-bit Sprite B FIFO WM, it forms a 9-bit
8 Sprite B FIFO WM pointer. Number in 64Bs of space in FIFO above which the Display A
RW Stream will generate requests to Memory (Value should be as recommended in the high
priority bandwidth analysis spreadsheet).
0b
7:5 RESERVED_5: MBZ
RW
SPRITE_A_FIFO_WATERMARK_HIGH_ORDER: This field is the high order bit for
0b Sprite A FIFO WM. Combined with lower order 8-bit Sprite A FIFO WM, it forms a 9-bit
4 Sprite A FIFO WM pointer. Number in 64Bs of space in FIFO above which the Display A
RW Stream will generate requests to Memory (Value should be as recommended in the high
priority bandwidth analysis spreadsheet).
0b
3:1 RESERVED_6: MBZ
RW
DISPLAY_PLANE_A_FIFO_WATERMARK_HIGH_ORDER: This field is the high
0b order bit for Display A FIFO WM. Combined with lower order 8-bit Display A FIFO WM, it
0 forms a 9-bit Display A FIFO WM pointer. Number in 64Bs of space in FIFO above which
RW the Display A Stream will generate requests to Memory (Value should be as
recommended in the high priority bandwidth analysis spreadsheet).

14.11.189 DSPHOWM1—Offset 70068h

Display FIFO WM1 High Order

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) DSPHOWM1: [GTTMMADR_LSB + 2BF20h] + 70068h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

Datasheet 709
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DISPLAY_PLANE_A_FIFO_WATERMARK1_HIGH_ORDER
SPRITE_D_FIFO_WATERMARK1_HIGH_ORDER
RESERVED

SPRITE_B_FIFO_WATERMARK1_HIGH_ORDER

SPRITE_A_FIFO_WATERMARK1_HIGH_ORDER
SPRITE_C_FIFO_WATERMARK1_HIGH_ORDER

DISPLAY_PLANE_B_FIFO_WATERMARK1_HIGH_ORDER
DISPLAY_FIFO_SELF_REFRESH_WATERMARK1_HIGH_ORDER_PROGRAMMING

RESERVED_1

RESERVED_2

RESERVED_3

RESERVED_4

RESERVED_5

RESERVED_6
Bit Default &
Description
Range Access

0b
31:25 RESERVED: Reserved.
RW
DISPLAY_FIFO_SELF_REFRESH_WATERMARK1_HIGH_ORDER_PROGRAMMING
: This field is the high order bit for the SR WM1 pointer . Combined with the lower order
9-bit SR FIFO WM1 pointer, it forms a 10-bit SR FIFO WM1 pointer. This register defines
0b the value of the watermark used by the Display streamer in case the CPU is in C2/C3/C4
24 and the memory has entered self refresh. Number in 64Bs of space in FIFO above which
RW the Display Stream will generate requests to Memory (Value should be as recommended
in the high priority bandwidth analysis spreadsheet).Note [DevCL, DevCTG, DevCDV]:
When calculating watermark values for 15/16bpp display formats, assume 32bpp for
purposes of calculation using the high priority bandwidth analysis spreadsheet.
0b
23:21 RESERVED_1: Reserved.
RW
SPRITE_D_FIFO_WATERMARK1_HIGH_ORDER: This field is the high order bit for
0b Sprite D FIFO WM1. Combined with lower order 8-bit Sprite D FIFO WM1, it forms a 9-
20 bit Sprite D FIFO WM1 pointer. Number in 64Bs of space in FIFO above which the Display
RW A Stream will generate requests to Memory (Value should be as recommended in the
high priority bandwidth analysis spreadsheet).
0b
19:17 RESERVED_2: Reserved.
RW
SPRITE_C_FIFO_WATERMARK1_HIGH_ORDER: This field is the high order bit for
0b Sprite C FIFO WM1. Combined with lower order 8-bit Sprite C FIFO WM1, it forms a 9-bit
16 Sprite C FIFO WM1 pointer. Number in 64Bs of space in FIFO above which the Display A
RW Stream will generate requests to Memory (Value should be as recommended in the high
priority bandwidth analysis spreadsheet).

Bay Trail-I SoC

710 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

0b
15:13 RESERVED_3: Reserved.
RW
DISPLAY_PLANE_B_FIFO_WATERMARK1_HIGH_ORDER: This field is the high
0b order bit for Display B FIFO WM1. Combined with lower order 8-bit Display B FIFO WM1,
12 it forms a 9-bit Display B FIFO WM1 pointer. Number in 64Bs of space in FIFO above
RW which the Display A Stream will generate requests to Memory (Value should be as
recommended in the high priority bandwidth analysis spreadsheet).

0b
11:9 RESERVED_4: Reserved.
RW

SPRITE_B_FIFO_WATERMARK1_HIGH_ORDER: This field is the high order bit for

0b Sprite B FIFO WM1. Combined with lower order 8-bit Sprite B FIFO WM1, it forms a 9-bit
8 Sprite B FIFO WM1 pointer. Number in 64Bs of space in FIFO above which the Display A
RW Stream will generate requests to Memory (Value should be as recommended in the high
priority bandwidth analysis spreadsheet).
0b
7:5 RESERVED_5: MBZ
RW
SPRITE_A_FIFO_WATERMARK1_HIGH_ORDER: This field is the high order bit for
0b Sprite A FIFO WM1. Combined with lower order 8-bit Sprite A FIFO WM1, it forms a 9-bit
4 Sprite A FIFO WM1 pointer. Number in 64Bs of space in FIFO above which the Display A
RW Stream will generate requests to Memory (Value should be as recommended in the high
priority bandwidth analysis spreadsheet).
0b
3:1 RESERVED_6: MBZ
RW
DISPLAY_PLANE_A_FIFO_WATERMARK1_HIGH_ORDER: This field is the high
0b order bit for Display A FIFO WM1. Combined with lower order 8-bit Display A FIFO WM1,
0 it forms a 9-bit Display A FIFO WM1 pointer. Number in 64Bs of space in FIFO above
RW which the Display A Stream will generate requests to Memory (Value should be as
recommended in the high priority bandwidth analysis spreadsheet).

14.11.190 FW4—Offset 70070h

Display FIFO Watermark1 Control 4

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) FW4: [GTTMMADR_LSB + 2BF20h] + 70070h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00040404h

Bay Trail-I SoC

Datasheet 711
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0

RESERVED

DISPLAY_SPRITE_A_FIFO_WATERMARK1
RESERVED_1
DISPLAY_SPRITE_B_FIFO_WATERMARK1

CURSOR_A_FIFO_WATERMARK1
Bit Default &
Description
Range Access

0b
31:24 RESERVED: : MBZ
RW

00000100b DISPLAY_SPRITE_B_FIFO_WATERMARK1: [DevCDV] Number in 64Bs of space in

23:16
RW FIFO above which the Display Sprite B Stream will generate request with status 2

0b
15:14 RESERVED_1: : MBZ
RW

000100b CURSOR_A_FIFO_WATERMARK1: DevCDV] Number in 64Bs of space in the Cursor A

13:8 FIFO above which the Cursor A Stream will generate requests with status 2 to Memory
RW (Value should be as recommended in the high priority bandwidth analysis spreadsheet).

00000100b DISPLAY_SPRITE_A_FIFO_WATERMARK1: DevCDV] Number in 64Bs of space in

7:0 FIFO above which the Display Sprite A Stream will generate request with status 2 (Value
RW should be as recommended in the high priority bandwidth analysis spreadsheet).

14.11.191 FW5—Offset 70074h

Display FIFO Watermark1 Control 5

Access Method
Type: Memory Mapped I/O Register FW5: [GTTMMADR_LSB + 2BF20h] + 70074h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 04040404h

Bay Trail-I SoC

712 Datasheet
Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0

RESERVED
DISPLAY_B_FIFO_WATERMARK1

DISPLAY_A_FIFO_WATERMARK1

CURSOR_B_FIFO_WATERMARK1

RESERVED_1

CURSORFIFO_SELF_REFRESH_WATERMARK1
Bit Default &
Description
Range Access

00000100b DISPLAY_B_FIFO_WATERMARK1: [DevCDV] Number in 64Bs of space in FIFO above

31:24
RW which the Display B Stream will generate request with status 2

00000100b DISPLAY_A_FIFO_WATERMARK1: [DevCDV] Number in 64Bs of space in FIFO above

23:16
RW which the Display A Stream will generate request with status 2

0b
15:14 RESERVED: : MBZ
RW

000100b CURSOR_B_FIFO_WATERMARK1: DevCDV] Number in 64Bs of space in the Cursor B

13:8 FIFO above which the Cursor B Stream will generate requests with status 2 to Memory
RW (Value should be as recommended in the high priority bandwidth analysis spreadsheet).

0b
7:6 RESERVED_1: : MBZ
RW

CURSORFIFO_SELF_REFRESH_WATERMARK1: DevCDV] Number in 64Bs of space

000100b in FIFO above which the Display Cursor Stream will generate request with status 2
5:0
RW during memory SR (Value should be as recommended in the high priority bandwidth
analysis spreadsheet).

14.11.192 FW6—Offset 70078h

Display FIFO Watermark1 Control 6

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) FW6: [GTTMMADR_LSB + 2BF20h] + 70078h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000078h

Bay Trail-I SoC

Datasheet 713
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0

RESERVED

DISPLAY_FIFO_SELF_REFRESH_WATERMARK1
Bit Default &
Description
Range Access

0b
31:9 RESERVED: : MBZ
RW

001111000 DISPLAY_FIFO_SELF_REFRESH_WATERMARK1: DevCDV] Number in 64Bs of

b space in FIFO above which the Display A/B Streamer will generate request with status 2
8:0
during max fifo mode (Value should be as recommended in the high priority bandwidth
RW analysis spreadsheet).

14.11.193 FW7—Offset 7007Ch

Display FIFO Watermark Control 7

Access Method
Type: Memory Mapped I/O Register FW7: [GTTMMADR_LSB + 2BF20h] + 7007Ch
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 040F040Fh

Bay Trail-I SoC

714 Datasheet
Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 1 0 0 0 0 0 0 1 1 1 1

DISPLAY_SPRITE_C_FIFO_WATERMARK
DISPLAY_SPRITE_C_FIFO_WATERMARK1
DISPLAY_SPRITE_D_FIFO_WATERMARK
DISPLAY_SPRITE_D_FIFO_WATERMARK1

Bit Default &

Description
Range Access

00000100b DISPLAY_SPRITE_D_FIFO_WATERMARK1: [DevVLVP] Number in 64Bs of space in

31:24
RW FIFO above which the Display Sprite D Stream will generate request with status 2

00001111b DISPLAY_SPRITE_D_FIFO_WATERMARK: [DevVLVP] Number in 64Bs of space in

23:16
RW FIFO above which the Display Sprite D Stream will generate request with status 2

00000100b DISPLAY_SPRITE_C_FIFO_WATERMARK1: DevVLVP] Number in 64Bs of space in

15:8
RW FIFO above which the Display Sprite C Stream will generate request with status 2

00001111b DISPLAY_SPRITE_C_FIFO_WATERMARK: DevVLVP] Number in 64Bs of space in

7:0
RW FIFO above which the Display Sprite C Stream will generate request with status 2

14.11.194 CURACNTR—Offset 70080h

Cursor A Control Register

Access Method
Type: Memory Mapped I/O Register CURACNTR: [GTTMMADR_LSB + 2BF20h] + 70080h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED

PIPE_SELECT

POPUP_CURSOR_ENABLED
CURSOR_GAMMA_ENABLE

CURSOR_MODE_SELECT_BIT

CURSOR_MODE_SELECT
RESERVED_1

_180ROTATION

RESERVED_2

RESERVED_3
RESERVED_4

Bay Trail-I SoC

Datasheet 715
 Graphics, Video and Display

Bit Default &

Description
Range Access

0b
31:30 RESERVED: Write as zero.
RW
PIPE_SELECT: [DevBW, DevCL, DevCDV] A state machine handles the synchronization
of the switch to both vertical blank signals. So as far as the software is concerned, when
0b both display pipes are being used, it can be switched at any time; the hardware will
29:28
RW synchronize the switch. 00 = HW cursor is attached to Display Pipe A. This is the default
after reset. 01 = HW cursor is attached to Display Pipe B. 10 = Reserved for pipe C 11 =
Reserved for pipe D [DevBLC] and [DevCTG] Reserved: Write as zero.
POPUP_CURSOR_ENABLED: . This bit should be turned on when using Cursor A as a
0b popup cursor. When in popup mode, hardware interprets the cursor base address as a
27
RW physical address instead of a graphics address.0 = Cursor A is hi-res 1 = Cursor A is
popup

CURSOR_GAMMA_ENABLE: This bit only has an effect when using the cursor in a
0b non-VGA mode. In VGA pop-up operation, the cursor data will always bypass the
26
RW gamma (palette) unit. 0 = Cursor pixel data bypasses gamma correction or palette
(default). 1 = Cursor pixel data is gamma to be corrected in the pipe.
0b
25:16 RESERVED_1: Write as zero
RW
_180ROTATION: This mode causes the cursor to be rotated 180 . In addition to setting
0b this bit, software must also set the base address to the lower right corner of the
15 unrotated image. Only 32 bits per pixel cursors can be rotated. This field must be zero
RW when the cursor format is 2 bits per pixel. 0 = No rotation 1 = 180 Rotation of 32 bit per
pixel cursors

0b
14:6 RESERVED_2: Reserved.
RW

0b
5 CURSOR_MODE_SELECT_BIT: See following table.
RW

0b
4 RESERVED_3: Reserved.
RW

0b
3 RESERVED_4: Reserved.
RW

0b CURSOR_MODE_SELECT: These three bits together with bit 5 select the mode for
2:0
RW cursor as shown in the following table.

14.11.195 CURABASE—Offset 70084h

Cursor A Base Address Register

Access Method
Type: Memory Mapped I/O Register
CURABASE: [GTTMMADR_LSB + 2BF20h] + 70084h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

716 Datasheet
Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DECRYPTION_REQUEST

POPUP_CURSOR_BASE_ADDRESS_MSBS
CURSOR_BASE_ADDRESS

RESERVED
Bit Default &
Description
Range Access

CURSOR_BASE_ADDRESS: . This field specifies bits 31:6 of the graphics address of

the base of the cursor. On [DevBW] and [DevCL] if the cursor is a popup, this field
specifies bits 31:6 of the physical address of the base of the cursor, and bits 35:32 of
the address are specified in the LSBs of this register. Popup cursor mode is selected
within the CURACNTR register.The cursor surface address must be 4K byte aligned. The
cursor must be in linear memory, it cannot be tiled. When performing 180 rotation, this
offset must be the difference between the last pixel of the last line of the cursor data in
its unrotated orientation and the cursor surface address. A write to this register also
acts as a trigger event to force the update of active registers from the staging registers
0b on the next display event. Each cursor register is double-buffered. The CPU writes to a
31:6 set of holding registers. The active registers are updated from the holding registers
RW following the leading edge of the vertical blank pulse. The update is postponed until the
next vblank if a write cycle is active to any of the cursor registers at the time of the
vblank. The update is also postponed if a write sequence is in progress. It is assumed
that if the cursor mode is changed, the cursor image will also be changed. To prevent
the cursor from appearing when it is only partially programmed, the active registers will
not be updated until both the cursor control and base address registers have been
programmed. If the cursor control register is written, the cursor base address must also
be written before the change will be effective. However, the base address register may
be changed (e.g., to change the shape of the cursor) without also writing to the control
register. If both are to be written, the control register must be written first.
0b
5 RESERVED: MBZ
RW
DECRYPTION_REQUEST: This bit requests decryption to be enabled for this plane.
This request will be qualified with the separate decryption allow message in order to
0b create the decryption enable. This bit is only allowed to change on a synchronous flip,
4 but once set with a synchronous flip, the bit can remain set while using asynchronous
RW flips. This value is loaded into the surface base address register of the associated plane.
Usage must conform to the rules outlined in the plane surface base address register. 0 =
Decryption request disabled (default) 1 = Decryption request enabled

0b POPUP_CURSOR_BASE_ADDRESS_MSBS: ([DevBW] and [DevCL] Only). This field

3:0 specifies bits 35:32 of the popup cursor physical address. If popup mode is not selected,
RW this field is ignored.

14.11.196 CURAPOS—Offset 70088h

Cursor A Position Register

Access Method

Bay Trail-I SoC

Datasheet 717
 Graphics, Video and Display

Type: Memory Mapped I/O Register

CURAPOS: [GTTMMADR_LSB + 2BF20h] + 70088h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CURSOR_Y_POSITION_SIGN_BIT

CURSOR_X_POSITION_SIGN_BIT
RESERVED

CURSOR_Y_POSITION_MAGNITUDE_BITS_11

CURSOR_X_POSITION_MAGNITUDE_BITS_11
RESERVED_1

Bit Default &

Description
Range Access

CURSOR_Y_POSITION_SIGN_BIT: This bit provides the sign bit of a signed 13-bit

0b value that specifies the horizontal position of cursor. (default is 0). For normal high
31 resolution display modes, the cursor must have at least a single pixel positioned over
RW the active screen. For use as a VGA Popup, the entire cursor must be positioned over the
active area of the VGA image.

0b
30:28 RESERVED: Write as zero.
RW

CURSOR_Y_POSITION_MAGNITUDE_BITS_11: 0: This register provides the

magnitude bits of a signed 12-bit value that specifies the vertical position of cursor. The
sign bit of this value is provided by bit 31of this register. (default is 0). For use as a VGA
0b Popup, the entire cursor must be positioned over the active area of the VGA image.
27:16 Enabling the border in VGA (VGA Border Enable bit in the VGA Config register) includes
RW the border in what is considered the active area . For HDMI modes where the vertical
zoom is greater than 1x, the position is specified using the zoomed grid. When
performing 180 rotation, this field specifies the vertical position of the lower right corner
relative to the end of the active video area in the unrotated orientation.
CURSOR_X_POSITION_SIGN_BIT: This bit provides the sign bit of a signed 13-bit
value that specifies the horizontal position of cursor. (default is 0). ). For normal high
0b resolution display modes, the cursor must have at least a single pixel positioned over
15
RW the active screen. For use as a VGA Popup, the entire cursor must be positioned over the
active area of the VGA image. Enabling the border in VGA (VGA Border Enable bit in the
VGA Config register) includes the border in what is considered the active area .
0b
14:12 RESERVED_1: Write as zero.
RW
CURSOR_X_POSITION_MAGNITUDE_BITS_11: 0: These 12 bits provide the signed
13-bit value that specifies the horizontal position of cursor. The sign bit is provided by
0b bit 15 of this register. (default is 0) For HDMI modes where the horizontal zoom is
11:0
RW greater than 1x, the position is specified using the zoomed grid. When performing 180
rotation, this field specifies the horizontal position of the lower right corner relative to
the end of the active video area in the unrotated orientation.

Bay Trail-I SoC

718 Datasheet
Graphics, Video and Display

14.11.197 CURAPALET_0—Offset 70090h

Cursor A Palette registers (4 Registers)

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) CURAPALET_0: [GTTMMADR_LSB + 2BF20h] + 70090h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BLUE_OR_V_VALUE
RESERVED

RED_OR_Y_VALUE

GREEN_OR_U_VALUE
Bit Default &
Description
Range Access

0b
31:24 RESERVED: Write as zero.
RW
RED_OR_Y_VALUE: These registers specify the cursor palette. RGB data is full range
0b unsigned numbers. YUV data will be unsigned for the Y and excess 128 notation for the
23:16
RW UV values. The data can be pre-gamma corrected and bypass the gamma correction
logic or passed through the gamma corrector.
GREEN_OR_U_VALUE: These registers specify the cursor palette. RGB data is full
0b range unsigned numbers. YUV data will be unsigned for the U and excess 128 notation
15:8
RW for the YV values. The data can be pre-gamma corrected and bypass the gamma
correction logic or passed through the gamma corrector.

BLUE_OR_V_VALUE: These registers specify the cursor palette. RGB data is full range
0b unsigned numbers. YUV data will be unsigned for the V and excess 128 notation for the
7:0
RW YU values. The data can be pre-gamma corrected and bypass the gamma correction
logic or passed through the gamma corrector.

14.11.198 CURAPALET_1—Offset 70094h

Cursor A Palette registers (4 Registers)

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) CURAPALET_1: [GTTMMADR_LSB + 2BF20h] + 70094h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

Datasheet 719
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BLUE_OR_V_VALUE
RESERVED

RED_OR_Y_VALUE

GREEN_OR_U_VALUE
Bit Default &
Description
Range Access

0b
31:24 RESERVED: Write as zero.
RW

RED_OR_Y_VALUE: These registers specify the cursor palette. RGB data is full range
0b unsigned numbers. YUV data will be unsigned for the Y and excess 128 notation for the
23:16
RW UV values. The data can be pre-gamma corrected and bypass the gamma correction
logic or passed through the gamma corrector.
GREEN_OR_U_VALUE: These registers specify the cursor palette. RGB data is full
0b range unsigned numbers. YUV data will be unsigned for the U and excess 128 notation
15:8
RW for the YV values. The data can be pre-gamma corrected and bypass the gamma
correction logic or passed through the gamma corrector.
BLUE_OR_V_VALUE: These registers specify the cursor palette. RGB data is full range
0b unsigned numbers. YUV data will be unsigned for the V and excess 128 notation for the
7:0
RW YU values. The daa can be pre-gamma corrected and bypass the gamma correction logic
or passed through the gamma corrector.

14.11.199 CURAPALET_2—Offset 70098h

Cursor A Palette registers (4 Registers)

Access Method
Type: Memory Mapped I/O Register CURAPALET_2: [GTTMMADR_LSB + 2BF20h] + 70098h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BLUE_OR_V_VALUE
RESERVED

GREEN_OR_U_VALUE
RED_OR_Y_VALUE

Bit Default &

Description
Range Access

0b
31:24 RESERVED: Write as zero.
RW

Bay Trail-I SoC

720 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

RED_OR_Y_VALUE: These registers specify the cursor palette. RGB data is full range
0b unsigned numbers. YUV data will be unsigned for the Y and excess 128 notation for the
23:16
RW UV values. The data can be pre-gamma corrected and bypass the gamma correction
logic or passed through the gamma corrector.
GREEN_OR_U_VALUE: These registers specify the cursor palette. RGB data is full
0b range unsigned numbers. YUV data will be unsigned for the U and excess 128 notation
15:8
RW for the YV values. The data can be pre-gamma corrected and bypass the gamma
correction logic or passed through the gamma corrector.

BLUE_OR_V_VALUE: These registers specify the cursor palette. RGB data is full range
0b unsigned numbers. YUV data will be unsigned for the V and excess 128 notation for the
7:0
RW YU values. The data can be pre-gamma corrected and bypass the gamma correction
logic or passed through the gamma corrector.

14.11.200 CURAPALET_3—Offset 7009Ch

Cursor A Palette registers (4 Registers)

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) CURAPALET_3: [GTTMMADR_LSB + 2BF20h] + 7009Ch

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BLUE_OR_V_VALUE
RESERVED

RED_OR_Y_VALUE

GREEN_OR_U_VALUE

Bit Default &

Description
Range Access

0b
31:24 RESERVED: Write as zero.
RW
RED_OR_Y_VALUE: These registers specify the cursor palette. RGB data is full range
0b unsigned numbers. YUV data will be unsigned for the Y and excess 128 notation for the
23:16
RW UV values. The data can be pre-gamma corrected and bypass the gamma correction
logic or passed through the gamma corrector.

GREEN_OR_U_VALUE: These registers specify the cursor palette. RGB data is full
0b range unsigned numbers. YUV data will be unsigned for the U and excess 128 notation
15:8
RW for the YV values. The data can be pre-gamma corrected and bypass the gamma
correction logic or passed through the gamma corrector.
BLUE_OR_V_VALUE: These registers specify the cursor palette. RGB data is full range
0b unsigned numbers. YUV data will be unsigned for the V and excess 128 notation for the
7:0
RW YU values. The data can be pre-gamma corrected and bypass the gamma correction
logic or passed through the gamma corrector.

Bay Trail-I SoC

Datasheet 721
 Graphics, Video and Display

14.11.201 CURALIVEBASE—Offset 700ACh

Cursor A Live Base Address Register

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) CURALIVEBASE: [GTTMMADR_LSB + 2BF20h] + 700ACh

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CURSOR_A_LIVE_BASE_ADDRESS

RESERVED
DECRYPTION_REQUEST

POPUP_CURSOR_BASE_ADDRESS_MSBS
Bit Default &
Description
Range Access

0b CURSOR_A_LIVE_BASE_ADDRESS: This gives the live value of the surface base

31:6
RO address as being currently used for the plane.

0b
5 RESERVED: MBZ
RO
DECRYPTION_REQUEST: This bit requests decryption to be enabled for this plane.
This request will be qualified with the separate decryption allow message in order to
0b create the decryption enable. This bit is only allowed to change on a synchronous flip,
4 but once set with a synchronous flip, the bit can remain set while using asynchronous
RO flips. This value is loaded into the surface base address register of the associated plane.
Usage must conform to the rules outlined in the plane surface base address register. 0 =
Decryption request disabled (default) 1 = Decryption request enabled

0b POPUP_CURSOR_BASE_ADDRESS_MSBS: ([DevBW] and [DevCL] Only). This field

3:0 specifies bits 35:32 of the popup cursor physical address. If popup mode is not selected,
RO this field is ignored.

14.11.202 CURBCNTR—Offset 700C0h

Cursor B Control Register

Access Method

Bay Trail-I SoC

722 Datasheet
Graphics, Video and Display

Type: Memory Mapped I/O Register

CURBCNTR: [GTTMMADR_LSB + 2BF20h] + 700C0h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0
CURSOR_GAMMA_ENABLE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CURSOR_MODE_SELECT_BIT
RESERVED

PIPE_SELECT

CURSOR_MODE_SELECT
RESERVED_1

RESERVED_2

_180ROTATION

RESERVED_3

RESERVED_4
Bit Default &
Description
Range Access

0b
31:30 RESERVED: Write as zero.
RW
PIPE_SELECT: [DevBW, DevCL, DevCDV]: A state machine handles the
synchronization of the switch to both vertical blank signals. So as far as the software is
0b concerned, when both display pipes are being used, it can be switched at any time; the
29:28 hardware will synchronize the switch. 00 = HW cursor is attached to Display Pipe A. This
RW is the default after reset. 01 = HW cursor is attached to Display Pipe B. 10 = Reserved
for to Display Pipe C. 11 = Reserved for to Display Pipe D. Reserved [DevBLC] and
[DevCTG]: Write as zero.

0b
27 RESERVED_1: Write as zero.
RW

0b CURSOR_GAMMA_ENABLE: 0 = Cursor pixel data bypasses gamma correction

26
RW (default). 1 = Cursor pixel data is gamma to be corrected.

0b
25:16 RESERVED_2: Reserved.
RW
_180ROTATION: This mode causes the cursor to be rotated 180 . In addition to setting
0b this bit, software must also set the base address to the lower right corner of the
15 unrotated image. Only 32 bits per pixel cursors can be rotated. This field must be zero
RW when the cursor format is 2 bits per pixel. 0 = No rotation 1 = 180 Rotation of 32 bit per
pixel cursors

0b
14:6 RESERVED_3: Write as zero
RW

0b
5 CURSOR_MODE_SELECT_BIT: See following table.
RW

0b
4:3 RESERVED_4: reserved
RW

0b CURSOR_MODE_SELECT: These three bits together with bit 5 select the mode for
2:0
RW cursor as shown in the following table.

14.11.203 CURBBASE—Offset 700C4h

Cursor B Base Address Register

Bay Trail-I SoC

Datasheet 723
 Graphics, Video and Display

Access Method
Type: Memory Mapped I/O Register
CURBBASE: [GTTMMADR_LSB + 2BF20h] + 700C4h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

POPUP_CURSOR_BASE_ADDRESS_MSBS
CURSOR_BASE_ADDRESS

RESERVED
DECRYPTION_REQUEST_THIS_BIT_REQUESTS_DECRYPTION_TO_BE_ENABLED_FOR_THIS_PLANE

Bay Trail-I SoC

724 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

CURSOR_BASE_ADDRESS: This register specifies the graphics address of the entire

cursor. It also acts as a trigger event to force the update of active registers on the next
display event. The cursor surface address must be 4K byte aligned. The cursor must be
in linear memory, it cannot be tiled. When performing 180 rotation, this offset must be
the difference between the last pixel of the last line of the cursor data in its unrotated
orientation and the cursor surface address. A write to this register also acts as a trigger
event to force the update of active registers from the staging registers on the next
display event. Each cursor register is double-buffered. The CPU writes to a set of holding
0b registers. The active registers are updated from the holding registers following the
31:6 leading edge of the vertical blank pulse. The update is postponed until the next vblank if
RW a write cycle is active to any of the cursor registers at the time of the vblank. The
update is also postponed if a write sequence is in progress. It is assumed that if the
cursor mode is changed, the cursor image will also be changed. To prevent the cursor
from appearing when it is only partially programmed, the active registers will not be
updated until both the cursor control and base address registers have been
programmed. If the cursor control register is written, the cursor base address must also
be written before the change will be effective. However, the base address register may
be changed (e.g., to change the shape of the cursor) without also writing to the control
register. If both are to be written, the control register must be written first.

0b
5 RESERVED: MBZ
RW

DECRYPTION_REQUEST_THIS_BIT_REQUESTS_DECRYPTION_TO_BE_ENABLE
D_FOR_THIS_PLANE: This request will be qualified with the separate decryption allow
message in order to create the decryption enable. This bit is only allowed to change on
0b a synchronous flip, but once set with a synchronous flip, the bit can remain set while
4
RW using asynchronous flips. This value is loaded into the surface base address register of
the associated plane. Usage must conform to the rules outlined in the plane surface
base address register. 0 = Decryption request disabled (default) 1 = Decryption request
enabled

0b POPUP_CURSOR_BASE_ADDRESS_MSBS: ([DevBW] and [DevCL] Only). This field

3:0 specifies bits 35:32 of the popup cursor physical address. If popup mode is not selected,
RW this field is ignored.

14.11.204 CURBPOS—Offset 700C8h

Cursor B Position Register

Access Method
Type: Memory Mapped I/O Register CURBPOS: [GTTMMADR_LSB + 2BF20h] + 700C8h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

Datasheet 725
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CURSOR_X_POSITION_SIGN_BIT
CURSOR_Y_POSITION_SIGN_BIT

RESERVED

CURSOR_Y_POSITION_MAGNITUDE_BITS_11

RESERVED_1

CURSOR_X_POSITION_MAGNITUDE_BITS_11
Bit Default &
Description
Range Access

CURSOR_Y_POSITION_SIGN_BIT: This bit provides the sign bit of a signed 13-bit

0b value that specifies the horizontal position of cursor. (default is 0). ). For normal high
31
RW resolution display modes, the cursor must have at least a single pixel positioned over
the active screen.
0b
30:28 RESERVED: Write as zero.
RW
CURSOR_Y_POSITION_MAGNITUDE_BITS_11: 0: This register provides the
0b magnitude bits of a signed 13-bit value that specifies the vertical position of cursor. The
27:16 sign bit of this value is provided by bit 31of this register. (default is 0) When performing
RW 180 rotation, this field specifies the vertical position of the lower right corner relative to
the end of the active video area in the unrotated orientation.
CURSOR_X_POSITION_SIGN_BIT: This bit provides the sign bit of a signed 13-bit
0b value that specifies the horizontal position of cursor. (default is 0). ). For normal high
15 resolution display modes, the cursor must have at least a single pixel positioned over
RW the active screen. For HDMI modes where the vertical zoom is greater than 1x, the
position is specified using the zoomed grid.
0b
14:12 RESERVED_1: Write as zero.
RW
CURSOR_X_POSITION_MAGNITUDE_BITS_11: 0: These 12 bits provide the signed
13-bit value that specifies the horizontal position of cursor. The sign bit is provided by
0b bit 15 of this register. (default is 0) For HDMI modes where the horizontal zoom is
11:0
RW greater than 1x, the position is specified using the zoomed grid. When performing 180
rotation, this field specifies the vertical position of the lower right corner relative to the
end of the active video area in the unrotated orientation.

14.11.205 CURBPALET_0—Offset 700D0h

Cursor B Palette registers (4 Registers)

Access Method
Type: Memory Mapped I/O Register
CURBPALET_0: [GTTMMADR_LSB + 2BF20h] + 700D0h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Bay Trail-I SoC

726 Datasheet
Graphics, Video and Display

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BLUE_OR_V_VALUE
RESERVED

RED_OR_Y

GREEN_OR_U_VALUE
Bit Default &
Description
Range Access

0b
31:24 RESERVED: Write as zero.
RW

0b RED_OR_Y: RGB data is full range unsigned numbers. YUV data will be unsigned for
23:16 the Y and excess 128 notation for the UV values. The data can be pre-gamma corrected
RW and bypass the gamma correction logic or passed through the gamma corrector.

GREEN_OR_U_VALUE: RGB data is full range unsigned numbers. YUV data will be
0b unsigned for the U and excess 128 notation for the YV values. The data can be pre-
15:8
RW gamma corrected and bypass the gamma correction logic or passed through the gamma
corrector.
BLUE_OR_V_VALUE: RGB data is full range unsigned numbers. YUV data will be
0b unsigned for the V and excess 128 notation for the YU values. The data can be pre-
7:0
RW gamma corrected and bypass the gamma correction logic or passed through the gamma
corrector.

14.11.206 CURBPALET_1—Offset 700D4h

Cursor B Palette registers (4 Registers)

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) CURBPALET_1: [GTTMMADR_LSB + 2BF20h] + 700D4h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BLUE_OR_V_VALUE
RESERVED

RED_OR_Y

GREEN_OR_U_VALUE

Bit Default &

Description
Range Access

0b
31:24 RESERVED: Write as zero.
RW

Bay Trail-I SoC

Datasheet 727
 Graphics, Video and Display

Bit Default &

Description
Range Access

0b RED_OR_Y: RGB data is full range unsigned numbers. YUV data will be unsigned for
23:16 the Y and excess 128 notation for the UV values. The data can be pre-gamma corrected
RW and bypass the gamma correction logic or passed through the gamma corrector.
GREEN_OR_U_VALUE: RGB data is full range unsigned numbers. YUV data will be
0b unsigned for the U and excess 128 notation for the YV values. The data can be pre-
15:8
RW gamma corrected and bypass the gamma correction logic or passed through the gamma
corrector.
BLUE_OR_V_VALUE: RGB data is full range unsigned numbers. YUV data will be
0b unsigned for the V and excess 128 notation for the YU values. The data can be pre-
7:0
RW gamma corrected and bypass the gamma correction logic or passed through the gamma
corrector.

14.11.207 CURBPALET_2—Offset 700D8h

Cursor B Palette registers (4 Registers)

Access Method
Type: Memory Mapped I/O Register
CURBPALET_2: [GTTMMADR_LSB + 2BF20h] + 700D8h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GREEN_OR_U_VALUE
RESERVED

BLUE_OR_V_VALUE
RED_OR_Y

Bit Default &

Description
Range Access

0b
31:24 RESERVED: Write as zero.
RW

0b RED_OR_Y: RGB data is full range unsigned numbers. YUV data will be unsigned for
23:16 the Y and excess 128 notation for the UV values. The data can be pre-gamma corrected
RW and bypass the gamma correction logic or passed through the gamma corrector.
GREEN_OR_U_VALUE: RGB data is full range unsigned numbers. YUV data will be
0b unsigned for the U and excess 128 notation for the YV values. The data can be pre-
15:8
RW gamma corrected and bypass the gamma correction logic or passed through the gamma
corrector.
BLUE_OR_V_VALUE: RGB data is full range unsigned numbers. YUV data will be
0b unsigned for the V and excess 128 notation for the YU values. The data can be pre-
7:0
RW gamma corrected and bypass the gamma correction logic or passed through the gamma
corrector.

14.11.208 CURBPALET_3—Offset 700DCh

Cursor B Palette registers (4 Registers)

Bay Trail-I SoC

728 Datasheet
Graphics, Video and Display

Access Method
Type: Memory Mapped I/O Register
CURBPALET_3: [GTTMMADR_LSB + 2BF20h] + 700DCh
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BLUE_OR_V_VALUE
RESERVED

RED_OR_Y

GREEN_OR_U_VALUE
Bit Default &
Description
Range Access

0b
31:24 RESERVED: Write as zero.
RW

0b RED_OR_Y: RGB data is full range unsigned numbers. YUV data will be unsigned for
23:16 the Y and excess 128 notation for the UV values. The data can be pre-gamma corrected
RW and bypass the gamma correction logic or passed through the gamma corrector.
GREEN_OR_U_VALUE: RGB data is full range unsigned numbers. YUV data will be
0b unsigned for the U and excess 128 notation for the YU values. The data can be pre-
15:8
RW gamma corrected and bypass the gamma correction logic or passed through the gamma
corrector.

BLUE_OR_V_VALUE: RGB data is full range unsigned numbers. YUV data will be
0b unsigned for the V and excess 128 notation for the YU values. The data can be pre-
7:0
RW gamma corrected and bypass the gamma correction logic or passed through the gamma
corrector.

14.11.209 CURBLIVEBASE—Offset 700ECh

Cursor B Live Base Address Register

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) CURBLIVEBASE: [GTTMMADR_LSB + 2BF20h] + 700ECh

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

Datasheet 729
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DECRYPTION_REQUEST_THIS_BIT_REQUESTS_DECRYPTION_TO_BE_ENABLED_FOR_THIS_PLANE

POPUP_CURSOR_BASE_ADDRESS_MSBS
RESERVED
CURSOR_B_LIVE_BASE_ADDRESS

Bit Default &

Description
Range Access

0b CURSOR_B_LIVE_BASE_ADDRESS: This gives the live value of the surface base

31:6
RO address as being currently used for Cursor B plane.

0b
5 RESERVED: MBZ
RO
DECRYPTION_REQUEST_THIS_BIT_REQUESTS_DECRYPTION_TO_BE_ENABLE
D_FOR_THIS_PLANE: This request will be qualified with the separate decryption allow
message in order to create the decryption enable. This bit is only allowed to change on
0b a synchronous flip, but once set with a synchronous flip, the bit can remain set while
4
RO using asynchronous flips. This value is loaded into the surface base address register of
the associated plane. Usage must conform to the rules outlined in the plane surface
base address register. 0 = Decryption request disabled (default) 1 = Decryption request
enabled

0b POPUP_CURSOR_BASE_ADDRESS_MSBS: ([DevBW] and [DevCL] Only). This field

3:0 specifies bits 35:32 of the popup cursor physical address. If popup mode is not selected,
RO this field is ignored.

Bay Trail-I SoC

730 Datasheet
Graphics, Video and Display

14.11.210 DSPAADDR—Offset 7017Ch

Display A Async flip Start Address Register

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) DSPAADDR: [GTTMMADR_LSB + 2BF20h] + 7017Ch

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DISPLAY_A_START_ADDRESS_BITS

RESERVED_1
RESERVED

FLIP_SOURCE
DECRYPTION_REQUEST
Bit Default &
Description
Range Access

DISPLAY_A_START_ADDRESS_BITS: This register provides the start address of the

display A plane or the first eye when running in stereo mode. This address must be at
least pixel aligned. This register can be written directly through software or by
command packets in the command stream. It represents an offset from the graphics
memory aperture base and is mapped to physical pages through the global GTT. This
0b address must be 4K aligned. When performing asynchronous flips and the display
31:12 surface is in tiled memory, this address must be 256K aligned. This register can be
RW written directly through software or by command packets in the command stream. It
represents an offset from the graphics memory aperture base and is mapped to physical
pages through the global GTT. If the device supports trusted operation and this plane is
not marked trusted, the memory pages must not be marked NoDMA . Write to this
register triggers async flip. The async flip address is written into the Display A Base
Address register 0x7019C

0b
11:4 RESERVED: MBZ
RW

0b FLIP_SOURCE: Project: All Default Value: 0b This bit indicates if the source of the flip
3 is CS or BCS so display can send the flip done response to the appropriate destination.
RW ValueNameDescriptionProject 0b CS Flip source is CS All 1b BCS Flip source is BCS All

DECRYPTION_REQUEST: Project: All Default Value: 0b This bit requests decryption to

be enabled for this plane. This request will be qualified with the separate decryption
0b allow message in order to create the decryption enable. This bit is only allowed to
2 change on a synchronous flip, but once set with a synchronous flip, the bit can remain
RW set while using asynchronous flips. This value is loaded into the surface base address
register of the associated plane. Usage must conform to the rules outlined in the plane
surface base address register.
0b
1:0 RESERVED_1: MBZ
RW

Bay Trail-I SoC

Datasheet 731
 Graphics, Video and Display

14.11.211 DSPACNTR—Offset 70180h

Display A Plane Control Register

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) DSPACNTR: [GTTMMADR_LSB + 2BF20h] + 70180h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

S3D_FORCE_DISPLAY_A_BOTTOM
DISPLAY_PLANE_A_PRIMARY_A_ENABLE

_180DISPLAY_ROTATION
DISPLAY_A_GAMMA_ENABLE

DISPLAY_A_SOURCE_PIXEL_FORMAT

PIPE_SELECT

KEY_WINDOW_ENABLE

RESERVED_1

RESERVED_2

RESERVED_3
RESERVED_4

RESERVED_5

TILED_SURFACE
RESERVED_6

RESERVED_7
KEY_ENABLE

PIXEL_MULTIPLY

RESERVED

Bit Default &

Description
Range Access

DISPLAY_PLANE_A_PRIMARY_A_ENABLE: When this bit is set, the primary plane

will generate pixels for display. When set to zero, display plane A memory fetches cease
0b and display is blanked (from this plane) at the next VBLANK event from the pipe that
31
RW display A is assigned. The display pipe must be enabled to enable this plane. There is an
override for the enable of this plane in the Pipe Configuration register. 1 = Enable 0 =
Disable

DISPLAY_A_GAMMA_ENABLE: This bit should only be changed after the plane has
0b been disabled. It controls the bypassing of the display pipe gamma unit for this display
30 plane s pixel data only. For 8-bit indexed display data, this bit should be set to a one. 0
RW = Display A pixel data bypasses the display pipe gamma correction logic (default). 1 =
Display A pixel data is gamma corrected in the display pipe gamma correction logic.
DISPLAY_A_SOURCE_PIXEL_FORMAT: These bits should only be changed after the
plane has been disabled. Pixel formats with an alpha channel (8:8:8:8) should not use
source keying. Pixel format of 8-bit indexed uses the palette. Before entering the
blender, each source format is converted to 10 bits per pixel (details are described in the
intermediate precision for the blender section of the Display Functions chapter). 000x =
Reserved. 0010 = 8-bpp Indexed. 0011 = Reserved. 0100 = Reserved. 0101 = 16-bit
BGRX (5:6:5:0) pixel format (XGA compatible). 0110 = 32-bit BGRX (8:8:8:8) pixel
0b format. Ignore alpha. 0111 = 32-bit BGRA (8:8:8:8) pixel format. (with pre-multiplied
29:26
RW alpha color format) 1000 = 32-bit RGBX (10:10:10:2) pixel format. Ignore alpha. 1001
= 32-bit RGBA (10:10:10:2) pixel format. (with pre-multiplied alpha color format) 1010
= 32-bit BGRX (10:10:10:2) pixel format Ignore alpha 1011 = 32-bit BGRA
(10:10:10:2) pixel format (with pre-multiplied alpha color format) 1100 = 64-bit RGBX
(16:16:16:16) 16 bit floating point pixel format. Ignore alpha. 1101 = 64-bit RGBA
(16:16:16:16) 16-bit floating point pixel format (with pre-multiplied color format) 1110
= 32-bit RGBX (8:8:8:8) pixel format. Ignore alpha. 1111 = 32-bit RGBA (8:8:8:8)
pixel format (with pre-multiplied color format)

Bay Trail-I SoC

732 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

0b
25:24 PIPE_SELECT: Plane A always ties to Pipe A. AccessType: Read Only Reserved
RO
KEY_WINDOW_ENABLE: . This bit applies only to devices with a display plane C. This
bit is set to one when the color key is used as a destination key for display C. Display
0b plane C must be enabled on the same pipe and it s Z-order should be programmed to be
23
RW behind display A for this to be set to a one.0 = Source Key applies to entire display
plane A 1 = Source Key applies to only pixels within the intersection between Display A
and Display C [DevBLC] and [DevCTG]: Reserved
KEY_ENABLE: . This bit enables source keying for display A. Source keying allows a
plane that is behind (below) this plane to show through where the display A key
matches the display A data. This function is overloaded to provide display C destination
0b keying when combined with the key window enable bit. Setting this bit is not allowed
22
RW when the display pixel format includes an alpha channel.0 = Source key is disabled 1 =
Source key is enabled [DevBLC] and [DevCTG]: Reserved In destination keying, primary
plane pixel will be made transparent when blending with sprite pixel as the destination if
the primary src key matches with the primary pixel value.

PIXEL_MULTIPLY: This cause the display plane to duplicate lines and pixels sent to
0b the assigned pipe. In the pixel multiply mode, the horizontal pixels are doubled and
21:20 lines are sent twice. Asynchronous flips are not used in this mode. Programming Notes:
RW Asynchronous flips are not permitted when pixel multiply is enabled. 00 = No
duplication 01 = Line/pixel Doubling 10 = Reserved 11 = Pixel Doubling only
0b
19 RESERVED: Software must preserve the contents of this bit.
RW
0b
18 RESERVED_1: Write as zero
RW
0b
17:16 RESERVED_2: Software must preserve the contents of this bit.
RW
_180DISPLAY_ROTATION: This mode causes the display plane to be rotated 180 . In
0b addition to setting this bit, software must also set the base address to the lower right
15
RW corner of the unrotated image. [DevCL] Do not enable 180 rotation together with Frame
Buffer Compression0 = No rotation 1 = 180 rotation

RESERVED_3: [DevBW, DevCL, DevCDV]: [DevBLC] and [DevCTG] Display A Trickle

0b Feed Enable: 0 = Trickle Feed Enabled - Display A data requests are sent whenever
14 there is space in the Display Data Buffer. 1 = Trickle Feed Disabled - Display A data
RW requests are sent in bursts. Note: On mobile products this bit will be ignored such that
Trickle Feed is always disabled. [DevELK] Must always be programmed disabled

RESERVED_4: [DevBW, DevCL, DevCDV]: [DevBLC] and [DevCTG] Display A Data

0b Buffer Partitioning Control: 0 = Display A Data Buffer will encompass Sprite A buffer
13 space when Sprite A is disabled. 1 = Display A Data Buffer will not use Sprite A buffer
RW space when Sprite A is disabled. Note: When in C3xR Max FIFO mode, this bit will be
ignored.
0b
12:11 RESERVED_5: Reserved.
RW
TILED_SURFACE: . This bit indicates that the display A surface data is in tiled memory.
0b The tile pitch is specified in bytes in the DSPASTRIDE register. Only X tiling is supported
10 for display surfaces.When this bit is set, it affects the hardware interpretation of the
RW DSPATILEOFF, DSPALINOFF, and DSPASURF registers. 0 = Display A surface uses linear
memory 1 = Display A surface uses X-tiled memory
RESERVED_6: [DevBW, DevCL, DevCDV] Write as zero [DevBLC, DevCTG]
Asynchronous Surface Address Update Enable: This bit will enable asynchronous
updates of the surface address when written by MMIO. The surface address will change
with the next TLB request or when start of vertical blank is reached. Updates during
0b vertical blank may not complete until after the first few active lines are displayed.
9
RW Restrictions: No command streamer initiated surface address updates are allowed when
this bit is enabled. Only one asynchronous update may be made per frame. Must wait
for vertical blank before again writing the surface address register. 0 = DSPASURF MMIO
writes will update synchronous to start of vertical blank (default) 1 = DSPASURF MMIO
writes will update asynchronously

Bay Trail-I SoC

Datasheet 733
 Graphics, Video and Display

Bit Default &

Description
Range Access

0b
8:1 RESERVED_7: Write as zero
RW
S3D_FORCE_DISPLAY_A_BOTTOM: This bit will force the display A plane to be on
0b the bottom of any sprite planes in the Z order. 0 = Display A Z-order is determined by
0
RW the other control bits in pipe A 1 = Display A is forced to be on the bottom of any sprite
planes in Z-order in pipe A

14.11.212 DSPALINOFF—Offset 70184h

Display A Linear Offset Register

Access Method
Type: Memory Mapped I/O Register DSPALINOFF: [GTTMMADR_LSB + 2BF20h] + 70184h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DISPLAY_A_OFFSET

Bit Default &

Description
Range Access

DISPLAY_A_OFFSET: This register provides the panning offset into the display A
plane. This value is added to the surface address to get the graphics address of the first
0b pixel to be displayed. This offset must be at least pixel aligned. This offset is the
31:0 difference between the address of the upper left pixel to be displayed and the display
RW surface address. When performing 180 rotation, this offset must be the difference
between the last pixel of the last line of the display data in its unrotated orientation and
the display surface address.

14.11.213 DSPASTRIDE—Offset 70188h

Display A Stride Register

Access Method
Type: Memory Mapped I/O Register DSPASTRIDE: [GTTMMADR_LSB + 2BF20h] + 70188h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

734 Datasheet
Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DISPLAY_A_STRIDE

RSVD0
Bit Default &
Description
Range Access

DISPLAY_A_STRIDE: This is the stride for display A in bytes. When using linear
memory, this must be 64 byte aligned. When using tiled memory, this must be 512 byte
aligned. This value is used to determine the line to line increment for the display. This
register is updated either through a command packet passed through the command
stream or writes to this register. When it is desired to update both this and the start
0b register, the stride register must be written first because the write to the start register is
31:6
RW the trigger that causes the update of both registers on the next VBLANK event. When
using tiled memory, the actual memory buffer stride is limited to a maximum of 16K
bytes. [DevBW, DevCL, DevCDV] The display stride must be power of 2 when doing
Asynch Flips. [DevBW, DevCL, DevCDV] The display stride must be 8KB or greater when
doing Asynch Flips together with 180 rotation. The value in this register is updated
through the command streamer during a synchronous flip.
0b
5:0 RSVD0: Reserved
RO

14.11.214 DSPAKEYVAL—Offset 70194h

Sprite Color Key Value Register

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) DSPAKEYVAL: [GTTMMADR_LSB + 2BF20h] + 70194h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RED_KEY_VALUE
RESERVED

GREEN_KEY_VALUE

BLUE_KEY_VALUE

Bit Default &

Description
Range Access

0b
31:24 RESERVED: Reserved.
RW
0b
23:16 RED_KEY_VALUE: Specifies the color key value for the sprite red/Cr channel.
RW

Bay Trail-I SoC

Datasheet 735
 Graphics, Video and Display

Bit Default &

Description
Range Access

0b
15:8 GREEN_KEY_VALUE: Specifies the color key value for the sprite green/Y channel.
RW
0b
7:0 BLUE_KEY_VALUE: Specifies the color key value for the sprite blue/Cb channel.
RW

14.11.215 DSPAKEYMSK—Offset 70198h

Sprite Color Key Mask Register

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) DSPAKEYMSK: [GTTMMADR_LSB + 2BF20h] + 70198h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GREEN_MASK_VALUE

BLUE_MASK_VALUE
RESERVED

RED_MASK_VALUE

Bit Default &

Description
Range Access

0b
31:24 RESERVED: reserved
RW
0b
23:16 RED_MASK_VALUE: Specifies the color key mask for the sprite red/Cr channel.
RW
0b
15:8 GREEN_MASK_VALUE: Specifies the color key mask for the sprite green/Y channel.
RW
0b
7:0 BLUE_MASK_VALUE: Specifies the color key mask for the sprite blue/Cb channel.
RW

14.11.216 DSPASURF—Offset 7019Ch

Display A Surface Base Address Register

Access Method
Type: Memory Mapped I/O Register
DSPASURF: [GTTMMADR_LSB + 2BF20h] + 7019Ch
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

736 Datasheet
Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DECRYPTION_REQUEST
DISPLAY_A_SURFACE_BASE_ADDRESS

RESERVED

FLIP_SOURCE

RESERVED_1
Bit Default &
Description
Range Access

DISPLAY_A_SURFACE_BASE_ADDRESS: . This address specifies the surface base

address. When the surface is tiled, panning is specified using (x, y) offsets in the
DSPATILEOFF register. When the surface is in linear memory, panning is specified using
0b a linear offset in the DSPALINOFF register.This address must be 4K aligned. When
31:12 performing asynchronous flips and the display surface is in tiled memory, this address
RW must be 256K aligned. This register can be written directly through software or by
command packets in the command stream. It represents an offset from the graphics
memory aperture base and is mapped to physical pages through the global GTT.
[DevBW] and [DevCL]: This address must be 128K aligned for linear memory.

0b
11:4 RESERVED: Reserved.
RW

0b FLIP_SOURCE: Project: All Default Value: 0b This bit indicates if the source of the flip
3 is CS or BCS so display can send the flip done response to the appropriate destination.
RW ValueNameDescriptionProject 0b CS Flip source is CS All 1b BCS Flip source is BCS All

DECRYPTION_REQUEST: Project: All Default Value: 0b This bit requests decryption to

be enabled for this plane. This request will be qualified with the separate decryption
0b allow message in order to create the decryption enable. This bit is only allowed to
2 change on a synchronous flip, but once set with a synchronous flip, the bit can remain
RW set while using asynchronous flips. This value is loaded into the surface base address
register of the associated plane. Usage must conform to the rules outlined in the plane
surface base address register.
0b
1:0 RESERVED_1: MBZ
RW

14.11.217 DSPATILEOFF—Offset 701A4h

Display A Tiled Offset Register

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) DSPATILEOFF: [GTTMMADR_LSB + 2BF20h] + 701A4h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

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Datasheet 737
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PLANE_START_Y_POSITION
RESERVED

PLANE_START_X_POSITION
RESERVED_1
Bit Default &
Description
Range Access

0b
31:28 RESERVED: Write as zero
RW
PLANE_START_Y_POSITION: These 12 bits specify the vertical position in lines of the
0b beginning of the active display plane relative to the display surface. When performing
27:16
RW 180 rotation, this field specifies the vertical position of the lower right corner relative to
the start of the active display plane in the unrotated orientation.
0b
15:12 RESERVED_1: Write as zero
RW
PLANE_START_X_POSITION: These 12 bits specify the horizontal offset in pixels of
the beginning of the active display plane relative to the display surface. When
0b performing 180 rotation, this field specifies the horizontal position of the lower right
11:0
RW corner relative to the start of the active display plane in the unrotated orientation.
[DevBW, DevCL, DevCDV] When display stride is 16KB and doing Asynch Flips, do not
program the offset to give pans of 7680 to 8191 bytes.

14.11.218 DSPASURFLIVE—Offset 701ACh

Display A Live Surface Base Address Register [DevCTG-B, DevCDV]

Access Method
Type: Memory Mapped I/O Register DSPASURFLIVE: [GTTMMADR_LSB + 2BF20h] + 701ACh
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

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738 Datasheet
Datasheet
Bay Trail-I SoC
0
0

31
31

PND_DEADLINE_CALCULATION_DISABLE

0
0

S0IX_PWM_BACKLIGHT_CLOCK_MUX_SELECT

Bit
Range

0
0

GM_DEGLITCH_EMUL_MODE

31:0

0
0

28
28

(Size: 32 bits)

0
0

VGA_OOO_QUEUE_DEPTH
Graphics, Video and Display

0b
RO

0
0

Access Method
Access
Default &

0
0

HPD_PORT_D_49_95MS_TIME_FLAG_BYPASS

Chicken Bit Register

0
0

Default: 00000000h
24
24

HPD_PORT_C_49_95MS_TIME_FLAG_BYPASS

0
0

HPD_PORT_B_49_95MS_TIME_FLAG_BYPASS

0
0

RESERVED

Type: Memory Mapped I/O Register

14.11.219 CBR1—Offset 70400h

0
0

ELPIN_409_SELECT

0
0

20
20

HPD_INPUT_ENABLE

0
0

CR12_WRITE_COUNTER_RESET

0
0

RESERVED_2

bits)

0
0

MONITOR_DETECTION

0
0

16
16

INVERT_DPO_FIELD
DISPLAY_A_LIVE_SURFACE_BASE_ADDRESS

0
0

RESERVED_3

0
0

HPD_TEST_MODE

0
0

SDVOC_SELECT

0
0

12
12

SDVOB_SELECT

0
0

VGA_STALL
Description

0
0

RESERVED_4

0
0

PIXEL_SIZE

8
8

0
0

IMMEDIATE_ASYNCHRONOUS_FLIPS
surface base address as being currently used for the plane.

0
0

PIPE_B_FRAME_START_POSITION

0
0

PIPE_B_PALETTE_WRITE_ENABLE
CBR1: [GTTMMADR_LSB + 2BF20h] + 70400h

0
0

PIPE_A_PALETTE_WRITE_ENABLE

4
4

0
0

VRD_FONT_FIFO_REQUEST_DELAY_ENABLE
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

0
0

PIPE_A_FRAME_START_POSITION

0
0

RESERVED_6
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

0
0

DISPLAY_A_LIVE_SURFACE_BASE_ADDRESS: . This gives the live value of the

PLLB_SAFE_SHUTDOWN_OVERRIDE
0
0

0
0

PLLA_SAFE_SHUTDOWN_OVERRIDE

739
 Graphics, Video and Display

Bit Default &

Description
Range Access

PND_DEADLINE_CALCULATION_DISABLE: 1 = PND deadline scheme is disabled.

0b Latency deadline calculation is based on the pre-programmed watermark level and the
31
RW 2-bit FIFO status region. 0 = PND deadline scheme is enabled. Latency deadline
calculation is based on actual FIFO level

S0IX_PWM_BACKLIGHT_CLOCK_MUX_SELECT: This bit is used to select the new

0b pwm backlight control during s0ix mode 0 = select s0ix pwm backlight control based on
30 25 MHz oscillator clock (default) 1 = select normal pwm backlight control based on
RW hrawclk Programming note: This bit is programmed to select either 200MHz refclk from
CCK or 25MHz refclk from XTAL. This bit cannot be changed on the fly.
0b
29 GM_DEGLITCH_EMUL_MODE: GM deglitch emulation mode
RW
VGA_OOO_QUEUE_DEPTH: 0xx = Disable out-of-order stall logic for VGA 100 =
0b Enable out-of-order VGA stall depth of 64 101 = Enable out-of-order VGA stall depth of
28:26
RW 48 110 = Enable out-of-order VGA stall depth of 32 111 = Enable out-of-order VGA stall
depth of 16

0b HPD_PORT_D_49_95MS_TIME_FLAG_BYPASS: bypass 49_95ms time flag in Port

25
RW D Not Used

HPD_PORT_C_49_95MS_TIME_FLAG_BYPASS: bypass 49_95ms time flag in Port C

0b Programming note: VLV uses HPD deglitch time as 50us. For glitches between 50us and
24
RW 250us during hot plug event, driver may see multiple hpd interrupts, driver shall either
service them or ignore them.
HPD_PORT_B_49_95MS_TIME_FLAG_BYPASS: bypass 49_95ms time flag in Port B
0b Programming note: VLV uses HPD deglitch time as 50us. For glitches between 50us and
23
RW 250us during hot plug event, driver may see multiple hpd interrupts, driver shall either
service them or ignore them.
0b
22 RESERVED: Reserved.
RW
0b ELPIN_409_SELECT: This bit is used to select one of the elpin 409 bug fixes 0 =
21
RW vrd_ci_rreq 1 = count comparator

HPD_INPUT_PIN_DISABLE (HPD_INPUT_ENABLE): [DevVLVP]: this bit is used to

0b disable HPD detection in the Display core from using HPD input pin pin 0 = HPD Input
20
RW pin is enabled to detect HPD detection by Display core (default) 1 = HPD input is pin is
disabled to detect HPD detection by Display core

0b CR12_WRITE_COUNTER_RESET: 0 = Disable CR12 write counter reset 1 = Enable

19
RW CR12 write counter reset

0b
18 RESERVED_2: Reserved.
RW
0b MONITOR_DETECTION: This bit is used to test the monitor detection. Do not program
17
RW unless directed.

0b INVERT_DPO_FIELD: Invert DPO interlaced field output. This bit is used to invert the
16
RW field sense input to the planes from DPO.

0b
15 RESERVED_3: Reserved.
RW
0b HPD_TEST_MODE: load programmable value for filter and long pulse value of HPD
14
RW register 0x70408.

0b
13 SDVOC_SELECT: sdvoc deglitch logic output select
RW
0b
12 SDVOB_SELECT: sdvob deglitch logic output select
RW
0b VGA_STALL: Stall native mode VGA when frequency is over 50 MHz. This bit is only
11
RW used during VGA native mode.

Bay Trail-I SoC

740 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

0b
10 RESERVED_4: to prevent async flip failures.
RW
0b
9 PIXEL_SIZE: This bit changes the VGA pixel width and height calculations.
RW
IMMEDIATE_ASYNCHRONOUS_FLIPS: This bit causes asynchronous flips to
0b complete immediately upon the start of the vertical blank period. When enabling this
8
RW feature, frame start should also be moved to the end of the vertical blank period by
setting the frame start position bit.
PIPE_B_FRAME_START_POSITION: This bit changes the position of frame start on
0b pipe B. This feature is used in conjunction with the immediate asynchronous flips bit to
7 enable fast asynchronous flips during vertical blanking. 0 = frame start occurs at start of
RW the vertical blank period 1 = frame start occurs at end of the vertical blank period
Default: 1, causing frame start to occur at the end of vertical blank
0b PIPE_B_PALETTE_WRITE_ENABLE: Disables anti-collision logic in the palette during
6
RW non-blanking periods on pipe B.

0b PIPE_A_PALETTE_WRITE_ENABLE: Disables anti-collision logic in the palette during

5
RW non-blanking periods on pipe A

0b VRD_FONT_FIFO_REQUEST_DELAY_ENABLE: This bit enable VRD font read request

4
RW delay in VGA mode

PIPE_A_FRAME_START_POSITION: This bit changes the position of frame start on

0b pipe A. This feature is used in conjunction with the immediate asynchronous flips bit to
3 enable fast asynchronous flips during vertical blanking. 0 = frame start occurs at start of
RW the vertical blank period 1 = frame start occurs at end of the vertical blank period
Default: 1, causing frame start to occur at the end of vertical blank

0b
2 RESERVED_6: Reserved.
RW

0b PLLB_SAFE_SHUTDOWN_OVERRIDE: This bit disables the dependency for pipe B to

1
RW be disabled before the PLL is shut down

0b PLLA_SAFE_SHUTDOWN_OVERRIDE: This bit disables the dependency for pipe A to

0
RW be disabled before the PLL is shut down

14.11.220 CBR2—Offset 70404h

Chicken2 Bit Register

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) CBR2: [GTTMMADR_LSB + 2BF20h] + 70404h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

Datasheet 741
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DPSEL_OVERRIDE

DPRAUDM_EARLY_HDE_DISABLE

DPRDDB_SYNC_SELECT

DPRVGA_DPBSTALL_UL_THRESHOLD

DPRAUDM_SAMPLE_PRESENT_DISABLE
DPRDDB_VGAENRST_DIS

DPIOMB0UNIT

MMIO_WRITE_EVENT
DBLATEN_ARMED_CURA_B

DDBMUNIT
HDCPUNIT
RESERVED

EDGE

HPD_INTR_FIX

PORT_B_LANES_READY_IGNORE
PORT_C_LANES_READY_IGNORE
DPLLS_OK_IGNORE
DPR_DPS_NOA_SCALEEN
DITHERING_ENHANCE_DISABLE

DPLRUNIT
DPRAUDM_CKGATE_PKTCNTRL_IDLE_DIS

DPR_VS_AFLIPTOTAL_CHICKEN
DCN_447625

DPR_DPIO_PORTOFF_NOT_HBLK_CHICKEN

DPR_VS_BYTEEN_CHICKEN
DPR_VS_AFLIPADDR_CHICKEN
RESERVED_1

RESERVED_2
Bit Default &
Description
Range Access

0b DPRDDB_VGAENRST_DIS: Enable rise and fall detection of DPRvgadis for DDB reset
31
RW (dprddb_vgaenrst_dis)

0b
30:28 RESERVED: Reserved.
RW
0b
27 DCN_447625: : - x8 support for hybrid gfx, Kwasi requested (dpr_dpio_x8_conc_sel)
RW
0b DPIOMB0UNIT: ignoring EDP logic when enabling Lanes by the dptc_otxoenb
26
RW [DevVLVP]: Reserved

0b DPSEL_OVERRIDE: when this chicken bit is set override the selects to 0

25
RW (dpsel_override) timeslice_sync_rst_b = DPRVGAdis | mrchicken2_Q[25]

0b DITHERING_ENHANCE_DISABLE: Anh need for dithering enhace

24
RW (dithering_enhance_disable)

0b
23 EDGE: edgeA/Bvblank, edgeDPSA/Bvblank, curA/Bedgevblank,
RW
0b DPRAUDM_EARLY_HDE_DISABLE: Chicken bit to Audio unit to disable early RAM
22
RW FIFO read in 2-channel mode (DPRAUDM_early_hde_disable)

0b DPLRUNIT: Selects cdclk for pwm logic, pwm logic, uses hrawclk by default (select
21
RW cdclk in scan mode or by setting a chicken bit) [DevVLVP]: Reserved

0b DPRAUDM_CKGATE_PKTCNTRL_IDLE_DIS: Chicken bit to disable audclk gating

20
RW when pktcontrol FSM is idle (DPRAUDM_ckgate_pktcntrl_idle_dis)

DPR_DPIO_PORTOFF_NOT_HBLK_CHICKEN: This bit is needed to qualify the port

0b off with hblank to take care of fragmented audio packet sent off. When chicken bit is
19
RW enabled, the port off is dependent upon state of hblank, else the legacy behavior rules
(dpr_dpio_portoff_not_hblk_chicken)

0b MMIO_WRITE_EVENT: 0: mmio_write_event = RMDecPipeSLC_pre 1:

18
RW mmio_write_event = 1'b0

0b
17 DBLATEN_ARMED_CURA_B: Dblaten_armed_curA/B
RW

0b
16 HPD_INTR_FIX: Freeses hpdb_intr_fix, hpdc_intr_fix, hpdd_intr_fix
RW

Bay Trail-I SoC

742 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

0b
15 RESERVED_1: Reserved.
RW

0b PORT_B_LANES_READY_IGNORE: 1: Lanes considered as ready for normal

14 operation 0: usual operation: Lanes readiness indications arrived from DPIO SEG
RW outputs [DevVLVP]: Reserved

0b PORT_C_LANES_READY_IGNORE: 1: Lanes considered as ready for normal

13 operation 0: usual operation: Lanes readiness indications arrived from DPIO SEG
RW outputs [DevVLVP]: Reserved

0b DPLLS_OK_IGNORE: 1: Both mPHY DPLLs considered as OK ('1'). Lanes can be

12 enabled. 0: usual operation: DPLL readiness indications arrived from DPIO SEG outputs
RW [DevVLVP]: Reserved
DPR_DPS_NOA_SCALEEN: This bit is to enable viewing critical control signals that
0b were added as a result of Cantiga B0 Overlay changes. Default = 0.
11
RW (dpr_dps_noa_scaleen) 0: Non-scaling signals are sent to NOA bus 1: Scaling signals
are sent to the NOA bus

0b DPR_VS_AFLIPTOTAL_CHICKEN: This chicken bit bypasses the current logic used for
10 calculating the number of requests to make for an asynchronous flip. It will be helpful
RW because the current logic is very difficult to validate. (dpr_vs_afliptotal_chicken)
DPR_VS_BYTEEN_CHICKEN: This chicken bit bypasses the current logic used for
0b selecting the proper byte enables. It is intended to address byte enables during
9
RW asynchronous flips, but it was easier to bypass the entire byte-enable circuit instead.
HSD bug #1932963. (dpr_vs_byteen_chicken)

0b DPR_VS_AFLIPADDR_CHICKEN: This chicken bit bypasses the current logic used for
8 selecting the starting fetch address of an asynchronous flip. HSD bug #1932964.
RW (dpr_vs_aflipaddr_chicken)

DPRDDB_SYNC_SELECT: When set vsync reset is asserted and when clear no reset is
0b asserted. (dprddb_novsyncreset) This selects between VRVSYNC and hi-res VSYCN
7:6 when set with dprvrd_novsyncreset also set sync_select novsyncreset.
RW (dprddb_sync_select) X0 = No Vsync reset 01 = VGA vsync or hi-res between Nat and
UL mode 11 = VGA vsync reset in both UL and native
0b
5 DDBMUNIT: C0 ECO1 chicken bit defaulted to fix enable
RW
0b HDCPUNIT: EGLK A5 ECO1 Fix. Read Data Fix For RMBus Protocol. vsmunit: Lock Up
4
RW Issue.

0b DPRVGA_DPBSTALL_UL_THRESHOLD: VGATEST2 issue fix, Stall throttling done

3:2 during horiz_blank and UL mode is asserted. (DPRVGA_dpbstall_ul_threshold). 01: DPB
RW to VGA stall during UL mode

0b DPRAUDM_SAMPLE_PRESENT_DISABLE: When set this bit will disable the sample

1 present bits being set in layout 1 mode of Audio. Default is to enable sample present on
RW Audio. (DPRAUDM_sample_present_disable) vsmunit: FBC/SR Power Fix

0b RESERVED_2: [DevVLVP] MBZ. This bit si the same as bit 31 in 70450h

0
RW rega_loadcount_crtdetect

14.11.221 CCBR—Offset 70408h

ChickenCount Bit Register

Access Method
Type: Memory Mapped I/O Register
CCBR: [GTTMMADR_LSB + 2BF20h] + 70408h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Bay Trail-I SoC

Datasheet 743
 Graphics, Video and Display

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

HPD_AND_CRT_DETECT_TEST_MODES
Bit Default &
Description
Range Access

0b
31:0 HPD_AND_CRT_DETECT_TEST_MODES: HPD and CRT detect test mode
RW

14.11.222 CBR3—Offset 7040Ch

Chicken3 Bit Register

Access Method
Type: Memory Mapped I/O Register
CBR3: [GTTMMADR_LSB + 2BF20h] + 7040Ch
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DPTPIPEB_CHICKEN_BITS

DPTPIPEA_CHICKEN_BITS

GOOD_SYNC

SELECT_CDCLK_COUNT_FOR_DEGLITCH

CHICKEN_UNGATECLK

READBACK
PIPEACLKGATEEN
MENC16

FREQUENCY_WINDOWING

AUXD_GMBUS_CONNECTION

AUXB_GMBUS_CONNECTION
MENC_NEVERENDING

AUXC_GMBUS_CONNECTION
PIPEBCLKGATEEN

CHICKEN_MULTIEDGEERROR

Bay Trail-I SoC

744 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

0b
31:25 DPTPIPEB_CHICKEN_BITS: not used [DevVLVP]: Reserved
RW
0b
24:18 DPTPIPEA_CHICKEN_BITS: not used [DevVLVP]: Reserved
RW
0b PIPEBCLKGATEEN: Enables reg_pipeBclkgateen_cd reg_pipeBclkgateen_db
17
RW [DevVLVP]: Reserved

0b PIPEACLKGATEEN: Enables reg_pipeAclkgateen_cd reg_pipeAclkgateen_da

16
RW [DevVLVP]: Reserved

0b MENC16: Chicken to cause MENC to output just 16 manchester 0s for sync (otherwise
15
RW 26) [DevVLVP]: Reserved

0b MENC_NEVERENDING: Chicken to cause MENC to output neverending sync 0s for

14
RW electrical testing [DevVLVP]: Reserved

0b FREQUENCY_WINDOWING: Chicken to tighten the frequency windowing [DevVLVP]:

13
RW Reserved

0b GOOD_SYNC: Chicken to check for only 8 good sync 0s instead of 12 [DevVLVP]:

12
RW Reserved

0b SELECT_CDCLK_COUNT_FOR_DEGLITCH: 11 = 1/16 2X bit clock divider value -

11:10 31.125ns 10 = 1/8 2X bit clock divider value - 62.5ns 01 = 1/4 2X bit clock divider value
RW - 125ns 00 = 25 - GMBUS type 50ns at 500MHz cdclk [DevVLVP]: Reserved
0b CHICKEN_UNGATECLK: 1 = Ungate clock 0 = Automatic clock gating [DevVLVP]:
9
RW Reserved

0b CHICKEN_MULTIEDGEERROR: 1 = Multiple edges in window is an eror 0 = Multiple

8
RW edges in window is okay [DevVLVP]: Reserved

0b READBACK: 11 = Readback of bit clock divide field gives the error type 01 = Readback
7:6 gives the recovered clock frequency 00 = Readback gives the programmed clock
RW frequency [DevVLVP]: Reserved
0b AUXD_GMBUS_CONNECTION: Selectes gmbus connection for AUXD [DevVLVP]:
5:4
RW Reserved

0b AUXC_GMBUS_CONNECTION: Selectes gmbus connection for AUXC [DevVLVP]:

3:2
RW Reserved

0b AUXB_GMBUS_CONNECTION: Selectes gmbus connection for AUXB [DevVLVP]:

1:0
RW Reserved

14.11.223 SWF00—Offset 70410h

Software Flag Registers

Access Method
Type: Memory Mapped I/O Register SWF00: [GTTMMADR_LSB + 2BF20h] + 70410h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

Datasheet 745
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESERVED_
Bit Default &
Description
Range Access

0b
31:0 RESERVED_: for Video BIOS and Drivers
RW

14.11.224 SWF01—Offset 70414h

Software Flag Registers

Access Method
Type: Memory Mapped I/O Register SWF01: [GTTMMADR_LSB + 2BF20h] + 70414h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED_

Bit Default &

Description
Range Access

0b
31:0 RESERVED_: for Video BIOS and Drivers
RW

14.11.225 SWF02—Offset 70418h

Software Flag Registers

Access Method
Type: Memory Mapped I/O Register SWF02: [GTTMMADR_LSB + 2BF20h] + 70418h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

746 Datasheet
Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESERVED_
Bit Default &
Description
Range Access

0b
31:0 RESERVED_: for Video BIOS and Drivers
RW

14.11.226 SWF03—Offset 7041Ch

Software Flag Registers

Access Method
Type: Memory Mapped I/O Register SWF03: [GTTMMADR_LSB + 2BF20h] + 7041Ch
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED_

Bit Default &

Description
Range Access

0b
31:0 RESERVED_: for Video BIOS and Drivers
RW

14.11.227 SWF04—Offset 70420h

Software Flag Registers

Access Method
Type: Memory Mapped I/O Register SWF04: [GTTMMADR_LSB + 2BF20h] + 70420h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

Datasheet 747
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESERVED_
Bit Default &
Description
Range Access

0b
31:0 RESERVED_: for Video BIOS and Drivers
RW

14.11.228 SWF05—Offset 70424h

Software Flag Registers

Access Method
Type: Memory Mapped I/O Register SWF05: [GTTMMADR_LSB + 2BF20h] + 70424h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED_

Bit Default &

Description
Range Access

0b
31:0 RESERVED_: for Video BIOS and Drivers
RW

14.11.229 SWF06—Offset 70428h

Software Flag Registers

Access Method
Type: Memory Mapped I/O Register SWF06: [GTTMMADR_LSB + 2BF20h] + 70428h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

748 Datasheet
Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESERVED_
Bit Default &
Description
Range Access

0b
31:0 RESERVED_: for Video BIOS and Drivers
RW

14.11.230 SWF07—Offset 7042Ch

Software Flag Registers

Access Method
Type: Memory Mapped I/O Register SWF07: [GTTMMADR_LSB + 2BF20h] + 7042Ch
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED_

Bit Default &

Description
Range Access

0b
31:0 RESERVED_: for Video BIOS and Drivers
RW

14.11.231 SWF08—Offset 70430h

Software Flag Registers

Access Method
Type: Memory Mapped I/O Register SWF08: [GTTMMADR_LSB + 2BF20h] + 70430h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

Datasheet 749
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESERVED_
Bit Default &
Description
Range Access

0b
31:0 RESERVED_: for Video BIOS and Drivers
RW

14.11.232 SWF09—Offset 70434h

Software Flag Registers

Access Method
Type: Memory Mapped I/O Register SWF09: [GTTMMADR_LSB + 2BF20h] + 70434h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED_

Bit Default &

Description
Range Access

0b
31:0 RESERVED_: for Video BIOS and Drivers
RW

14.11.233 SWF0A—Offset 70438h

Software Flag Registers

Access Method
Type: Memory Mapped I/O Register SWF0A: [GTTMMADR_LSB + 2BF20h] + 70438h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

750 Datasheet
Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESERVED_
Bit Default &
Description
Range Access

0b
31:0 RESERVED_: for Video BIOS and Drivers
RW

14.11.234 SWF0B—Offset 7043Ch

Software Flag Registers

Access Method
Type: Memory Mapped I/O Register SWF0B: [GTTMMADR_LSB + 2BF20h] + 7043Ch
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED_

Bit Default &

Description
Range Access

0b
31:0 RESERVED_: for Video BIOS and Drivers
RW

14.11.235 SWF0C—Offset 70440h

Software Flag Registers

Access Method
Type: Memory Mapped I/O Register SWF0C: [GTTMMADR_LSB + 2BF20h] + 70440h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

Datasheet 751
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESERVED_
Bit Default &
Description
Range Access

0b
31:0 RESERVED_: for Video BIOS and Drivers
RW

14.11.236 SWF0D—Offset 70444h

Software Flag Registers

Access Method
Type: Memory Mapped I/O Register SWF0D: [GTTMMADR_LSB + 2BF20h] + 70444h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED_

Bit Default &

Description
Range Access

0b
31:0 RESERVED_: for Video BIOS and Drivers
RW

14.11.237 SWF0E—Offset 70448h

Software Flag Registers

Access Method
Type: Memory Mapped I/O Register SWF0E: [GTTMMADR_LSB + 2BF20h] + 70448h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

752 Datasheet
Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESERVED_
Bit Default &
Description
Range Access

0b
31:0 RESERVED_: for Video BIOS and Drivers
RW

14.11.238 SWF0F—Offset 7044Ch

Software Flag Registers

Access Method
Type: Memory Mapped I/O Register SWF0F: [GTTMMADR_LSB + 2BF20h] + 7044Ch
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED_

Bit Default &

Description
Range Access

0b
31:0 RESERVED_: for Video BIOS and Drivers
RW

14.11.239 CBR4—Offset 70450h

Display Chicken Bits 4 ;

Access Method
Type: Memory Mapped I/O Register CBR4: [GTTMMADR_LSB + 2BF20h] + 70450h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

Datasheet 753
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FLIP_MSA_VERTICAL_TOTAL_IN_INTERLACE_MODE

DAC_DBL_LIN_GREEN_CHANNEL_COUNTER_SOURCE_SELECT

DAC_DBL_LIN_RGB_DAC_DFT_MODE_ENABLE
DRPO_DPT_FIELD_INVERT
CRC_DOUBLEBUFFER_DISABLE

SDVO_RX_FIX

DAC_DBL_LIN_RED_CHANNEL_COUNTER_SOURCE_SELECT
DAC_DOUBLE_LINEARITY_REGISTER

DAC_DBL_LIN_COUNTER_2_OVERRIDE_SELECT
REGA_LOADCOUNT_CRTDETECT

RESERVED

PCH_FIELD_ID_FIX
HPD_TEST_MODE

LVDS_LEGACY_WRITE_PROTECTION

RESERVED_1
HPD_GLITCH_REMOVAL_COUNT_VALUE_SELECTION

DAC_DBL_LIN_BLUE_CHANNEL_COUNTER_SOURCE_SELECT
Bit Default &
Description
Range Access

0b REGA_LOADCOUNT_CRTDETECT: Project: All Format: Load initial value to crtdetect

31
RW counter

0b HPD_TEST_MODE: Project: All Default Value: 0b Load programmable value for filter
30 and long pulse value of HPD Value Name Description Project 0b Short Pulse Short Pulse
RW All 1b Long Pulse Long Pulse All
0b
29 RESERVED: Project: All Format: PBC
RW

0b FLIP_MSA_VERTICAL_TOTAL_IN_INTERLACE_MODE: Project: All Format: Set to 1

28
RW to flip MSA vtotal

0b DRPO_DPT_FIELD_INVERT: Project: All Format: Invert interlaced field ID output

27
RW from dptunit.

0b CRC_DOUBLEBUFFER_DISABLE: Project: All Format: Disable doublebuffering on

26
RW CRCs so enable/disable and source select will happen immediately.

0b HPD_GLITCH_REMOVAL_COUNT_VALUE_SELECTION: Project: All Default Value:

25 0b Value Name Description Project 0b 500us 500us glitch removal All 1b 50us 50us
RW glitch removal All

0b SDVO_RX_FIX: Project: All Format: Program SDVO receiver fix values [DevVLVP]:
24:21
RW Reserved

0b
20 LVDS_LEGACY_WRITE_PROTECTION: Project: All Format: [DevVLVP]: Reserved
RW

0b PCH_FIELD_ID_FIX: Project: All Format: 1: CPU and PCH field IDs are independent 0:
19
RW CPU field ID is tied to PCH field ID [DevVLVP]: Reserved

0b
18:16 RESERVED_1: Project: All Format: MBZ
RW

Bay Trail-I SoC

754 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

DAC_DOUBLE_LINEARITY_REGISTER: Project: All Format: Project: DevIBX-B Value

0b Name Description Project 00b Disable Normal RGB operation, no test mode enabled All
15:8
RW 01b Counter 1 Counter 1 All 10b Inverse Counter 1 Inverse of counter 1 All 11b Counter
2 Counter 2 All
DAC_DBL_LIN_RED_CHANNEL_COUNTER_SOURCE_SELECT: Project: DevIBX-B
0b Default Value: 00b DefaultVaueDesc BitFieldDesc Value Name Description Project 00b
7:6 Disable Normal RGB operation, no test mode enabled All 01b Counter 1 Counter 1 All
RW 10b Inverse Counter 1 Inverse of Counter 1 All 11b Counter 2 Counter 2 All
Programming Notes Notes Errata Description Project # Desc All
DAC_DBL_LIN_BLUE_CHANNEL_COUNTER_SOURCE_SELECT: Project: DevIBX-B
0b Default Value: 00b Value Name Description Project 00b Disable Normal RGB operation,
5:4
RW no test mode enabled All 01b Counter 1 Counter 1 All 10b Inverse Counter 1 Inverse of
counter 1 All 11b Counter 2 Counter 2 All
DAC_DBL_LIN_GREEN_CHANNEL_COUNTER_SOURCE_SELECT: Project: DevIBX-
0b B Default Value: 00b Value Name Description Project 00b Disable Normal RGB
3:2
RW operation, no test mode enabled All 01b Counter 1 Counter 1 All 10b Inverse Counter 1
Inverse of counter 1 All 11b Counter 2 Counter 2 All

DAC_DBL_LIN_COUNTER_2_OVERRIDE_SELECT: Project: DevIBX-B Default Value:

0b 0b Value Name Description Project 0b No override No override, count value is from
1
RW counter 2 All 1b Override Override mode enabled, count value is from 8-bit override
value All

0b DAC_DBL_LIN_RGB_DAC_DFT_MODE_ENABLE: Project: DevIBX-B Default Value:

0 0b Value Name Description Project 0b Disable Normal operation, no test mode enabled
RW All 1b Enable RGB DAC DFT mode enabled All

14.11.240 PIPEB_DSL—Offset 71000h

Display Scan Line

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) PIPEB_DSL: [GTTMMADR_LSB + 2BF20h] + 71000h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CURRENT_FIELD

RESERVED

PIPE_B_DISPLAY_LINE_COUNTER

Bay Trail-I SoC

Datasheet 755
 Graphics, Video and Display

Bit Default &

Description
Range Access

CURRENT_FIELD: [DevBLC, DevCTG, DevCDV] Provides read back of the current field
0b being displayed on display pipe B. Non-TV mode: 0 = first field (odd field) 1 = second
31
RO field (even field) TV mode: 1 = first field (odd field) 0 = second field (even field)
[DevBW and DevCL] Reserved: Read only.

0b
30:13 RESERVED: Read only.
RO

PIPE_B_DISPLAY_LINE_COUNTER: This register enables the read back of the

0b display vertical line counter . The display line values are from the pipe B timing
12:0
RO generator. They change at the leading edge of HSYNC, and can be safely read at any
time.

14.11.241 PIPEB_SLC—Offset 71004h

Pipe B Display Scan Line Range Compare Register

Access Method
Type: Memory Mapped I/O Register
PIPEB_SLC: [GTTMMADR_LSB + 2BF20h] + 71004h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
INCLUSIVE_EXCLUSIVE

RESERVED

START_SCAN_LINE_NUMBER

RESERVED_1

END_SCAN_LINE_NUMBER

Bit Default &

Description
Range Access

0b
31 INCLUSIVE_EXCLUSIVE: 1 = Inclusive Within Range, 0 = Exclusive Out of Range
RW
0b
30:29 RESERVED: Read only.
RW
START_SCAN_LINE_NUMBER: [DevBLC, DevCTG, DevCDV] This field specifies the
starting scan line number of the Scan Line Window. Format = U16 in scan lines, where
0b scan line 0 is the first line of the display frame. Range = [0,Display Buffer height in
28:16
RW lines-1]. [DevBW] and [DevCL] End Scan Line Number: This field specifies the ending
scan line number of the Scan Line Window. Format = U16 in scan lines, where scan line
0 is the first line of the display frame. Range = [0, Display Buffer height in lines-1].
0b
15:13 RESERVED_1: Read only.
RW

Bay Trail-I SoC

756 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

END_SCAN_LINE_NUMBER: [DevBLC, DevCTG, DevCDV] This field specifies the

ending scan line number of the Scan Line Window. Format = U16 in scan lines, where
0b scan line 0 is the first line of the display frame. Range = [0, Display Buffer height in
12:0
RW lines-1]. [DevBW] and [DevCL] Start Scan Line Number: This field specifies the starting
scan line number of the Scan Line Window. Format = U16 in scan lines, where scan line
0 is the first line of the display frame. Range = [0,Display Buffer height in lines-1].

14.11.242 PIPEBCONF—Offset 71008h

Pipe B Configuration Register

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) PIPEBCONF: [GTTMMADR_LSB + 2BF20h] + 71008h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DISPLAYPORT_POWER_MODE_SWITCH_DEVVLVP
DISPLAY_OVERLAY_PLANES_OFF

REFRESH_RATE_CXSR_MODE_ASSOCIATION

BITS_PER_COLOR
FRAME_START_DELAY

MIPI_DISPLAY_SELF_REFRESH_MODE_FOR_MIPI_B

S3D_SPRITE_INTERLEAVING_FORMAT
DISPLAY_PORT_AUDIO_ONLY_MODE

DDA_RESET_TEST_MODE
PIPE_B_ENABLE

FORCE_BORDER

CURSOR_PLANES_OFF

COLOR_CORRECTION_MATRIX_ENABLE_ON_PIPE_B

S3D_SPRITE_ORDER
INTERLACED_MODE

COLOR_RANGE_SELECT

RESERVED_1

DITHERING_ENABLE

RESERVED_2
PIPE_STATE
RESERVED

PIPE_B_GAMMA_UNIT_MODE

DITHERING_TYPE

Bit Default &

Description
Range Access

PIPE_B_ENABLE: Setting this bit to the value of one, turns on pipe B. This must be
done before any planes are enabled on this pipe. Changing it to a zero should only be
done when all planes that are assigned to this pipe have been disabled. Turning the pipe
enable bit off disables the timing generator in this pipe. Plane disable occurs after the
next VBLANK event after the plane is disabled. Synchronization pulses to the display are
not maintained if the timing generator is disabled. Power consumption will be at its
0b lowest state when disabled. A separate bit controls the DPLL enable for this pipe. Pipe
31
RW timing registers should contain valid values before this bit is enabled. Disabling the Pipe
and changing the timing registers and re-enabling the pipe before the next VBLANK will
cause the mode change to occur at the end of the current frame. This requires no wait
on the software s part. On the other hand, if this is the disabling of the pipe, that does
require a software wait for VBLANK to occur. Synchronization pulses to the display are
not maintained if the timing generator is disabled. Power consumption is at it s lowest
state. 1 = Enable 0 = Disable

Bay Trail-I SoC

Datasheet 757
 Graphics, Video and Display

Bit Default &

Description
Range Access

0b PIPE_STATE: This bit indicates the actual state of the pipe. Since there can be some
30 delay between disabling the pipe and the pipe actually shutting off, this bit indicates the
RO true current state of the pipe. 0 = Disabled 1 = Enabled AccessType: Read Only
0b
29 RESERVED: Write as zero.
RW
FRAME_START_DELAY: Used to delay the frame start signal that is sent to the display
planes. Normal operation uses the default 00 value and test modes can use the delayed
0b frame start to shorten the test time. This would be set to 00 for normal operation. 00 =
28:27 Frame Start occurs on the first HBLANK after the start of VBLANK 01 = Frame Start
RW occurs on the second HBLANK after the start of VBLANK 10 = Frame Start occurs on the
third HBLANK after the start of VBLANK 11 = Frame Start occurs on the forth HBLANK
after the start of VBLANK

0b DISPLAY_PORT_AUDIO_ONLY_MODE: [DevVLVP] Setting this bit to 1 indicates the

26 DisplayPort will output audio only. 0 = DisplayPort will output Video or Video and Audio
RW 1 = DisplayPort will output Audio only
0b FORCE_BORDER: : (TEST MODE)0 = Normal Operation 1 = Color information is
25
RW ignored and border color is substituted during active region

PIPE_B_GAMMA_UNIT_MODE: . This bit selects which mode the pipe gamma

correction logic works in. In the palette mode, it behaves as a 3X256x8 RAM lookup.
0b VGA and indexed mode operation should use the palette in 8-bit mode. In the 10-bit
24
RW gamma mode, it will act as a piecewise linear interpolation. Other gamma units such as
in the overlay and sprite are unaffected by this bit.0 = 8-bit Palette Mode 1 = 10-bit
Gamma Mode
INTERLACED_MODE: These bits are used for software control of interlaced behavior.
They are updated immediately if the pipe is off, or in the vertical blank after
programming if pipe is enabled. 0xx = Progressive 100 = Interlaced embedded panel
using programmable vertical sync shift (2x) 101 = Interlaced using vertical sync shift.
0b Backup option to setting 110. (2x) 110 = Interlaced with VSYNC/HSYNC Field Indication
23:21
RW using legacy vertical sync shift. Used for SDVO. 111 = Interlaced with Field 0 Only using
legacy vertical sync shift. Not used. Note: VGA display modes, sDVO line stall, and Panel
fitting do not work while in interlaced modes Setting the Interlaced embedded panel
mode causes hardware to automatically modify the output to match the specifications of
panels that support interlaced mode.

MIPI_DISPLAY_SELF_REFRESH_MODE_FOR_MIPI_B: .0 = Normal Operation,

0b display controller generate timing and refresh display panel at refresh rate 1 = Display
20
RW self-refresh mode. Display controller update frame buffer in display module on demand
only
DISPLAY_OVERLAY_PLANES_OFF: . This bit when set will cause all enabled Display
and overlay planes that are assigned to this pipe to be disabled by overriding the
0b current setting of the plane enable bit, at the next VBLANK. Timing signals continue as
19
RW they were but the screen becomes blank. Setting the bit back to a zero will then allow
the display and overlay planes to resume on the following VBLANK.0 = Normal
Operation 1 = Planes assigned to this pipe are disabled.
CURSOR_PLANES_OFF: . This bit when set will cause all enabled cursor planes that
are assigned to this pipe to be disabled by overriding the current setting of the plane
0b enable bit, at the next VBLANK. Timing signals continue as they were but the screen
18
RW becomes blank. Setting the bit back to a zero will then allow the cursor planes to
resume on the following VBLANK. 0 = Normal Operation 1 = Planes assigned to this pipe
are disabled.
REFRESH_RATE_CXSR_MODE_ASSOCIATION: These bits select how refresh rates
are tied to CxSR on pipe B. When they are set to anything other than 00, bits 23:21 of
this register must be programmed to 0xx. Switching between 01 and 10 settings directly
is not allowed. Software must program this field to 00 before switching. Software is
0b responsible for enabling this mode only for integrated dispay panels that support
17:16 corresponding mode. 00 Default no dynamic refresh rate change enabled. Software
RW control only. 01 Progressive-to-progressive refresh rate change enabled and tied to
CxSR. Pixel clock values set in FPB0/FPB1 settings in the DPLLB control register and
FPB0/FPB1 divider registers. 10 Progressive-to-interlaced refresh rate change enabled
and tied to CxSR. Pixel clock value does not change in this case. Scaling must be
disabled in this mode. Uses programmable VS shift 11 Reserved

Bay Trail-I SoC

758 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

0b COLOR_CORRECTION_MATRIX_ENABLE_ON_PIPE_B: 1 = Color Correction

15 Coefficients are enabled to perform color correction 0 = Color Correction Coefficients are
RW disabled
DISPLAYPORT_POWER_MODE_SWITCH_DEVVLVP: This bit selects the software
controlled progressive to progressive power saving mode (software controlled DRRS).
0b Hardware Controlled Refresh Rate Select must be disabled when enabling this. Link and
14
RW data M/N 1 values are used for normal settings, M/N 2 values are used for low power
settings. 0 Normal progressive refresh rate (default) 1 Low Power progressive refresh
rate

0b COLOR_RANGE_SELECT: [DevVLVP]: This bit is used to select the color range of RBG
13 outputs. 0 = Apply full 0-255 color range to the output (Default) 1 = Apply 16-235 color
RW range to the output

0b S3D_SPRITE_ORDER: This bit controls the blending order of the sprite planes for S3D
12 support: 0 = Sprite C first. The first line or pixel comes from Sprite C (default) 1 =
RW Sprite D first. The first line or pixel comes from Sprite D

0b S3D_SPRITE_INTERLEAVING_FORMAT: These bits control the Sprite C/D

11:10 interleaving format in S3D mode 00 = No interleaving 01 = Line interleaving 10 = Pixel
RW interleaving 11 = Reserved
RESERVED_1: [DevCDV, DevVLVP] MBZ Scrambling enable [DevCTG]: This bit enables
0b scrambling for DisplayPort. Software must set this bit appropriately when enabling a
9:8 DisplayPort output. 00 = Scrambling disabled (Default) 01 = Scrambling enabled, no SR
RW after initialization at loop 2 of training 10 - RESERVED 11 = Scrambling and SR enabled.
Scrambling is reset every 512 BS symbols.

BITS_PER_COLOR: [DevCTG, DevCDV, DevVLVP]: This field selects the number of bits
per color sent to a receiver device connected to this port. Color format takes place on
the Vblank after being written. Color format change can be done independent of a pixel
0b clock change. Selecting a pixel color depth higher or lower than the pixel color depth of
7:5
RW the frame buffer results in dithering the output stream. For further details on Display
Port fixed frequency programming to accommodate these formats refer to DP Frequency
Programming in DPLL section of Bspec. 000 = 8 bits per color (Default) 001 = 10 bits
per color 010 = 6 bits per color 011 = RESERVED 1xx = RESERVED

0b DITHERING_ENABLE: [DevCTG, DevCDV]: This bit enables dithering for DisplayPort

4 6bpc or 8bpc modes 0 Dithering disabled (Default) 1 Dithering enabled Programming
RW Note: Dithering should only be enabled for 8bpc or 6bpc.

0b DITHERING_TYPE: [DevCTG, DevCDV]: This bit selects dithering type for DisplayPort
3:2 6bpc or 8bpc modes 00 - Spatial only (default) 01- Spatio-Temporal 1 10- Spatio-
RW Temporal 2 (testmode) 11- Temporal only (testmode)

0b DDA_RESET_TEST_MODE: [DevCTG, DevCDV]: 0 Do not reset DDA 1 Reset DDA

1
RW every 8th display frame

0b
0 RESERVED_2: Write as zero
RW

14.11.243 PIPEBGCMAXRED—Offset 71010h

Pipe B Gamma Correction Max Red

Access Method
Type: Memory Mapped I/O Register
PIPEBGCMAXRED: [GTTMMADR_LSB + 2BF20h] + 71010h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00010000h

Bay Trail-I SoC

Datasheet 759
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MAX_RED_GAMMA_CORRECTION_POINT
RESERVED

Bit Default &

Description
Range Access

0b
31:17 RESERVED: Reserved.
RW

100000000 MAX_RED_GAMMA_CORRECTION_POINT: . 129th reference point for red channel

16:0 00000000b of the pipe piecewise linear gamma correction. The value should always be programmed
RW to be less than or equal to 1024.0.Format: 11.6 Default: 0x10000

14.11.244 PIPEBGCMAXGREEN—Offset 71014h

Pipe B Gamma Correction Max Green

Access Method
Type: Memory Mapped I/O Register
PIPEBGCMAXGREEN: [GTTMMADR_LSB + 2BF20h] + 71014h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00010000h

Bay Trail-I SoC

760 Datasheet
Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESERVED

MAX_GREEN_GAMMA_CORRECTION_POINT
Bit Default &
Description
Range Access

0b
31:17 RESERVED: Reserved.
RW

100000000 MAX_GREEN_GAMMA_CORRECTION_POINT: . 129th reference point for green

16:0 00000000b channel of the pipe piecewise linear gamma correction. The value should always be
RW programmed to be less than or equal to 1024.0.Format: 11.6 Default: 0x10000

14.11.245 PIPEBGCMAXBLUE—Offset 71018h

Pipe B Gamma Correction Max Blue

Access Method
Type: Memory Mapped I/O Register
PIPEBGCMAXBLUE: [GTTMMADR_LSB + 2BF20h] + 71018h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00010000h

Bay Trail-I SoC

Datasheet 761
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESERVED

MAX_BLUE_GAMMA_CORRECTION_POINT
Bit Default &
Description
Range Access

0b
31:17 RESERVED: Reserved.
RW

100000000 MAX_BLUE_GAMMA_CORRECTION_POINT: . 129th reference point for blue channel

16:0 00000000b of the pipe piecewise linear gamma correction. The value should always be programmed
RW to be less than or equal to 1024.0.Format: 11.6 Default: 0x10000

14.11.246 PIPEBSTAT—Offset 71024h

Pipe B Status

Access Method
Type: Memory Mapped I/O Register
PIPEBSTAT: [GTTMMADR_LSB + 2BF20h] + 71024h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

762 Datasheet
Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ODD_FIELD_INTERRUPT_STATUS

START_OF_VERTICAL_BLANK_INTERRUPT_STATUS
START_OF_VERTICAL_BLANK_INTERRUPT_ENABLE

PLANE_B_FLIP_DONE_INTERRUPT_STATUS
PIPE_B_UNDERFLOW_STATUS
SPRITE_D_FLIP_DONE_INTERRUPT_ENABLE

PLANE_B_FLIP_DONE_INTERRUPT_ENABLE

PIPE_B_HORIZONTAL_BLANK_INTERRUPT_ENABLE
SPRITE_D_FLIP_DONE_INTERRUPT_STATUS

PIPE_B_PANEL_SELF_REFRESH_STATUS
CRC_ERROR_ENABLE
CRC_DONE_ENABLE

DISPLAY_LINE_COMPARE_ENABLE
BLM_EVENT_ENABLE

ODD_FIELD_INTERRUPT_EVENT_ENABLE

PANEL_SELF_REFRESH_PSR_INTERRUPT_ENABLE_ON_PIPE_B

PIPE_B_FRAMESTART_INTERRUPT_ENABLE

SPRITE_C_FLIP_DONE_INTERRUPT_STATUS

SECOND_PERFORMANCE_COUNTER2_INTERRUPT_STATUS

PIPE_B_VERTICAL_SYNC_STATUS
PIPE_B_DISPLAY_LINE_COMPARE_STATUS
PERFORMANCE_COUNTER2_INTERRUPT_ENABLE

CRC_ERROR_STATUS
CRC_DONE_INTERRUPT_STATUS

BLM_IMAGE_BRIGHTNESS_STATUS
RESERVED

EVEN_FIELD_INTERRUPT_STATUS

PIPE_B_FRAMESTART_INTERRUPT_STATUS
SPRITE_C_FLIP_DONE_INTERRUPT_ENABLE

PIPE_B_HORIZONTAL_BLANK_STATUS
VERTICAL_SYNC_INTERRUPT_ENABLE

EVEN_FIELD_INTERRUPT_EVENT_ENABLE

Bit Default &

Description
Range Access

PIPE_B_UNDERFLOW_STATUS: This bit is set when an underflow occurs at the

0b display pipe B. It is cleared by writing a one to this bit. This event will occur naturally
31 during mode changes, to be effective, it should be cleared after a mode change. This bit
RW/1C is only valid after Pipe B has been completely configured. 1 = FIFO B Underflow
occurred 0 = FIFO B Underflow did not occur AccessType: One to Clear

0b SPRITE_D_FLIP_DONE_INTERRUPT_ENABLE: This will enable the consideration of

30 the Sprite D flip done interrupt status bit in the first line interrupt logic 0 = Sprite D Flip
RW Done Interrupt Disabled 1 = Sprite D Flip Done Interrupt Enabled

0b CRC_ERROR_ENABLE: This will enable the consideration of the CRC error status bit in
29 the first line interrupt/status logic. 0 = CRC Error Detect Disabled 1 = CRC Error Detect
RW Enabled

0b CRC_DONE_ENABLE: This will enable the consideration of the CRC done status bit in
28 the first line interrupt/status logic. 0 = CRC Done Detect Disabled 1 = CRC Done Detect
RW Enabled

0b PERFORMANCE_COUNTER2_INTERRUPT_ENABLE: This bit enables the second

27 performance counter interrupt. 0 = Second Performance Counter2 Interrupt Status
RW Disabled 1 = Second Performance Counter2 interrupt Status Enabled

0b PLANE_B_FLIP_DONE_INTERRUPT_ENABLE: This will enable the consideration of

26 the Plane B flip done interrupt status bit in the first line interrupt logic 0 = Plane B flip
RW done Interrupt/Status Disabled 1 = Plane B flip done Interrupt/Status Enabled
0b VERTICAL_SYNC_INTERRUPT_ENABLE: 0 = Vertical Sync Interrupt/Status Disabled
25
RW 1 = Vertical Sync Interrupt/Status Enabled

0b DISPLAY_LINE_COMPARE_ENABLE: 0 = Pipe B Display Line Compare Status Report

24
RW Disabled 1 = Pipe B Display Line Compare Status report Enabled

BLM_EVENT_ENABLE: [DevCL, DevCTG, DevCDV]: This interrupt is generated by the

0b image brightness segment comparators. Which segment cause an interrupt are
23
RW controlled by the BLM Histogram control register. 0 = No BLM event enabled 1 = BLM
event enabled

Bay Trail-I SoC

Datasheet 763
 Graphics, Video and Display

Bit Default &

Description
Range Access

0b SPRITE_C_FLIP_DONE_INTERRUPT_ENABLE: This will enable the consideration of

22 the Sprite C flip done interrupt status bit in the first line interrupt logic 0 = Sprite C Flip
RW Done Interrupt Disabled 1 = Sprite C Flip Done Interrupt Enabled

0b ODD_FIELD_INTERRUPT_EVENT_ENABLE: . This bit should only be used when this

21 pipe is in an interlaced display timing.0 = Odd Field Event disable 1 = Odd Field Event
RW enable

0b EVEN_FIELD_INTERRUPT_EVENT_ENABLE: . This bit should only be used when this

20 pipe is in an interlaced display timing.0 = Even field Event disable 1 = Even field Event
RW enable
0b PANEL_SELF_REFRESH_PSR_INTERRUPT_ENABLE_ON_PIPE_B: 0 = PSR
19
RW interrupt Disabled on Pipe B 1 = PSR Interrupt Enabled on Pipe B

START_OF_VERTICAL_BLANK_INTERRUPT_ENABLE: This will enable the

0b consideration of the start of vertical blank interrupt status bit in the first line interrupt/
18
RW status logic. 0 = Start of Vertical Blank Interrupt/Status Disabled 1 = Start of Vertical
Blank Interrupt/Status Enabled

0b PIPE_B_FRAMESTART_INTERRUPT_ENABLE: This will enable the consideration of

17 the vertical blank interrupt status bit in the first line interrupt/status logic. 0 = Pipe B
RW Framestart Interrupt/Status Disabled 1 = Pipe B Framestart Interrupt/Status Enabled
PIPE_B_HORIZONTAL_BLANK_INTERRUPT_ENABLE: : This will enable the
0b consideration of the start of horizontal blank interrupt status bit in the first line
16
RW interrupt/status logic0 = Start of Horizontal Blank Interrupt/Status Disabled 1 = Start of
Horizontal Blank Interrupt/Status Enabled

0b SPRITE_D_FLIP_DONE_INTERRUPT_STATUS: MMIO Flip Event is completed on

15
RW/1C Sprite D 0 = Sprite D Flip Not Done 1 = Sprite D Flip Done AccessType: One to Clear

0b SPRITE_C_FLIP_DONE_INTERRUPT_STATUS: MMIO Flip Event is completed on

14
RW/1C Sprite C 0 = Sprite C Flip Not Done 1 = Sprite C Flip Done AccessType: One to Clear

0b CRC_ERROR_STATUS: This bit is set when a Pipe B CRC error is detected. It is cleared
13
RW/1C by a write of a one. 0 = No CRC Error 1 = CRC Error detected AccessType: One to Clear

0b CRC_DONE_INTERRUPT_STATUS: This bit is set when Pipe B CRC calculation and

12 compare are complete. It is cleared by a write of a one. 0 = CRC Not Done 1 = CRC
RW/1C Done AccessType: One to Clear

SECOND_PERFORMANCE_COUNTER2_INTERRUPT_STATUS: This bit is set when

0b the second performance counter2 generates an interrupt. It is cleared by a write of a
11
RW/1C one. 0 = Second performance counter interrupt event not asserted 1 = Second
performance counter interrtup event asserted AccessType: One to Clear

0b PLANE_B_FLIP_DONE_INTERRUPT_STATUS: Async/Sync Flip Event is completed

10 on Display Plane B 0 = Plane B Flip Not Done 1 = Plane B Flip Done AccessType: One to
RW/1C Clear
0b PIPE_B_VERTICAL_SYNC_STATUS: 0 = Vertical Sync not asserted 1 = Vertical Sync
9
RW/1C asserted AccessType: One to Clear

PIPE_B_DISPLAY_LINE_COMPARE_STATUS: This bit is cleared when a write to this

0b register occurs with this bit as a one. Writes with this bit as a zero has no effect on the
8
RW/1C value of the bit. 0 = Display Line Compare Status not asserted 1 = Display Line
Compare Status asserted AccessType: One to Clear

BLM_IMAGE_BRIGHTNESS_STATUS: [DevCL, DevCTG, DevCDV]: This bit is cleared

0b when a write to this register occurs with this bit as a one. Writes with this bit as a zero
7
RW/1C has no effect on the value of the bit. 0 =DPST Interrupt has not occurred on pipe B 1 =
DPST Interrupt has occurred on pipe B AccessType: One to Clear
0b
6 RESERVED: MBZ
RW

Bay Trail-I SoC

764 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

ODD_FIELD_INTERRUPT_STATUS: . This status bit will be set on a Odd field VBLANK

event. This bit should only be used when this pipe is in an interlaced display timing. For
synchronization with register updates, the actual event will occur one line after the start
0b of VBLANK. To use this bit in a polling manner, clear the bit by writing a one to it
5
RW/1C followed by the polling loop waiting for it to become set.Note: This bit will not be set
when pipe is in Interlaced with Field 0 Only using legacy vertical sync shift mode. 0 =
Odd Field Vertical Blank has not occurred 1 = Odd Field Vertical Blank has occurred
AccessType: One to Clear

EVEN_FIELD_INTERRUPT_STATUS: . This status bit will be set on a even filed

VBLANK event. This bit should only be used when this pipe is in an interlaced display
timing. For synchronization with register updates, the actual event will occur one line
0b after the start of VBLANK. To use this bit in a polling manner, clear the bit by writing a
4
RW/1C one to it followed by the polling loop waiting for it to become set.Note: This bit will not
be set when pipe is in Interlaced with Field 0 Only using legacy vertical sync shift mode.
0 = Even Field Vertical Blank has not occurred 1 = Even Field Vertical Blank has
occurred AccessType: One to Clear
PIPE_B_PANEL_SELF_REFRESH_STATUS: This bit indicates interrupt is generated
by the PSR controller and intends to send interrupt to SW driver when the PSR interrupt
0b enable bit (70028h bit 22) is set. This is cleared when a write to this register occurs with
3
RW/1C this bit as a one. Write with this bit as a zero has no effect on the value of the bit. 0 =
PSR Interrupt has not occurred on pipe B 1 = PSR interrupt has occurred on pipe B
AccessType: One to Clear
START_OF_VERTICAL_BLANK_INTERRUPT_STATUS: This status bit will be set at
the beginning of a VBLANK event. At this point, the double buffered display registers
0b flip, taking their new values. To use this bit in a polling manner, clear the bit by writing a
2
RW/1C one to it followed by the polling loop waiting for it to become set. In MIPI DSR mode,
GPIO TE trigger sets the Vblank Interrupt status 0 = Start of Vertical Blank has not
occurred 1 = Start of Vertical Blank has occurred AccessType: One to Clear
PIPE_B_FRAMESTART_INTERRUPT_STATUS: This status bit will be set on a
VBLANK event, when the frame start occurs. The display registers are updated at the
start of vertical blank, but the new register data is not utilized by the display pipeline
0b until the point in the vertical blank period when the frame start occurs, which is the
1
RW/1C event that triggers this bit. To use this bit in a polling manner, clear the bit by writing a
one to it followed by the polling loop waiting for it to become set. 0 = Pipe B Framestart
Status has not occurred 1 = Pipe B Framestart Status has occurred AccessType: One to
Clear
0b PIPE_B_HORIZONTAL_BLANK_STATUS: 0 = Pipe B Horizontal Blank has not
0
RW/1C occurred 1 = Pipe B Horizontal Blank has occurred AccessType: One to Clear

14.11.247 PIPEBFRAMECOUNT—Offset 71040h

Pipe B Frame Counter

Access Method
Type: Memory Mapped I/O Register PIPEBFRAMECOUNT: [GTTMMADR_LSB + 2BF20h] + 71040h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

Datasheet 765
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PIPE_B_FRAME_COUNT
Bit Default &
Description
Range Access

0b PIPE_B_FRAME_COUNT: Provides read back of the display pipe frame counter. This
31:0 counter increments on every start of vertical blank and rolls over back to 0 after 2^32
RO frames

14.11.248 PIPEBFLIPCOUNT—Offset 71044h

Pipe B Flip Counter

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) PIPEBFLIPCOUNT: [GTTMMADR_LSB + 2BF20h] + 71044h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PIPE_B_FLIP_COUNT

Bit Default &

Description
Range Access

PIPE_B_FLIP_COUNT: Provides read back of the display pipe flip counter. This
0b counter increments on each flip of the surface of the primary plane on this pipe. This
31:0
RO includes command streamer asynchronous and synchronous flips and any MMIO writes
to the primary plane surface address. It rolls over back to 0 after 2^32 flips.

14.11.249 PIPEBMSAMISC—Offset 71048h

Pipe B MSA MISC

Access Method

Bay Trail-I SoC

766 Datasheet
Graphics, Video and Display

Type: Memory Mapped I/O Register

PIPEBMSAMISC: [GTTMMADR_LSB + 2BF20h] + 71048h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HARDWARE_DRIVE_MSA_MISC1_ENABLE

MSA_MISC1_FIELD_S3D
RESERVED

Bit Default &

Description
Range Access

HARDWARE_DRIVE_MSA_MISC1_ENABLE: This bit enables hardware to drive MSA

MISC1 bit3:1 with the stero 3D left/right eye field indication. Hardware will drive 000
when S3D mode is disabled, 001 when enabled and the upcoming video frame is right
0b eye, 011 when enabled and the upcoming video frame is left eye. When this bit is
31
RW disabled, software may manually program the MSA MISC1 Field S3D field in bit 2:0 in
this register to set MISC1 bit 3:1 0 = Disable hardware driving MSA MISC1 bit 3:1. Allow
software to manually program MSA MISC1 bit3:1 through MSA_MISC1_FIELD_S3D
(default) 1 = Enable hardware to drive MSA MISC1 bit3:1 for S3D
0b
30:3 RESERVED: Reserved.
RW

MSA_MISC1_FIELD_S3D: This field provides software to manually program MSC1

stero video attribute for DisplayPort: 000 = No stereo video transported 001 = For
0b progressive video, the next (upcoming) video frame is RIGHT eye 010 = Reserved 011
2:0 = For progressive video, the next (upcoming) video frame is LEFT eye 100 = Stacked
RW top and bottom top half represents left-eye view and bottom half represents right-eye
view 101 = Stacked top and bottom top half represents right-eye view and bottom half
represents left-eye view

14.11.250 DSPBADDR—Offset 7117Ch

Display B Async flip Start Address Register

Access Method
Type: Memory Mapped I/O Register
DSPBADDR: [GTTMMADR_LSB + 2BF20h] + 7117Ch
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

Datasheet 767
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DISPLAY_B_START_ADDRESS_BITS

DECRYPTION_REQUEST
RESERVED_MBZ

FLIP_SOURCE

RESERVED_MBZ_1
Bit Default &
Description
Range Access

DISPLAY_B_START_ADDRESS_BITS: This register provides the start address of the

display B plane or the first eye when running in stereo mode. This address must be at
least pixel aligned. This register can be written directly through software or by
command packets in the command stream. It represents an offset from the graphics
memory aperture base and is mapped to physical pages through the global GTT. This
0b address must be 4K aligned. When performing asynchronous flips and the display
31:12 surface is in tiled memory, this address must be 256K aligned. This register can be
RW written directly through software or by command packets in the command stream. It
represents an offset from the graphics memory aperture base and is mapped to physical
pages through the global GTT. If the device supports trusted operation and this plane is
not marked trusted, the memory pages must not be marked NoDMA . Write to this
register triggers async flip The async flip address is written into the Display B Base
Address register 0x7119C
0b
11:4 RESERVED_MBZ: Reserved.
RW

0b FLIP_SOURCE: Project: All Default Value: 0b This bit indicates if the source of the flip
3 is CS or BCS so display can send the flip done response to the appropriate destination.
RW ValueNameDescriptionProject 0b CS Flip source is CS All 1b BCS Flip source is BCS All
DECRYPTION_REQUEST: Project: All Default Value: 0b This bit requests decryption to
be enabled for this plane. This request will be qualified with the separate decryption
0b allow message in order to create the decryption enable. This bit is only allowed to
2 change on a synchronous flip, but once set with a synchronous flip, the bit can remain
RW set while using asynchronous flips. This value is loaded into the surface base address
register of the associated plane. Usage must conform to the rules outlined in the plane
surface base address register.

0b
1:0 RESERVED_MBZ_1: Reserved.
RW

14.11.251 DSPBCNTR—Offset 71180h

Display B/Sprite Plane Control Register

Access Method
Type: Memory Mapped I/O Register DSPBCNTR: [GTTMMADR_LSB + 2BF20h] + 71180h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 01000000h

Bay Trail-I SoC

768 Datasheet
Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DISPLAY_B_SOURCE_PIXEL_FORMAT

PIPE_SELECT

KEY_WINDOW_ENABLE

PIXEL_MULTIPLY
DISPLAY_B_SPRITE_PRIMARY_B_ENABLE
DISPLAY_B_SPRITE_GAMMA_ENABLE

RESERVED

TILED_SURFACE
SOURCE_KEY_ENABLE

_180DISPLAY_ROTATION

S3D_FORCE_DISPLAY_B_BOTTOM
RESERVED_1
RESERVED_2

RESERVED_3

RESERVED_4

RESERVED_5
Bit Default &
Description
Range Access

DISPLAY_B_SPRITE_PRIMARY_B_ENABLE: This bit will enable or disable the

display B/sprite. When this bit is set, the plane will generate pixels for display. When set
0b to zero, memory fetches cease and display is blanked (from this plane) at the next
31
RW VBLANK event from the pipe that this plane is assigned. At least one of the display pipes
must be enabled to enable this plane. There is an override for the enable of this plane in
the Pipe Configuration register. 1 = Enable 0 = Disable
DISPLAY_B_SPRITE_GAMMA_ENABLE: This bit should only be changed after the
0b plane has been disabled. It controls the bypassing of the display pipe gamma unit for
30 this display plane pixel data only. For 8-bit indexed display data, this bit should be set to
RW a one. 0 = Display B pixel data bypasses the pipe gamma correction logic (default). 1 =
Display B pixel data is gamma corrected in the pipe gamma correction logic

DISPLAY_B_SOURCE_PIXEL_FORMAT: This field selects the pixel format for the

sprite/display B. Pixel formats with an alpha channel (8:8:8:8) should not use source
keying. Before entering the blender, each source format is converted to 10 bits per pixel
(details are described in the intermediate precision for the blender section of the Display
Functions chapter). 000x = Reserved. 0010 = 8-bpp Indexed. 0011 = Reserved. 0100 =
Reserved. 0101 = 16-bit BGRX (5:6:5:0) pixel format (XGA compatible). 0110 = 32-bit
0b BGRX (8:8:8:8) pixel format. Ignore alpha. 0111 = 32-bit BGRA (8:8:8:8) pixel format.
29:26 (with pre-multiplied alpha color format) 1000 = 32-bit RGBX (10:10:10:2) pixel format.
RW Ignore alpha. 1001 = 32-bit RGBA (10:10:10:2) pixel format. (with pre-multiplied alpha
color format) 1010 = 32-bit BGRX (10:10:10:2) pixel format Ignore alpha 1011 = 32-
bit BGRA (10:10:10:2) pixel format (with pre-multiplied alpha color format) 1100 = 64-
bit RGBX (16:16:16:16) 16 bit floating point pixel format. Ignore alpha. 1101 = 64-bit
RGBA (16:16:16:16) 16-bit floating point pixel format (with pre-multiplied color format)
1110 = 32-bit RGBX (8:8:8:8) pixel format. Ignore alpha. 1111 = 32-bit RGBA
(8:8:8:8) pixel format (with pre-multiplied color format)
01b
25:24 PIPE_SELECT: Plane B always ties to Pipe B. Reserved AccessType: Read Only
RO
KEY_WINDOW_ENABLE: This applies only to devices with a Display Plane C. It
determines what area of the screen the source key compare should be applied. This bit
is set to one when the color key is used as a destination key for display C. Display plane
0b C must be enabled on the same pipe and display A should not be enabled on this pipe
23
RW for this to be used. The function is only effective when display C is enabled and defined
by Z-order to be behind display B. 0 = If keying is enabled, it applies to the entire
display B plane 1 = If keying is enabled, it applies only to the intersection between
display B and display C [DevBLC] and [DevCTG]: Reserved

Bay Trail-I SoC

Datasheet 769
 Graphics, Video and Display

Bit Default &

Description
Range Access

SOURCE_KEY_ENABLE: When used as a sprite or a secondary this enables source

color keying. Sprite pixel values that match the key will become transparent. Source
keying allows a plane that is behind (below) this plane to show through where the
display B data matches the display B key. This function is overloaded to provide display
0b C destination keying when combined with the key window enable bit.. Setting this bit is
22
RW not allowed when the display pixel format includes an alpha channel. 0 = Sprite source
key is disabled (default) 1 = Sprite source key is enabled. [DevBLC] and [DevCTG]:
Reserved In destination keying, primary plane pixel will be made transparent when
blending with sprite pixel as the destination if the primary src key matches with the
primary pixel value.
PIXEL_MULTIPLY: This cause the display plane to duplicate lines and pixels sent to
0b the assigned pipe. In the line/pixel doubling mode, the horizontal pixels are doubled and
21:20 lines are sent twice. Asynchronous flips are not used in this mode. Programming Notes:
RW Asynchronous flips are not permitted when pixel multiply is enabled. 00 = No
duplication 01 = Line/pixel Doubling 10 = Reserved 11 = Pixel Doubling only
0b
19:16 RESERVED: Write as zero
RW
_180DISPLAY_ROTATION: This mode causes the display plane to be rotated 180 . In
0b addition to setting this bit, software must also set the base address to the lower right
15
RW corner of the unrotated image. [DevCL] Do not enable 180 rotation together with Frame
Buffer Compression 0 = No rotation 1 = 180 rotation
RESERVED_1: [DevBW, DevCL, DevCDV] [DevBLC, DevCTG] Display B Trickle Feed
0b Enable: 0 = Trickle Feed Enabled - Display B data requests are sent whenever there is
14 space in the Display Data Buffer. 1 = Trickle Feed Disabled - Display B data requests are
RW sent in bursts. Note: On mobile products this bit will be ignored such that Trickle Feed is
always disabled. [DevELK] Must always be programmed disabled
RESERVED_2: [DevBW, DevCL, DevCDV] [DevBLC, DevCTG] Display B Data Buffer
0b Partitioning Control: 0 = Display B Data Buffer will encompass Sprite B buffer space
13
RW when Sprite B is disabled. 1 = Display B Data Buffer will not use Sprite B buffer space
when Sprite B is disabled. Note: When in C3xR Max FIFO mode, this bit will be ignored.
0b
12:11 RESERVED_3: Reserved.
RW
TILED_SURFACE: This bit indicates that the display B surface data is in tiled memory.
0b The tile pitch is specified in bytes in the DSPBSTRIDE register. Only X tiling is supported
10 for display surfaces. When this bit is set, it affects the hardware interpretation of the
RW DSPBLINOFF, DSPBTILEOFF, and DSPBSURF registers. 0 = Display B surface uses linear
memory 1 = Display B surface uses X-tiled memory
RESERVED_4: [DevBW, DevCL, DevCDV] Write as zero [DevBLC, DevCTG]
Asynchronous Surface Address Update Enable: This bit will enable asynchronous
updates of the surface address when written by MMIO. The surface address will change
with the next TLB request or when start of vertical blank is reached. Updates during
0b vertical blank may not complete until after the first few active lines are displayed.
9
RW Restrictions: No command streamer initiated surface address updates are allowed when
this bit is enabled. Only one asynchronous update may be made per frame. Must wait
for vertical blank before again writing the surface address register. 0 = DSPBSURF MMIO
writes will update synchronous to start of vertical blank (default) 1 = DSPBSURF MMIO
writes will update asynchronously

0b
8:1 RESERVED_5: Write as zero
RW

S3D_FORCE_DISPLAY_B_BOTTOM: This bit will force the display B plane to be on

0b the bottom of any sprite planes in the Z order. 0 = Display B Z-order is determined by
0
RW the other control bits in pipe B 1 = Display B is forced to be on the bottom of any sprite
planes in Z-order in pipe B

14.11.252 DSPBLINOFFSET—Offset 71184h

Display B/Sprite Linear Offset Register

Access Method

Bay Trail-I SoC

770 Datasheet
Graphics, Video and Display

Type: Memory Mapped I/O Register

DSPBLINOFFSET: [GTTMMADR_LSB + 2BF20h] + 71184h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DISPLAY_B_OFFSET
Bit Default &
Description
Range Access

DISPLAY_B_OFFSET: This register provides the panning offset into the display B
plane. This value is added to the surface address to get the graphics address of the first
0b pixel to be displayed. This offset must be at least pixel aligned. This offset is the
31:0 difference between the address of the upper left pixel to be displayed and the display
RW surface address. When performing 180 rotation, this offset must be the difference
between the last pixel of the last line of the display data in its unrotated orientation and
the display surface address.

14.11.253 DSPBSTRIDE—Offset 71188h

Display B/Sprite Stride Register

Access Method
Type: Memory Mapped I/O Register DSPBSTRIDE: [GTTMMADR_LSB + 2BF20h] + 71188h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DISPLAY_B_SPRITE_STRIDE

RESERVED

Bay Trail-I SoC

Datasheet 771
 Graphics, Video and Display

Bit Default &

Description
Range Access

DISPLAY_B_SPRITE_STRIDE: This is the stride for display B/Sprite in bytes. When

using linear memory, this must be 64 byte aligned. When using tiled memory, this must
be 512 byte aligned. The maximum value for this register is fixed. This register is
updated through a command packet passed through the command stream or writes to
this register. When it is desired to update both this and the start register, the stride
0b register must be written first because the write to the start register is the trigger that
31:6
RW causes the update of both registers on the next VBLANK event. When using tiled
memory, the actual memory buffer stride is limited to a maximum of 16K bytes.
[DevBW, DevCL, DevCDV] The display stride must be power of 2 when doing Asynch
Flips. [DevBW, DevCL, DevCDV] The display stride must be 8KB or greater when doing
Asynch Flips together with 180 rotation. The value in this register is updated through
the command streamer during a synchronous flip.
0b
5:0 RESERVED: Reserved.
RW

14.11.254 DSPBKEYVAL—Offset 71194h

Sprite Color Key Value Register

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) DSPBKEYVAL: [GTTMMADR_LSB + 2BF20h] + 71194h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BLUE_KEY_VALUE
RESERVED

RED_KEY_VALUE

GREEN_KEY_VALUE

Bit Default &

Description
Range Access

0b
31:24 RESERVED: reserved
RW
0b
23:16 RED_KEY_VALUE: Specifies the color key value for the sprite red/Cr channel.
RW
0b
15:8 GREEN_KEY_VALUE: Specifies the color key value for the sprite green/Y channel.
RW
0b
7:0 BLUE_KEY_VALUE: Specifies the color key value for the sprite blue/Cb channel.
RW

14.11.255 DSPBKEYMSK—Offset 71198h

Sprite Color Key Mask Register

Access Method

Bay Trail-I SoC

772 Datasheet
Graphics, Video and Display

Type: Memory Mapped I/O Register

DSPBKEYMSK: [GTTMMADR_LSB + 2BF20h] + 71198h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BLUE_MASK_VALUE
RESERVED

RED_MASK_VALUE

GREEN_MASK_VALUE
Bit Default &
Description
Range Access

0b
31:24 RESERVED: reserved
RW
0b
23:16 RED_MASK_VALUE: Specifies the color key mask for the sprite red/Cr channel.
RW
0b
15:8 GREEN_MASK_VALUE: Specifies the color key mask for the sprite green/Y channel.
RW
0b
7:0 BLUE_MASK_VALUE: Specifies the color key mask for the sprite blue/Cb channel.
RW

14.11.256 DSPBSURF—Offset 7119Ch

Display B Surface Address Register

Access Method
Type: Memory Mapped I/O Register DSPBSURF: [GTTMMADR_LSB + 2BF20h] + 7119Ch
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

Datasheet 773
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DECRYPTION_REQUEST
DISPLAY_B_SURFACE_BASE_ADDRESS

RESERVED_MBZ

FLIP_SOURCE

RESERVED_MBZ_1
Bit Default &
Description
Range Access

DISPLAY_B_SURFACE_BASE_ADDRESS: This address specifies the surface base

address. When the surface is tiled, panning is specified using (x, y) offsets in the
DSPBTILEOFF register. When the surface is in linear memory, panning is specified using
0b a linear offset in the DSPBLINOFF register. This address must be 4K aligned. When
31:12 performing asynchronous flips and the display surface is in tiled memory, this address
RW must be 256K aligned. This register can be written directly through software or by
command packets in the command stream. It represents an offset from the graphics
memory aperture base and is mapped to physical pages through the global GTT.
[DevBW] and [DevCL]: This address must be 128K aligned for linear memory.

0b
11:4 RESERVED_MBZ: Reserved.
RW

0b FLIP_SOURCE: Project: All Default Value: 0b This bit indicates if the source of the flip
3 is CS or BCS so display can send the flip done response to the appropriate destination.
RW ValueNameDescriptionProject 0b CS Flip source is CS All 1b BCS Flip source is BCS All

DECRYPTION_REQUEST: Project: All Default Value: 0b This bit requests decryption to

be enabled for this plane. This request will be qualified with the separate decryption
0b allow message in order to create the decryption enable. This bit is only allowed to
2 change on a synchronous flip, but once set with a synchronous flip, the bit can remain
RW set while using asynchronous flips. This value is loaded into the surface base address
register of the associated plane. Usage must conform to the rules outlined in the plane
surface base address register.
0b
1:0 RESERVED_MBZ_1: Reserved.
RW

14.11.257 DSPBTILEOFF—Offset 711A4h

Display B Tiled Offset Register

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) DSPBTILEOFF: [GTTMMADR_LSB + 2BF20h] + 711A4h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

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774 Datasheet
Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PLANE_START_Y_POSITION
RESERVED

PLANE_START_X_POSITION
RESERVED_1
Bit Default &
Description
Range Access

0b
31:28 RESERVED: Write as zero
RW
PLANE_START_Y_POSITION: These 12 bits specify the vertical position in lines of the
0b beginning of the active display plane relative to the display surface. When performing
27:16
RW 180 rotation, this field specifies the vertical position of the lower right corner relative to
the start of the active display plane in the unrotated orientation.
0b
15:12 RESERVED_1: Write as zero
RW
PLANE_START_X_POSITION: These 12 bits specify the horizontal offset in pixels of
the beginning of the active display plane relative to the display surface. When
0b performing 180 rotation, this field specifies the horizontal position of the lower right
11:0
RW corner relative to the start of the active display plane in the unrotated orientation.
[DevBW, DevCL, DevCDV] When display stride is 16KB and doing Asynch Flips, do not
program the offset to give pans of 7680 to 8191 bytes.

14.11.258 DSPBSURFLIVE—Offset 711ACh

Display B Live Surface Base Address Register [DevCTG-B, DevCDV]

Access Method
Type: Memory Mapped I/O Register DSPBSURFLIVE: [GTTMMADR_LSB + 2BF20h] + 711ACh
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

Datasheet 775
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DISPLAY_B_LIVE_SURFACE_BASE_ADDRESS
Bit Default &
Description
Range Access

0b DISPLAY_B_LIVE_SURFACE_BASE_ADDRESS: . This gives the live value of the

31:0
RO surface base address as being currently used for the plane.

14.11.259 DSPBFLPQSTAT—Offset 71200h

Flip Queue Status Register

Access Method
Type: Memory Mapped I/O Register
DSPBFLPQSTAT: [GTTMMADR_LSB + 2BF20h] + 71200h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED

QUEUE_FREE_ENTRY_COUNT_RO

QUEUE_OCCUPIED_ENTRY_COUNT_RO

Bay Trail-I SoC

776 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

0b
31:16 RESERVED: Write as zero (RO)
RO

0b QUEUE_FREE_ENTRY_COUNT_RO: This value indicates the number of free entries in

15:8 the queue at the time that the register was read. The total number of entries in the
RO queue is the sum of the occupied entry count and the free entry count.

0b QUEUE_OCCUPIED_ENTRY_COUNT_RO: This value indicates the number of

7:0 occupied entries in the queue at the time that the register was read. The total number
RO of entries in the queue is the sum of the occupied entry count and the free entry count.

14.11.260 VGACNTRL—Offset 71400h

VGA Display Plane Control Register

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) VGACNTRL: [GTTMMADR_LSB + 2BF20h] + 71400h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VGA_DISPLAY_DISABLE
VGA_POP_UP_2X_CENTERED_MODE_SCALING

DUAL_PIPE_VGA_PALETTE_B_WRITE_DISABLE
VGA_PIPE_SELECT

RESERVED_

VGA_PALETTE_READ_SELECT
VGA_BORDER_ENABLE

VGA_PALETTE_A_WRITE_DISABLE

LEGACY_VGA_8_BIT_PALETTE_ENABLE
PALETTE_BYPASS_TEST_MODE
NINE_DOT_DISABLE
RESERVED

RESERVED__1

BLINK_DUTY_CYCLE
VGA_CENTERING_ENABLE

VSYNC_BLINK_RATE

Bit Default &

Description
Range Access

VGA_DISPLAY_DISABLE: This bit will disable the VGA compatible display mode. It
has no effect on VGA register or A0000-BFFFF memory aperture accesses which are
controlled by the PCI configuration and VGA register settings. VGA display should only
be enabled if all display planes other than VGA are disabled. After enabling the VGA,
0b most display planes need to stay disabled, only the VGA popup (cursor A) can be
31
RW enabled. The VGA display is never trusted. No secrets are allowed in the pre-allocated
memory and VGA is limited to access only that memory. During trusted operation (when
registers are locked via Lock), this bit will always act as if it was set to a one (disabled
VGA display). VGA 132 Column text mode is not supported. 0 = VGA Display Enabled 1
= VGA Display Disabled

Bay Trail-I SoC

Datasheet 777
 Graphics, Video and Display

Bit Default &

Description
Range Access

VGA_POP_UP_2X_CENTERED_MODE_SCALING: When this bit is set to a one, the

VGA and pop-up data is scaled using pixel doubling in both the horizontal and vertical
direction for use on un-scaled flat panel displays. Setting this bit allows the VGA to run
at higher dot clock frequencies and creates a larger (4x the size) image for better
0b quality on larger displays. It is intended for use in one of the centering modes when not
30 using the internal panel fitting. Do not use it for native VGA modes or when internal
RW panel fitting is used to scale VGA. In the situations where it is used, for 1280 wide or
larger panels this bit should be set. For exactly 1280 wide panels, the Nine-dot disable
bit should also be set. This operation is in addition to the VGA functions that double the
pixels and lines. 0 = VGA display is normal size 1 = VGA and VGA popup data is doubled
in the horizontal and vertical direction.

VGA_PIPE_SELECT: This bit only applies to devices with dual pipe support. For devices
with a single display pipe, this bit will be ignored. For dual pipe devices, this bit
0b determines which pipe is to receive the VGA display data. This must be changed only
29
RW when the VGA display is in the disabled state via the VGA display disable bit or during
the write to enable VGA display. 0 = Selects Assigns the VGA display to Pipe A 1 =
Selects Assigns the VGA display to Pipe B

0b
28:27 RESERVED_: Software must preserve the contents of these bits.
RW

VGA_BORDER_ENABLE: This bit determines if the VGA border areas during VGA
centering modes are included in the active display area and do or do not appear on
integrated TV encoder output and devices that use centering such as on DVO connected
0b flat panel, TV displays, or integrated panels. For use with the internal panel fitting logic,
26 the border if enabled will be scaled along with the pixel data. Setting this bit allows the
RW popup to be positioned overlapping the border area of the image. 0 = VGA Border areas
are not included in the image size calculations for centering only active area. 1 = VGA
Border areas are enabled and is passed to the display pipe for display and used in the
image size calculation for centering modes

VGA_CENTERING_ENABLE: VGA centering modes use the pipe timing generators to

determine the actual display timings. This would normally correspond to the display
panel size and timings. The VGA registers determine the centered VGA image height
and width. The VGA border may or may not be considered in the calculation selected by
the VGA Border Enable bit. For a proper image, the VGA image size should not exceed
the pipe timing generator active rectangle. When using the internal panel fitting logic,
the horizontal image size needs to be less than or equal to 2048 pixels to generate a
proper image. The VGA image will either be centered within the pipe timing rectangle or
0b appear in the upper left corner. Upper left corner centered mode is generally used for
25:24
RW external panel scaling where the DVO stall signal is used and is always used for internal
panel fitting operation. When panel fitter is enabled on the same pipe as VGA this
register setting is ignored and upper left corner centered mode is always selected. When
centering is disabled, the VGA CRTC registers determine the display timing compatible
with legacy VGA devices for driving CRT like devices. 00 = VGA centering is disabled,
VGA operates in Native VGA mode or when driving integrated TV 01 = VGA centering is
enabled, VGA image appears in the center of the larger rectangle 10 = VGA centering is
enabled, VGA image appears in the upper left corner of the larger rectangle 11 = VGA
centering is enabled, VGA image appears in the upper left corner of the larger rectangle
VGA_PALETTE_READ_SELECT: This bit only applies to dual display pipe devices and
0b determines which palette VGA palette read accesses will occur from. 0 = VGA palette
23
RW reads will access Palette A (default). 1 = VGA palette reads will access Palette B VGA
palette reads are reads from I/O address 0x3c9.
VGA_PALETTE_A_WRITE_DISABLE: This determines which palette the VGA palette
0b writes will have as a destination. One or both palettes can be the destination. If both are
22 disabled, writes will not affect the palette RAM contents. 0 = VGA palette writes will
RW update Palette A (default). 1 = VGA palette writes will not update Palette A VGA palette
writes are writes to I/O address 0x3C9h.
DUAL_PIPE_VGA_PALETTE_B_WRITE_DISABLE: This determines which palette
0b the VGA palette writes will have as a destination. One or both palettes can be the
21 destination. If both are disabled, writes will not affect the palette RAM contents. 0 =
RW VGA palette writes will update Palette B (default). 1 = VGA palette writes will not update
Palette B VGA palette writes are writes to I/O address 0x3C9h.

Bay Trail-I SoC

778 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

LEGACY_VGA_8_BIT_PALETTE_ENABLE: This bit only affects reads and writes to

the palette through VGA I/O addresses. In the 6-bit mode, the 8-bits of data are shifted
0b up two bits on the write (upper two bits are lost) and shifted two bits down on the read.
20
RW It provides backward compatibility for original VGA programs (in it s default state) as
well as VESA VBE support for 8-bit palette. It does not affect palette accesses through
the palette register MMIO path. 0 = 6-bit DAC (default). 1 = 8-bit DAC.

0b PALETTE_BYPASS_TEST_MODE: 0 = Pass VGA data through the palette for

19 translation (Normal Operation) 1 = Bypass the palette for allowing testing without
RW loading palette both VGA and popup data will bypass the palette in this mode.
NINE_DOT_DISABLE: Prevents DOS applications from setting the VGA display into a
real 9-dot per character operation mode, instead the device emulates that using 8-dots
per character. This is intended to provide VGA compatibility on DVI type connectors and
0b integrated panels where there would otherwise not be room for the 720 horizontal pixels
18
RW or 1440 pixels when horizontally doubled. The VGA register bit SR01(0) functionality is
disabled. VGA panning control handles the pseudo 9-dot mode when both this bit is set
and SR01(0) is clear. 0 = Enable use of 9-dot enable bit in VGA registers 1 = Ignore the
9-dot per character bit and always use 8

0b
17 RESERVED: Reserved.
RW

0b
16:8 RESERVED__1: Software must preserve the contents of these bits.
RW

BLINK_DUTY_CYCLE: Controls the VGA text mode blink duty cycle relative to the
0b cursor blink duty cycle. 00 = 100% Duty Cycle, Full Cursor Rate (Default) 01 = 25%
7:6
RW Duty Cycle, Cursor Rate 10 = 50% Duty Cycle, Cursor Rate 11 = 75% Duty Cycle,
Cursor Rate
VSYNC_BLINK_RATE: Controls the VGA blink rate in terms of the number of VSYNCs
0b per on/off cycle. These bits are programmed with the (VSYNCs/cycle)/2-1. The proper
5:0
RW programming of this register is determined by the VSYNC rate that the display requires
when in a VGA display mode.

14.11.261 SWF10—Offset 71410h

Software Flag Registers

Access Method
Type: Memory Mapped I/O Register SWF10: [GTTMMADR_LSB + 2BF20h] + 71410h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED_

Bit Default &

Description
Range Access

0b
31:0 RESERVED_: for Video BIOS and Drivers
RW

Bay Trail-I SoC

Datasheet 779
 Graphics, Video and Display

14.11.262 SWF11—Offset 71414h

Software Flag Registers

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) SWF11: [GTTMMADR_LSB + 2BF20h] + 71414h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit Default & RESERVED_ Description

Range Access

0b
31:0 RESERVED_: for Video BIOS and Drivers
RW

14.11.263 SWF12—Offset 71418h

Software Flag Registers

Access Method
Type: Memory Mapped I/O Register
SWF12: [GTTMMADR_LSB + 2BF20h] + 71418h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED_

Bit Default &

Description
Range Access

0b
31:0 RESERVED_: for Video BIOS and Drivers
RW

14.11.264 SWF13—Offset 7141Ch

Software Flag Registers

Access Method

Bay Trail-I SoC

780 Datasheet
Graphics, Video and Display

Type: Memory Mapped I/O Register

SWF13: [GTTMMADR_LSB + 2BF20h] + 7141Ch
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESERVED_
Bit Default &
Description
Range Access

0b
31:0 RESERVED_: for Video BIOS and Drivers
RW

14.11.265 SWF14—Offset 71420h

Software Flag Registers

Access Method
Type: Memory Mapped I/O Register SWF14: [GTTMMADR_LSB + 2BF20h] + 71420h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED_

Bit Default &

Description
Range Access

0b
31:0 RESERVED_: for Video BIOS and Drivers
RW

14.11.266 SWF15—Offset 71424h

Software Flag Registers

Access Method

Bay Trail-I SoC

Datasheet 781
 Graphics, Video and Display

Type: Memory Mapped I/O Register

SWF15: [GTTMMADR_LSB + 2BF20h] + 71424h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESERVED_
Bit Default &
Description
Range Access

0b
31:0 RESERVED_: for Video BIOS and Drivers
RW

14.11.267 SWF16—Offset 71428h

Software Flag Registers

Access Method
Type: Memory Mapped I/O Register SWF16: [GTTMMADR_LSB + 2BF20h] + 71428h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED_

Bit Default &

Description
Range Access

0b
31:0 RESERVED_: for Video BIOS and Drivers
RW

14.11.268 SWF17—Offset 7142Ch

Software Flag Registers

Access Method

Bay Trail-I SoC

782 Datasheet
Graphics, Video and Display

Type: Memory Mapped I/O Register

SWF17: [GTTMMADR_LSB + 2BF20h] + 7142Ch
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESERVED_
Bit Default &
Description
Range Access

0b
31:0 RESERVED_: for Video BIOS and Drivers
RW

14.11.269 SWF18—Offset 71430h

Software Flag Registers

Access Method
Type: Memory Mapped I/O Register SWF18: [GTTMMADR_LSB + 2BF20h] + 71430h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED_

Bit Default &

Description
Range Access

0b
31:0 RESERVED_: for Video BIOS and Drivers
RW

14.11.270 SWF19—Offset 71434h

Software Flag Registers

Access Method

Bay Trail-I SoC

Datasheet 783
 Graphics, Video and Display

Type: Memory Mapped I/O Register

SWF19: [GTTMMADR_LSB + 2BF20h] + 71434h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESERVED_
Bit Default &
Description
Range Access

0b
31:0 RESERVED_: for Video BIOS and Drivers
RW

14.11.271 SWF1A—Offset 71438h

Software Flag Registers

Access Method
Type: Memory Mapped I/O Register SWF1A: [GTTMMADR_LSB + 2BF20h] + 71438h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED_

Bit Default &

Description
Range Access

0b
31:0 RESERVED_: for Video BIOS and Drivers
RW

14.11.272 SWF1B—Offset 7143Ch

Software Flag Registers

Access Method

Bay Trail-I SoC

784 Datasheet
Graphics, Video and Display

Type: Memory Mapped I/O Register

SWF1B: [GTTMMADR_LSB + 2BF20h] + 7143Ch
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESERVED_
Bit Default &
Description
Range Access

0b
31:0 RESERVED_: for Video BIOS and Drivers
RW

14.11.273 SWF1C—Offset 71440h

Software Flag Registers

Access Method
Type: Memory Mapped I/O Register SWF1C: [GTTMMADR_LSB + 2BF20h] + 71440h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED_

Bit Default &

Description
Range Access

0b
31:0 RESERVED_: for Video BIOS and Drivers
RW

14.11.274 SWF1D—Offset 71444h

Software Flag Registers

Access Method

Bay Trail-I SoC

Datasheet 785
 Graphics, Video and Display

Type: Memory Mapped I/O Register

SWF1D: [GTTMMADR_LSB + 2BF20h] + 71444h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESERVED_
Bit Default &
Description
Range Access

0b
31:0 RESERVED_: for Video BIOS and Drivers
RW

14.11.275 SWF1E—Offset 71448h

Software Flag Registers

Access Method
Type: Memory Mapped I/O Register SWF1E: [GTTMMADR_LSB + 2BF20h] + 71448h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED_

Bit Default &

Description
Range Access

0b
31:0 RESERVED_: for Video BIOS and Drivers
RW

14.11.276 SWF1F—Offset 7144Ch

Software Flag Registers

Access Method

Bay Trail-I SoC

786 Datasheet
Graphics, Video and Display

Type: Memory Mapped I/O Register

SWF1F: [GTTMMADR_LSB + 2BF20h] + 7144Ch
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESERVED_
Bit Default &
Description
Range Access

0b
31:0 RESERVED_: for Video BIOS and Drivers
RW

14.11.277 SPACNTR—Offset 72180h

Sprite A Control Register

Access Method
Type: Memory Mapped I/O Register SPACNTR: [GTTMMADR_LSB + 2BF20h] + 72180h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPRITE_A_SOURCE_PIXEL_FORMAT

SPRITE_A_PIPE_SELECT

PIXEL_MULTIPLY

COLOR_CONVERSION_DISABLED

RESERVED_1

RESERVED_2

RESERVED_3
SPRITE_SOURCE_KEY_ENABLE

YUV_FORMAT

YUV_BYTE_ORDER

TILED_SURFACE

SPRITE_A_Z_ORDER
RESERVED
SPRITE_A_ENABLE
SPRITE_A_GAMMA_ENABLE

_180DISPLAY_ROTATION

SPRITE_A_BOTTOM

Bay Trail-I SoC

Datasheet 787
 Graphics, Video and Display

Bit Default &

Description
Range Access

SPRITE_A_ENABLE: This bit will enable or disable the Sprite A. When this bit is set,
the plane will generate pixels for display to be combined by the blender for the target
pipe. When set to zero, memory fetches cease and display is blanked (from this plane)
0b at the next VBLANK event from the pipe that this plane is assigned. At least one of the
31
RW display pipes must be enabled to enable this plane. There is an override for the enable
of this plane in the Pipe Configuration register. This bit only has an effect when the plane
is not trusted. When the plane is marked trusted, this bit will be overridden and the
display disabled when the registers are unlocked. 1 = Enable 0 = Disable
SPRITE_A_GAMMA_ENABLE: There are two gamma adjustments possible in the
Sprite A data path. This bit controls the gamma correction in the display pipe not the
gamma control in this plane. It affects only the pixel data from this display plane. For
0b pixel format of 8-bit indexed, this bit should be set to a one. Gamma correction logic
30 that is contained in the Sprite A logic is disabled by loading the default values into those
RW registers. When this plane is marked as trusted, this bit should always be set to zero to
force the pipe gamma to be always be bypassed. 0 = Sprite A pixel data bypasses the
display pipe gamma correction logic (default). 1 = Sprite A pixel data is gamma
corrected in the pipe gamma correction logic
SPRITE_A_SOURCE_PIXEL_FORMAT: This field selects the pixel format for the
sprite/Sprite A. Pixel formats with an alpha channel should not use source keying.
Before entering the blender, each source format is converted to 10 bits per pixel (details
are described in the intermediate precision for the blender section of the Display
Functions chapter). 0000 = YUV 4:2:2 packed (see byte order below). 0001 = Reserved
0b 0010 = 8-bpp Indexed. 0011 = Reserved. 0100 = Reserved. 0101 = 16-bit BGRX
29:26
RW (5:6:5:0) pixel format (XGA compatible). 0110 = 32-bit BGRX (8:8:8:8) pixel format.
Ignore alpha. 0111 = 32-bit BGRA (8:8:8:8) pixel format with pre-multiplied alpha
channel. 1000 = 32-bit RGBX (10:10:10:2) pixel format. Ignore alpha. 1001 = 32-bit
RGBA (10:10:10:2) pixel format 1010 = Reserved. 1011 = Reserved. 1100 = Reserved.
1101 = Reserved. 1110 = 32-bit RGBX (8:8:8:8) pixel format. Ignore alpha. 1111 = 32-
bit RGBA (8:8:8:8)
0b
25:24 SPRITE_A_PIPE_SELECT: Sprite A always ties to pipe A. Reserved.
RW
0b
23 RESERVED: Reserved.
RW
SPRITE_SOURCE_KEY_ENABLE: When used as a sprite in the 16/32-bpp modes
without alpha this enables source color keying. Sprite pixel values that match (within
range) the key will become transparent. Setting this bit is not allowed when the Sprite A
pixel format includes an alpha channel. [DevBW] Erratum: This bit must always be set
to 0 when Sprite A pixel format is YUV 0 = Sprite source key is disabled (default) 1 =
Sprite source key is enabled. Each sprite has built in source keying enabled/disabled. If
the source keying is disabled and no alpha blending is enabled, the pixels are tagged as
opaque. If sprite source keying is enabled and no alpha blending is enabled, it works as
0b follows: For YUV sprite data, each yuv channel data is compared with the corresponding
22
RW channel s key color Low and High (each channel inrange can be masked out). If all three
channels are in range between the low and high key values, it is considered source
compared. For RGB sprite data, each 24-bit RGB pixel data is compared with the 24-bit
key value (note it only uses the 24-bit Low key value for comparison). Each 24-bit has
to be equal (each bit comparison can also be masked out) for the source compared. If
the sprite source data compare and matches, then the sprite data will be tagged as
transparent when blending with its destination pixel. If the sprite source data does not
compare, then the sprite data will be tagged as opaque when blending with its
destination pixel.
PIXEL_MULTIPLY: This cause the display plane to duplicate lines and pixels sent to
0b the assigned pipe. In the line/pixel doubling mode, the horizontal pixels are doubled and
21:20 lines are sent twice. This is a method of scaling the source image by two (both H and V).
RW 00 = No line/Pixel duplication 01 = Line/Pixel Doubling 10 = Line Doubling only 11 =
Pixel Doubling only
COLOR_CONVERSION_DISABLED: This bit enables or disables the color conversion
logic. Color conversion is intended to be used with the formats that support YUV formats
0b such as the YUV 4:2:2 packed format and x:8:8:8 and 8:8:8:8 formats. Formats such
19
RW as RGB5:5:5 and 5:6:5 do not have YUV versions. 0 = Pixel data is sent through the
conversion logic (only applies to YUV formats) 1 = Pixel data is not sent through the
YUV-)RGB conversion logic.

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788 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

0b YUV_FORMAT: This bit specifies the source YUV format for the YUV to RGB color
18 conversion operation. This field is ignored when source data is RGB. 0 = ITU-R
RW Recommendation BT.601 1 = ITU-R Recommendation BT.709

0b YUV_BYTE_ORDER: This field is used to select the byte order when using YUV 4:2:2
17:16 data formats. For other formats, this field is ignored. 00 = YUYV 01 = UYVY 10 = YVYU
RW 11 = VYUY
_180DISPLAY_ROTATION: This mode causes the display plane to be rotated 180 . In
0b addition to setting this bit, software must also set the base address to the lower right
15
RW corner of the unrotated image and calculate the x, y offset as relative to the lower right
corner. 0 = No rotation 1 = 180 rotation
0b
14:11 RESERVED_1: Reserved.
RW
TILED_SURFACE: This bit indicates that the Sprite A surface data is in tiled memory.
0b The tile pitch is specified in bytes in the DSPCSTRIDE register. Only X tiling is supported
10 for display surfaces. When this bit is set, it affects the hardware interpretation of the
RW DSPCTILEOFF, DSPCLINOFF, and DSPCSURFADDR registers. 0 = Sprite A surface uses
linear memory 1 = Sprite A surface uses X-tiled memory
0b
9:3 RESERVED_2: Write as zero
RW
SPRITE_A_BOTTOM: This bit will force the Sprite A plane to be on the bottom of the Z
0b order. If the plane is marked as trusted, it only applies to the Z order of the trusted
2
RW planes. 0 = Sprite A Z order is determined by the other control bits 1 = Sprite A is
forced to be on the bottom of the Z order.
0b
1 RESERVED_3: Reserved.
RW
SPRITE_A_Z_ORDER: With Sprite A and B z-order, bottom control bits, Sprite A plane
is placed in a specific z-order among other planes. Display Pipe A Z-orders SA zorderSA
bottomSB zorderSB bottomResulting Pipe Z-order (from bottom to top)Source Keying
0b 0000PA SA SB CAPA in Black 1000PA SB SA CAPA in Black 0001SB PA SA CAuse src
0 keying on SB 0011SB PA SA CAuse src keying on SB 1001SB SA PA CAuse src keying on
RW SA 1011SB SA PA CAuse src keying on SA 0100SA PA SB CAuse src keying on SA
1100SA PA SB CAuse src keying on SA 0110SA SB PA CAuse src keying on SB 1110SA
SB PA CAuse src keying on SB 0: Sprite A z-order is disabled 1: Sprite A z-order is
enabled

14.11.278 SPALINOFF—Offset 72184h

Sprite A Linear Offset Register

Access Method
Type: Memory Mapped I/O Register
SPALINOFF: [GTTMMADR_LSB + 2BF20h] + 72184h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

Datasheet 789
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SPRITE_A_OFFSET
Bit Default &
Description
Range Access

SPRITE_A_OFFSET: This register provides the panning offset into the Sprite A plane.
This value is added to the surface address to get the graphics address of the first pixel
0b to be displayed. This offset must be at least pixel aligned. This offset is the difference
31:0 between the address of the upper left pixel to be displayed and the display surface
RW address. When performing 180 rotation, this offset must be the difference between the
last pixel of the last line of the display data in its unrotated orientation and the display
surface address.

14.11.279 SPASTRIDE—Offset 72188h

Sprite A Stride Register

Access Method
Type: Memory Mapped I/O Register
SPASTRIDE: [GTTMMADR_LSB + 2BF20h] + 72188h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPRITE_A_STRIDE

RESERVED

Bit Default &

Description
Range Access

SPRITE_A_STRIDE: This is the stride for Sprite A in bytes. When using linear memory,
this must be 64 byte aligned. When using tiled memory, this must be 256 byte aligned.
This register is updated through a command packet passed through the command
0b stream or writes to this register. When it is desired to update both this and the start
31:6
RW register, the stride register must be written first because the write to the start register is
the trigger that causes the update of both registers on the next VBLANK event. When
using tiled memory, the actual memory buffer stride is limited to a maximum of 16K
bytes.
0b
5:0 RESERVED: Reserved.
RW

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790 Datasheet
Graphics, Video and Display

14.11.280 SPAPOS—Offset 7218Ch

Sprite A Position Register

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) SPAPOS: [GTTMMADR_LSB + 2BF20h] + 7218Ch

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPRITEY_POSITION

RESERVED_1
RESERVED

SPRITE_X_POSITION
Bit Default &
Description
Range Access

0b
31:28 RESERVED: Write as zero
RW
SPRITEY_POSITION: These 12 bits specify the vertical position in lines of the sprite
(upper left corner) relative to the beginning of the active video area. When performing
0b 180 rotation, this field specifies the vertical position of the lower right corner relative to
27:16
RW the end of the active video area in the unrotated orientation. The defined sprite
rectangle must always be completely contained within the displayable area of the screen
image.
0b
15:12 RESERVED_1: Write as zero
RW

SPRITE_X_POSITION: These 12 bits specify the horizontal position in pixels of the

sprite (upper left corner) relative the beginning of the active video area. When
0b performing 180 rotation, this field specifies the horizontal position of the original lower
11:0
RW right corner relative to the original end of the active video area in the unrotated
orientation. The defined sprite rectangle must always be completely contained within
the displayable area of the screen image.

14.11.281 SPASIZE—Offset 72190h

Sprite A Height and Width Register

Access Method
Type: Memory Mapped I/O Register SPASIZE: [GTTMMADR_LSB + 2BF20h] + 72190h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

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Datasheet 791
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESERVED

SPRITE_HEIGHT

SPRITE_WIDTH
RESERVED_1
Bit Default &
Description
Range Access

0b
31:28 RESERVED: Write as zero
RW

0b SPRITE_HEIGHT: This register field is used to specify the height of the sprite in lines.
27:16 The value in the register is the height minus one. The defined sprite rectangle must
RW always be completely contained within the displayable area of the screen image.

0b
15:12 RESERVED_1: Write as zero
RW

SPRITE_WIDTH: This register field is used to specify the width of the sprite in pixels.
This does not have to be the same as the stride but should be less than or equal to the
0b stride (converted to pixels). The value in the register is the width minus one. The
11:0
RW defined sprite rectangle must always be completely contained within the displayable
area of the screen image. The sprite width is limited to even values when YUV source
pixel format is used (actual width, not the width minus one value).

14.11.282 SPAKEYMINVAL—Offset 72194h

Sprite A Color Key Min Value Register

Access Method
Type: Memory Mapped I/O Register SPAKEYMINVAL: [GTTMMADR_LSB + 2BF20h] + 72194h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RED_KEY_MIN_VALUE
RESERVED

GREEN_KEY_MIN_VALUE

BLUE_KEY_MIN_VALUE

Bit Default &

Description
Range Access

0b
31:24 RESERVED: Write as zero
RW

Bay Trail-I SoC

792 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

0b RED_KEY_MIN_VALUE: Specifies the color key minimum value for the sprite red/Cr
23:16
RW channel.

0b GREEN_KEY_MIN_VALUE: Specifies the color key minimum value for the sprite
15:8
RW green/Y channel.

0b BLUE_KEY_MIN_VALUE: Specifies the color key minimum value for the sprite blue/Cb
7:0
RW channel.

14.11.283 SPAKEYMSK—Offset 72198h

Sprite A Color Key Mask Register

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) SPAKEYMSK: [GTTMMADR_LSB + 2BF20h] + 72198h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BLUE_CHANNEL_ENABLE
RESERVED

RED_CHANNEL_ENABLE
GREEN_CHANNEL_ENABLE
Bit Default &
Description
Range Access

0b
31:3 RESERVED: Write as zero
RW
0b RED_CHANNEL_ENABLE: Specifies the source color key enable for the red/Cr
2
RW channel.

0b GREEN_CHANNEL_ENABLE: Specifies the source color key enable for the green/Y
1
RW channel.

0b BLUE_CHANNEL_ENABLE: Specifies the source color key enable for the blue/Cb
0
RW channel

14.11.284 SPASURF—Offset 7219Ch

Sprite A Surface Address Register

Access Method

Bay Trail-I SoC

Datasheet 793
 Graphics, Video and Display

Type: Memory Mapped I/O Register

SPASURF: [GTTMMADR_LSB + 2BF20h] + 7219Ch
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DECRYPTION_REQUEST
SPRITE_A_SURFACE_BASE_ADDRESS

RESERVED

FLIP_SOURCE

RESERVED_1
Bit Default &
Description
Range Access

SPRITE_A_SURFACE_BASE_ADDRESS: This address specifies the surface base

address. When the surface is tiled, panning is specified using (x, y) offsets in the
DSPCTILEOFF register. When the surface is in linear memory, panning is specified using
a linear offset in the DSPCLINOFF register. This address must be 4K aligned. This
0b register can be written directly through software or by command packets in the
31:12 command stream. It represents an offset from the graphics memory aperture base and
RW is mapped to physical pages through the global GTT. If the device supports trusted
operation and this plane is not marked trusted, the memory pages must not be marked
NoDMA . The value in this register is updated through the command streamer during
synchronous flips. [DevBW] and [DevCL]: This address must be 128K aligned for linear
memory.
0b
11:4 RESERVED: : MBZ
RW

0b FLIP_SOURCE: Project: All Default Value: 0b This bit indicates if the source of the flip
3 is CS or BCS so display can send the flip done response to the appropriate destination.
RW ValueNameDescriptionProject 0b CS Flip source is CS All 1b BCS Flip source is BCS All
DECRYPTION_REQUEST: Project: All Default Value: 0b This bit requests decryption to
be enabled for this plane. This request will be qualified with the separate decryption
allow message in order to create the decryption enable. This bit is only allowed to
0b change on a synchronous flip, but once set with a synchronous flip, the bit can remain
2
RW set while using asynchronous flips. This value is loaded into the surface base address
register of the associated plane. Usage must conform to the rules outlined in the plane
surface base address register. ValueNameDescriptionProject 0b Not requested
Decrytpion not requested All 1b Requested Decryption requested All
0b
1:0 RESERVED_1: : MBZ
RW

14.11.285 SPAKEYMAXVAL—Offset 721A0h

Sprite A Color Key Max Value Register

Access Method

Bay Trail-I SoC

794 Datasheet
Graphics, Video and Display

Type: Memory Mapped I/O Register

SPAKEYMAXVAL: [GTTMMADR_LSB + 2BF20h] + 721A0h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RED_KEY_MAX_VALUE

GREEN_KEY_MAX_VALUE
RESERVED

BLUE_KEY_MAX_VALUE
Bit Default &
Description
Range Access

0b
31:24 RESERVED: Write as zero
RW
0b
23:16 RED_KEY_MAX_VALUE: Specifies the color key value for the sprite red/Cr channel.
RW
0b GREEN_KEY_MAX_VALUE: Specifies the color key value for the sprite green/Y
15:8
RW channel.

0b
7:0 BLUE_KEY_MAX_VALUE: Specifies the color key value for the sprite blue/Cb channel.
RW

14.11.286 SPATILEOFF—Offset 721A4h

Sprite A Tiled Offset Register

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) SPATILEOFF: [GTTMMADR_LSB + 2BF20h] + 721A4h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

Datasheet 795
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PLANE_START_Y_POSITION
RESERVED

PLANE_START_X_POSITION
RESERVED_1
Bit Default &
Description
Range Access

0b
31:28 RESERVED: Write as zero
RW
PLANE_START_Y_POSITION: These 12 bits specify the vertical position in lines of the
0b beginning of the active display plane relative to the display surface. When performing
27:16
RW 180 rotation, this field specifies the vertical position of the lower right corner relative to
the start of the active display plane in the unrotated orientation.
0b
15:12 RESERVED_1: Write as zero
RW
PLANE_START_X_POSITION: These 12 bits specify the horizontal offset in pixels of
0b the beginning of the active display plane relative to the display surface. When
11:0
RW performing 180 rotation, this field specifies the horizontal position of the lower right
corner relative to the start of the active display plane in the unrotated orientation.

14.11.287 SPACONTALPHA—Offset 721A8h

Sprite A Constant Alpha Register

Access Method
Type: Memory Mapped I/O Register SPACONTALPHA: [GTTMMADR_LSB + 2BF20h] + 721A8h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

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796 Datasheet
Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENABLE_CONSTANT_ALPHA

RESERVED

SPRITE_A_CONSTANT_ALPHA_VALUE
Bit Default &
Description
Range Access

ENABLE_CONSTANT_ALPHA: Sprite A Sprite constant alpha provides a way to apply

an alpha value to all video sprite pixels. Each pixel color channel is multiplied by the
0b constant alpha before proceeding to the blender. This can be used to create fade out
31
RW effects. This is intended for CE device use where the video sprite might still be used to
generate video output. 0 Sprite A Sprite Constant Alpha is disabled 1 Sprite A Sprite
Constant Alpha is enabled

0b
30:8 RESERVED: : MBZ
RW

SPRITE_A_CONSTANT_ALPHA_VALUE: This field provides the alpha value when

0b constant alpha is enabled. A value of FF means fully opaque and a value of zero means
7:0
RW fully transparent. Values in between those values allow for a blending of sprite with
other surfaces.

14.11.288 SPALIVESURF—Offset 721ACh

Sprite A Live Surface Address Register

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) SPALIVESURF: [GTTMMADR_LSB + 2BF20h] + 721ACh

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

Datasheet 797
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DECRYPTION_REQUEST
SPRITE_A_LIVE_SURFACE_BASE_ADDRESS

RESERVED

FLIP_SOURCE

RESERVED_1
Bit Default &
Description
Range Access

0b SPRITE_A_LIVE_SURFACE_BASE_ADDRESS: This gives the live value of the surface

31:12
RO base address as being currently used for the Sprite A plane.

0b
11:4 RESERVED: : MBZ
RO

0b FLIP_SOURCE: Project: All Default Value: 0b This bit indicates if the source of the flip
3 is CS or BCS so display can send the flip done response to the appropriate destination.
RO ValueNameDescriptionProject 0b CS Flip source is CS All 1b BCS Flip source is BCS All
DECRYPTION_REQUEST: Project: All Default Value: 0b This bit requests decryption to
be enabled for this plane. This request will be qualified with the separate decryption
allow message in order to create the decryption enable. This bit is only allowed to
0b change on a synchronous flip, but once set with a synchronous flip, the bit can remain
2
RO set while using asynchronous flips. This value is loaded into the surface base address
register of the associated plane. Usage must conform to the rules outlined in the plane
surface base address register. ValueNameDescriptionProject 0b Not requested
Decrytpion not requested All 1b Requested Decryption requested All
0b
1:0 RESERVED_1: : MBZ
RO

14.11.289 SPACLRC0—Offset 721D0h

Sprite A Color Correction 0 Register

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) SPACLRC0: [GTTMMADR_LSB + 2BF20h] + 721D0h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 01000000h

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798 Datasheet
Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESERVED

CONTRAST

BRIGHTNESS
RESERVED_1
Bit Default &
Description
Range Access

0b
31:27 RESERVED: Reserved.
RW
CONTRAST: Contrast adjustment applies to YUV data. The Y channel is multiplied by
the value contained in the register field. This signed fixed-point number is in 3i.6f
001000000 format with the first 3 MSBs as the integer value and the last 6 LSBs as the fraction
26:18 b value. The allowed contrast value ranges from 0 to 7.53125 decimal. Bypassing
RW Contrast, for YUV modes and for source data in RGB format, is accomplished by
programming this field to a field value that represents 1.0 decimal or 001.000000 binary
.

0b
17:8 RESERVED_1: Reserved.
RW

BRIGHTNESS: This field provides the brightness adjustment with a 8-bit 2 s

compliment value ranging [-128, +127]. This value is added to the Y value after
0b contrast multiply and before YUV to RGB conversion. A value of zero disables this
7:0 adjustment affect. This 8-bit signed value provides half of the achievable brightness
RW adjustment dynamic range. A full range brightness value would have a programmable
range of [-255, +255]. Bypassing Brightness for YUV formats and for source data in
RGB format, is accomplished by programming this field to 0.

14.11.290 SPACLRC1—Offset 721D4h

Sprite A Color Correction 1 Register

Access Method
Type: Memory Mapped I/O Register
SPACLRC1: [GTTMMADR_LSB + 2BF20h] + 721D4h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000080h

Bay Trail-I SoC

Datasheet 799
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0

RESERVED

SATURATION_AND_HUE_SIN_SH_SIN

RESERVED_1

SATURATION_AND_HUE_COS_SH_COS
Bit Default &
Description
Range Access

0b
31:27 RESERVED: Reserved.
RW

SATURATION_AND_HUE_SIN_SH_SIN: This 11-bit signed fixed-point number is in

2 s compliment (s3i.7f) format with the MSB as the sign, next 3 MSBs as the integer
value and the last 7 LSBs as the fraction value. This field can be used in two modes.
When full range YUV data is operated on, this field contains the saturation value. When
the range-limited YCbCr data is used, software should program this field with the
0b product of the saturation multiplier value multiplied by the CbCr range scale factor
26:16
RW (=128/112). Similar to the contrast field, there is no limit for saturation reduction
saturation = 0 means all pixels become the same value. However, increasing contrast
can only be increased by a factor less than 8. For example, the largest contrast with
value of 0x7.7F can bring input range [0, 32] to a full display color range of [0, 255].
Bypassing Hue, even for source data in RGB format, is accomplished by programming
this field to 0.0.

0b
15:10 RESERVED_1: Reserved.
RW

SATURATION_AND_HUE_COS_SH_COS: This unsigned fixed-point number is in

3i.7f format with the first 3 MSBs be the integer value and the last 7 LSBs be the
fraction value. This field can be used in two modes. When full range YUV data is
operated on, this field contains the saturation value. When the range-limited YCbCr data
001000000 is used, software should program this field with the product of the saturation multiplier
9:0 0b value multiplied by the CbCr range scale factor (=128/112). Similar to the contrast field,
RW there is no limit for saturation reduction saturation = 0 means all pixels become the
same value. However, increasing contrast can only be increased by a factor less than 8.
For example, the largest contrast with value of 0x7.7F can bring input range [0, 32] to a
full display color range of [0, 255]. Bypassing Saturation, even for source data in RGB
format, is accomplished by programming this field to 1.0.

14.11.291 SPAGAMC5—Offset 721E0h

Sprite A Gamma Correction Registers

Access Method
Type: Memory Mapped I/O Register SPAGAMC5: [GTTMMADR_LSB + 2BF20h] + 721E0h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00C0C0C0h

Bay Trail-I SoC

800 Datasheet
Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0

RED_V_CR

BLUE_U_CB
RESERVED

GREEN_Y
Bit Default &
Description
Range Access

0b
31:24 RESERVED: Reserved
RW
11000000b
23:16 RED_V_CR: gamma correction mapping Red to cr
RW
11000000b
15:8 GREEN_Y: gamma correction mapping green to Y
RW
11000000b
7:0 BLUE_U_CB: gamma correction mapping Blue to CB
RW

14.11.292 SPAGAMC4—Offset 721E4h

Sprite A Gamma Correction Registers

Access Method
Type: Memory Mapped I/O Register
SPAGAMC4: [GTTMMADR_LSB + 2BF20h] + 721E4h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00808080h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
GREEN_Y
RESERVED

BLUE_U_CB
RED_V_CR

Bit Default &

Description
Range Access

0b
31:24 RESERVED: Reserved.
RW
10000000b
23:16 RED_V_CR: gamma correction mapping Red to CR
RW
10000000b
15:8 GREEN_Y: gamma correction mapping green to Y
RW
10000000b
7:0 BLUE_U_CB: gamma correction mapping Blue to CB
RW

14.11.293 SPAGAMC3—Offset 721E8h

Sprite A Gamma Correction Registers

Bay Trail-I SoC

Datasheet 801
 Graphics, Video and Display

Access Method
Type: Memory Mapped I/O Register
SPAGAMC3: [GTTMMADR_LSB + 2BF20h] + 721E8h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00404040h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0

BLUE_U_CB
RESERVED

RED_V_CR

GREEN_Y
Bit Default &
Description
Range Access

0b
31:24 RESERVED: Reserved.
RW

01000000b
23:16 RED_V_CR: gamma correction mapping Red to CR
RW

01000000b
15:8 GREEN_Y: gamma correction mapping green to Y
RW

01000000b
7:0 BLUE_U_CB: gamma correction mapping Blue to CB
RW

14.11.294 SPAGAMC2—Offset 721ECh

Sprite A Gamma Correction Registers

Access Method
Type: Memory Mapped I/O Register SPAGAMC2: [GTTMMADR_LSB + 2BF20h] + 721ECh
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00202020h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0
RED_V_CR

BLUE_U_CB
RESERVED

GREEN_Y

Bit Default &

Description
Range Access

0b
31:24 RESERVED: Reserved.
RW
00100000b
23:16 RED_V_CR: gamma correction mapping Red to CR
RW

Bay Trail-I SoC

802 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

00100000b
15:8 GREEN_Y: gamma correction mapping green to Y
RW
00100000b
7:0 BLUE_U_CB: gamma correction mapping Blue to CB
RW

14.11.295 SPAGAMC1—Offset 721F0h

Sprite A Gamma Correction Registers

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) SPAGAMC1: [GTTMMADR_LSB + 2BF20h] + 721F0h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00101010h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0

BLUE_U_CB
RESERVED

RED_V_CR

GREEN_Y

Bit Default &

Description
Range Access

0b
31:24 RESERVED: Reserved.
RW
00010000b
23:16 RED_V_CR: gamma correction mapping Red to CR
RW

00010000b
15:8 GREEN_Y: gamma correction mapping green to Y
RW

00010000b
7:0 BLUE_U_CB: gamma correction mapping Blue to CB
RW

14.11.296 SPAGAMC0—Offset 721F4h

Sprite A Gamma Correction Registers

Access Method
Type: Memory Mapped I/O Register SPAGAMC0: [GTTMMADR_LSB + 2BF20h] + 721F4h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00080808h

Bay Trail-I SoC

Datasheet 803
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0

RED_V_CR

BLUE_U_CB
RESERVED

GREEN_Y
Bit Default &
Description
Range Access

0b
31:24 RESERVED: reserved
RW
00001000b
23:16 RED_V_CR: gamma correction mapping Red to CR
RW
00001000b
15:8 GREEN_Y: gamma correction mapping green to Y
RW
00001000b
7:0 BLUE_U_CB: gamma correction mapping Blue to CB
RW

14.11.297 SPBCNTR—Offset 72280h

Sprite B Control Register

Access Method
Type: Memory Mapped I/O Register
SPBCNTR: [GTTMMADR_LSB + 2BF20h] + 72280h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPRITE_B_ENABLE

SPRITE_B_PIPE_SELECT

SPRITE_SOURCE_KEY_ENABLE

YUV_FORMAT
SPRITE_B_SOURCE_PIXEL_FORMAT

PIXEL_MULTIPLY
SPRITE_B_GAMMA_ENABLE

TILED_SURFACE
_180DISPLAY_ROTATION

SPRITE_B_BOTTOM

SPRITE_B_Z_ORDER
RESERVED

COLOR_CONVERSION_DISABLED

YUV_BYTE_ORDER

RESERVED_1

RESERVED_2

RESERVED_3

Bay Trail-I SoC

804 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

SPRITE_B_ENABLE: This bit will enable or disable the Sprite B. When this bit is set,
the plane will generate pixels for display to be combined by the blender for the target
pipe. When set to zero, memory fetches cease and display is blanked (from this plane)
0b at the next VBLANK event from the pipe that this plane is assigned. At least one of the
31
RW display pipes must be enabled to enable this plane. There is an override for the enable
of this plane in the Pipe Configuration register. This bit only has an effect when the plane
is not trusted. When the plane is marked trusted, this bit will be overridden and the
display disabled when the registers are unlocked. 1 = Enable 0 = Disable
SPRITE_B_GAMMA_ENABLE: There are two gamma adjustments possible in the
Sprite B data path. This bit controls the gamma correction in the display pipe not the
gamma control in this plane. It affects only the pixel data from this display plane. For
0b pixel format of 8-bit indexed, this bit should be set to a one. Gamma correction logic
30 that is contained in the Sprite B logic is disabled by loading the default values into those
RW registers. When this plane is marked as trusted, this bit should always be set to zero to
force the pipe gamma to be always be bypassed. 0 = Sprite B pixel data bypasses the
display pipe gamma correction logic (default). 1 = Sprite B pixel data is gamma
corrected in the pipe gamma correction logic
SPRITE_B_SOURCE_PIXEL_FORMAT: This field selects the pixel format for the
sprite/Sprite B. Pixel formats with an alpha channel should not use source keying.
Before entering the blender, each source format is converted to 10 bits per pixel (details
are described in the intermediate precision for the blender section of the Display
Functions chapter). 0000 = YUV 4:2:2 packed (see byte order below). 0001 = Reserved
0b 0010 = 8-bpp Indexed. 0011 = Reserved. 0100 = Reserved. 0101 = 16-bit BGRX
29:26
RW (5:6:5:0) pixel format (XGA compatible). 0110 = 32-bit BGRX (8:8:8:8) pixel format.
Ignore alpha. 0111 = 32-bit BGRA (8:8:8:8) pixel format with pre-multiplied alpha
channel. 1000 = 32-bit RGBX (10:10:10:2) pixel format. Ignore alpha. 1001 = 32-bit
RGBA (10:10:10:2) pixel format 1010 = Reserved. 1011 = Reserved. 1100 = Reserved.
1101 = Reserved. 1110 = 32-bit RGBX (8:8:8:8) pixel format. Ignore alpha. 1111 = 32-
bit RGBA (8:8:8:8)
0b
25:24 SPRITE_B_PIPE_SELECT: Sprite B always ties to Pipe A. Reserved
RW
0b
23 RESERVED: Reserved.
RW
SPRITE_SOURCE_KEY_ENABLE: When used as a sprite in the 16/32-bpp modes
without alpha this enables source color keying. Sprite pixel values that match (within
0b range) the key will become transparent. Setting this bit is not allowed when the Sprite B
22
RW pixel format includes an alpha channel. [DevBW] Erratum: This bit must always be set
to 0 when Sprite B pixel format is YUV 0 = Sprite source key is disabled (default) 1 =
Sprite source key is enabled.
PIXEL_MULTIPLY: This cause the display plane to duplicate lines and pixels sent to
0b the assigned pipe. In the line/pixel doubling mode, the horizontal pixels are doubled and
21:20 lines are sent twice. This is a method of scaling the source image by two (both H and V).
RW 00 = No line/Pixel duplication 01 = Line/Pixel Doubling 10 = Line Doubling only 11 =
Pixel Doubling only
COLOR_CONVERSION_DISABLED: This bit enables or disables the color conversion
logic. Color conversion is intended to be used with the formats that support YUV formats
0b such as the YUV 4:2:2 packed format and x:8:8:8 and 8:8:8:8 formats. Formats such
19
RW as RGB5:5:5 and 5:6:5 do not have YUV versions. 0 = Pixel data is sent through the
conversion logic (only applies to YUV formats) 1 = Pixel data is not sent through the
YUV-)RGB conversion logic.

0b YUV_FORMAT: This bit specifies the source YUV format for the YUV to RGB color
18 conversion operation. This field is ignored when source data is RGB. 0 = ITU-R
RW Recommendation BT.601 1 = ITU-R Recommendation BT.709

0b YUV_BYTE_ORDER: This field is used to select the byte order when using YUV 4:2:2
17:16 data formats. For other formats, this field is ignored. 00 = YUYV 01 = UYVY 10 = YVYU
RW 11 = VYUY
_180DISPLAY_ROTATION: This mode causes the display plane to be rotated 180 . In
0b addition to setting this bit, software must also set the base address to the lower right
15
RW corner of the unrotated image and calculate the x, y offset as relative to the lower right
corner. 0 = No rotation 1 = 180 rotation

Bay Trail-I SoC

Datasheet 805
 Graphics, Video and Display

Bit Default &

Description
Range Access

0b
14:11 RESERVED_1: Reserved.
RW
TILED_SURFACE: This bit indicates that the Sprite B surface data is in tiled memory.
0b The tile pitch is specified in bytes in the DSPCSTRIDE register. Only X tiling is supported
10 for display surfaces. When this bit is set, it affects the hardware interpretation of the
RW DSPCTILEOFF, DSPCLINOFF, and DSPCSURFADDR registers. 0 = Sprite B surface uses
linear memory 1 = Sprite B surface uses X-tiled memory

0b
9:3 RESERVED_2: Write as zero
RW

SPRITE_B_BOTTOM: This bit will force the Sprite B plane to be on the bottom of the Z
0b order. If the plane is marked as trusted, it only applies to the Z order of the trusted
2
RW planes. 0 = Sprite B Z order is determined by the other control bits 1 = Sprite B is
forced to be on the bottom of the Z order.
0b
1 RESERVED_3: Reserved.
RW
SPRITE_B_Z_ORDER: With Sprite A and B z-order, bottom control bits, Sprite B plane
is placed in a specific z-order among other planes in pipe A. Display Pipe A Z-orders SA
zorderSA bottomSB zorderSB bottomResulting Pipe Z-order (from bottom to top)Source
0b Keying 0000PA SA SB CAPA in Black 1000PA SB SA CAPA in Black 0001SB PA SA CAuse
0 src keying on SB 0011SB PA SA CAuse src keying on SB 1001SB SA PA CAuse src keying
RW on SA 1011SB SA PA CAuse src keying on SA 0100SA PA SB CAuse src keying on SA
1100SA PA SB CAuse src keying on SA 0110SA SB PA CAuse src keying on SB 1110SA
SB PA CAuse src keying on SB 0: Sprite B z-order is disabled 1: Sprite B z-order is
enabled

14.11.298 SPBLINOFF—Offset 72284h

Sprite B Linear Offset Register

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) SPBLINOFF: [GTTMMADR_LSB + 2BF20h] + 72284h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPRITE_B_OFFSET

Bay Trail-I SoC

806 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

SPRITE_B_OFFSET: This register provides the panning offset into the Sprite B plane.
This value is added to the surface address to get the graphics address of the first pixel
0b to be displayed. This offset must be at least pixel aligned. This offset is the difference
31:0 between the address of the upper left pixel to be displayed and the display surface
RW address. When performing 180 rotation, this offset must be the difference between the
last pixel of the last line of the display data in its unrotated orientation and the display
surface address.

14.11.299 SPBSTRIDE—Offset 72288h

Sprite B Stride Register

Access Method
Type: Memory Mapped I/O Register SPBSTRIDE: [GTTMMADR_LSB + 2BF20h] + 72288h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPRITE_B_STRIDE

RESERVED
Bit Default &
Description
Range Access

SPRITE_B_STRIDE: This is the stride for Sprite B in bytes. When using linear memory,
this must be 64 byte aligned. When using tiled memory, this must be 256 byte aligned.
This register is updated through a command packet passed through the command
0b stream or writes to this register. When it is desired to update both this and the start
31:6
RW register, the stride register must be written first because the write to the start register is
the trigger that causes the update of both registers on the next VBLANK event. When
using tiled memory, the actual memory buffer stride is limited to a maximum of 16K
bytes.

0b
5:0 RESERVED: Reserved.
RW

14.11.300 SPBPOS—Offset 7228Ch

Sprite B Position Register

Access Method
Type: Memory Mapped I/O Register SPBPOS: [GTTMMADR_LSB + 2BF20h] + 7228Ch
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

Datasheet 807
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESERVED

SPRITEY_POSITION

SPRITE_X_POSITION
RESERVED_1
Bit Default &
Description
Range Access

0b
31:28 RESERVED: Write as zero
RW
SPRITEY_POSITION: These 12 bits specify the vertical position in lines of the sprite
(upper left corner) relative to the beginning of the active video area. When performing
0b 180 rotation, this field specifies the vertical position of the lower right corner relative to
27:16
RW the end of the active video area in the unrotated orientation. The defined sprite
rectangle must always be completely contained within the displayable area of the screen
image.
0b
15:12 RESERVED_1: Write as zero
RW
SPRITE_X_POSITION: These 12 bits specify the horizontal position in pixels of the
sprite (upper left corner) relative the beginning of the active video area. When
0b performing 180 rotation, this field specifies the horizontal position of the original lower
11:0
RW right corner relative to the original end of the active video area in the unrotated
orientation. The defined sprite rectangle must always be completely contained within
the displayable area of the screen image.

14.11.301 SPBSIZE—Offset 72290h

Sprite B Height and Width Register

Access Method
Type: Memory Mapped I/O Register
SPBSIZE: [GTTMMADR_LSB + 2BF20h] + 72290h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPRITE_WIDTH
RESERVED

RESERVED_1
SPRITE_HEIGHT

Bit Default &

Description
Range Access

0b
31:28 RESERVED: Write as zero
RW

Bay Trail-I SoC

808 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

0b SPRITE_HEIGHT: This register field is used to specify the height of the sprite in lines.
27:16 The value in the register is the height minus one. The defined sprite rectangle must
RW always be completely contained within the displayable area of the screen image.
0b
15:12 RESERVED_1: Write as zero
RW
SPRITE_WIDTH: This register field is used to specify the width of the sprite in pixels.
This does not have to be the same as the stride but should be less than or equal to the
0b stride (converted to pixels). The value in the register is the width minus one. The
11:0
RW defined sprite rectangle must always be completely contained within the displayable
area of the screen image. The sprite width is limited to even values when YUV source
pixel format is used (actual width, not the width minus one value).

14.11.302 SPBKEYMINVAL—Offset 72294h

Sprite B Color Key Min Value Register

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) SPBKEYMINVAL: [GTTMMADR_LSB + 2BF20h] + 72294h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED

RED_KEY_MIN_VALUE

BLUE_KEY_MIN_VALUE
GREEN_KEY_MIN_VALUE

Bit Default &

Description
Range Access

0b
31:24 RESERVED: Write as zero
RW
0b RED_KEY_MIN_VALUE: Specifies the color key minimum value for the sprite red/Cr
23:16
RW channel.

0b GREEN_KEY_MIN_VALUE: Specifies the color key minimum value for the sprite
15:8
RW green/Y channel.

0b BLUE_KEY_MIN_VALUE: Specifies the color key minimum value for the sprite blue/Cb
7:0
RW channel.

14.11.303 SPBKEYMSK—Offset 72298h

Sprite B Color Key Mask Register

Access Method

Bay Trail-I SoC

Datasheet 809
 Graphics, Video and Display

Type: Memory Mapped I/O Register

SPBKEYMSK: [GTTMMADR_LSB + 2BF20h] + 72298h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RED_CHANNEL_ENABLE
RESERVED

GREEN_CHANNEL_ENABLE
BLUE_CHANNEL_ENABLE
Bit Default &
Description
Range Access

0b
31:3 RESERVED: Write as zero
RW
0b RED_CHANNEL_ENABLE: Specifies the source color key enable for the red/Cr
2
RW channel.

0b GREEN_CHANNEL_ENABLE: Specifies the source color key enable for the green/Y
1
RW channel.

0b BLUE_CHANNEL_ENABLE: Specifies the source color key enable for the blue/Cb
0
RW channel

14.11.304 SPBSURF—Offset 7229Ch

Sprite B Surface Address Register

Access Method
Type: Memory Mapped I/O Register SPBSURF: [GTTMMADR_LSB + 2BF20h] + 7229Ch
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

810 Datasheet
Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SPRITE_B_SURFACE_BASE_ADDRESS

DECRYPTION_REQUEST
RESERVED_MBZ

FLIP_SOURCE

RESERVED_MBZ_1
Bit Default &
Description
Range Access

SPRITE_B_SURFACE_BASE_ADDRESS: This address specifies the surface base

address. When the surface is tiled, panning is specified using (x, y) offsets in the
DSPCTILEOFF register. When the surface is in linear memory, panning is specified using
a linear offset in the DSPCLINOFF register. This address must be 4K aligned. This
0b register can be written directly through software or by command packets in the
31:12 command stream. It represents an offset from the graphics memory aperture base and
RW is mapped to physical pages through the global GTT. If the device supports trusted
operation and this plane is not marked trusted, the memory pages must not be marked
NoDMA . The value in this register is updated through the command streamer during
synchronous flips. [DevBW] and [DevCL]: This address must be 128K aligned for linear
memory.
0b
11:4 RESERVED_MBZ: Reserved.
RW

0b FLIP_SOURCE: Project: All Default Value: 0b This bit indicates if the source of the flip
3 is CS or BCS so display can send the flip done response to the appropriate destination.
RW ValueNameDescriptionProject 0b CS Flip source is CS All 1b BCS Flip source is BCS All
DECRYPTION_REQUEST: Project: All Default Value: 0b This bit requests decryption to
be enabled for this plane. This request will be qualified with the separate decryption
allow message in order to create the decryption enable. This bit is only allowed to
0b change on a synchronous flip, but once set with a synchronous flip, the bit can remain
2
RW set while using asynchronous flips. This value is loaded into the surface base address
register of the associated plane. Usage must conform to the rules outlined in the plane
surface base address register. ValueNameDescriptionProject 0b Not requested
Decrytpion not requested All 1b Requested Decryption requested All
0b
1:0 RESERVED_MBZ_1: Reserved.
RW

14.11.305 SPBKEYMAXVAL—Offset 722A0h

Sprite B Color Key Max Value Register

Access Method
Type: Memory Mapped I/O Register
SPBKEYMAXVAL: [GTTMMADR_LSB + 2BF20h] + 722A0h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

Datasheet 811
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RED_KEY_MAX_VALUE
RESERVED

GREEN_KEY_MAX_VALUE

BLUE_KEY_MAX_VALUE
Bit Default &
Description
Range Access

0b
31:24 RESERVED: Write as zero
RW
0b
23:16 RED_KEY_MAX_VALUE: Specifies the color key value for the sprite red/Cr channel.
RW
0b GREEN_KEY_MAX_VALUE: Specifies the color key value for the sprite green/Y
15:8
RW channel.

0b
7:0 BLUE_KEY_MAX_VALUE: Specifies the color key value for the sprite blue/Cb channel.
RW

14.11.306 SPBTILEOFF—Offset 722A4h

Sprite B Tiled Offset Register

Access Method
Type: Memory Mapped I/O Register
SPBTILEOFF: [GTTMMADR_LSB + 2BF20h] + 722A4h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PLANE_START_Y_POSITION

PLANE_START_X_POSITION
RESERVED

RESERVED_1

Bit Default &

Description
Range Access

0b
31:28 RESERVED: Write as zero
RW

Bay Trail-I SoC

812 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

PLANE_START_Y_POSITION: These 12 bits specify the vertical position in lines of the

0b beginning of the active display plane relative to the display surface. When performing
27:16
RW 180 rotation, this field specifies the vertical position of the lower right corner relative to
the start of the active display plane in the unrotated orientation.
0b
15:12 RESERVED_1: Write as zero
RW
PLANE_START_X_POSITION: These 12 bits specify the horizontal offset in pixels of
0b the beginning of the active display plane relative to the display surface. When
11:0
RW performing 180 rotation, this field specifies the horizontal position of the lower right
corner relative to the start of the active display plane in the unrotated orientation.

14.11.307 SPBCONTALPHA—Offset 722A8h

Sprite B Constant Alpha Register

Access Method
Type: Memory Mapped I/O Register
SPBCONTALPHA: [GTTMMADR_LSB + 2BF20h] + 722A8h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SPRITE_B_CONSTANT_ALPHA_VALUE
ENABLE_CONSTANT_ALPHA

RESERVED

Bit Default &

Description
Range Access

ENABLE_CONSTANT_ALPHA: Sprite B Sprite constant alpha provides a way to apply

an alpha value to all video sprite pixels. Each pixel color channel is multiplied by the
0b constant alpha before proceeding to the blender. This can be used to create fade out
31
RW effects. This is intended for CE device use where the video sprite might still be used to
generate video output. 0 Sprite B Sprite Constant Alpha is disabled 1 Sprite B Sprite
Constant Alpha is enabled
0b
30:8 RESERVED: : MBZ
RW
SPRITE_B_CONSTANT_ALPHA_VALUE: This field provides the alpha value when
0b constant alpha is enabled. A value of FF means fully opaque and a value of zero means
7:0
RW fully transparent. Values in between those values allow for a blending of sprite with
other surfaces.

Bay Trail-I SoC

Datasheet 813
 Graphics, Video and Display

14.11.308 SPBLIVESURF—Offset 722ACh

Sprite B Live Surface Address Register

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) SPBLIVESURF: [GTTMMADR_LSB + 2BF20h] + 722ACh

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0
SPRITE_B_LIVE_SURFACE_BASE_ADDRESS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESERVED_MBZ

RESERVED_MBZ_1
FLIP_SOURCE
DECRYPTION_REQUEST
Bit Default &
Description
Range Access

0b SPRITE_B_LIVE_SURFACE_BASE_ADDRESS: This gives the live value of the surface

31:12
RO base address as being currently used for Sprite B plane.

0b
11:4 RESERVED_MBZ: Reserved.
RO

0b FLIP_SOURCE: Project: All Default Value: 0b This bit indicates if the source of the flip
3 is CS or BCS so display can send the flip done response to the appropriate destination.
RO ValueNameDescriptionProject 0b CS Flip source is CS All 1b BCS Flip source is BCS All
DECRYPTION_REQUEST: Project: All Default Value: 0b This bit requests decryption to
be enabled for this plane. This request will be qualified with the separate decryption
allow message in order to create the decryption enable. This bit is only allowed to
0b change on a synchronous flip, but once set with a synchronous flip, the bit can remain
2
RO set while using asynchronous flips. This value is loaded into the surface base address
register of the associated plane. Usage must conform to the rules outlined in the plane
surface base address register. ValueNameDescriptionProject 0b Not requested
Decrytpion not requested All 1b Requested Decryption requested All

0b
1:0 RESERVED_MBZ_1: Reserved.
RO

14.11.309 SPBCLRC0—Offset 722D0h

Sprite B Color Correction 0 Register

Access Method

Bay Trail-I SoC

814 Datasheet
Graphics, Video and Display

Type: Memory Mapped I/O Register

SPBCLRC0: [GTTMMADR_LSB + 2BF20h] + 722D0h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 01000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED

CONTRAST

BRIGHTNESS
RESERVED_1
Bit Default &
Description
Range Access

0b
31:27 RESERVED: Reserved.
RW
CONTRAST: Contrast adjustment applies to YUV data. The Y channel is multiplied by
the value contained in the register field. This signed fixed-point number is in 3i.6f
001000000 format with the first 3 MSBs as the integer value and the last 6 LSBs as the fraction
26:18 b value. The allowed contrast value ranges from 0 to 7.53125 decimal. Bypassing
RW Contrast, for YUV modes and for source data in RGB format, is accomplished by
programming this field to a field value that represents 1.0 decimal or 001.000000 binary
.

0b
17:8 RESERVED_1: Reserved.
RW

BRIGHTNESS: This field provides the brightness adjustment with a 8-bit 2 s

compliment value ranging [-128, +127]. This value is added to the Y value after
0b contrast multiply and before YUV to RGB conversion. A value of zero disables this
7:0 adjustment affect. This 8-bit signed value provides half of the achievable brightness
RW adjustment dynamic range. A full range brightness value would have a programmable
range of [-255, +255]. Bypassing Brightness for YUV formats and for source data in
RGB format, is accomplished by programming this field to 0.

14.11.310 SPBCLRC1—Offset 722D4h

Sprite B Color Correction 1 Register

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) SPBCLRC1: [GTTMMADR_LSB + 2BF20h] + 722D4h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000080h

Bay Trail-I SoC

Datasheet 815
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0

RESERVED

SATURATION_AND_HUE_SIN_SH_SIN

RESERVED_1

SATURATION_AND_HUE_COS_SH_COS
Bit Default &
Description
Range Access

0b
31:27 RESERVED: Reserved.
RW

SATURATION_AND_HUE_SIN_SH_SIN: This 11-bit signed fixed-point number is in

2 s compliment (s3i.7f) format with the MSB as the sign, next 3 MSBs as the integer
value and the last 7 LSBs as the fraction value. This field can be used in two modes.
When full range YUV data is operated on, this field contains the saturation value. When
the range-limited YCbCr data is used, software should program this field with the
0b product of the saturation multiplier value multiplied by the CbCr range scale factor
26:16
RW (=128/112). Similar to the contrast field, there is no limit for saturation reduction
saturation = 0 means all pixels become the same value. However, increasing contrast
can only be increased by a factor less than 8. For example, the largest contrast with
value of 0x7.7F can bring input range [0, 32] to a full display color range of [0, 255].
Bypassing Hue, even for source data in RGB format, is accomplished by programming
this field to 0.0.

0b
15:10 RESERVED_1: Reserved.
RW

SATURATION_AND_HUE_COS_SH_COS: This unsigned fixed-point number is in

3i.7f format with the first 3 MSBs be the integer value and the last 7 LSBs be the
fraction value. This field can be used in two modes. When full range YUV data is
operated on, this field contains the saturation value. When the range-limited YCbCr data
001000000 is used, software should program this field with the product of the saturation multiplier
9:0 0b value multiplied by the CbCr range scale factor (=128/112). Similar to the contrast field,
RW there is no limit for saturation reduction saturation = 0 means all pixels become the
same value. However, increasing contrast can only be increased by a factor less than 8.
For example, the largest contrast with value of 0x7.7F can bring input range [0, 32] to a
full display color range of [0, 255]. Bypassing Saturation, even for source data in RGB
format, is accomplished by programming this field to 1.0.

14.11.311 SPBGAMC5—Offset 722E0h

Sprite B Gamma Correction Registers

Access Method
Type: Memory Mapped I/O Register SPBGAMC5: [GTTMMADR_LSB + 2BF20h] + 722E0h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00C0C0C0h

Bay Trail-I SoC

816 Datasheet
Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0

RED_V_CR

BLUE_U_CB
RESERVED

GREEN_Y
Bit Default &
Description
Range Access

0b
31:24 RESERVED: reserved
RW
11000000b
23:16 RED_V_CR: gamma correction mapping Red to CR
RW
11000000b
15:8 GREEN_Y: gamma correction mapping green to Y
RW
11000000b
7:0 BLUE_U_CB: gamma correction mapping Blue to CB
RW

14.11.312 SPBGAMC4—Offset 722E4h

Sprite B Gamma Correction Registers

Access Method
Type: Memory Mapped I/O Register
SPBGAMC4: [GTTMMADR_LSB + 2BF20h] + 722E4h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00808080h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
GREEN_Y
RESERVED

BLUE_U_CB
RED_V_CR

Bit Default &

Description
Range Access

0b
31:24 RESERVED: reserved
RW
10000000b
23:16 RED_V_CR: gamma correction mapping Red to CR
RW
10000000b
15:8 GREEN_Y: gamma correction mapping Green to Y
RW
10000000b
7:0 BLUE_U_CB: gamma correction mapping CB
RW

14.11.313 SPBGAMC3—Offset 722E8h

Sprite B Gamma Correction Registers

Bay Trail-I SoC

Datasheet 817
 Graphics, Video and Display

Access Method
Type: Memory Mapped I/O Register
SPBGAMC3: [GTTMMADR_LSB + 2BF20h] + 722E8h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00404040h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0

BLUE_U_CB
RESERVED

RED_V_CR

GREEN_Y
Bit Default &
Description
Range Access

0b
31:24 RESERVED: reserved
RW

01000000b
23:16 RED_V_CR: gamma correction mapping red to CR
RW

01000000b
15:8 GREEN_Y: gamma correction mapping Green to Y
RW

01000000b
7:0 BLUE_U_CB: gamma correction mapping Blue to CB
RW

14.11.314 SPBGAMC2—Offset 722ECh

Sprite B Gamma Correction Registers

Access Method
Type: Memory Mapped I/O Register SPBGAMC2: [GTTMMADR_LSB + 2BF20h] + 722ECh
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00202020h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0
RED_V_CR

BLUE_U_CB
RESERVED

GREEN_Y

Bit Default &

Description
Range Access

0b
31:24 RESERVED: reserved
RW
00100000b
23:16 RED_V_CR: gamma correction mapping Red to CR
RW

Bay Trail-I SoC

818 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

00100000b
15:8 GREEN_Y: gamma correction mapping green to Y
RW
00100000b
7:0 BLUE_U_CB: gamma correction mapping blue to CB
RW

14.11.315 SPBGAMC1—Offset 722F0h

Sprite B Gamma Correction Registers

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) SPBGAMC1: [GTTMMADR_LSB + 2BF20h] + 722F0h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00101010h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0

BLUE_U_CB
RESERVED

RED_V_CR

GREEN_Y

Bit Default &

Description
Range Access

0b
31:24 RESERVED: reserved
RW
00010000b
23:16 RED_V_CR: gamma correction mapping red to CR
RW

00010000b
15:8 GREEN_Y: gamma correction mapping green to Y
RW

00010000b
7:0 BLUE_U_CB: gamma correction mapping blue to CB
RW

14.11.316 SPBGAMC0—Offset 722F4h

Sprite B Gamma Correction Registers

Access Method
Type: Memory Mapped I/O Register SPBGAMC0: [GTTMMADR_LSB + 2BF20h] + 722F4h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00080808h

Bay Trail-I SoC

Datasheet 819
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0

RED_V_CR

BLUE_U_CB
RESERVED

GREEN_Y
Bit Default &
Description
Range Access

0b
31:24 RESERVED: reserved
RW
00001000b
23:16 RED_V_CR: gamma correction mapping Red to CR
RW
00001000b
15:8 GREEN_Y: gamma correction mapping green to Y
RW
00001000b
7:0 BLUE_U_CB: gamma correction mapping blue to CB
RW

14.11.317 SPCCNTR—Offset 72380h

Sprite C Control Register

Access Method
Type: Memory Mapped I/O Register
SPCCNTR: [GTTMMADR_LSB + 2BF20h] + 72380h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPRITE_C_SOURCE_PIXEL_FORMAT

SPRITE_SOURCE_KEY_ENABLE

PIXEL_MULTIPLY

YUV_FORMAT
SPRITE_C_PIPE_SELECT

TILED_SURFACE

SPRITE_C_BOTTOM
SPRITE_C_ENABLE

_180DISPLAY_ROTATION
SPRITE_C_GAMMA_ENABLE

RESERVED

COLOR_CONVERSION_DISABLED

YUV_BYTE_ORDER

RESERVED_1

RESERVED_2

RESERVED_3
SPRITE_C_Z_ORDER

Bay Trail-I SoC

820 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

SPRITE_C_ENABLE: This bit will enable or disable the Sprite C. When this bit is set,
the plane will generate pixels for display to be combined by the blender for the target
pipe. When set to zero, memory fetches cease and display is blanked (from this plane)
0b at the next VBLANK event from the pipe that this plane is assigned. At least one of the
31
RW display pipes must be enabled to enable this plane. There is an override for the enable
of this plane in the Pipe Configuration register. This bit only has an effect when the plane
is not trusted. When the plane is marked trusted, this bit will be overridden and the
display disabled when the registers are unlocked. 1 = Enable 0 = Disable
SPRITE_C_GAMMA_ENABLE: There are two gamma adjustments possible in the
Sprite C data path. This bit controls the gamma correction in the display pipe not the
gamma control in this plane. It affects only the pixel data from this display plane. For
0b pixel format of 8-bit indexed, this bit should be set to a one. Gamma correction logic
30 that is contained in the Sprite C logic is disabled by loading the default values into those
RW registers. When this plane is marked as trusted, this bit should always be set to zero to
force the pipe gamma to be always be bypassed. 0 = Sprite C pixel data bypasses the
display pipe gamma correction logic (default). 1 = Sprite C pixel data is gamma
corrected in the pipe gamma correction logic
SPRITE_C_SOURCE_PIXEL_FORMAT: This field selects the pixel format for the
sprite/Sprite C. Pixel formats with an alpha channel should not use source keying.
Before entering the blender, each source format is converted to 10 bits per pixel (details
are described in the intermediate precision for the blender section of the Display
Functions chapter). 0000 = YUV 4:2:2 packed (see byte order below). 0001 = Reserved
0b 0010 = 8-bpp Indexed. 0011 = Reserved. 0100 = Reserved. 0101 = 16-bit BGRX
29:26
RW (5:6:5:0) pixel format (XGA compatible). 0110 = 32-bit BGRX (8:8:8:8) pixel format.
Ignore alpha. 0111 = 32-bit BGRA (8:8:8:8) pixel format with pre-multiplied alpha
channel. 1000 = 32-bit RGBX (10:10:10:2) pixel format. Ignore alpha. 1001 = 32-bit
RGBA (10:10:10:2) pixel format 1010 = Reserved. 1011 = Reserved. 1100 = Reserved.
1101 = Reserved. 1110 = 32-bit RGBX (8:8:8:8) pixel format. Ignore alpha. 1111 = 32-
bit RGBA (8:8:8:8)
0b
25:24 SPRITE_C_PIPE_SELECT: Sprite C always ties to Pipe B Reserved.
RW
0b
23 RESERVED: Reserved.
RW
SPRITE_SOURCE_KEY_ENABLE: When used as a sprite in the 16/32-bpp modes
without alpha this enables source color keying. Sprite pixel values that match (within
0b range) the key will become transparent. Setting this bit is not allowed when the Sprite C
22
RW pixel format includes an alpha channel. [DevBW] Erratum: This bit must always be set
to 0 when Sprite C pixel format is YUV 0 = Sprite source key is disabled (default) 1 =
Sprite source key is enabled.
PIXEL_MULTIPLY: This cause the display plane to duplicate lines and pixels sent to
0b the assigned pipe. In the line/pixel doubling mode, the horizontal pixels are doubled and
21:20 lines are sent twice. This is a method of scaling the source image by two (both H and V).
RW 00 = No line/Pixel duplication 01 = Line/Pixel Doubling 10 = Line Doubling only 11 =
Pixel Doubling only
COLOR_CONVERSION_DISABLED: This bit enables or disables the color conversion
logic. Color conversion is intended to be used with the formats that support YUV formats
0b such as the YUV 4:2:2 packed format and x:8:8:8 and 8:8:8:8 formats. Formats such
19
RW as RGB5:5:5 and 5:6:5 do not have YUV versions. 0 = Pixel data is sent through the
conversion logic (only applies to YUV formats) 1 = Pixel data is not sent through the
YUV-)RGB conversion logic.

0b YUV_FORMAT: This bit specifies the source YUV format for the YUV to RGB color
18 conversion operation. This field is ignored when source data is RGB. 0 = ITU-R
RW Recommendation BT.601 1 = ITU-R Recommendation BT.709

0b YUV_BYTE_ORDER: This field is used to select the byte order when using YUV 4:2:2
17:16 data formats. For other formats, this field is ignored. 00 = YUYV 01 = UYVY 10 = YVYU
RW 11 = VYUY
_180DISPLAY_ROTATION: This mode causes the display plane to be rotated 180 . In
0b addition to setting this bit, software must also set the base address to the lower right
15
RW corner of the unrotated image and calculate the x, y offset as relative to the lower right
corner. 0 = No rotation 1 = 180 rotation

Bay Trail-I SoC

Datasheet 821
 Graphics, Video and Display

Bit Default &

Description
Range Access

0b
14:11 RESERVED_1: Reserved.
RW
TILED_SURFACE: This bit indicates that the Sprite C surface data is in tiled memory.
0b The tile pitch is specified in bytes in the DSPCSTRIDE register. Only X tiling is supported
10 for display surfaces. When this bit is set, it affects the hardware interpretation of the
RW DSPCTILEOFF, DSPCLINOFF, and DSPCSURFADDR registers. 0 = Sprite C surface uses
linear memory 1 = Sprite C surface uses X-tiled memory

0b
9:3 RESERVED_2: Write as zero
RW

SPRITE_C_BOTTOM: This bit will force the Sprite C plane to be on the bottom of the Z
0b order. If the plane is marked as trusted, it only applies to the Z order of the trusted
2
RW planes. 0 = Sprite C Z order is determined by the other control bits 1 = Sprite C is
forced to be on the bottom of the Z order.
0b
1 RESERVED_3: Reserved.
RW
SPRITE_C_Z_ORDER: With Sprite C and D z-order, bottom control bits, Sprite C plane
is placed in a specific z-order among other planes in pipe B. Display Pipe B Z-orders SC
zorderSC bottomSD zorderSD bottomResulting Pipe Z-order (from bottom to top)Source
Keying 0000PB SC SD CBPB in Black 1000PB SD SC CBPB in Black 0001SD PB SC CBuse
0b src keying on SD 0011SD PB SC CBuse src keying on SD 1001SD SC PB CBuse src
0
RW keying on SC 1011SD SC PB CBuse src keying on SC 0100SC PB SD CBuse src keying on
SC 1100SC PB SD CBuse src keying on SC 0110SC SD PB CBuse src keying on SD
1110SC SD PB CBuse src keying on SD 0101Not Allowed 0111Not Allowed 1101Not
Allowed 1111Not Allowed 1010Not Allowed 1011Not Allowed 0: Sprite C z-order is
disabled 1: Sprite C z-order is enabled

14.11.318 SPCLINOFF—Offset 72384h

Sprite C Linear Offset Register

Access Method
Type: Memory Mapped I/O Register SPCLINOFF: [GTTMMADR_LSB + 2BF20h] + 72384h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPRITE_C_OFFSET

Bay Trail-I SoC

822 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

SPRITE_C_OFFSET: This register provides the panning offset into the Sprite C plane.
This value is added to the surface address to get the graphics address of the first pixel
0b to be displayed. This offset must be at least pixel aligned. This offset is the difference
31:0 between the address of the upper left pixel to be displayed and the display surface
RW address. When performing 180 rotation, this offset must be the difference between the
last pixel of the last line of the display data in its unrotated orientation and the display
surface address.

14.11.319 SPCSTRIDE—Offset 72388h

Sprite C Stride Register

Access Method
Type: Memory Mapped I/O Register SPCSTRIDE: [GTTMMADR_LSB + 2BF20h] + 72388h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPRITE_C_STRIDE

RESERVED
Bit Default &
Description
Range Access

SPRITE_C_STRIDE: This is the stride for Sprite C in bytes. When using linear memory,
this must be 64 byte aligned. When using tiled memory, this must be 256 byte aligned.
This register is updated through a command packet passed through the command
0b stream or writes to this register. When it is desired to update both this and the start
31:6
RW register, the stride register must be written first because the write to the start register is
the trigger that causes the update of both registers on the next VBLANK event. When
using tiled memory, the actual memory buffer stride is limited to a maximum of 16K
bytes.

0b
5:0 RESERVED: Reserved.
RW

14.11.320 SPCPOS—Offset 7238Ch

Sprite C Position Register

Access Method
Type: Memory Mapped I/O Register SPCPOS: [GTTMMADR_LSB + 2BF20h] + 7238Ch
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

Datasheet 823
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESERVED

SPRITEY_POSITION

SPRITE_X_POSITION
RESERVED_1
Bit Default &
Description
Range Access

0b
31:28 RESERVED: Write as zero
RW
SPRITEY_POSITION: These 12 bits specify the vertical position in lines of the sprite
(upper left corner) relative to the beginning of the active video area. When performing
0b 180 rotation, this field specifies the vertical position of the lower right corner relative to
27:16
RW the end of the active video area in the unrotated orientation. The defined sprite
rectangle must always be completely contained within the displayable area of the screen
image.
0b
15:12 RESERVED_1: Write as zero
RW
SPRITE_X_POSITION: These 12 bits specify the horizontal position in pixels of the
sprite (upper left corner) relative the beginning of the active video area. When
0b performing 180 rotation, this field specifies the horizontal position of the original lower
11:0
RW right corner relative to the original end of the active video area in the unrotated
orientation. The defined sprite rectangle must always be completely contained within
the displayable area of the screen image.

14.11.321 SPCSIZE—Offset 72390h

Sprite C Height and Width Register

Access Method
Type: Memory Mapped I/O Register
SPCSIZE: [GTTMMADR_LSB + 2BF20h] + 72390h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPRITE_WIDTH
RESERVED

RESERVED_1
SPRITE_HEIGHT

Bit Default &

Description
Range Access

0b
31:28 RESERVED: Write as zero
RW

Bay Trail-I SoC

824 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

0b SPRITE_HEIGHT: This register field is used to specify the height of the sprite in lines.
27:16 The value in the register is the height minus one. The defined sprite rectangle must
RW always be completely contained within the displayable area of the screen image.
0b
15:12 RESERVED_1: Write as zero
RW
SPRITE_WIDTH: This register field is used to specify the width of the sprite in pixels.
This does not have to be the same as the stride but should be less than or equal to the
0b stride (converted to pixels). The value in the register is the width minus one. The
11:0
RW defined sprite rectangle must always be completely contained within the displayable
area of the screen image. The sprite width is limited to even values when YUV source
pixel format is used (actual width, not the width minus one value).

14.11.322 SPCKEYMINVAL—Offset 72394h

Sprite C Color Key Min Value Register

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) SPCKEYMINVAL: [GTTMMADR_LSB + 2BF20h] + 72394h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED

RED_KEY_MIN_VALUE

BLUE_KEY_MIN_VALUE
GREEN_KEY_MIN_VALUE

Bit Default &

Description
Range Access

0b
31:24 RESERVED: Write as zero
RW
0b RED_KEY_MIN_VALUE: Specifies the color key minimum value for the sprite red/Cr
23:16
RW channel.

0b GREEN_KEY_MIN_VALUE: Specifies the color key minimum value for the sprite
15:8
RW green/Y channel.

0b BLUE_KEY_MIN_VALUE: Specifies the color key minimum value for the sprite blue/Cb
7:0
RW channel.

14.11.323 SPCKEYMSK—Offset 72398h

Sprite C Color Key Mask Register

Access Method

Bay Trail-I SoC

Datasheet 825
 Graphics, Video and Display

Type: Memory Mapped I/O Register

SPCKEYMSK: [GTTMMADR_LSB + 2BF20h] + 72398h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RED_CHANNEL_ENABLE
RESERVED

GREEN_CHANNEL_ENABLE
BLUE_CHANNEL_ENABLE
Bit Default &
Description
Range Access

0b
31:3 RESERVED: Write as zero
RW
0b RED_CHANNEL_ENABLE: Specifies the source color key enable for the red/Cr
2
RW channel.

0b GREEN_CHANNEL_ENABLE: Specifies the source color key enable for the green/Y
1
RW channel.

0b BLUE_CHANNEL_ENABLE: Specifies the source color key enable for the blue/Cb
0
RW channel

14.11.324 SPCSURF—Offset 7239Ch

Sprite C Surface Address Register

Access Method
Type: Memory Mapped I/O Register SPCSURF: [GTTMMADR_LSB + 2BF20h] + 7239Ch
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

826 Datasheet
Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DECRYPTION_REQUEST
RESERVED

FLIP_SOURCE
SPRITE_C_SURFACE_BASE_ADDRESS

RESERVED_1
Bit Default &
Description
Range Access

SPRITE_C_SURFACE_BASE_ADDRESS: This address specifies the surface base

address. When the surface is tiled, panning is specified using (x, y) offsets in the
DSPCTILEOFF register. When the surface is in linear memory, panning is specified using
a linear offset in the DSPCLINOFF register. This address must be 4K aligned. This
0b register can be written directly through software or by command packets in the
31:12 command stream. It represents an offset from the graphics memory aperture base and
RW is mapped to physical pages through the global GTT. If the device supports trusted
operation and this plane is not marked trusted, the memory pages must not be marked
NoDMA . The value in this register is updated through the command streamer during
synchronous flips. [DevBW] and [DevCL]: This address must be 128K aligned for linear
memory.
0b
11:4 RESERVED: : MBZ
RW

0b FLIP_SOURCE: Project: All Default Value: 0b This bit indicates if the source of the flip
3 is CS or BCS so display can send the flip done response to the appropriate destination.
RW ValueNameDescriptionProject 0b CS Flip source is CS All 1b BCS Flip source is BCS All
DECRYPTION_REQUEST: Project: All Default Value: 0b This bit requests decryption to
be enabled for this plane. This request will be qualified with the separate decryption
allow message in order to create the decryption enable. This bit is only allowed to
0b change on a synchronous flip, but once set with a synchronous flip, the bit can remain
2
RW set while using asynchronous flips. This value is loaded into the surface base address
register of the associated plane. Usage must conform to the rules outlined in the plane
surface base address register. ValueNameDescriptionProject 0b Not requested
Decrytpion not requested All 1b Requested Decryption requested All
0b
1:0 RESERVED_1: : MBZ
RW

14.11.325 SPCKEYMAXVAL—Offset 723A0h

Sprite C Color Key Max Value Register

Access Method
Type: Memory Mapped I/O Register
SPCKEYMAXVAL: [GTTMMADR_LSB + 2BF20h] + 723A0h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

Datasheet 827
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RED_KEY_MAX_VALUE
RESERVED

GREEN_KEY_MAX_VALUE

BLUE_KEY_MAX_VALUE
Bit Default &
Description
Range Access

0b
31:24 RESERVED: Write as zero
RW
0b
23:16 RED_KEY_MAX_VALUE: Specifies the color key value for the sprite red/Cr channel.
RW
0b GREEN_KEY_MAX_VALUE: Specifies the color key value for the sprite green/Y
15:8
RW channel.

0b
7:0 BLUE_KEY_MAX_VALUE: Specifies the color key value for the Sprite Clue/Cb channel.
RW

14.11.326 SPCTILEOFF—Offset 723A4h

Sprite C Tiled Offset Register

Access Method
Type: Memory Mapped I/O Register
SPCTILEOFF: [GTTMMADR_LSB + 2BF20h] + 723A4h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PLANE_START_Y_POSITION

PLANE_START_X_POSITION
RESERVED

RESERVED_1

Bit Default &

Description
Range Access

0b
31:28 RESERVED: Write as zero
RW

Bay Trail-I SoC

828 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

PLANE_START_Y_POSITION: These 12 bits specify the vertical position in lines of the

0b beginning of the active display plane relative to the display surface. When performing
27:16
RW 180 rotation, this field specifies the vertical position of the lower right corner relative to
the start of the active display plane in the unrotated orientation.
0b
15:12 RESERVED_1: Write as zero
RW
PLANE_START_X_POSITION: These 12 bits specify the horizontal offset in pixels of
0b the beginning of the active display plane relative to the display surface. When
11:0
RW performing 180 rotation, this field specifies the horizontal position of the lower right
corner relative to the start of the active display plane in the unrotated orientation.

14.11.327 SPCCONTALPHA—Offset 723A8h

Sprite C Constant Alpha Register

Access Method
Type: Memory Mapped I/O Register
SPCCONTALPHA: [GTTMMADR_LSB + 2BF20h] + 723A8h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENABLE_CONSTANT_ALPHA

RESERVED

SPRITE_C_CONSTANT_ALPHA_VALUE

Bit Default &

Description
Range Access

ENABLE_CONSTANT_ALPHA: Sprite C Sprite constant alpha provides a way to apply

an alpha value to all video sprite pixels. Each pixel color channel is multiplied by the
0b constant alpha before proceeding to the blender. This can be used to create fade out
31
RW effects. This is intended for CE device use where the video sprite might still be used to
generate video output. 0 Sprite C Sprite Constant Alpha is disabled 1 Sprite C Sprite
Constant Alpha is enabled
0b
30:8 RESERVED: : MBZ
RW
SPRITE_C_CONSTANT_ALPHA_VALUE: This field provides the alpha value when
0b constant alpha is enabled. A value of FF means fully opaque and a value of zero means
7:0
RW fully transparent. Values in between those values allow for a blending of sprite with
other surfaces.

Bay Trail-I SoC

Datasheet 829
 Graphics, Video and Display

14.11.328 SPCLIVESURF—Offset 723ACh

Sprite C Live Surface Address Register

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) SPCLIVESURF: [GTTMMADR_LSB + 2BF20h] + 723ACh

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0
SPRITE_C_LIVE_SURFACE_BASE_ADDRESS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESERVED_1
RESERVED

FLIP_SOURCE
DECRYPTION_REQUEST
Bit Default &
Description
Range Access

0b SPRITE_C_LIVE_SURFACE_BASE_ADDRESS: This gives the live value of the surface

31:12
RO base address as being currently used for Sprite C.

0b
11:4 RESERVED: : MBZ
RO

0b FLIP_SOURCE: Project: All Default Value: 0b This bit indicates if the source of the flip
3 is CS or BCS so display can send the flip done response to the appropriate destination.
RO ValueNameDescriptionProject 0b CS Flip source is CS All 1b BCS Flip source is BCS All
DECRYPTION_REQUEST: Project: All Default Value: 0b This bit requests decryption to
be enabled for this plane. This request will be qualified with the separate decryption
allow message in order to create the decryption enable. This bit is only allowed to
0b change on a synchronous flip, but once set with a synchronous flip, the bit can remain
2
RO set while using asynchronous flips. This value is loaded into the surface base address
register of the associated plane. Usage must conform to the rules outlined in the plane
surface base address register. ValueNameDescriptionProject 0b Not requested
Decrytpion not requested All 1b Requested Decryption requested All

0b
1:0 RESERVED_1: : MBZ
RO

14.11.329 SPCCLRC0—Offset 723D0h

Sprite C Color Correction 0 Register

Access Method

Bay Trail-I SoC

830 Datasheet
Graphics, Video and Display

Type: Memory Mapped I/O Register

SPCCLRC0: [GTTMMADR_LSB + 2BF20h] + 723D0h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 01000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED

CONTRAST

BRIGHTNESS
RESERVED_1
Bit Default &
Description
Range Access

0b
31:27 RESERVED: Reserved.
RW
CONTRAST: Contrast adjustment applies to YUV data. The Y channel is multiplied by
the value contained in the register field. This signed fixed-point number is in 3i.6f
001000000 format with the first 3 MSBs as the integer value and the last 6 LSBs as the fraction
26:18 b value. The allowed contrast value ranges from 0 to 7.53125 decimal. Bypassing
RW Contrast, for YUV modes and for source data in RGB format, is accomplished by
programming this field to a field value that represents 1.0 decimal or 001.000000 binary
.

0b
17:8 RESERVED_1: Reserved.
RW

BRIGHTNESS: This field provides the brightness adjustment with a 8-bit 2 s

compliment value ranging [-128, +127]. This value is added to the Y value after
0b contrast multiply and before YUV to RGB conversion. A value of zero disables this
7:0 adjustment affect. This 8-bit signed value provides half of the achievable brightness
RW adjustment dynamic range. A full range brightness value would have a programmable
range of [-255, +255]. Bypassing Brightness for YUV formats and for source data in
RGB format, is accomplished by programming this field to 0.

14.11.330 SPCCLRC1—Offset 723D4h

Sprite C Color Correction 1 Register

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) SPCCLRC1: [GTTMMADR_LSB + 2BF20h] + 723D4h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000080h

Bay Trail-I SoC

Datasheet 831
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0

RESERVED

SATURATION_AND_HUE_SIN_SH_SIN

RESERVED_1

SATURATION_AND_HUE_COS_SH_COS
Bit Default &
Description
Range Access

0b
31:27 RESERVED: Reserved.
RW

SATURATION_AND_HUE_SIN_SH_SIN: This 11-bit signed fixed-point number is in

2 s compliment (s3i.7f) format with the MSB as the sign, next 3 MSBs as the integer
value and the last 7 LSBs as the fraction value. This field can be used in two modes.
When full range YUV data is operated on, this field contains the saturation value. When
the range-limited YCbCr data is used, software should program this field with the
0b product of the saturation multiplier value multiplied by the CbCr range scale factor
26:16
RW (=128/112). Similar to the contrast field, there is no limit for saturation reduction
saturation = 0 means all pixels become the same value. However, increasing contrast
can only be increased by a factor less than 8. For example, the largest contrast with
value of 0x7.7F can bring input range [0, 32] to a full display color range of [0, 255].
Bypassing Hue, even for source data in RGB format, is accomplished by programming
this field to 0.0.

0b
15:10 RESERVED_1: Reserved.
RW

SATURATION_AND_HUE_COS_SH_COS: This unsigned fixed-point number is in

3i.7f format with the first 3 MSBs be the integer value and the last 7 LSBs be the
fraction value. This field can be used in two modes. When full range YUV data is
operated on, this field contains the saturation value. When the range-limited YCbCr data
001000000 is used, software should program this field with the product of the saturation multiplier
9:0 0b value multiplied by the CbCr range scale factor (=128/112). Similar to the contrast field,
RW there is no limit for saturation reduction saturation = 0 means all pixels become the
same value. However, increasing contrast can only be increased by a factor less than 8.
For example, the largest contrast with value of 0x7.7F can bring input range [0, 32] to a
full display color range of [0, 255]. Bypassing Saturation, even for source data in RGB
format, is accomplished by programming this field to 1.0.

14.11.331 SPCGAMC5—Offset 723E0h

Sprite C Gamma Correction Registers

Access Method
Type: Memory Mapped I/O Register SPCGAMC5: [GTTMMADR_LSB + 2BF20h] + 723E0h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00C0C0C0h

Bay Trail-I SoC

832 Datasheet
Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0

RED_V_CR

BLUE_U_CB
RESERVED

GREEN_Y
Bit Default &
Description
Range Access

0b
31:24 RESERVED: reserved
RW
11000000b
23:16 RED_V_CR: gamma correction mapping Red to CR
RW
11000000b
15:8 GREEN_Y: gamma correction mapping Green to Y
RW
11000000b
7:0 BLUE_U_CB: gamma correction mapping Blue to CB
RW

14.11.332 SPCGAMC4—Offset 723E4h

Sprite C Gamma Correction Registers

Access Method
Type: Memory Mapped I/O Register
SPCGAMC4: [GTTMMADR_LSB + 2BF20h] + 723E4h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00808080h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
GREEN_Y
RESERVED

BLUE_U_CB
RED_V_CR

Bit Default &

Description
Range Access

0b
31:24 RESERVED: reserved
RW
10000000b
23:16 RED_V_CR: gamma correction mapping Red to CR
RW
10000000b
15:8 GREEN_Y: gamma correction mapping Green to Y
RW
10000000b
7:0 BLUE_U_CB: gamma correction mapping CB
RW

14.11.333 SPCGAMC3—Offset 723E8h

Sprite C Gamma Correction Registers

Bay Trail-I SoC

Datasheet 833
 Graphics, Video and Display

Access Method
Type: Memory Mapped I/O Register
SPCGAMC3: [GTTMMADR_LSB + 2BF20h] + 723E8h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00404040h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0

BLUE_U_CB
RESERVED

RED_V_CR

GREEN_Y
Bit Default &
Description
Range Access

0b
31:24 RESERVED: reserved
RW

01000000b
23:16 RED_V_CR: gamma correction mapping Red to CR
RW

01000000b
15:8 GREEN_Y: gamma correction mapping Green to Y
RW

01000000b
7:0 BLUE_U_CB: gamma correction mapping Blue to CB
RW

14.11.334 SPCGAMC2—Offset 723ECh

Sprite C Gamma Correction Registers

Access Method
Type: Memory Mapped I/O Register SPCGAMC2: [GTTMMADR_LSB + 2BF20h] + 723ECh
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00202020h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0
RED_V_CR

BLUE_U_CB
RESERVED

GREEN_Y

Bit Default &

Description
Range Access

0b
31:24 RESERVED: reserved
RW
00100000b
23:16 RED_V_CR: gamma correction mapping Red to CR
RW

Bay Trail-I SoC

834 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

00100000b
15:8 GREEN_Y: gamma correction mapping green to Y
RW
00100000b
7:0 BLUE_U_CB: gamma correction mapping Blue to CB
RW

14.11.335 SPCGAMC1—Offset 723F0h

Sprite C Gamma Correction Registers

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) SPCGAMC1: [GTTMMADR_LSB + 2BF20h] + 723F0h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00101010h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0

BLUE_U_CB
RESERVED

RED_V_CR

GREEN_Y

Bit Default &

Description
Range Access

0b
31:24 RESERVED: reserved
RW
00010000b
23:16 RED_V_CR: gamma correction mapping Red to CR
RW

00010000b
15:8 GREEN_Y: gamma correction mapping Green to Y
RW

00010000b
7:0 BLUE_U_CB: gamma correction mapping Blue to CB
RW

14.11.336 SPCGAMC0—Offset 723F4h

Sprite C Gamma Correction Registers

Access Method
Type: Memory Mapped I/O Register SPCGAMC0: [GTTMMADR_LSB + 2BF20h] + 723F4h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00080808h

Bay Trail-I SoC

Datasheet 835
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0

RED_V_CR

BLUE_U_CB
RESERVED

GREEN_Y
Bit Default &
Description
Range Access

0b
31:24 RESERVED: reserved
RW
00001000b
23:16 RED_V_CR: gamma correction mapping Red to CR
RW
00001000b
15:8 GREEN_Y: gamma correction mapping Green to Y
RW
00001000b
7:0 BLUE_U_CB: gamma correction mapping Blue to CB
RW

14.11.337 SWF30—Offset 72414h

Software Flag Registers

Access Method
Type: Memory Mapped I/O Register
SWF30: [GTTMMADR_LSB + 2BF20h] + 72414h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED_

Bit Default &

Description
Range Access

0b
31:0 RESERVED_: for Video BIOS and Drivers
RW

14.11.338 SWF31—Offset 72418h

Software Flag Registers

Access Method

Bay Trail-I SoC

836 Datasheet
Graphics, Video and Display

Type: Memory Mapped I/O Register

SWF31: [GTTMMADR_LSB + 2BF20h] + 72418h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESERVED_
Bit Default &
Description
Range Access

0b
31:0 RESERVED_: for Video BIOS and Drivers
RW

14.11.339 SWF32—Offset 7241Ch

Software Flag Registers

Access Method
Type: Memory Mapped I/O Register SWF32: [GTTMMADR_LSB + 2BF20h] + 7241Ch
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED_

Bit Default &

Description
Range Access

0b
31:0 RESERVED_: for Video BIOS and Drivers
RW

14.11.340 SPDCNTR—Offset 72480h

Sprite D Control Register

Access Method

Bay Trail-I SoC

Datasheet 837
 Graphics, Video and Display

Type: Memory Mapped I/O Register

SPDCNTR: [GTTMMADR_LSB + 2BF20h] + 72480h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPRITE_D_GAMMA_ENABLE

SPRITE_D_PIPE_SELECT

COLOR_CONVERSION_DISABLED

YUV_BYTE_ORDER

SPRITE_D_Z_ORDER
SPRITE_D_ENABLE

RESERVED

PIXEL_MULTIPLY

YUV_FORMAT

TILED_SURFACE
SPRITE_SOURCE_KEY_ENABLE

_180DISPLAY_ROTATION
SPRITE_D_SOURCE_PIXEL_FORMAT

RESERVED_1

RESERVED_2

SPRITE_D_BOTTOM
RESERVED_3
Bit Default &
Description
Range Access

SPRITE_D_ENABLE: This bit will enable or disable the Sprite D. When this bit is set,
the plane will generate pixels for display to be combined by the blender for the target
pipe. When set to zero, memory fetches cease and display is blanked (from this plane)
0b at the next VBLANK event from the pipe that this plane is assigned. At least one of the
31
RW display pipes must be enabled to enable this plane. There is an override for the enable
of this plane in the Pipe Configuration register. This bit only has an effect when the plane
is not trusted. When the plane is marked trusted, this bit will be overridden and the
display disabled when the registers are unlocked. 1 = Enable 0 = Disable
SPRITE_D_GAMMA_ENABLE: There are two gamma adjustments possible in the
Sprite D data path. This bit controls the gamma correction in the display pipe not the
gamma control in this plane. It affects only the pixel data from this display plane. For
0b pixel format of 8-bit indexed, this bit should be set to a one. Gamma correction logic
30 that is contained in the Sprite D logic is disabled by loading the default values into those
RW registers. When this plane is marked as trusted, this bit should always be set to zero to
force the pipe gamma to be always be bypassed. 0 = Sprite D pixel data bypasses the
display pipe gamma correction logic (default). 1 = Sprite D pixel data is gamma
corrected in the pipe gamma correction logic
SPRITE_D_SOURCE_PIXEL_FORMAT: This field selects the pixel format for the
sprite/Sprite D. Pixel formats with an alpha channel should not use source keying.
Before entering the blender, each source format is converted to 10 bits per pixel (details
are described in the intermediate precision for the blender section of the Display
Functions chapter). 0000 = YUV 4:2:2 packed (see byte order below). 0001 = Reserved
0b 0010 = 8-bpp Indexed. 0011 = Reserved. 0100 = Reserved. 0101 = 16-bit BGRX
29:26
RW (5:6:5:0) pixel format (XGA compatible). 0110 = 32-bit BGRX (8:8:8:8) pixel format.
Ignore alpha. 0111 = 32-bit BGRA (8:8:8:8) pixel format with pre-multiplied alpha
channel. 1000 = 32-bit RGBX (10:10:10:2) pixel format. Ignore alpha. 1001 = 32-bit
RGBA (10:10:10:2) pixel format 1010 = Reserved. 1011 = Reserved. 1100 = Reserved.
1101 = Reserved. 1110 = 32-bit RGBX (8:8:8:8) pixel format. Ignore alpha. 1111 = 32-
bit RGBA (8:8:8:8)
0b
25:24 SPRITE_D_PIPE_SELECT: Sprite D always ties to Pipe B. Reserved.
RW
0b
23 RESERVED: Reserved.
RW

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838 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

SPRITE_SOURCE_KEY_ENABLE: When used as a sprite in the 16/32-bpp modes

without alpha this enables source color keying. Sprite pixel values that match (within
0b range) the key will become transparent. Setting this bit is not allowed when the Sprite D
22
RW pixel format includes an alpha channel. [DevBW] Erratum: This bit must always be set
to 0 when Sprite D pixel format is YUV 0 = Sprite source key is disabled (default) 1 =
Sprite source key is enabled.
PIXEL_MULTIPLY: This cause the display plane to duplicate lines and pixels sent to
0b the assigned pipe. In the line/pixel doubling mode, the horizontal pixels are doubled and
21:20 lines are sent twice. This is a method of scaling the source image by two (both H and V).
RW 00 = No line/Pixel duplication 01 = Line/Pixel Doubling 10 = Line Doubling only 11 =
Pixel Doubling only

COLOR_CONVERSION_DISABLED: This bit enables or disables the color conversion

logic. Color conversion is intended to be used with the formats that support YUV formats
0b such as the YUV 4:2:2 packed format and x:8:8:8 and 8:8:8:8 formats. Formats such
19
RW as RGB5:5:5 and 5:6:5 do not have YUV versions. 0 = Pixel data is sent through the
conversion logic (only applies to YUV formats) 1 = Pixel data is not sent through the
YUV-)RGB conversion logic.

0b YUV_FORMAT: This bit specifies the source YUV format for the YUV to RGB color
18 conversion operation. This field is ignored when source data is RGB. 0 = ITU-R
RW Recommendation BT.601 1 = ITU-R Recommendation BT.709

0b YUV_BYTE_ORDER: This field is used to select the byte order when using YUV 4:2:2
17:16 data formats. For other formats, this field is ignored. 00 = YUYV 01 = UYVY 10 = YVYU
RW 11 = VYUY

_180DISPLAY_ROTATION: This mode causes the display plane to be rotated 180 . In

0b addition to setting this bit, software must also set the base address to the lower right
15
RW corner of the unrotated image and calculate the x, y offset as relative to the lower right
corner. 0 = No rotation 1 = 180 rotation
0b
14:11 RESERVED_1: Reserved.
RW
TILED_SURFACE: This bit indicates that the Sprite D surface data is in tiled memory.
0b The tile pitch is specified in bytes in the DSPCSTRIDE register. Only X tiling is supported
10 for display surfaces. When this bit is set, it affects the hardware interpretation of the
RW DSPCTILEOFF, DSPCLINOFF, and DSPCSURFADDR registers. 0 = Sprite D surface uses
linear memory 1 = Sprite D surface uses X-tiled memory

0b
9:3 RESERVED_2: Write as zero
RW

SPRITE_D_BOTTOM: This bit will force the Sprite D plane to be on the bottom of the Z
0b order. If the plane is marked as trusted, it only applies to the Z order of the trusted
2
RW planes. 0 = Sprite D Z order is determined by the other control bits 1 = Sprite D is
forced to be on the bottom of the Z order.
0b
1 RESERVED_3: Reserved.
RW
SPRITE_D_Z_ORDER: With Sprite C and D z-order, bottom control bits, Sprite D plane
is placed in a specific z-order among other planes in pipe B. Display Pipe B Z-orders SC
zorderSC bottomSD zorderSD bottomResulting Pipe Z-order (from bottom to top)Source
Keying 0000PB SC SD CBPB in Black 1000PB SD SC CBPB in Black 0001SD PB SC CBuse
0b src keying on SD 0011SD PB SC CBuse src keying on SD 1001SD SC PB CBuse src
0
RW keying on SC 1011SD SC PB CBuse src keying on SC 0100SC PB SD CBuse src keying on
SC 1100SC PB SD CBuse src keying on SC 0110SC SD PB CBuse src keying on SD
1110SC SD PB CBuse src keying on SD 0101Not Allowed 0111Not Allowed 1101Not
Allowed 1111Not Allowed 1010Not Allowed 1011Not Allowed 0: Sprite D z-order is
disabled 1: Sprite D z-order is enabled

14.11.341 SPDLINOFF—Offset 72484h

Sprite D Linear Offset Register

Access Method

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Datasheet 839
 Graphics, Video and Display

Type: Memory Mapped I/O Register

SPDLINOFF: [GTTMMADR_LSB + 2BF20h] + 72484h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SPRITE_D_OFFSET
Bit Default &
Description
Range Access

SPRITE_D_OFFSET: This register provides the panning offset into the Sprite D plane.
This value is added to the surface address to get the graphics address of the first pixel
0b to be displayed. This offset must be at least pixel aligned. This offset is the difference
31:0 between the address of the upper left pixel to be displayed and the display surface
RW address. When performing 180 rotation, this offset must be the difference between the
last pixel of the last line of the display data in its unrotated orientation and the display
surface address.

14.11.342 SPDSTRIDE—Offset 72488h

Sprite D Stride Register

Access Method
Type: Memory Mapped I/O Register
SPDSTRIDE: [GTTMMADR_LSB + 2BF20h] + 72488h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPRITE_D_STRIDE

RESERVED

Bay Trail-I SoC

840 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

SPRITE_D_STRIDE: This is the stride for Sprite D in bytes. When using linear memory,
this must be 64 byte aligned. When using tiled memory, this must be 256 byte aligned.
This register is updated through a command packet passed through the command
0b stream or writes to this register. When it is desired to update both this and the start
31:6
RW register, the stride register must be written first because the write to the start register is
the trigger that causes the update of both registers on the next VBLANK event. When
using tiled memory, the actual memory buffer stride is limited to a maximum of 16K
bytes.
0b
5:0 RESERVED: Reserved.
RW

14.11.343 SPDPOS—Offset 7248Ch

Sprite D Position Register

Access Method
Type: Memory Mapped I/O Register
SPDPOS: [GTTMMADR_LSB + 2BF20h] + 7248Ch
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED

SPRITEY_POSITION

SPRITE_X_POSITION
RESERVED_1

Bit Default &

Description
Range Access

0b
31:28 RESERVED: Write as zero
RW
SPRITEY_POSITION: These 12 bits specify the vertical position in lines of the sprite
(upper left corner) relative to the beginning of the active video area. When performing
0b 180 rotation, this field specifies the vertical position of the lower right corner relative to
27:16
RW the end of the active video area in the unrotated orientation. The defined sprite
rectangle must always be completely contained within the displayable area of the screen
image.
0b
15:12 RESERVED_1: Write as zero
RW
SPRITE_X_POSITION: These 12 bits specify the horizontal position in pixels of the
sprite (upper left corner) relative the beginning of the active video area. When
0b performing 180 rotation, this field specifies the horizontal position of the original lower
11:0
RW right corner relative to the original end of the active video area in the unrotated
orientation. The defined sprite rectangle must always be completely contained within
the displayable area of the screen image.

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Datasheet 841
 Graphics, Video and Display

14.11.344 SPDSIZE—Offset 72490h

Sprite D Height and Width Register

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) SPDSIZE: [GTTMMADR_LSB + 2BF20h] + 72490h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SPRITE_WIDTH
RESERVED_1
RESERVED

SPRITE_HEIGHT

Bit Default &

Description
Range Access

0b
31:28 RESERVED: Write as zero
RW

0b SPRITE_HEIGHT: This register field is used to specify the height of the sprite in lines.
27:16 The value in the register is the height minus one. The defined sprite rectangle must
RW always be completely contained within the displayable area of the screen image.
0b
15:12 RESERVED_1: Write as zero
RW
SPRITE_WIDTH: This register field is used to specify the width of the sprite in pixels.
This does not have to be the same as the stride but should be less than or equal to the
0b stride (converted to pixels). The value in the register is the width minus one. The
11:0
RW defined sprite rectangle must always be completely contained within the displayable
area of the screen image. The sprite width is limited to even values when YUV source
pixel format is used (actual width, not the width minus one value).

14.11.345 SPDKEYMINVAL—Offset 72494h

Sprite D Color Key Min Value Register

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) SPDKEYMINVAL: [GTTMMADR_LSB + 2BF20h] + 72494h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

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842 Datasheet
Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESERVED

RED_KEY_MIN_VALUE

GREEN_KEY_MIN_VALUE

BLUE_KEY_MIN_VALUE
Bit Default &
Description
Range Access

0b
31:24 RESERVED: Write as zero
RW
0b RED_KEY_MIN_VALUE: Specifies the color key minimum value for the sprite red/Cr
23:16
RW channel.

0b GREEN_KEY_MIN_VALUE: Specifies the color key minimum value for the sprite
15:8
RW green/Y channel.

0b BLUE_KEY_MIN_VALUE: Specifies the color key minimum value for the sprite blue/Cb
7:0
RW channel.

14.11.346 SPDKEYMSK—Offset 72498h

Sprite D Color Key Mask Register

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) SPDKEYMSK: [GTTMMADR_LSB + 2BF20h] + 72498h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RED_CHANNEL_ENABLE
RESERVED

GREEN_CHANNEL_ENABLE
BLUE_CHANNEL_ENABLE

Bit Default &

Description
Range Access

0b
31:3 RESERVED: Write as zero
RW

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Datasheet 843
 Graphics, Video and Display

Bit Default &

Description
Range Access

0b RED_CHANNEL_ENABLE: Specifies the source color key enable for the red/Cr
2
RW channel.

0b GREEN_CHANNEL_ENABLE: Specifies the source color key enable for the green/Y
1
RW channel.

0b BLUE_CHANNEL_ENABLE: Specifies the source color key enable for the blue/Cb
0
RW channel

14.11.347 SPDSURF—Offset 7249Ch

Sprite D Surface Address Register

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) SPDSURF: [GTTMMADR_LSB + 2BF20h] + 7249Ch

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPRITE_D_SURFACE_BASE_ADDRESS

RESERVED

FLIP_SOURCE
DECRYPTION_REQUEST

RESERVED_1

Bit Default &

Description
Range Access

SPRITE_D_SURFACE_BASE_ADDRESS: This address specifies the surface base

address. When the surface is tiled, panning is specified using (x, y) offsets in the
DSPCTILEOFF register. When the surface is in linear memory, panning is specified using
a linear offset in the DSPCLINOFF register. This address must be 4K aligned. This
0b register can be written directly through software or by command packets in the
31:12 command stream. It represents an offset from the graphics memory aperture base and
RW is mapped to physical pages through the global GTT. If the device supports trusted
operation and this plane is not marked trusted, the memory pages must not be marked
NoDMA . The value in this register is updated through the command streamer during
synchronous flips. [DevBW] and [DevCL]: This address must be 128K aligned for linear
memory.
0b
11:4 RESERVED: : MBZ
RW

0b FLIP_SOURCE: Project: All Default Value: 0b This bit indicates if the source of the flip
3 is CS or BCS so display can send the flip done response to the appropriate destination.
RW ValueNameDescriptionProject 0b CS Flip source is CS All 1b BCS Flip source is BCS All

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844 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

DECRYPTION_REQUEST: Project: All Default Value: 0b This bit requests decryption to

be enabled for this plane. This request will be qualified with the separate decryption
allow message in order to create the decryption enable. This bit is only allowed to
0b change on a synchronous flip, but once set with a synchronous flip, the bit can remain
2
RW set while using asynchronous flips. This value is loaded into the surface base address
register of the associated plane. Usage must conform to the rules outlined in the plane
surface base address register. ValueNameDescriptionProject 0b Not requested
Decrytpion not requested All 1b Requested Decryption requested All

0b
1:0 RESERVED_1: : MBZ
RW

14.11.348 SPDKEYMAXVAL—Offset 724A0h

Sprite D Color Key Max Value Register

Access Method
Type: Memory Mapped I/O Register
SPDKEYMAXVAL: [GTTMMADR_LSB + 2BF20h] + 724A0h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RED_KEY_MAX_VALUE

BLUE_KEY_MAX_VALUE
RESERVED

GREEN_KEY_MAX_VALUE

Bit Default &

Description
Range Access

0b
31:24 RESERVED: Write as zero
RW
0b
23:16 RED_KEY_MAX_VALUE: Specifies the color key value for the sprite red/Cr channel.
RW
0b GREEN_KEY_MAX_VALUE: Specifies the color key value for the sprite green/Y
15:8
RW channel.

0b
7:0 BLUE_KEY_MAX_VALUE: Specifies the color key value for the Sprite blue/Cb channel.
RW

14.11.349 SPDTILEOFF—Offset 724A4h

Sprite D Tiled Offset Register

Access Method

Bay Trail-I SoC

Datasheet 845
 Graphics, Video and Display

Type: Memory Mapped I/O Register

SPDTILEOFF: [GTTMMADR_LSB + 2BF20h] + 724A4h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED

PLANE_START_Y_POSITION

PLANE_START_X_POSITION
RESERVED_1
Bit Default &
Description
Range Access

0b
31:28 RESERVED: Write as zero
RW
PLANE_START_Y_POSITION: These 12 bits specify the vertical position in lines of the
0b beginning of the active display plane relative to the display surface. When performing
27:16
RW 180 rotation, this field specifies the vertical position of the lower right corner relative to
the start of the active display plane in the unrotated orientation.
0b
15:12 RESERVED_1: Write as zero
RW
PLANE_START_X_POSITION: These 12 bits specify the horizontal offset in pixels of
0b the beginning of the active display plane relative to the display surface. When
11:0
RW performing 180 rotation, this field specifies the horizontal position of the lower right
corner relative to the start of the active display plane in the unrotated orientation.

14.11.350 SPDCONTALPHA—Offset 724A8h

Sprite D Constant Alpha Register

Access Method
Type: Memory Mapped I/O Register
SPDCONTALPHA: [GTTMMADR_LSB + 2BF20h] + 724A8h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

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846 Datasheet
Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENABLE_CONSTANT_ALPHA

SPRITE_D_CONSTANT_ALPHA_VALUE
Bit Default & RESERVED
Description
Range Access

ENABLE_CONSTANT_ALPHA: Sprite D Sprite constant alpha provides a way to apply

an alpha value to all video sprite pixels. Each pixel color channel is multiplied by the
0b constant alpha before proceeding to the blender. This can be used to create fade out
31
RW effects. This is intended for CE device use where the video sprite might still be used to
generate video output. 0 Sprite D Constant Alpha is disabled 1 Sprite D Constant Alpha
is enabled

0b
30:8 RESERVED: : MBZ
RW

SPRITE_D_CONSTANT_ALPHA_VALUE: This field provides the alpha value when

0b constant alpha is enabled. A value of FF means fully opaque and a value of zero means
7:0
RW fully transparent. Values in between those values allow for a blending of sprite with
other surfaces.

14.11.351 SPDLIVESURF—Offset 724ACh

Sprite D Live Surface Address Register

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) SPDLIVESURF: [GTTMMADR_LSB + 2BF20h] + 724ACh

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

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Datasheet 847
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DECRYPTION_REQUEST
SPRITE_D_LIVE_SURFACE_BASE_ADDRESS

RESERVED

FLIP_SOURCE

RESERVED_1
Bit Default &
Description
Range Access

0b SPRITE_D_LIVE_SURFACE_BASE_ADDRESS: This gives the live value of the

31:12
RO surface base address as being currently used for Sprite D

0b
11:4 RESERVED: : MBZ
RO

0b FLIP_SOURCE: Project: All Default Value: 0b This bit indicates if the source of the flip
3 is CS or BCS so display can send the flip done response to the appropriate destination.
RO ValueNameDescriptionProject 0b CS Flip source is CS All 1b BCS Flip source is BCS All
DECRYPTION_REQUEST: Project: All Default Value: 0b This bit requests decryption to
be enabled for this plane. This request will be qualified with the separate decryption
allow message in order to create the decryption enable. This bit is only allowed to
0b change on a synchronous flip, but once set with a synchronous flip, the bit can remain
2
RO set while using asynchronous flips. This value is loaded into the surface base address
register of the associated plane. Usage must conform to the rules outlined in the plane
surface base address register. ValueNameDescriptionProject 0b Not requested
Decrytpion not requested All 1b Requested Decryption requested All
0b
1:0 RESERVED_1: : MBZ
RO

14.11.352 SPDCLRC0—Offset 724D0h

Sprite D Color Correction 0 Register

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) SPDCLRC0: [GTTMMADR_LSB + 2BF20h] + 724D0h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 01000000h

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848 Datasheet
Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESERVED

CONTRAST

BRIGHTNESS
RESERVED_1
Bit Default &
Description
Range Access

0b
31:27 RESERVED: Reserved.
RW
CONTRAST: Contrast adjustment applies to YUV data. The Y channel is multiplied by
the value contained in the register field. This signed fixed-point number is in 3i.6f
001000000 format with the first 3 MSBs as the integer value and the last 6 LSBs as the fraction
26:18 b value. The allowed contrast value ranges from 0 to 7.53125 decimal. Bypassing
RW Contrast, for YUV modes and for source data in RGB format, is accomplished by
programming this field to a field value that represents 1.0 decimal or 001.000000 binary
.

0b
17:8 RESERVED_1: Reserved.
RW

BRIGHTNESS: This field provides the brightness adjustment with a 8-bit 2 s

compliment value ranging [-128, +127]. This value is added to the Y value after
0b contrast multiply and before YUV to RGB conversion. A value of zero disables this
7:0 adjustment affect. This 8-bit signed value provides half of the achievable brightness
RW adjustment dynamic range. A full range brightness value would have a programmable
range of [-255, +255]. Bypassing Brightness for YUV formats and for source data in
RGB format, is accomplished by programming this field to 0.

14.11.353 SPDCLRC1—Offset 724D4h

Sprite D Color Correction 1 Register

Access Method
Type: Memory Mapped I/O Register
SPDCLRC1: [GTTMMADR_LSB + 2BF20h] + 724D4h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000080h

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Datasheet 849
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0

RESERVED

SATURATION_AND_HUE_SIN_SH_SIN

RESERVED_1

SATURATION_AND_HUE_COS_SH_COS
Bit Default &
Description
Range Access

0b
31:27 RESERVED: Reserved.
RW

SATURATION_AND_HUE_SIN_SH_SIN: This 11-bit signed fixed-point number is in

2 s compliment (s3i.7f) format with the MSB as the sign, next 3 MSBs as the integer
value and the last 7 LSBs as the fraction value. This field can be used in two modes.
When full range YUV data is operated on, this field contains the saturation value. When
the range-limited YCbCr data is used, software should program this field with the
0b product of the saturation multiplier value multiplied by the CbCr range scale factor
26:16
RW (=128/112). Similar to the contrast field, there is no limit for saturation reduction
saturation = 0 means all pixels become the same value. However, increasing contrast
can only be increased by a factor less than 8. For example, the largest contrast with
value of 0x7.7F can bring input range [0, 32] to a full display color range of [0, 255].
Bypassing Hue, even for source data in RGB format, is accomplished by programming
this field to 0.0.

0b
15:10 RESERVED_1: Reserved.
RW

SATURATION_AND_HUE_COS_SH_COS: This unsigned fixed-point number is in

3i.7f format with the first 3 MSBs be the integer value and the last 7 LSBs be the
fraction value. This field can be used in two modes. When full range YUV data is
operated on, this field contains the saturation value. When the range-limited YCbCr data
001000000 is used, software should program this field with the product of the saturation multiplier
9:0 0b value multiplied by the CbCr range scale factor (=128/112). Similar to the contrast field,
RW there is no limit for saturation reduction saturation = 0 means all pixels become the
same value. However, increasing contrast can only be increased by a factor less than 8.
For example, the largest contrast with value of 0x7.7F can bring input range [0, 32] to a
full display color range of [0, 255]. Bypassing Saturation, even for source data in RGB
format, is accomplished by programming this field to 1.0.

14.11.354 SPDGAMC5—Offset 724E0h

Sprite D Gamma Correction Registers

Access Method
Type: Memory Mapped I/O Register SPDGAMC5: [GTTMMADR_LSB + 2BF20h] + 724E0h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00C0C0C0h

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850 Datasheet
Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0

RED_V_CR

BLUE_U_CB
RESERVED

GREEN_Y
Bit Default &
Description
Range Access

0b
31:24 RESERVED: reserved
RW
11000000b
23:16 RED_V_CR: gamma correction mapping Red to CR
RW
11000000b
15:8 GREEN_Y: gamma correction mapping Green to Y
RW
11000000b
7:0 BLUE_U_CB: gamma correction mapping Blue to CB
RW

14.11.355 SPDGAMC4—Offset 724E4h

Sprite D Gamma Correction Registers

Access Method
Type: Memory Mapped I/O Register
SPDGAMC4: [GTTMMADR_LSB + 2BF20h] + 724E4h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00808080h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
GREEN_Y
RESERVED

BLUE_U_CB
RED_V_CR

Bit Default &

Description
Range Access

0b
31:24 RESERVED: reserved
RW
10000000b
23:16 RED_V_CR: gamma correction mapping Red to CR
RW
10000000b
15:8 GREEN_Y: gamma correction mapping green to Y
RW
10000000b
7:0 BLUE_U_CB: gamma correction mapping blue to CB
RW

14.11.356 SPDGAMC3—Offset 724E8h

Sprite D Gamma Correction Registers

Bay Trail-I SoC

Datasheet 851
 Graphics, Video and Display

Access Method
Type: Memory Mapped I/O Register
SPDGAMC3: [GTTMMADR_LSB + 2BF20h] + 724E8h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00404040h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0

BLUE_U_CB
RESERVED

RED_V_CR

GREEN_Y
Bit Default &
Description
Range Access

0b
31:24 RESERVED: reserved
RW

01000000b
23:16 RED_V_CR: gamma correction mapping Red to CR
RW

01000000b
15:8 GREEN_Y: gamma correction mapping Green to Y
RW

01000000b
7:0 BLUE_U_CB: gamma correction mapping blue to CB
RW

14.11.357 SPDGAMC2—Offset 724ECh

Sprite D Gamma Correction Registers

Access Method
Type: Memory Mapped I/O Register SPDGAMC2: [GTTMMADR_LSB + 2BF20h] + 724ECh
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00202020h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0
RED_V_CR

BLUE_U_CB
RESERVED

GREEN_Y

Bit Default &

Description
Range Access

0b
31:24 RESERVED: reserved
RW
00100000b
23:16 RED_V_CR: gamma correction mapping Red to CR
RW

Bay Trail-I SoC

852 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

00100000b
15:8 GREEN_Y: gamma correction mapping green to Y
RW
00100000b
7:0 BLUE_U_CB: gamma correction mapping Blue to CB
RW

14.11.358 SPDGAMC1—Offset 724F0h

Sprite D Gamma Correction Registers

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) SPDGAMC1: [GTTMMADR_LSB + 2BF20h] + 724F0h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00101010h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0

BLUE_U_CB
RESERVED

RED_V_CR

GREEN_Y

Bit Default &

Description
Range Access

0b
31:24 RESERVED: reserved
RW
00010000b
23:16 RED_V_CR: gamma correction mapping red to CR
RW

00010000b
15:8 GREEN_Y: gamma correction mapping green to Y
RW

00010000b
7:0 BLUE_U_CB: gamma correction mapping blue to CB
RW

14.11.359 SPDGAMC0—Offset 724F4h

Sprite D Gamma Correction Registers

Access Method
Type: Memory Mapped I/O Register SPDGAMC0: [GTTMMADR_LSB + 2BF20h] + 724F4h
(Size: 32 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00080808h

Bay Trail-I SoC

Datasheet 853
 Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0

RED_V_CR

BLUE_U_CB
RESERVED

GREEN_Y
Bit Default &
Description
Range Access

0b
31:24 RESERVED: reserved
RW
00001000b
23:16 RED_V_CR: gamma correction mapping Red to CR
RW
00001000b
15:8 GREEN_Y: gamma correction mapping Green to Y
RW
00001000b
7:0 BLUE_U_CB: gamma correction mapping blue to CB
RW

14.11.360 PCSRC—Offset 73000h

Performance Counter Source Register

Access Method
Type: Memory Mapped I/O Register
PCSRC: [GTTMMADR_LSB + 2BF20h] + 73000h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PERFORMANCE_COUNTER_ENABLE

PERFORMANCE_COUNTER_THRESHOLD_VALUE
MAX_OR_MIN
RESERVED
RESET_COUNTER

RESERVED_1
SOURCE_FOR_PERFORMANCE_COUNTER

Bay Trail-I SoC

854 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

0b PERFORMANCE_COUNTER_ENABLE: This bit enables the performance counter. 0 =

31
RW Performance counter is disabled 1 = Performance counter is enabled.

0b
30 RESERVED: Reserved.
RW

0b RESET_COUNTER: This bit indicates when the counter will be reset. 1 = Reset after
29 each frame, summing all events in the frame 0 = Reset after each event within the
RW frame

0b MAX_OR_MIN: This bit tells whether the stored counter value for an event is the
28 maximum or the minimum value. The previous value is used to do the compare. 0 =
RW Stored value is the maximum latency 1 = Stored value is the minimum latency
SOURCE_FOR_PERFORMANCE_COUNTER: These bits indicate the source for the
performance counter. 000000 = Overlay Register Request Latency [DevBW] and
[DevCL] 000001 = VGA Font Request Latency 000010 = VGA Character Request
Latency 000011 = Display A FIFO Status 000100 = Display B FIFO Status 000101 =
Sprite A FIFO Status 000110 = Cursor A FIFO Status 000111 = Cursor B FIFO Status
001000 = Display Steamer A TLB Latency 001001 = Display Streamer B TLB Latency
001010 = Sprite Streamer A TLB Latency 001011 = Cursor Streamer A TLB Latency
001100 = Cursor Streamer B TLB Latency 001101 = Overlay Streamer TLB Latency
[DevBW] and [DevCL] 001110 = Display Steamer A Request Latency 001111 = Display
Streamer B Request Latency 010000 = Sprite Streamer A Request Latency 010001 =
Cursor Streamer A Request Latency 010010 = Cursor Streamer B Request Latency
010011 = Overlay Streamer Request Latency [DevBW] and [DevCL] 010100 = Display
A Command Request Latency 010101 = Display B Command Request Latency 010110 =
Sprite A Command Request Latency 010111 = Cursor A Command Request Latency
011000 = Cursor B Command Request Latency 011001 = Overlay Command Request
0b Latency [DevBW] and [DevCL] 011010 = DPFC Dummy Read [DevCTG] 011011 = DPFC
27:22
RW Self Refresh [DevCTG] 011100 = Sprite B FIFO status 011101 = Sprite C FIFO status
011110 = Sprite D FIFO status 011111 = Sprite B TLB Request Latency 100000 = Sprite
C TLB Request Latency 100001 = Sprite D TLB Request Latency 100010 = Sprite B
Request Latency 100011 = Sprite C Request Latency 100100 = Sprite D Request
Latency 100101 = Sprite B Command Request Latency 100110 = Sprite C Command
Request Latency 100111 = Sprite D Command Request Latency 101000 = SR exit to
data HP Put (measure the latency from the SRexit failing edge to the first data HP Put.
This event shall be measured by either planeA, SpriteA, SpriteB, or CurA in pipeA)
101001 = InSR to data HP Put (measure the latency from any data request made during
inSR is active to the first data HP Put. This event shall be measured by either planeA,
SpriteA, SpriteB, or CurA in pipeA) 101010 = SR exit to TLB HP Put (measure the
latency from the SRexit failing edge to the first TLB HP Put. This event shall be
measured by either planeA, SpriteA, SpriteB, or CurA in pipeA ) 101011 = InSR to TLB
HP Put (measure the latency from any TLB request made during inSR is active to the
first TLB HP Put. This event shall be measured by either planeA, SpriteA, SpriteB, or
CurA in pipeA )
0b
21:16 RESERVED_1: Write as zero.
RW
PERFORMANCE_COUNTER_THRESHOLD_VALUE: This value is used to compare
0b against the performance counter. If the performance counter matches this value, an
15:0 interrupt is generated if the interrupt bit is enabled. When the source selected is DDB
RW FIFO status, the threshold value is used to program the value needed to monitor in the
DDB FIFO. No interrupt is generated in this condition.

14.11.361 PCSTAT—Offset 73004h

Performance Counter Status Register

Access Method
Type: Memory Mapped I/O Register PCSTAT: [GTTMMADR_LSB + 2BF20h] + 73004h
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Bay Trail-I SoC

Datasheet 855
 Graphics, Video and Display

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SOURCE_FOR_PERFORMANCE_COUNTER
RESET_COUNTER

RESERVED

PERFORMANCE_COUNTER_VALUE
OVERFLOW

MAX_OR_MIN

Bit Default &

Description
Range Access

0b OVERFLOW: This bit indicates weather the 16 bit counter overflowed or not. 0 =
31
RO Counter is valid 1 = Counter is invalid since it overflowed

0b RESET_COUNTER: This bit indicates when the counter will be reset. 1 = Reset after
30
RO each frame, sum of all event in the frame 0 = Reset after each event within the frame

0b MAX_OR_MIN: This bit tells whether the stored counter value for an event is the
29 maximum or the minimum value of the previous event. 0 = Stored value is the
RO maximum latency 1 = Stored value is the minimum latency

SOURCE_FOR_PERFORMANCE_COUNTER: These bits indicate the source for the

performance counter. 000000 = Overlay Register Request Latency [DevBW] and
[DevCL] 000001 = VGA Font Request Latency 000010 = VGA Character Request
Latency 000011 = Display A FIFO Status 000100 = Display B FIFO Status 000101 =
Sprite A FIFO Status 000110 = Cursor A FIFO Status 000111 = Cursor B FIFO Status
001000 = Display Steamer A TLB Latency 001001 = Display Streamer B TLB Latency
001010 = Sprite Streamer A TLB Latency 001011 = Cursor Streamer A TLB Latency
001100 = Cursor Streamer B TLB Latency 001101 = Overlay Streamer TLB Latency
[DevBW] and [DevCL] 001110 = Display Steamer A Request Latency 001111 = Display
Streamer B Request Latency 010000 = Sprite Streamer A Request Latency 010001 =
Cursor Streamer A Request Latency 010010 = Cursor Streamer B Request Latency
010011 = Overlay Streamer Request Latency [DevBW] and [DevCL] 010100 = Display
A Command Request Latency 010101 = Display B Command Request Latency 010110 =
Sprite A Command Request Latency 010111 = Cursor A Command Request Latency
011000 = Cursor B Command Request Latency 011001 = Overlay Command Request
0b Latency [DevBW] and [DevCL] 011010 = DPFC Dummy Read [DevCTG] 011011 = DPFC
28:23
RO Self Refresh [DevCTG] 011100 = Sprite B FIFO status 011101 = Sprite C FIFO status
011110 = Sprite D FIFO status 011111 = Sprite B TLB Request Latency 100000 = Sprite
C TLB Request Latency 100001 = Sprite D TLB Request Latency 100010 = Sprite B
Request Latency 100011 = Sprite C Request Latency 100100 = Sprite D Request
Latency 100101 = Sprite B Command Request Latency 100110 = Sprite C Command
Request Latency 100111 = Sprite D Command Request Latency 101000 = SR exit to
data HP Put (measure the latency from the SRexit failing edge to the first data HP Put.
This event shall be measured by either planeA, SpriteA, SpriteB, or CurA in pipeA)
101001 = InSR to data HP Put (measure the latency from any data request made during
inSR is active to the first data HP Put. This event shall be measured by either planeA,
SpriteA, SpriteB, or CurA in pipeA ) 101010 = SR exit to TLB HP Put (measure the
latency from the SRexit failing edge to the first TLB HP Put. This event shall be
measured by either planeA, SpriteA, SpriteB, or CurA in pipeA) 101011 = InSR to TLB
HP Put (measure the latency from any TLB request made during inSR is active to the
first TLB HP Put. This event shall be measured by either planeA, SpriteA, SpriteB, or
CurA in pipeA )

0b
22:16 RESERVED: Write as zero.
RO

Bay Trail-I SoC

856 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

0b PERFORMANCE_COUNTER_VALUE: This is the value of the performance counter for

15:0
RO the source indicated in the source field.

14.11.362 PCSRC2—Offset 73008h

Performance Counter Source2 Register

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) PCSRC2: [GTTMMADR_LSB + 2BF20h] + 73008h

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MAX_OR_MIN
RESERVED
RESERVED_1
RESET_COUNTER

SOURCE_FOR_PERFORMANCE_COUNTER

RESERVED_2

PERFORMANCE_COUNTER_THRESHOLD_VALUE

Bit Default &

Description
Range Access

0b RESERVED: Programming note: This second performance counter is enabled by the

31
RW enable bit in the PCSRC1 bit 31.

0b
30 RESERVED_1: Reserved.
RW

0b RESET_COUNTER: This bit indicates when the counter will be reset. 1 = Reset after
29 each frame, summing all events in the frame 0 = Reset after each event within the
RW frame

0b MAX_OR_MIN: This bit tells whether the stored counter value for an event is the
28 maximum or the minimum value. The previous value is used to do the compare. 0 =
RW Stored value is the maximum latency 1 = Stored value is the minimum latency

Bay Trail-I SoC

Datasheet 857
 Graphics, Video and Display

Bit Default &

Description
Range Access

SOURCE_FOR_PERFORMANCE_COUNTER: These bits indicate the source for the

performance counter. 000000 = Overlay Register Request Latency [DevBW] and
[DevCL] 000001 = VGA Font Request Latency 000010 = VGA Character Request
Latency 000011 = Display A FIFO Status 000100 = Display B FIFO Status 000101 =
Sprite A FIFO Status 000110 = Cursor A FIFO Status 000111 = Cursor B FIFO Status
001000 = Display Streamer A TLB Latency 001001 = Display Streamer B TLB Latency
001010 = Sprite Streamer A TLB Latency 001011 = Cursor Streamer A TLB Latency
001100 = Cursor Streamer B TLB Latency 001101 = Overlay Streamer TLB Latency
[DevBW] and [DevCL] 001110 = Display Streamer A Request Latency 001111 = Display
Streamer B Request Latency 010000 = Sprite Streamer A Request Latency 010001 =
Cursor Streamer A Request Latency 010010 = Cursor Streamer B Request Latency
010011 = Overlay Streamer Request Latency [DevBW] and [DevCL] 010100 = Display
A Command Request Latency 010101 = Display B Command Request Latency 010110 =
Sprite A Command Request Latency 010111 = Cursor A Command Request Latency
011000 = Cursor B Command Request Latency 011001 = Overlay Command Request
0b Latency [DevBW] and [DevCL] 011010 = DPFC Dummy Read [DevCTG] 011011 = DPFC
27:22
RW Self Refresh [DevCTG] 011100 = Sprite B FIFO status 011101 = Sprite C FIFO status
011110 = Sprite D FIFO status 011111 = Sprite B TLB Request Latency 100000 = Sprite
C TLB Request Latency 100001 = Sprite D TLB Request Latency 100010 = Sprite B
Request Latency 100011 = Sprite C Request Latency 100100 = Sprite D Request
Latency 100101 = Sprite B Command Request Latency 100110 = Sprite C Command
Request Latency 100111 = Sprite D Command Request Latency 101000 = SR exit to
data HP Put (measure the latency from the SRexit failing edge to the first data HP Put.
This event shall be measured by either planeB, SpriteC, SpriteD, or CurB in pipeB)
101001 = InSR to data HP Put (measure the latency from any data request made during
inSR is active to the first data HP Put. This event shall be measured by either planeB,
SpriteC, SpriteD, or CurB in pipeB) 101010 = SR exit to TLB HP Put (measure the
latency from the SRexit failing edge to the first TLB HP Put. This event shall be
measured by either planeB, SpriteC, SpriteD, or CurB in pipeB ) 101011 = InSR to TLB
HP Put (measure the latency from any TLB request made during inSR is active to the
first TLB HP Put. This event shall be measured by either planeB, SpriteC, SpriteD, or
CurB in pipeB )

0b
21:16 RESERVED_2: Write as zero.
RW

PERFORMANCE_COUNTER_THRESHOLD_VALUE: This value is used to compare

0b against the performance counter. If the performance counter matches this value, an
15:0 interrupt is generated if the interrupt bit is enabled. When the source selected is DDB
RW FIFO status, the threshold value is used to program the value needed to monitor in the
DDB FIFO. No interrupt is generated in this condition.

14.11.363 PCSTAT2—Offset 7300Ch

Performance Counter Status2 Register

Access Method
Type: Memory Mapped I/O Register
PCSTAT2: [GTTMMADR_LSB + 2BF20h] + 7300Ch
(Size: 32 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00000000h

Bay Trail-I SoC

858 Datasheet
Graphics, Video and Display

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SOURCE_FOR_PERFORMANCE_COUNTER
RESET_COUNTER

RESERVED

PERFORMANCE_COUNTER_VALUE
OVERFLOW

MAX_OR_MIN

Bit Default &

Description
Range Access

0b OVERFLOW: This bit indicates weather the 16 bit counter overflowed or not. 0 =
31
RO Counter is valid 1 = Counter is invalid since it overflowed

0b RESET_COUNTER: This bit indicates when the counter will be reset. 1 = Reset after
30
RO each frame, sum of all event in the frame 0 = Reset after each event within the frame

0b MAX_OR_MIN: This bit tells whether the stored counter value for an event is the
29 maximum or the minimum value of the previous event. 0 = Stored value is the
RO maximum latency 1 = Stored value is the minimum latency

SOURCE_FOR_PERFORMANCE_COUNTER: These bits indicate the source for the

performance counter. 000000 = Overlay Register Request Latency [DevBW] and
[DevCL] 000001 = VGA Font Request Latency 000010 = VGA Character Request
Latency 000011 = Display A FIFO Status 000100 = Display B FIFO Status 000101 =
Sprite A FIFO Status 000110 = Cursor A FIFO Status 000111 = Cursor B FIFO Status
001000 = Display Steamer A TLB Latency 001001 = Display Streamer B TLB Latency
001010 = Sprite Streamer A TLB Latency 001011 = Cursor Streamer A TLB Latency
001100 = Cursor Streamer B TLB Latency 001101 = Overlay Streamer TLB Latency
[DevBW] and [DevCL] 001110 = Display Steamer A Request Latency 001111 = Display
Streamer B Request Latency 010000 = Sprite Streamer A Request Latency 010001 =
Cursor Streamer A Request Latency 010010 = Cursor Streamer B Request Latency
010011 = Overlay Streamer Request Latency [DevBW] and [DevCL] 010100 = Display
A Command Request Latency 010101 = Display B Command Request Latency 010110 =
Sprite A Command Request Latency 010111 = Cursor A Command Request Latency
011000 = Cursor B Command Request Latency 011001 = Overlay Command Request
0b Latency [DevBW] and [DevCL] 011010 = DPFC Dummy Read [DevCTG] 011011 = DPFC
28:23
RO Self Refresh [DevCTG] 011100 = Sprite B FIFO status 011101 = Sprite C FIFO status
011110 = Sprite D FIFO status 011111 = Sprite B TLB Request Latency 100000 = Sprite
C TLB Request Latency 100001 = Sprite D TLB Request Latency 100010 = Sprite B
Request Latency 100011 = Sprite C Request Latency 100100 = Sprite D Request
Latency 100101 = Sprite B Command Request Latency 100110 = Sprite C Command
Request Latency 101001 = InSR to HP Put (first put after inSR failing edge) 101000 =
SR exit to data HP Put (measure the latency from the SRexit failing edge to the first data
HP Put. This event shall be measured by either planeB, SpriteC, SpriteD, or CurB in
pipeB) 101001 = InSR to data HP Put (measure the latency from any data request made
during inSR is active to the first data HP Put. This event shall be measured by either
planeB, SpriteC, SpriteD, or CurB in pipeB) 101010 = SR exit to TLB HP Put (measure
the latency from the SRexit failing edge to the first TLB HP Put. This event shall be
measured by either planeB, SpriteC, SpriteD, or CurB in pipeB ) 101011 = InSR to TLB
HP Put (measure the latency from any TLB request made during inSR is active to the
first TLB HP Put. This event shall be measured by either planeB, SpriteC, SpriteD, or
CurB in pipeB )

0b
22:16 RESERVED: Write as zero.
RO

Bay Trail-I SoC

Datasheet 859
 Graphics, Video and Display

Bit Default &

Description
Range Access

0b PERFORMANCE_COUNTER_VALUE: This is the value of the performance counter for

15:0
RO the source indicated in the source field.

Bay Trail-I SoC

860 Datasheet
Graphics, Video and Display

Bay Trail-I SoC

Datasheet 861
 Graphics, Video and Display

14.12 Memory Mapped Registers (Read Only)

Table 161. Summary of Display Memory Mapped I/O Registers—GTTMMADR_LSB

Default
Offset Size Register ID—Description
Value

3BAh 1 “ST01 (ST01_MDA)—Offset 3BAh” on page 862 00h

3C2h 1 “ST00—Offset 3C2h” on page 863 00h

3C7h 1 “DACSTATE—Offset 3C7h” on page 864 00h
3DAh 1 “ST01 (ST01_CGA)—Offset 3DAh” on page 865 00h

14.12.1 ST01 (ST01_MDA)—Offset 3BAh

Input Status 1

Access Method
Type: Memory Mapped I/O Register ST01_MDA: [GTTMMADR_LSB + 2BF20h] + 3BAh
(Size: 8 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00h
7 4 0

0 0 0 0 0 0 0 0
RESERVED_AS_PER_VGA_SPECIFICATION

VIDEO_FEEDBACK_1_0

RESERVED_1

DIS_PLAY_ENA_BLE_OUTPUT
VER_TI_CAL_RETRACE_VIDEO
RESERVED

Bit Default &

Description
Range Access

0b
7 RESERVED_AS_PER_VGA_SPECIFICATION: Read as 0s.
RO
0b
6 RESERVED: Read as 0.
RO
VIDEO_FEEDBACK_1_0: These are diagnostic video bits that are selected by the Color
Plane Enable Register. These bits that are programmably connected to 2 of the 8 color
0b bits sent to the palette. Bits 4 and 5 of the Color Plane Enable Register (AR12) selects
5:4
RO which two of the 8 possible color bits become connected to these 2 bits of this register.
The current software normally does not use these 2 bits. They exist for EGA
compatibility.

Bay Trail-I SoC

862 Datasheet
Graphics, Video and Display

Bit Default &

Description
Range Access

VER_TI_CAL_RETRACE_VIDEO: 0 = VSYNC inactive (Indicates that a vertical retrace

interval is not taking place). 1 = VSYNC active (Indicates that a vertical retrace interval
is taking place). Note: VGA pixel generation is not locked to the display output but is
loosely coupled. A VSYNC indication may not occur during the actual VSYNC going to the
display but during the VSYNC that is generated as part of the VGA pixel generation. The
0b exact relationship will vary with the VGA display operational mode. This status bit will
3 remain active when the VGA is disabled and the device is running in high resolution
RO modes (non-VGA) to allow for applications that (now it is incorrect) use these status
registers bits. In this case, the status will come from the pipe that the VGA is assigned
to. Bits 4 and 5 of the Vertical Retrace End Register (CR11) previously could program
this bit to generate an interrupt at the start of the vertical retrace interval. This ability to
generate interrupts at the start of the vertical retrace interval is a feature that is largely
unused by legacy software. Interrupts are not supported through the VGA register bits.
0b
2:1 RESERVED_1: Read as 0s.
RO
DIS_PLAY_ENA_BLE_OUTPUT: Display Enable is a status bit (bit 0) in VGA Input
Status Register 1 that indicates when either a horizontal retrace interval or a vertical
retrace interval is taking place. This was used with the IBM* EGA graphics system (and
the ones that preceded it, including MDA and CGA). In those cases, it was important to
check the status of this bit to ensure that one or the other retrace intervals was taking
place before reading from or writing to the frame buffer. In these earlier systems,
reading from or writing to frame buffer at times outside the retrace intervals meant that
the CRT controller would be denied access to the frame buffer. This resulted in either
snow or a flickering display. This bit provides compatibility with software designed for
0b those early graphics controllers. This bit is currently used in DOS applications that
0
RO access the palette to prevent the sparkle associated with read and write accesses to the
palette ram with the same address on the same clock cycle. This status bit will remain
active when the VGA display is disabled and the device is running in high resolution
modes (non-VGA) to allow for applications that (now considered incorrect) use these
status registers bits. In this case, the status will come from the pipe that the VGA is
assigned to. When in panel fitting VGA or centered VGA operation, the meaning of these
bits will not be consistent with native VGA timings. 0 = Active display data is being sent
to the display. Neither a horizontal retrace interval or a vertical retrace interval is
currently taking place. 1 = Either a horizontal retrace interval (horizontal blanking) or a
vertical retrace interval (vertical blanking) is currently taking place.

14.12.2 ST00—Offset 3C2h

Input Status 0

Access Method
Type: Memory Mapped I/O Register ST00: [GTTMMADR_LSB + 2BF20h] + 3C2h
(Size: 8 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00h

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 Graphics, Video and Display

7 4 0

0 0 0 0 0 0 0 0

RESERVED

RGB_COMPARATOR_SENSE
CRT_INTER_RUPT_PENDING

RESERVED_1
Bit Default &
Description
Range Access

CRT_INTER_RUPT_PENDING: This bit is here for EGA compatibility and will always
return zero. Note that the generation of interrupts was originally enabled, through bits
0b [4,5] of the Vertical Retrace End Register (CR11). This ability to generate interrupts at
7 the start of the vertical retrace interval is a feature that is typically unused by DOS
RO software and therefore is only supported through other means for use under a operating
system support. 0 = CRT (vertical retrace interval) interrupt is not pending. 1 = CRT
(vertical retrace interval) interrupt is pending

0b
6:5 RESERVED: Read as 0s.
RO

RGB_COMPARATOR_SENSE: This bit returns the state of the output of the RGB
output comparator(s). Video BIOS uses this bit during POST to determine whether the
display is connected and if it is a color or monochrome CRT. BIOS blanks the screen or
0b clears the frame buffer to display only black. Next, BIOS outputs a ramp to the D-to-A
4
RO converters to test for the presence of a color display by determining which code cause
the comparator to switch. Finally, if the BIOS does not detect any termination resistors
on Red or Blue, it tests for the presence of a display using the Green signal. The result
of each such test is read via this bit. 0 = Below threshold 1 = Above threshold
0b
3:0 RESERVED_1: Read as 0s.
RO

14.12.3 DACSTATE—Offset 3C7h

DAC State Register

Access Method
Type: Memory Mapped I/O Register DACSTATE: [GTTMMADR_LSB + 2BF20h] + 3C7h
(Size: 8 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00h
7 4 0

0 0 0 0 0 0 0 0
RESERVED

DAC_STATE

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Bit Default &

Description
Range Access

0b
7:2 RESERVED: Read as 0.
RO
DAC_STATE: This field indicates which of the two index registers was most recently
0b written. Bits [1:0] Index Register Indicated 00 Palette Write Index Register at I/O
1:0
RO Address 3C7h (default) 01 Reserved 10 Reserved 11 Palette Read Index Register at I/O
Address 3C8h

14.12.4 ST01 (ST01_CGA)—Offset 3DAh

Input Status 1

Access Method
Type: Memory Mapped I/O Register ST01_CGA: [GTTMMADR_LSB + 2BF20h] + 3DAh
(Size: 8 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00h
7 4 0

0 0 0 0 0 0 0 0
RESERVED_AS_PER_VGA_SPECIFICATION

VIDEO_FEEDBACK_1_0

VER_TI_CAL_RETRACE_VIDEO

RESERVED_1

DIS_PLAY_ENA_BLE_OUTPUT
RESERVED

Bit Default &

Description
Range Access

0b
7 RESERVED_AS_PER_VGA_SPECIFICATION: Read as 0s.
RO
0b
6 RESERVED: Read as 0.
RO
VIDEO_FEEDBACK_1_0: These are diagnostic video bits that are selected by the Color
Plane Enable Register. These bits that are programmably connected to 2 of the 8 color
0b bits sent to the palette. Bits 4 and 5 of the Color Plane Enable Register (AR12) selects
5:4
RO which two of the 8 possible color bits become connected to these 2 bits of this register.
The current software normally does not use these 2 bits. They exist for EGA
compatibility.

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 Graphics, Video and Display

Bit Default &

Description
Range Access

VER_TI_CAL_RETRACE_VIDEO: 0 = VSYNC inactive (Indicates that a vertical retrace

interval is not taking place). 1 = VSYNC active (Indicates that a vertical retrace interval
is taking place). Note: VGA pixel generation is not locked to the display output but is
loosely coupled. A VSYNC indication may not occur during the actual VSYNC going to the
display but during the VSYNC that is generated as part of the VGA pixel generation. The
0b exact relationship will vary with the VGA display operational mode. This status bit will
3 remain active when the VGA is disabled and the device is running in high resolution
RO modes (non-VGA) to allow for applications that (now it is incorrect) use these status
registers bits. In this case, the status will come from the pipe that the VGA is assigned
to. Bits 4 and 5 of the Vertical Retrace End Register (CR11) previously could program
this bit to generate an interrupt at the start of the vertical retrace interval. This ability to
generate interrupts at the start of the vertical retrace interval is a feature that is largely
unused by legacy software. Interrupts are not supported through the VGA register bits.
0b
2:1 RESERVED_1: Read as 0s.
RO
DIS_PLAY_ENA_BLE_OUTPUT: Display Enable is a status bit (bit 0) in VGA Input
Status Register 1 that indicates when either a horizontal retrace interval or a vertical
retrace interval is taking place. This was used with the IBM* EGA graphics system (and
the ones that preceded it, including MDA and CGA). In those cases, it was important to
check the status of this bit to ensure that one or the other retrace intervals was taking
place before reading from or writing to the frame buffer. In these earlier systems,
reading from or writing to frame buffer at times outside the retrace intervals meant that
the CRT controller would be denied access to the frame buffer. This resulted in either
snow or a flickering display. This bit provides compatibility with software designed for
0b those early graphics controllers. This bit is currently used in DOS applications that
0
RO access the palette to prevent the sparkle associated with read and write accesses to the
palette ram with the same address on the same clock cycle. This status bit will remain
active when the VGA display is disabled and the device is running in high resolution
modes (non-VGA) to allow for applications that (now considered incorrect) use these
status registers bits. In this case, the status will come from the pipe that the VGA is
assigned to. When in panel fitting VGA or centered VGA operation, the meaning of these
bits will not be consistent with native VGA timings. 0 = Active display data is being sent
to the display. Neither a horizontal retrace interval or a vertical retrace interval is
currently taking place. 1 = Either a horizontal retrace interval (horizontal blanking) or a
vertical retrace interval (vertical blanking) is currently taking place.

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 Graphics, Video and Display

14.13 Memory Mapped Registers (Write Only)

Table 162. Summary of Display Memory Mapped I/O Registers—GTTMMADR_LSB

Default
Offset Size Register ID—Description
Value

3BAh 1 “FCR (FCR_MDA_Write)—Offset 3BAh” on page 868 00h

3C2h 1 “MSR (MSR_Write)—Offset 3C2h” on page 868 00h

3C7h 1 “DACRX—Offset 3C7h” on page 870 00h
3DAh 1 “FCR (FCR_CGA_Write)—Offset 3DAh” on page 870 00h

14.13.1 FCR (FCR_MDA_Write)—Offset 3BAh

Feature Control

Access Method
Type: Memory Mapped I/O Register FCR_MDA_Write: [GTTMMADR_LSB + 2BF20h] + 3BAh
(Size: 8 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00h
7 4 0

0 0 0 0 0 0 0 0

RESERVED_1
RESERVED

VSYNC_CONTROL

Bit Default &

Description
Range Access

0b
7:4 RESERVED: Read as 0.
RW
VSYNC_CONTROL: This bit is provided for compatibility only and has no other
function. Reads and writes to this bit have no effect other than to change the value of
0b this bit. The previous definition of this bit selected the output on the VSYNC pin. 0 =
3
RW Was used to set VSYNC out put on the VSYNC pin (default). 1 = Was used to set the log
i cal 'OR' of VSYNC and Display Ena ble output on the VSYNC pin. This capability was not
typically very useful..
0b
2:0 RESERVED_1: Read as 0.
RW

14.13.2 MSR (MSR_Write)—Offset 3C2h

Miscellaneous Output

Access Method

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Type: Memory Mapped I/O Register

MSR_Write: [GTTMMADR_LSB + 2BF20h] + 3C2h
(Size: 8 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00h
7 4 0

0 0 0 0 0 0 0 0

I_O_ADDRESS_SELECT
A0000_BFFFFH_MEMORY_ACCESS_ENABLE
CRT_VSYNC_POLARITY

PAGE_SELECT
CRT_HSYNC_POLA_RITY

RESERVED

Bit Default & CLOCK_SELECT

Description
Range Access

CRT_VSYNC_POLARITY: This is a legacy function that is used in native VGA modes.

0b For most cases, sync polarity will be controlled by the port control bits. The VGA settings
7 can be optionally selected for compatibility with the original VGA when used in the VGA
RW native mode. Sync polarity was used in VGA to signal the monitor how many lines of
active display are being generated. 0 = Positive Polarity (default). 1 = Negative Polarity.
CRT_HSYNC_POLA_RITY: This is a legacy function that is used in native VGA modes.
0b For most cases, sync polarity will be controlled by the port control bits. The VGA settings
6
RW can be optionally selected for compatibility with the original VGA when used in the VGA
native mode. 0 = Positive Polarity (default). 1 = Negative Polarity
PAGE_SELECT: In Odd/Even Memory Map Mode 1 (GR6), this bit selects the upper or
0b lower 64 KB page in dis play mem ory for CPU access: 0 = Upper page (default) 1 =
5 Lower page. Selects between two 64KB pages of frame buffer memory during standard
RW VGA odd/even modes (modes 0h through 5h). Bit 1 of register GR06 can also program
this bit in other modes. Note that this bit is would normally set to 1 by the software.

0b
4 RESERVED: Read as 0.
RW

CLOCK_SELECT: These bits can select the dot clock source for the CRT interface. The
bits should be used to select the dot clock in standard native VGA modes only. When in
the centering or upper left corner modes, these bits should be set to have no effect on
0b the clock rate. The actual frequencies that these bits select, if they have any affect at
3:2 all, is programmable through the DPLL registers that default to the standard values used
RW for VGA. 00 = CLK0, 25.175 MHz (for standard VGA modes with 640 pixel (8-dot)
horizontal resolution) (default) 01 = CLK1, 28.322 MHz. (for standard VGA modes with
720 pixel (9-dot) horizontal resolution) 10 = Was used to select an external clock (now
unused) 11 = Reserved

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Bit Default &

Description
Range Access

A0000_BFFFFH_MEMORY_ACCESS_ENABLE: VGA Compatibility bit enables access

to local video memory (frame buffer) at A0000(BFFFFh. When disabled, accesses to VGA
memory are blocked in this region. This bit is independent of and does not block CPU
0b access to the video linear frame buffer at other addresses. Note that it is typical for AGP
1 chipsets to shadow this register to allow proper steering of memory accesses to the
RW proper bus. 0 = Prevent CPU access to memory/registers/ROM through the A0000-
BFFFF VGA memory aperture (default). 1 = Allow CPU access to memory/registers/ROM
through the A0000-BFFFF VGA memory aperture. This memory must be mapped as UC
by the CPU; see VGA Host Access Memory Munging in Display and Overlay Functions.
I_O_ADDRESS_SELECT: This bit selects 3Bxh or 3Dxh as the I/O address for the CRT
Controller re gisters, the Feature Control Register (FCR), and Input Status Register 1
0b (ST01). Presently ignored (whole range is claimed), but will ignore 3Bx for color
0 configuration or 3Dx for monochrome. Note that it is typical in AGP chipsets to shadow
RW this bit and properly steer I/O cycles to the proper bus for operation where a MDA exists
on another bus such as ISA. 0 = Select 3Bxh I/O address (MDA emulation) (default). 1
= Select 3Dxh I/O address (CGA emulation).

14.13.3 DACRX—Offset 3C7h

Palette Read Index Register

Access Method
Type: Memory Mapped I/O Register DACRX: [GTTMMADR_LSB + 2BF20h] + 3C7h
(Size: 8 bits)

GTTMMADR_LSB Type: PCI Configuration Register (Size: 32

bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00h
7 4 0

0 0 0 0 0 0 0 0
PALETTE_READ_INDEX

Bit Default &

Description
Range Access

PALETTE_READ_INDEX: The 8-bit index value programmed into this register chooses
which of 256 standard color data positions within the palette are to be made accessible
0b for being read from via the Palette Data Register (DACDATA). The index value held in
7:0 this register is automatically incremented when all three bytes of the color data position
WO selected by the current index have been read. A write to this register will abort a
uncompleted palette write sequence. This register allows access to the palette even
when running non-VGA display modes.

14.13.4 FCR (FCR_CGA_Write)—Offset 3DAh

Feature Control

Access Method

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Type: Memory Mapped I/O Register

FCR_CGA_Write: [GTTMMADR_LSB + 2BF20h] + 3DAh
(Size: 8 bits)
GTTMMADR_LSB Type: PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference: [B:0, D:2, F:0] + 10h

Default: 00h
7 4 0

0 0 0 0 0 0 0 0

RESERVED

VSYNC_CONTROL

RESERVED_1
Bit Default &
Description
Range Access

0b
7:4 RESERVED: Read as 0.
RW
VSYNC_CONTROL: This bit is provided for compatibility only and has no other
function. Reads and writes to this bit have no effect other than to change the value of
0b this bit. The previous definition of this bit selected the output on the VSYNC pin. 0 =
3
RW Was used to set VSYNC out put on the VSYNC pin (default). 1 = Was used to set the log
i cal 'OR' of VSYNC and Display Ena ble output on the VSYNC pin. This capability was not
typically very useful..
0b
2:0 RESERVED_1: Read as 0.
RW

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 MIPI-Camera Serial Interface (CSI) & ISP

15 MIPI-Camera Serial Interface

(CSI) & ISP
The MIPI CSI and controller front end interfaces with three sensors and is capable of
simultaneously acquiring three streams, one from each sensor. These three streams
are presented to the ISP.

Note: If a 1-lane sensor needs to be connected to a MIPI-CSI port, that port must use a 1-
lane port configuration.

MIPI-CSI

Camera
IO 3

ISP
IO GPIO

15.1 Signal Descriptions

Please see Chapter 2, “Physical Interfaces” for additional details.

The signal description table has the following headings:

• Signal Name: The name of the signal/pin
• Direction: The buffer direction can be either input, output, or I/O (bidirectional)
• Platform Power: The reference power plane.
• Description: A brief explanation of the signal’s function

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Table 163. CSI Signals

Direction
Signal Name Description
Plat. Power

MCSI1_CLKP/N I Clock Lane: MIPI CSI input clock lane 0 for port 1.
V1P24S
MCSI1_DP/N[3:0] I Data Lanes: Four MIPI CSI Data Lanes (0-3) for port
V1P24S 1. Lanes 2 and 3 can optionally used as data lanes for
port 3.
MCSI2_CLKP/N I Clock Lane: MIPI CSI input clock lane 0 for port 2.
V1P24S
MCSI2_DP/N[0] I Data Lane: Single MIPI CSI Data Lanes for port 2.
V1P24S
MCSI3_CLKP/N I Clock Lane: MIPI CSI input clock lane 0 for port
V1P24S 3.
MCSI_RCOMP I/O Resistor Compensation: This is for pre-driver
slew rate compensation for the MIPI CSI
Interface. Please contact your Intel
representative for details.

Table 164. GPIO Signals (Sheet 1 of 2)

Direction
Signal Name Description
Plat. Power

MCSI_GPIO[00] I/O Output from shutter switch when its pressed halfway.
V1P8S This switch state is used to trigger the Auto focus LED for
Xenon Flash or Torch mode for LED Flash
MCSI_GPIO[01] I/O Output from shutter switch when its pressed full way.
V1P8S This switch state is used to trigger Xenon flash or LED
Flash
MCSI_GPIO[02] I/O Active high control signal to Xenon Flash to start charging
V1P8S the Capacitor

MCSI_GPIO[03] I/O Active low output from Xenon Flash to indicate that the
V1P8S capacitor is fully charged and is ready to be triggered

MCSI_GPIO[04] I/O Active high Xenon Flash trigger / Enables Torch Mode on
V1P8S LED Flash IC

MCSI_GPIO[05] I/O Enables Red Eye Reduction LED for Xenon / Triggers
V1P8S STROBE on LED Flash IC /

MCSI_GPIO[06] I/O Camera Sensor 0 Strobe Output to SoC to indicate

V1P8S beginning of capture / Active high signal to still camera to
power down the device.
MCSI_GPIO[07] I/O Camera Sensor 1 Strobe Output to SoC to indicate
V1P8S beginning of capture / Active high signal to still camera to
power down the device.

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 MIPI-Camera Serial Interface (CSI) & ISP

Table 164. GPIO Signals (Sheet 2 of 2)

Direction
Signal Name Description
Plat. Power

MCSI_GPIO[08] I/O Active high signal to video camera to power down the
V1P8S device.

MCSI_GPIO[09] I/O Active low output signal to reset digital still camera #0.
V1P8S
MCSI_GPIO[10] I/O Active low output signal to reset digital still camera #1
V1P8S
MCSI_GPIO[11] I/O Active low output signal to reset digital video camera
V1P8S

Figure 97. Camera Connectivity

Camera ISP
Port 1 Port 1 PHY
Data 0 Data 0
Image Signal Processor

MIPI-CSI Controller

Data 1 Data 1
Data 2 Data 2
Data 3 Data 3
Clock Clock
Port 2 Port 2 PHY
Data 0 Data 0
Clock Clock
Port 3 PHY
Data 0
Port 3 Data 1
Clock Clock

Camera GPIO

15.2 Features
• Integrated MIPI-CSI 2.0 interface
• Image Signal Processor (ISP) with DMA and local SRAM
• Imaging data is received by the MIPI-CSI interface and is relayed to the ISP for
processing
• Up to five MIPI-CSI 2.0 data lanes
— Each lane can operate at up to 1GT/s. resulting in roughly 800 Mbit/s of actual
pixels
• The MIPI-CSI interface supports lossless compressed image streams to increases
the effective bandwidth without losing data

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• Up to 24MP sensors supported, and full HD 1080p60

— Can also support Stereo HD 1080p30
• Up to two cameras can be operated simultaneously
— Stereoscopic Captures
— Front + Back Camera Usage

15.2.1 Imaging Capabilities

The following table summarizes imaging capabilities.

Table 165. Imaging Capabilities

Feature Capabilities

Sensor interface Configurable MIPI-CSI2 interfaces.

3 sensors: x2, x2, x1 or x3, x1, x1
2 sensors: x4, x1
Simultaneous Up to 2 simultaneous sensors
sensors
2D Image capture 24MP @ 15fps
2D video capture Up to 1080p60
Input formats RAW 8, 10, 12, 14, RGB444, 565, 888, YUV420, 422, JPEG.
(Sensor -> SoC)
Output formats YUV422, YUV420, RAW
(SoC -> Sensor)
Special Features Image and video stabilization
Low light noise reduction
Burst mode capture
Memory to memory processing
3A (Auto Exposure (AE), Auto White Balance (AWB) and Auto Focus (AF))
High Dynamic Range (HDR)
Multi-focus
Zero shutter lag

15.2.2 Simultaneous Acquisition

All three cameras can be active at the same time.

SoC will support on-the-fly processing for only one image at a time. While this image is
being processed on-the-fly, images from the other two cameras are saved to DRAM for
later processing.

15.2.3 Primary Camera Still Image Resolution

Maximum still image resolution for the primary camera in post-processing mode is
limited by the resolution of the sensors. Currently 24 Mpixel sensors are supported.

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 MIPI-Camera Serial Interface (CSI) & ISP

Maximum primary camera on-the-fly still image resolution for primary camera is 16
Mpixel at 18 fps.

Higher resolution, or higher frame rates are supported as long as the product of
resolution and frame rate does not exceed 288 Mpixels/s (= 16 Mpixels * 18 fps).

Maximum primary camera on-the-fly stereoscopic still image resolution for primary
camera is 8 Mpixel for each of the left and right images at 18 fps. The number of
Mpixels can be increased by decreasing the frame rate.

15.2.4 Burst Mode Support

The SoC supports capturing multiple images back to back at maximum sensor
resolution. At least 5 images must be captured in burst mode. The maximum number
of images that can be so captured is limited only by available system memory. These
images need not be processed on-the-fly.

15.2.5 Continuous Mode Capture

SoC supports capturing images and saving them to DRAM in a ring of frame buffers
continuously at maximum sensor resolution. These images must then be fetched and
processed on-the-fly by the ISP. This adds a round trip to memory for every frame and
increases the bandwidth requirements.

15.2.6 Secondary Camera Still Image Resolution

Maximum secondary camera still image resolution is 4 Mpixel at 15 fps.

15.2.7 Primary Camera Video Resolution

Maximum primary camera video resolution is 1080p60.

Maximum primary camera dual video resolution is 1080p30.

Maximum stereo resolution is 1080p30.

15.2.8 Secondary Camera Video Resolution

Maximum secondary camera video resolution is 1080p30.

15.2.9 Bit Depth

Capable of processing 14-bit images at the stated performance levels.

Capable of processing 18-bit images at half the performance levels, i.e. process on-
the-fly 16 Mpixel 18-bit images at 7 fps instead of 15 fps.

Capable of processing up to 18-bit precision.

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The higher precision processing will be employed mainly for high dynamic range
imaging (HDR).

15.3 Imaging Subsystem Integration

Figure 98. Image Processing Components

x1 data (x3 data)

Lens Sensor 1

Camera I2C 1
SOC

Camera I2C 2
I2C Controller

CPU
Stereo Pair

x2 Data MIPI Dphy Memory

Lens Sensor2 Memory
(x1 data) /RX ISP Controller
Synchronization

JPEG
Video Encode

Camera I2C 3
Camera Sideband<0:11>
GPIO/Camera
x2 data Sidebands
(x1 data)
Lens Sensor3

Camera Peripherals

Pre-
AF Shutter LED Flash
Flash

15.3.1 CPU Core

The CPU core augments the signal processing capabilities of the hardware to perform
post-processing on images such as auto focus, auto white balance, and auto exposure.
The CPU also runs the drivers that control the GPIOs and I2C for sensor control.

15.3.2 Imaging Signal Processor (ISP)

The ISP (Imaging Signal Processor) includes a 64-way vector processor enabling high
quality camera functionality. Key features include support of three camera sensors.

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15.3.2.1 MIPI-CSI-2 Ports

The SoC has three MIPI clock lanes and five MIPI data lanes. The Analog Front End
(AFE) and Digital Physical Layer (DPHY) take these lanes and connects them to three
virtual ports. Two data lanes are dedicated to each of the rear facing cameras and the
remaining one data lane is connected to the front facing camera. The MIPI interfaces
follow the MIPI-CSI-2 specifications as defined by the MIPI Alliance. They support
YUV420, YUV422, RGB444, RGB555, RGB565, and RAW 8b/10b/12b. Both MIPI ports
support compression settings specified in MIPI-CSI-2 draft specification 1.01.00 Annex
E. The compression is implemented in Hardware with support for Predictor 1 and
Predictor 2. Supported compression schemes:
• 12-8-12
• 12-7-12
• 12-6-12
• 10-8-10
• 10-7-10
• 10-6-10

The data compression schemes above use an X-Y-Z naming convention where X is the
number of bits per pixel in the original image, Y is the encoded (compressed) bits per
pixel and Z is the decoded (uncompressed) bits per pixel.

15.3.2.2 I2C for Camera Interface

The platform supports three (3) I2C ports for the camera interface. These ports are
used to control the camera sensors and the camera peripherals such as flash LED and
lens motor.

15.3.2.3 Camera Sideband for Camera Interface

Twelve (12) GPIO signals are allocated for camera functions, refer to Table 164 for
signal names. These GPIOs are multiplexed and are available for other usages without
powering on the ISP. The ISP provides a timing control block through which the GPIOs
can be controlled to support assertion, de-assertion, pulse widths and delay. The
configuration below of camera GPIOs is just an example of how the GPIOs can be used.
Several of these functions could be implemented using I2C, depending on the sensor
implementation for the platform.
• Sensor Reset signals
—Force hardware reset on one or more of the sensors.
• Sensor Single Shot Trigger signal
—Indicate that the target sensor needs to send a full frame in a single shot mode,
or to capture the full frame for flash synchronization.
• PreLight Trigger signal
—Light up a pilot lamp prior to firing the flash for preventing red-eye.
• Flash Trigger signal
—Indicate that a full frame is about to be captured. The Flash fires when it detects
an assertion of the signal.

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• Sensor Strobe Trigger signal

—Asserted by the target sensor to indicate the start of a full frame, when it is
configured in the single shot mode, or to indicate a flash exposed frame for
flash synchronization.

15.4 Functional Description

At a high level, the Camera Subsystem supports the following modes:
• Preview
• Image capture
• Video capture

15.4.1 Preview Mode

Once the ISP and the camera subsystem is enabled, the ISP goes into the preview
mode where very low resolution frames, such as VGA/480p (programmable), are being
processed.

15.4.2 Image Capture

During the image capture mode, the camera subsystem can acquire at a peak
throughput of 24 Mpixels @ 15fps. While doing this, it continues to output preview
frames simultaneously.
• The ISP can output RAW, RGB or YUV formats. The ISP can capture one full frame
at a time or perform burst mode capture, where up to five full back-to-back frames
are recorded.
• The ISP will not limit the number of back-to-back full frames captured, but the
number is programmable and determined on how much memory can be allocated
dynamically.
• The ISP can process all the frames on the fly and writes to memory only after fully
processing the frames, without requiring download of any part of the frame for
further processing.
—The exceptions to this approach are image stabilization and some other advanced
functions requiring temporal information over multiple frames.

The ISP can support image stabilization in image capture model.

• The ISP initially outputs preview frames.
• When the user decides to capture the picture, image stabilization is enabled. The
ISP checks the previous frame for motion and compensates for it appropriately.

Auto Exposure (AE), Auto Focus (AF), and Auto White Balance (AWB), together known
as 3A, are implemented in the CPU to provide flexibility.

15.4.3 Video Capture

During video recording, the ISP can capture video up to 1080p @ 60 fps and output
preview frames concurrently. The ISP output video frames to memory in YUV420 or
YUV422 format.

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15.4.4 ISP Overview

The Camera Subsystem consists of 2 parts, the hardware subsystem and a software
stack that implements the ISP functionality on top of this hardware.

The core of the ISP is a vector processor. The vector processor is supported by the
following components:
• Interfaces for data and control
• A small input formatter that parallelizes the data
• A scalar (RISC) processor, for system control and low-rate processing
• An accelerator for scaling, digital zoom, and lens distortion correction
• A DMA engine transfers large amounts of data such as input and output image data
or large parameter sets between LPDDR2 and the ISP block.

15.4.5 Memory Management Unit (MMU)

The camera subsystem has capabilities to deal with a virtual address space, since a
contiguous memory range in the order 16–32MB cannot be guaranteed by the OS.

15.4.5.1 Interface
The MMU performs the lookup required for address translation from a virtual to physical
32-bit address. The lookup tables are stored external to the system. The MMU performs
the lookup through a master interface without burst support that is connected to the
Open Core Protocol (OCP) master of the subsystem. The MMU configuration registers
can be accessed through a 32-bit Core I/O (CIO) slave interface. Additionally there is a
32-bit CIO slave interface connected to the address translator.

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15.5 MIPI-CSI-2 Receiver

MIPI-CSI-2 devices are camera serial interface devices. They are categorized into two
types, a CSI transmitter device with Camera Control Interface (CCI) slave and CSI
receiver device with CCI master.

Data transfer by means of MIPI-CSI is unidirectional that is, from transmitter to

receiver. CCI data transfer is bidirectional between the CCI slave and master.

Camera Serial Interface Bus (CSI) is a type of serial bus that enables transfer of data
between a Transmitter device and a receiver device. The CSI device has a point-to-
point connections with another CSI device by means of D-PHYs and as shown in
Figure 99.

Similarly, CCI (Camera Control Interface bus) is a type of serial bus that enables
transfer back and forth between the master CCI and a Slave CCI Unit.

Figure 99. MIPI-CSI Bus Block Diagram

Device e.g. a Camera containing Unidirectional High Device e.g. an application engine
the CSI transmitter and CCI slave Speed Data Link or base band containing the CSI
receiver and the CCI master
N Data Lanes
CSI Transmitter Where N may be
CSI Receiver
1, 2, 3, or 4
DataN+ DataN+
DataN- DataN-

Data1+ Data1+
Data1- Data1-

Clock+ Clock+
Clock- Clock-

CCI Slave 400kHz Bidirectional CCI Master

Control Link
SCL SCL
SDA SDA

D-PHY data lane signals are transferred point-to-point differentially using two signal
lines and a clock lane. There are two signaling modes, a high speed mode that operates
at 1000Mbs and a low power mode that works at 10Mbs. The mode is set to low power
mode and a stop state at start up/power up. Depending on the desired data transfer
type, the lanes switch between high and low power modes.

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The CCI interface consists of an I2C bus which has a clock line and a bidirectional data
line.

The MIPI-CSI-2 devices operate in a layered fashion. There are 5 layers identified at
the receiver and transmitter ends.

MIPI-CSI-2 Functional Layers:

• PHY Layer:
— An embedded electrical layer sends and detects start of packet signalling and
end of packet signalling on the data lanes. It contains a serializer and
deserializer unit to interface with the PPI / lane management unit. There is also
a clock divider unit to source and receive the clock during different modes of
operation.
• PPI/Lane Management Unit:
— This layer does the lane buffering and distributes the data in the lanes as
programmed in a round robin manner and also merges them for the PLI/Low
Level Protocol unit.
• PLI/Low Level Protocol Unit:
— This layer packetizes as well as de-packetizes the data with respect to channels,
frames, colors and line formats. There are ECC generator and corrector units to
recover the data free from errors in the packet headers. There is also a CRC
checker or CRC generator unit to pack the payload data with CRC checksum bits
for payload data protection.
• Pixel/Byte to Byte/Pixel Packing Formats:
— Conversion of pixel formats to data bytes in the payload data is done depending
on the type of image data supported by the application. It also re-converts the
raw data bytes to pixel format understandable to the application layer.
• Application:
— Depending on the type of formats, camera types, capability of the camera used
by the transmitter, the application layer recovers the image formats and
reproduces the image in the display unit. It also works on de-framing the data
into pixel-to-packing formats. High level encoding and decoding of image data is
handled in the application unit.

15.5.1 MIPI-CSI-2 Receiver Features

CSI Features:
• Compliant to CSI-2 MIPI specification for Camera Serial Interface (Version 1.00)
• Supports standard D-PHY transceiver compliant to the MIPI Specification
• Supports PHY data programmability up to four lanes.
• Supports PHY data time-out programming.
• Has controls to start and re-start the CSI-2 data transmission for synchronization
failures and to support recovery.

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• The ISP may not support all the data formats that the CSI-2 receiver can handle.
—Refer to Table 165 for formats supported by the ISP
• Supports all generic short packet data types.
• Single Image Signal Processor interface for pixel transfers to support multiple
image streams for all virtual channel numbers.

D-PHY Features:
• Supports synchronous transfer in high speed mode with a bit rate of 80-1000Mb/s
• Supports asynchronous transfer in low power mode with a bit rate of 10Mb/s.
• Differential signalling for HS data
• Spaced one-hot encoding for Low Power [LP] data
• Data lanes support transfer of data in high speed as well as low power modes.
• Supports ultra low power mode, escape mode, and high speed mode
• Has a clock divider unit to generate clock for parallel data reception and
transmission from and to the PPI unit.
• Activates and disconnects high speed terminators for reception and control mode.
• Activates and disconnects low power terminators for reception and transmission.

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15.6 Register Map

Refer to Chapter 3, “Register Access Methods” and Chapter 4, “Mapping Address
Spaces” for additional information.

Figure 100.MIPI CSI Register Map

PCI Space

CPU
Core

SoC Transaction
Router
D:0,F:0
PCI
CAM
Graphics
(I/O)
D:2,F:0
Bus 0
PCI
ECAM
Camera ISP
(Mem)
D:3,F:0

#1 D:16,F:0
xHCI USB
MMC
SD/

D:20,F:0 #2 D:17,F:0
#3 D:18,F:0

USB Dev
D:22,F:0 SATA
D:19,F:0 Memory
Camera ISP Space
PCI Header
DMA F:0 D:3,F:0
I2C0 F:1
I2C1 F:2
SIO D:24

LPE Audio (I2S)

I2C2 F:3
D:21,F:0
I2C3 F:4
I2C4 F:5 ISPMMADR
I2C5 F:6
I2C6 F:7 Trusted Execution
ISP
Engine (TXE)
Registers
D:26,F:0
RP1 F:0
PCIe D:28

RP2 F:1
RP3 F:2
HDA
RP4 F:3 D:27,F:0

EHCI USB DMA F:0

D:29,F:0
PWM1 F:1
SIO D:30

PWM2 F:2
LPC (iLB) F:0 HSUART1 F:3
D:31
PCU

HSUART2 F:4
SMB F:3 SPI F:5

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15.7 Image Signal Processor PCI Configuration Registers

Table 166. Summary of Image Signal Processor PCI Configuration Registers—0/2/0

Default
Offset Size Register ID—Description
Value

0h 4 “iunit_ID_type (ID)—Offset 0h” on page 886 0F388086h

4h 4 “iunit_PCICMDSTS_type (PCICMDSTS)—Offset 4h” on page 886 00100000h

8h 4 “iunit_RIDCC_type (RIDCC)—Offset 8h” on page 887 04800001h
Ch 4 “iunit_HDR_type (HDR)—Offset Ch” on page 888 00000000h

10h 4 “iunit_ISPMMADR_type (ISPMMADR)—Offset 10h” on page 888 00000000h

2Ch 4 “iunit_SSID_type (SSID)—Offset 2Ch” on page 889 00000000h
34h 4 “iunit_CAPPOINT_type (CAPPOINT)—Offset 34h” on page 889 00000080h

3Ch 4 “iunit_INTR_type (INTR)—Offset 3Ch” on page 889 00000000h

80h 4 “iunit_PMCAP_type (PMCAP)—Offset 80h” on page 890 00229001h
84h 4 “iunit_PMCS_type (PMCS)—Offset 84h” on page 891 00000000h

90h 4 “iunit_MSI_CAPID_type (MSI_CAPID)—Offset 90h” on page 891 00000005h

94h 4 “iunit_MSI_ADDRESS_type (MSI_ADDRESS)—Offset 94h” on page 892 00000000h
98h 4 “iunit_MSI_DATA_type (MSI_DATA)—Offset 98h” on page 893 00000000h

“iunit_INTERRUPT_CONTROL_type (INTERRUPT_CONTROL)—Offset 9Ch” on

9Ch 4 00000100h
page 893
B0h 4 “iunit_PERF0_type (PERF0)—Offset B0h” on page 894 00000000h

B4h 4 “iunit_PERF1_type (PERF1)—Offset B4h” on page 895 00000000h

B8h 4 “iunit_PERF2_type (PERF2)—Offset B8h” on page 895 00000000h
BCh 4 “iunit_PERF3_type (PERF3)—Offset BCh” on page 896 00000000h

C0h 4 “iunit_MISR0_type (MISR0)—Offset C0h” on page 896 FFFFFFFFh

C4h 4 “iunit_MISR1_type (MISR1)—Offset C4h” on page 897 FFFFFFFFh
C8h 4 “iunit_MISR2_type (MISR2)—Offset C8h” on page 897 FFFFFFFFh

CCh 4 “iunit_MISR3_type (MISR3)—Offset CCh” on page 898 FFFFFFFFh

“iunit_MANUFACTURING_ID_type (MANUFACTURING_ID)—Offset D0h” on
D0h 4 00000000h
page 898
“iunit_IUNIT_ACCESS_CTRL_VIOL_type (IUNIT_ACCESS_CTRL_VIOL)—Offset D4h”
D4h 4 00000000h
on page 898

“iunit_IUNIT_DEADLINE_STATUS_type (IUNIT_DEADLINE_STATUS)—Offset D8h”

D8h 4 00000000h
on page 899
“iunit_IUNIT_AFE_HS_CONTROL_type (IUNIT_AFE_HS_CONTROL)—Offset DCh” on
DCh 4 64000A00h
page 900
“iunit_IUNIT_AFE_RCOMP_CONTROL_type (IUNIT_AFE_RCOMP_CONTROL)—Offset
E0h 4 00000000h
E0h” on page 901

“iunit_IUNIT_AFE_TRIM_CONTROL_type (IUNIT_AFE_TRIM_CONTROL)—Offset
E4h 4 00000000h
E4h” on page 902
“iunit_IUNIT_CSI_CONTROL_type (IUNIT_CSI_CONTROL)—Offset E8h” on
E8h 4 000003F8h
page 903
“iunit_IUNIT_DEADLINE_CONTROL_type (IUNIT_DEADLINE_CONTROL)—Offset
ECh 4 040A0100h
ECh” on page 904

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Table 166. Summary of Image Signal Processor PCI Configuration Registers—0/2/0

Default
Offset Size Register ID—Description
Value

“iunit_IUNIT_RCOMP_STATUS_type (IUNIT_RCOMP_STATUS)—Offset F0h” on

F0h 4 16161616h
page 905
“iunit_IUNIT_RCOMP_CONTROL_type (IUNIT_RCOMP_CONTROL)—Offset F4h” on
F4h 4 00200001h
page 906
F8h 4 “iunit_IUNIT_STATUS_type (IUNIT_STATUS)—Offset F8h” on page 907 0000EB01h
FCh 4 “iunit_IUNIT_CONTROL_type (IUNIT_CONTROL)—Offset FCh” on page 908 00000103h

15.7.1 iunit_ID_type (ID)—Offset 0h

PCI Device and Vendor ID Register

Access Method
Type: PCI Configuration Register
ID: [B:0, D:3, F:0] + 0h
(Size: 32 bits)

Default: 0F388086h
31 28 24 20 16 12 8 4 0

0 0 0 0 1 1 1 1 0 0 1 1 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0
DIDL

VID
DIDH

Bit Default &

Description
Range Access

01E7h DIDH: DEVICE_IDENTIFICATION_NUMBER_HIGH: Upper bits of ISP Device ID.

31:19 Connected to straps at IUNIT top level. (Tangier IUNIT Device IDs range from 16'h1178
RO through 16'h117F. Valleyview IUNIT Device IDs range from 16'h0F38 through 16'h0F3F.)

000b DIDL: DEVICE_IDENTIFICATION_NUMBER_LOW: Lower bits of ISP Device ID.

18:16 Connected to fuse FB_isp_device_id. (Tangier IUNIT Device IDs range from 16'h1178
RO through 16'h117F. Valleyview IUNIT Device IDs range from 16'h0F38 through 16'h0F3F.)
8086h
15:0 VID: VENDOR_IDENTIFICATION_NUMBER: PCI standard identification for Intel.
RO

15.7.2 iunit_PCICMDSTS_type (PCICMDSTS)—Offset 4h

PCI Command and Status Register

Access Method
Type: PCI Configuration Register PCICMDSTS: [B:0, D:3, F:0] + 4h
(Size: 32 bits)

Default: 00100000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IS

BME
MSE
RSVD_31_21

CAP

RSVD_18_11

RSVD_9_3

RSVD_0_0
ID

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Bit Default &

Description
Range Access

0h
31:21 RSVD_31_21: Reserved
RO

1b CAP: CAPABILITY_LIST: Indicates that the CAPPOINT register at 34h provides an offset
20 into PCI Configuration Space containing a pointer to the location of the first item in the
RO list.
0b IS: INTERRUPT_STATUS: Reflects the state of the interrupt in the camera device. Is set
19
RO to 1 if IER and IIR are both set. Otherwise is set to 0.

0h
18:11 RSVD_18_11: Reserved
RO
ID: INTERRUPT_DISABLE: When 1, blocks the sending of ASSERT_INTA and
0b DEASSERT_INTA messages to the Intel Legacy Block (ILB). The interrupt status is not
10
RW blocked from being reflected in PCICMDSTS.IS. When 0, permits the sending of
ASSERT_INTA and DEASSERT_INTA messages to the ILB.

0h
9:3 RSVD_9_3: Reserved
RO

0h BME: BUS_MASTER_ENABLE: Enables ISP to function as a PCI compliant master. When

2
RW 0, blocks the sending of MSI interrupts. When 1, permits the sending of MSI interrupts.

MSE: MEMORY_SPACE_ENABLE: When set, accesses to this device's memory space is

0h enabled. When 1, the ISP will compare the incoming address on the IOSF bus with
1 ISPMMADR(31:22). If there is a match and if the IOSF command is either a MEMRD or
RW MEMWR, the ISP will select the command and present it on the AHB bus. When 0, the
ISP will not claim MEMRD or MEMWR IOSF commands.
0h
0 RSVD_0_0: Reserved
RO

15.7.3 iunit_RIDCC_type (RIDCC)—Offset 8h

Revision Identification and Class Codes

Access Method
Type: PCI Configuration Register
(Size: 32 bits) RIDCC: [B:0, D:3, F:0] + 8h

Default: 04800001h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
BCC

SCC

PI

RID

Bit Default &

Description
Range Access

04h
31:24 BCC: BASE_CLASS_CODE: Indicates a multimedia device.
RO
80h
23:16 SCC: SUB_CLASS_CODE: Indicates other multimedia device.
RO
0h
15:8 PI: PROGRAMMING_INTERFACE: Default programming interface.
RO
01h RID: REVISION_ID: The value in this field reflects the value of strapRID(7:0) (which is
7:0
RO an input pin of ISP) and can be changed with each stepping of the silicon.

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15.7.4 iunit_HDR_type (HDR)—Offset Ch

Header Type

Access Method
Type: PCI Configuration Register
(Size: 32 bits) HDR: [B:0, D:3, F:0] + Ch

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSVD_31_24

MFUNC

RSVD_15_0
HDR
Bit Default &
Description
Range Access

0h
31:24 RSVD_31_24: Reserved
RO
0h
23 MFUNC: MULTI_FUNCTION_STATUS: IUNIT is a single function.
RO
0h
22:16 HDR: HEADER_CODE: Indicates a type 0 header format.
RO
0h
15:0 RSVD_15_0: Reserved
RO

15.7.5 iunit_ISPMMADR_type (ISPMMADR)—Offset 10h

Memory Mapped Address Range. This is the base address for all memory mapped
registers.

Access Method
Type: PCI Configuration Register
(Size: 32 bits) ISPMMADR: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BA

RSVD_21_0

Bit Default &

Description
Range Access

BA: BASE_ADDRESS: Set by the OS, these bits correspond to address signals (31:22).
0h The ISP will compare the IOSF address (31:22) with ISPMMADR(31:22). If there is a
31:22 match, and PCICMDSTS(1) = MSE = 1 and the IOSF command is either a MEMRD or
RW MEMWR, the ISP will select the command and present it on the AHB bus to the vendor
IP.

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Bit Default &

Description
Range Access

0h
21:0 RSVD_21_0: Reserved
RO

15.7.6 iunit_SSID_type (SSID)—Offset 2Ch

Subsystem Identifiers

Access Method
Type: PCI Configuration Register
(Size: 32 bits) SSID: [B:0, D:3, F:0] + 2Ch

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SSID
Bit Default &
Description
Range Access

0h SSID: SUBSYSTEM_IDENTIFIERS: The value in this field is a copy of the SSID register
31:0 programmed by the graphics device driver or BIOS in the Device 0/2/0 PCI header. To
RO change the subsystem ID, write to Device 0/2/0 SSID instead of to this SSID.

15.7.7 iunit_CAPPOINT_type (CAPPOINT)—Offset 34h

Capabilities Pointer

Access Method
Type: PCI Configuration Register
CAPPOINT: [B:0, D:3, F:0] + 34h
(Size: 32 bits)

Default: 00000080h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
RSVD_31_8

CAP

Bit Default &

Description
Range Access

0h
31:8 RSVD_31_8: Reserved
RO

80h
7:0 CAP: CAPABILITIES_POINTER: The first item in the capabilities list is at address 80h.
RO

15.7.8 iunit_INTR_type (INTR)—Offset 3Ch

Interrupt. This register is programmed by SBIOS.

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Access Method
Type: PCI Configuration Register
INTR: [B:0, D:3, F:0] + 3Ch
(Size: 32 bits)

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RSVD_31_16

IPIN

ILIN
Bit Default &
Description
Range Access

0h
31:16 RSVD_31_16: Reserved
RO

IPIN: INTERRUPT_PIN: PCI Device 0/3/0 (IUNIT) is a single function device. If INTx is
0h used, the PCI spec requires that it use INTA#. If INTx is used (FB_intx_supported fuse
15:8
RO is 1), then this field is hard coded to 01h. If INTx is not used (FB_intx_supported fuse is
0), this field is hard coded to 00h.
0h ILIN: INTERRUPT_LINE: BIOS written value to communicate interrupt line routing
7:0
RW information to the ISP device driver.

15.7.9 iunit_PMCAP_type (PMCAP)—Offset 80h

Power Management Capabilities

Access Method
Type: PCI Configuration Register
PMCAP: [B:0, D:3, F:0] + 80h
(Size: 32 bits)

Default: 00229001h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1
RSVD_24_22

DSI

RSVD_20_19
PMES

D2S
D1S

VS

CAPID
NEXT_CAP

Bit Default &

Description
Range Access

0h
31:27 PMES: PME_SUPPORT: The camera controller does not generate PME#.
RO
0h
26 D2S: D2_SUPPORT: The D2 power management state is not supported.
RO
0h
25 D1S: D1_SUPPORT: The D1 power management state is not supported.
RO
0h
24:22 RSVD_24_22: Reserved
RO

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Bit Default &

Description
Range Access

01h DSI: DEVICE_SPECIFIC_INITIALIZATION: Hardwired to 1 to indicate that special

21 initialization of the camera controller is required before generic class device driver is to
RO use it.
0h
20:19 RSVD_20_19: Reserved
RO
2h VS: VERSION: Indicates compliance with revision 1.1 of the PCI Power Management
18:16
RO Specification.

90h NEXT_CAP: POINTER_TO_NEXT_CAPABILITY: Indicates the next item in the

15:8
RO capabilities list.

01h
7:0 CAPID: CAPABILITIES: SIG defines this ID is 01h for power management.
RO

15.7.10 iunit_PMCS_type (PMCS)—Offset 84h

Power Management Control/Status.

Access Method
Type: PCI Configuration Register
(Size: 32 bits) PMCS: [B:0, D:3, F:0] + 84h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PS
RSVD_31_2

Bit Default &

Description
Range Access

0h
31:2 RSVD_31_2: Reserved
RO

0h PS: POWER_STATE: Power management is implemented by writing to control registers

1:0 in the PUNIT. This field may be programmed by the software driver, but no action is
RW taken based on writing to this field.

15.7.11 iunit_MSI_CAPID_type (MSI_CAPID)—Offset 90h

Message Signaled Interrupts Capability ID and Control Register

Access Method
Type: PCI Configuration Register
MSI_CAPID: [B:0, D:3, F:0] + 90h
(Size: 32 bits)

Default: 00000005h

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31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

MME

CAPID
MSIE
RSVD_31_24

MMC
C64

NEXT_CAP
Bit Default &
Description
Range Access

0h
31:24 RSVD_31_24: Reserved
RO
0h
23 C64: 64_BIT_ADDRESS_CAPABLE: 32-bit capable only.
RO
0h MME: MULTIPLE_MESSAGE_ENABLE: This field is RW for software compatibility, but
22:20
RW only a single message is ever generated.

0h
19:17 MMC: MULTIPLE_MESSAGE_CAPABLE: This device is only single message capable.
RO
MSIE: MSI_ENABLE: If set, MSI is enabled. PCICMDSTS.BME must be set for an MSI to
0h be generated.When 0, blocks the sending of a MSI interrupt. The interrupt status is not
16
RW blocked from being reflected in the PCICMDSTS.IS bit. When 1, permits sending of a
MSI interrupt.

0h
15:8 NEXT_CAP: POINTER_TO_NEXT_CAPABILITY: Indicates this is the last item in the list.
RO

05h
7:0 CAPID: CAPABILITY_ID: Indicates an MSI capability.
RO

15.7.12 iunit_MSI_ADDRESS_type (MSI_ADDRESS)—Offset 94h

MSI Message Address

Access Method
Type: PCI Configuration Register MSI_ADDRESS: [B:0, D:3, F:0] + 94h
(Size: 32 bits)

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSVD_1_0
MA

Bit Default &

Description
Range Access

0h MA: MSI_ADDRESS: System specified message address, always DW aligned. When the
31:2 ISP issues an MSI interrupt as a MEMWR on the IOSF, the memory address used is
RW 12xFEE, MSI_ADDRESS[19:0].
0h
1:0 RSVD_1_0: Reserved
RO

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15.7.13 iunit_MSI_DATA_type (MSI_DATA)—Offset 98h

MSI Message Data

Access Method
Type: PCI Configuration Register
(Size: 32 bits) MSI_DATA: [B:0, D:3, F:0] + 98h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MD
RSVD_31_16

Bit Default &

Description
Range Access

0h
31:16 RSVD_31_16: Reserved
RO
MD: MSI_DATA: This 16-bit field is programmed by system software and is driven onto
0h the lower word of data during the data phase of the MSI write transaction. When the ISP
15:0
RW issues an MSI interrupt as a MEMWR on the IOSF, the write data corresponds to the
value of this field.

15.7.14 iunit_INTERRUPT_CONTROL_type (INTERRUPT_CONTROL)—

Offset 9Ch
INTERRUPT_CONTROL

Access Method
Type: PCI Configuration Register INTERRUPT_CONTROL: [B:0, D:3, F:0] + 9Ch
(Size: 32 bits)

Default: 00000100h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
RSVD_31_25

RSVD_23_17

RSVD_15_9

RSVD_7_1
IER

IIR

IMR

ISR

Bit Default &

Description
Range Access

0h
31:25 RSVD_31_25: Reserved
RO

Intel® Atom™ Processor E3800 Product Family

Datasheet 893
 MIPI-Camera Serial Interface (CSI) & ISP

Bit Default &

Description
Range Access

IER: IER: This is an enable bit that allows the sending of an interrupt to the CPU using
either MSI or INTR mechanisms. The interrupt is sent immediately to the CPU. The
firmware running on the ISP guarantees ordering by reading the last data write from
memory before raising the interrupt. 1 = If MSI_ENABLE is set, then an MSI is sent to
0h the CPU when the IIR bit is set, or if the IIR bit remains set after software writes to this
24 register. If INTERRUPT_DISABLE is not set, then an ASSERT_INTA message is sent to
RW the Intel Legacy Block (ILB) when the IIR bit is set by hardware, or if the IIR bit remains
set after software writes to this register. If software clears the IIR bit, and
INTERRUPT_DISABLE is not set then a DEASSERT_INTA message is sent to the ILB. 0 =
Do not generate an MSI even if the MSI_ENABLE bit is set. Do not send ASSERT_INTA or
DEASSERT_INTA messages to the ILB even if the INTERRUPT_DISABLE bit is not set.

0h
23:17 RSVD_23_17: Reserved
RO

IIR: IIR: This is the persistent value of the interrupt bit. It is set by hardware, and
0h cleared by software. Software must write a 1 to clear this bit. Writing a 0 is a NOP. If
16 both software and hardware attempt to write to this field in the same clock cycle,
RW/1C hardware wins. 1 = An interrupt was received from the vendor IP when the IMR bit was
not set, and software has not yet cleared it. 0 = There is no pending interrupt.
0h
15:9 RSVD_15_9: Reserved
RO
1b IMR: IMR: Interrupt Mask bit. 1 = IIR bit will not be set when the ISR bit is set. 0 = IIR
8
RW bit will be set when the ISR bit is set.

0h
7:1 RSVD_7_1: Reserved
RO
0h ISR: ISR: Reflects the state of the interrupt line from the vendor IP, after it is
0
RO synchronized to the czclk domain.

15.7.15 iunit_PERF0_type (PERF0)—Offset B0h

Performance

Access Method
Type: PCI Configuration Register PERF0: [B:0, D:3, F:0] + B0h
(Size: 32 bits)

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CRIFLO

Bit Default &

Description
Range Access

CRIFLO: IUNIT has four performance counters. When counting is enabled, the 11-bit
reads_in_flight counter keeps track of the number of outstanding reads that have been
requested, but not yet returned back at the OCP master interface. The 11-bit
max_reads_in_flight counter keeps track of the maximum number of reads in flight in
0h any given clock cycle. Each clock cycle, if there are any reads in flight, the
31:0 reads_in_fight counter is added to a 64-bit cumulative_reads_in_flight counter, and the
RW/SE 48-bit active_cycles counter is incremented by 1. Reading this register returns bits 31:0
of the cumulative_reads_in_flight counter. This counter should be read only after
counting is disabled. Reading while the counters are enabled will return undefined
values. All four counters are disabled at reset. Writing (any value) to this register, will
enable all four counters.

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MIPI-Camera Serial Interface (CSI) & ISP

15.7.16 iunit_PERF1_type (PERF1)—Offset B4h

Performance

Access Method
Type: PCI Configuration Register
(Size: 32 bits) PERF1: [B:0, D:3, F:0] + B4h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CRIFHI
Bit Default &
Description
Range Access

CRIFHI: IUNIT has four performance counters. When counting is enabled, the 11-bit
reads_in_flight counter keeps track of the number of outstanding reads that have been
requested, but not yet returned back at the OCP master interface. The 11-bit
max_reads_in_flight counter keeps track of the maximum number of reads in flight in
0h any given clock cycle. Each clock cycle, if there are any reads in flight, the
31:0 reads_in_fight counter is added to a 64-bit cumulative_reads_in_flight counter, and the
RW/SE 48-bit active_cycles counter is incremented by 1. Reading this register returns bits
63:32 of the cumulative_reads_in_flight counter. This counter should be read only after
counting is disabled. Reading while the counters are enabled will return undefined
values. All four counters are disabled at reset. Writing (any value) to this register, will
disable all four counters.

15.7.17 iunit_PERF2_type (PERF2)—Offset B8h

Performance

Access Method
Type: PCI Configuration Register
(Size: 32 bits) PERF2: [B:0, D:3, F:0] + B8h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ACLO

Bit Default &

Description
Range Access

ACLO: IUNIT has four performance counters. When counting is enabled, the 11-bit
reads_in_flight counter keeps track of the number of outstanding reads that have been
requested, but not yet returned back at the OCP master interface. The 11-bit
max_reads_in_flight counter keeps track of the maximum number of reads in flight in
0h any given clock cycle. Each clock cycle, if there are any reads in flight, the
31:0 reads_in_fight counter is added to a 64-bit cumulative_reads_in_flight counter, and the
RW/SE 48-bit active_cycles counter is incremented by 1. Reading this register returns bits 31:0
of the active_cycles counter. This counter should be read only after counting is disabled.
Reading while the counters are enabled will return undefined values. All four counters
are disabled at reset. Writing (any value) to this register, will clear all four counters. The
counters should only be cleared after they are disabled.

Intel® Atom™ Processor E3800 Product Family

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 MIPI-Camera Serial Interface (CSI) & ISP

15.7.18 iunit_PERF3_type (PERF3)—Offset BCh

Performance

Access Method
Type: PCI Configuration Register
(Size: 32 bits) PERF3: [B:0, D:3, F:0] + BCh

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSVD_31_27

MRIF

ACHI
Bit Default &
Description
Range Access

0h
31:27 RSVD_31_27: Reserved
RO
MRIF: IUNIT has four performance counters. When counting is enabled, the 11-bit
reads_in_flight counter keeps track of the number of outstanding reads that have been
requested, but not yet returned back at the OCP master interface. The 11-bit
max_reads_in_flight counter keeps track of the maximum number of reads in flight in
any given clock cycle. Each clock cycle, if there are any reads in flight, the
0h reads_in_fight counter is added to a 64-bit cumulative_reads_in_flight counter, and the
26:16
RW/SE 48-bit active_cycles counter is incremented by 1. Reading this register returns bits 11:0
of the max_reads_in_flight counter. This counter should be read only after counting is
disabled. Reading while the counters are enabled will return undefined values. All four
counters are disabled at reset. Writing (any value) to this register, will clear the
max_reads_in_flight counters only. The counters should only be cleared after they are
disabled.
ACHI: IUNIT has four performance counters. When counting is enabled, the 11-bit
reads_in_flight counter keeps track of the number of outstanding reads that have been
requested, but not yet returned back at the OCP master interface. The 11-bit
max_reads_in_flight counter keeps track of the maximum number of reads in flight in
any given clock cycle. Each clock cycle, if there are any reads in flight, the
0h reads_in_fight counter is added to a 64-bit cumulative_reads_in_flight counter, and the
15:0
RW/SE 48-bit active_cycles counter is incremented by 1. Reading this register returns bits
47:32 of the active_cycles counter. This counter should be read only after counting is
disabled. Reading while the counters are enabled will return undefined values. All four
counters are disabled at reset. Writing (any value) to this register, will clear the
max_reads_in_flight counters only. The counters should only be cleared after they are
disabled.

15.7.19 iunit_MISR0_type (MISR0)—Offset C0h

OCP Master Write Data

Access Method
Type: PCI Configuration Register MISR0: [B:0, D:3, F:0] + C0h
(Size: 32 bits)

Default: FFFFFFFFh

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MIPI-Camera Serial Interface (CSI) & ISP

31 28 24 20 16 12 8 4 0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

MISR0
Bit Default &
Description
Range Access

FFFFFFFFh MISR0: MISR0: Write to this register address clears this MISR. This is a 8:1
31:0 compression MISR capturing the 256-bit write data on the OCP interface between
RW/C ISP_CSS and Iunit wrapper.

15.7.20 iunit_MISR1_type (MISR1)—Offset C4h

OCP Master Read Data

Access Method
Type: PCI Configuration Register
(Size: 32 bits) MISR1: [B:0, D:3, F:0] + C4h

Default: FFFFFFFFh
31 28 24 20 16 12 8 4 0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
MISR1

Bit Default &

Description
Range Access

FFFFFFFFh MISR1: MISR1: Write to this register address clears this MISR. This is a 8:1
31:0 compression MISR capturing the 256-bit read return data on the OCP interface between
RW/C ISP_CSS and Iunit wrapper.

15.7.21 iunit_MISR2_type (MISR2)—Offset C8h

OCP Master Address and Control

Access Method
Type: PCI Configuration Register MISR2: [B:0, D:3, F:0] + C8h
(Size: 32 bits)

Default: FFFFFFFFh
31 28 24 20 16 12 8 4 0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
MISR2

Bit Default &

Description
Range Access

FFFFFFFFh MISR2: MISR2: Write to this register address clears this MISR. This is a 4:1
31:0
RW/C compression MISR capturing the control signals on the OCP Master port in the Iunit.

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 MIPI-Camera Serial Interface (CSI) & ISP

15.7.22 iunit_MISR3_type (MISR3)—Offset CCh

Scalar Processor output

Access Method
Type: PCI Configuration Register
(Size: 32 bits) MISR3: [B:0, D:3, F:0] + CCh

Default: FFFFFFFFh
31 28 24 20 16 12 8 4 0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

MISR3
Bit Default &
Description
Range Access

FFFFFFFFh MISR3: MISR3: Write to this register address clears this MISR. This is a 4:1
31:0
RW/C compression MISR capturing the output signals of the Scalar Processor.

15.7.23 iunit_MANUFACTURING_ID_type (MANUFACTURING_ID)—

Offset D0h
Manufacturing ID

Access Method
Type: PCI Configuration Register
(Size: 32 bits) MANUFACTURING_ID: [B:0, D:3, F:0] + D0h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSVD_31_24

MID

Bit Default &

Description
Range Access

0h
31:24 RSVD_31_24: Reserved
RO

0h
23:0 MID: MANUFACTURING_ID: Hardwired to strapMANID(23:0).
RO

15.7.24 iunit_IUNIT_ACCESS_CTRL_VIOL_type
(IUNIT_ACCESS_CTRL_VIOL)—Offset D4h
IUNIT Access control violation register

Access Method
Type: PCI Configuration Register
IUNIT_ACCESS_CTRL_VIOL: [B:0, D:3, F:0] + D4h
(Size: 32 bits)

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MIPI-Camera Serial Interface (CSI) & ISP

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EN_INTR_ACCESS_CTRL_VIOL

SAI_VIOL
MULTIPLE_SAI_VIOL
RSVD_30_21

RSVD_18_15

VIOL_SAI

RSVD_7_7

INITIAL_SAI
Bit Default &
Description
Range Access

0b EN_INTR_ACCESS_CTRL_VIOL: Enable Interrupt on access control violation: When

31 set, the IUNIT will latch violation information into this register and send an interrupt
RW request (opcode 0XEE) and (port 0x04) to the PUNIT.

00h
30:21 RSVD_30_21: Reserved
RO

0b SAI_VIOL: SAI_VIOL: If set, the IUNIT has detected an SAI violation and has captured
20 the status in this register. This bit must be cleared by software in order for IUNIT to
RW capture the next violation.

0b MULTIPLE_SAI_VIOL: If set, more than one SAI violation has been detected in the
19 IUNIT. Status for the 1st violation has been captured in this register. It is recommend
RW that software clear this bit whenever it clears bit[20] of this register.

0h
18:15 RSVD_18_15: Reserved
RO

00h VIOL_SAI: VIOL_SAI: SAI bits that triggered the violation: This 7-bit value indicates
14:8
RW the SAI of the subsequent transaction which caused the violation.

0b
7 RSVD_7_7: Reserved
RO

00h INITIAL_SAI: INITIAL_SAI: This 7-bit value indicates the SAI of the initial transaction
6:0
RW for SAI mismatch error codes.

15.7.25 iunit_IUNIT_DEADLINE_STATUS_type
(IUNIT_DEADLINE_STATUS)—Offset D8h
IUNIT Deadline Status Register

Access Method
Type: PCI Configuration Register
IUNIT_DEADLINE_STATUS: [B:0, D:3, F:0] + D8h
(Size: 32 bits)

Default: 00000000h

Intel® Atom™ Processor E3800 Product Family

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 MIPI-Camera Serial Interface (CSI) & ISP

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SDRAM_WAKEUP_PSTATE

GT
DN
Bit Default &
Description
Range Access

SDRAM_WAKEUP_PSTATE: SDRAM_WAKEUP_PSTATE: State of the SDRAM_WAKEUP

0h state machine. 00b = State machine is idle; 01b = sdram_wakeup seen, waiting for all
31:30 memory transactions in flight to complete; 10b = All memory transactions are
RO completed, waiting for acknowledgement from czclk domain before returning to idle
state;

0h DN: DN: Computed deadline value to be send with the next request on IB PFI bus. This
29:11 is the internal deadline value. The actual deadline that is sent on the IB PFI bus is the
RO maximum of GT+MDD or DN.
0h
10:0 GT: GT: Current value of Global Timer
RO

15.7.26 iunit_IUNIT_AFE_HS_CONTROL_type
(IUNIT_AFE_HS_CONTROL)—Offset DCh
High-speed termination control MIPI CSI DPHY

Access Method
Type: PCI Configuration Register
(Size: 32 bits) IUNIT_AFE_HS_CONTROL: [B:0, D:3, F:0] + DCh

Default: 64000A00h
31 28 24 20 16 12 8 4 0

0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0
HS_CLK_UNGATE_DLY

HS_CLK_EN_DLY

HS_DATA_EN_DLY
RSVD_23_22

CSI3_CLK_HS_TERM_OVRD

CSI2_CLK_HS_TERM_OVRD

CSI1_CLK_HS_TERM_OVRD

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MIPI-Camera Serial Interface (CSI) & ISP

Bit Default &

Description
Range Access

HS_CLK_UNGATE_DLY: HS_CLK_UNGATE_DLY: Delay between the assertion of HS

enable and the ungating of the HS clocks going to the DPHY logic for all clock lanes. HS
64h clocks are gated by default and are ungated after Tclk-settle time. The range of this field
31:24
RW is 0 nsec to 510 nsec in increments of 2 nsec, with reset value 0x64 indicating 200 nsec.
Note that we use czclk to increment the counter, hence the actual delay can be as much
as 10 nsec larger than the programmed value.
0h
23:22 RSVD_23_22: Reserved
RW
CSI3_CLK_HS_TERM_OVRD: CSI3_CLK_HS_TERM_OVRD: Override for HS
termination enable for CSI3 clock lane. 00b = Use the termination enable output from
00b the DPHY IP and gate XOR clocks in high speed mode; 01b = Keep HS termination (and
21:20
RW HS enable) always on; 10b = Generate HS termination by sampling the CP/CN lines
using coreclk and gate XOR clocks in high speed mode; 11b = Use the termination
enable output from the DPHY IP;
CSI2_CLK_HS_TERM_OVRD: CSI2_CLK_HS_TERM_OVRD: Override for HS
termination enable for CSI2 clock lane. 00b = Use the termination enable output from
00b the DPHY IP and gate XOR clocks in high speed mode; 01b = Keep HS termination (and
19:18
RW HS enable) always on; 10b = Generate HS termination by sampling the CP/CN lines
using coreclk and gate XOR clocks in high speed mode; 11b = Use the termination
enable output from the DPHY IP;
CSI1_CLK_HS_TERM_OVRD: CSI1_CLK_HS_TERM_OVRD: Override for HS
termination enable for CSI1 clock lane. 00b = Use the termination enable output from
00b the DPHY IP and gate XOR clocks in high speed mode; 01b = Keep HS termination (and
17:16
RW HS enable) always on; 10b = Generate HS termination by sampling the CP/CN lines
using coreclk and gate XOR clocks in high speed mode; 11b = Use the termination
enable output from the DPHY IP;
HS_CLK_EN_DLY: HS_CLK_EN_DLY: Delay between the assertion of HS termination
0Ah enable and the assertion of HS enable for all clock lanes. The range of this field is 0 nsec
15:8 to 510 nsec in increments of 2 nsec, with reset value 0x0A indicating 20 nsec. Note that
RW we use czclk to increment the counter, hence the actual delay can be as much as 10
nsec larger than the programmed value.
HS_DATA_EN_DLY: HS_DATA_EN_DLY: Delay between the assertion of HS
0h termination enable and the assertion of HS enable for all data lanes. The range of this
7:0 field is 0 nsec to 510 nsec in increments of 2 nsec, with reset value 0x0 indicating 0
RW nsec. Note that we use czclk to increment the counter, hence the actual delay can be as
much as 10 nsec larger than the programmed value.

15.7.27 iunit_IUNIT_AFE_RCOMP_CONTROL_type
(IUNIT_AFE_RCOMP_CONTROL)—Offset E0h
AFE RCOMP control

Access Method
Type: PCI Configuration Register
IUNIT_AFE_RCOMP_CONTROL: [B:0, D:3, F:0] + E0h
(Size: 32 bits)

Default: 00000000h

Intel® Atom™ Processor E3800 Product Family

Datasheet 901
 MIPI-Camera Serial Interface (CSI) & ISP

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ICSI_RCOMPTARGET
RSVD_31_16

RSVD_15_9

ICSI_RCOMPSTATICLEGDIS

RSVD_7_4
Bit Default &
Description
Range Access

0h
31:16 RSVD_31_16: Reserved
RO
0h
15:9 RSVD_15_9: Reserved
RW
0b ICSI_RCOMPSTATICLEGDIS: ICSI_RCOMPSTATICLEGDIS: Disable RCOMP static leg
8
RW in AFE

0h
7:4 RSVD_7_4: Reserved
RW
ICSI_RCOMPTARGET: ICSI_RCOMPTARGET: RCOMP target level range is 70ohm to
0h 130ohm differential impedance. 0000b = 50ohms; 0001b = 30ohms; 0010b = 35ohms;
3:0
RW 0011b = 40ohms; 0100b = 45ohms; 0101b = 55ohms; 0110b = 60ohms; 0111b =
65ohms;

15.7.28 iunit_IUNIT_AFE_TRIM_CONTROL_type
(IUNIT_AFE_TRIM_CONTROL)—Offset E4h
Configurable delay for CSI AFE data/clk lanes

Access Method
Type: PCI Configuration Register IUNIT_AFE_TRIM_CONTROL: [B:0, D:3, F:0] + E4h
(Size: 32 bits)

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ICSI2_HSRXDATATRIM

ICSI1_HSRXDATATRIM
ICSI3_HSRXCLKTRIM

ICSI2_HSRXCLKTRIM

ICSI1_HSRXCLKTRIM

Bit Default &

Description
Range Access

0h ICSI3_HSRXCLKTRIM: ICSI3_HSRXCLKTRIM: Delay for CSI3 clock lane. Refer to the

31:28
RW CSI AFE Circuit Architecture Spec (CAS) for the actual delays for each trim value setting.

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MIPI-Camera Serial Interface (CSI) & ISP

Bit Default &

Description
Range Access

0h ICSI2_HSRXCLKTRIM: ICSI2_HSRXCLKTRIM: Delay for CSI2 clock lane. Refer to the

27:24
RW CSI AFE Circuit Architecture Spec (CAS) for the actual delays for each trim value setting.

0h ICSI2_HSRXDATATRIM: ICSI2_HSRXDATATRIM: Delay for CSI2 data lane. Refer to

23:20 the CSI AFE Circuit Architecture Spec (CAS) for the actual delays for each trim value
RW setting.
0h ICSI1_HSRXCLKTRIM: ICSI1_HSRXCLKTRIM: Delay for CSI1 clock lane. Refer to the
19:16
RW CSI AFE Circuit Architecture Spec (CAS) for the actual delays for each trim value setting.

0h ICSI1_HSRXDATATRIM: ICSI1_HSRXDATATRIM: Delay for CSI1 data lanes. Refer to

15:0 the CSI AFE Circuit Architecture Spec (CAS) for the actual delays for each trim value
RW setting.

15.7.29 iunit_IUNIT_CSI_CONTROL_type (IUNIT_CSI_CONTROL)—

Offset E8h
Control register for MIPI-CSI

Access Method
Type: PCI Configuration Register
(Size: 32 bits) IUNIT_CSI_CONTROL: [B:0, D:3, F:0] + E8h

Default: 000003F8h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0

CSI3_ACTIVE_LANES

CSI2_ACTIVE_LANES

CSI1_ACTIVE_LANES

CSI3_DISABLE
CSI2_DISABLE
CSI1_DISABLE
RSVD_31_20

RSVD_15_10
CSI_PORTCONFIG

Bit Default &

Description
Range Access

0h
31:20 RSVD_31_20: Reserved
RW

0h CSI_PORTCONFIG: CSI_PORTCONFIG: Used to enable the CSI data lanes to CSI ports
19:16 if FB_csi_portconfig_override fuse is set. This field is ignored if
RW FB_csi_portconfig_override fuse is clear.
0h
15:10 RSVD_15_10: Reserved
RW

11b CSI3_ACTIVE_LANES: Used to determine which of the lanes that are enabled by the
9:8 FB_csi_portconfig fuses or the CSI_PORTCONFIG field, are currently being used on the
RW MIPI CSI3 interface. 1=active, 0=inactive.

1b CSI2_ACTIVE_LANES: Used to determine which of the lanes that are enabled by the
7 FB_csi_portconfig fuses or the CSI_PORTCONFIG field, are currently being used on the
RW MIPI CSI2 interface. 1=active, 0=inactive.

1111b CSI1_ACTIVE_LANES: Used to determine which of the lanes that are enabled by the
6:3 FB_csi_portconfig fuses or the CSI_PORTCONFIG field, are currently being used on the
RW MIPI CSI1 interface. 1=active, 0=inactive.
0b CSI3_DISABLE: 1 = Disable MIPI CSI3 interface. 0 = Enable MIPI CSI3 interface if
2
RW FB_csi_portdisable[2] fuse is cleared

Intel® Atom™ Processor E3800 Product Family

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 MIPI-Camera Serial Interface (CSI) & ISP

Bit Default &

Description
Range Access

0b CSI2_DISABLE: 1 = Disable MIPI CSI2 interface. 0 = Enable MIPI CSI2 interface if

1
RW FB_csi_portdisable[1] fuse is cleared

0b CSI1_DISABLE: 1 = Disable MIPI CSI1 interface. 0 = Enable MIPI CSI1 interface if

0
RW FB_csi_portdisable[0] fuse is cleared

15.7.30 iunit_IUNIT_DEADLINE_CONTROL_type
(IUNIT_DEADLINE_CONTROL)—Offset ECh
IUNIT Deadline Control Register

Access Method
Type: PCI Configuration Register
(Size: 32 bits) IUNIT_DEADLINE_CONTROL: [B:0, D:3, F:0] + ECh

Default: 040A0100h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0

DIS_GTP64_CHK
FDD

MDD

DS
DI

RSVD_15_12

RSVD_7_4

IGNORE_WAKEUP
Bit Default &
Description
Range Access

04h FDD: FIRST_DEADLINE_DELAY: Delay between the rising edge of WAKEUP signal and
31:24 the fake deadline that will be specified for the first request of that line. Unit in 250 nsec.
RW Reset value of 8'h04 indicates FDD = 1 usec.
DI: DEADLINE_INCREMENT: Difference in deadline times between adjacent requests. If
0Ah the current request is for 32B, the next deadline will be DI more than the current
23:16 deadline. If the current request is for 64B, the next deadline will be 2*DI more than the
RW current deadline. Unit in 1/1024 usec. Reset value of 8'h0A indicates DI = 9.765625
nsec.
0h
15:12 RSVD_15_12: Reserved
RW

1h MDD: MINIMUM_DEADLINE_DELAY: Minimum separation between current Global Timer

11:8 value and the deadline specified with any request on the PFI interface. Unit is 250 nsec.
RW Reset value of 4'h1 indicates MDD = 250 nsec.
0h
7:4 RSVD_7_4: Reserved
RW
IGNORE_WAKEUP: If clear, then after each rising edge of sdram_wakeup, the OCP
0b master interface is stalled until all reads in flight and all FIFOs are empty and then the
3
RW next deadline is set to GT + FDD. If set, the sdram_wakeup signal from ISP_CSS is
ignored.

0b DIS_GTP64_CHK: If clear, then the PFI interface is stalled whenever the next deadline
2 value exceeds GT + 64 usec. This check is a safety measure to make sure that deadline
RW does not drift too far into the future. If set, this check is not performed.

Intel® Atom™ Processor E3800 Product Family

904 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

Bit Default &

Description
Range Access

DS: DEADLINE_SCHEME: 11b = Reserved; 10b = Reserved; 01b = When WAKEUP is

asserted, FDD is added to the current global timer to compute DN. With each request,
the deadline sent to Pondicherry is either DN, or the sum of the global timer and MDD,
whichever is larger. After each request is sent, DN is computed by adding DI for each
32Byte request sent to either DN or the sum of the global timer and MDD, whichever is
0h larger. Each clock cycle, DN is checked to make sure it is greater than the current global
1:0 timer, else it is set to the global timer.; 00b = When WAKEUP is asserted, FDD is added
RW to the current global timer to compute DN. With each request, the deadline sent to
Pondicherry is either DN, or the sum of the global timer and MDD, whichever is larger.
After each request is sent, DN is computed by adding DI for each 32Byte request sent to
DN. Each cycle, DN is checked to make sure that it is either greater than the current
global timer, or is less than the global timer by no more than 64 usec, else it is set to the
global timer minus 64 usec.

15.7.31 iunit_IUNIT_RCOMP_STATUS_type (IUNIT_RCOMP_STATUS)—

Offset F0h
IUNIT RCOMP Status Register

Access Method
Type: PCI Configuration Register IUNIT_RCOMP_STATUS: [B:0, D:3, F:0] + F0h
(Size: 32 bits)

Default: 16161616h
31 28 24 20 16 12 8 4 0

0 0 0 1 0 1 1 0 0 0 0 1 0 1 1 0 0 0 0 1 0 1 1 0 0 0 0 1 0 1 1 0
CALIB_EXIT_TOGGLE_LIMIT

CALIB_EXIT_0101

CALIB_EXIT_1010
CSI3_RCOMP_UPDATE_VALUE

CSI2_RCOMP_UPDATE_VALUE

CSI1_RCOMP_UPDATE_VALUE

CALIB_EXIT_ERROR

CSI_RCOMP_CALIBRATION_VALUE

Bit Default &

Description
Range Access

CALIB_EXIT_TOGGLE_LIMIT: CALIB_EXIT_TOGGLE_LIMIT: If set, indicates that the

0b last calibration cycle exited because the number of toggles matched the value specified
31
RO by the CSI_HS_ROGGLE_LIMIT_CREG_ENC field of the IUNIT_RCOMP_CONTROL
register.
16h CSI3_RCOMP_UPDATE_VALUE: MIPI CSI3 RCOMP value: Current RCOMP value on
30:24
RO MIPI CSI3 port

0b CALIB_EXIT_0101: CALIB_EXIT_0101: If set, indicates that the last calibration cycle

23
RO exited because the last four states of rcompcountup were 0101

16h CSI2_RCOMP_UPDATE_VALUE: MIPI CSI2 RCOMP value: Current RCOMP value on

22:16
RO MIPI CSI2 port

0b CALIB_EXIT_1010: CALIB_EXIT_1010: If set, indicates that the last calibration cycle

15
RO exited because the last four states of rcompcountup were 1010

Intel® Atom™ Processor E3800 Product Family

Datasheet 905
 MIPI-Camera Serial Interface (CSI) & ISP

Bit Default &

Description
Range Access

16h CSI1_RCOMP_UPDATE_VALUE: MIPI CSI1 RCOMP value: Current RCOMP value on

14:8
RO MIPI CSI1 port

0b CALIB_EXIT_ERROR: CALIB_EXIT_ERROR: If set, indicates that the last calibration

7
RO cycle exited due to an error condition.

16h CSI_RCOMP_CALIBRATION_VALUE: MIPI CSI RCOMP value from last calibration

6:0
RO cycle

15.7.32 iunit_IUNIT_RCOMP_CONTROL_type
(IUNIT_RCOMP_CONTROL)—Offset F4h
MIPI CSI RCOMP control register

Access Method
Type: PCI Configuration Register
(Size: 32 bits) IUNIT_RCOMP_CONTROL: [B:0, D:3, F:0] + F4h

Default: 00200001h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

CSI3_HS_RCOMP_OVR_ENABLE
CSI2_HS_RCOMP_OVR_ENABLE
CSI1_HS_RCOMP_OVR_ENABLE
CSI_HS_CALIB_LOOP_DELAY
CSI_HS_OVR_CLK_GATE_ON_UPDATE

CSI_HS_RCOMP_OVR_CODE
RSVD_31_24

CSI_HS_RCOMP_UPDATE_MODE

RSVD_15_11

CSI_HS_RCOMP_ENABLE
CSI_HS_TOGGLE_LIMIT_CREG_ENC

Bit Default &

Description
Range Access

0h
31:24 RSVD_31_24: Reserved
RW
CSI_HS_OVR_CLK_GATE_ON_UPDATE: CSI_HS_OVR_CLK_GATE_ON_UPDATE: If
0b cleared, the high speed clock going to the digital logic is gated when RCOMP update is
23
RW happening. The clock is gated for a minimum of 100 nsec. If this bit is set, then the high
speed clock is not gated during the update cycle.
CSI_HS_RCOMP_UPDATE_MODE: CSI_HS_RCOMP_UPDATE_MODE: 00b = RCOMP is
01b updated if the clock lane is in LP11 state. 01b = RCOMP is updated if all the data lanes
22:21 are in LP11 state. 10b = RCOMP is updated immediately after calibration is completed,
RW or the CSI[1-3]_HS_RCOMP_OVR_ENABLE bits are written to 1 by software. 11b =
Reserved.

0h CSI_HS_TOGGLE_LIMIT_CREG_ENC: CSI_HS_TOGGLE_LIMIT_CREG_ENC: HS state

20:19 machine toggle limit. Number of times RCOMP state machine will toggle before exiting.
RW 2'b00: 6 toggles; 2'b01: 4 toggles; 2'b10: 8 toggles; 2'b11: 10 toggles;

Intel® Atom™ Processor E3800 Product Family

906 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

Bit Default &

Description
Range Access

CSI_HS_CALIB_LOOP_DELAY: CSI_HS_CALIB_LOOP_DELAY: Delay after applying a

0h new RCOMP value to the AFE, before sampling the count up/down input from the AFE.
18:16 0h=)50-53ns; 1h=)60ns; 2h=)70-72ns; 3h=)80-83ns; 4h=)90ns; 5h=)100-102ns;
RW 6h=)125-128ns; 7h=)150ns. At the start of each RCOMP calibration cycle, the state
machine waits for 8x this delay before starting to sample the count up/down signal.

0h
15:11 RSVD_15_11: Reserved
RW

CSI3_HS_RCOMP_OVR_ENABLE: CSI3_HS_RCOMP_OVR_ENABLE: If set, then the

0b CSI_HS_RCOMP_OVRD field is used as the RCOMP value during the update cycle for CSI
10 port 3. If clear, then the output of the RCOMP calibration engine (stored in
RW CSI_RCOMP_CALIBRATION_VALUE field of IUNIT_RCOMP_STATUS register) is used as
the RCOMP value during the update cycle for CSI port 3.
CSI2_HS_RCOMP_OVR_ENABLE: CSI2_HS_RCOMP_OVR_ENABLE: If set, then the
0b CSI_HS_RCOMP_OVRD field is used as the RCOMP value during the update cycle for CSI
9 port 2. If clear, then the output of the RCOMP calibration engine (stored in
RW CSI_RCOMP_CALIBRATION_VALUE field of IUNIT_RCOMP_STATUS register) is used as
the RCOMP value during the update cycle for CSI port 2.
CSI1_HS_RCOMP_OVR_ENABLE: CSI1_HS_RCOMP_OVR_ENABLE: If set, then the
0b CSI_HS_RCOMP_OVRD field is used as the RCOMP value during the update cycle for CSI
8 port 1. If clear, then the output of the RCOMP calibration engine (stored in
RW CSI_RCOMP_CALIBRATION_VALUE field of IUNIT_RCOMP_STATUS register) is used as
the RCOMP value during the update cycle for CSI port 1.

0h CSI_HS_RCOMP_OVR_CODE: CSI_HS_RCOMP_OVR_CODE: Software defined value

7:1 to use as the RCOMP value for CSI[1-3] ports if the CSI[1-3]_HS_RCOMP_OVR_ENABLE
RW fields are set.

1b CSI_HS_RCOMP_ENABLE: CSI_HS_RCOMP_ENABLE: Enable CSI HS RCOMP. (Note:

0 This bit does not affect the initial RCOMP at the de-assertion of reset which is controlled
RW by the fuse FB_disable_initial_RCOMP.)

15.7.33 iunit_IUNIT_STATUS_type (IUNIT_STATUS)—Offset F8h

IUNIT Status Register

Access Method
Type: PCI Configuration Register
IUNIT_STATUS: [B:0, D:3, F:0] + F8h
(Size: 32 bits)

Default: 0000EB01h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 0 0 0 0 0 0 0 1
ISP_BUSY
ISCLK

CZCLK
RSVD_31_18

RSVD_7_7

RSVD_3_3
TCGSM

LCGSM

Bit Default &

Description
Range Access

0h
31:18 RSVD_31_18: Reserved
RO
07h
17:13 ISCLK: Reflects the value of cck_isp_isclk_ratio_zcznfwh input pin.
RO
0Bh
12:8 CZCLK: Reflects the value of cck_xxx_czclk_ratio_zcznfwh input pin.
RO

Intel® Atom™ Processor E3800 Product Family

Datasheet 907
 MIPI-Camera Serial Interface (CSI) & ISP

Bit Default &

Description
Range Access

0b
7 RSVD_7_7: Reserved
RO
TCGSM: ISP trunk clock gating state machine. 0h = RUN_TRUNK_CLK; 1h =
0h STOP_TRUNK_CLK; 2h = WAIT_FOR_RESUME; 3h = START_TRUNK_CLK; 4h =
6:4 WAIT_FOR_LOCAL_CLK_TO_START. The reset value will be RUN_TRUNK_CLK. If the
RO FB_override_initial_clock_gating fuse is not set, then shortly after reset, the value of
this register will automatically change to STOP_TRUNK_CLK.

0b
3 RSVD_3_3: Reserved
RO

LCGSM: ISP local clock gating state machine. 0h = RUN_LOCAL_CLK; 1h =

0h WAIT_FOR_FIFO_EMPTY; 2h = STOP_LOCAL_CLK. The reset value will be
2:1
RO RUN_LOCAL_CLK. If the FB_override_initial_clock_gating fuse is not set, then shortly
after reset, the value of this register will automatically change to STOP_LOCAL_CLK.
1b
0 ISP_BUSY: ISP_BUSY: 1 = ISP is busy; 0 = ISP is idle.
RO

15.7.34 iunit_IUNIT_CONTROL_type (IUNIT_CONTROL)—Offset FCh

IUNIT Control Register

Access Method
Type: PCI Configuration Register
(Size: 32 bits) IUNIT_CONTROL: [B:0, D:3, F:0] + FCh

Default: 00000103h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1
DISABLE_ISM_IDLE_FREEZE

ISPCLK_GATING_DISABLE
FUNCTION_DISABLE_MMIO

DDMA
FUNTION_DISABLE_CFG

DISABLE_OCP_PHASE_ORDERING

THERM_MASK

MID

RCOMPCLK_GATING_DISABLE

SRSE
RSVD_29_29

PERF_MASK

RSVD_23_22

ICACHE_CMD_WEIGHT

IBEWC
IBERC

Bit Default &

Description
Range Access

FUNTION_DISABLE_CFG: FUNCTION_DISABLE_CFG: When set, the IUNIT stops

0b accepting any new Configuration cycle requests on the IOSF Primary bus including any
31
RW new configuration cycle requests to clear this bit. Both legacy and MSI interrupts are
disabled as well.
0b FUNCTION_DISABLE_MMIO: FUNCTION_DISABLE_MMIO: When set, the IUNIT stops
30
RW accepting any new MMIO access requests on the IOSF Primary bus.

0b
29 RSVD_29_29: Reserved
RW

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908 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

Bit Default &

Description
Range Access

PERF_MASK: PERF_MASK: This field determines the amount of performance throttling

0h applied to ispclk. The value of this field determines how many beat periods of ispclk are
28:24 killed, where a beat period is defined as 16 ispclk cycles. A 16 cycle period was chosen
RW to make the throttling independent of the actual clock ratio between ispclk and coreclk.
Note that clock gating should be enabled when thermal throttling is enabled.

0h
23:22 RSVD_23_22: Reserved
RW

DISABLE_ISM_IDLE_FREEZE: DISABLE_ISM_IDLE_FREEZE: When IUNIT receive a

0h RESET_WARN message from PUNIT, it will freeze the IOSF primary Idle State Machine
21 (among other things), before sending an OK_TO_RESET message to PUNIT. If the
RW DISABLE_ISM_IDLE_FREEZE bit is set, IUNIT will not freeze the ISM in the IDLE state as
part of this reset sequence.
DISABLE_OCP_PHASE_ORDERING: DISABLE_OCP_PHASE_ORDERING: By default,
0h IUNIT will follow the OCP phase ordering protocol and wait until a write command is
20 accepted before accepting the write data corresponding to that command. If the
RW DISABLE_OCP_PHASE_ORDERING bit is set, the IUNIT wrapper will accept the write
data independent of the write command.
ICACHE_CMD_WEIGHT: ICACHE_CMD_WEIGHT: 0b = Requests from the OCP master
0h port sending Icache miss traffic will win arbitration over requests from the OCP master
19
RW port that sends pixel data traffic. 1b = Requests from the two OCP master interfaces will
be accepted in a round robin fashion.
THERM_MASK: THERM_MASK: This field determines the amount of thermal throttling
applied to ispclk. The value of this field determines how many beat periods of ispclk are
0h killed, where a beat period is defined as 16 ispclk cycles. A 16 cycle period was chosen
18:16 to make the throttling independent of the actual clock ratio between ispclk and coreclk.
RW 000 = No throttling; 001 = 12.5% throttling; 010 = 25% throttling; 011 = 37.5%
throttling; 100 = 50% throttling; 101 = 62.5% throttling; 110 = 75% throttling; 111 =
87.5% throttling;

01h MID: MIN_IDLE_DELAY: Minimum wait time after the rising edge of idle, before the
15:8 clock gating state machine will start the sequence to gate ispclk. Range is 0 to 130 usec.
RW Unit is 0.512 usec. Reset value of 8'h1 indicates MID = 0.512 usec.

0b RCOMPCLK_GATING_DISABLE: 1 = Disable clock gating for rcompclk. 0 = Enable

7 clock gating for rcompclk. Note: All clock gating is disabled by hardware while reset is
RW asserted, regardless of the state of this field.

ISPCLK_GATING_DISABLE: ISPCLK_GATING_DISABLE: 11 = Disable local clock

00b gating and trunk clock gating for ispclk.; 10 = Enable local clock gating for ispclk, but
6:5 disable trunk clock gating.; 01 = Reserved; 00 = Enable local clock gating and trunk
RW clock gating for ispclk. Note: All clock gating is disabled by hardware while reset is
asserted, regardless of the state of this field.

0b DDMA: 1 = Disable DMA. Stop sending any requests on the IB PFI port. 0 = Enable
4
RW DMA. IB PFI port operates normally.

SRSE: SOFT_RESET_SEQUENCE_ENABLE: If SRSE=2b00: When an

IUNIT_RESET_WARN message is received from PUNIT, IUNIT will a) stop accepting
requests on the IOSF primary interface, b) stop accepting new requests from the OCP
master interface, c) wait until read data from all earlier read requests received from the
OCP master interface have been returned by SSA, d) wait until SSA reads data for all
earlier PFI write requests, and e) wait for all DPHY lanes to enter stop state (LP11), and
then f) send an IUNIT_OK_TO_RESET posted message to PUNIT. If SRSE=2b01: When
0h an IUNIT_RESET_WARN message is received from PUNIT, IUNIT will a) stop accepting
3:2 requests on the IOSF primary interface, b) stop accepting new requests from the OCP
RW master interface, c) wait until read data from all earlier read requests received from the
OCP master interface have been returned by SSA, d) wait until SSA reads data for all
earlier PFI write requests, and then e) send an IUNIT_OK_TO_RESET posted message to
PUNIT. If SRSE=2b10: When an IUNIT_RESET_WARN message is received from PUNIT,
IUNIT will wait for all DPHY lanes to enter stop state (LP11), and then send an
IUNIT_OK_TO_RESET posted message to PUNIT. If SRSE=2b11: When an
IUNIT_RESET_WARN message is received from PUNIT, IUNIT will immediately send an
IUINT_OK_TO_RESET posted message to PUNIT.

Intel® Atom™ Processor E3800 Product Family

Datasheet 909
 MIPI-Camera Serial Interface (CSI) & ISP

Bit Default &

Description
Range Access

1b IBEWC: IB_ENABLE_WRITE_COMBINING: When set, enables the combining of adjacent

1 32-byte write requests to the same cache line. When cleared, each 32-byte write
RW request is sent as a separate request on the IB interface.

1b IBERC: IB_ENABLE_READ_COMBINING: When set, enables the combining of adjacent

0 32-byte read requests to the same cache line. When cleared, each 32-byte read request
RW is sent as a separate request on the IB interface.

Intel® Atom™ Processor E3800 Product Family

910 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

15.8 Image Signal Processor Memory Mapped IO Registers

Table 167. Summary of Image Signal Processor Memory Mapped I/O Registers—
ISPMMADR
Offset Size Register ID—Description Default Value

“reg_gpd_gp_reg_reg_gp_sdram_wakeup_type
0h 4 00000000h
(gpd_gp_reg_reg_gp_sdram_wakeup)—Offset 0h” on page 951
“reg_gpd_gp_reg_reg_gp_idle_type (gpd_gp_reg_reg_gp_idle)—Offset
4h 4 00000000h
4h” on page 952
“reg_gpd_gp_reg_reg_gp_irq_req0_type
8h 4 00000000h
(gpd_gp_reg_reg_gp_irq_req0)—Offset 8h” on page 953

“reg_gpd_gp_reg_reg_gp_irq_req1_type
Ch 4 00000000h
(gpd_gp_reg_reg_gp_irq_req1)—Offset Ch” on page 953
“reg_gpd_gp_reg_reg_gp_sp_stream_stat_type
10h 4 00022022h
(gpd_gp_reg_reg_gp_sp_stream_stat)—Offset 10h” on page 954
“reg_gpd_gp_reg_reg_gp_sp_stream_stat_b_type
14h 4 00000000h
(gpd_gp_reg_reg_gp_sp_stream_stat_b)—Offset 14h” on page 956

“reg_gpd_gp_reg_reg_gp_isp_stream_stat_type
18h 4 02200000h
(gpd_gp_reg_reg_gp_isp_stream_stat)—Offset 18h” on page 958
“reg_gpd_gp_reg_reg_gp_mod_stream_stat_type
1Ch 4 AA88A222h
(gpd_gp_reg_reg_gp_mod_stream_stat)—Offset 1Ch” on page 960
“reg_gpd_gp_reg_reg_gp_sp_stream_stat_irq_cond_type
20h 4 (gpd_gp_reg_reg_gp_sp_stream_stat_irq_cond)—Offset 20h” on 00000000h
page 962
“reg_gpd_gp_reg_reg_gp_sp_stream_stat_b_irq_cond_type
24h 4 (gpd_gp_reg_reg_gp_sp_stream_stat_b_irq_cond)—Offset 24h” on 00000000h
page 963
“reg_gpd_gp_reg_reg_gp_isp_stream_stat_irq_cond_type
28h 4 (gpd_gp_reg_reg_gp_isp_stream_stat_irq_cond)—Offset 28h” on 00000000h
page 964
“reg_gpd_gp_reg_reg_gp_mod_stream_stat_irq_cond_type
2Ch 4 (gpd_gp_reg_reg_gp_mod_stream_stat_irq_cond)—Offset 2Ch” on 00000000h
page 964
“reg_gpd_gp_reg_reg_gp_sp_stream_stat_irq_enable_type
30h 4 (gpd_gp_reg_reg_gp_sp_stream_stat_irq_enable)—Offset 30h” on 00000000h
page 965
“reg_gpd_gp_reg_reg_gp_sp_stream_stat_b_irq_enable_type
34h 4 (gpd_gp_reg_reg_gp_sp_stream_stat_b_irq_enable)—Offset 34h” on 00000000h
page 966
“reg_gpd_gp_reg_reg_gp_isp_stream_stat_irq_enable_type
38h 4 (gpd_gp_reg_reg_gp_isp_stream_stat_irq_enable)—Offset 38h” on 00000000h
page 966
“reg_gpd_gp_reg_reg_gp_mod_stream_stat_irq_enable_type
3Ch 4 (gpd_gp_reg_reg_gp_mod_stream_stat_irq_enable)—Offset 3Ch” on 00000000h
page 967
“reg_gpd_gp_reg_reg_gp_switch_if_type
40h 4 00000000h
(gpd_gp_reg_reg_gp_switch_if)—Offset 40h” on page 968
“reg_gpd_gp_reg_reg_gp_switch_gdc1_type
44h 4 00000000h
(gpd_gp_reg_reg_gp_switch_gdc1)—Offset 44h” on page 969

“reg_gpd_gp_reg_reg_gp_switch_gdc2_type
48h 4 00000000h
(gpd_gp_reg_reg_gp_switch_gdc2)—Offset 48h” on page 969
“reg_gpd_gp_reg_reg_gp_srst_type (gpd_gp_reg_reg_gp_srst)—Offset
4Ch 4 00000000h
4Ch” on page 970

Intel® Atom™ Processor E3800 Product Family

Datasheet 911
 MIPI-Camera Serial Interface (CSI) & ISP

Table 167. Summary of Image Signal Processor Memory Mapped I/O Registers—
ISPMMADR (Continued)
Offset Size Register ID—Description Default Value

“reg_gpd_gp_reg_reg_gp_slv_reg_srst_type
50h 4 00000000h
(gpd_gp_reg_reg_gp_slv_reg_srst)—Offset 50h” on page 972

“reg_gpd_tc_FifoWriteCmd_type (gpd_tc_FifoWriteCmd)—Offset 100h” on

100h 4 00000000h
page 973
“reg_gpd_c_gpio_reg_gpio_doe_type (gpd_c_gpio_reg_gpio_doe)—Offset
400h 4 00000000h
400h” on page 973
“reg_gpd_c_gpio_reg_gpio_do_select_type
404h 4 00000000h
(gpd_c_gpio_reg_gpio_do_select)—Offset 404h” on page 974

“reg_gpd_c_gpio_reg_gpio_do_0_type (gpd_c_gpio_reg_gpio_do_0)—
408h 4 00000000h
Offset 408h” on page 974
“reg_gpd_c_gpio_reg_gpio_do_1_type (gpd_c_gpio_reg_gpio_do_1)—
40Ch 4 00000000h
Offset 40Ch” on page 975
“reg_gpd_c_gpio_reg_gpio_do_pwm_cnt_0_type
410h 4 00000000h
(gpd_c_gpio_reg_gpio_do_pwm_cnt_0)—Offset 410h” on page 975

“reg_gpd_c_gpio_reg_gpio_do_pwm_cnt_1_type
414h 4 00000000h
(gpd_c_gpio_reg_gpio_do_pwm_cnt_1)—Offset 414h” on page 976
“reg_gpd_c_gpio_reg_gpio_do_pwm_cnt_2_type
418h 4 00000000h
(gpd_c_gpio_reg_gpio_do_pwm_cnt_2)—Offset 418h” on page 977
“reg_gpd_c_gpio_reg_gpio_do_pwm_cnt_3_type
41Ch 4 00000000h
(gpd_c_gpio_reg_gpio_do_pwm_cnt_3)—Offset 41Ch” on page 977

“reg_gpd_c_gpio_reg_gpio_do_pwm_main_cnt_type
420h 4 00000000h
(gpd_c_gpio_reg_gpio_do_pwm_main_cnt)—Offset 420h” on page 978
“reg_gpd_c_gpio_reg_gpio_do_pwm_enable_type
424h 4 00000000h
(gpd_c_gpio_reg_gpio_do_pwm_enable)—Offset 424h” on page 979
“reg_gpd_c_gpio_reg_gpio_di_debouncemethod_type
428h 4 00000000h
(gpd_c_gpio_reg_gpio_di_debouncemethod)—Offset 428h” on page 979

“reg_gpd_c_gpio_reg_gpio_di_debounce_cnt0_type
42Ch 4 00000000h
(gpd_c_gpio_reg_gpio_di_debounce_cnt0)—Offset 42Ch” on page 980
“reg_gpd_c_gpio_reg_gpio_di_debounce_cnt1_type
430h 4 00000000h
(gpd_c_gpio_reg_gpio_di_debounce_cnt1)—Offset 430h” on page 981
“reg_gpd_c_gpio_reg_gpio_di_debounce_cnt2_type
434h 4 00000000h
(gpd_c_gpio_reg_gpio_di_debounce_cnt2)—Offset 434h” on page 981
“reg_gpd_c_gpio_reg_gpio_di_debounce_cnt3_type
438h 4 00000000h
(gpd_c_gpio_reg_gpio_di_debounce_cnt3)—Offset 438h” on page 982

“reg_gpd_c_gpio_reg_gpio_di_activelevel_type
43Ch 4 00000FFFh
(gpd_c_gpio_reg_gpio_di_activelevel)—Offset 43Ch” on page 982
“reg_gpd_c_gpio_reg_gpio_di_debouncemethod_type
440h 4 00000FFFh
(gpd_c_gpio_reg_gpio_di_debouncemethod)—Offset 428h” on page 979
“reg_gpd_irq_ctrl_reg_irq_edge_type (gpd_irq_ctrl_reg_irq_edge)—Offset
500h 4 00000000h
500h” on page 984

“reg_gpd_irq_ctrl_reg_irq_mask_type (gpd_irq_ctrl_reg_irq_mask)—
504h 4 00000000h
Offset 504h” on page 984
“reg_gpd_irq_ctrl_reg_irq_status_type (gpd_irq_ctrl_reg_irq_status)—
508h 4 00000000h
Offset 508h” on page 984
“reg_gpd_irq_ctrl_reg_irq_clear_type (gpd_irq_ctrl_reg_irq_clear)—Offset
50Ch 4 00000000h
50Ch” on page 986

“reg_gpd_irq_ctrl_reg_irq_enable_type (gpd_irq_ctrl_reg_irq_enable)—
510h 4 00000000h
Offset 510h” on page 986

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912 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

Table 167. Summary of Image Signal Processor Memory Mapped I/O Registers—
ISPMMADR (Continued)
Offset Size Register ID—Description Default Value

“reg_gpd_irq_ctrl_reg_irq_level_not_pulse_type
514h 4 00000000h
(gpd_irq_ctrl_reg_irq_level_not_pulse)—Offset 514h” on page 987

“reg_gpd_irq_ctrl_reg_irq_str_out_enable_type
518h 4 00000000h
(gpd_irq_ctrl_reg_irq_str_out_enable)—Offset 518h” on page 987
“reg_gpd_gptimer_reg_reset_type (gpd_gptimer_reg_reset)—Offset
600h 4 00000000h
600h” on page 988
“reg_gpd_gptimer_overall_enable_type (gpd_gptimer_overall_enable)—
604h 4 00000000h
Offset 604h” on page 988

“reg_gpd_gptimer_enable_timer_0_type
608h 4 00000000h
(gpd_gptimer_enable_timer_0)—Offset 608h” on page 989
“reg_gpd_gptimer_enable_timer_1_type
60Ch 4 00000000h
(gpd_gptimer_enable_timer_1)—Offset 60Ch” on page 989
“reg_gpd_gptimer_enable_timer_2_type
610h 4 00000000h
(gpd_gptimer_enable_timer_2)—Offset 610h” on page 990

“reg_gpd_gptimer_enable_timer_3_type
614h 4 00000000h
(gpd_gptimer_enable_timer_3)—Offset 614h” on page 991
“reg_gpd_gptimer_enable_timer_4_type
618h 4 00000000h
(gpd_gptimer_enable_timer_4)—Offset 618h” on page 991
“reg_gpd_gptimer_enable_timer_5_type
61Ch 4 00000000h
(gpd_gptimer_enable_timer_5)—Offset 61Ch” on page 992

“reg_gpd_gptimer_enable_timer_6_type
620h 4 00000000h
(gpd_gptimer_enable_timer_6)—Offset 620h” on page 992
“reg_gpd_gptimer_enable_timer_7_type
624h 4 00000000h
(gpd_gptimer_enable_timer_7)—Offset 624h” on page 993
“reg_gpd_gptimer_value_timer_0_type (gpd_gptimer_value_timer_0)—
628h 4 00000000h
Offset 628h” on page 993

“reg_gpd_gptimer_value_timer_1_type (gpd_gptimer_value_timer_1)—
62Ch 4 00000000h
Offset 62Ch” on page 994
“reg_gpd_gptimer_value_timer_2_type (gpd_gptimer_value_timer_2)—
630h 4 00000000h
Offset 630h” on page 994
“reg_gpd_gptimer_value_timer_3_type (gpd_gptimer_value_timer_3)—
634h 4 00000000h
Offset 634h” on page 995
“reg_gpd_gptimer_value_timer_4_type (gpd_gptimer_value_timer_4)—
638h 4 00000000h
Offset 638h” on page 995

“reg_gpd_gptimer_value_timer_5_type (gpd_gptimer_value_timer_5)—
63Ch 4 00000000h
Offset 63Ch” on page 996
“reg_gpd_gptimer_value_timer_6_type (gpd_gptimer_value_timer_6)—
640h 4 00000000h
Offset 640h” on page 996
“reg_gpd_gptimer_value_timer_7_type (gpd_gptimer_value_timer_7)—
644h 4 00000000h
Offset 644h” on page 997

“reg_gpd_gptimer_count_type_timer_0_type
648h 4 00000000h
(gpd_gptimer_count_type_timer_0)—Offset 648h” on page 997
“reg_gpd_gptimer_count_type_timer_1_type
64Ch 4 00000000h
(gpd_gptimer_count_type_timer_1)—Offset 64Ch” on page 998
“reg_gpd_gptimer_count_type_timer_2_type
650h 4 00000000h
(gpd_gptimer_count_type_timer_2)—Offset 650h” on page 999

“reg_gpd_gptimer_count_type_timer_3_type
654h 4 00000000h
(gpd_gptimer_count_type_timer_3)—Offset 654h” on page 999

Intel® Atom™ Processor E3800 Product Family

Datasheet 913
 MIPI-Camera Serial Interface (CSI) & ISP

Table 167. Summary of Image Signal Processor Memory Mapped I/O Registers—
ISPMMADR (Continued)
Offset Size Register ID—Description Default Value

“reg_gpd_gptimer_count_type_timer_4_type
658h 4 00000000h
(gpd_gptimer_count_type_timer_4)—Offset 658h” on page 1000

“reg_gpd_gptimer_count_type_timer_5_type
65Ch 4 00000000h
(gpd_gptimer_count_type_timer_5)—Offset 65Ch” on page 1000
“reg_gpd_gptimer_count_type_timer_6_type
660h 4 00000000h
(gpd_gptimer_count_type_timer_6)—Offset 660h” on page 1001
“reg_gpd_gptimer_count_type_timer_7_type
664h 4 00000000h
(gpd_gptimer_count_type_timer_7)—Offset 664h” on page 1002

“reg_gpd_gptimer_signal_select_timer_0_type
668h 4 00000000h
(gpd_gptimer_signal_select_timer_0)—Offset 668h” on page 1002
“reg_gpd_gptimer_signal_select_timer_1_type
66Ch 4 00000000h
(gpd_gptimer_signal_select_timer_1)—Offset 66Ch” on page 1003
“reg_gpd_gptimer_signal_select_timer_2_type
670h 4 00000000h
(gpd_gptimer_signal_select_timer_2)—Offset 670h” on page 1004

“reg_gpd_gptimer_signal_select_timer_3_type
674h 4 00000000h
(gpd_gptimer_signal_select_timer_3)—Offset 674h” on page 1004
“reg_gpd_gptimer_signal_select_timer_4_type
678h 4 00000000h
(gpd_gptimer_signal_select_timer_4)—Offset 678h” on page 1005
“reg_gpd_gptimer_signal_select_timer_5_type
67Ch 4 00000000h
(gpd_gptimer_signal_select_timer_5)—Offset 67Ch” on page 1006

“reg_gpd_gptimer_signal_select_timer_6_type
680h 4 00000000h
(gpd_gptimer_signal_select_timer_6)—Offset 680h” on page 1006
“reg_gpd_gptimer_signal_select_timer_7_type
684h 4 00000000h
(gpd_gptimer_signal_select_timer_7)—Offset 684h” on page 1007
“reg_gpd_gptimer_irq_trigger_value_0_type
688h 4 00000000h
(gpd_gptimer_irq_trigger_value_0)—Offset 688h” on page 1008

“reg_gpd_gptimer_irq_trigger_value_1_type
68Ch 4 00000000h
(gpd_gptimer_irq_trigger_value_1)—Offset 68Ch” on page 1008
“reg_gpd_gptimer_irq_timer_select_0_type
690h 4 00000000h
(gpd_gptimer_irq_timer_select_0)—Offset 690h” on page 1009
“reg_gpd_gptimer_irq_timer_select_1_type
694h 4 00000000h
(gpd_gptimer_irq_timer_select_1)—Offset 694h” on page 1009
“reg_gpd_gptimer_irq_enable_0_type (gpd_gptimer_irq_enable_0)—
698h 4 00000000h
Offset 698h” on page 1010

“reg_gpd_gptimer_irq_enable_1_type (gpd_gptimer_irq_enable_1)—
69Ch 4 00000000h
Offset 69Ch” on page 1010
“reg_scp_stat_and_ctrl_type (scp_stat_and_ctrl)—Offset 10000h” on
10000h 4 000000A0h
page 1011
“reg_scp_base_address_type (scp_base_address)—Offset 10004h” on
10004h 4 00000000h
page 1012

10008h 4 “reg_scp_unused_2_type (scp_unused_2)—Offset 10008h” on page 1013 00000000h

“reg_scp_base_addr_seg_0_MI_xmem_master_int_type
10010h 4 (scp_base_addr_seg_0_MI_xmem_master_int)—Offset 10010h” on 00000000h
page 1013
“reg_scp_base_addr_seg_0_MI_config_ilm_conf_ilm_master_type
10014h 4 (scp_base_addr_seg_0_MI_config_ilm_conf_ilm_master)—Offset 10014h” 00000000h
on page 1014
10018h 4 “reg_scp_unused_6_type (scp_unused_6)—Offset 10018h” on page 1015 00000000h
1001Ch 4 “reg_scp_unused_7_type (scp_unused_7)—Offset 1001Ch” on page 1015 00000000h

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914 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

Table 167. Summary of Image Signal Processor Memory Mapped I/O Registers—
ISPMMADR (Continued)
Offset Size Register ID—Description Default Value

10024h 4 “reg_scp_debug_pc_type (scp_debug_pc)—Offset 10024h” on page 1015 00000000h

“reg_scp_stall_stat_fifo_loc_mt_am_inst_0_op0_type
10028h 4 (scp_stall_stat_fifo_loc_mt_am_inst_0_op0)—Offset 10028h” on 00000000h
page 1016
“reg_scp_unused_11_type (scp_unused_11)—Offset 1002Ch” on
1002Ch 4 00000000h
page 1017
“reg_scp_pmem_slave_access_type (scp_pmem_slave_access)—Offset
10030h 4 00000000h
10030h” on page 1018

“reg_isp_stat_and_ctrl_type (isp_stat_and_ctrl)—Offset 20000h” on

20000h 4 000000A0h
page 1018
“reg_isp_base_address_type (isp_base_address)—Offset 20004h” on
20004h 4 00000000h
page 1020
20008h 4 “reg_isp_unused_2_type (isp_unused_2)—Offset 20008h” on page 1020 00000000h
“reg_isp_base_addr_seg_0_MI_base_config_mem_master_type
20010h 4 (isp_base_addr_seg_0_MI_base_config_mem_master)—Offset 20010h” 00000000h
on page 1021
20014h 4 “reg_isp_unused_5_type (isp_unused_5)—Offset 20014h” on page 1021 00000000h

2001Ch 4 “reg_isp_debug_pc_type (isp_debug_pc)—Offset 2001Ch” on page 1022 00000000h

“reg_isp_stall_stat_base_config_mem_iam_op0_type
20020h 4 (isp_stall_stat_base_config_mem_iam_op0)—Offset 20020h” on 00000000h
page 1022
20024h 4 “reg_isp_unused_9_type (isp_unused_9)—Offset 20024h” on page 1024 00000000h
“reg_isp_pmem_slave_access_type (isp_pmem_slave_access)—Offset
20028h 4 00000000h
20028h” on page 1024
“reg_ifmt_ift_prim_IF_sw_rst_type (ifmt_ift_prim_IF_sw_rst)—Offset
30000h 4 00000000h
30000h” on page 1025

“reg_ifmt_ift_prim_IF_start_line_type (ifmt_ift_prim_IF_start_line)—
30004h 4 00000000h
Offset 30004h” on page 1025
“reg_ifmt_ift_prim_IF_start_column_type
30008h 4 00000000h
(ifmt_ift_prim_IF_start_column)—Offset 30008h” on page 1026
“reg_ifmt_ift_prim_IF_Cropped_height_type
3000Ch 4 00000000h
(ifmt_ift_prim_IF_Cropped_height)—Offset 3000Ch” on page 1026
“reg_ifmt_ift_prim_IF_Cropped_width_type
30010h 4 00000000h
(ifmt_ift_prim_IF_Cropped_width)—Offset 30010h” on page 1027

“reg_ifmt_ift_prim_IF_Vert_Decim_type (ifmt_ift_prim_IF_Vert_Decim)—
30014h 4 00000000h
Offset 30014h” on page 1028
“reg_ifmt_ift_prim_IF_Horiz_Decim_type
30018h 4 00000000h
(ifmt_ift_prim_IF_Horiz_Decim)—Offset 30018h” on page 1028
“reg_ifmt_ift_prim_IF_Horiz_Deinter_type
3001Ch 4 00000000h
(ifmt_ift_prim_IF_Horiz_Deinter)—Offset 3001Ch” on page 1029

“reg_ifmt_ift_prim_IF_Left_Pad_type (ifmt_ift_prim_IF_Left_Pad)—Offset
30020h 4 00000000h
30020h” on page 1029
“reg_ifmt_ift_prim_IF_EOF_Offset_type (ifmt_ift_prim_IF_EOF_Offset)—
30024h 4 00000000h
Offset 30024h” on page 1030
“reg_ifmt_ift_prim_IF_Start_addr_type (ifmt_ift_prim_IF_Start_addr)—
30028h 4 00000000h
Offset 30028h” on page 1030

“reg_ifmt_ift_prim_IF_End_addr_type (ifmt_ift_prim_IF_End_addr)—
3002Ch 4 00000000h
Offset 3002Ch” on page 1031

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Datasheet 915
 MIPI-Camera Serial Interface (CSI) & ISP

Table 167. Summary of Image Signal Processor Memory Mapped I/O Registers—
ISPMMADR (Continued)
Offset Size Register ID—Description Default Value

“reg_ifmt_ift_prim_IF_incr_type (ifmt_ift_prim_IF_incr)—Offset 30030h”

30030h 4 00000000h
on page 1032

“reg_ifmt_ift_prim_IF_YUV_420_format_type
30034h 4 00000000h
(ifmt_ift_prim_IF_YUV_420_format)—Offset 30034h” on page 1032
“reg_ifmt_ift_prim_IF_Vsynch_active_low_type
30038h 4 00000000h
(ifmt_ift_prim_IF_Vsynch_active_low)—Offset 30038h” on page 1033
“reg_ifmt_ift_prim_IF_Hsynch_active_low_type
3003Ch 4 00000000h
(ifmt_ift_prim_IF_Hsynch_active_low)—Offset 3003Ch” on page 1033

“reg_ifmt_ift_prim_IF_ReEnable_type (ifmt_ift_prim_IF_ReEnable)—
30040h 4 00000000h
Offset 30040h” on page 1034
“reg_ifmt_ift_prim_IF_block_input_type (ifmt_ift_prim_IF_block_input)—
30044h 4 00000000h
Offset 30044h” on page 1034
“reg_ifmt_ift_prim_IF_Vert_Deinter_type
30048h 4 00000000h
(ifmt_ift_prim_IF_Vert_Deinter)—Offset 30048h” on page 1035

“reg_ifmt_ift_prim_IF_FSM_Sync_status_type
30100h 4 00000000h
(ifmt_ift_prim_IF_FSM_Sync_status)—Offset 30100h” on page 1036
“reg_ifmt_ift_prim_FSM_Sync_counter_type
30104h 4 00000000h
(ifmt_ift_prim_FSM_Sync_counter)—Offset 30104h” on page 1036
“reg_ifmt_ift_prim_FSM_Crop_status_type
30108h 4 00000000h
(ifmt_ift_prim_FSM_Crop_status)—Offset 30108h” on page 1037

“reg_ifmt_ift_prim_FSM_Crop_line_counter_type
3010Ch 4 00000000h
(ifmt_ift_prim_FSM_Crop_line_counter)—Offset 3010Ch” on page 1038
“reg_ifmt_ift_prim_FSM_Crop_pixel_counter_type
30110h 4 00000000h
(ifmt_ift_prim_FSM_Crop_pixel_counter)—Offset 30110h” on page 1038
“reg_ifmt_ift_prim_FSM_Deinterl_idx_buffer_type
30114h 4 00000000h
(ifmt_ift_prim_FSM_Deinterl_idx_buffer)—Offset 30114h” on page 1039

“reg_ifmt_ift_prim_FSM_Horiz_Decim_cnt_type
30118h 4 00000000h
(ifmt_ift_prim_FSM_Horiz_Decim_cnt)—Offset 30118h” on page 1040
“reg_ifmt_ift_prim_FSM_Vertic_Decim_cnt_type
3011Ch 4 00000000h
(ifmt_ift_prim_FSM_Vertic_Decim_cnt)—Offset 3011Ch” on page 1040
“reg_ifmt_ift_prim_FSM_Vertic_Block_Decim_cnt_type
30120h 4 (ifmt_ift_prim_FSM_Vertic_Block_Decim_cnt)—Offset 30120h” on 00000000h
page 1041
“reg_ifmt_ift_prim_IF_FSM_Padding_status_type
30124h 4 00000000h
(ifmt_ift_prim_IF_FSM_Padding_status)—Offset 30124h” on page 1042
“reg_ifmt_ift_prim_IF_FSM_Padding_elem_idx_type
30128h 4 00000000h
(ifmt_ift_prim_IF_FSM_Padding_elem_idx)—Offset 30128h” on page 1042

“reg_ifmt_ift_prim_IF_FSM_Vec_Sup_type
3012Ch 4 00000000h
(ifmt_ift_prim_IF_FSM_Vec_Sup)—Offset 3012Ch” on page 1043
“reg_ifmt_ift_prim_IF_FSM_Vec_Sup_Buf_full_type
30130h 4 00000000h
(ifmt_ift_prim_IF_FSM_Vec_Sup_Buf_full)—Offset 30130h” on page 1044
“reg_ifmt_ift_prim_IF_FSM_Vec_Sup_rd_accept_type
30134h 4 (ifmt_ift_prim_IF_FSM_Vec_Sup_rd_accept)—Offset 30134h” on 00000001h
page 1044
“reg_ifmt_ift_prim_IF_Pixel_Fifo_status_type
30138h 4 00000001h
(ifmt_ift_prim_IF_Pixel_Fifo_status)—Offset 30138h” on page 1045

“reg_ifmt_ift_prim_b_IF_sw_rst_type (ifmt_ift_prim_b_IF_sw_rst)—
30200h 4 00000000h
Offset 30200h” on page 1046
“reg_ifmt_ift_prim_b_IF_start_line_type (ifmt_ift_prim_b_IF_start_line)—
30204h 4 00000000h
Offset 30204h” on page 1046

Intel® Atom™ Processor E3800 Product Family

916 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

Table 167. Summary of Image Signal Processor Memory Mapped I/O Registers—
ISPMMADR (Continued)
Offset Size Register ID—Description Default Value

“reg_ifmt_ift_prim_b_IF_start_column_type
30208h 4 00000000h
(ifmt_ift_prim_b_IF_start_column)—Offset 30208h” on page 1047

“reg_ifmt_ift_prim_b_IF_Cropped_height_type
3020Ch 4 00000000h
(ifmt_ift_prim_b_IF_Cropped_height)—Offset 3020Ch” on page 1047
“reg_ifmt_ift_prim_b_IF_Cropped_width_type
30210h 4 00000000h
(ifmt_ift_prim_b_IF_Cropped_width)—Offset 30210h” on page 1048
“reg_ifmt_ift_prim_b_IF_Vert_Decim_type
30214h 4 00000000h
(ifmt_ift_prim_b_IF_Vert_Decim)—Offset 30214h” on page 1049

“reg_ifmt_ift_prim_b_IF_Horiz_Decim_type
30218h 4 00000000h
(ifmt_ift_prim_b_IF_Horiz_Decim)—Offset 30218h” on page 1049
“reg_ifmt_ift_prim_b_IF_Horiz_Deinter_type
3021Ch 4 00000000h
(ifmt_ift_prim_b_IF_Horiz_Deinter)—Offset 3021Ch” on page 1050
“reg_ifmt_ift_prim_b_IF_Left_Pad_type (ifmt_ift_prim_b_IF_Left_Pad)—
30220h 4 00000000h
Offset 30220h” on page 1050

“reg_ifmt_ift_prim_b_IF_EOF_Offset_type
30224h 4 00000000h
(ifmt_ift_prim_b_IF_EOF_Offset)—Offset 30224h” on page 1051
“reg_ifmt_ift_prim_b_IF_Start_addr_type
30228h 4 00000000h
(ifmt_ift_prim_b_IF_Start_addr)—Offset 30228h” on page 1052
“reg_ifmt_ift_prim_b_IF_End_addr_type
3022Ch 4 00000000h
(ifmt_ift_prim_b_IF_End_addr)—Offset 3022Ch” on page 1052

“reg_ifmt_ift_prim_b_IF_incr_type (ifmt_ift_prim_b_IF_incr)—Offset
30230h 4 00000000h
30230h” on page 1053
“reg_ifmt_ift_prim_b_IF_YUV_420_format_type
30234h 4 00000000h
(ifmt_ift_prim_b_IF_YUV_420_format)—Offset 30234h” on page 1053
“reg_ifmt_ift_prim_b_IF_Vsynch_active_low_type
30238h 4 00000000h
(ifmt_ift_prim_b_IF_Vsynch_active_low)—Offset 30238h” on page 1054

“reg_ifmt_ift_prim_b_IF_Hsynch_active_low_type
3023Ch 4 00000000h
(ifmt_ift_prim_b_IF_Hsynch_active_low)—Offset 3023Ch” on page 1055
“reg_ifmt_ift_prim_b_IF_ReEnable_type (ifmt_ift_prim_b_IF_ReEnable)—
30240h 4 00000000h
Offset 30240h” on page 1055
“reg_ifmt_ift_prim_b_IF_block_input_type
30244h 4 00000000h
(ifmt_ift_prim_b_IF_block_input)—Offset 30244h” on page 1056
“reg_ifmt_ift_prim_b_IF_Vert_Deinter_type
30248h 4 00000000h
(ifmt_ift_prim_b_IF_Vert_Deinter)—Offset 30248h” on page 1056

“reg_ifmt_ift_prim_b_IF_FSM_Sync_status_type
30300h 4 00000000h
(ifmt_ift_prim_b_IF_FSM_Sync_status)—Offset 30300h” on page 1057
“reg_ifmt_ift_prim_b_FSM_Sync_counter_type
30304h 4 00000000h
(ifmt_ift_prim_b_FSM_Sync_counter)—Offset 30304h” on page 1058
“reg_ifmt_ift_prim_b_FSM_Crop_status_type
30308h 4 00000000h
(ifmt_ift_prim_b_FSM_Crop_status)—Offset 30308h” on page 1058

“reg_ifmt_ift_prim_b_FSM_Crop_line_counter_type
3030Ch 4 00000000h
(ifmt_ift_prim_b_FSM_Crop_line_counter)—Offset 3030Ch” on page 1059
“reg_ifmt_ift_prim_b_FSM_Crop_pixel_counter_type
30310h 4 (ifmt_ift_prim_b_FSM_Crop_pixel_counter)—Offset 30310h” on 00000000h
page 1060
“reg_ifmt_ift_prim_b_FSM_Deinterl_idx_buffer_type
30314h 4 (ifmt_ift_prim_b_FSM_Deinterl_idx_buffer)—Offset 30314h” on 00000000h
page 1060
“reg_ifmt_ift_prim_b_FSM_Horiz_Decim_cnt_type
30318h 4 00000000h
(ifmt_ift_prim_b_FSM_Horiz_Decim_cnt)—Offset 30318h” on page 1061

Intel® Atom™ Processor E3800 Product Family

Datasheet 917
 MIPI-Camera Serial Interface (CSI) & ISP

Table 167. Summary of Image Signal Processor Memory Mapped I/O Registers—
ISPMMADR (Continued)
Offset Size Register ID—Description Default Value

“reg_ifmt_ift_prim_b_FSM_Vertic_Decim_cnt_type
3031Ch 4 00000000h
(ifmt_ift_prim_b_FSM_Vertic_Decim_cnt)—Offset 3031Ch” on page 1062

“reg_ifmt_ift_prim_b_FSM_Vertic_Block_Decim_cnt_type
30320h 4 (ifmt_ift_prim_b_FSM_Vertic_Block_Decim_cnt)—Offset 30320h” on 00000000h
page 1062

“reg_ifmt_ift_prim_b_IF_FSM_Padding_status_type
30324h 4 00000000h
(ifmt_ift_prim_b_IF_FSM_Padding_status)—Offset 30324h” on page 1063
“reg_ifmt_ift_prim_b_IF_FSM_Padding_elem_idx_type
30328h 4 (ifmt_ift_prim_b_IF_FSM_Padding_elem_idx)—Offset 30328h” on 00000000h
page 1064
“reg_ifmt_ift_prim_b_IF_FSM_Vec_Sup_type
3032Ch 4 00000000h
(ifmt_ift_prim_b_IF_FSM_Vec_Sup)—Offset 3032Ch” on page 1064
“reg_ifmt_ift_prim_b_IF_FSM_Vec_Sup_Buf_full_type
30330h 4 (ifmt_ift_prim_b_IF_FSM_Vec_Sup_Buf_full)—Offset 30330h” on 00000000h
page 1065
“reg_ifmt_ift_prim_b_IF_FSM_Vec_Sup_rd_accept_type
30334h 4 (ifmt_ift_prim_b_IF_FSM_Vec_Sup_rd_accept)—Offset 30334h” on 00000001h
page 1066
“reg_ifmt_ift_prim_b_IF_Pixel_Fifo_status_type
30338h 4 00000001h
(ifmt_ift_prim_b_IF_Pixel_Fifo_status)—Offset 30338h” on page 1066

“reg_ifmt_ift_sec_IF_sw_rst_type (ifmt_ift_sec_IF_sw_rst)—Offset
30400h 4 00000000h
30400h” on page 1067
“reg_ifmt_ift_sec_IF_start_line_type (ifmt_ift_sec_IF_start_line)—Offset
30404h 4 00000000h
30404h” on page 1068
“reg_ifmt_ift_sec_IF_start_column_type (ifmt_ift_sec_IF_start_column)—
30408h 4 00000000h
Offset 30408h” on page 1068

“reg_ifmt_ift_sec_IF_Cropped_height_type
3040Ch 4 00000000h
(ifmt_ift_sec_IF_Cropped_height)—Offset 3040Ch” on page 1069
“reg_ifmt_ift_sec_IF_Cropped_width_type
30410h 4 00000000h
(ifmt_ift_sec_IF_Cropped_width)—Offset 30410h” on page 1070
“reg_ifmt_ift_sec_IF_Vert_Decim_type (ifmt_ift_sec_IF_Vert_Decim)—
30414h 4 00000000h
Offset 30414h” on page 1070
“reg_ifmt_ift_sec_IF_Horiz_Decim_type (ifmt_ift_sec_IF_Horiz_Decim)—
30418h 4 00000000h
Offset 30418h” on page 1071

“reg_ifmt_ift_sec_IF_Horiz_Deinter_type
3041Ch 4 00000000h
(ifmt_ift_sec_IF_Horiz_Deinter)—Offset 3041Ch” on page 1071
“reg_ifmt_ift_sec_IF_Left_Pad_type (ifmt_ift_sec_IF_Left_Pad)—Offset
30420h 4 00000000h
30420h” on page 1072
“reg_ifmt_ift_sec_IF_EOF_Offset_type (ifmt_ift_sec_IF_EOF_Offset)—
30424h 4 00000000h
Offset 30424h” on page 1072

“reg_ifmt_ift_sec_IF_Start_addr_type (ifmt_ift_sec_IF_Start_addr)—
30428h 4 00000000h
Offset 30428h” on page 1073
“reg_ifmt_ift_sec_IF_End_addr_type (ifmt_ift_sec_IF_End_addr)—Offset
3042Ch 4 00000000h
3042Ch” on page 1074
“reg_ifmt_ift_sec_IF_incr_type (ifmt_ift_sec_IF_incr)—Offset 30430h” on
30430h 4 00000000h
page 1074

“reg_ifmt_ift_sec_IF_YUV_420_format_type
30434h 4 00000000h
(ifmt_ift_sec_IF_YUV_420_format)—Offset 30434h” on page 1075
“reg_ifmt_ift_sec_IF_Vsynch_active_low_type
30438h 4 00000000h
(ifmt_ift_sec_IF_Vsynch_active_low)—Offset 30438h” on page 1075

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MIPI-Camera Serial Interface (CSI) & ISP

Table 167. Summary of Image Signal Processor Memory Mapped I/O Registers—
ISPMMADR (Continued)
Offset Size Register ID—Description Default Value

“reg_ifmt_ift_sec_IF_Hsynch_active_low_type
3043Ch 4 00000000h
(ifmt_ift_sec_IF_Hsynch_active_low)—Offset 3043Ch” on page 1076

“reg_ifmt_ift_sec_IF_ReEnable_type (ifmt_ift_sec_IF_ReEnable)—Offset
30440h 4 00000000h
30440h” on page 1077
“reg_ifmt_ift_sec_IF_block_input_type (ifmt_ift_sec_IF_block_input)—
30444h 4 00000000h
Offset 30444h” on page 1077
“reg_ifmt_ift_sec_IF_Vert_Deinter_type (ifmt_ift_sec_IF_Vert_Deinter)—
30448h 4 00000000h
Offset 30448h” on page 1078

“reg_ifmt_ift_sec_IF_FSM_Sync_status_type
30500h 4 00000000h
(ifmt_ift_sec_IF_FSM_Sync_status)—Offset 30500h” on page 1078
“reg_ifmt_ift_sec_FSM_Sync_counter_type
30504h 4 00000000h
(ifmt_ift_sec_FSM_Sync_counter)—Offset 30504h” on page 1079
“reg_ifmt_ift_sec_FSM_Crop_status_type
30508h 4 00000000h
(ifmt_ift_sec_FSM_Crop_status)—Offset 30508h” on page 1080

“reg_ifmt_ift_sec_FSM_Crop_line_counter_type
3050Ch 4 00000000h
(ifmt_ift_sec_FSM_Crop_line_counter)—Offset 3050Ch” on page 1080
“reg_ifmt_ift_sec_FSM_Crop_pixel_counter_type
30510h 4 00000000h
(ifmt_ift_sec_FSM_Crop_pixel_counter)—Offset 30510h” on page 1081
“reg_ifmt_ift_sec_FSM_Deinterl_idx_buffer_type
30514h 4 00000000h
(ifmt_ift_sec_FSM_Deinterl_idx_buffer)—Offset 30514h” on page 1082

“reg_ifmt_ift_sec_FSM_Horiz_Decim_cnt_type
30518h 4 00000000h
(ifmt_ift_sec_FSM_Horiz_Decim_cnt)—Offset 30518h” on page 1082
“reg_ifmt_ift_sec_FSM_Vertic_Decim_cnt_type
3051Ch 4 00000000h
(ifmt_ift_sec_FSM_Vertic_Decim_cnt)—Offset 3051Ch” on page 1083
“reg_ifmt_ift_sec_FSM_Vertic_Block_Decim_cnt_type
30520h 4 (ifmt_ift_sec_FSM_Vertic_Block_Decim_cnt)—Offset 30520h” on 00000000h
page 1084
“reg_ifmt_ift_sec_IF_FSM_Padding_status_type
30524h 4 00000000h
(ifmt_ift_sec_IF_FSM_Padding_status)—Offset 30524h” on page 1084

“reg_ifmt_ift_sec_IF_FSM_Padding_elem_idx_type
30528h 4 00000000h
(ifmt_ift_sec_IF_FSM_Padding_elem_idx)—Offset 30528h” on page 1085

“reg_ifmt_ift_sec_IF_FSM_Vec_Sup_type
3052Ch 4 00000000h
(ifmt_ift_sec_IF_FSM_Vec_Sup)—Offset 3052Ch” on page 1086
“reg_ifmt_ift_sec_IF_FSM_Vec_Sup_Buf_full_type
30530h 4 00000000h
(ifmt_ift_sec_IF_FSM_Vec_Sup_Buf_full)—Offset 30530h” on page 1086
“reg_ifmt_ift_sec_IF_FSM_Vec_Sup_rd_accept_type
30534h 4 00000001h
(ifmt_ift_sec_IF_FSM_Vec_Sup_rd_accept)—Offset 30534h” on page 1087

“reg_ifmt_ift_sec_IF_Pixel_Fifo_status_type
30538h 4 00000001h
(ifmt_ift_sec_IF_Pixel_Fifo_status)—Offset 30538h” on page 1088
“reg_ifmt_mem_cpy_MemCopy_sw_rst_type
30600h 4 00000000h
(ifmt_mem_cpy_MemCopy_sw_rst)—Offset 30600h” on page 1088
“reg_ifmt_mem_cpy_MemCopy_in_endian_type
30604h 4 00000000h
(ifmt_mem_cpy_MemCopy_in_endian)—Offset 30604h” on page 1089

“reg_ifmt_mem_cpy_MemCopy_out_endian_type
30608h 4 00000000h
(ifmt_mem_cpy_MemCopy_out_endian)—Offset 30608h” on page 1090
“reg_ifmt_mem_cpy_MemCopy_bit_swap_type
3060Ch 4 00000000h
(ifmt_mem_cpy_MemCopy_bit_swap)—Offset 3060Ch” on page 1090
“reg_ifmt_mem_cpy_MemCopy_block_synch_type
30610h 4 00000000h
(ifmt_mem_cpy_MemCopy_block_synch)—Offset 30610h” on page 1091

Intel® Atom™ Processor E3800 Product Family

Datasheet 919
 MIPI-Camera Serial Interface (CSI) & ISP

Table 167. Summary of Image Signal Processor Memory Mapped I/O Registers—
ISPMMADR (Continued)
Offset Size Register ID—Description Default Value

“reg_ifmt_mem_cpy_MemCopy_packet_synch_type
30614h 4 00000000h
(ifmt_mem_cpy_MemCopy_packet_synch)—Offset 30614h” on page 1092

“reg_ifmt_mem_cpy_MemCopy_rd_post_wr_sync_type
30618h 4 (ifmt_mem_cpy_MemCopy_rd_post_wr_sync)—Offset 30618h” on 00000000h
page 1092

“reg_ifmt_mem_cpy_MemCopy_dual_input_type
3061Ch 4 00000000h
(ifmt_mem_cpy_MemCopy_dual_input)—Offset 3061Ch” on page 1093
“reg_ifmt_mem_cpy_MemCopy_ReEnable_type
30620h 4 00000000h
(ifmt_mem_cpy_MemCopy_ReEnable)—Offset 30620h” on page 1094
“reg_ifmt_mem_cpy_MemCopy_token_data_type
30700h 4 00000000h
(ifmt_mem_cpy_MemCopy_token_data)—Offset 30700h” on page 1094

“reg_ifmt_mem_cpy_MemCopy_FSM_Sync_status_type
30704h 4 (ifmt_mem_cpy_MemCopy_FSM_Sync_status)—Offset 30704h” on 00000000h
page 1095

“reg_ifmt_mem_cpy_MemCopy_FSM_Sync_bytes_cnt_type
30708h 4 (ifmt_mem_cpy_MemCopy_FSM_Sync_bytes_cnt)—Offset 30708h” on 00000000h
page 1096

“reg_ifmt_mem_cpy_MemCopy_FSM_Sync_token_cnt_type
3070Ch 4 (ifmt_mem_cpy_MemCopy_FSM_Sync_token_cnt)—Offset 3070Ch” on 00000000h
page 1096

“reg_ifmt_mem_cpy_MemCopy_FSM_Pack_idx_cnt_type
30710h 4 (ifmt_mem_cpy_MemCopy_FSM_Pack_idx_cnt)—Offset 30710h” on 00000000h
page 1097

“reg_ifmt_mem_cpy_MemCopy_FSM_Buf_Sup_status_type
30714h 4 (ifmt_mem_cpy_MemCopy_FSM_Buf_Sup_status)—Offset 30714h” on 00000000h
page 1098

“reg_ifmt_mem_cpy_MemCopy_FSM_Buf_Sup_cnt_type
30718h 4 (ifmt_mem_cpy_MemCopy_FSM_Buf_Sup_cnt)—Offset 30718h” on 00000000h
page 1098

“reg_ifmt_mem_cpy_MemCopy_FSM_CioWr_status_type
3071Ch 4 (ifmt_mem_cpy_MemCopy_FSM_CioWr_status)—Offset 3071Ch” on 00000004h
page 1099

“reg_ifmt_mem_cpy_MemCopy_FSM_CioWr_addr_type
30720h 4 (ifmt_mem_cpy_MemCopy_FSM_CioWr_addr)—Offset 30720h” on 00000000h
page 1100
“reg_ifmt_gp_reg_IFMT_input_switch_lut_reg0_type
30800h 4 (ifmt_gp_reg_IFMT_input_switch_lut_reg0)—Offset 30800h” on 00000000h
page 1101
“reg_ifmt_gp_reg_IFMT_input_switch_lut_reg1_type
30804h 4 (ifmt_gp_reg_IFMT_input_switch_lut_reg1)—Offset 30804h” on 00000000h
page 1101
“reg_ifmt_gp_reg_IFMT_input_switch_lut_reg2_type
30808h 4 (ifmt_gp_reg_IFMT_input_switch_lut_reg2)—Offset 30808h” on 00000000h
page 1102
“reg_ifmt_gp_reg_IFMT_input_switch_lut_reg3_type
3080Ch 4 (ifmt_gp_reg_IFMT_input_switch_lut_reg3)—Offset 3080Ch” on 00000000h
page 1103
“reg_ifmt_gp_reg_IFMT_input_switch_lut_reg4_type
30810h 4 (ifmt_gp_reg_IFMT_input_switch_lut_reg4)—Offset 30810h” on 00000000h
page 1103
“reg_ifmt_gp_reg_IFMT_input_switch_lut_reg5_type
30814h 4 (ifmt_gp_reg_IFMT_input_switch_lut_reg5)—Offset 30814h” on 00000000h
page 1104

Intel® Atom™ Processor E3800 Product Family

920 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

Table 167. Summary of Image Signal Processor Memory Mapped I/O Registers—
ISPMMADR (Continued)
Offset Size Register ID—Description Default Value

“reg_ifmt_gp_reg_IFMT_input_switch_lut_reg6_type
30818h 4 (ifmt_gp_reg_IFMT_input_switch_lut_reg6)—Offset 30818h” on 00000000h
page 1104
“reg_ifmt_gp_reg_IFMT_input_switch_lut_reg7_type
3081Ch 4 (ifmt_gp_reg_IFMT_input_switch_lut_reg7)—Offset 3081Ch” on 00000000h
page 1105
“reg_ifmt_gp_reg_IFMT_input_switch_fsync_lut_type
30820h 4 (ifmt_gp_reg_IFMT_input_switch_fsync_lut)—Offset 30820h” on 00000000h
page 1105
“reg_ifmt_gp_reg_IFMT_srst_type (ifmt_gp_reg_IFMT_srst)—Offset
30824h 4 00000000h
30824h” on page 1106

“reg_ifmt_gp_reg_IFMT_slv_reg_srst_type
30828h 4 00000000h
(ifmt_gp_reg_IFMT_slv_reg_srst)—Offset 30828h” on page 1107
“reg_ifmt_gp_reg_IFMT_input_switch_ch_id_fmt_type_type
3082Ch 4 (ifmt_gp_reg_IFMT_input_switch_ch_id_fmt_type)—Offset 3082Ch” on 00000000h
page 1108
“reg_ifmt_irq_ctrl_IFMT_IRQ_ctrl_edge_type
30A00h 4 00000000h
(ifmt_irq_ctrl_IFMT_IRQ_ctrl_edge)—Offset 30A00h” on page 1108
“reg_ifmt_irq_ctrl_IFMT_IRQ_ctrl_mask_type
30A04h 4 00000000h
(ifmt_irq_ctrl_IFMT_IRQ_ctrl_mask)—Offset 30A04h” on page 1109

“reg_ifmt_irq_ctrl_IFMT_IRQ_ctrl_status_type
30A08h 4 00000000h
(ifmt_irq_ctrl_IFMT_IRQ_ctrl_status)—Offset 30A08h” on page 1110
“reg_ifmt_irq_ctrl_IFMT_IRQ_ctrl_clear_type
30A0Ch 4 00000000h
(ifmt_irq_ctrl_IFMT_IRQ_ctrl_clear)—Offset 30A0Ch” on page 1110
“reg_ifmt_irq_ctrl_IFMT_IRQ_ctrl_enable_type
30A10h 4 00000000h
(ifmt_irq_ctrl_IFMT_IRQ_ctrl_enable)—Offset 30A10h” on page 1111

“reg_ifmt_irq_ctrl_IFMT_IRQ_ctrl_edge_pulse_type
30A14h 4 00000000h
(ifmt_irq_ctrl_IFMT_IRQ_ctrl_edge_pulse)—Offset 30A14h” on page 1112
“reg_isp_dma_DMA_FSM_Command_type
40000h 4 00000001h
(isp_dma_DMA_FSM_Command)—Offset 40000h” on page 1112
“reg_isp_dma_DMA_CH0_Packing_setup_type
41000h 4 00000000h
(isp_dma_DMA_CH0_Packing_setup)—Offset 41000h” on page 1113
“reg_isp_dma_DMA_CH1_Packing_setup_type
41004h 4 00000000h
(isp_dma_DMA_CH1_Packing_setup)—Offset 41004h” on page 1114

“reg_isp_dma_DMA_CH2_Packing_setup_type
41008h 4 00000000h
(isp_dma_DMA_CH2_Packing_setup)—Offset 41008h” on page 1114
“reg_isp_dma_DMA_CH3_Packing_setup_type
4100Ch 4 00000000h
(isp_dma_DMA_CH3_Packing_setup)—Offset 4100Ch” on page 1115
“reg_isp_dma_DMA_CH4_Packing_setup_type
41010h 4 00000000h
(isp_dma_DMA_CH4_Packing_setup)—Offset 41010h” on page 1116

“reg_isp_dma_DMA_CH5_Packing_setup_type
41014h 4 00000000h
(isp_dma_DMA_CH5_Packing_setup)—Offset 41014h” on page 1117
“reg_isp_dma_DMA_CH6_Packing_setup_type
41018h 4 00000000h
(isp_dma_DMA_CH6_Packing_setup)—Offset 41018h” on page 1118
“reg_isp_dma_DMA_CH7_Packing_setup_type
4101Ch 4 00000000h
(isp_dma_DMA_CH7_Packing_setup)—Offset 4101Ch” on page 1118

“reg_isp_dma_DMA_CH8_Packing_setup_type
41020h 4 00000000h
(isp_dma_DMA_CH8_Packing_setup)—Offset 41020h” on page 1119
“reg_isp_dma_DMA_CH9_Packing_setup_type
41024h 4 00000000h
(isp_dma_DMA_CH9_Packing_setup)—Offset 41024h” on page 1120

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Datasheet 921
 MIPI-Camera Serial Interface (CSI) & ISP

Table 167. Summary of Image Signal Processor Memory Mapped I/O Registers—
ISPMMADR (Continued)
Offset Size Register ID—Description Default Value

“reg_isp_dma_DMA_CH10_Packing_setup_type
41028h 4 00000000h
(isp_dma_DMA_CH10_Packing_setup)—Offset 41028h” on page 1121

“reg_isp_dma_DMA_CH11_Packing_setup_type
4102Ch 4 00000000h
(isp_dma_DMA_CH11_Packing_setup)—Offset 4102Ch” on page 1121
“reg_isp_dma_DMA_CH12_Packing_setup_type
41030h 4 00000000h
(isp_dma_DMA_CH12_Packing_setup)—Offset 41030h” on page 1122
“reg_isp_dma_DMA_CH13_Packing_setup_type
41034h 4 00000000h
(isp_dma_DMA_CH13_Packing_setup)—Offset 41034h” on page 1123

“reg_isp_dma_DMA_CH14_Packing_setup_type
41038h 4 00000000h
(isp_dma_DMA_CH14_Packing_setup)—Offset 41038h” on page 1124
“reg_isp_dma_DMA_CH15_Packing_setup_type
4103Ch 4 00000000h
(isp_dma_DMA_CH15_Packing_setup)—Offset 4103Ch” on page 1124
“reg_isp_dma_DMA_CH16_Packing_setup_type
41040h 4 00000000h
(isp_dma_DMA_CH16_Packing_setup)—Offset 41040h” on page 1125

“reg_isp_dma_DMA_CH17_Packing_setup_type
41044h 4 00000000h
(isp_dma_DMA_CH17_Packing_setup)—Offset 41044h” on page 1126
“reg_isp_dma_DMA_CH18_Packing_setup_type
41048h 4 00000000h
(isp_dma_DMA_CH18_Packing_setup)—Offset 41048h” on page 1127
“reg_isp_dma_DMA_CH19_Packing_setup_type
4104Ch 4 00000000h
(isp_dma_DMA_CH19_Packing_setup)—Offset 4104Ch” on page 1127

“reg_isp_dma_DMA_CH20_Packing_setup_type
41050h 4 00000000h
(isp_dma_DMA_CH20_Packing_setup)—Offset 41050h” on page 1128
“reg_isp_dma_DMA_CH21_Packing_setup_type
41054h 4 00000000h
(isp_dma_DMA_CH21_Packing_setup)—Offset 41054h” on page 1129
“reg_isp_dma_DMA_CH22_Packing_setup_type
41058h 4 00000000h
(isp_dma_DMA_CH22_Packing_setup)—Offset 41058h” on page 1130

“reg_isp_dma_DMA_CH23_Packing_setup_type
4105Ch 4 00000000h
(isp_dma_DMA_CH23_Packing_setup)—Offset 4105Ch” on page 1130
“reg_isp_dma_DMA_CH24_Packing_setup_type
41060h 4 00000000h
(isp_dma_DMA_CH24_Packing_setup)—Offset 41060h” on page 1131
“reg_isp_dma_DMA_CH25_Packing_setup_type
41064h 4 00000000h
(isp_dma_DMA_CH25_Packing_setup)—Offset 41064h” on page 1132
“reg_isp_dma_DMA_CH26_Packing_setup_type
41068h 4 00000000h
(isp_dma_DMA_CH26_Packing_setup)—Offset 41068h” on page 1133

“reg_isp_dma_DMA_CH28_Packing_setup_type
41070h 4 00000000h
(isp_dma_DMA_CH28_Packing_setup)—Offset 41070h” on page 1133
“reg_isp_dma_DMA_CH29_Packing_setup_type
41074h 4 00000000h
(isp_dma_DMA_CH29_Packing_setup)—Offset 41074h” on page 1134
“reg_isp_dma_DMA_CH30_Packing_setup_type
41078h 4 00000000h
(isp_dma_DMA_CH30_Packing_setup)—Offset 41078h” on page 1135

“reg_isp_dma_DMA_CH31_Packing_setup_type
4107Ch 4 00000000h
(isp_dma_DMA_CH31_Packing_setup)—Offset 4107Ch” on page 1136
“reg_isp_dma_DMA_CH0_dev_stride_A_type
41100h 4 00000000h
(isp_dma_DMA_CH0_dev_stride_A)—Offset 41100h” on page 1136
“reg_isp_dma_DMA_CH1_dev_stride_A_type
41104h 4 00000000h
(isp_dma_DMA_CH1_dev_stride_A)—Offset 41104h” on page 1137

“reg_isp_dma_DMA_CH2_dev_stride_A_type
41108h 4 00000000h
(isp_dma_DMA_CH2_dev_stride_A)—Offset 41108h” on page 1137

Intel® Atom™ Processor E3800 Product Family

922 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

Table 167. Summary of Image Signal Processor Memory Mapped I/O Registers—
ISPMMADR (Continued)
Offset Size Register ID—Description Default Value

“reg_isp_dma_DMA_CH3_dev_stride_A_type
4110Ch 4 00000000h
(isp_dma_DMA_CH3_dev_stride_A)—Offset 4110Ch” on page 1138

“reg_isp_dma_DMA_CH4_dev_stride_A_type
41110h 4 00000000h
(isp_dma_DMA_CH4_dev_stride_A)—Offset 41110h” on page 1138
“reg_isp_dma_DMA_CH5_dev_stride_A_type
41114h 4 00000000h
(isp_dma_DMA_CH5_dev_stride_A)—Offset 41114h” on page 1139
“reg_isp_dma_DMA_CH6_dev_stride_A_type
41118h 4 00000000h
(isp_dma_DMA_CH6_dev_stride_A)—Offset 41118h” on page 1139

“reg_isp_dma_DMA_CH7_dev_stride_A_type
4111Ch 4 00000000h
(isp_dma_DMA_CH7_dev_stride_A)—Offset 4111Ch” on page 1140
“reg_isp_dma_DMA_CH8_dev_stride_A_type
41120h 4 00000000h
(isp_dma_DMA_CH8_dev_stride_A)—Offset 41120h” on page 1140
“reg_isp_dma_DMA_CH9_dev_stride_A_type
41124h 4 00000000h
(isp_dma_DMA_CH9_dev_stride_A)—Offset 41124h” on page 1141

“reg_isp_dma_DMA_CH10_dev_stride_A_type
41128h 4 00000000h
(isp_dma_DMA_CH10_dev_stride_A)—Offset 41128h” on page 1141
“reg_isp_dma_DMA_CH11_dev_stride_A_type
4112Ch 4 00000000h
(isp_dma_DMA_CH11_dev_stride_A)—Offset 4112Ch” on page 1142
“reg_isp_dma_DMA_CH12_dev_stride_A_type
41130h 4 00000000h
(isp_dma_DMA_CH12_dev_stride_A)—Offset 41130h” on page 1142

“reg_isp_dma_DMA_CH13_dev_stride_A_type
41134h 4 00000000h
(isp_dma_DMA_CH13_dev_stride_A)—Offset 41134h” on page 1143
“reg_isp_dma_DMA_CH14_dev_stride_A_type
41138h 4 00000000h
(isp_dma_DMA_CH14_dev_stride_A)—Offset 41138h” on page 1144
“reg_isp_dma_DMA_CH15_dev_stride_A_type
4113Ch 4 00000000h
(isp_dma_DMA_CH15_dev_stride_A)—Offset 4113Ch” on page 1144

“reg_isp_dma_DMA_CH16_dev_stride_A_type
41140h 4 00000000h
(isp_dma_DMA_CH16_dev_stride_A)—Offset 41140h” on page 1145
“reg_isp_dma_DMA_CH17_dev_stride_A_type
41144h 4 00000000h
(isp_dma_DMA_CH17_dev_stride_A)—Offset 41144h” on page 1145
“reg_isp_dma_DMA_CH18_dev_stride_A_type
41148h 4 00000000h
(isp_dma_DMA_CH18_dev_stride_A)—Offset 41148h” on page 1146
“reg_isp_dma_DMA_CH19_dev_stride_A_type
4114Ch 4 00000000h
(isp_dma_DMA_CH19_dev_stride_A)—Offset 4114Ch” on page 1146

“reg_isp_dma_DMA_CH20_dev_stride_A_type
41150h 4 00000000h
(isp_dma_DMA_CH20_dev_stride_A)—Offset 41150h” on page 1147
“reg_isp_dma_DMA_CH21_dev_stride_A_type
41154h 4 00000000h
(isp_dma_DMA_CH21_dev_stride_A)—Offset 41154h” on page 1147
“reg_isp_dma_DMA_CH0_dev_Pack_left_crop_and_elem_A_type
41200h 4 (isp_dma_DMA_CH0_dev_Pack_left_crop_and_elem_A)—Offset 41200h” 00000000h
on page 1148
“reg_isp_dma_DMA_CH1_dev_Pack_left_crop_and_elem_A_type
41204h 4 (isp_dma_DMA_CH1_dev_Pack_left_crop_and_elem_A)—Offset 41204h” 00000000h
on page 1149
“reg_isp_dma_DMA_CH2_dev_Pack_left_crop_and_elem_A_type
41208h 4 (isp_dma_DMA_CH2_dev_Pack_left_crop_and_elem_A)—Offset 41208h” 00000000h
on page 1150
“reg_isp_dma_DMA_CH3_dev_Pack_left_crop_and_elem_A_type
4120Ch 4 (isp_dma_DMA_CH3_dev_Pack_left_crop_and_elem_A)—Offset 4120Ch” 00000000h
on page 1151

Intel® Atom™ Processor E3800 Product Family

Datasheet 923
 MIPI-Camera Serial Interface (CSI) & ISP

Table 167. Summary of Image Signal Processor Memory Mapped I/O Registers—
ISPMMADR (Continued)
Offset Size Register ID—Description Default Value

“reg_isp_dma_DMA_CH4_dev_Pack_left_crop_and_elem_A_type
41210h 4 (isp_dma_DMA_CH4_dev_Pack_left_crop_and_elem_A)—Offset 41210h” 00000000h
on page 1152
“reg_isp_dma_DMA_CH5_dev_Pack_left_crop_and_elem_A_type
41214h 4 (isp_dma_DMA_CH5_dev_Pack_left_crop_and_elem_A)—Offset 41214h” 00000000h
on page 1153
“reg_isp_dma_DMA_CH6_dev_Pack_left_crop_and_elem_A_type
41218h 4 (isp_dma_DMA_CH6_dev_Pack_left_crop_and_elem_A)—Offset 41218h” 00000000h
on page 1154
“reg_isp_dma_DMA_CH7_dev_Pack_left_crop_and_elem_A_type
4121Ch 4 (isp_dma_DMA_CH7_dev_Pack_left_crop_and_elem_A)—Offset 4121Ch” 00000000h
on page 1155
“reg_isp_dma_DMA_CH8_dev_Pack_left_crop_and_elem_A_type
41220h 4 (isp_dma_DMA_CH8_dev_Pack_left_crop_and_elem_A)—Offset 41220h” 00000000h
on page 1156
“reg_isp_dma_DMA_CH9_dev_Pack_left_crop_and_elem_A_type
41224h 4 (isp_dma_DMA_CH9_dev_Pack_left_crop_and_elem_A)—Offset 41224h” 00000000h
on page 1157
“reg_isp_dma_DMA_CH10_dev_Pack_left_crop_and_elem_A_type
41228h 4 (isp_dma_DMA_CH10_dev_Pack_left_crop_and_elem_A)—Offset 41228h” 00000000h
on page 1158
“reg_isp_dma_DMA_CH11_dev_Pack_left_crop_and_elem_A_type
4122Ch 4 (isp_dma_DMA_CH11_dev_Pack_left_crop_and_elem_A)—Offset 4122Ch” 00000000h
on page 1159
“reg_isp_dma_DMA_CH12_dev_Pack_left_crop_and_elem_A_type
41230h 4 (isp_dma_DMA_CH12_dev_Pack_left_crop_and_elem_A)—Offset 41230h” 00000000h
on page 1160
“reg_isp_dma_DMA_CH13_dev_Pack_left_crop_and_elem_A_type
41234h 4 (isp_dma_DMA_CH13_dev_Pack_left_crop_and_elem_A)—Offset 41234h” 00000000h
on page 1161
“reg_isp_dma_DMA_CH14_dev_Pack_left_crop_and_elem_A_type
41238h 4 (isp_dma_DMA_CH14_dev_Pack_left_crop_and_elem_A)—Offset 41238h” 00000000h
on page 1162
“reg_isp_dma_DMA_CH15_dev_Pack_left_crop_and_elem_A_type
4123Ch 4 (isp_dma_DMA_CH15_dev_Pack_left_crop_and_elem_A)—Offset 4123Ch” 00000000h
on page 1163
“reg_isp_dma_DMA_CH16_dev_Pack_left_crop_and_elem_A_type
41240h 4 (isp_dma_DMA_CH16_dev_Pack_left_crop_and_elem_A)—Offset 41240h” 00000000h
on page 1164
“reg_isp_dma_DMA_CH17_dev_Pack_left_crop_and_elem_A_type
41244h 4 (isp_dma_DMA_CH17_dev_Pack_left_crop_and_elem_A)—Offset 41244h” 00000000h
on page 1165
“reg_isp_dma_DMA_CH18_dev_Pack_left_crop_and_elem_A_type
41248h 4 (isp_dma_DMA_CH18_dev_Pack_left_crop_and_elem_A)—Offset 41248h” 00000000h
on page 1166
“reg_isp_dma_DMA_CH19_dev_Pack_left_crop_and_elem_A_type
4124Ch 4 (isp_dma_DMA_CH19_dev_Pack_left_crop_and_elem_A)—Offset 4124Ch” 00000000h
on page 1167
“reg_isp_dma_DMA_CH20_dev_Pack_left_crop_and_elem_A_type
41250h 4 (isp_dma_DMA_CH20_dev_Pack_left_crop_and_elem_A)—Offset 41250h” 00000000h
on page 1168
“reg_isp_dma_DMA_CH21_dev_Pack_left_crop_and_elem_A_type
41254h 4 (isp_dma_DMA_CH21_dev_Pack_left_crop_and_elem_A)—Offset 41254h” 00000000h
on page 1169

Intel® Atom™ Processor E3800 Product Family

924 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

Table 167. Summary of Image Signal Processor Memory Mapped I/O Registers—
ISPMMADR (Continued)
Offset Size Register ID—Description Default Value

“reg_isp_dma_DMA_CH22_dev_Pack_left_crop_and_elem_A_type
41258h 4 (isp_dma_DMA_CH22_dev_Pack_left_crop_and_elem_A)—Offset 41258h” 00000000h
on page 1170
“reg_isp_dma_DMA_CH23_dev_Pack_left_crop_and_elem_A_type
4125Ch 4 (isp_dma_DMA_CH23_dev_Pack_left_crop_and_elem_A)—Offset 4125Ch” 00000000h
on page 1171
“reg_isp_dma_DMA_CH24_dev_Pack_left_crop_and_elem_A_type
41260h 4 (isp_dma_DMA_CH24_dev_Pack_left_crop_and_elem_A)—Offset 41260h” 00000000h
on page 1172
“reg_isp_dma_DMA_CH25_dev_Pack_left_crop_and_elem_A_type
41264h 4 (isp_dma_DMA_CH25_dev_Pack_left_crop_and_elem_A)—Offset 41264h” 00000000h
on page 1173
“reg_isp_dma_DMA_CH26_dev_Pack_left_crop_and_elem_A_type
41268h 4 (isp_dma_DMA_CH26_dev_Pack_left_crop_and_elem_A)—Offset 41268h” 00000000h
on page 1174
“reg_isp_dma_DMA_CH27_dev_Pack_left_crop_and_elem_A_type
4126Ch 4 (isp_dma_DMA_CH27_dev_Pack_left_crop_and_elem_A)—Offset 4126Ch” 00000000h
on page 1175
“reg_isp_dma_DMA_CH28_dev_Pack_left_crop_and_elem_A_type
41270h 4 (isp_dma_DMA_CH28_dev_Pack_left_crop_and_elem_A)—Offset 41270h” 00000000h
on page 1176
“reg_isp_dma_DMA_CH29_dev_Pack_left_crop_and_elem_A_type
41274h 4 (isp_dma_DMA_CH29_dev_Pack_left_crop_and_elem_A)—Offset 41274h” 00000000h
on page 1177
“reg_isp_dma_DMA_CH30_dev_Pack_left_crop_and_elem_A_type
41278h 4 (isp_dma_DMA_CH30_dev_Pack_left_crop_and_elem_A)—Offset 41278h” 00000000h
on page 1178
“reg_isp_dma_DMA_CH31_dev_Pack_left_crop_and_elem_A_type
4127Ch 4 (isp_dma_DMA_CH31_dev_Pack_left_crop_and_elem_A)—Offset 4127Ch” 00000000h
on page 1179
“reg_isp_dma_DMA_CH22_dev_stride_A_type
412C0h 4 00000000h
(isp_dma_DMA_CH22_dev_stride_A)—Offset 412C0h” on page 1180

“reg_isp_dma_DMA_CH23_dev_stride_A_type
412C4h 4 00000000h
(isp_dma_DMA_CH23_dev_stride_A)—Offset 412C4h” on page 1181

“reg_isp_dma_DMA_CH24_dev_stride_A_type
412C8h 4 00000000h
(isp_dma_DMA_CH24_dev_stride_A)—Offset 412C8h” on page 1181
“reg_isp_dma_DMA_CH25_dev_stride_A_type
412CCh 4 00000000h
(isp_dma_DMA_CH25_dev_stride_A)—Offset 412CCh” on page 1182
“reg_isp_dma_DMA_CH26_dev_stride_A_type
412D0h 4 00000000h
(isp_dma_DMA_CH26_dev_stride_A)—Offset 412D0h” on page 1182

“reg_isp_dma_DMA_CH27_dev_stride_A_type
412D4h 4 00000000h
(isp_dma_DMA_CH27_dev_stride_A)—Offset 412D4h” on page 1183
“reg_isp_dma_DMA_CH28_dev_stride_A_type
412D8h 4 00000000h
(isp_dma_DMA_CH28_dev_stride_A)—Offset 412D8h” on page 1184
“reg_isp_dma_DMA_CH29_dev_stride_A_type
412DCh 4 00000000h
(isp_dma_DMA_CH29_dev_stride_A)—Offset 412DCh” on page 1184

“reg_isp_dma_DMA_CH30_dev_stride_A_type
412E0h 4 00000000h
(isp_dma_DMA_CH30_dev_stride_A)—Offset 412E0h” on page 1185
“reg_isp_dma_DMA_CH31_dev_stride_A_type
412E4h 4 00000000h
(isp_dma_DMA_CH31_dev_stride_A)—Offset 412E4h” on page 1185
“reg_isp_dma_DMA_CH0_Device_Xb_A_type
41300h 4 00000000h
(isp_dma_DMA_CH0_Device_Xb_A)—Offset 41300h” on page 1186

Intel® Atom™ Processor E3800 Product Family

Datasheet 925
 MIPI-Camera Serial Interface (CSI) & ISP

Table 167. Summary of Image Signal Processor Memory Mapped I/O Registers—
ISPMMADR (Continued)
Offset Size Register ID—Description Default Value

“reg_isp_dma_DMA_CH1_Device_Xb_A_type
41304h 4 00000000h
(isp_dma_DMA_CH1_Device_Xb_A)—Offset 41304h” on page 1186

“reg_isp_dma_DMA_CH2_Device_Xb_A_type
41308h 4 00000000h
(isp_dma_DMA_CH2_Device_Xb_A)—Offset 41308h” on page 1187
“reg_isp_dma_DMA_CH3_Device_Xb_A_type
4130Ch 4 00000000h
(isp_dma_DMA_CH3_Device_Xb_A)—Offset 4130Ch” on page 1188
“reg_isp_dma_DMA_CH4_Device_Xb_A_type
41310h 4 00000000h
(isp_dma_DMA_CH4_Device_Xb_A)—Offset 41310h” on page 1188

“reg_isp_dma_DMA_CH5_Device_Xb_A_type
41314h 4 00000000h
(isp_dma_DMA_CH5_Device_Xb_A)—Offset 41314h” on page 1189
“reg_isp_dma_DMA_CH6_Device_Xb_A_type
41318h 4 00000000h
(isp_dma_DMA_CH6_Device_Xb_A)—Offset 41318h” on page 1190
“reg_isp_dma_DMA_CH7_Device_Xb_A_type
4131Ch 4 00000000h
(isp_dma_DMA_CH7_Device_Xb_A)—Offset 4131Ch” on page 1190

“reg_isp_dma_DMA_CH8_Device_Xb_A_type
41320h 4 00000000h
(isp_dma_DMA_CH8_Device_Xb_A)—Offset 41320h” on page 1191
“reg_isp_dma_DMA_CH9_Device_Xb_A_type
41324h 4 00000000h
(isp_dma_DMA_CH9_Device_Xb_A)—Offset 41324h” on page 1192
“reg_isp_dma_DMA_CH10_Device_Xb_A_type
41328h 4 00000000h
(isp_dma_DMA_CH10_Device_Xb_A)—Offset 41328h” on page 1192

“reg_isp_dma_DMA_CH11_Device_Xb_A_type
4132Ch 4 00000000h
(isp_dma_DMA_CH11_Device_Xb_A)—Offset 4132Ch” on page 1193
“reg_isp_dma_DMA_CH12_Device_Xb_A_type
41330h 4 00000000h
(isp_dma_DMA_CH12_Device_Xb_A)—Offset 41330h” on page 1194
“reg_isp_dma_DMA_CH13_Device_Xb_A_type
41334h 4 00000000h
(isp_dma_DMA_CH13_Device_Xb_A)—Offset 41334h” on page 1194

“reg_isp_dma_DMA_CH14_Device_Xb_A_type
41338h 4 00000000h
(isp_dma_DMA_CH14_Device_Xb_A)—Offset 41338h” on page 1195
“reg_isp_dma_DMA_CH15_Device_Xb_A_type
4133Ch 4 00000000h
(isp_dma_DMA_CH15_Device_Xb_A)—Offset 4133Ch” on page 1196
“reg_isp_dma_DMA_CH16_Device_Xb_A_type
41340h 4 00000000h
(isp_dma_DMA_CH16_Device_Xb_A)—Offset 41340h” on page 1196
“reg_isp_dma_DMA_CH17_Device_Xb_A_type
41344h 4 00000000h
(isp_dma_DMA_CH17_Device_Xb_A)—Offset 41344h” on page 1197

“reg_isp_dma_DMA_CH18_Device_Xb_A_type
41348h 4 00000000h
(isp_dma_DMA_CH18_Device_Xb_A)—Offset 41348h” on page 1198
“reg_isp_dma_DMA_CH19_Device_Xb_A_type
4134Ch 4 00000000h
(isp_dma_DMA_CH19_Device_Xb_A)—Offset 4134Ch” on page 1198
“reg_isp_dma_DMA_CH20_Device_Xb_A_type
41350h 4 00000000h
(isp_dma_DMA_CH20_Device_Xb_A)—Offset 41350h” on page 1199

“reg_isp_dma_DMA_CH21_Device_Xb_A_type
41354h 4 00000000h
(isp_dma_DMA_CH21_Device_Xb_A)—Offset 41354h” on page 1200
“reg_isp_dma_DMA_CH22_Device_Xb_A_type
41358h 4 00000000h
(isp_dma_DMA_CH22_Device_Xb_A)—Offset 41358h” on page 1200
“reg_isp_dma_DMA_CH23_Device_Xb_A_type
4135Ch 4 00000000h
(isp_dma_DMA_CH23_Device_Xb_A)—Offset 4135Ch” on page 1201

“reg_isp_dma_DMA_CH24_Device_Xb_A_type
41360h 4 00000000h
(isp_dma_DMA_CH24_Device_Xb_A)—Offset 41360h” on page 1202

Intel® Atom™ Processor E3800 Product Family

926 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

Table 167. Summary of Image Signal Processor Memory Mapped I/O Registers—
ISPMMADR (Continued)
Offset Size Register ID—Description Default Value

“reg_isp_dma_DMA_CH25_Device_Xb_A_type
41364h 4 00000000h
(isp_dma_DMA_CH25_Device_Xb_A)—Offset 41364h” on page 1202

“reg_isp_dma_DMA_CH26_Device_Xb_A_type
41368h 4 00000000h
(isp_dma_DMA_CH26_Device_Xb_A)—Offset 41368h” on page 1203
“reg_isp_dma_DMA_CH27_Device_Xb_A_type
4136Ch 4 00000000h
(isp_dma_DMA_CH27_Device_Xb_A)—Offset 4136Ch” on page 1204
“reg_isp_dma_DMA_CH28_Device_Xb_A_type
41370h 4 00000000h
(isp_dma_DMA_CH28_Device_Xb_A)—Offset 41370h” on page 1204

“reg_isp_dma_DMA_CH29_Device_Xb_A_type
41374h 4 00000000h
(isp_dma_DMA_CH29_Device_Xb_A)—Offset 41374h” on page 1205
“reg_isp_dma_DMA_CH30_Device_Xb_A_type
41378h 4 00000000h
(isp_dma_DMA_CH30_Device_Xb_A)—Offset 41378h” on page 1206
“reg_isp_dma_DMA_CH31_Device_Xb_A_type
4137Ch 4 00000000h
(isp_dma_DMA_CH31_Device_Xb_A)—Offset 4137Ch” on page 1206

“reg_isp_dma_DMA_CH0_dev_stride_B_type
41400h 4 00000000h
(isp_dma_DMA_CH0_dev_stride_B)—Offset 41400h” on page 1207
“reg_isp_dma_DMA_CH1_dev_stride_B_type
41404h 4 00000000h
(isp_dma_DMA_CH1_dev_stride_B)—Offset 41404h” on page 1207
“reg_isp_dma_DMA_CH2_dev_stride_B_type
41408h 4 00000000h
(isp_dma_DMA_CH2_dev_stride_B)—Offset 41408h” on page 1208

“reg_isp_dma_DMA_CH3_dev_stride_B_type
4140Ch 4 00000000h
(isp_dma_DMA_CH3_dev_stride_B)—Offset 4140Ch” on page 1209
“reg_isp_dma_DMA_CH4_dev_stride_B_type
41410h 4 00000000h
(isp_dma_DMA_CH4_dev_stride_B)—Offset 41410h” on page 1209
“reg_isp_dma_DMA_CH5_dev_stride_B_type
41414h 4 00000000h
(isp_dma_DMA_CH5_dev_stride_B)—Offset 41414h” on page 1210

“reg_isp_dma_DMA_CH6_dev_stride_B_type
41418h 4 00000000h
(isp_dma_DMA_CH6_dev_stride_B)—Offset 41418h” on page 1210
“reg_isp_dma_DMA_CH7_dev_stride_B_type
4141Ch 4 00000000h
(isp_dma_DMA_CH7_dev_stride_B)—Offset 4141Ch” on page 1211
“reg_isp_dma_DMA_CH8_dev_stride_B_type
41420h 4 00000000h
(isp_dma_DMA_CH8_dev_stride_B)—Offset 41420h” on page 1211
“reg_isp_dma_DMA_CH9_dev_stride_B_type
41424h 4 00000000h
(isp_dma_DMA_CH9_dev_stride_B)—Offset 41424h” on page 1212

“reg_isp_dma_DMA_CH10_dev_stride_B_type
41428h 4 00000000h
(isp_dma_DMA_CH10_dev_stride_B)—Offset 41428h” on page 1212
“reg_isp_dma_DMA_CH11_dev_stride_B_type
4142Ch 4 00000000h
(isp_dma_DMA_CH11_dev_stride_B)—Offset 4142Ch” on page 1213
“reg_isp_dma_DMA_CH12_dev_stride_B_type
41430h 4 00000000h
(isp_dma_DMA_CH12_dev_stride_B)—Offset 41430h” on page 1213

“reg_isp_dma_DMA_CH13_dev_stride_B_type
41434h 4 00000000h
(isp_dma_DMA_CH13_dev_stride_B)—Offset 41434h” on page 1214
“reg_isp_dma_DMA_CH14_dev_stride_B_type
41438h 4 00000000h
(isp_dma_DMA_CH14_dev_stride_B)—Offset 41438h” on page 1214
“reg_isp_dma_DMA_CH15_dev_stride_B_type
4143Ch 4 00000000h
(isp_dma_DMA_CH15_dev_stride_B)—Offset 4143Ch” on page 1215

“reg_isp_dma_DMA_CH16_dev_stride_B_type
41440h 4 00000000h
(isp_dma_DMA_CH16_dev_stride_B)—Offset 41440h” on page 1215

Intel® Atom™ Processor E3800 Product Family

Datasheet 927
 MIPI-Camera Serial Interface (CSI) & ISP

Table 167. Summary of Image Signal Processor Memory Mapped I/O Registers—
ISPMMADR (Continued)
Offset Size Register ID—Description Default Value

“reg_isp_dma_DMA_CH17_dev_stride_B_type
41444h 4 00000000h
(isp_dma_DMA_CH17_dev_stride_B)—Offset 41444h” on page 1216

“reg_isp_dma_DMA_CH18_dev_stride_B_type
41448h 4 00000000h
(isp_dma_DMA_CH18_dev_stride_B)—Offset 41448h” on page 1216
“reg_isp_dma_DMA_CH19_dev_stride_B_type
4144Ch 4 00000000h
(isp_dma_DMA_CH19_dev_stride_B)—Offset 4144Ch” on page 1217
“reg_isp_dma_DMA_CH20_dev_stride_B_type
41450h 4 00000000h
(isp_dma_DMA_CH20_dev_stride_B)—Offset 41450h” on page 1218

“reg_isp_dma_DMA_CH21_dev_stride_B_type
41454h 4 00000000h
(isp_dma_DMA_CH21_dev_stride_B)—Offset 41454h” on page 1218
“reg_isp_dma_DMA_CH22_dev_stride_B_type
41458h 4 00000000h
(isp_dma_DMA_CH22_dev_stride_B)—Offset 41458h” on page 1219
“reg_isp_dma_DMA_CH23_dev_stride_B_type
4145Ch 4 00000000h
(isp_dma_DMA_CH23_dev_stride_B)—Offset 4145Ch” on page 1219

“reg_isp_dma_DMA_CH24_dev_stride_B_type
41460h 4 00000000h
(isp_dma_DMA_CH24_dev_stride_B)—Offset 41460h” on page 1220
“reg_isp_dma_DMA_CH26_dev_stride_B_type
41468h 4 00000000h
(isp_dma_DMA_CH26_dev_stride_B)—Offset 41468h” on page 1220
“reg_isp_dma_DMA_CH27_dev_stride_B_type
4146Ch 4 00000000h
(isp_dma_DMA_CH27_dev_stride_B)—Offset 4146Ch” on page 1221

“reg_isp_dma_DMA_CH28_dev_stride_B_type
41470h 4 00000000h
(isp_dma_DMA_CH28_dev_stride_B)—Offset 41470h” on page 1221
“reg_isp_dma_DMA_CH29_dev_stride_B_type
41474h 4 00000000h
(isp_dma_DMA_CH29_dev_stride_B)—Offset 41474h” on page 1222
“reg_isp_dma_DMA_CH30_dev_stride_B_type
41478h 4 00000000h
(isp_dma_DMA_CH30_dev_stride_B)—Offset 41478h” on page 1223

“reg_isp_dma_DMA_CH31_dev_stride_B_type
4147Ch 4 00000000h
(isp_dma_DMA_CH31_dev_stride_B)—Offset 4147Ch” on page 1223
“reg_isp_dma_DMA_CH0_dev_Pack_left_crop_and_elem_B_type
41500h 4 (isp_dma_DMA_CH0_dev_Pack_left_crop_and_elem_B)—Offset 41500h” 00000000h
on page 1224

“reg_isp_dma_DMA_CH1_dev_Pack_left_crop_and_elem_B_type
41504h 4 (isp_dma_DMA_CH1_dev_Pack_left_crop_and_elem_B)—Offset 41504h” 00000000h
on page 1225

“reg_isp_dma_DMA_CH2_dev_Pack_left_crop_and_elem_B_type
41508h 4 (isp_dma_DMA_CH2_dev_Pack_left_crop_and_elem_B)—Offset 41508h” 00000000h
on page 1225

“reg_isp_dma_DMA_CH3_dev_Pack_left_crop_and_elem_B_type
4150Ch 4 (isp_dma_DMA_CH3_dev_Pack_left_crop_and_elem_B)—Offset 4150Ch” 00000000h
on page 1226

“reg_isp_dma_DMA_CH4_dev_Pack_left_crop_and_elem_B_type
41510h 4 (isp_dma_DMA_CH4_dev_Pack_left_crop_and_elem_B)—Offset 41510h” 00000000h
on page 1227

“reg_isp_dma_DMA_CH5_dev_Pack_left_crop_and_elem_B_type
41514h 4 (isp_dma_DMA_CH5_dev_Pack_left_crop_and_elem_B)—Offset 41514h” 00000000h
on page 1228

“reg_isp_dma_DMA_CH6_dev_Pack_left_crop_and_elem_B_type
41518h 4 (isp_dma_DMA_CH6_dev_Pack_left_crop_and_elem_B)—Offset 41518h” 00000000h
on page 1229

Intel® Atom™ Processor E3800 Product Family

928 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

Table 167. Summary of Image Signal Processor Memory Mapped I/O Registers—
ISPMMADR (Continued)
Offset Size Register ID—Description Default Value

“reg_isp_dma_DMA_CH7_dev_Pack_left_crop_and_elem_B_type
4151Ch 4 (isp_dma_DMA_CH7_dev_Pack_left_crop_and_elem_B)—Offset 4151Ch” 00000000h
on page 1230
“reg_isp_dma_DMA_CH8_dev_Pack_left_crop_and_elem_B_type
41520h 4 (isp_dma_DMA_CH8_dev_Pack_left_crop_and_elem_B)—Offset 41520h” 00000000h
on page 1231
“reg_isp_dma_DMA_CH9_dev_Pack_left_crop_and_elem_B_type
41524h 4 (isp_dma_DMA_CH9_dev_Pack_left_crop_and_elem_B)—Offset 41524h” 00000000h
on page 1232
“reg_isp_dma_DMA_CH10_dev_Pack_left_crop_and_elem_B_type
41528h 4 (isp_dma_DMA_CH10_dev_Pack_left_crop_and_elem_B)—Offset 41528h” 00000000h
on page 1233
“reg_isp_dma_DMA_CH11_dev_Pack_left_crop_and_elem_B_type
4152Ch 4 (isp_dma_DMA_CH11_dev_Pack_left_crop_and_elem_B)—Offset 4152Ch” 00000000h
on page 1234
“reg_isp_dma_DMA_CH12_dev_Pack_left_crop_and_elem_B_type
41530h 4 (isp_dma_DMA_CH12_dev_Pack_left_crop_and_elem_B)—Offset 41530h” 00000000h
on page 1235
“reg_isp_dma_DMA_CH13_dev_Pack_left_crop_and_elem_B_type
41534h 4 (isp_dma_DMA_CH13_dev_Pack_left_crop_and_elem_B)—Offset 41534h” 00000000h
on page 1236
“reg_isp_dma_DMA_CH14_dev_Pack_left_crop_and_elem_B_type
41538h 4 (isp_dma_DMA_CH14_dev_Pack_left_crop_and_elem_B)—Offset 41538h” 00000000h
on page 1237
“reg_isp_dma_DMA_CH15_dev_Pack_left_crop_and_elem_B_type
4153Ch 4 (isp_dma_DMA_CH15_dev_Pack_left_crop_and_elem_B)—Offset 4153Ch” 00000000h
on page 1238
“reg_isp_dma_DMA_CH16_dev_Pack_left_crop_and_elem_B_type
41540h 4 (isp_dma_DMA_CH16_dev_Pack_left_crop_and_elem_B)—Offset 41540h” 00000000h
on page 1239
“reg_isp_dma_DMA_CH17_dev_Pack_left_crop_and_elem_B_type
41544h 4 (isp_dma_DMA_CH17_dev_Pack_left_crop_and_elem_B)—Offset 41544h” 00000000h
on page 1240
“reg_isp_dma_DMA_CH18_dev_Pack_left_crop_and_elem_B_type
41548h 4 (isp_dma_DMA_CH18_dev_Pack_left_crop_and_elem_B)—Offset 41548h” 00000000h
on page 1241
“reg_isp_dma_DMA_CH19_dev_Pack_left_crop_and_elem_B_type
4154Ch 4 (isp_dma_DMA_CH19_dev_Pack_left_crop_and_elem_B)—Offset 4154Ch” 00000000h
on page 1242
“reg_isp_dma_DMA_CH20_dev_Pack_left_crop_and_elem_B_type
41550h 4 (isp_dma_DMA_CH20_dev_Pack_left_crop_and_elem_B)—Offset 41550h” 00000000h
on page 1243
“reg_isp_dma_DMA_CH21_dev_Pack_left_crop_and_elem_B_type
41554h 4 (isp_dma_DMA_CH21_dev_Pack_left_crop_and_elem_B)—Offset 41554h” 00000000h
on page 1244
“reg_isp_dma_DMA_CH22_dev_Pack_left_crop_and_elem_B_type
41558h 4 (isp_dma_DMA_CH22_dev_Pack_left_crop_and_elem_B)—Offset 41558h” 00000000h
on page 1245
“reg_isp_dma_DMA_CH23_dev_Pack_left_crop_and_elem_B_type
4155Ch 4 (isp_dma_DMA_CH23_dev_Pack_left_crop_and_elem_B)—Offset 4155Ch” 00000000h
on page 1246
“reg_isp_dma_DMA_CH24_dev_Pack_left_crop_and_elem_B_type
41560h 4 (isp_dma_DMA_CH24_dev_Pack_left_crop_and_elem_B)—Offset 41560h” 00000000h
on page 1247

Intel® Atom™ Processor E3800 Product Family

Datasheet 929
 MIPI-Camera Serial Interface (CSI) & ISP

Table 167. Summary of Image Signal Processor Memory Mapped I/O Registers—
ISPMMADR (Continued)
Offset Size Register ID—Description Default Value

“reg_isp_dma_DMA_CH25_dev_Pack_left_crop_and_elem_B_type
41564h 4 (isp_dma_DMA_CH25_dev_Pack_left_crop_and_elem_B)—Offset 41564h” 00000000h
on page 1248
“reg_isp_dma_DMA_CH26_dev_Pack_left_crop_and_elem_B_type
41568h 4 (isp_dma_DMA_CH26_dev_Pack_left_crop_and_elem_B)—Offset 41568h” 00000000h
on page 1249
“reg_isp_dma_DMA_CH27_dev_Pack_left_crop_and_elem_B_type
4156Ch 4 (isp_dma_DMA_CH27_dev_Pack_left_crop_and_elem_B)—Offset 4156Ch” 00000000h
on page 1250
“reg_isp_dma_DMA_CH28_dev_Pack_left_crop_and_elem_B_type
41570h 4 (isp_dma_DMA_CH28_dev_Pack_left_crop_and_elem_B)—Offset 41570h” 00000000h
on page 1251
“reg_isp_dma_DMA_CH29_dev_Pack_left_crop_and_elem_B_type
41574h 4 (isp_dma_DMA_CH29_dev_Pack_left_crop_and_elem_B)—Offset 41574h” 00000000h
on page 1252
“reg_isp_dma_DMA_CH30_dev_Pack_left_crop_and_elem_B_type
41578h 4 (isp_dma_DMA_CH30_dev_Pack_left_crop_and_elem_B)—Offset 41578h” 00000000h
on page 1253
“reg_isp_dma_DMA_CH31_dev_Pack_left_crop_and_elem_B_type
4157Ch 4 (isp_dma_DMA_CH31_dev_Pack_left_crop_and_elem_B)—Offset 4157Ch” 00000000h
on page 1254
“reg_isp_dma_DMA_CH0_Device_Xb_B_type
41600h 4 00000000h
(isp_dma_DMA_CH0_Device_Xb_B)—Offset 41600h” on page 1255

“reg_isp_dma_DMA_CH1_Device_Xb_B_type
41604h 4 00000000h
(isp_dma_DMA_CH1_Device_Xb_B)—Offset 41604h” on page 1256
“reg_isp_dma_DMA_CH2_Device_Xb_B_type
41608h 4 00000000h
(isp_dma_DMA_CH2_Device_Xb_B)—Offset 41608h” on page 1257
“reg_isp_dma_DMA_CH3_Device_Xb_B_type
4160Ch 4 00000000h
(isp_dma_DMA_CH3_Device_Xb_B)—Offset 4160Ch” on page 1257

“reg_isp_dma_DMA_CH4_Device_Xb_B_type
41610h 4 00000000h
(isp_dma_DMA_CH4_Device_Xb_B)—Offset 41610h” on page 1258
“reg_isp_dma_DMA_CH5_Device_Xb_B_type
41614h 4 00000000h
(isp_dma_DMA_CH5_Device_Xb_B)—Offset 41614h” on page 1259
“reg_isp_dma_DMA_CH6_Device_Xb_B_type
41618h 4 00000000h
(isp_dma_DMA_CH6_Device_Xb_B)—Offset 41618h” on page 1259
“reg_isp_dma_DMA_CH7_Device_Xb_B_type
4161Ch 4 00000000h
(isp_dma_DMA_CH7_Device_Xb_B)—Offset 4161Ch” on page 1260

“reg_isp_dma_DMA_CH8_Device_Xb_B_type
41620h 4 00000000h
(isp_dma_DMA_CH8_Device_Xb_B)—Offset 41620h” on page 1261
“reg_isp_dma_DMA_CH9_Device_Xb_B_type
41624h 4 00000000h
(isp_dma_DMA_CH9_Device_Xb_B)—Offset 41624h” on page 1261
“reg_isp_dma_DMA_CH10_Device_Xb_B_type
41628h 4 00000000h
(isp_dma_DMA_CH10_Device_Xb_B)—Offset 41628h” on page 1262

“reg_isp_dma_DMA_CH11_Device_Xb_B_type
4162Ch 4 00000000h
(isp_dma_DMA_CH11_Device_Xb_B)—Offset 4162Ch” on page 1263
“reg_isp_dma_DMA_CH12_Device_Xb_B_type
41630h 4 00000000h
(isp_dma_DMA_CH12_Device_Xb_B)—Offset 41630h” on page 1263
“reg_isp_dma_DMA_CH13_Device_Xb_B_type
41634h 4 00000000h
(isp_dma_DMA_CH13_Device_Xb_B)—Offset 41634h” on page 1264

“reg_isp_dma_DMA_CH14_Device_Xb_B_type
41638h 4 00000000h
(isp_dma_DMA_CH14_Device_Xb_B)—Offset 41638h” on page 1265

Intel® Atom™ Processor E3800 Product Family

930 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

Table 167. Summary of Image Signal Processor Memory Mapped I/O Registers—
ISPMMADR (Continued)
Offset Size Register ID—Description Default Value

“reg_isp_dma_DMA_CH15_Device_Xb_B_type
4163Ch 4 00000000h
(isp_dma_DMA_CH15_Device_Xb_B)—Offset 4163Ch” on page 1265

“reg_isp_dma_DMA_CH16_Device_Xb_B_type
41640h 4 00000000h
(isp_dma_DMA_CH16_Device_Xb_B)—Offset 41640h” on page 1266
“reg_isp_dma_DMA_CH17_Device_Xb_B_type
41644h 4 00000000h
(isp_dma_DMA_CH17_Device_Xb_B)—Offset 41644h” on page 1267
“reg_isp_dma_DMA_CH18_Device_Xb_B_type
41648h 4 00000000h
(isp_dma_DMA_CH18_Device_Xb_B)—Offset 41648h” on page 1267

“reg_isp_dma_DMA_CH19_Device_Xb_B_type
4164Ch 4 00000000h
(isp_dma_DMA_CH19_Device_Xb_B)—Offset 4164Ch” on page 1268
“reg_isp_dma_DMA_CH20_Device_Xb_B_type
41650h 4 00000000h
(isp_dma_DMA_CH20_Device_Xb_B)—Offset 41650h” on page 1269
“reg_isp_dma_DMA_CH21_Device_Xb_B_type
41654h 4 00000000h
(isp_dma_DMA_CH21_Device_Xb_B)—Offset 41654h” on page 1269

“reg_isp_dma_DMA_CH22_Device_Xb_B_type
41658h 4 00000000h
(isp_dma_DMA_CH22_Device_Xb_B)—Offset 41658h” on page 1270
“reg_isp_dma_DMA_CH23_Device_Xb_B_type
4165Ch 4 00000000h
(isp_dma_DMA_CH23_Device_Xb_B)—Offset 4165Ch” on page 1271
“reg_isp_dma_DMA_CH24_Device_Xb_B_type
41660h 4 00000000h
(isp_dma_DMA_CH24_Device_Xb_B)—Offset 41660h” on page 1271

“reg_isp_dma_DMA_CH25_Device_Xb_B_type
41664h 4 00000000h
(isp_dma_DMA_CH25_Device_Xb_B)—Offset 41664h” on page 1272
“reg_isp_dma_DMA_CH26_Device_Xb_B_type
41668h 4 00000000h
(isp_dma_DMA_CH26_Device_Xb_B)—Offset 41668h” on page 1273
“reg_isp_dma_DMA_CH27_Device_Xb_B_type
4166Ch 4 00000000h
(isp_dma_DMA_CH27_Device_Xb_B)—Offset 4166Ch” on page 1273

“reg_isp_dma_DMA_CH28_Device_Xb_B_type
41670h 4 00000000h
(isp_dma_DMA_CH28_Device_Xb_B)—Offset 41670h” on page 1274
“reg_isp_dma_DMA_CH29_Device_Xb_B_type
41674h 4 00000000h
(isp_dma_DMA_CH29_Device_Xb_B)—Offset 41674h” on page 1275
“reg_isp_dma_DMA_CH31_Device_Xb_B_type
41678h 4 00000000h
(isp_dma_DMA_CH31_Device_Xb_B)—Offset 41678h” on page 1275
“reg_isp_dma_DMA_CH0_Yb_type (isp_dma_DMA_CH0_Yb)—Offset
41700h 4 00000000h
41700h” on page 1276

“reg_isp_dma_DMA_CH1_Yb_type (isp_dma_DMA_CH1_Yb)—Offset
41704h 4 00000000h
41704h” on page 1277
“reg_isp_dma_DMA_CH2_Yb_type (isp_dma_DMA_CH2_Yb)—Offset
41708h 4 00000000h
41708h” on page 1277
“reg_isp_dma_DMA_CH3_Yb_type (isp_dma_DMA_CH3_Yb)—Offset
4170Ch 4 00000000h
4170Ch” on page 1278

“reg_isp_dma_DMA_CH4_Yb_type (isp_dma_DMA_CH4_Yb)—Offset
41710h 4 00000000h
41710h” on page 1278
“reg_isp_dma_DMA_CH5_Yb_type (isp_dma_DMA_CH5_Yb)—Offset
41714h 4 00000000h
41714h” on page 1279
“reg_isp_dma_DMA_CH6_Yb_type (isp_dma_DMA_CH6_Yb)—Offset
41718h 4 00000000h
41718h” on page 1279

“reg_isp_dma_DMA_CH7_Yb_type (isp_dma_DMA_CH7_Yb)—Offset
4171Ch 4 00000000h
4171Ch” on page 1280

Intel® Atom™ Processor E3800 Product Family

Datasheet 931
 MIPI-Camera Serial Interface (CSI) & ISP

Table 167. Summary of Image Signal Processor Memory Mapped I/O Registers—
ISPMMADR (Continued)
Offset Size Register ID—Description Default Value

“reg_isp_dma_DMA_CH8_Yb_type (isp_dma_DMA_CH8_Yb)—Offset
41720h 4 00000000h
41720h” on page 1281

“reg_isp_dma_DMA_CH9_Yb_type (isp_dma_DMA_CH9_Yb)—Offset
41724h 4 00000000h
41724h” on page 1281
“reg_isp_dma_DMA_CH10_Yb_type (isp_dma_DMA_CH10_Yb)—Offset
41728h 4 00000000h
41728h” on page 1282
“reg_isp_dma_DMA_CH11_Yb_type (isp_dma_DMA_CH11_Yb)—Offset
4172Ch 4 00000000h
4172Ch” on page 1282

“reg_isp_dma_DMA_CH12_Yb_type (isp_dma_DMA_CH12_Yb)—Offset
41730h 4 00000000h
41730h” on page 1283
“reg_isp_dma_DMA_CH13_Yb_type (isp_dma_DMA_CH13_Yb)—Offset
41734h 4 00000000h
41734h” on page 1283
“reg_isp_dma_DMA_CH14_Yb_type (isp_dma_DMA_CH14_Yb)—Offset
41738h 4 00000000h
41738h” on page 1284

“reg_isp_dma_DMA_CH15_Yb_type (isp_dma_DMA_CH15_Yb)—Offset
4173Ch 4 00000000h
4173Ch” on page 1285
“reg_isp_dma_DMA_CH16_Yb_type (isp_dma_DMA_CH16_Yb)—Offset
41740h 4 00000000h
41740h” on page 1285
“reg_isp_dma_DMA_CH17_Yb_type (isp_dma_DMA_CH17_Yb)—Offset
41744h 4 00000000h
41744h” on page 1286

“reg_isp_dma_DMA_CH18_Yb_type (isp_dma_DMA_CH18_Yb)—Offset
41748h 4 00000000h
41748h” on page 1286
“reg_isp_dma_DMA_CH19_Yb_type (isp_dma_DMA_CH19_Yb)—Offset
4174Ch 4 00000000h
4174Ch” on page 1287
“reg_isp_dma_DMA_CH20_Yb_type (isp_dma_DMA_CH20_Yb)—Offset
41750h 4 00000000h
41750h” on page 1287

“reg_isp_dma_DMA_CH21_Yb_type (isp_dma_DMA_CH21_Yb)—Offset
41754h 4 00000000h
41754h” on page 1288
“reg_isp_dma_DMA_CH22_Yb_type (isp_dma_DMA_CH22_Yb)—Offset
41758h 4 00000000h
41758h” on page 1289
“reg_isp_dma_DMA_CH23_Yb_type (isp_dma_DMA_CH23_Yb)—Offset
4175Ch 4 00000000h
4175Ch” on page 1289
“reg_isp_dma_DMA_CH24_Yb_type (isp_dma_DMA_CH24_Yb)—Offset
41760h 4 00000000h
41760h” on page 1290

“reg_isp_dma_DMA_CH25_Yb_type (isp_dma_DMA_CH25_Yb)—Offset
41764h 4 00000000h
41764h” on page 1290
“reg_isp_dma_DMA_CH26_Yb_type (isp_dma_DMA_CH26_Yb)—Offset
41768h 4 00000000h
41768h” on page 1291
“reg_isp_dma_DMA_CH27_Yb_type (isp_dma_DMA_CH27_Yb)—Offset
4176Ch 4 00000000h
4176Ch” on page 1291

“reg_isp_dma_DMA_CH28_Yb_type (isp_dma_DMA_CH28_Yb)—Offset
41770h 4 00000000h
41770h” on page 1292
“reg_isp_dma_DMA_CH29_Yb_type (isp_dma_DMA_CH29_Yb)—Offset
41774h 4 00000000h
41774h” on page 1293
“reg_isp_dma_DMA_CH31_Yb_type (isp_dma_DMA_CH31_Yb)—Offset
4177Ch 4 00000000h
4177Ch” on page 1293

“reg_isp_dma_DMA_CH0_pending_command_type
41800h 4 00000000h
(isp_dma_DMA_CH0_pending_command)—Offset 41800h” on page 1294

Intel® Atom™ Processor E3800 Product Family

932 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

Table 167. Summary of Image Signal Processor Memory Mapped I/O Registers—
ISPMMADR (Continued)
Offset Size Register ID—Description Default Value

“reg_isp_dma_DMA_CH1_pending_command_type
41804h 4 00000000h
(isp_dma_DMA_CH1_pending_command)—Offset 41804h” on page 1294

“reg_isp_dma_DMA_CH2_pending_command_type
41808h 4 00000000h
(isp_dma_DMA_CH2_pending_command)—Offset 41808h” on page 1295
“reg_isp_dma_DMA_CH3_pending_command_type
4180Ch 4 00000000h
(isp_dma_DMA_CH3_pending_command)—Offset 4180Ch” on page 1296
“reg_isp_dma_DMA_CH4_pending_command_type
41810h 4 00000000h
(isp_dma_DMA_CH4_pending_command)—Offset 41810h” on page 1296

“reg_isp_dma_DMA_CH5_pending_command_type
41814h 4 00000000h
(isp_dma_DMA_CH5_pending_command)—Offset 41814h” on page 1297
“reg_isp_dma_DMA_CH6_pending_command_type
41818h 4 00000000h
(isp_dma_DMA_CH6_pending_command)—Offset 41818h” on page 1298
“reg_isp_dma_DMA_CH7_pending_command_type
4181Ch 4 00000000h
(isp_dma_DMA_CH7_pending_command)—Offset 4181Ch” on page 1298

“reg_isp_dma_DMA_CH8_pending_command_type
41820h 4 00000000h
(isp_dma_DMA_CH8_pending_command)—Offset 41820h” on page 1299
“reg_isp_dma_DMA_CH9_pending_command_type
41824h 4 00000000h
(isp_dma_DMA_CH9_pending_command)—Offset 41824h” on page 1300
“reg_isp_dma_DMA_CH10_pending_command_type
41828h 4 00000000h
(isp_dma_DMA_CH10_pending_command)—Offset 41828h” on page 1300

“reg_isp_dma_DMA_CH11_pending_command_type
4182Ch 4 00000000h
(isp_dma_DMA_CH11_pending_command)—Offset 4182Ch” on page 1301
“reg_isp_dma_DMA_CH12_pending_command_type
41830h 4 00000000h
(isp_dma_DMA_CH12_pending_command)—Offset 41830h” on page 1302
“reg_isp_dma_DMA_CH13_pending_command_type
41834h 4 00000000h
(isp_dma_DMA_CH13_pending_command)—Offset 41834h” on page 1302

“reg_isp_dma_DMA_CH14_pending_command_type
41838h 4 00000000h
(isp_dma_DMA_CH14_pending_command)—Offset 41838h” on page 1303
“reg_isp_dma_DMA_CH15_pending_command_type
4183Ch 4 00000000h
(isp_dma_DMA_CH15_pending_command)—Offset 4183Ch” on page 1304
“reg_isp_dma_DMA_CH16_pending_command_type
41840h 4 00000000h
(isp_dma_DMA_CH16_pending_command)—Offset 41840h” on page 1304
“reg_isp_dma_DMA_CH17_pending_command_type
41844h 4 00000000h
(isp_dma_DMA_CH17_pending_command)—Offset 41844h” on page 1305

“reg_isp_dma_DMA_CH18_pending_command_type
41848h 4 00000000h
(isp_dma_DMA_CH18_pending_command)—Offset 41848h” on page 1306
“reg_isp_dma_DMA_CH19_pending_command_type
4184Ch 4 00000000h
(isp_dma_DMA_CH19_pending_command)—Offset 4184Ch” on page 1306
“reg_isp_dma_DMA_CH20_pending_command_type
41850h 4 00000000h
(isp_dma_DMA_CH20_pending_command)—Offset 41850h” on page 1307

“reg_isp_dma_DMA_CH21_pending_command_type
41854h 4 00000000h
(isp_dma_DMA_CH21_pending_command)—Offset 41854h” on page 1308
“reg_isp_dma_DMA_CH22_pending_command_type
41858h 4 00000000h
(isp_dma_DMA_CH22_pending_command)—Offset 41858h” on page 1308
“reg_isp_dma_DMA_CH23_pending_command_type
4185Ch 4 00000000h
(isp_dma_DMA_CH23_pending_command)—Offset 4185Ch” on page 1309

“reg_isp_dma_DMA_CH24_pending_command_type
41860h 4 00000000h
(isp_dma_DMA_CH24_pending_command)—Offset 41860h” on page 1310

Intel® Atom™ Processor E3800 Product Family

Datasheet 933
 MIPI-Camera Serial Interface (CSI) & ISP

Table 167. Summary of Image Signal Processor Memory Mapped I/O Registers—
ISPMMADR (Continued)
Offset Size Register ID—Description Default Value

“reg_isp_dma_DMA_CH25_pending_command_type
41864h 4 00000000h
(isp_dma_DMA_CH25_pending_command)—Offset 41864h” on page 1310

“reg_isp_dma_DMA_CH26_pending_command_type
41868h 4 00000000h
(isp_dma_DMA_CH26_pending_command)—Offset 41868h” on page 1311
“reg_isp_dma_DMA_CH27_pending_command_type
4186Ch 4 00000000h
(isp_dma_DMA_CH27_pending_command)—Offset 4186Ch” on page 1312
“reg_isp_dma_DMA_CH28_pending_command_type
41870h 4 00000000h
(isp_dma_DMA_CH28_pending_command)—Offset 41870h” on page 1312

“reg_isp_dma_DMA_CH29_pending_command_type
41874h 4 00000000h
(isp_dma_DMA_CH29_pending_command)—Offset 41874h” on page 1313
“reg_isp_dma_DMA_CH30_pending_command_type
41878h 4 00000000h
(isp_dma_DMA_CH30_pending_command)—Offset 41878h” on page 1314
“reg_isp_dma_DMA_CH31_pending_command_type
4187Ch 4 00000000h
(isp_dma_DMA_CH31_pending_command)—Offset 4187Ch” on page 1314

“reg_isp_dma_DMA_command_token_type
42000h 4 00000000h
(isp_dma_DMA_command_token)—Offset 42000h” on page 1315
“reg_isp_dma_DMA_command_src_addr_type
42004h 4 00000000h
(isp_dma_DMA_command_src_addr)—Offset 42004h” on page 1316
“reg_isp_dma_DMA_command_dst_addr_type
42008h 4 00000000h
(isp_dma_DMA_command_dst_addr)—Offset 42008h” on page 1316

“reg_isp_dma_DMA_command_ctrl_id_type
4200Ch 4 00000000h
(isp_dma_DMA_command_ctrl_id)—Offset 4200Ch” on page 1317
“reg_isp_dma_DMA_FSM_Ctrl_status_type
42010h 4 00000001h
(isp_dma_DMA_FSM_Ctrl_status)—Offset 42010h” on page 1317
“reg_isp_dma_DMA_FSM_Pack_status_type
42014h 4 00000001h
(isp_dma_DMA_FSM_Pack_status)—Offset 42014h” on page 1318

“reg_isp_dma_DMA_FSM_request_status_type
42018h 4 00000000h
(isp_dma_DMA_FSM_request_status)—Offset 42018h” on page 1319
“reg_isp_dma_DMA_FSM_write_status_type
4201Ch 4 00000000h
(isp_dma_DMA_FSM_write_status)—Offset 4201Ch” on page 1320
“reg_isp_dma_DMA_FSM_Ctrl_dev_idx_type
42110h 4 00000000h
(isp_dma_DMA_FSM_Ctrl_dev_idx)—Offset 42110h” on page 1320
“reg_isp_dma_DMA_FSM_Pack_cnt_Yb_type
42114h 4 00000000h
(isp_dma_DMA_FSM_Pack_cnt_Yb)—Offset 42114h” on page 1321

“reg_isp_dma_DMA_FSM_Request_cnt_Yb_type
42118h 4 00000000h
(isp_dma_DMA_FSM_Request_cnt_Yb)—Offset 42118h” on page 1322
“reg_isp_dma_DMA_FSM_Write_cnt_Y_type
4211Ch 4 00000000h
(isp_dma_DMA_FSM_Write_cnt_Y)—Offset 4211Ch” on page 1322
“reg_isp_dma_DMA_FSM_Ctrl_req_addr_type
42210h 4 00000000h
(isp_dma_DMA_FSM_Ctrl_req_addr)—Offset 42210h” on page 1323

“reg_isp_dma_DMA_FSM_Pack_req_cnt_Xb_type
42214h 4 00000000h
(isp_dma_DMA_FSM_Pack_req_cnt_Xb)—Offset 42214h” on page 1323
“reg_isp_dma_DMA_FSM_Request_cnt_Xb_type
42218h 4 00000000h
(isp_dma_DMA_FSM_Request_cnt_Xb)—Offset 42218h” on page 1324
“reg_isp_dma_DMA_FSM_Write_cnt_Xb_type
4221Ch 4 00000000h
(isp_dma_DMA_FSM_Write_cnt_Xb)—Offset 4221Ch” on page 1325

“reg_isp_dma_DMA_FSM_Ctrl_req_stride_type
42310h 4 00000000h
(isp_dma_DMA_FSM_Ctrl_req_stride)—Offset 42310h” on page 1326

Intel® Atom™ Processor E3800 Product Family

934 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

Table 167. Summary of Image Signal Processor Memory Mapped I/O Registers—
ISPMMADR (Continued)
Offset Size Register ID—Description Default Value

“reg_isp_dma_DMA_FSM_Pack_wr_cnt_Xb_type
42314h 4 00000000h
(isp_dma_DMA_FSM_Pack_wr_cnt_Xb)—Offset 42314h” on page 1326

“reg_isp_dma_DMA_FSM_Req_remining_Xb_type
42318h 4 00000000h
(isp_dma_DMA_FSM_Req_remining_Xb)—Offset 42318h” on page 1327
“reg_isp_dma_DMA_FSM_Wr_remining_Xb_type
4231Ch 4 00000000h
(isp_dma_DMA_FSM_Wr_remining_Xb)—Offset 4231Ch” on page 1328
“reg_isp_dma_DMA_FSM_Ctrl_req_Xb_type
42410h 4 00000000h
(isp_dma_DMA_FSM_Ctrl_req_Xb)—Offset 42410h” on page 1328

“reg_isp_dma_DMA_FSM_Req_burst_cnt_type
42418h 4 0000FFFFh
(isp_dma_DMA_FSM_Req_burst_cnt)—Offset 42418h” on page 1329
“reg_isp_dma_DMA_FSM_Wr_burst_cnt_type
4241Ch 4 0000FFFFh
(isp_dma_DMA_FSM_Wr_burst_cnt)—Offset 4241Ch” on page 1330
“reg_isp_dma_DMA_FSM_Ctrl_req_Yb_type
42510h 4 00000000h
(isp_dma_DMA_FSM_Ctrl_req_Yb)—Offset 42510h” on page 1330

“reg_isp_dma_DMA_FSM_Ctrl_Pack_req_dev_idx_type
42610h 4 (isp_dma_DMA_FSM_Ctrl_Pack_req_dev_idx)—Offset 42610h” on 00000000h
page 1331

“reg_isp_dma_DMA_FSM_Ctrl_Pack_wr_dev_idx_type
42710h 4 (isp_dma_DMA_FSM_Ctrl_Pack_wr_dev_idx)—Offset 42710h” on 00000000h
page 1332

“reg_isp_dma_DMA_FSM_Ctrl_Wr_addr_type
42810h 4 00000000h
(isp_dma_DMA_FSM_Ctrl_Wr_addr)—Offset 42810h” on page 1332
“reg_isp_dma_DMA_FSM_Ctrl_Wr_stride_type
42910h 4 00000000h
(isp_dma_DMA_FSM_Ctrl_Wr_stride)—Offset 42910h” on page 1333
“reg_isp_dma_DMA_FSM_Ctrl_pack_req_Xb_type
42A10h 4 00000000h
(isp_dma_DMA_FSM_Ctrl_pack_req_Xb)—Offset 42A10h” on page 1333

“reg_isp_dma_DMA_FSM_Ctrl_pack_Yb_type
42B10h 4 00000000h
(isp_dma_DMA_FSM_Ctrl_pack_Yb)—Offset 42B10h” on page 1334
“reg_isp_dma_DMA_FSM_Ctrl_pack_wr_Xb_type
42C10h 4 00000000h
(isp_dma_DMA_FSM_Ctrl_pack_wr_Xb)—Offset 42C10h” on page 1335
“reg_isp_dma_DMA_FSM_Ctrl_pack_req_elem_type
42D10h 4 00000000h
(isp_dma_DMA_FSM_Ctrl_pack_req_elem)—Offset 42D10h” on page 1335
“reg_isp_dma_DMA_FSM_Ctrl_pack_wr_elem_type
42E10h 4 00000000h
(isp_dma_DMA_FSM_Ctrl_pack_wr_elem)—Offset 42E10h” on page 1336

“reg_isp_dma_DMA_FSM_Ctrl_pack_sz_ext_ctrl_id_type
42F10h 4 (isp_dma_DMA_FSM_Ctrl_pack_sz_ext_ctrl_id)—Offset 42F10h” on 00000000h
page 1337

“reg_isp_dma_Dev_Interf_0_req_side_type
43000h 4 00000000h
(isp_dma_Dev_Interf_0_req_side)—Offset 43000h” on page 1338
“reg_isp_dma_Dev_Interf_1_req_side_type
43004h 4 00000006h
(isp_dma_Dev_Interf_1_req_side)—Offset 43004h” on page 1338
“reg_isp_dma_Dev_Interf_2_req_side_type
43008h 4 00000006h
(isp_dma_Dev_Interf_2_req_side)—Offset 43008h” on page 1339

“reg_isp_dma_Dev_Interf_0_snd_side_type
43100h 4 00000004h
(isp_dma_Dev_Interf_0_snd_side)—Offset 43100h” on page 1340
“reg_isp_dma_Dev_Interf_1_snd_side_type
43104h 4 00000006h
(isp_dma_Dev_Interf_1_snd_side)—Offset 43104h” on page 1341
“reg_isp_dma_Dev_Interf_2_snd_side_type
43108h 4 00000006h
(isp_dma_Dev_Interf_2_snd_side)—Offset 43108h” on page 1341

Intel® Atom™ Processor E3800 Product Family

Datasheet 935
 MIPI-Camera Serial Interface (CSI) & ISP

Table 167. Summary of Image Signal Processor Memory Mapped I/O Registers—
ISPMMADR (Continued)
Offset Size Register ID—Description Default Value

“reg_isp_dma_Dev_Interf_0_Fifo_status_type
43200h 4 00000004h
(isp_dma_Dev_Interf_0_Fifo_status)—Offset 43200h” on page 1342

“reg_isp_dma_Dev_Interf_1_Fifo_status_type
43204h 4 00000004h
(isp_dma_Dev_Interf_1_Fifo_status)—Offset 43204h” on page 1343
“reg_isp_dma_Dev_Interf_2_Fifo_status_type
43208h 4 00000004h
(isp_dma_Dev_Interf_2_Fifo_status)—Offset 43208h” on page 1344
“reg_isp_dma_Dev_Interf_0_Req_complete_bust_type
43300h 4 (isp_dma_Dev_Interf_0_Req_complete_bust)—Offset 43300h” on 00000000h
page 1345
“reg_isp_dma_Dev_Interf_1_Req_complete_bust_type
43304h 4 (isp_dma_Dev_Interf_1_Req_complete_bust)—Offset 43304h” on 00000000h
page 1346
“reg_isp_dma_Dev_Interf_2_Req_complete_bust_type
43308h 4 (isp_dma_Dev_Interf_2_Req_complete_bust)—Offset 43308h” on 00000000h
page 1347
“reg_isp_dma_Dev_Interf_2_Max_burst_Size_type
43408h 4 0000007Fh
(isp_dma_Dev_Interf_2_Max_burst_Size)—Offset 43408h” on page 1347

50000h 4 “reg_gdc1_reg0_type (gdc1_reg0)—Offset 50000h” on page 1348 00000000h

50004h 4 “reg_gdc1_woi_x_type (gdc1_woi_x)—Offset 50004h” on page 1349 00000000h
50008h 4 “reg_gdc1_woi_y_type (gdc1_woi_y)—Offset 50008h” on page 1349 00000000h

5000Ch 4 “reg_gdc1_bpp_type (gdc1_bpp)—Offset 5000Ch” on page 1350 00000000h

“reg_gdc1_fryipxfrx_start_type (gdc1_fryipxfrx_start)—Offset 50010h” on
50010h 4 00000000h
page 1350

50014h 4 “reg_gdc1_oxdim_type (gdc1_oxdim)—Offset 50014h” on page 1351 00000000h

50018h 4 “reg_gdc1_oydim_type (gdc1_oydim)—Offset 50018h” on page 1351 00000000h
5001Ch 4 “reg_gdc1_src_addr_type (gdc1_src_addr)—Offset 5001Ch” on page 1352 00000000h

50020h 4 “reg_gdc1_src_end_type (gdc1_src_end)—Offset 50020h” on page 1352 00000000h

“reg_gdc1_src_wrap_type (gdc1_src_wrap)—Offset 50024h” on
50024h 4 00000000h
page 1353

“reg_gdc1_src_stride_type (gdc1_src_stride)—Offset 50028h” on

50028h 4 00000000h
page 1353

“reg_gdc1_dst_addr_type (gdc1_dst_addr)—Offset 5002Ch” on

5002Ch 4 00000000h
page 1354
“reg_gdc1_dst_stride_type (gdc1_dst_stride)—Offset 50030h” on
50030h 4 00000000h
page 1354
50034h 4 “reg_gdc1_dx_type (gdc1_dx)—Offset 50034h” on page 1355 00000000h
50038h 4 “reg_gdc1_dy_type (gdc1_dy)—Offset 50038h” on page 1355 00000000h

“reg_gdc1_P0_primX_ixdim_type (gdc1_P0_primX_ixdim)—Offset
5003Ch 4 00000000h
5003Ch” on page 1356
“reg_gdc1_P0_primY_iydim_type (gdc1_P0_primY_iydim)—Offset
50040h 4 00000000h
50040h” on page 1356
“reg_gdc1_P1_primX_type (gdc1_P1_primX)—Offset 50044h” on
50044h 4 00000000h
page 1357

“reg_gdc1_P1_primY_type (gdc1_P1_primY)—Offset 50048h” on

50048h 4 00000000h
page 1357
“reg_gdc1_P2_primX_type (gdc1_P2_primX)—Offset 5004Ch” on
5004Ch 4 00000000h
page 1358

Intel® Atom™ Processor E3800 Product Family

936 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

Table 167. Summary of Image Signal Processor Memory Mapped I/O Registers—
ISPMMADR (Continued)
Offset Size Register ID—Description Default Value

“reg_gdc1_P2_primY_type (gdc1_P2_primY)—Offset 50050h” on

50050h 4 00000000h
page 1358

“reg_gdc1_P3_primX_type (gdc1_P3_primX)—Offset 50054h” on

50054h 4 00000000h
page 1359
“reg_gdc1_P3_primY_type (gdc1_P3_primY)—Offset 50058h” on
50058h 4 00000000h
page 1359
“reg_gdc1_perf_mode_type (gdc1_perf_mode)—Offset 5005Ch” on
5005Ch 4 00000000h
page 1360

“reg_gdc1_interp_type_type (gdc1_interp_type)—Offset 50060h” on

50060h 4 00000000h
page 1361
“reg_gdc1_scan_mode_type (gdc1_scan_mode)—Offset 50064h” on
50064h 4 00000000h
page 1361
“reg_gdc1_proc_mode_type (gdc1_proc_mode)—Offset 50068h” on
50068h 4 00000000h
page 1362

60000h 4 “reg_gdc2_reg0_type (gdc2_reg0)—Offset 60000h” on page 1362 00000000h

60004h 4 “reg_gdc2_woi_x_type (gdc2_woi_x)—Offset 60004h” on page 1363 00000000h
60008h 4 “reg_gdc2_woi_y_type (gdc2_woi_y)—Offset 60008h” on page 1363 00000000h

6000Ch 4 “reg_gdc2_bpp_type (gdc2_bpp)—Offset 6000Ch” on page 1364 00000000h

“reg_gdc2_fryipxfrx_start_type (gdc2_fryipxfrx_start)—Offset 60010h” on
60010h 4 00000000h
page 1364

60014h 4 “reg_gdc2_oxdim_type (gdc2_oxdim)—Offset 60014h” on page 1365 00000000h

60018h 4 “reg_gdc2_oydim_type (gdc2_oydim)—Offset 60018h” on page 1365 00000000h
6001Ch 4 “reg_gdc2_src_addr_type (gdc2_src_addr)—Offset 6001Ch” on page 1366 00000000h

60020h 4 “reg_gdc2_src_end_type (gdc2_src_end)—Offset 60020h” on page 1366 00000000h

“reg_gdc2_src_wrap_type (gdc2_src_wrap)—Offset 60024h” on
60024h 4 00000000h
page 1367

“reg_gdc2_src_stride_type (gdc2_src_stride)—Offset 60028h” on

60028h 4 00000000h
page 1367

“reg_gdc2_dst_addr_type (gdc2_dst_addr)—Offset 6002Ch” on

6002Ch 4 00000000h
page 1368
“reg_gdc2_dst_stride_type (gdc2_dst_stride)—Offset 60030h” on
60030h 4 00000000h
page 1368
60034h 4 “reg_gdc2_dx_type (gdc2_dx)—Offset 60034h” on page 1369 00000000h
60038h 4 “reg_gdc2_dy_type (gdc2_dy)—Offset 60038h” on page 1369 00000000h

“reg_gdc2_P0_primX_ixdim_type (gdc2_P0_primX_ixdim)—Offset
6003Ch 4 00000000h
6003Ch” on page 1370
“reg_gdc2_P0_primY_iydim_type (gdc2_P0_primY_iydim)—Offset
60040h 4 00000000h
60040h” on page 1370
“reg_gdc2_P1_primX_type (gdc2_P1_primX)—Offset 60044h” on
60044h 4 00000000h
page 1371

“reg_gdc2_P1_primY_type (gdc2_P1_primY)—Offset 60048h” on

60048h 4 00000000h
page 1371
“reg_gdc2_P2_primX_type (gdc2_P2_primX)—Offset 6004Ch” on
6004Ch 4 00000000h
page 1372
“reg_gdc2_P2_primY_type (gdc2_P2_primY)—Offset 60050h” on
60050h 4 00000000h
page 1372

Intel® Atom™ Processor E3800 Product Family

Datasheet 937
 MIPI-Camera Serial Interface (CSI) & ISP

Table 167. Summary of Image Signal Processor Memory Mapped I/O Registers—
ISPMMADR (Continued)
Offset Size Register ID—Description Default Value

“reg_gdc2_P3_primX_type (gdc2_P3_primX)—Offset 60054h” on

60054h 4 00000000h
page 1373

“reg_gdc2_P3_primY_type (gdc2_P3_primY)—Offset 60058h” on

60058h 4 00000000h
page 1373
“reg_gdc2_perf_mode_type (gdc2_perf_mode)—Offset 6005Ch” on
6005Ch 4 00000000h
page 1374
“reg_gdc2_interp_type_type (gdc2_interp_type)—Offset 60060h” on
60060h 4 00000000h
page 1375

“reg_gdc2_scan_mode_type (gdc2_scan_mode)—Offset 60064h” on

60064h 4 00000000h
page 1375
“reg_gdc2_proc_mode_type (gdc2_proc_mode)—Offset 60068h” on
60068h 4 00000000h
page 1376
“reg_data_out_sys_c_mmu_MMU_invalidate_cache_type
70000h 4 (data_out_sys_c_mmu_MMU_invalidate_cache)—Offset 70000h” on 00000000h
page 1376
“reg_data_out_sys_c_mmu_MMU_page_table_base_type
70004h 4 (data_out_sys_c_mmu_MMU_page_table_base)—Offset 70004h” on 00000000h
page 1377
“reg_inp_sys_csi_receiver_csi1_dev_ready_type
80100h 4 00000000h
(inp_sys_csi_receiver_csi1_dev_ready)—Offset 80100h” on page 1377

“reg_inp_sys_csi_receiver_csi1_int_status_type
80104h 4 00000000h
(inp_sys_csi_receiver_csi1_int_status)—Offset 80104h” on page 1378
“reg_inp_sys_csi_receiver_csi1_int_enable_type
80108h 4 00000000h
(inp_sys_csi_receiver_csi1_int_enable)—Offset 80108h” on page 1380
“reg_inp_sys_csi_receiver_csi1_func_prg_type
8010Ch 4 0007FFFFh
(inp_sys_csi_receiver_csi1_func_prg)—Offset 8010Ch” on page 1381

“reg_inp_sys_csi_receiver_csi1_init_cnt_type
80110h 4 00000000h
(inp_sys_csi_receiver_csi1_init_cnt)—Offset 80110h” on page 1382
“reg_inp_sys_csi_receiver_csi_backend_fs_ls_type
8011Ch 4 00000002h
(inp_sys_csi_receiver_csi_backend_fs_ls)—Offset 8011Ch” on page 1382
“reg_inp_sys_csi_receiver_csi_backend_ls_dvalid_type
80120h 4 (inp_sys_csi_receiver_csi_backend_ls_dvalid)—Offset 80120h” on 00000002h
page 1383
“reg_inp_sys_csi_receiver_csi_backend_dvalid_le_type
80124h 4 (inp_sys_csi_receiver_csi_backend_dvalid_le)—Offset 80124h” on 00000002h
page 1384
“reg_inp_sys_csi_receiver_csi_backend_le_fe_type
80128h 4 00000002h
(inp_sys_csi_receiver_csi_backend_le_fe)—Offset 80128h” on page 1384
“reg_inp_sys_csi_receiver_csi_backend_fe_fs_type
8012Ch 4 00000002h
(inp_sys_csi_receiver_csi_backend_fe_fs)—Offset 8012Ch” on page 1385

“reg_inp_sys_csi_receiver_csi_backend_le_ls_type
80130h 4 00000004h
(inp_sys_csi_receiver_csi_backend_le_ls)—Offset 80130h” on page 1386
“reg_inp_sys_csi_receiver_csi_backend_two_pixel_en_type
80134h 4 (inp_sys_csi_receiver_csi_backend_two_pixel_en)—Offset 80134h” on 00000000h
page 1386
“reg_inp_sys_csi_receiver_csi1_raw16_18_data_id_type
80138h 4 (inp_sys_csi_receiver_csi1_raw16_18_data_id)—Offset 80138h” on 00000000h
page 1387
“reg_inp_sys_csi_receiver_csi1_sync_cnt_type
8013Ch 4 FFFFFFFFh
(inp_sys_csi_receiver_csi1_sync_cnt)—Offset 8013Ch” on page 1388

Intel® Atom™ Processor E3800 Product Family

938 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

Table 167. Summary of Image Signal Processor Memory Mapped I/O Registers—
ISPMMADR (Continued)
Offset Size Register ID—Description Default Value

“reg_inp_sys_csi_receiver_csi1_rx_cnt_type
80140h 4 FFFFFFFFh
(inp_sys_csi_receiver_csi1_rx_cnt)—Offset 80140h” on page 1388

“reg_inp_sys_csi_receiver_csi_backend_rst_type
80144h 4 00000000h
(inp_sys_csi_receiver_csi_backend_rst)—Offset 80144h” on page 1389
“reg_inp_sys_csi_receiver_csi_backend_comp_pred_reg0_vc0_type
80148h 4 (inp_sys_csi_receiver_csi_backend_comp_pred_reg0_vc0)—Offset 00000000h
80148h” on page 1390
“reg_inp_sys_csi_receiver_csi_backend_comp_reg1_vc0_type
8014Ch 4 (inp_sys_csi_receiver_csi_backend_comp_reg1_vc0)—Offset 8014Ch” on 00000000h
page 1391
“reg_inp_sys_csi_receiver_csi_backend_comp_pred_reg0_vc1_type
80150h 4 (inp_sys_csi_receiver_csi_backend_comp_pred_reg0_vc1)—Offset 00000000h
80150h” on page 1392
“reg_inp_sys_csi_receiver_csi_backend_comp_reg1_vc1_type
80154h 4 (inp_sys_csi_receiver_csi_backend_comp_reg1_vc1)—Offset 80154h” on 00000000h
page 1393
“reg_inp_sys_csi_receiver_csi_backend_comp_pred_reg0_vc2_type
80158h 4 (inp_sys_csi_receiver_csi_backend_comp_pred_reg0_vc2)—Offset 00000000h
80158h” on page 1394
“reg_inp_sys_csi_receiver_csi_backend_comp_reg1_vc2_type
8015Ch 4 (inp_sys_csi_receiver_csi_backend_comp_reg1_vc2)—Offset 8015Ch” on 00000000h
page 1396
“reg_inp_sys_csi_receiver_csi_backend_comp_pred_reg0_vc3_type
80160h 4 (inp_sys_csi_receiver_csi_backend_comp_pred_reg0_vc3)—Offset 00000000h
80160h” on page 1396
“reg_inp_sys_csi_receiver_csi_backend_comp_reg1_vc3_type
80164h 4 (inp_sys_csi_receiver_csi_backend_comp_reg1_vc3)—Offset 80164h” on 00000000h
page 1398
“reg_inp_sys_csi_receiver_csi_backend_raw18_reg_type
80168h 4 (inp_sys_csi_receiver_csi_backend_raw18_reg)—Offset 80168h” on 00000000h
page 1399
“reg_inp_sys_csi_receiver_csi_backend_force_raw8_reg_type
8016Ch 4 (inp_sys_csi_receiver_csi_backend_force_raw8_reg)—Offset 8016Ch” on 00000000h
page 1399

“reg_inp_sys_csi_receiver_csi_backend_raw16_reg_type
80170h 4 (inp_sys_csi_receiver_csi_backend_raw16_reg)—Offset 80170h” on 00000000h
page 1400

“reg_inp_sys_csi_receiver_csi2_dev_ready_type
80200h 4 00000000h
(inp_sys_csi_receiver_csi2_dev_ready)—Offset 80200h” on page 1401
“reg_inp_sys_csi_receiver_csi2_int_status_type
80204h 4 00000000h
(inp_sys_csi_receiver_csi2_int_status)—Offset 80204h” on page 1402
“reg_inp_sys_csi_receiver_csi2_int_enable_type
80208h 4 00000000h
(inp_sys_csi_receiver_csi2_int_enable)—Offset 80208h” on page 1403

“reg_inp_sys_csi_receiver_csi2_func_prg_type
8020Ch 4 0007FFFFh
(inp_sys_csi_receiver_csi2_func_prg)—Offset 8020Ch” on page 1404
“reg_inp_sys_csi_receiver_csi2_init_cnt_type
80210h 4 00000000h
(inp_sys_csi_receiver_csi2_init_cnt)—Offset 80210h” on page 1405
“reg_inp_sys_csi_receiver_csi2_raw16_18_data_id_type
80238h 4 (inp_sys_csi_receiver_csi2_raw16_18_data_id)—Offset 80238h” on 00000000h
page 1406
“reg_inp_sys_csi_receiver_csi2_sync_cnt_type
8023Ch 4 000000FFh
(inp_sys_csi_receiver_csi2_sync_cnt)—Offset 8023Ch” on page 1406

Intel® Atom™ Processor E3800 Product Family

Datasheet 939
 MIPI-Camera Serial Interface (CSI) & ISP

Table 167. Summary of Image Signal Processor Memory Mapped I/O Registers—
ISPMMADR (Continued)
Offset Size Register ID—Description Default Value

“reg_inp_sys_csi_receiver_csi2_rx_cnt_type
80240h 4 000000FFh
(inp_sys_csi_receiver_csi2_rx_cnt)—Offset 80240h” on page 1407

“reg_inp_sys_csi_receiver_csi3_dev_ready_type
80300h 4 00000000h
(inp_sys_csi_receiver_csi3_dev_ready)—Offset 80300h” on page 1408
“reg_inp_sys_csi_receiver_csi3_int_status_type
80304h 4 00000000h
(inp_sys_csi_receiver_csi3_int_status)—Offset 80304h” on page 1408
“reg_inp_sys_csi_receiver_csi3_int_enable_type
80308h 4 00000000h
(inp_sys_csi_receiver_csi3_int_enable)—Offset 80308h” on page 1410

“reg_inp_sys_csi_receiver_csi3_func_prg_type
8030Ch 4 0007FFFFh
(inp_sys_csi_receiver_csi3_func_prg)—Offset 8030Ch” on page 1411
“reg_inp_sys_csi_receiver_csi3_init_cnt_type
80310h 4 00000000h
(inp_sys_csi_receiver_csi3_init_cnt)—Offset 80310h” on page 1412
“reg_inp_sys_csi_receiver_csi3_raw16_18_data_id_type
80338h 4 (inp_sys_csi_receiver_csi3_raw16_18_data_id)—Offset 80338h” on 00000000h
page 1412
“reg_inp_sys_csi_receiver_csi3_sync_cnt_type
8033Ch 4 0000FFFFh
(inp_sys_csi_receiver_csi3_sync_cnt)—Offset 8033Ch” on page 1413

“reg_inp_sys_csi_receiver_csi3_rx_cnt_type
80340h 4 00000000h
(inp_sys_csi_receiver_csi3_rx_cnt)—Offset 80340h” on page 1414
“reg_inp_sys_csi_receiver_csi_be_gen_sh_acc_ovl_type
80800h 4 (inp_sys_csi_receiver_csi_be_gen_sh_acc_ovl)—Offset 80800h” on 00000000h
page 1415
“reg_inp_sys_csi_receiver_csi_sh_be_srst_type
80804h 4 00000000h
(inp_sys_csi_receiver_csi_sh_be_srst)—Offset 80804h” on page 1415
“reg_inp_sys_csi_receiver_csi_sh_be_two_ppc_type
80808h 4 00000000h
(inp_sys_csi_receiver_csi_sh_be_two_ppc)—Offset 80808h” on page 1416

“reg_inp_sys_csi_receiver_csi_sh_be_comp_reg_vc0_type
8080Ch 4 (inp_sys_csi_receiver_csi_sh_be_comp_reg_vc0)—Offset 8080Ch” on 00000000h
page 1417

“reg_inp_sys_csi_receiver_csi_sh_be_comp_reg_vc1_type
80810h 4 (inp_sys_csi_receiver_csi_sh_be_comp_reg_vc1)—Offset 80810h” on 00000000h
page 1418
“reg_inp_sys_csi_receiver_csi_sh_be_comp_reg_vc2_type
80814h 4 (inp_sys_csi_receiver_csi_sh_be_comp_reg_vc2)—Offset 80814h” on 00000000h
page 1419
“reg_inp_sys_csi_receiver_csi_sh_be_comp_reg_vc3_type
80818h 4 (inp_sys_csi_receiver_csi_sh_be_comp_reg_vc3)—Offset 80818h” on 00000000h
page 1421
“reg_inp_sys_csi_receiver_csi_sh_be_sel_be_type
8081Ch 4 00000000h
(inp_sys_csi_receiver_csi_sh_be_sel_be)—Offset 8081Ch” on page 1422

“reg_inp_sys_csi_receiver_csi_sh_be_raw16_reg_type
80820h 4 (inp_sys_csi_receiver_csi_sh_be_raw16_reg)—Offset 80820h” on 00000000h
page 1422

“reg_inp_sys_csi_receiver_csi_sh_be_raw18_reg_type
80824h 4 (inp_sys_csi_receiver_csi_sh_be_raw18_reg)—Offset 80824h” on 00000000h
page 1423

“reg_inp_sys_csi_receiver_csi_sh_be_force_raw8_reg_type
80828h 4 (inp_sys_csi_receiver_csi_sh_be_force_raw8_reg)—Offset 80828h” on 00000000h
page 1424

“reg_inp_sys_csi_receiver_csi_sh_be_irq_stat_reg_type
8082Ch 4 (inp_sys_csi_receiver_csi_sh_be_irq_stat_reg)—Offset 8082Ch” on 00000000h
page 1425

Intel® Atom™ Processor E3800 Product Family

940 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

Table 167. Summary of Image Signal Processor Memory Mapped I/O Registers—
ISPMMADR (Continued)
Offset Size Register ID—Description Default Value

“reg_inp_sys_csi_receiver_csi_sh_be_irq_stat_clear_reg_type
80830h 4 (inp_sys_csi_receiver_csi_sh_be_irq_stat_clear_reg)—Offset 80830h” on 00000000h
page 1425
“reg_inp_sys_csi_receiver_csi_sh_be_custom_enable_reg_type
80834h 4 (inp_sys_csi_receiver_csi_sh_be_custom_enable_reg)—Offset 80834h” on 00000000h
page 1426
“reg_inp_sys_capt_unit_a_reg_CaptStartMode_type
81000h 4 00000000h
(inp_sys_capt_unit_a_reg_CaptStartMode)—Offset 81000h” on page 1427

“reg_inp_sys_capt_unit_a_reg_Capt_Start_Addr_type
81004h 4 (inp_sys_capt_unit_a_reg_Capt_Start_Addr)—Offset 81004h” on 00000000h
page 1428

“reg_inp_sys_capt_unit_a_reg_Capt_Mem_Region_Size_type
81008h 4 (inp_sys_capt_unit_a_reg_Capt_Mem_Region_Size)—Offset 81008h” on 00000080h
page 1428

“reg_inp_sys_capt_unit_a_reg_Capt_Num_Mem_Regions_type
8100Ch 4 (inp_sys_capt_unit_a_reg_Capt_Num_Mem_Regions)—Offset 8100Ch” on 00000003h
page 1429

“reg_inp_sys_capt_unit_a_reg_Capt_Init_type
81010h 4 00000000h
(inp_sys_capt_unit_a_reg_Capt_Init)—Offset 81010h” on page 1430
“reg_inp_sys_capt_unit_a_reg_Capt_Start_Addr_type
81014h 4 (inp_sys_capt_unit_a_reg_Capt_Start_Addr)—Offset 81004h” on 00000000h
page 1428
“reg_inp_sys_capt_unit_a_reg_Capt_Stop_type
81018h 4 00000000h
(inp_sys_capt_unit_a_reg_Capt_Stop)—Offset 81018h” on page 1431
“reg_inp_sys_capt_unit_a_reg_Capt_Packet_Length_type
8101Ch 4 (inp_sys_capt_unit_a_reg_Capt_Packet_Length)—Offset 8101Ch” on 00000000h
page 1432
“reg_inp_sys_capt_unit_a_reg_Capt_Received_Length_type
81020h 4 (inp_sys_capt_unit_a_reg_Capt_Received_Length)—Offset 81020h” on 00000000h
page 1432
“reg_inp_sys_capt_unit_a_reg_Capt_Received_Short_Packets_type
81024h 4 (inp_sys_capt_unit_a_reg_Capt_Received_Short_Packets)—Offset 00000000h
81024h” on page 1433
“reg_inp_sys_capt_unit_a_reg_Capt_Received_Long_Packets_type
81028h 4 (inp_sys_capt_unit_a_reg_Capt_Received_Long_Packets)—Offset 00000000h
81028h” on page 1433
“reg_inp_sys_capt_unit_a_reg_Capt_Last_Command_type
8102Ch 4 (inp_sys_capt_unit_a_reg_Capt_Last_Command)—Offset 8102Ch” on 0000000Fh
page 1434
“reg_inp_sys_capt_unit_a_reg_Capt_Next_Command_type
81030h 4 (inp_sys_capt_unit_a_reg_Capt_Next_Command)—Offset 81030h” on 0000000Fh
page 1435
“reg_inp_sys_capt_unit_a_reg_Capt_Last_Acknowledge_type
81034h 4 (inp_sys_capt_unit_a_reg_Capt_Last_Acknowledge)—Offset 81034h” on 0000000Fh
page 1435
“reg_inp_sys_capt_unit_a_reg_Capt_Next_Acknowledge_type
81038h 4 (inp_sys_capt_unit_a_reg_Capt_Next_Acknowledge)—Offset 81038h” on 0000000Fh
page 1436
“reg_inp_sys_capt_unit_a_reg_Capt_FSM_State_Info_type
8103Ch 4 (inp_sys_capt_unit_a_reg_Capt_FSM_State_Info)—Offset 8103Ch” on 00000000h
page 1436
“reg_inp_sys_capt_unit_b_reg_CaptStartMode_type
82000h 4 00000000h
(inp_sys_capt_unit_b_reg_CaptStartMode)—Offset 82000h” on page 1437

Intel® Atom™ Processor E3800 Product Family

Datasheet 941
 MIPI-Camera Serial Interface (CSI) & ISP

Table 167. Summary of Image Signal Processor Memory Mapped I/O Registers—
ISPMMADR (Continued)
Offset Size Register ID—Description Default Value

“reg_inp_sys_capt_unit_b_reg_Capt_Start_Addr_type
82004h 4 (inp_sys_capt_unit_b_reg_Capt_Start_Addr)—Offset 82004h” on 00000000h
page 1438
“reg_inp_sys_capt_unit_b_reg_Capt_Mem_Region_Size_type
82008h 4 (inp_sys_capt_unit_b_reg_Capt_Mem_Region_Size)—Offset 82008h” on 00000080h
page 1439
“reg_inp_sys_capt_unit_b_reg_Capt_Num_Mem_Regions_type
8200Ch 4 (inp_sys_capt_unit_b_reg_Capt_Num_Mem_Regions)—Offset 8200Ch” on 00000003h
page 1439
“reg_inp_sys_capt_unit_b_reg_Capt_Init_type
82010h 4 00000000h
(inp_sys_capt_unit_b_reg_Capt_Init)—Offset 82010h” on page 1440

“reg_inp_sys_capt_unit_b_reg_Capt_Start_Addr_type
82014h 4 (inp_sys_capt_unit_b_reg_Capt_Start_Addr)—Offset 82004h” on 00000000h
page 1438

“reg_inp_sys_capt_unit_b_reg_Capt_Stop_type
82018h 4 00000000h
(inp_sys_capt_unit_b_reg_Capt_Stop)—Offset 82018h” on page 1441
“reg_inp_sys_capt_unit_b_reg_Capt_Packet_Length_type
8201Ch 4 (inp_sys_capt_unit_b_reg_Capt_Packet_Length)—Offset 8201Ch” on 00000000h
page 1442
“reg_inp_sys_capt_unit_b_reg_Capt_Received_Length_type
82020h 4 (inp_sys_capt_unit_b_reg_Capt_Received_Length)—Offset 82020h” on 00000000h
page 1442
“reg_inp_sys_capt_unit_b_reg_Capt_Received_Short_Packets_type
82024h 4 (inp_sys_capt_unit_b_reg_Capt_Received_Short_Packets)—Offset 00000000h
82024h” on page 1443
“reg_inp_sys_capt_unit_b_reg_Capt_Received_Long_Packets_type
82028h 4 (inp_sys_capt_unit_b_reg_Capt_Received_Long_Packets)—Offset 00000000h
82028h” on page 1444
“reg_inp_sys_capt_unit_b_reg_Capt_Last_Command_type
8202Ch 4 (inp_sys_capt_unit_b_reg_Capt_Last_Command)—Offset 8202Ch” on 0000000Fh
page 1444
“reg_inp_sys_capt_unit_b_reg_Capt_Next_Command_type
82030h 4 (inp_sys_capt_unit_b_reg_Capt_Next_Command)—Offset 82030h” on 0000000Fh
page 1445

“reg_inp_sys_capt_unit_b_reg_Capt_Last_Acknowledge_type
82034h 4 (inp_sys_capt_unit_b_reg_Capt_Last_Acknowledge)—Offset 82034h” on 0000000Fh
page 1445

“reg_inp_sys_capt_unit_b_reg_Capt_Next_Acknowledge_type
82038h 4 (inp_sys_capt_unit_b_reg_Capt_Next_Acknowledge)—Offset 82038h” on 0000000Fh
page 1446

“reg_inp_sys_capt_unit_b_reg_Capt_FSM_State_Info_type
8203Ch 4 (inp_sys_capt_unit_b_reg_Capt_FSM_State_Info)—Offset 8203Ch” on 00000000h
page 1447

“reg_inp_sys_capt_unit_c_reg_CaptStartMode_type
83000h 4 00000000h
(inp_sys_capt_unit_c_reg_CaptStartMode)—Offset 83000h” on page 1448
“reg_inp_sys_capt_unit_c_reg_Capt_Start_Addr_type
83004h 4 (inp_sys_capt_unit_c_reg_Capt_Start_Addr)—Offset 83004h” on 00000000h
page 1448
“reg_inp_sys_capt_unit_c_reg_Capt_Mem_Region_Size_type
83008h 4 (inp_sys_capt_unit_c_reg_Capt_Mem_Region_Size)—Offset 83008h” on 00000080h
page 1449

Intel® Atom™ Processor E3800 Product Family

942 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

Table 167. Summary of Image Signal Processor Memory Mapped I/O Registers—
ISPMMADR (Continued)
Offset Size Register ID—Description Default Value

“reg_inp_sys_capt_unit_c_reg_Capt_Num_Mem_Regions_type
8300Ch 4 (inp_sys_capt_unit_c_reg_Capt_Num_Mem_Regions)—Offset 8300Ch” on 00000003h
page 1450
“reg_inp_sys_capt_unit_c_reg_Capt_Init_type
83010h 4 00000000h
(inp_sys_capt_unit_c_reg_Capt_Init)—Offset 83010h” on page 1450

“reg_inp_sys_capt_unit_c_reg_Capt_Start_Addr_type
83014h 4 (inp_sys_capt_unit_c_reg_Capt_Start_Addr)—Offset 83004h” on 00000000h
page 1448

“reg_inp_sys_capt_unit_c_reg_Capt_Stop_type
83018h 4 00000000h
(inp_sys_capt_unit_c_reg_Capt_Stop)—Offset 83018h” on page 1452
“reg_inp_sys_capt_unit_c_reg_Capt_Packet_Length_type
8301Ch 4 (inp_sys_capt_unit_c_reg_Capt_Packet_Length)—Offset 8301Ch” on 00000000h
page 1452
“reg_inp_sys_capt_unit_c_reg_Capt_Received_Length_type
83020h 4 (inp_sys_capt_unit_c_reg_Capt_Received_Length)—Offset 83020h” on 00000000h
page 1453
“reg_inp_sys_capt_unit_c_reg_Capt_Received_Short_Packets_type
83024h 4 (inp_sys_capt_unit_c_reg_Capt_Received_Short_Packets)—Offset 00000000h
83024h” on page 1453
“reg_inp_sys_capt_unit_c_reg_Capt_Received_Long_Packets_type
83028h 4 (inp_sys_capt_unit_c_reg_Capt_Received_Long_Packets)—Offset 00000000h
83028h” on page 1454
“reg_inp_sys_capt_unit_c_reg_Capt_Last_Command_type
8302Ch 4 (inp_sys_capt_unit_c_reg_Capt_Last_Command)—Offset 8302Ch” on 0000000Fh
page 1455
“reg_inp_sys_capt_unit_c_reg_Capt_Next_Command_type
83030h 4 (inp_sys_capt_unit_c_reg_Capt_Next_Command)—Offset 83030h” on 0000000Fh
page 1455
“reg_inp_sys_capt_unit_c_reg_Capt_Last_Acknowledge_type
83034h 4 (inp_sys_capt_unit_c_reg_Capt_Last_Acknowledge)—Offset 83034h” on 0000000Fh
page 1456
“reg_inp_sys_capt_unit_c_reg_Capt_Next_Acknowledge_type
83038h 4 (inp_sys_capt_unit_c_reg_Capt_Next_Acknowledge)—Offset 83038h” on 0000000Fh
page 1456

“reg_inp_sys_capt_unit_c_reg_Capt_FSM_State_Info_type
8303Ch 4 (inp_sys_capt_unit_c_reg_Capt_FSM_State_Info)—Offset 8303Ch” on 00000000h
page 1457

“reg_inp_sys_acq_unit_reg_Acq_Start_Addr_type
84000h 4 00000000h
(inp_sys_acq_unit_reg_Acq_Start_Addr)—Offset 84000h” on page 1458
“reg_inp_sys_acq_unit_reg_Acq_Mem_Region_Size_type
84004h 4 (inp_sys_acq_unit_reg_Acq_Mem_Region_Size)—Offset 84004h” on 00000080h
page 1459
“reg_inp_sys_acq_unit_reg_Acq_Num_Mem_Regions_type
84008h 4 (inp_sys_acq_unit_reg_Acq_Num_Mem_Regions)—Offset 84008h” on 00000003h
page 1459
“reg_inp_sys_acq_unit_reg_Acq_Init_type
8400Ch 4 00000000h
(inp_sys_acq_unit_reg_Acq_Init)—Offset 8400Ch” on page 1460
“reg_inp_sys_acq_unit_reg_Acq_Received_Short_Packets_type
84010h 4 (inp_sys_acq_unit_reg_Acq_Received_Short_Packets)—Offset 84010h” on 00000000h
page 1461
“reg_inp_sys_acq_unit_reg_Acq_Received_Long_Packets_type
84014h 4 (inp_sys_acq_unit_reg_Acq_Received_Long_Packets)—Offset 84014h” on 00000000h
page 1461

Intel® Atom™ Processor E3800 Product Family

Datasheet 943
 MIPI-Camera Serial Interface (CSI) & ISP

Table 167. Summary of Image Signal Processor Memory Mapped I/O Registers—
ISPMMADR (Continued)
Offset Size Register ID—Description Default Value

“reg_inp_sys_acq_unit_reg_Acq_Last_Command_type
84018h 4 (inp_sys_acq_unit_reg_Acq_Last_Command)—Offset 84018h” on 0000000Fh
page 1462
“reg_inp_sys_acq_unit_reg_Acq_Next_Command_type
8401Ch 4 (inp_sys_acq_unit_reg_Acq_Next_Command)—Offset 8401Ch” on 0000000Fh
page 1462
“reg_inp_sys_acq_unit_reg_Acq_Last_Acknowledge_type
84020h 4 (inp_sys_acq_unit_reg_Acq_Last_Acknowledge)—Offset 84020h” on 0000000Fh
page 1463
“reg_inp_sys_acq_unit_reg_Acq_Next_Acknowledge_type
84024h 4 (inp_sys_acq_unit_reg_Acq_Next_Acknowledge)—Offset 84024h” on 0000000Fh
page 1464
“reg_inp_sys_acq_unit_reg_Acq_FSM_State_Info_type
84028h 4 (inp_sys_acq_unit_reg_Acq_FSM_State_Info)—Offset 84028h” on 00000000h
page 1464
“reg_inp_sys_acq_unit_reg_Acq_Int_Cntr_Info_type
8402Ch 4 (inp_sys_acq_unit_reg_Acq_Int_Cntr_Info)—Offset 8402Ch” on 00000000h
page 1465
“reg_inp_sys_dma_DMA_FSM_Command_type
85000h 4 00000000h
(inp_sys_dma_DMA_FSM_Command)—Offset 85000h” on page 1466

“reg_inp_sys_dma_DMA_CH0_Packing_setup_type
86000h 4 00000000h
(inp_sys_dma_DMA_CH0_Packing_setup)—Offset 86000h” on page 1467
“reg_inp_sys_dma_DMA_CH0_dev_stride_A_type
86100h 4 00000000h
(inp_sys_dma_DMA_CH0_dev_stride_A)—Offset 86100h” on page 1468
“reg_inp_sys_dma_DMA_CH0_dev_Pack_left_crop_and_elem_A_type
86200h 4 (inp_sys_dma_DMA_CH0_dev_Pack_left_crop_and_elem_A)—Offset 00000000h
86200h” on page 1468
“reg_inp_sys_dma_DMA_CH0_Device_Xb_A_type
86300h 4 00000000h
(inp_sys_dma_DMA_CH0_Device_Xb_A)—Offset 86300h” on page 1469

“reg_inp_sys_dma_DMA_CH0_dev_stride_B_type
86400h 4 00000000h
(inp_sys_dma_DMA_CH0_dev_stride_B)—Offset 86400h” on page 1470
“reg_inp_sys_dma_DMA_CH0_dev_Pack_left_crop_and_elem_B_type
86500h 4 (inp_sys_dma_DMA_CH0_dev_Pack_left_crop_and_elem_B)—Offset 00000000h
86500h” on page 1471

“reg_inp_sys_dma_DMA_CH0_Device_Xb_B_type
86600h 4 00000000h
(inp_sys_dma_DMA_CH0_Device_Xb_B)—Offset 86600h” on page 1471
“reg_inp_sys_dma_DMA_CH0_Yb_type (inp_sys_dma_DMA_CH0_Yb)—
86700h 4 00000000h
Offset 86700h” on page 1472
“reg_inp_sys_dma_DMA_CH0_pending_command_type
86800h 4 (inp_sys_dma_DMA_CH0_pending_command)—Offset 86800h” on 00000000h
page 1473
“reg_inp_sys_dma_DMA_command_token_type
87000h 4 00000000h
(inp_sys_dma_DMA_command_token)—Offset 87000h” on page 1473

“reg_inp_sys_dma_DMA_command_src_addr_type
87004h 4 00000000h
(inp_sys_dma_DMA_command_src_addr)—Offset 87004h” on page 1474
“reg_inp_sys_dma_DMA_command_dst_addr_type
87008h 4 00000000h
(inp_sys_dma_DMA_command_dst_addr)—Offset 87008h” on page 1474
“reg_inp_sys_dma_DMA_command_ctrl_id_type
8700Ch 4 00000000h
(inp_sys_dma_DMA_command_ctrl_id)—Offset 8700Ch” on page 1475

“reg_inp_sys_dma_DMA_FSM_Ctrl_status_type
87010h 4 00000001h
(inp_sys_dma_DMA_FSM_Ctrl_status)—Offset 87010h” on page 1476

Intel® Atom™ Processor E3800 Product Family

944 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

Table 167. Summary of Image Signal Processor Memory Mapped I/O Registers—
ISPMMADR (Continued)
Offset Size Register ID—Description Default Value

“reg_inp_sys_dma_DMA_FSM_Pack_status_type
87014h 4 00000000h
(inp_sys_dma_DMA_FSM_Pack_status)—Offset 87014h” on page 1476

“reg_inp_sys_dma_DMA_FSM_request_status_type
87018h 4 00000000h
(inp_sys_dma_DMA_FSM_request_status)—Offset 87018h” on page 1477
“reg_inp_sys_dma_DMA_FSM_write_status_type
8701Ch 4 00000000h
(inp_sys_dma_DMA_FSM_write_status)—Offset 8701Ch” on page 1478
“reg_inp_sys_dma_DMA_FSM_Ctrl_dev_idx_type
87110h 4 00000000h
(inp_sys_dma_DMA_FSM_Ctrl_dev_idx)—Offset 87110h” on page 1479

“reg_inp_sys_dma_DMA_FSM_Pack_cnt_Yb_type
87114h 4 00000000h
(inp_sys_dma_DMA_FSM_Pack_cnt_Yb)—Offset 87114h” on page 1479
“reg_inp_sys_dma_DMA_FSM_Request_cnt_Yb_type
87118h 4 (inp_sys_dma_DMA_FSM_Request_cnt_Yb)—Offset 87118h” on 00000000h
page 1480
“reg_inp_sys_dma_DMA_FSM_Write_cnt_Y_type
8711Ch 4 00000000h
(inp_sys_dma_DMA_FSM_Write_cnt_Y)—Offset 8711Ch” on page 1481
“reg_inp_sys_dma_DMA_FSM_Ctrl_req_addr_type
87210h 4 00000000h
(inp_sys_dma_DMA_FSM_Ctrl_req_addr)—Offset 87210h” on page 1481

“reg_inp_sys_dma_DMA_FSM_Pack_req_cnt_Xb_type
87214h 4 (inp_sys_dma_DMA_FSM_Pack_req_cnt_Xb)—Offset 87214h” on 00000000h
page 1482

“reg_inp_sys_dma_DMA_FSM_Request_cnt_Xb_type
87218h 4 (inp_sys_dma_DMA_FSM_Request_cnt_Xb)—Offset 87218h” on 00000000h
page 1483

“reg_inp_sys_dma_DMA_FSM_Write_cnt_Xb_type
8721Ch 4 00000000h
(inp_sys_dma_DMA_FSM_Write_cnt_Xb)—Offset 8721Ch” on page 1483
“reg_inp_sys_dma_DMA_FSM_Ctrl_req_stride_type
87310h 4 00000000h
(inp_sys_dma_DMA_FSM_Ctrl_req_stride)—Offset 87310h” on page 1484
“reg_inp_sys_dma_DMA_FSM_Pack_wr_cnt_Xb_type
87314h 4 (inp_sys_dma_DMA_FSM_Pack_wr_cnt_Xb)—Offset 87314h” on 00000000h
page 1485
“reg_inp_sys_dma_DMA_FSM_Req_remining_Xb_type
87318h 4 (inp_sys_dma_DMA_FSM_Req_remining_Xb)—Offset 87318h” on 00000000h
page 1485
“reg_inp_sys_dma_DMA_FSM_Wr_remining_Xb_type
8731Ch 4 (inp_sys_dma_DMA_FSM_Wr_remining_Xb)—Offset 8731Ch” on 00000000h
page 1486
“reg_inp_sys_dma_DMA_FSM_Ctrl_req_Xb_type
87410h 4 00000000h
(inp_sys_dma_DMA_FSM_Ctrl_req_Xb)—Offset 87410h” on page 1487
“reg_inp_sys_dma_DMA_FSM_Req_burst_cnt_type
87418h 4 0000FFFFh
(inp_sys_dma_DMA_FSM_Req_burst_cnt)—Offset 87418h” on page 1487

“reg_inp_sys_dma_DMA_FSM_Wr_burst_cnt_type
8741Ch 4 0000FFFFh
(inp_sys_dma_DMA_FSM_Wr_burst_cnt)—Offset 8741Ch” on page 1488
“reg_inp_sys_dma_DMA_FSM_Ctrl_req_Yb_type
87510h 4 00000000h
(inp_sys_dma_DMA_FSM_Ctrl_req_Yb)—Offset 87510h” on page 1489
“reg_inp_sys_dma_DMA_FSM_Ctrl_Pack_req_dev_idx_type
87610h 4 (inp_sys_dma_DMA_FSM_Ctrl_Pack_req_dev_idx)—Offset 87610h” on 00000000h
page 1489
“reg_inp_sys_dma_DMA_FSM_Ctrl_Pack_wr_dev_idx_type
87710h 4 (inp_sys_dma_DMA_FSM_Ctrl_Pack_wr_dev_idx)—Offset 87710h” on 00000000h
page 1490

Intel® Atom™ Processor E3800 Product Family

Datasheet 945
 MIPI-Camera Serial Interface (CSI) & ISP

Table 167. Summary of Image Signal Processor Memory Mapped I/O Registers—
ISPMMADR (Continued)
Offset Size Register ID—Description Default Value

“reg_inp_sys_dma_DMA_FSM_Ctrl_Wr_addr_type
87810h 4 00000000h
(inp_sys_dma_DMA_FSM_Ctrl_Wr_addr)—Offset 87810h” on page 1491

“reg_inp_sys_dma_DMA_FSM_Ctrl_Wr_stride_type
87910h 4 00000000h
(inp_sys_dma_DMA_FSM_Ctrl_Wr_stride)—Offset 87910h” on page 1491
“reg_inp_sys_dma_DMA_FSM_Ctrl_pack_req_Xb_type
87A10h 4 (inp_sys_dma_DMA_FSM_Ctrl_pack_req_Xb)—Offset 87A10h” on 00000000h
page 1492
“reg_inp_sys_dma_DMA_FSM_Ctrl_pack_Yb_type
87B10h 4 00000000h
(inp_sys_dma_DMA_FSM_Ctrl_pack_Yb)—Offset 87B10h” on page 1493
“reg_inp_sys_dma_DMA_FSM_Ctrl_pack_wr_Xb_type
87C10h 4 (inp_sys_dma_DMA_FSM_Ctrl_pack_wr_Xb)—Offset 87C10h” on 00000000h
page 1493
“reg_inp_sys_dma_DMA_FSM_Ctrl_pack_req_elem_type
87D10h 4 (inp_sys_dma_DMA_FSM_Ctrl_pack_req_elem)—Offset 87D10h” on 00000000h
page 1494
“reg_inp_sys_dma_DMA_FSM_Ctrl_pack_wr_elem_type
87E10h 4 (inp_sys_dma_DMA_FSM_Ctrl_pack_wr_elem)—Offset 87E10h” on 00000000h
page 1495
“reg_inp_sys_dma_DMA_FSM_Ctrl_pack_sz_ext_ctrl_id_type
87F10h 4 (inp_sys_dma_DMA_FSM_Ctrl_pack_sz_ext_ctrl_id)—Offset 87F10h” on 00000000h
page 1495
“reg_inp_sys_dma_Dev_Interf_0_req_side_type
88000h 4 00000000h
(inp_sys_dma_Dev_Interf_0_req_side)—Offset 88000h” on page 1496

“reg_inp_sys_dma_Dev_Interf_1_req_side_type
88004h 4 00000006h
(inp_sys_dma_Dev_Interf_1_req_side)—Offset 88004h” on page 1497
“reg_inp_sys_dma_Dev_Interf_0_snd_side_type
88100h 4 00000004h
(inp_sys_dma_Dev_Interf_0_snd_side)—Offset 88100h” on page 1498
“reg_inp_sys_dma_Dev_Interf_1_snd_side_type
88104h 4 00000006h
(inp_sys_dma_Dev_Interf_1_snd_side)—Offset 88104h” on page 1499

“reg_inp_sys_dma_Dev_Interf_0_Fifo_status_type
88200h 4 00000004h
(inp_sys_dma_Dev_Interf_0_Fifo_status)—Offset 88200h” on page 1500

“reg_inp_sys_dma_Dev_Interf_1_Fifo_status_type
88204h 4 00000004h
(inp_sys_dma_Dev_Interf_1_Fifo_status)—Offset 88204h” on page 1501
“reg_inp_sys_dma_Dev_Interf_0_Req_complete_bust_type
88300h 4 (inp_sys_dma_Dev_Interf_0_Req_complete_bust)—Offset 88300h” on 00000000h
page 1502
“reg_inp_sys_dma_Dev_Interf_1_Req_complete_bust_type
88304h 4 (inp_sys_dma_Dev_Interf_1_Req_complete_bust)—Offset 88304h” on 00000000h
page 1503
“reg_inp_sys_dma_Dev_Interf_1_Max_burst_Size_type
88400h 4 (inp_sys_dma_Dev_Interf_1_Max_burst_Size)—Offset 88400h” on 0000007Fh
page 1504
“reg_inp_sys_inp_ctrl_inpsys_captA_start_addr_type
89000h 4 (inp_sys_inp_ctrl_inpsys_captA_start_addr)—Offset 89000h” on 00000000h
page 1504
“reg_inp_sys_inp_ctrl_inpsys_captB_start_addr_type
89004h 4 (inp_sys_inp_ctrl_inpsys_captB_start_addr)—Offset 89004h” on 00000000h
page 1505
“reg_inp_sys_inp_ctrl_inpsys_captC_start_addr_type
89008h 4 (inp_sys_inp_ctrl_inpsys_captC_start_addr)—Offset 89008h” on 00000000h
page 1506

Intel® Atom™ Processor E3800 Product Family

946 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

Table 167. Summary of Image Signal Processor Memory Mapped I/O Registers—
ISPMMADR (Continued)
Offset Size Register ID—Description Default Value

“reg_inp_sys_inp_ctrl_inpsys_captA_mem_region_size_type
8900Ch 4 (inp_sys_inp_ctrl_inpsys_captA_mem_region_size)—Offset 8900Ch” on 00000080h
page 1506
“reg_inp_sys_inp_ctrl_inpsys_captB_mem_region_size_type
89010h 4 (inp_sys_inp_ctrl_inpsys_captB_mem_region_size)—Offset 89010h” on 00000080h
page 1507
“reg_inp_sys_inp_ctrl_inpsys_captC_mem_region_size_type
89014h 4 (inp_sys_inp_ctrl_inpsys_captC_mem_region_size)—Offset 89014h” on 00000080h
page 1508
“reg_inp_sys_inp_ctrl_inpsys_captA_num_mem_regions_type
89018h 4 (inp_sys_inp_ctrl_inpsys_captA_num_mem_regions)—Offset 89018h” on 00000003h
page 1508
“reg_inp_sys_inp_ctrl_inpsys_captB_num_mem_regions_type
8901Ch 4 (inp_sys_inp_ctrl_inpsys_captB_num_mem_regions)—Offset 8901Ch” on 00000003h
page 1509
“reg_inp_sys_inp_ctrl_inpsys_captC_num_mem_regions_type
89020h 4 (inp_sys_inp_ctrl_inpsys_captC_num_mem_regions)—Offset 89020h” on 00000003h
page 1510
“reg_inp_sys_inp_ctrl_inpsys_acq_start_addr_type
89024h 4 00000000h
(inp_sys_inp_ctrl_inpsys_acq_start_addr)—Offset 89024h” on page 1511

“reg_inp_sys_inp_ctrl_inpsys_acq_mem_region_size_type
89028h 4 (inp_sys_inp_ctrl_inpsys_acq_mem_region_size)—Offset 89028h” on 00000080h
page 1511

“reg_inp_sys_inp_ctrl_inpsys_acq_num_mem_regions_type
8902Ch 4 (inp_sys_inp_ctrl_inpsys_acq_num_mem_regions)—Offset 8902Ch” on 00000003h
page 1512

“reg_inp_sys_inp_ctrl_inpsys_ctrl_init_type
89030h 4 00000000h
(inp_sys_inp_ctrl_inpsys_ctrl_init)—Offset 89030h” on page 1513
“reg_inp_sys_inp_ctrl_inpsys_last_cmd_type
89034h 4 0000000Fh
(inp_sys_inp_ctrl_inpsys_last_cmd)—Offset 89034h” on page 1513
“reg_inp_sys_inp_ctrl_inpsys_next_cmd_type
89038h 4 0000000Fh
(inp_sys_inp_ctrl_inpsys_next_cmd)—Offset 89038h” on page 1514

“reg_inp_sys_inp_ctrl_inpsys_last_ack_type
8903Ch 4 0000000Fh
(inp_sys_inp_ctrl_inpsys_last_ack)—Offset 8903Ch” on page 1514

“reg_inp_sys_inp_ctrl_inpsys_next_ack_type
89040h 4 0000000Fh
(inp_sys_inp_ctrl_inpsys_next_ack)—Offset 89040h” on page 1515
“reg_inp_sys_inp_ctrl_inpsys_top_fsm_state_type
89044h 4 00000000h
(inp_sys_inp_ctrl_inpsys_top_fsm_state)—Offset 89044h” on page 1515
“reg_inp_sys_inp_ctrl_inpsys_captA_fsm_state_type
89048h 4 (inp_sys_inp_ctrl_inpsys_captA_fsm_state)—Offset 89048h” on 00000000h
page 1516
“reg_inp_sys_inp_ctrl_inpsys_captB_fsm_state_type
8904Ch 4 (inp_sys_inp_ctrl_inpsys_captB_fsm_state)—Offset 8904Ch” on 00000000h
page 1517
“reg_inp_sys_inp_ctrl_inpsys_captC_fsm_state_type
89050h 4 (inp_sys_inp_ctrl_inpsys_captC_fsm_state)—Offset 89050h” on 00000000h
page 1517
“reg_inp_sys_inp_ctrl_inpsys_acq_fsm_state_type
89054h 4 00000000h
(inp_sys_inp_ctrl_inpsys_acq_fsm_state)—Offset 89054h” on page 1518

“reg_inp_sys_inp_ctrl_inpsys_capt_reserve_one_mem_region_type
89058h 4 (inp_sys_inp_ctrl_inpsys_capt_reserve_one_mem_region)—Offset 00000000h
89058h” on page 1519

Intel® Atom™ Processor E3800 Product Family

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 MIPI-Camera Serial Interface (CSI) & ISP

Table 167. Summary of Image Signal Processor Memory Mapped I/O Registers—
ISPMMADR (Continued)
Offset Size Register ID—Description Default Value

“reg_inp_sys_gpreg_str_multicastA_sel_type
8A000h 4 00000000h
(inp_sys_gpreg_str_multicastA_sel)—Offset 8A000h” on page 1520

“reg_inp_sys_gpreg_str_multicastB_sel_type
8A004h 4 00000000h
(inp_sys_gpreg_str_multicastB_sel)—Offset 8A004h” on page 1521
“reg_inp_sys_gpreg_str_multicastC_sel_type
8A008h 4 00000000h
(inp_sys_gpreg_str_multicastC_sel)—Offset 8A008h” on page 1521
“reg_inp_sys_gpreg_str_mux_sel_type (inp_sys_gpreg_str_mux_sel)—
8A00Ch 4 00000000h
Offset 8A00Ch” on page 1522

“reg_inp_sys_gpreg_str_mon_status_type
8A010h 4 00000000h
(inp_sys_gpreg_str_mon_status)—Offset 8A010h” on page 1522
“reg_inp_sys_gpreg_str_mon_irq_cond_type
8A014h 4 00000000h
(inp_sys_gpreg_str_mon_irq_cond)—Offset 8A014h” on page 1524
“reg_inp_sys_gpreg_str_mon_irq_en_type
8A018h 4 00000000h
(inp_sys_gpreg_str_mon_irq_en)—Offset 8A018h” on page 1525

“reg_inp_sys_gpreg_isys_srst_type (inp_sys_gpreg_isys_srst)—Offset
8A01Ch 4 00000000h
8A01Ch” on page 1526
“reg_inp_sys_gpreg_isys_slv_reg_srst_type
8A020h 4 00000000h
(inp_sys_gpreg_isys_slv_reg_srst)—Offset 8A020h” on page 1527
“reg_inp_sys_gpreg_str_deint_portA_cnt_type
8A024h 4 00000000h
(inp_sys_gpreg_str_deint_portA_cnt)—Offset 8A024h” on page 1528

“reg_inp_sys_gpreg_str_deint_portB_cnt_type
8A028h 4 00000000h
(inp_sys_gpreg_str_deint_portB_cnt)—Offset 8A028h” on page 1529
“reg_inp_sys_fifo_adapter_CSI_generic_short_packet_available_type
8B008h 4 (inp_sys_fifo_adapter_CSI_generic_short_packet_available)—Offset 00000001h
8B008h” on page 1530
“reg_inp_sys_irq_ctrl_irq_edge_type (inp_sys_irq_ctrl_irq_edge)—Offset
8C000h 4 00000000h
8C000h” on page 1530
“reg_inp_sys_irq_ctrl_irq_mask_type (inp_sys_irq_ctrl_irq_mask)—Offset
8C004h 4 00000000h
8C004h” on page 1531

“reg_inp_sys_irq_ctrl_irq_status_type (inp_sys_irq_ctrl_irq_status)—
8C008h 4 00000000h
Offset 8C008h” on page 1532

“reg_inp_sys_irq_ctrl_irq_clear_type (inp_sys_irq_ctrl_irq_clear)—Offset
8C00Ch 4 00000000h
8C00Ch” on page 1533
“reg_inp_sys_irq_ctrl_irq_en_type (inp_sys_irq_ctrl_irq_en)—Offset
8C010h 4 00000000h
8C010h” on page 1535
“reg_inp_sys_irq_ctrl_irq_level_not_pulse_type
8C014h 4 00000000h
(inp_sys_irq_ctrl_irq_level_not_pulse)—Offset 8C014h” on page 1536

“reg_isel_gpr_reg_gp_syncgen_enable_type
90000h 4 00000000h
(isel_gpr_reg_gp_syncgen_enable)—Offset 90000h” on page 1537
“reg_isel_gpr_reg_gp_syncgen_free_running_type
90004h 4 00000000h
(isel_gpr_reg_gp_syncgen_free_running)—Offset 90004h” on page 1537
“reg_isel_gpr_reg_gp_syncgen_pause_type
90008h 4 00000000h
(isel_gpr_reg_gp_syncgen_pause)—Offset 90008h” on page 1538

“reg_isel_gpr_reg_gp_nr_frames_type (isel_gpr_reg_gp_nr_frames)—
9000Ch 4 00000000h
Offset 9000Ch” on page 1539
“reg_isel_gpr_reg_gp_syngen_nr_pix_type
90010h 4 00000000h
(isel_gpr_reg_gp_syngen_nr_pix)—Offset 90010h” on page 1539
“reg_isel_gpr_reg_gp_syngen_nr_lines_type
90014h 4 00000000h
(isel_gpr_reg_gp_syngen_nr_lines)—Offset 90014h” on page 1540

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MIPI-Camera Serial Interface (CSI) & ISP

Table 167. Summary of Image Signal Processor Memory Mapped I/O Registers—
ISPMMADR (Continued)
Offset Size Register ID—Description Default Value

“reg_isel_gpr_reg_gp_syngen_hblank_cycles_type
90018h 4 00000000h
(isel_gpr_reg_gp_syngen_hblank_cycles)—Offset 90018h” on page 1541

“reg_isel_gpr_reg_gp_syngen_vblank_cycles_type
9001Ch 4 00000000h
(isel_gpr_reg_gp_syngen_vblank_cycles)—Offset 9001Ch” on page 1541
“reg_isel_gpr_reg_gp_isel_sof_type (isel_gpr_reg_gp_isel_sof)—Offset
90020h 4 00000000h
90020h” on page 1542
“reg_isel_gpr_reg_gp_isel_eof_type (isel_gpr_reg_gp_isel_eof)—Offset
90024h 4 00000000h
90024h” on page 1543

“reg_isel_gpr_reg_gp_isel_sol_type (isel_gpr_reg_gp_isel_sol)—Offset
90028h 4 00000000h
90028h” on page 1543
“reg_isel_gpr_reg_gp_isel_eol_type (isel_gpr_reg_gp_isel_eol)—Offset
9002Ch 4 00000000h
9002Ch” on page 1544
“reg_isel_gpr_reg_gp_isel_lfsr_enable_type
90030h 4 00000000h
(isel_gpr_reg_gp_isel_lfsr_enable)—Offset 90030h” on page 1544

“reg_isel_gpr_reg_gp_isel_lfsr_enable_b_type
90034h 4 00000000h
(isel_gpr_reg_gp_isel_lfsr_enable_b)—Offset 90034h” on page 1545
“reg_isel_gpr_reg_gp_isel_lfsr_reset_value_type
90038h 4 00000000h
(isel_gpr_reg_gp_isel_lfsr_reset_value)—Offset 90038h” on page 1546
“reg_isel_gpr_reg_gp_isel_tpg_enable_type
9003Ch 4 00000000h
(isel_gpr_reg_gp_isel_tpg_enable)—Offset 9003Ch” on page 1546

“reg_isel_gpr_reg_gp_isel_tpg_enable_b_type
90040h 4 00000000h
(isel_gpr_reg_gp_isel_tpg_enable_b)—Offset 90040h” on page 1547
“reg_isel_gpr_reg_gp_isel_hor_cnt_mask_type
90044h 4 00000000h
(isel_gpr_reg_gp_isel_hor_cnt_mask)—Offset 90044h” on page 1548
“reg_isel_gpr_reg_gp_isel_ver_cnt_mask_type
90048h 4 00000000h
(isel_gpr_reg_gp_isel_ver_cnt_mask)—Offset 90048h” on page 1548

“reg_isel_gpr_reg_gp_isel_xy_cnt_mask_type
9004Ch 4 00000000h
(isel_gpr_reg_gp_isel_xy_cnt_mask)—Offset 9004Ch” on page 1549
“reg_isel_gpr_reg_gp_isel_hor_cnt_delta_type
90050h 4 00000000h
(isel_gpr_reg_gp_isel_hor_cnt_delta)—Offset 90050h” on page 1550
“reg_isel_gpr_reg_gp_isel_ver_cnt_delta_type
90054h 4 00000000h
(isel_gpr_reg_gp_isel_ver_cnt_delta)—Offset 90054h” on page 1550
“reg_isel_gpr_reg_gp_isel_tpg_mode_type
90058h 4 00000000h
(isel_gpr_reg_gp_isel_tpg_mode)—Offset 90058h” on page 1551

“reg_isel_gpr_reg_gp_isel_tpg_red1_type
9005Ch 4 00000000h
(isel_gpr_reg_gp_isel_tpg_red1)—Offset 9005Ch” on page 1552
“reg_isel_gpr_reg_gp_isel_tpg_green1_type
90060h 4 00000000h
(isel_gpr_reg_gp_isel_tpg_green1)—Offset 90060h” on page 1552
“reg_isel_gpr_reg_gp_isel_tpg_blue1_type
90064h 4 00000000h
(isel_gpr_reg_gp_isel_tpg_blue1)—Offset 90064h” on page 1553

“reg_isel_gpr_reg_gp_isel_tpg_red2_type
90068h 4 00000000h
(isel_gpr_reg_gp_isel_tpg_red2)—Offset 90068h” on page 1554
“reg_isel_gpr_reg_gp_isel_tpg_green2_type
9006Ch 4 00000000h
(isel_gpr_reg_gp_isel_tpg_green2)—Offset 9006Ch” on page 1554
“reg_isel_gpr_reg_gp_isel_tpg_blue2_type
90070h 4 00000000h
(isel_gpr_reg_gp_isel_tpg_blue2)—Offset 90070h” on page 1555

“reg_isel_gpr_reg_gp_isel_ch_id_type (isel_gpr_reg_gp_isel_ch_id)—
90074h 4 00000000h
Offset 90074h” on page 1556

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 MIPI-Camera Serial Interface (CSI) & ISP

Table 167. Summary of Image Signal Processor Memory Mapped I/O Registers—
ISPMMADR (Continued)
Offset Size Register ID—Description Default Value

“reg_isel_gpr_reg_gp_isel_fmt_type_type
90078h 4 00000000h
(isel_gpr_reg_gp_isel_fmt_type)—Offset 90078h” on page 1556

“reg_isel_gpr_reg_gp_isel_data_sel_type
9007Ch 4 00000000h
(isel_gpr_reg_gp_isel_data_sel)—Offset 9007Ch” on page 1557
“reg_isel_gpr_reg_gp_isel_sband_sel_type
90080h 4 00000000h
(isel_gpr_reg_gp_isel_sband_sel)—Offset 90080h” on page 1557
“reg_isel_gpr_reg_gp_isel_sync_sel_type
90084h 4 00000000h
(isel_gpr_reg_gp_isel_sync_sel)—Offset 90084h” on page 1558

“reg_isel_gpr_reg_gp_syncgen_hor_cnt_type
90088h 4 00000000h
(isel_gpr_reg_gp_syncgen_hor_cnt)—Offset 90088h” on page 1559
“reg_isel_gpr_reg_gp_syncgen_ver_cnt_type
9008Ch 4 00000000h
(isel_gpr_reg_gp_syncgen_ver_cnt)—Offset 9008Ch” on page 1559
“reg_isel_gpr_reg_gp_syncgen_frame_cnt_type
90090h 4 00000000h
(isel_gpr_reg_gp_syncgen_frame_cnt)—Offset 90090h” on page 1560

“reg_isel_gpr_reg_gp_soft_reset_type (isel_gpr_reg_gp_soft_reset)—
90094h 4 00000000h
Offset 90094h” on page 1561
“reg_isel_fa_send_to_GP_FIFO_type (isel_fa_send_to_GP_FIFO)—Offset
90100h 4 00000000h
90100h” on page 1561
“reg_isel_fa_check_send_to_GP_FIFO_type
90108h 4 00000001h
(isel_fa_check_send_to_GP_FIFO)—Offset 90108h” on page 1562

“reg_isel_irq_ctrl_reg_irq_edge_type (isel_irq_ctrl_reg_irq_edge)—Offset
90200h 4 00000000h
90200h” on page 1563
“reg_isel_irq_ctrl_reg_irq_mask_type (isel_irq_ctrl_reg_irq_mask)—
90204h 4 00000000h
Offset 90204h” on page 1563
“reg_isel_irq_ctrl_reg_irq_status_type (isel_irq_ctrl_reg_irq_status)—
90208h 4 00000000h
Offset 90208h” on page 1564

“reg_isel_irq_ctrl_reg_irq_clear_type (isel_irq_ctrl_reg_irq_clear)—Offset
9020Ch 4 00000000h
9020Ch” on page 1564
“reg_isel_irq_ctrl_reg_irq_enable_type (isel_irq_ctrl_reg_irq_enable)—
90210h 4 00000000h
Offset 90210h” on page 1565
“reg_isel_irq_ctrl_reg_irq_level_not_pulse_type
90214h 4 00000000h
(isel_irq_ctrl_reg_irq_level_not_pulse)—Offset 90214h” on page 1566
“reg_icache_out_sys_c_mmu_MMU_invalidate_cache_type
A0000h 4 (icache_out_sys_c_mmu_MMU_invalidate_cache)—Offset A0000h” on 00000000h
page 1566
“reg_icache_out_sys_c_mmu_MMU_page_table_base_type
A0004h 4 (icache_out_sys_c_mmu_MMU_page_table_base)—Offset A0004h” on 00000000h
page 1567
“mem_scp_config_ilm_conf_ilm_prg_mem_sl_ip_pmem_prg_mem_first_t
B0000h 8 ype (scp_config_ilm_conf_ilm_prg_mem_sl_ip_pmem_prg_mem_first)— 0000000000000000h
Offset B0000h” on page 1568
“mem_scp_config_ilm_conf_ilm_prg_mem_sl_ip_pmem_prg_mem_last_t
B7FF8h 8 ype (scp_config_ilm_conf_ilm_prg_mem_sl_ip_pmem_prg_mem_last)— 0000000000000000h
Offset B7FF8h” on page 1568
“mem_isp_simd_vamem1_asp_lut_sl_ipvamem_asp_lut_first_type
1C0000h 2 (isp_simd_vamem1_asp_lut_sl_ipvamem_asp_lut_first)—Offset 1C0000h” 0000h
on page 1569
“mem_isp_simd_vamem1_asp_lut_sl_ipvamem_asp_lut_last_type
1C0FFEh 2 (isp_simd_vamem1_asp_lut_sl_ipvamem_asp_lut_last)—Offset 1C0FFEh” 0000h
on page 1569

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MIPI-Camera Serial Interface (CSI) & ISP

Table 167. Summary of Image Signal Processor Memory Mapped I/O Registers—
ISPMMADR (Continued)
Offset Size Register ID—Description Default Value

“mem_isp_simd_vamem2_asp_lut_sl_ipvamem_asp_lut_first_type
1D0000h 2 (isp_simd_vamem2_asp_lut_sl_ipvamem_asp_lut_first)—Offset 0000h
1D0000h” on page 1570
“mem_isp_simd_vamem2_asp_lut_sl_ipvamem_asp_lut_last_type
1D0FFEh 2 (isp_simd_vamem2_asp_lut_sl_ipvamem_asp_lut_last)—Offset 1D0FFEh” 0000h
on page 1570
“mem_isp_simd_vamem3_asp_lut_sl_ipvamem_asp_lut_first_type
1E0000h 2 (isp_simd_vamem3_asp_lut_sl_ipvamem_asp_lut_first)—Offset 1E0000h” 0000h
on page 1571
“mem_isp_simd_vamem3_asp_lut_sl_ipvamem_asp_lut_last_type
1E0FFEh 2 (isp_simd_vamem3_asp_lut_sl_ipvamem_asp_lut_last)—Offset 1E0FFEh” 0000h
on page 1571
“mem_isp_simd_histogram_asp_histogram_sl_iphist_asp_histogram_first
_type
1F0000h 4 00000000h
(isp_simd_histogram_asp_histogram_sl_iphist_asp_histogram_first)—
Offset 1F0000h” on page 1572
“mem_isp_simd_histogram_asp_histogram_sl_iphist_asp_histogram_last
_type
1F0FFCh 4 00000000h
(isp_simd_histogram_asp_histogram_sl_iphist_asp_histogram_last)—
Offset 1F0FFCh” on page 1572

“mem_isp_base_dmem_data_mem_sl_ipdmem_data_mem_first_type
200000h 4 (isp_base_dmem_data_mem_sl_ipdmem_data_mem_first)—Offset 00000000h
200000h” on page 1573

“mem_isp_base_dmem_data_mem_sl_ipdmem_data_mem_last_type
203FFCh 4 (isp_base_dmem_data_mem_sl_ipdmem_data_mem_last)—Offset 00000000h
203FFCh” on page 1573

“mem_scp_dmem_mem_sl_ip_dmem_mem_first_type
300000h 4 (scp_dmem_mem_sl_ip_dmem_mem_first)—Offset 300000h” on 00000000h
page 1574

“mem_scp_dmem_mem_sl_ip_dmem_mem_last_type
307FFCh 4 (scp_dmem_mem_sl_ip_dmem_mem_last)—Offset 307FFCh” on 00000000h
page 1574

“reg_fa_sp_isp_send_to_SP_type (fa_sp_isp_send_to_SP)—Offset
380008h 4 00000000h
380008h” on page 1575

“reg_fa_sp_isp_send_to_ISP_type (fa_sp_isp_send_to_ISP)—Offset
38000Ch 4 00000000h
38000Ch” on page 1575
“reg_fa_sp_isp_check_receive_from_SP_type
380010h 4 00000001h
(fa_sp_isp_check_receive_from_SP)—Offset 380010h” on page 1576
“reg_fa_sp_isp_check_receive_from_ISP_type
380014h 4 00000001h
(fa_sp_isp_check_receive_from_ISP)—Offset 380014h” on page 1576

“reg_fa_sp_isp_check_send_to_SP_type (fa_sp_isp_check_send_to_SP)—
380018h 4 00000000h
Offset 380018h” on page 1577
“reg_fa_sp_isp_check_send_to_ISP_type
38001Ch 4 00000000h
(fa_sp_isp_check_send_to_ISP)—Offset 38001Ch” on page 1578

15.8.1 reg_gpd_gp_reg_reg_gp_sdram_wakeup_type
(gpd_gp_reg_reg_gp_sdram_wakeup)—Offset 0h
Access Method

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Type: Memory Mapped I/O Register

gpd_gp_reg_reg_gp_sdram_wakeup: [ISPMMADR] + 0h
(Size: 32 bits)
ISPMMADR Type: PCI Configuration Register (Size: 32 bits)
ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

unused_reg_gp_sdram_wakeup

reg_gp_sdram_wakeup
Bit Default &
Description
Range Access

0h
31:1 unused_reg_gp_sdram_wakeup: Unused
RW
0h reg_gp_sdram_wakeup: when set to 1, this signal will cause the memory controller
0
RW to bring the external SDRAM into an active state.

15.8.2 reg_gpd_gp_reg_reg_gp_idle_type
(gpd_gp_reg_reg_gp_idle)—Offset 4h
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) gpd_gp_reg_reg_gp_idle: [ISPMMADR] + 4h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_reg_gp_idle

reg_gp_idle

Bit Default &

Description
Range Access

0h
31:1 unused_reg_gp_idle: Unused
RW

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MIPI-Camera Serial Interface (CSI) & ISP

Bit Default &

Description
Range Access

0h
0 reg_gp_idle: Should be set to 1 when ISP system is in ?idle? mode.
RW

15.8.3 reg_gpd_gp_reg_reg_gp_irq_req0_type
(gpd_gp_reg_reg_gp_irq_req0)—Offset 8h
Access Method
Type: Memory Mapped I/O Register
gpd_gp_reg_reg_gp_irq_req0: [ISPMMADR] + 8h
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

unused_reg_gp_irq_req0

reg_gp_irq_req0
Bit Default &
Description
Range Access

0h
31:1 unused_reg_gp_irq_req0: Unused
RW

0h reg_gp_irq_req0: possibly causes an interrupt request (if the host interrupt controller
0
RW is properly configured)

15.8.4 reg_gpd_gp_reg_reg_gp_irq_req1_type
(gpd_gp_reg_reg_gp_irq_req1)—Offset Ch
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) gpd_gp_reg_reg_gp_irq_req1: [ISPMMADR] + Ch

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h

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31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

unused_reg_gp_irq_req1

reg_gp_irq_req1
Bit Default &
Description
Range Access

0h
31:1 unused_reg_gp_irq_req1: Unused
RW
0h reg_gp_irq_req1: possibly causes an interrupt request (if the host interrupt controller
0
RW is properly configured)

15.8.5 reg_gpd_gp_reg_reg_gp_sp_stream_stat_type
(gpd_gp_reg_reg_gp_sp_stream_stat)—Offset 10h
Indicate the status of the streaming ports of the scalar processor. All valid and accept
signals of the scalar processor are reflected in this register and in
reg_gp_sp_stream_stat_b.

Access Method
Type: Memory Mapped I/O Register gpd_gp_reg_reg_gp_sp_stream_stat: [ISPMMADR] + 10h
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00022022h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0
SP_STR_MON_SP2SIF_accept
SP_STR_MON_SP2ISP_accept

SP_STR_MON_DMA2SP_accept

SP_STR_MON_SP2DMA_accept

SP_STR_MON_SIF2SP_accept
SP_STR_MON_SP2PIFB_accept

SP_STR_MON_PIF2SP_accept

SP_STR_MON_SP2PIF_accept

SP_STR_MON_ISYS2SP_accept

SP_STR_MON_SP2ISYS_accept

SP_STR_MON_GPD2SP_accept

SP_STR_MON_SP2GPD_accept

SP_STR_MON_ISP2SP_accept

SP_STR_MON_SP2MC_accept
SP_STR_MON_PIFB2SP_accept

SP_STR_MON_ISYS2SP_valid
SP_STR_MON_PIF2SP_valid

SP_STR_MON_SP2PIF_valid

SP_STR_MON_ISP2SP_valid

SP_STR_MON_SP2ISP_valid

SP_STR_MON_MC2SP_accept
SP_STR_MON_SP2ISYS_valid

SP_STR_MON_GPD2SP_valid

SP_STR_MON_SP2GPD_valid
SP_STR_MON_PIFB2SP_valid

SP_STR_MON_SP2PIFB_valid

SP_STR_MON_DMA2SP_valid

SP_STR_MON_SP2DMA_valid

SP_STR_MON_SP2MC_valid

SP_STR_MON_SIF2SP_valid

SP_STR_MON_SP2SIF_valid
SP_STR_MON_MC2SP_valid

Bit Default &

Description
Range Access

SP_STR_MON_PIFB2SP_accept: Returns the value 1 if the SP can accept an

0h acknowledge token from the FIFO between the primary input formatter B acknowledge
31
RO port and the SP. Returns the value 0 if the SP cannot accept a token on this SP input
port.

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MIPI-Camera Serial Interface (CSI) & ISP

Bit Default &

Description
Range Access

SP_STR_MON_PIFB2SP_valid: Returns the value 1 if a valid acknowledge token from

0h the FIFO between the primary input formatter B acknowledge port and the SP, is present
30
RO on the primary input formatter B input port of the SP. Returns the value 0 if there is no
valid acknowledge token available on this SP input port.

0h SP_STR_MON_SP2PIFB_accept: Returns the value 1 if the command FIFO between

29 SP and the Primary input formatter B can accept a command from the SP. Returns the
RO value 0 if this FIFO cannot accept a token from the SP.

0h SP_STR_MON_SP2PIFB_valid: Returns the value 1 if SP sends a command using the

28 streaming port connected to the Primary Input Formatter B command FIFO. Returns the
RO value 0 if the SP does not send a command to this FIFO
SP_STR_MON_PIF2SP_accept: Returns the value 1 if the SP can accept an
0h acknowledge token from the FIFO between the primary input formatter acknowledge
27
RO port and the SP. Returns the value 0 if the SP cannot accept a token on this SP input
port.

SP_STR_MON_PIF2SP_valid: Returns the value 1 if a valid acknowledge token from

0h the FIFO between the primary input formatter acknowledge port and the SP, is present
26
RO on the primary input formatter input port of the SP. Returns the value 0 if there is no
valid acknowledge token available on this SP input port.

0h SP_STR_MON_SP2PIF_accept: Returns the value 1 if the command FIFO between SP

25 and the Primary input formatter can accept a command from the SP. Returns the value 0
RO if this command FIFO cannot accept a command from the SP.

0h SP_STR_MON_SP2PIF_valid: Returns the value 1 if SP sends a command using the

24 streaming port connected to the Primary Input Formatter command FIFO. Returns the
RO value 0 if the SP does not send a command to the Primary Input formatter

0h SP_STR_MON_ISYS2SP_accept: Returns the value 1 if the SP can accept an

23 acknowledge token from the FIFO between the input system acknowledge port and the
RO SP. Returns the value 0 if the SP cannot accept a token on this SP input port.
SP_STR_MON_ISYS2SP_valid: Returns the value 1 if a valid acknowledge token from
0h the FIFO between the input system acknowledge port and the SP, is present on the input
22
RO system input port of the SP. Returns the value 0 if there is no valid acknowledge token
available on this SP input port.

0h SP_STR_MON_SP2ISYS_accept: Returns the value 1 if the command FIFO between

21 SP and the input system can accept a command from the SP. Returns the value 0 if this
RO command FIFO cannot accept a command from the SP.

0h SP_STR_MON_SP2ISYS_valid: Returns the value 1 if SP sends a command using the

20 streaming port connected to the input system command FIFO. Returns the value 0 if the
RO SP does not send a command to the input system

0h SP_STR_MON_GPD2SP_accept: Returns the value 1 if the SP can accept a token

19 from the streaming FIFO between the fifo adpater in GP devices and the SP. Returns 0 if
RO the SP cannot accept a token from this FIFO.

0h SP_STR_MON_GPD2SP_valid: Returns the value 1 if the streaming FIFO between the

18 fifo adapter in GP devices and the SP has a valid token for the SP. Returns the value 0 if
RO this FIFO is empty.

1h SP_STR_MON_SP2GPD_accept: Returns the value 1 if the token FIFO between SP

17 and fifo adapter can accept a token from the SP. Returns the value 0 if this token FIFO is
RO full.

0h SP_STR_MON_SP2GPD_valid: Returns the value 1 if SP sends a token using the

16 streaming port connected to the token FIFO between the SP and the fifo adapter in
RO GP_devices. Returns the value 0 if the SP does not send a token to the fifo adapter.

0h SP_STR_MON_ISP2SP_accept: Returns the value 1 if the SP can accept a token from

15 the streaming FIFO between the ISP and the SP. Returns 0 if the SP cannot accept a
RO token from this FIFO.

0h SP_STR_MON_ISP2SP_valid: Returns the value 1 if the streaming FIFO between the

14
RO ISP and the SP has a valid token for the SP. Returns the value 0 if this FIFO is empty

1h SP_STR_MON_SP2ISP_accept: Returns the value 1 if the token FIFO between SP

13
RO and ISP can accept a token from the SP. Returns the value 0 if this token FIFO is full.

Intel® Atom™ Processor E3800 Product Family

Datasheet 955
 MIPI-Camera Serial Interface (CSI) & ISP

Bit Default &

Description
Range Access

0h SP_STR_MON_SP2ISP_valid: Returns the value 1 if SP sends a token using the

12 streaming port connected to the ISP token FIFO. Returns the value 0 if the SP does not
RO send a token to the ISP

0h SP_STR_MON_DMA2SP_accept: Returns the value 1 if the SP can accept an

11 acknowledge token from the FIFO between the DMA acknowledge port and the SP.
RO Returns the value 0 if the SP cannot accept a token on this SP input port.
SP_STR_MON_DMA2SP_valid: Returns the value 1 if a valid acknowledge token from
0h the FIFO between the DMA acknowledge port and the SP, is present on the DMA input
10
RO port of the SP. Returns the value 0 if there is no valid acknowledge token available on
this SP input port.

0h SP_STR_MON_SP2DMA_accept: Returns the value 1 if the command FIFO between

9 SP and the DMA can accept a command from the SP. Returns the value 0 if this
RO command FIFO cannot accept a command from the SP.

0h SP_STR_MON_SP2DMA_valid: Returns the value 1 if SP sends a command using the

8 streaming port connected to the DMA command FIFO. Returns the value 0 if the SP does
RO not send a command to the DMA

0h SP_STR_MON_MC2SP_accept: Returns the value 1 if the SP can accept an

7 acknowledge token from the FIFO between the stream2mem acknowledge port and the
RO SP. Returns the value 0 if the SP cannot accept a token on this SP input port.
SP_STR_MON_MC2SP_valid: Returns the value 1 if a valid acknowledge token from
0h the FIFO between the stream2mem acknowledge port and the SP, is present on the
6
RO stream2mem input port of the SP. Returns the value 0 if there is no valid acknowledge
token available on this SP input port.

1h SP_STR_MON_SP2MC_accept: Returns the value 1 if the command FIFO between SP

5 and the stream2mem can accept a command from the SP. Returns the value 0 if this
RO command FIFO is full.

0h SP_STR_MON_SP2MC_valid: Returns the value 1 if SP sends a command using the

4 streaming port connected to the stream2mem command FIFO. Returns the value 0 if the
RO SP does not send a command to the stream2mem

SP_STR_MON_SIF2SP_accept: Returns the value 1 if the SP can accept an

0h acknowledge token from the FIFO between the secondary input formatter acknowledge
3
RO port and the SP. Returns the value 0 if the SP cannot accept a token on this SP input
port.
SP_STR_MON_SIF2SP_valid: Returns the value 1 if a valid acknowledge token from
0h the FIFO between the secondary input formatter acknowledge port and the SP, is
2
RO present on the secondary input formatter input port of the SP. Returns the value 0 if
there is no valid acknowledge token available on this SP input port.

1h SP_STR_MON_SP2SIF_accept: Returns the value 1 if the command FIFO between SP

1 and the secondary input formatter can accept a command from the SP. Returns the
RO value 0 if this command FIFO is full.

0h SP_STR_MON_SP2SIF_valid: Returns the value 1 if SP sends a command using the

0 streaming port connected to the Secondary Input Formatter command FIFO. Returns
RO the value 0 if the SP does not send a command to the Secondary Input formatter

15.8.6 reg_gpd_gp_reg_reg_gp_sp_stream_stat_b_type
(gpd_gp_reg_reg_gp_sp_stream_stat_b)—Offset 14h
Indicate the status of the streaming ports of the scalar processor. All valid and accept
signals of the scalar processor are reflected in this register and in
reg_gp_sp_stream_stat.

Access Method

Intel® Atom™ Processor E3800 Product Family

956 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

Type: Memory Mapped I/O Register

gpd_gp_reg_reg_gp_sp_stream_stat_b: [ISPMMADR] + 14h
(Size: 32 bits)
ISPMMADR Type: PCI Configuration Register (Size: 32 bits)
ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SP_STR_MON_SP2GDC2_accept

SP_STR_MON_SP2GDC1_accept
unused_reg_gp_sp_stream_stat_b

SP_STR_MON_GDC22SP_accept

SP_STR_MON_GDC12SP_accept
SP_STR_MON_GDC22SP_valid

SP_STR_MON_GDC12SP_valid
SP_STR_MON_SP2GDC2_valid

SP_STR_MON_SP2GDC1_valid
Bit Default &
Description
Range Access

0h
31:8 unused_reg_gp_sp_stream_stat_b: Unused
RW

0h SP_STR_MON_GDC22SP_accept: Returns the value 1 if the SP can accept an

7 acknowledge token from the FIFO between the GDC2 acknowledge port and the SP.
RO Returns the value 0 if the SP cannot accept a token on this SP input port.

SP_STR_MON_GDC22SP_valid: Returns the value 1 if a valid acknowledge token

0h from the FIFO between the GDC2 acknowledge port and the SP, is present on the GDC2
6
RO input port of the SP. Returns the value 0 if there is no valid acknowledge token available
on this SP input port.

0h SP_STR_MON_SP2GDC2_accept: Returns the value 1 if the command FIFO between

5 SP and GDC2 can accept a command from the SP. Returns the value 0 if this command
RO FIFO cannot accept a command from the SP.

0h SP_STR_MON_SP2GDC2_valid: Returns the value 1 if SP sends a command using

4 the streaming port connected to GDC2 command FIFO. Returns the value 0 if the SP
RO does not send a command to GDC2

0h SP_STR_MON_GDC12SP_accept: Returns the value 1 if the SP can accept an

3 acknowledge token from the FIFO between the GDC1 acknowledge port and the SP.
RO Returns the value 0 if the SP cannot accept a token on this SP input port.
SP_STR_MON_GDC12SP_valid: Returns the value 1 if a valid acknowledge token
0h from the FIFO between the GDC1 acknowledge port and the SP, is present on the GDC1
2
RO input port of the SP. Returns the value 0 if there is no valid acknowledge token available
on this SP input port.

0h SP_STR_MON_SP2GDC1_accept: Returns the value 1 if the command FIFO between

1 SP and GDC1 can accept a command from the SP. Returns the value 0 if this command
RO FIFO cannot accept a command from the SP.

0h SP_STR_MON_SP2GDC1_valid: Returns the value 1 if SP sends a command using

0 the streaming port connected to GDC1 command FIFO. Returns the value 0 if the SP
RO does not send a command to GDC1

Intel® Atom™ Processor E3800 Product Family

Datasheet 957
 MIPI-Camera Serial Interface (CSI) & ISP

15.8.7 reg_gpd_gp_reg_reg_gp_isp_stream_stat_type
(gpd_gp_reg_reg_gp_isp_stream_stat)—Offset 18h
Indicate the status of the streaming ports of the vector processor. All valid and accept
signals of the vector processor are reflected in this register.

Access Method
Type: Memory Mapped I/O Register
gpd_gp_reg_reg_gp_isp_stream_stat: [ISPMMADR] + 18h
(Size: 32 bits)
ISPMMADR Type: PCI Configuration Register (Size: 32 bits)
ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 02200000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ISP_STR_MON_SP2ISP_accept

ISP_STR_MON_GDC22ISP_accept

ISP_STR_MON_ISP2GDC2_accept

ISP_STR_MON_GDC12ISP_accept

ISP_STR_MON_ISP2GDC1_accept

ISP_STR_MON_DMA2ISP_accept

ISP_STR_MON_ISP2DMA_accept

ISP_STR_MON_PIFB2ISP_accept

ISP_STR_MON_ISP2PIFB_accept

ISP_STR_MON_PIF2ISP_accept

ISP_STR_MON_ISP2PIF_accept
ISP_STR_MON_GPD2ISP_accept

ISP_STR_MON_ISP2GPD_accept
unused_reg_gp_isp_stream_stat

ISP_STR_MON_ISP2SP_accept

ISP_STR_MON_ISP2PIFB_valid
ISP_STR_MON_GPD2ISP_valid
ISP_STR_MON_SP2ISP_valid

ISP_STR_MON_ISP2GPD_valid

ISP_STR_MON_ISP2GDC2_valid

ISP_STR_MON_ISP2GDC1_valid

ISP_STR_MON_ISP2DMA_valid

ISP_STR_MON_PIFB2ISP_valid

ISP_STR_MON_PIF2ISP_valid

ISP_STR_MON_ISP2PIF_valid
ISP_STR_MON_ISP2SP_valid

ISP_STR_MON_GDC22ISP_valid

ISP_STR_MON_GDC12ISP_valid

ISP_STR_MON_DMA2ISP_valid

Bit Default &

Description
Range Access

0h
31:28 unused_reg_gp_isp_stream_stat: Unused
RW

0h ISP_STR_MON_SP2ISP_accept: Returns the value 1 if the ISP can accept a token

27 from the streaming FIFO between the SP and the ISP. Returns 0 if the ISP cannot accept
RO a token from this FIFO.

0h ISP_STR_MON_SP2ISP_valid: Returns the value 1 if the streaming FIFO between

26 the SP and the ISP has a valid token for the ISP. Returns the value 0 if this FIFO is
RO empty
1h ISP_STR_MON_ISP2SP_accept: Returns the value 1 if the token FIFO between ISP
25
RO and SP can accept a token from the ISP. Returns the value 0 if this token FIFO is full.

0h ISP_STR_MON_ISP2SP_valid: Returns the value 1 if ISP sends a token using the

24 streaming port connected to the SP token FIFO. Returns the value 0 if the ISP does not
RO send a token to the SP

0h ISP_STR_MON_GPD2ISP_accept: Returns the value 1 if the ISP can accept a token

23 from the streaming FIFO between the fifo adpater in GP devices and the ISP. Returns 0
RO if the ISP cannot accept a token from this FIFO.

0h ISP_STR_MON_GPD2ISP_valid: Returns the value 1 if the streaming FIFO between

22 the fifo adapter in GP devices and the ISP has a valid token for the ISP. Returns the
RO value 0 if this FIFO is empty.

1h ISP_STR_MON_ISP2GPD_accept: Returns the value 1 if the token FIFO between ISP

21 and fifo adapter can accept a token from the ISP. Returns the value 0 if this token FIFO
RO is full.

0h ISP_STR_MON_ISP2GPD_valid: Returns the value 1 if ISP sends a token using the

20 streaming port connected to the token FIFO between the ISP and the fifo adapter in
RO GP_devices. Returns the value 0 if the ISP does not send a token to the fifo adapter.

Intel® Atom™ Processor E3800 Product Family

958 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

Bit Default &

Description
Range Access

0h ISP_STR_MON_GDC22ISP_accept: Returns the value 1 if the ISP can accept an

19 acknowledge token from the FIFO between the GDC2 acknowledge port and the ISP.
RO Returns the value 0 if the ISP cannot accept a token on this ISP input port.
ISP_STR_MON_GDC22ISP_valid: Returns the value 1 if a valid acknowledge token
0h from the FIFO between the GDC2 acknowledge port and the ISP, is present on the GDC2
18
RO input port of the ISP. Returns the value 0 if there is no valid acknowledge token available
on this ISP input port.

0h ISP_STR_MON_ISP2GDC2_accept: Returns the value 1 if the command FIFO

17 between ISP and GDC2 can accept a command from the ISP. Returns the value 0 if this
RO command FIFO is full.

0h ISP_STR_MON_ISP2GDC2_valid: Returns the value 1 if ISP sends a command using

16 the streaming port connected to the GDC2 command FIFO. Returns the value 0 if the
RO ISP does not send a command to GDC2

0h ISP_STR_MON_GDC12ISP_accept: Returns the value 1 if the ISP can accept an

15 acknowledge token from the FIFO between the GDC1 acknowledge port and the ISP.
RO Returns the value 0 if the ISP cannot accept a token on this ISP input port.
ISP_STR_MON_GDC12ISP_valid: Returns the value 1 if a valid acknowledge token
0h from the FIFO between the GDC1 acknowledge port and the ISP, is present on the GDC1
14
RO input port of the ISP. Returns the value 0 if there is no valid acknowledge token available
on this ISP input port.

0h ISP_STR_MON_ISP2GDC1_accept: Returns the value 1 if the command FIFO

13 between ISP and GDC1 can accept a command from the ISP. Returns the value 0 if this
RO command FIFO is full.

0h ISP_STR_MON_ISP2GDC1_valid: Returns the value 1 if ISP sends a command using

12 the streaming port connected to the GDC1 command FIFO. Returns the value 0 if the
RO ISP does not send a command to GDC1

0h ISP_STR_MON_DMA2ISP_accept: Returns the value 1 if the ISP can accept an

11 acknowledge token from the FIFO between the DMA acknowledge port and the ISP.
RO Returns the value 0 if the ISP cannot accept a token on this ISP input port.

ISP_STR_MON_DMA2ISP_valid: Returns the value 1 if a valid acknowledge token

0h from the FIFO between the DMA acknowledge port and the ISP, is present on the DMA
10
RO input port of the ISP. Returns the value 0 if there is no valid acknowledge token available
on this ISP input port.

0h ISP_STR_MON_ISP2DMA_accept: Returns the value 1 if the command FIFO

9 between ISP and the DMA can accept a command from the ISP. Returns the value 0 if
RO this command FIFO cannot accept a token from the ISP.

0h ISP_STR_MON_ISP2DMA_valid: Returns the value 1 if ISP sends a command using

8 the streaming port connected to the DMA command FIFO. Returns the value 0 if the ISP
RO does not send a command to the DMA
ISP_STR_MON_PIFB2ISP_accept: Returns the value 1 if the ISP can accept an
0h acknowledge token from the FIFO between the primary input formatter B acknowledge
7
RO port and the ISP. Returns the value 0 if the ISP cannot accept a token on this ISP input
port.

ISP_STR_MON_PIFB2ISP_valid: Returns the value 1 if a valid acknowledge token

0h from the FIFO between the primary input formatter B acknowledge port and the ISP, is
6
RO present on the primary input formatter B input port of the ISP. Returns the value 0 if
there is no valid acknowledge token available on this ISP input port.

0h ISP_STR_MON_ISP2PIFB_accept: Returns the value 1 if the command FIFO

5 between ISP and the Primary input formatter B can accept a command from the ISP.
RO Returns the value 0 if this FIFO cannot accept a command from the ISP.

0h ISP_STR_MON_ISP2PIFB_valid: Returns the value 1 if ISP sends a command using

4 the streaming port connected to the Primary Input Formatter B command FIFO. Returns
RO the value 0 if the ISP does not send a command to the Primary Input formatter B
ISP_STR_MON_PIF2ISP_accept: Returns the value 1 if the ISP can accept an
0h acknowledge token from the FIFO between the primary input formatter acknowledge
3
RO port and the ISP. Returns the value 0 if the ISP cannot accept a token on this ISP input
port.

Intel® Atom™ Processor E3800 Product Family

Datasheet 959
 MIPI-Camera Serial Interface (CSI) & ISP

Bit Default &

Description
Range Access

ISP_STR_MON_PIF2ISP_valid: Returns the value 1 if a valid acknowledge token

0h from the FIFO between the primary input formatter acknowledge port and the ISP, is
2
RO present on the primary input formatter input port of the ISP. Returns the value 0 if there
is no valid acknowledge token available on this ISP input port.

0h ISP_STR_MON_ISP2PIF_accept: Returns the value 1 if the command FIFO between

1 ISP and the Primary input formatter can accept a command from the ISP. Returns the
RO value 0 if this command FIFO is full.

0h ISP_STR_MON_ISP2PIF_valid: Returns the value 1 if ISP sends a command using

0 the streaming port connected to the Primary Input Formatter command FIFO. Returns
RO the value 0 if the ISP does not send a command to the Primary Input formatter

15.8.8 reg_gpd_gp_reg_reg_gp_mod_stream_stat_type
(gpd_gp_reg_reg_gp_mod_stream_stat)—Offset 1Ch
Indicate the status of the streaming ports of the modules. All module's valid and accept
ports used for control are reflected in this register.

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) gpd_gp_reg_reg_gp_mod_stream_stat: [ISPMMADR] + 1Ch

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: AA88A222h
31 28 24 20 16 12 8 4 0

1 0 1 0 1 0 1 0 1 0 0 0 1 0 0 0 1 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0

MOD_STR_MON_SIF2SP_valid
MOD_STR_MON_DMA2SP_valid

MOD_STR_MON_SP2MC_accept

MOD_STR_MON_CELLS2PIFB_accept
MOD_STR_MON_GDC22CELLS_valid

MOD_STR_MON_SP2DMA_valid

MOD_STR_MON_SP2SIF_valid

MOD_STR_MON_CELLS2PIFB_valid
MOD_STR_MON_PIFB2CELLS_accept
MOD_STR_MON_GDC12CELLS_valid
MOD_STR_MON_SP2DMA_accept

MOD_STR_MON_DMA2SP_accept

MOD_STR_MON_ISP2DMA_valid

MOD_STR_MON_DMA2ISP_valid

MOD_STR_MON_MC2SP_valid

MOD_STR_MON_PIFB2CELLS_valid

MOD_STR_MON_PIFA2CELLS_accept
MOD_STR_MON_PIFA2CELLS_valid
MOD_STR_MON_CELLS2GDC2_accept
MOD_STR_MON_CELLS2GDC2_valid
MOD_STR_MON_GDC22CELLS_accept

MOD_STR_MON_CELLS2GDC1_accept
MOD_STR_MON_CELLS2GDC1_valid
MOD_STR_MON_GDC12CELLS_accept

MOD_STR_MON_SP2SIF_accept

MOD_STR_MON_SIF2SP_accept

MOD_STR_MON_CELLS2PIFA_valid
MOD_STR_MON_SP2MC_valid
MOD_STR_MON_MC2SP_accept
MOD_STR_MON_ISP2DMA_accept

MOD_STR_MON_DMA2ISP_accept

MOD_STR_MON_CELLS2PIFA_accept

Bit Default &

Description
Range Access

1h MOD_STR_MON_CELLS2GDC2_accept: Returns the value 1 if the acknowledge FIFO

31 between GDC2 and ISP/SP can accept an acknowledge token from GDC2. Returns the
RO value 0 if this FIFO is full.

0h MOD_STR_MON_CELLS2GDC2_valid: Returns the value 1 if GDC2 sends an

30 acknowledge token using the streaming port connected to the acknowledge FIFO to the
RO ISP/SP. Returns the value 0 if GDC2 does not send an acknowledge token to this FIFO.

1h MOD_STR_MON_GDC22CELLS_accept: Returns the value 1 if GDC2 can accept a

29 command token from the command FIFO between the ISP/SP and GDC2. Returns the
RO value 0 if GDC2 cannot accept a command token.

Intel® Atom™ Processor E3800 Product Family

960 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

Bit Default &

Description
Range Access

0h MOD_STR_MON_GDC22CELLS_valid: Returns the value 1 if there is a command

28 available on the command fifo between SP/ISP and GDC2. Returns the value 0 if the
RO command FIFO for GDC2 is empty.

1h MOD_STR_MON_CELLS2GDC1_accept: Returns the value 1 if the acknowledge FIFO

27 between GDC1 and ISP/SP can accept an acknowledge token from GDC1. Returns the
RO value 0 if this FIFO is full.

0h MOD_STR_MON_CELLS2GDC1_valid: Returns the value 1 if GDC1 sends an

26 acknowledge token using the streaming port connected to the acknowledge FIFO to the
RO ISP/SP. Returns the value 0 if GDC1 does not send an acknowledge token to this FIFO.

1h MOD_STR_MON_GDC12CELLS_accept: Returns the value 1 if GDC1 can accept a

25 command token from the command FIFO between the ISP/SP and GDC1. Returns the
RO value 0 if GDC1 cannot accept a command token.

0h MOD_STR_MON_GDC12CELLS_valid: Returns the value 1 if there is a command

24 available on the command fifo between SP/ISP and GDC1. Returns the value 0 if the
RO command FIFO for GDC1 is empty.

1h MOD_STR_MON_SP2DMA_accept: Returns the value 1 if the acknowledge FIFO

23 between the DMA and SP can accept an acknowledge token from the DMA. Returns the
RO value 0 if this FIFO is full.

0h MOD_STR_MON_SP2DMA_valid: Returns the value 1 if DMA sends an acknowledge

22 token using the streaming port connected to the acknowledge FIFO to the SP. Returns
RO the value 0 if the DMA does not send an acknowledge token to this FIFO.

0h MOD_STR_MON_DMA2SP_accept: Returns the value 1 if the DMA can accept a

21 command token from the command FIFO between the SP and the DMA. Returns the
RO value 0 if the DMA cannot accept a command token.

0h MOD_STR_MON_DMA2SP_valid: Returns the value 1 if there is a command available

20 on the command fifo between SP and the DMA. Returns the value 0 if the command
RO FIFO for the DMA is empty.

1h MOD_STR_MON_ISP2DMA_accept: Returns the value 1 if the acknowledge FIFO

19 between the DMA and ISP can accept an acknowledge token from the DMA. Returns the
RO value 0 if this FIFO is full.

0h MOD_STR_MON_ISP2DMA_valid: Returns the value 1 if DMA sends an acknowledge

18 token using the streaming port connected to the acknowledge FIFO to the ISP. Returns
RO the value 0 if the DMA does not send an acknowledge token to this FIFO.

0h MOD_STR_MON_DMA2ISP_accept: Returns the value 1 if the DMA can accept a

17 command token from the command FIFO between the SP and the DMA. Returns the
RO value 0 if the DMA cannot accept a command token.

0h MOD_STR_MON_DMA2ISP_valid: Returns the value 1 if there is a command

16 available on the command fifo between ISP and the DMA. Returns the value 0 if the
RO command FIFO for the DMA is empty.

1h MOD_STR_MON_SP2MC_accept: Returns the value 1 if stream2mem can accept a

15 command token from the command FIFO between the SP and the stream2mem.
RO Returns the value 0 if stream2mem cannot accept a command token.

0h MOD_STR_MON_SP2MC_valid: Returns the value 1 if there is a command available

14 on the command fifo between the SP and the stream2mem. Returns the value 0 if the
RO command FIFO for the stream2mem is empty.

1h MOD_STR_MON_MC2SP_accept: Returns the value 1 if the acknowledge FIFO

13 between the stream2mem and the SP can accept an acknowledge token from the
RO stream2mem. Returns the value 0 if this FIFO is full.
MOD_STR_MON_MC2SP_valid: Returns the value 1 if the stream2mem sends an
0h acknowledge token using its acknowledge output port connected to the acknowledge
12
RO FIFO between the stream2mem and the SP. Returns the value 0 if the stream2mem
does not send an acknowledge token to this FIFO.

0h MOD_STR_MON_SP2SIF_accept: Returns the value 1 if secondary input formatter

11 can accept a command token from the command FIFO between the SP and the
RO secondary input formatter. Returns the value 0 if this FIFO is full.

Intel® Atom™ Processor E3800 Product Family

Datasheet 961
 MIPI-Camera Serial Interface (CSI) & ISP

Bit Default &

Description
Range Access

0h MOD_STR_MON_SP2SIF_valid: Returns the value 1 if there is a command available

10 on the command fifo between the SP and the secondary input formatter. Returns the
RO value 0 if the command FIFO for the secondary input formatter is empty.

1h MOD_STR_MON_SIF2SP_accept: Returns the value 1 if the acknowledge FIFO

9 between the secondary input formatter and the SP can accept an acknowledge token
RO from the secondary input formatter. Returns the value 0 if this FIFO is full.
MOD_STR_MON_SIF2SP_valid: Returns the value 1 if the secondary input formatter
0h sends an acknowledge token using its acknowledge output port connected to the
8
RO acknowledge FIFO between the secondary input formatter and the SP. Returns the value
0 if the secondary input formatter does not send an acknowledge token to this FIFO.
MOD_STR_MON_CELLS2PIFB_accept: Returns the value 1 if primary input formatter
0h B can accept a command token from the command FIFO between the ISP/SP and the
7
RO primary input formatter B. Returns the value 0 if the primary input formatter B cannot
accept a command token.

0h MOD_STR_MON_CELLS2PIFB_valid: Returns the value 1 if there is a command

6 available on the command fifo between SP/ISP and the primary input formatter B.
RO Returns the value 0 if the command FIFO for the primary input formatter B is empty.

MOD_STR_MON_PIFB2CELLS_accept: Returns the value 1 if the acknowledge FIFO

1h between the primary input formatter B and the ISP/SP can accept an acknowledge
5
RO token from the primary input formatter B. Returns the value 0 if this command FIFO is
full.
MOD_STR_MON_PIFB2CELLS_valid: Returns the value 1 if primary input formatter
0h B sends an acknowledge token using the streaming port connected to the acknowledge
4
RO FIFO to the ISP/SP. Returns the value 0 if the primary input formatter B does not send
an acknowledge token to this FIFO.
MOD_STR_MON_CELLS2PIFA_accept: Returns the value 1 if primary input
0h formatter A can accept a command token from the command FIFO between the ISP/SP
3
RO and the primary input formatter A. Returns the value 0 if the primary input formatter A
cannot accept a command token.

0h MOD_STR_MON_CELLS2PIFA_valid: Returns the value 1 if there is a command

2 available on the command fifo between SP/ISP and the primary input formatter A.
RO Returns the value 0 if the command FIFO for the primary input formatter A is empty.

MOD_STR_MON_PIFA2CELLS_accept: Returns the value 1 if the acknowledge FIFO

1h between the primary input formatter A and the ISP/SP can accept an acknowledge
1
RO token from the primary input formatter A. Returns the value 0 if this command FIFO is
full.
MOD_STR_MON_PIFA2CELLS_valid: Returns the value 1 if primary input formatter
0h A sends an acknowledge token using the streaming port connected to the acknowledge
0
RO FIFO to the ISP/SP. Returns the value 0 if the primary input formatter A does not send
an acknowledge token to this FIFO.

15.8.9 reg_gpd_gp_reg_reg_gp_sp_stream_stat_irq_cond_type
(gpd_gp_reg_reg_gp_sp_stream_stat_irq_cond)—Offset 20h
Access Method
Type: Memory Mapped I/O Register gpd_gp_reg_reg_gp_sp_stream_stat_irq_cond:
(Size: 32 bits) [ISPMMADR] + 20h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h

Intel® Atom™ Processor E3800 Product Family

962 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

reg_gp_sp_stream_stat_irq_cond
Bit Default &
Description
Range Access

0h reg_gp_sp_stream_stat_irq_cond: This register indicates which condition of the SP

31:0
RW streaming ports will enable the SP streaming stat irq output

15.8.10 reg_gpd_gp_reg_reg_gp_sp_stream_stat_b_irq_cond_type
(gpd_gp_reg_reg_gp_sp_stream_stat_b_irq_cond)—Offset
24h
Access Method
Type: Memory Mapped I/O Register gpd_gp_reg_reg_gp_sp_stream_stat_b_irq_cond:
(Size: 32 bits) [ISPMMADR] + 24h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_reg_gp_sp_stream_stat_b_irq_cond

reg_gp_sp_stream_stat_b_irq_cond

Intel® Atom™ Processor E3800 Product Family

Datasheet 963
 MIPI-Camera Serial Interface (CSI) & ISP

Bit Default &

Description
Range Access

0h
31:8 unused_reg_gp_sp_stream_stat_b_irq_cond: Unused
RW
0h reg_gp_sp_stream_stat_b_irq_cond: This register indicates which condition of the
7:0
RW SP streaming ports b will enable the SP streaming stat b irq output

15.8.11 reg_gpd_gp_reg_reg_gp_isp_stream_stat_irq_cond_type
(gpd_gp_reg_reg_gp_isp_stream_stat_irq_cond)—Offset 28h
Access Method
Type: Memory Mapped I/O Register gpd_gp_reg_reg_gp_isp_stream_stat_irq_cond:
(Size: 32 bits) [ISPMMADR] + 28h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_reg_gp_isp_stream_stat_irq_cond

reg_gp_isp_stream_stat_irq_cond

Bit Default &

Description
Range Access

0h
31:28 unused_reg_gp_isp_stream_stat_irq_cond: Unused
RW
0h reg_gp_isp_stream_stat_irq_cond: This register indicates which condition of the
27:0
RW ISP streaming ports will enable the ISP streaming stat irq output

15.8.12 reg_gpd_gp_reg_reg_gp_mod_stream_stat_irq_cond_type
(gpd_gp_reg_reg_gp_mod_stream_stat_irq_cond)—Offset 2Ch
Access Method
Type: Memory Mapped I/O Register gpd_gp_reg_reg_gp_mod_stream_stat_irq_cond:
(Size: 32 bits) [ISPMMADR] + 2Ch

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Intel® Atom™ Processor E3800 Product Family

964 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

reg_gp_mod_stream_stat_irq_cond
Bit Default &
Description
Range Access

0h reg_gp_mod_stream_stat_irq_cond: This register indicates which condition of the

31:0
RW MOD streaming ports will enable the MOD streaming stat irq output

15.8.13 reg_gpd_gp_reg_reg_gp_sp_stream_stat_irq_enable_type
(gpd_gp_reg_reg_gp_sp_stream_stat_irq_enable)—Offset 30h
Access Method
Type: Memory Mapped I/O Register gpd_gp_reg_reg_gp_sp_stream_stat_irq_enable:
(Size: 32 bits) [ISPMMADR] + 30h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
reg_gp_sp_stream_stat_irq_enable
unused_reg_gp_sp_stream_stat_irq_enable

Intel® Atom™ Processor E3800 Product Family

Datasheet 965
 MIPI-Camera Serial Interface (CSI) & ISP

Bit Default &

Description
Range Access

0h
31:16 unused_reg_gp_sp_stream_stat_irq_enable: Unused
RW
0h reg_gp_sp_stream_stat_irq_enable: This register enables the SP streaming stat irq
15:0
RW output for each of the 16 ports

15.8.14 reg_gpd_gp_reg_reg_gp_sp_stream_stat_b_irq_enable_type
(gpd_gp_reg_reg_gp_sp_stream_stat_b_irq_enable)—Offset
34h
Access Method
Type: Memory Mapped I/O Register gpd_gp_reg_reg_gp_sp_stream_stat_b_irq_enable:
(Size: 32 bits) [ISPMMADR] + 34h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_reg_gp_sp_stream_stat_b_irq_enable

reg_gp_sp_stream_stat_b_irq_enable

Bit Default &

Description
Range Access

0h
31:4 unused_reg_gp_sp_stream_stat_b_irq_enable: Unused
RW

0h reg_gp_sp_stream_stat_b_irq_enable: This register enables the SP streaming stat

3:0
RW b irq output for each of the 4 ports

15.8.15 reg_gpd_gp_reg_reg_gp_isp_stream_stat_irq_enable_type
(gpd_gp_reg_reg_gp_isp_stream_stat_irq_enable)—Offset
38h
Access Method

Intel® Atom™ Processor E3800 Product Family

966 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

Type: Memory Mapped I/O Register gpd_gp_reg_reg_gp_isp_stream_stat_irq_enable:

(Size: 32 bits) [ISPMMADR] + 38h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

unused_reg_gp_isp_stream_stat_irq_enable

reg_gp_isp_stream_stat_irq_enable
Bit Default &
Description
Range Access

0h
31:14 unused_reg_gp_isp_stream_stat_irq_enable: Unused
RW

0h reg_gp_isp_stream_stat_irq_enable: This register enables the ISP streaming stat

13:0
RW irq output for each of the 14 ports

15.8.16 reg_gpd_gp_reg_reg_gp_mod_stream_stat_irq_enable_type
(gpd_gp_reg_reg_gp_mod_stream_stat_irq_enable)—Offset
3Ch
Access Method
Type: Memory Mapped I/O Register gpd_gp_reg_reg_gp_mod_stream_stat_irq_enable:
(Size: 32 bits) [ISPMMADR] + 3Ch

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h

Intel® Atom™ Processor E3800 Product Family

Datasheet 967
 MIPI-Camera Serial Interface (CSI) & ISP

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

unused_reg_gp_mod_stream_stat_irq_enable

reg_gp_mod_stream_stat_irq_enable
Bit Default &
Description
Range Access

0h
31:16 unused_reg_gp_mod_stream_stat_irq_enable: Unused
RW

0h reg_gp_mod_stream_stat_irq_enable: This register enables the MOD streaming

15:0
RW stat irq output for each of the 16 ports

15.8.17 reg_gpd_gp_reg_reg_gp_switch_if_type
(gpd_gp_reg_reg_gp_switch_if)—Offset 40h
Access Method
Type: Memory Mapped I/O Register
gpd_gp_reg_reg_gp_switch_if: [ISPMMADR] + 40h
(Size: 32 bits)
ISPMMADR Type: PCI Configuration Register (Size: 32 bits)
ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_reg_gp_switch_if

reg_gp_switch_if

Bit Default &

Description
Range Access

0h
31:1 unused_reg_gp_switch_if: Unused
RW

Intel® Atom™ Processor E3800 Product Family

968 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

Bit Default &

Description
Range Access

0h reg_gp_switch_if: Selects the control stream switch for the primary input formatter
0 and for primary input formatter b. The input formatters can be controlled by the scalar
RW processor (value=1) or by the ISP (value=0)

15.8.18 reg_gpd_gp_reg_reg_gp_switch_gdc1_type
(gpd_gp_reg_reg_gp_switch_gdc1)—Offset 44h
Access Method
Type: Memory Mapped I/O Register
gpd_gp_reg_reg_gp_switch_gdc1: [ISPMMADR] + 44h
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

unused_reg_gp_switch_gdc1

reg_gp_switch_gdc1
Bit Default &
Description
Range Access

0h
31:1 unused_reg_gp_switch_gdc1: Unused
RW
0h reg_gp_switch_gdc1: Selects the control stream switch for the GDC1. GDC1 can be
0
RW controlled by the scalar processor (value=1) or the ISP (value=0)

15.8.19 reg_gpd_gp_reg_reg_gp_switch_gdc2_type
(gpd_gp_reg_reg_gp_switch_gdc2)—Offset 48h
Access Method
Type: Memory Mapped I/O Register gpd_gp_reg_reg_gp_switch_gdc2: [ISPMMADR] + 48h
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h

Intel® Atom™ Processor E3800 Product Family

Datasheet 969
 MIPI-Camera Serial Interface (CSI) & ISP

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

unused_reg_gp_switch_gdc2

reg_gp_switch_gdc2
Bit Default &
Description
Range Access

0h
31:1 unused_reg_gp_switch_gdc2: Unused
RW

0h reg_gp_switch_gdc2: Selects the control stream switch for the GDC2. GDC2 can be
0
RW controlled by the scalar processor (value=1) or the ISP (value=0)

15.8.20 reg_gpd_gp_reg_reg_gp_srst_type
(gpd_gp_reg_reg_gp_srst)—Offset 4Ch
Soft reset for several modules in the system. If '1' is written to a bit, the module(s)
connected to that bit are held in reset until a '0' is written to that bit.

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) gpd_gp_reg_reg_gp_srst: [ISPMMADR] + 4Ch

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SRST_SF_ISYS_SP

SRST_IFMT_CBUS
SRST_ISEL_CBUS
SRST_ISYS_CBUS
SRST_SF_GDC2_CELLS
SRST_SF_GDC1_CELLS
SRST_SF_DMA_CELLS

SRST_SF_PIF_CELLS

SRST_DMA
SRST_WBUS
SRST_HOST12BUS
SRST_NBUS

SRST_SLV_GRP_BUS

SRST_FACELLFIFOS
SRST_VEC_BUS
SRST_OCP2CIO

SRST_SF_ISP_SP

SRST_ISP

SRST_IFT_SEC_PIPE
SRST_OSYS

SRST_TC

SRST_GPDEV_CBUS
unused_reg_gp_srst

SRST_SP

SRST_SF_MC_SP
SRST_SF_SIF_SP

SRST_GPIO
SRST_GDC2
SRST_GDC1

SRST_GPTIMER

Bit Default &

Description
Range Access

0h
31:29 unused_reg_gp_srst: Unused
RW

0h
28 SRST_WBUS: soft reset bit for the wide bus
RW

Intel® Atom™ Processor E3800 Product Family

970 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

Bit Default &

Description
Range Access

0h
27 SRST_HOST12BUS: soft reset bit for the bus from host to fifo adapters
RW
0h
26 SRST_NBUS: soft reset bit for the narrow bus
RW
0h
25 SRST_OCP2CIO: soft reset bit for the OCP2CIO converter
RW
0h
24 SRST_SP: soft reset bit for the SP
RW
0h
23 SRST_SF_GDC2_CELLS: soft reset bit for the FIFOs between the GDC2 and the cells
RW
0h
22 SRST_SF_GDC1_CELLS: soft reset bit for the FIFOs between the GDC1 and the cells
RW
0h
21 SRST_SF_DMA_CELLS: soft reset bit for the FIFOs between the DMA and the cells
RW
0h
20 SRST_SF_ISYS_SP: soft reset bit for the FIFOs between the input system and the SP
RW
0h
19 SRST_SF_MC_SP: soft reset bit for the FIFOs between the stream2memory and the SP
RW
0h SRST_SF_SIF_SP: soft reset bit for the FIFOs between the secondary input formatter
18
RW and the SP

0h SRST_SF_PIF_CELLS: soft reset bit for the FIFOs between the primary input
17
RW formatters and the cells

0h
16 SRST_SF_ISP_SP: soft reset bit for the FIFOs between SP and ISP
RW
0h
15 SRST_DMA: soft reset bit for the DMA
RW
0h
14 SRST_SLV_GRP_BUS: soft reset bit for the slave group bus
RW
0h
13 SRST_ISP: soft reset bit for the isp (vector processor)
RW
0h
12 SRST_VEC_BUS: soft reset bit for the vector bus
RW
0h
11 SRST_GDC2: soft reset bit for the GDC2 block
RW
0h
10 SRST_GDC1: soft reset bit for the GDC1 block
RW
0h SRST_IFT_SEC_PIPE: soft reset bit for the CIO pipeline after the secondary input
9
RW formatter

0h
8 SRST_OSYS: soft reset bit for the blocks in the output system cluster
RW
0h SRST_FACELLFIFOS: soft reset bit for the fifo's connected to the fifo adapter between
7
RW host and cells

0h
6 SRST_GPTIMER: soft reset bit for the GP timer block
RW
0h
5 SRST_TC: soft reset bit for the timed controller block
RW

Intel® Atom™ Processor E3800 Product Family

Datasheet 971
 MIPI-Camera Serial Interface (CSI) & ISP

Bit Default &

Description
Range Access

0h
4 SRST_GPIO: soft reset bit for the gpio block
RW
0h
3 SRST_GPDEV_CBUS: soft reset bit for the gp devices cluster control bus
RW
0h
2 SRST_IFMT_CBUS: soft reset bit for the input formatting cluster control bus
RW
0h
1 SRST_ISEL_CBUS: soft reset bit for the input selector cluster control bus
RW
0h
0 SRST_ISYS_CBUS: soft reset bit for the input system control bus
RW

15.8.21 reg_gpd_gp_reg_reg_gp_slv_reg_srst_type
(gpd_gp_reg_reg_gp_slv_reg_srst)—Offset 50h
Soft reset for the slave accessible registers in some blocks. If '1' is written to a bit, the
attached registers get their default value. They can only be overwritten after writing a
'0' to this bit

Access Method
Type: Memory Mapped I/O Register gpd_gp_reg_reg_gp_slv_reg_srst: [ISPMMADR] + 50h
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SLV_REG_SRST_GDC2
SLV_REG_SRST_GDC1
unused_reg_gp_slv_reg_srst

SLV_REG_SRST_DMA

Bit Default &

Description
Range Access

0h
31:3 unused_reg_gp_slv_reg_srst: Unused
RW
0h
2 SLV_REG_SRST_GDC2: soft reset bit for the slave registers in the GDC2
RW
0h
1 SLV_REG_SRST_GDC1: soft reset bit for the slave registers in the GDC1
RW
0h
0 SLV_REG_SRST_DMA: soft reset bit for the slave registers in the DMA
RW

Intel® Atom™ Processor E3800 Product Family

972 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

15.8.22 reg_gpd_tc_FifoWriteCmd_type (gpd_tc_FifoWriteCmd)—

Offset 100h
Access Method
Type: Memory Mapped I/O Register
gpd_tc_FifoWriteCmd: [ISPMMADR] + 100h
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FifoWriteCmd
Bit Default &
Description
Range Access

0h FifoWriteCmd: Timed controller Command input. A Timed Controller command

31:0
WO consists of 5 32-bit tokens that need to be written sequentially to this register location

15.8.23 reg_gpd_c_gpio_reg_gpio_doe_type
(gpd_c_gpio_reg_gpio_doe)—Offset 400h
Access Method
Type: Memory Mapped I/O Register gpd_c_gpio_reg_gpio_doe: [ISPMMADR] + 400h
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_reg_gpio_doe

reg_gpio_doe

Bit Default &

Description
Range Access

0h
31:12 unused_reg_gpio_doe: Unused
RW

0h reg_gpio_doe: indicates for each bit whether it is intended to be an input (value='0')

11:0
RW or an output (value='1')

Intel® Atom™ Processor E3800 Product Family

Datasheet 973
 MIPI-Camera Serial Interface (CSI) & ISP

15.8.24 reg_gpd_c_gpio_reg_gpio_do_select_type
(gpd_c_gpio_reg_gpio_do_select)—Offset 404h
Access Method
Type: Memory Mapped I/O Register
gpd_c_gpio_reg_gpio_do_select: [ISPMMADR] + 404h
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

unused_reg_gpio_do_select

reg_gpio_do_select
Bit Default &
Description
Range Access

0h
31:12 unused_reg_gpio_do_select: Unused
RW
0h reg_gpio_do_select: indicates for each bit of gpio_do whether it should have the
11:0
RW value from source 0 (value='0') or source 1 (value='1').

15.8.25 reg_gpd_c_gpio_reg_gpio_do_0_type
(gpd_c_gpio_reg_gpio_do_0)—Offset 408h
Access Method
Type: Memory Mapped I/O Register gpd_c_gpio_reg_gpio_do_0: [ISPMMADR] + 408h
(Size: 32 bits)
ISPMMADR Type: PCI Configuration Register (Size: 32 bits)
ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_reg_gpio_do_0

reg_gpio_do_0

Intel® Atom™ Processor E3800 Product Family

974 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

Bit Default &

Description
Range Access

0h
31:12 unused_reg_gpio_do_0: Unused
RW
0h
11:0 reg_gpio_do_0: provides the value for each of the output bits (source 0)
RW

15.8.26 reg_gpd_c_gpio_reg_gpio_do_1_type
(gpd_c_gpio_reg_gpio_do_1)—Offset 40Ch
Access Method
Type: Memory Mapped I/O Register
gpd_c_gpio_reg_gpio_do_1: [ISPMMADR] + 40Ch
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_reg_gpio_do_1

reg_gpio_do_1
Bit Default &
Description
Range Access

0h
31:12 unused_reg_gpio_do_1: Unused
RW

0h
11:0 reg_gpio_do_1: provides the value for each of the output bits (source 1)
RW

15.8.27 reg_gpd_c_gpio_reg_gpio_do_pwm_cnt_0_type
(gpd_c_gpio_reg_gpio_do_pwm_cnt_0)—Offset 410h
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) gpd_c_gpio_reg_gpio_do_pwm_cnt_0: [ISPMMADR] + 410h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h

Intel® Atom™ Processor E3800 Product Family

Datasheet 975
 MIPI-Camera Serial Interface (CSI) & ISP

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

unused_reg_gpio_do_pwm_cnt_0

reg_gpio_do_pwm_cnt_0
Bit Default &
Description
Range Access

0h
31:6 unused_reg_gpio_do_pwm_cnt_0: Unused
RW
0h reg_gpio_do_pwm_cnt_0: indicates duty cycle for PWM output 0. value d means
5:0
RW duty cycle d/64

15.8.28 reg_gpd_c_gpio_reg_gpio_do_pwm_cnt_1_type
(gpd_c_gpio_reg_gpio_do_pwm_cnt_1)—Offset 414h
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) gpd_c_gpio_reg_gpio_do_pwm_cnt_1: [ISPMMADR] + 414h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_reg_gpio_do_pwm_cnt_1

reg_gpio_do_pwm_cnt_1

Bit Default &

Description
Range Access

0h
31:6 unused_reg_gpio_do_pwm_cnt_1: Unused
RW

Intel® Atom™ Processor E3800 Product Family

976 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

Bit Default &

Description
Range Access

0h reg_gpio_do_pwm_cnt_1: indicates duty cycle for PWM output 1. value d means

5:0
RW duty cycle d/64

15.8.29 reg_gpd_c_gpio_reg_gpio_do_pwm_cnt_2_type
(gpd_c_gpio_reg_gpio_do_pwm_cnt_2)—Offset 418h
Access Method
Type: Memory Mapped I/O Register
gpd_c_gpio_reg_gpio_do_pwm_cnt_2: [ISPMMADR] + 418h
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_reg_gpio_do_pwm_cnt_2

reg_gpio_do_pwm_cnt_2
Bit Default &
Description
Range Access

0h
31:6 unused_reg_gpio_do_pwm_cnt_2: Unused
RW

0h reg_gpio_do_pwm_cnt_2: indicates duty cycle for PWM output 2. value d means

5:0
RW duty cycle d/64

15.8.30 reg_gpd_c_gpio_reg_gpio_do_pwm_cnt_3_type
(gpd_c_gpio_reg_gpio_do_pwm_cnt_3)—Offset 41Ch
Access Method
Type: Memory Mapped I/O Register
gpd_c_gpio_reg_gpio_do_pwm_cnt_3: [ISPMMADR] + 41Ch
(Size: 32 bits)
ISPMMADR Type: PCI Configuration Register (Size: 32 bits)
ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h

Intel® Atom™ Processor E3800 Product Family

Datasheet 977
 MIPI-Camera Serial Interface (CSI) & ISP

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

unused_reg_gpio_do_pwm_cnt_3

reg_gpio_do_pwm_cnt_3
Bit Default &
Description
Range Access

0h
31:6 unused_reg_gpio_do_pwm_cnt_3: Unused
RW
0h reg_gpio_do_pwm_cnt_3: indicates duty cycle for PWM output 3. value d means
5:0
RW duty cycle d/64

15.8.31 reg_gpd_c_gpio_reg_gpio_do_pwm_main_cnt_type
(gpd_c_gpio_reg_gpio_do_pwm_main_cnt)—Offset 420h
Access Method
Type: Memory Mapped I/O Register gpd_c_gpio_reg_gpio_do_pwm_main_cnt: [ISPMMADR] +
(Size: 32 bits) 420h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_reg_gpio_do_pwm_main_cnt

reg_gpio_do_pwm_main_cnt

Bit Default &

Description
Range Access

0h
31:20 unused_reg_gpio_do_pwm_main_cnt: Unused
RW

Intel® Atom™ Processor E3800 Product Family

978 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

Bit Default &

Description
Range Access

0h
19:0 reg_gpio_do_pwm_main_cnt: indicates wrapping value for PWM main counter
RW

15.8.32 reg_gpd_c_gpio_reg_gpio_do_pwm_enable_type
(gpd_c_gpio_reg_gpio_do_pwm_enable)—Offset 424h
Access Method
Type: Memory Mapped I/O Register
gpd_c_gpio_reg_gpio_do_pwm_enable: [ISPMMADR] + 424h
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_reg_gpio_do_pwm_enable

reg_gpio_do_pwm_enable
Bit Default &
Description
Range Access

0h
31:12 unused_reg_gpio_do_pwm_enable: Unused
RW

0h reg_gpio_do_pwm_enable: indicates per bit whether PWM is on (value='1') or

11:0
RW output is fixed '0' (value='0')

15.8.33 reg_gpd_c_gpio_reg_gpio_di_debouncemethod_type
(gpd_c_gpio_reg_gpio_di_debouncemethod)—Offset 428h
Access Method
Type: Memory Mapped I/O Register gpd_c_gpio_reg_gpio_di_debouncemethod: [ISPMMADR] +
(Size: 32 bits) 428h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h

Intel® Atom™ Processor E3800 Product Family

Datasheet 979
 MIPI-Camera Serial Interface (CSI) & ISP

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

unused_reg_gpio_di_debouncemethod

reg_gpio_di_debouncemethod
Bit Default &
Description
Range Access

0h
31:24 unused_reg_gpio_di_debouncemethod: Unused
RW

0h reg_gpio_di_debouncemethod: indicates for each input bit which debouncing

23:0 counter value is chosen: '00': debounce_cnt0, '01': debounce_cnt1, '10':
RW debounce_cnt2, '11': debounce_cnt3'

15.8.34 reg_gpd_c_gpio_reg_gpio_di_debounce_cnt0_type
(gpd_c_gpio_reg_gpio_di_debounce_cnt0)—Offset 42Ch
Access Method
Type: Memory Mapped I/O Register gpd_c_gpio_reg_gpio_di_debounce_cnt0: [ISPMMADR] +
(Size: 32 bits) 42Ch

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
reg_gpio_di_debounce_cnt0

Bit Default &

Description
Range Access

0h reg_gpio_di_debounce_cnt0: Indicates the period an input has to be stable before

31:0
RW passing its value to the output*

Intel® Atom™ Processor E3800 Product Family

980 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

15.8.35 reg_gpd_c_gpio_reg_gpio_di_debounce_cnt1_type
(gpd_c_gpio_reg_gpio_di_debounce_cnt1)—Offset 430h
Access Method
Type: Memory Mapped I/O Register gpd_c_gpio_reg_gpio_di_debounce_cnt1: [ISPMMADR] +
(Size: 32 bits) 430h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

reg_gpio_di_debounce_cnt1

Bit Default &

Description
Range Access

0h reg_gpio_di_debounce_cnt1: Indicates the period an input has to be stable before

31:0
RW passing its value to the output*

15.8.36 reg_gpd_c_gpio_reg_gpio_di_debounce_cnt2_type
(gpd_c_gpio_reg_gpio_di_debounce_cnt2)—Offset 434h
Access Method
Type: Memory Mapped I/O Register gpd_c_gpio_reg_gpio_di_debounce_cnt2: [ISPMMADR] +
(Size: 32 bits) 434h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
reg_gpio_di_debounce_cnt2

Intel® Atom™ Processor E3800 Product Family

Datasheet 981
 MIPI-Camera Serial Interface (CSI) & ISP

Bit Default &

Description
Range Access

0h reg_gpio_di_debounce_cnt2: Indicates the period an input has to be stable before

31:0
RW passing its value to the output

15.8.37 reg_gpd_c_gpio_reg_gpio_di_debounce_cnt3_type
(gpd_c_gpio_reg_gpio_di_debounce_cnt3)—Offset 438h
Access Method
Type: Memory Mapped I/O Register gpd_c_gpio_reg_gpio_di_debounce_cnt3: [ISPMMADR] +
(Size: 32 bits) 438h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

reg_gpio_di_debounce_cnt3

Bit Default &

Description
Range Access

0h reg_gpio_di_debounce_cnt3: Indicates the period an input has to be stable before

31:0
RW passing its value to the output

15.8.38 reg_gpd_c_gpio_reg_gpio_di_activelevel_type
(gpd_c_gpio_reg_gpio_di_activelevel)—Offset 43Ch
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) gpd_c_gpio_reg_gpio_di_activelevel: [ISPMMADR] + 43Ch

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000FFFh

Intel® Atom™ Processor E3800 Product Family

982 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1

unused_reg_gpio_di_activelevel

reg_gpio_di_activelevel
Bit Default &
Description
Range Access

0h
31:12 unused_reg_gpio_di_activelevel: Unused
RW
FFFh reg_gpio_di_activelevel: indicates for each bit whether it is intended to be active low
11:0
RW (value='0') or active high (value='1').

15.8.39 reg_gpd_c_gpio_reg_gpio_di_type
(gpd_c_gpio_reg_gpio_di)—Offset 440h
Access Method
Type: Memory Mapped I/O Register gpd_c_gpio_reg_gpio_di: [ISPMMADR] + 440h
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000FFFh
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
unused_reg_gpio_di

reg_gpio_di

Bit Default &

Description
Range Access

0h
31:12 unused_reg_gpio_di: Unused
RW

FFFh
11:0 reg_gpio_di: contains the values of all debounced, active level compensated inputs
RO

Intel® Atom™ Processor E3800 Product Family

Datasheet 983
 MIPI-Camera Serial Interface (CSI) & ISP

15.8.40 reg_gpd_irq_ctrl_reg_irq_edge_type
(gpd_irq_ctrl_reg_irq_edge)—Offset 500h
Access Method
Type: Memory Mapped I/O Register
gpd_irq_ctrl_reg_irq_edge: [ISPMMADR] + 500h
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

reg_irq_edge
Bit Default &
Description
Range Access

0h reg_irq_edge: indicates for each bit whether an interrupt request should be generated
31:0
RW on a falling edge (value='0') or a rising edge (value='1').

15.8.41 reg_gpd_irq_ctrl_reg_irq_mask_type
(gpd_irq_ctrl_reg_irq_mask)—Offset 504h
Access Method
Type: Memory Mapped I/O Register
gpd_irq_ctrl_reg_irq_mask: [ISPMMADR] + 504h
(Size: 32 bits)
ISPMMADR Type: PCI Configuration Register (Size: 32 bits)
ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
reg_irq_mask

Bit Default &

Description
Range Access

0h reg_irq_mask: indicates for each bit of irq_di whether it can generate an interrupt
31:0 request (value='1') or not (value='0'). Setting will affect reg_irq_value as well as IRQ
RW output pin

15.8.42 reg_gpd_irq_ctrl_reg_irq_status_type
(gpd_irq_ctrl_reg_irq_status)—Offset 508h
Indicates for each bit whether a non-masked interrupt has been generated (value='1').
Can be cleared by writing a '1' into the the corresponding bit of the req_irq_clear
register.

Intel® Atom™ Processor E3800 Product Family

984 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

Access Method
Type: Memory Mapped I/O Register
gpd_irq_ctrl_reg_irq_status: [ISPMMADR] + 508h
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IRQ_STAT_ISP
IRQ_STAT_SW_1
IRQ_STAT_SW_0

IRQ_STAT_ISYS_2

IRQ_STAT_ISP_DMEM_ERROR
IRQ_STAT_ISP_BAMEM_ERROR

IRQ_STAT_ISP_SMON
IRQ_STAT_SP_SMON
IRQ_STAT_SP_DMEM_ERROR

IRQ_STAT_SP
IRQ_STAT_SP_SMON_B

IRQ_STAT_IFMT
IRQ_STAT_DMA

IRQ_STAT_MOD_SMON

IRQ_STAT_ISYS
IRQ_STAT_SP_IMEM_ERROR
IRQ_STAT_GPTIMER_1
IRQ_STAT_GPTIMER_0

IRQ_STAT_ISP_PMEM_ERROR

IRQ_STAT_ISEL

IRQ_STAT_GPIO_PINS
Bit Default &
Description
Range Access

0h IRQ_STAT_SP_SMON_B: Represents the irq status of the irq_out from the SP

31
RO streaming monitor b

0h
30 IRQ_STAT_DMA: Represents the irq status of the DMA
RO
0h
29 IRQ_STAT_SW_1: Represents the irq status of the GP register IRQ SW 1
RO
0h
28 IRQ_STAT_SW_0: Represents the irq status of the GP register IRQ SW 0
RO
0h IRQ_STAT_GPTIMER_1: Represents the irq status of the irq[1] out signal from the GP
27
RO Timer block

0h IRQ_STAT_GPTIMER_0: Represents the irq status of the irq[0] out signal from the GP
26
RO Timer block

0h IRQ_STAT_ISYS_2: Represents the irq status of the irq out signal from the input
25
RO system

0h IRQ_STAT_SP_DMEM_ERROR: Represents the irq status of the error signal from the
24
RO SP data memory

0h IRQ_STAT_SP_IMEM_ERROR: Represents the irq status of the error signal from the
23
RO SP instruction cache memory

0h IRQ_STAT_ISP_DMEM_ERROR: Represents the irq status of the error signal from the
22
RO ISP data memory

0h IRQ_STAT_ISP_BAMEM_ERROR: Represents the irq status of the error signal from

21
RO the ISP vector memory

0h IRQ_STAT_ISP_PMEM_ERROR: Represents the irq status of the error signal from the
20
RO ISP program memory

0h IRQ_STAT_MOD_SMON: Represents the irq status of the irq_out from the MOD
19
RO streaming monitor

Intel® Atom™ Processor E3800 Product Family

Datasheet 985
 MIPI-Camera Serial Interface (CSI) & ISP

Bit Default &

Description
Range Access

0h IRQ_STAT_ISP_SMON: Represents the irq status of the irq_out from the ISP
18
RO streaming monitor

0h IRQ_STAT_SP_SMON: Represents the irq status of the irq_out from the SP streaming
17
RO monitor

0h IRQ_STAT_IFMT: Represents the irq status of the irq_out from the input formatting
16
RO subsystem

0h
15 IRQ_STAT_ISEL: Represents the irq status of the irq_out from the input selector
RO
0h
14 IRQ_STAT_ISYS: Represents the irq status of the irq_out from the input system
RO
0h
13 IRQ_STAT_ISP: Represents the irq status of the irq_out from isp2300
RO
0h
12 IRQ_STAT_SP: Represents the irq status of the irq_out from scalar processor
RO
0h IRQ_STAT_GPIO_PINS: Represents the irq status of the - potentially debounced -
11:0
RO GPIO input pins

15.8.43 reg_gpd_irq_ctrl_reg_irq_clear_type
(gpd_irq_ctrl_reg_irq_clear)—Offset 50Ch
Access Method
Type: Memory Mapped I/O Register gpd_irq_ctrl_reg_irq_clear: [ISPMMADR] + 50Ch
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
reg_irq_clear

Bit Default &

Description
Range Access

0h reg_irq_clear: Clears (set to '0') bits in reg_irq_status. When writing a '1' into a bit of
31:0 this register, the corresponding bit in the req_irq_status is cleared. When writing a '0'
WO into a bit of this register, the corresponding bit in the req_irq_status is not affected.

15.8.44 reg_gpd_irq_ctrl_reg_irq_enable_type
(gpd_irq_ctrl_reg_irq_enable)—Offset 510h
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) gpd_irq_ctrl_reg_irq_enable: [ISPMMADR] + 510h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Intel® Atom™ Processor E3800 Product Family

986 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

reg_irq_enable
Bit Default &
Description
Range Access

0h reg_irq_enable: Indicates for each bit whether an interrupt cause as monitored by the
31:0
RW req_irq_status register also affects the IRQ pin (value='1') or not (value='0')

15.8.45 reg_gpd_irq_ctrl_reg_irq_level_not_pulse_type
(gpd_irq_ctrl_reg_irq_level_not_pulse)—Offset 514h
Access Method
Type: Memory Mapped I/O Register gpd_irq_ctrl_reg_irq_level_not_pulse: [ISPMMADR] + 514h
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
reg_irq_level_not_pulse

Bit Default &

Description
Range Access

0h reg_irq_level_not_pulse: Indicates for each bit whether an interrupt cause is

31:0
RW translated into a pulse (value='0') or into a constant level '1' (value='1') on the IRQ pin

15.8.46 reg_gpd_irq_ctrl_reg_irq_str_out_enable_type
(gpd_irq_ctrl_reg_irq_str_out_enable)—Offset 518h
Access Method
Type: Memory Mapped I/O Register gpd_irq_ctrl_reg_irq_str_out_enable: [ISPMMADR] + 518h
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h

Intel® Atom™ Processor E3800 Product Family

Datasheet 987
 MIPI-Camera Serial Interface (CSI) & ISP

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

reg_irq_str_out_enable
Bit Default &
Description
Range Access

0h reg_irq_str_out_enable: Indicates for each bit whether an interrupt cause as

31:0 monitored by the req_irq_status register also results in a send token on the irq_str_out
RW port (value='1') or not (value='0')

15.8.47 reg_gpd_gptimer_reg_reset_type (gpd_gptimer_reg_reset)—

Offset 600h
Access Method
Type: Memory Mapped I/O Register gpd_gptimer_reg_reset: [ISPMMADR] + 600h
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_reg_reset

reg_reset

Bit Default &

Description
Range Access

0h
31:8 unused_reg_reset: Unused
RW
0h reg_reset: GP Timer reset. Write '1' to bit x to reset timer x. Write 0xFF to reset all
7:0
WO timers.

15.8.48 reg_gpd_gptimer_overall_enable_type
(gpd_gptimer_overall_enable)—Offset 604h
Access Method
Type: Memory Mapped I/O Register gpd_gptimer_overall_enable: [ISPMMADR] + 604h
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Intel® Atom™ Processor E3800 Product Family

988 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

unused_overall_enable

overall_enable
Bit Default &
Description
Range Access

0h
31:1 unused_overall_enable: Unused
RW
0h overall_enable: GP Timer enable. Write '1' to enable all enabled timers, write '0' to
0
RW disable all timers.

15.8.49 reg_gpd_gptimer_enable_timer_0_type
(gpd_gptimer_enable_timer_0)—Offset 608h
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) gpd_gptimer_enable_timer_0: [ISPMMADR] + 608h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

enable_timer_0
unused_enable_timer_0

Bit Default &

Description
Range Access

0h
31:1 unused_enable_timer_0: Unused
RW

0h enable_timer_0: GP Timer enable. Write '1' to enable timer 0. Write '0' to disable
0
RW timer 0

15.8.50 reg_gpd_gptimer_enable_timer_1_type
(gpd_gptimer_enable_timer_1)—Offset 60Ch
Access Method

Intel® Atom™ Processor E3800 Product Family

Datasheet 989
 MIPI-Camera Serial Interface (CSI) & ISP

Type: Memory Mapped I/O Register

gpd_gptimer_enable_timer_1: [ISPMMADR] + 60Ch
(Size: 32 bits)
ISPMMADR Type: PCI Configuration Register (Size: 32 bits)
ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

unused_enable_timer_1

enable_timer_1
Bit Default &
Description
Range Access

0h
31:1 unused_enable_timer_1: Unused
RW
0h enable_timer_1: GP Timer enable. Write '1' to enable timer 1. Write '0' to disable
0
RW timer 1

15.8.51 reg_gpd_gptimer_enable_timer_2_type
(gpd_gptimer_enable_timer_2)—Offset 610h
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) gpd_gptimer_enable_timer_2: [ISPMMADR] + 610h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
enable_timer_2
unused_enable_timer_2

Bit Default &

Description
Range Access

0h
31:1 unused_enable_timer_2: Unused
RW

0h enable_timer_2: GP Timer enable. Write '1' to enable timer 2. Write '0' to disable
0
RW timer 2

Intel® Atom™ Processor E3800 Product Family

990 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

15.8.52 reg_gpd_gptimer_enable_timer_3_type
(gpd_gptimer_enable_timer_3)—Offset 614h
Access Method
Type: Memory Mapped I/O Register
gpd_gptimer_enable_timer_3: [ISPMMADR] + 614h
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

unused_enable_timer_3

enable_timer_3
Bit Default &
Description
Range Access

0h
31:1 unused_enable_timer_3: Unused
RW

0h enable_timer_3: GP Timer enable. Write '1' to enable timer 3. Write '0' to disable
0
RW timer 3

15.8.53 reg_gpd_gptimer_enable_timer_4_type
(gpd_gptimer_enable_timer_4)—Offset 618h
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) gpd_gptimer_enable_timer_4: [ISPMMADR] + 618h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_enable_timer_4

enable_timer_4

Intel® Atom™ Processor E3800 Product Family

Datasheet 991
 MIPI-Camera Serial Interface (CSI) & ISP

Bit Default &

Description
Range Access

0h
31:1 unused_enable_timer_4: Unused
RW
0h enable_timer_4: GP Timer enable. Write '1' to enable timer 4. Write '0' to disable
0
RW timer 4

15.8.54 reg_gpd_gptimer_enable_timer_5_type
(gpd_gptimer_enable_timer_5)—Offset 61Ch
Access Method
Type: Memory Mapped I/O Register
gpd_gptimer_enable_timer_5: [ISPMMADR] + 61Ch
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_enable_timer_5

enable_timer_5
Bit Default &
Description
Range Access

0h
31:1 unused_enable_timer_5: Unused
RW

0h enable_timer_5: GP Timer enable. Write '1' to enable timer 5. Write '0' to disable
0
RW timer 5

15.8.55 reg_gpd_gptimer_enable_timer_6_type
(gpd_gptimer_enable_timer_6)—Offset 620h
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) gpd_gptimer_enable_timer_6: [ISPMMADR] + 620h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h

Intel® Atom™ Processor E3800 Product Family

992 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

unused_enable_timer_6

enable_timer_6
Bit Default &
Description
Range Access

0h
31:1 unused_enable_timer_6: Unused
RW
0h enable_timer_6: GP Timer enable. Write '1' to enable timer 6. Write '0' to disable
0
RW timer 6

15.8.56 reg_gpd_gptimer_enable_timer_7_type
(gpd_gptimer_enable_timer_7)—Offset 624h
Access Method
Type: Memory Mapped I/O Register gpd_gptimer_enable_timer_7: [ISPMMADR] + 624h
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_enable_timer_7

enable_timer_7

Bit Default &

Description
Range Access

0h
31:1 unused_enable_timer_7: Unused
RW
0h enable_timer_7: GP Timer enable. Write '1' to enable timer 7. Write '0' to disable
0
RW timer 7

15.8.57 reg_gpd_gptimer_value_timer_0_type
(gpd_gptimer_value_timer_0)—Offset 628h
Access Method

Intel® Atom™ Processor E3800 Product Family

Datasheet 993
 MIPI-Camera Serial Interface (CSI) & ISP

Type: Memory Mapped I/O Register

gpd_gptimer_value_timer_0: [ISPMMADR] + 628h
(Size: 32 bits)
ISPMMADR Type: PCI Configuration Register (Size: 32 bits)
ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

value_timer_0
Bit Default &
Description
Range Access

0h
31:0 value_timer_0: Returns the value of timer 0
RO

15.8.58 reg_gpd_gptimer_value_timer_1_type
(gpd_gptimer_value_timer_1)—Offset 62Ch
Access Method
Type: Memory Mapped I/O Register
gpd_gptimer_value_timer_1: [ISPMMADR] + 62Ch
(Size: 32 bits)
ISPMMADR Type: PCI Configuration Register (Size: 32 bits)
ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
value_timer_1

Bit Default &

Description
Range Access

0h
31:0 value_timer_1: Returns the value of timer 1
RO

15.8.59 reg_gpd_gptimer_value_timer_2_type
(gpd_gptimer_value_timer_2)—Offset 630h
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) gpd_gptimer_value_timer_2: [ISPMMADR] + 630h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h

Intel® Atom™ Processor E3800 Product Family

994 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

value_timer_2
Bit Default &
Description
Range Access

0h
31:0 value_timer_2: Returns the value of timer 2
RO

15.8.60 reg_gpd_gptimer_value_timer_3_type
(gpd_gptimer_value_timer_3)—Offset 634h
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) gpd_gptimer_value_timer_3: [ISPMMADR] + 634h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
value_timer_3

Bit Default &

Description
Range Access

0h
31:0 value_timer_3: Returns the value of timer 3
RO

15.8.61 reg_gpd_gptimer_value_timer_4_type
(gpd_gptimer_value_timer_4)—Offset 638h
Access Method
Type: Memory Mapped I/O Register gpd_gptimer_value_timer_4: [ISPMMADR] + 638h
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h

Intel® Atom™ Processor E3800 Product Family

Datasheet 995
 MIPI-Camera Serial Interface (CSI) & ISP

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

value_timer_4
Bit Default &
Description
Range Access

0h
31:0 value_timer_4: Returns the value of timer 4
RO

15.8.62 reg_gpd_gptimer_value_timer_5_type
(gpd_gptimer_value_timer_5)—Offset 63Ch
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) gpd_gptimer_value_timer_5: [ISPMMADR] + 63Ch

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
value_timer_5

Bit Default &

Description
Range Access

0h
31:0 value_timer_5: Returns the value of timer 5
RO

15.8.63 reg_gpd_gptimer_value_timer_6_type
(gpd_gptimer_value_timer_6)—Offset 640h
Access Method
Type: Memory Mapped I/O Register gpd_gptimer_value_timer_6: [ISPMMADR] + 640h
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h

Intel® Atom™ Processor E3800 Product Family

996 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

value_timer_6
Bit Default &
Description
Range Access

0h
31:0 value_timer_6: Returns the value of timer 6
RO

15.8.64 reg_gpd_gptimer_value_timer_7_type
(gpd_gptimer_value_timer_7)—Offset 644h
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) gpd_gptimer_value_timer_7: [ISPMMADR] + 644h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
value_timer_7

Bit Default &

Description
Range Access

0h
31:0 value_timer_7: Returns the value of timer 7
RO

15.8.65 reg_gpd_gptimer_count_type_timer_0_type
(gpd_gptimer_count_type_timer_0)—Offset 648h
Access Method
Type: Memory Mapped I/O Register gpd_gptimer_count_type_timer_0: [ISPMMADR] + 648h
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h

Intel® Atom™ Processor E3800 Product Family

Datasheet 997
 MIPI-Camera Serial Interface (CSI) & ISP

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

unused_count_type_timer_0

count_type_timer_0
Bit Default &
Description
Range Access

0h
31:2 unused_count_type_timer_0: Unused
RW

0h count_type_timer_0: Indicates what needs to be counted by timer 0, 00- # cycles the

1:0 signal is high (1), 01- # cycles the signal is low (0), 10- # changes from low to high, 11-
RW # changes from high to low

15.8.66 reg_gpd_gptimer_count_type_timer_1_type
(gpd_gptimer_count_type_timer_1)—Offset 64Ch
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) gpd_gptimer_count_type_timer_1: [ISPMMADR] + 64Ch

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_count_type_timer_1

count_type_timer_1

Bit Default &

Description
Range Access

0h
31:2 unused_count_type_timer_1: Unused
RW

0h count_type_timer_1: Indicates what needs to be counted by timer 1, 00- # cycles the

1:0 signal is high (1), 01- # cycles the signal is low (0), 10- # changes from low to high, 11-
RW # changes from high to low

Intel® Atom™ Processor E3800 Product Family

998 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

15.8.67 reg_gpd_gptimer_count_type_timer_2_type
(gpd_gptimer_count_type_timer_2)—Offset 650h
Access Method
Type: Memory Mapped I/O Register
gpd_gptimer_count_type_timer_2: [ISPMMADR] + 650h
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

unused_count_type_timer_2

count_type_timer_2
Bit Default &
Description
Range Access

0h
31:2 unused_count_type_timer_2: Unused
RW

0h count_type_timer_2: Indicates what needs to be counted by timer 2, 00- # cycles the

1:0 signal is high (1), 01- # cycles the signal is low (0), 10- # changes from low to high, 11-
RW # changes from high to low

15.8.68 reg_gpd_gptimer_count_type_timer_3_type
(gpd_gptimer_count_type_timer_3)—Offset 654h
Access Method
Type: Memory Mapped I/O Register gpd_gptimer_count_type_timer_3: [ISPMMADR] + 654h
(Size: 32 bits)
ISPMMADR Type: PCI Configuration Register (Size: 32 bits)
ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_count_type_timer_3

count_type_timer_3

Intel® Atom™ Processor E3800 Product Family

Datasheet 999
 MIPI-Camera Serial Interface (CSI) & ISP

Bit Default &

Description
Range Access

0h
31:2 unused_count_type_timer_3: Unused
RW

0h count_type_timer_3: Indicates what needs to be counted by timer 3, 00- # cycles the

1:0 signal is high (1), 01- # cycles the signal is low (0), 10- # changes from low to high, 11-
RW # changes from high to low

15.8.69 reg_gpd_gptimer_count_type_timer_4_type
(gpd_gptimer_count_type_timer_4)—Offset 658h
Access Method
Type: Memory Mapped I/O Register
gpd_gptimer_count_type_timer_4: [ISPMMADR] + 658h
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_count_type_timer_4

count_type_timer_4
Bit Default &
Description
Range Access

0h
31:2 unused_count_type_timer_4: Unused
RW

0h count_type_timer_4: Indicates what needs to be counted by timer 4, 00- # cycles the

1:0 signal is high (1), 01- # cycles the signal is low (0), 10- # changes from low to high, 11-
RW # changes from high to low

15.8.70 reg_gpd_gptimer_count_type_timer_5_type
(gpd_gptimer_count_type_timer_5)—Offset 65Ch
Access Method
Type: Memory Mapped I/O Register
gpd_gptimer_count_type_timer_5: [ISPMMADR] + 65Ch
(Size: 32 bits)
ISPMMADR Type: PCI Configuration Register (Size: 32 bits)
ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h

Intel® Atom™ Processor E3800 Product Family

1000 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

unused_count_type_timer_5

count_type_timer_5
Bit Default &
Description
Range Access

0h
31:2 unused_count_type_timer_5: Unused
RW

0h count_type_timer_5: Indicates what needs to be counted by timer 5, 00- # cycles the

1:0 signal is high (1), 01- # cycles the signal is low (0), 10- # changes from low to high, 11-
RW # changes from high to low

15.8.71 reg_gpd_gptimer_count_type_timer_6_type
(gpd_gptimer_count_type_timer_6)—Offset 660h
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) gpd_gptimer_count_type_timer_6: [ISPMMADR] + 660h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_count_type_timer_6

count_type_timer_6

Bit Default &

Description
Range Access

0h
31:2 unused_count_type_timer_6: Unused
RW

0h count_type_timer_6: Indicates what needs to be counted by timer 6, 00- # cycles the

1:0 signal is high (1), 01- # cycles the signal is low (0), 10- # changes from low to high, 11-
RW # changes from high to low

Intel® Atom™ Processor E3800 Product Family

Datasheet 1001
 MIPI-Camera Serial Interface (CSI) & ISP

15.8.72 reg_gpd_gptimer_count_type_timer_7_type
(gpd_gptimer_count_type_timer_7)—Offset 664h
Access Method
Type: Memory Mapped I/O Register
gpd_gptimer_count_type_timer_7: [ISPMMADR] + 664h
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

unused_count_type_timer_7

count_type_timer_7
Bit Default &
Description
Range Access

0h
31:2 unused_count_type_timer_7: Unused
RW

0h count_type_timer_7: Indicates what needs to be counted by timer 7, 00- # cycles the

1:0 signal is high (1), 01- # cycles the signal is low (0), 10- # changes from low to high, 11-
RW # changes from high to low

15.8.73 reg_gpd_gptimer_signal_select_timer_0_type
(gpd_gptimer_signal_select_timer_0)—Offset 668h
Access Method
Type: Memory Mapped I/O Register gpd_gptimer_signal_select_timer_0: [ISPMMADR] + 668h
(Size: 32 bits)
ISPMMADR Type: PCI Configuration Register (Size: 32 bits)
ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h

Intel® Atom™ Processor E3800 Product Family

1002 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

unused_signal_select_timer_0

signal_select_timer_0
Bit Default &
Description
Range Access

0h
31:6 unused_signal_select_timer_0: Unused
RW
0h
5:0 signal_select_timer_0: Selects which of the 55 input signals is counted by timer 0
RW

15.8.74 reg_gpd_gptimer_signal_select_timer_1_type
(gpd_gptimer_signal_select_timer_1)—Offset 66Ch
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) gpd_gptimer_signal_select_timer_1: [ISPMMADR] + 66Ch

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_signal_select_timer_1

signal_select_timer_1

Bit Default &

Description
Range Access

0h
31:6 unused_signal_select_timer_1: Unused
RW
0h
5:0 signal_select_timer_1: Selects which of the 55 input signals is counted by timer 1
RW

Intel® Atom™ Processor E3800 Product Family

Datasheet 1003
 MIPI-Camera Serial Interface (CSI) & ISP

15.8.75 reg_gpd_gptimer_signal_select_timer_2_type
(gpd_gptimer_signal_select_timer_2)—Offset 670h
Access Method
Type: Memory Mapped I/O Register
gpd_gptimer_signal_select_timer_2: [ISPMMADR] + 670h
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

unused_signal_select_timer_2

signal_select_timer_2
Bit Default &
Description
Range Access

0h
31:6 unused_signal_select_timer_2: Unused
RW
0h
5:0 signal_select_timer_2: Selects which of the 55 input signals is counted by timer 2
RW

15.8.76 reg_gpd_gptimer_signal_select_timer_3_type
(gpd_gptimer_signal_select_timer_3)—Offset 674h
Access Method
Type: Memory Mapped I/O Register gpd_gptimer_signal_select_timer_3: [ISPMMADR] + 674h
(Size: 32 bits)
ISPMMADR Type: PCI Configuration Register (Size: 32 bits)
ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h

Intel® Atom™ Processor E3800 Product Family

1004 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

unused_signal_select_timer_3

signal_select_timer_3
Bit Default &
Description
Range Access

0h
31:6 unused_signal_select_timer_3: Unused
RW
0h
5:0 signal_select_timer_3: Selects which of the 55 input signals is counted by timer 3
RW

15.8.77 reg_gpd_gptimer_signal_select_timer_4_type
(gpd_gptimer_signal_select_timer_4)—Offset 678h
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) gpd_gptimer_signal_select_timer_4: [ISPMMADR] + 678h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_signal_select_timer_4

signal_select_timer_4

Bit Default &

Description
Range Access

0h
31:6 unused_signal_select_timer_4: Unused
RW
0h
5:0 signal_select_timer_4: Selects which of the 55 input signals is counted by timer 4
RW

Intel® Atom™ Processor E3800 Product Family

Datasheet 1005
 MIPI-Camera Serial Interface (CSI) & ISP

15.8.78 reg_gpd_gptimer_signal_select_timer_5_type
(gpd_gptimer_signal_select_timer_5)—Offset 67Ch
Access Method
Type: Memory Mapped I/O Register
gpd_gptimer_signal_select_timer_5: [ISPMMADR] + 67Ch
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

unused_signal_select_timer_5

signal_select_timer_5
Bit Default &
Description
Range Access

0h
31:6 unused_signal_select_timer_5: Unused
RW
0h
5:0 signal_select_timer_5: Selects which of the 55 input signals is counted by timer 5
RW

15.8.79 reg_gpd_gptimer_signal_select_timer_6_type
(gpd_gptimer_signal_select_timer_6)—Offset 680h
Access Method
Type: Memory Mapped I/O Register gpd_gptimer_signal_select_timer_6: [ISPMMADR] + 680h
(Size: 32 bits)
ISPMMADR Type: PCI Configuration Register (Size: 32 bits)
ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h

Intel® Atom™ Processor E3800 Product Family

1006 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

unused_signal_select_timer_6

signal_select_timer_6
Bit Default &
Description
Range Access

0h
31:6 unused_signal_select_timer_6: Unused
RW
0h
5:0 signal_select_timer_6: Selects which of the 55 input signals is counted by timer 6
RW

15.8.80 reg_gpd_gptimer_signal_select_timer_7_type
(gpd_gptimer_signal_select_timer_7)—Offset 684h
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) gpd_gptimer_signal_select_timer_7: [ISPMMADR] + 684h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_signal_select_timer_7

signal_select_timer_7

Bit Default &

Description
Range Access

0h
31:6 unused_signal_select_timer_7: Unused
RW
0h
5:0 signal_select_timer_7: Selects which of the 55 input signals is counted by timer 7
RW

Intel® Atom™ Processor E3800 Product Family

Datasheet 1007
 MIPI-Camera Serial Interface (CSI) & ISP

15.8.81 reg_gpd_gptimer_irq_trigger_value_0_type
(gpd_gptimer_irq_trigger_value_0)—Offset 688h
Access Method
Type: Memory Mapped I/O Register
gpd_gptimer_irq_trigger_value_0: [ISPMMADR] + 688h
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

irq_trigger_value_0
Bit Default &
Description
Range Access

0h irq_trigger_value_0: IRQ trigger value for interrupt 0. If the timer selected by

31:0
RW irq_timer_select_0 reaches this value, irq_0 will be enabled

15.8.82 reg_gpd_gptimer_irq_trigger_value_1_type
(gpd_gptimer_irq_trigger_value_1)—Offset 68Ch
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) gpd_gptimer_irq_trigger_value_1: [ISPMMADR] + 68Ch

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
irq_trigger_value_1

Bit Default &

Description
Range Access

0h irq_trigger_value_1: IRQ trigger value for interrupt 1. If the timer selected by

31:0
RW irq_timer_select_1 reaches this value, irq_1 will be enabled

Intel® Atom™ Processor E3800 Product Family

1008 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

15.8.83 reg_gpd_gptimer_irq_timer_select_0_type
(gpd_gptimer_irq_timer_select_0)—Offset 690h
Access Method
Type: Memory Mapped I/O Register
gpd_gptimer_irq_timer_select_0: [ISPMMADR] + 690h
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

unused_irq_timer_select_0

irq_timer_select_0
Bit Default &
Description
Range Access

0h
31:3 unused_irq_timer_select_0: Unused
RW
0h
2:0 irq_timer_select_0: Indicates which of the 8 timers will be used for irq_0 generation
RW

15.8.84 reg_gpd_gptimer_irq_timer_select_1_type
(gpd_gptimer_irq_timer_select_1)—Offset 694h
Access Method
Type: Memory Mapped I/O Register gpd_gptimer_irq_timer_select_1: [ISPMMADR] + 694h
(Size: 32 bits)
ISPMMADR Type: PCI Configuration Register (Size: 32 bits)
ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_irq_timer_select_1

irq_timer_select_1

Intel® Atom™ Processor E3800 Product Family

Datasheet 1009
 MIPI-Camera Serial Interface (CSI) & ISP

Bit Default &

Description
Range Access

0h
31:3 unused_irq_timer_select_1: Unused
RW
0h
2:0 irq_timer_select_1: Indicates which of the 8 timers will be used for irq_1 generation
RW

15.8.85 reg_gpd_gptimer_irq_enable_0_type
(gpd_gptimer_irq_enable_0)—Offset 698h
Access Method
Type: Memory Mapped I/O Register
gpd_gptimer_irq_enable_0: [ISPMMADR] + 698h
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_irq_enable_0

irq_enable_0
Bit Default &
Description
Range Access

0h
31:1 unused_irq_enable_0: Unused
RW
0h
0 irq_enable_0: Enable interrupt 0
RW

15.8.86 reg_gpd_gptimer_irq_enable_1_type
(gpd_gptimer_irq_enable_1)—Offset 69Ch
Access Method
Type: Memory Mapped I/O Register gpd_gptimer_irq_enable_1: [ISPMMADR] + 69Ch
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h

Intel® Atom™ Processor E3800 Product Family

1010 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

unused_irq_enable_1

irq_enable_1
Bit Default &
Description
Range Access

0h
31:1 unused_irq_enable_1: Unused
RW

0h
0 irq_enable_1: Enable interrupt 1
RW

15.8.87 reg_scp_stat_and_ctrl_type (scp_stat_and_ctrl)—Offset

10000h
Access Method
Type: Memory Mapped I/O Register
scp_stat_and_ctrl: [ISPMMADR] + 10000h
(Size: 32 bits)
ISPMMADR Type: PCI Configuration Register (Size: 32 bits)
ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 000000A0h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0
arb_cont_dmem_Arb_mem_wp_source1

arb_cont_dmem_Arb_mem_wp_source0
unused_stat_and_ctrl

broken_irq_mask_flag

sleeping_flag

broken_flag
arb_period_dmem_Arb_mem_wp

prefetch_enable_flag

ready_irq_mask_flag

irq_clear_flag

start_flag
reset_flag
invalidate_cache_flag

stalling_flag

ready_flag

run_flag
break_flag
sleeping_irq_mask_flag

Bit Default &

Description
Range Access

0h
31:29 unused_stat_and_ctrl: Unused
RW
0h arb_cont_dmem_Arb_mem_wp_source1: Arbiter contender group bandwidth for
28:24
RW dmem_Arb_mem_wp_source1

Intel® Atom™ Processor E3800 Product Family

Datasheet 1011
 MIPI-Camera Serial Interface (CSI) & ISP

Bit Default &

Description
Range Access

0h arb_cont_dmem_Arb_mem_wp_source0: Arbiter contender group bandwidth for

23:19
RW dmem_Arb_mem_wp_source0

0h
18:14 arb_period_dmem_Arb_mem_wp: Arbiter period for dmem_Arb_mem_wp
RW
0h
13 prefetch_enable_flag: Prefetch enable flag for config_ilm_conf_ilm_icache
RW
0h
12 invalidate_cache_flag: Invalidate cache flag for config_ilm_conf_ilm_icache
RW
0h
11 sleeping_irq_mask_flag: Sleeping IRQ mask flag
RW
0h
10 ready_irq_mask_flag: Ready IRQ mask flag
RW
0h
9 broken_irq_mask_flag: Broken IRQ mask flag
RW
0h
8 irq_clear_flag: IRQ clear flag
RW
1h
7 stalling_flag: Stalling flag. Set to one when not executing an instruction.
RO
0h
6 sleeping_flag: Sleeping flag
RO
1h
5 ready_flag: Ready flag. Set to one when not executing a program.
RO
0h
4 broken_flag: Broken flag
RO
0h
3 run_flag: Run flag
RW
0h
2 break_flag: Break flag
RW
0h
1 start_flag: Start flag
WO
0h
0 reset_flag: Reset flag
WO

15.8.88 reg_scp_base_address_type (scp_base_address)—Offset

10004h
Access Method
Type: Memory Mapped I/O Register
scp_base_address: [ISPMMADR] + 10004h
(Size: 32 bits)
ISPMMADR Type: PCI Configuration Register (Size: 32 bits)
ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h

Intel® Atom™ Processor E3800 Product Family

1012 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

base_address
Bit Default &
Description
Range Access

0h
31:0 base_address: Start address
RW

15.8.89 reg_scp_unused_2_type (scp_unused_2)—Offset 10008h

Access Method
Type: Memory Mapped I/O Register
scp_unused_2: [ISPMMADR] + 10008h
(Size: 32 bits)
ISPMMADR Type: PCI Configuration Register (Size: 32 bits)
ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_2

Bit Default &

Description
Range Access

0h
31:0 unused_2: Unused
RW

15.8.90 reg_scp_base_addr_seg_0_MI_xmem_master_int_type
(scp_base_addr_seg_0_MI_xmem_master_int)—Offset 10010h
Access Method
Type: Memory Mapped I/O Register scp_base_addr_seg_0_MI_xmem_master_int: [ISPMMADR]
(Size: 32 bits) + 10010h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h

Intel® Atom™ Processor E3800 Product Family

Datasheet 1013
 MIPI-Camera Serial Interface (CSI) & ISP

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

base_addr_seg_0_MI_xmem_master_int
Bit Default &
Description
Range Access

0h base_addr_seg_0_MI_xmem_master_int: Base address for segment 0 of master

31:0
RW interface xmem_master_int

15.8.91 reg_scp_base_addr_seg_0_MI_config_ilm_conf_ilm_master_type
(scp_base_addr_seg_0_MI_config_ilm_conf_ilm_master)—
Offset 10014h
Access Method
Type: Memory Mapped I/O Register scp_base_addr_seg_0_MI_config_ilm_conf_ilm_master:
(Size: 32 bits) [ISPMMADR] + 10014h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
base_addr_seg_0_MI_config_ilm_conf_ilm_master

Intel® Atom™ Processor E3800 Product Family

1014 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

Bit Default &

Description
Range Access

0h base_addr_seg_0_MI_config_ilm_conf_ilm_master: Base address for segment 0

31:0
RW of master interface config_ilm_conf_ilm_master

15.8.92 reg_scp_unused_6_type (scp_unused_6)—Offset 10018h

Access Method
Type: Memory Mapped I/O Register
scp_unused_6: [ISPMMADR] + 10018h
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

unused_6

Bit Default &

Description
Range Access

0h
31:0 unused_6: Unused
RW

15.8.93 reg_scp_unused_7_type (scp_unused_7)—Offset 1001Ch

Access Method
Type: Memory Mapped I/O Register
scp_unused_7: [ISPMMADR] + 1001Ch
(Size: 32 bits)
ISPMMADR Type: PCI Configuration Register (Size: 32 bits)
ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_7

Bit Default &

Description
Range Access

0h
31:0 unused_7: Unused
RW

15.8.94 reg_scp_debug_pc_type (scp_debug_pc)—Offset 10024h

Access Method

Intel® Atom™ Processor E3800 Product Family

Datasheet 1015
 MIPI-Camera Serial Interface (CSI) & ISP

Type: Memory Mapped I/O Register

scp_debug_pc: [ISPMMADR] + 10024h
(Size: 32 bits)
ISPMMADR Type: PCI Configuration Register (Size: 32 bits)
ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

debug_pc
Bit Default &
Description
Range Access

0h
31:0 debug_pc: Debug program counter
RO

15.8.95 reg_scp_stall_stat_fifo_loc_mt_am_inst_0_op0_type
(scp_stall_stat_fifo_loc_mt_am_inst_0_op0)—Offset 10028h
Access Method
Type: Memory Mapped I/O Register scp_stall_stat_fifo_loc_mt_am_inst_0_op0: [ISPMMADR] +
(Size: 32 bits) 10028h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_stall_stat_fifo_loc_mt_am_inst_0_op0

stall_stat_config_ilm_conf_ilm_iam_op1
stall_stat_config_ilm_conf_ilm_iam_op0
stall_stat_xmem_loc_mt_am_inst_2_op0
stall_stat_dmem_loc_mt_am_inst_1_op0

stall_stat_fifo_loc_mt_am_inst_0_op9
stall_stat_fifo_loc_mt_am_inst_0_op8
stall_stat_fifo_loc_mt_am_inst_0_op7
stall_stat_fifo_loc_mt_am_inst_0_op6
stall_stat_fifo_loc_mt_am_inst_0_op5
stall_stat_fifo_loc_mt_am_inst_0_op4
stall_stat_fifo_loc_mt_am_inst_0_op3
stall_stat_fifo_loc_mt_am_inst_0_op2
stall_stat_fifo_loc_mt_am_inst_0_op1
stall_stat_fifo_loc_mt_am_inst_0_op0
stall_stat_fifo_loc_mt_am_inst_0_op10

Bit Default &

Description
Range Access

0h
31:15 unused_stall_stat_fifo_loc_mt_am_inst_0_op0: Unused
RW

Intel® Atom™ Processor E3800 Product Family

1016 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

Bit Default &

Description
Range Access

0h stall_stat_config_ilm_conf_ilm_iam_op1: Stalling flag for msink

14
RO config_ilm_conf_ilm_iam_op1

0h stall_stat_config_ilm_conf_ilm_iam_op0: Stalling flag for msink

13
RO config_ilm_conf_ilm_iam_op0

0h stall_stat_xmem_loc_mt_am_inst_2_op0: Stalling flag for msink

12
RO xmem_loc_mt_am_inst_2_op0

0h stall_stat_dmem_loc_mt_am_inst_1_op0: Stalling flag for msink

11
RO dmem_loc_mt_am_inst_1_op0

0h stall_stat_fifo_loc_mt_am_inst_0_op10: Stalling flag for msink

10
RO fifo_loc_mt_am_inst_0_op10

0h stall_stat_fifo_loc_mt_am_inst_0_op9: Stalling flag for msink

9
RO fifo_loc_mt_am_inst_0_op9

0h stall_stat_fifo_loc_mt_am_inst_0_op8: Stalling flag for msink

8
RO fifo_loc_mt_am_inst_0_op8

0h stall_stat_fifo_loc_mt_am_inst_0_op7: Stalling flag for msink

7
RO fifo_loc_mt_am_inst_0_op7

0h stall_stat_fifo_loc_mt_am_inst_0_op6: Stalling flag for msink

6
RO fifo_loc_mt_am_inst_0_op6

0h stall_stat_fifo_loc_mt_am_inst_0_op5: Stalling flag for msink

5
RO fifo_loc_mt_am_inst_0_op5

0h stall_stat_fifo_loc_mt_am_inst_0_op4: Stalling flag for msink

4
RO fifo_loc_mt_am_inst_0_op4

0h stall_stat_fifo_loc_mt_am_inst_0_op3: Stalling flag for msink

3
RO fifo_loc_mt_am_inst_0_op3

0h stall_stat_fifo_loc_mt_am_inst_0_op2: Stalling flag for msink

2
RO fifo_loc_mt_am_inst_0_op2

0h stall_stat_fifo_loc_mt_am_inst_0_op1: Stalling flag for msink

1
RO fifo_loc_mt_am_inst_0_op1

0h stall_stat_fifo_loc_mt_am_inst_0_op0: Stalling flag for msink

0
RO fifo_loc_mt_am_inst_0_op0

15.8.96 reg_scp_unused_11_type (scp_unused_11)—Offset 1002Ch

Access Method
Type: Memory Mapped I/O Register
scp_unused_11: [ISPMMADR] + 1002Ch
(Size: 32 bits)
ISPMMADR Type: PCI Configuration Register (Size: 32 bits)
ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_11

Intel® Atom™ Processor E3800 Product Family

Datasheet 1017
 MIPI-Camera Serial Interface (CSI) & ISP

Bit Default &

Description
Range Access

0h
31:0 unused_11: Unused
RW

15.8.97 reg_scp_pmem_slave_access_type
(scp_pmem_slave_access)—Offset 10030h
Access Method
Type: Memory Mapped I/O Register
scp_pmem_slave_access: [ISPMMADR] + 10030h
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

pmem_slave_access

Bit Default &

Description
Range Access

0h
31:0 pmem_slave_access: Pmem slave access flag
RW

15.8.98 reg_isp_stat_and_ctrl_type (isp_stat_and_ctrl)—Offset 20000h

Access Method
Type: Memory Mapped I/O Register isp_stat_and_ctrl: [ISPMMADR] + 20000h
(Size: 32 bits)
ISPMMADR Type: PCI Configuration Register (Size: 32 bits)
ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 000000A0h

Intel® Atom™ Processor E3800 Product Family

1018 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0

unused_stat_and_ctrl

prefetch_enable_flag

broken_irq_mask_flag

broken_flag

reset_flag
arb_cont_base_dmem_Arb_data_mem_wp0_source1
arb_cont_base_dmem_Arb_data_mem_wp0_source0

invalidate_cache_flag

ready_irq_mask_flag

irq_clear_flag

ready_flag

run_flag
break_flag
start_flag
sleeping_irq_mask_flag

stalling_flag
sleeping_flag
arb_period_base_dmem_Arb_data_mem_wp0
Bit Default &
Description
Range Access

0h
31:17 unused_stat_and_ctrl: Unused
RW
0h arb_cont_base_dmem_Arb_data_mem_wp0_source1: Arbiter contender group
16
RW bandwidth for base_dmem_Arb_data_mem_wp0_source1

0h arb_cont_base_dmem_Arb_data_mem_wp0_source0: Arbiter contender group

15
RW bandwidth for base_dmem_Arb_data_mem_wp0_source0

0h arb_period_base_dmem_Arb_data_mem_wp0: Arbiter period for

14
RW base_dmem_Arb_data_mem_wp0

0h
13 prefetch_enable_flag: Prefetch enable flag for base_config_mem_icache
RW
0h
12 invalidate_cache_flag: Invalidate cache flag for base_config_mem_icache
RW
0h
11 sleeping_irq_mask_flag: Sleeping IRQ mask flag
RW
0h
10 ready_irq_mask_flag: Ready IRQ mask flag
RW
0h
9 broken_irq_mask_flag: Broken IRQ mask flag
RW
0h
8 irq_clear_flag: IRQ clear flag
RW
1h
7 stalling_flag: Stalling flag. Set to one when not executing an instruction.
RO
0h
6 sleeping_flag: Sleeping flag
RO
1h
5 ready_flag: Ready flag. Set to one when not executing a program.
RO

Intel® Atom™ Processor E3800 Product Family

Datasheet 1019
 MIPI-Camera Serial Interface (CSI) & ISP

Bit Default &

Description
Range Access

0h
4 broken_flag: Broken flag
RO
0h
3 run_flag: Run flag
RW
0h
2 break_flag: Break flag
RW
0h
1 start_flag: Start flag
WO
0h
0 reset_flag: Reset flag
WO

15.8.99 reg_isp_base_address_type (isp_base_address)—Offset

20004h
Access Method
Type: Memory Mapped I/O Register isp_base_address: [ISPMMADR] + 20004h
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
base_address

Bit Default &

Description
Range Access

0h
31:0 base_address: Start address
RW

15.8.100 reg_isp_unused_2_type (isp_unused_2)—Offset 20008h

Access Method
Type: Memory Mapped I/O Register isp_unused_2: [ISPMMADR] + 20008h
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_2

Intel® Atom™ Processor E3800 Product Family

1020 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

Bit Default &

Description
Range Access

0h
31:0 unused_2: Unused
RW

15.8.101 reg_isp_base_addr_seg_0_MI_base_config_mem_master_type
(isp_base_addr_seg_0_MI_base_config_mem_master)—Offset
20010h
Access Method
Type: Memory Mapped I/O Register isp_base_addr_seg_0_MI_base_config_mem_master:
(Size: 32 bits) [ISPMMADR] + 20010h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

base_addr_seg_0_MI_base_config_mem_master

Bit Default &

Description
Range Access

0h base_addr_seg_0_MI_base_config_mem_master: Base address for segment 0 of

31:0
RW master interface base_config_mem_master

15.8.102 reg_isp_unused_5_type (isp_unused_5)—Offset 20014h

Access Method
Type: Memory Mapped I/O Register
isp_unused_5: [ISPMMADR] + 20014h
(Size: 32 bits)
ISPMMADR Type: PCI Configuration Register (Size: 32 bits)
ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h

Intel® Atom™ Processor E3800 Product Family

Datasheet 1021
 MIPI-Camera Serial Interface (CSI) & ISP

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

unused_5
Bit Default &
Description
Range Access

0h
31:0 unused_5: Unused
RW

15.8.103 reg_isp_debug_pc_type (isp_debug_pc)—Offset 2001Ch

Access Method
Type: Memory Mapped I/O Register isp_debug_pc: [ISPMMADR] + 2001Ch
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
debug_pc

Bit Default &

Description
Range Access

0h
31:0 debug_pc: Debug program counter
RO

15.8.104 reg_isp_stall_stat_base_config_mem_iam_op0_type
(isp_stall_stat_base_config_mem_iam_op0)—Offset 20020h
Access Method
Type: Memory Mapped I/O Register isp_stall_stat_base_config_mem_iam_op0: [ISPMMADR] +
(Size: 32 bits) 20020h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h

Intel® Atom™ Processor E3800 Product Family

1022 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

unused_stall_stat_base_config_mem_iam_op0

stall_stat_simd_vamem3_loc_mt_am_inst_5_op0
stall_stat_simd_vamem2_loc_mt_am_inst_4_op0
stall_stat_simd_vamem1_loc_mt_am_inst_3_op0
stall_stat_simd_vmem_loc_mt_am_inst_2_op0
stall_stat_simd_histogram_loc_mt_am_inst_6_op0

stall_stat_base_fifo_loc_mt_am_inst_1_op6
stall_stat_base_fifo_loc_mt_am_inst_1_op5
stall_stat_base_fifo_loc_mt_am_inst_1_op4
stall_stat_base_fifo_loc_mt_am_inst_1_op3
stall_stat_base_fifo_loc_mt_am_inst_1_op2
stall_stat_base_fifo_loc_mt_am_inst_1_op1
stall_stat_base_fifo_loc_mt_am_inst_1_op0
stall_stat_base_dmem_loc_mt_am_inst_0_op0
stall_stat_base_config_mem_iam_op1
stall_stat_base_config_mem_iam_op0
Bit Default &
Description
Range Access

0h
31:15 unused_stall_stat_base_config_mem_iam_op0: Unused
RW

0h stall_stat_simd_histogram_loc_mt_am_inst_6_op0: Stalling flag for msink

14
RO simd_histogram_loc_mt_am_inst_6_op0

0h stall_stat_simd_vamem3_loc_mt_am_inst_5_op0: Stalling flag for msink

13
RO simd_vamem3_loc_mt_am_inst_5_op0

0h stall_stat_simd_vamem2_loc_mt_am_inst_4_op0: Stalling flag for msink

12
RO simd_vamem2_loc_mt_am_inst_4_op0

0h stall_stat_simd_vamem1_loc_mt_am_inst_3_op0: Stalling flag for msink

11
RO simd_vamem1_loc_mt_am_inst_3_op0

0h stall_stat_simd_vmem_loc_mt_am_inst_2_op0: Stalling flag for msink

10
RO simd_vmem_loc_mt_am_inst_2_op0

0h stall_stat_base_fifo_loc_mt_am_inst_1_op6: Stalling flag for msink

9
RO base_fifo_loc_mt_am_inst_1_op6

0h stall_stat_base_fifo_loc_mt_am_inst_1_op5: Stalling flag for msink

8
RO base_fifo_loc_mt_am_inst_1_op5

0h stall_stat_base_fifo_loc_mt_am_inst_1_op4: Stalling flag for msink

7
RO base_fifo_loc_mt_am_inst_1_op4

0h stall_stat_base_fifo_loc_mt_am_inst_1_op3: Stalling flag for msink

6
RO base_fifo_loc_mt_am_inst_1_op3

0h stall_stat_base_fifo_loc_mt_am_inst_1_op2: Stalling flag for msink

5
RO base_fifo_loc_mt_am_inst_1_op2

0h stall_stat_base_fifo_loc_mt_am_inst_1_op1: Stalling flag for msink

4
RO base_fifo_loc_mt_am_inst_1_op1

0h stall_stat_base_fifo_loc_mt_am_inst_1_op0: Stalling flag for msink

3
RO base_fifo_loc_mt_am_inst_1_op0

0h stall_stat_base_dmem_loc_mt_am_inst_0_op0: Stalling flag for msink

2
RO base_dmem_loc_mt_am_inst_0_op0

Intel® Atom™ Processor E3800 Product Family

Datasheet 1023
 MIPI-Camera Serial Interface (CSI) & ISP

Bit Default &

Description
Range Access

0h stall_stat_base_config_mem_iam_op1: Stalling flag for msink

1
RO base_config_mem_iam_op1

0h stall_stat_base_config_mem_iam_op0: Stalling flag for msink

0
RO base_config_mem_iam_op0

15.8.105 reg_isp_unused_9_type (isp_unused_9)—Offset 20024h

Access Method
Type: Memory Mapped I/O Register
isp_unused_9: [ISPMMADR] + 20024h
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_9

Bit Default &

Description
Range Access

0h
31:0 unused_9: Unused
RW

15.8.106 reg_isp_pmem_slave_access_type (isp_pmem_slave_access)—

Offset 20028h
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) isp_pmem_slave_access: [ISPMMADR] + 20028h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
pmem_slave_access

Intel® Atom™ Processor E3800 Product Family

1024 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

Bit Default &

Description
Range Access

0h
31:0 pmem_slave_access: Pmem slave access flag
RW

15.8.107 reg_ifmt_ift_prim_IF_sw_rst_type
(ifmt_ift_prim_IF_sw_rst)—Offset 30000h
Access Method
Type: Memory Mapped I/O Register
ifmt_ift_prim_IF_sw_rst: [ISPMMADR] + 30000h
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

unused_IF_sw_rst

IF_sw_rst
Bit Default &
Description
Range Access

0h
31:1 unused_IF_sw_rst: Unused
RW

0h
0 IF_sw_rst: Software Reset
RW

15.8.108 reg_ifmt_ift_prim_IF_start_line_type
(ifmt_ift_prim_IF_start_line)—Offset 30004h
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) ifmt_ift_prim_IF_start_line: [ISPMMADR] + 30004h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_IF_start_line

IF_start_line

Intel® Atom™ Processor E3800 Product Family

Datasheet 1025
 MIPI-Camera Serial Interface (CSI) & ISP

Bit Default &

Description
Range Access

0h
31:16 unused_IF_start_line: Unused
RW
0h
15:0 IF_start_line: Start line: number of line to skip before passing the 1st line
RW

15.8.109 reg_ifmt_ift_prim_IF_start_column_type
(ifmt_ift_prim_IF_start_column)—Offset 30008h
Access Method
Type: Memory Mapped I/O Register
ifmt_ift_prim_IF_start_column: [ISPMMADR] + 30008h
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_IF_start_column

IF_start_column

Bit Default &

Description
Range Access

0h
31:16 unused_IF_start_column: Unused
RW
0h IF_start_column: Start column: number pixel component to skip before passing the
15:0
RW 1st of a line

15.8.110 reg_ifmt_ift_prim_IF_Cropped_height_type
(ifmt_ift_prim_IF_Cropped_height)—Offset 3000Ch
Access Method
Type: Memory Mapped I/O Register ifmt_ift_prim_IF_Cropped_height: [ISPMMADR] + 3000Ch
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h

Intel® Atom™ Processor E3800 Product Family

1026 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

unused_IF_Cropped_height

IF_Cropped_height
Bit Default &
Description
Range Access

0h
31:16 unused_IF_Cropped_height: Unused
RW
0h
15:0 IF_Cropped_height: Cropped height: number of lines of the cropped image
RW

15.8.111 reg_ifmt_ift_prim_IF_Cropped_width_type
(ifmt_ift_prim_IF_Cropped_width)—Offset 30010h
Access Method
Type: Memory Mapped I/O Register ifmt_ift_prim_IF_Cropped_width: [ISPMMADR] + 30010h
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IF_Cropped_width
unused_IF_Cropped_width

Bit Default &

Description
Range Access

0h
31:16 unused_IF_Cropped_width: Unused
RW
0h
15:0 IF_Cropped_width: Cropped width: number of pixel component of the cropped image
RW

Intel® Atom™ Processor E3800 Product Family

Datasheet 1027
 MIPI-Camera Serial Interface (CSI) & ISP

15.8.112 reg_ifmt_ift_prim_IF_Vert_Decim_type
(ifmt_ift_prim_IF_Vert_Decim)—Offset 30014h
Access Method
Type: Memory Mapped I/O Register
ifmt_ift_prim_IF_Vert_Decim: [ISPMMADR] + 30014h
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

unused_IF_Vert_Decim

IF_Vert_Decim
Bit Default &
Description
Range Access

0h
31:12 unused_IF_Vert_Decim: Unused
RW
0h
11:0 IF_Vert_Decim: Vertical decimation factor
RW

15.8.113 reg_ifmt_ift_prim_IF_Horiz_Decim_type
(ifmt_ift_prim_IF_Horiz_Decim)—Offset 30018h
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) ifmt_ift_prim_IF_Horiz_Decim: [ISPMMADR] + 30018h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_IF_Horiz_Decim

IF_Horiz_Decim

Intel® Atom™ Processor E3800 Product Family

1028 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

Bit Default &

Description
Range Access

0h
31:12 unused_IF_Horiz_Decim: Unused
RW
0h
11:0 IF_Horiz_Decim: Horizontal decimation factor
RW

15.8.114 reg_ifmt_ift_prim_IF_Horiz_Deinter_type
(ifmt_ift_prim_IF_Horiz_Deinter)—Offset 3001Ch
Access Method
Type: Memory Mapped I/O Register
ifmt_ift_prim_IF_Horiz_Deinter: [ISPMMADR] + 3001Ch
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_IF_Horiz_Deinter

IF_Horiz_Deinter
Bit Default &
Description
Range Access

0h
31:3 unused_IF_Horiz_Deinter: Unused
RW

0h
2:0 IF_Horiz_Deinter: Horizontal deinterleaving factor
RW

15.8.115 reg_ifmt_ift_prim_IF_Left_Pad_type
(ifmt_ift_prim_IF_Left_Pad)—Offset 30020h
Access Method
Type: Memory Mapped I/O Register
ifmt_ift_prim_IF_Left_Pad: [ISPMMADR] + 30020h
(Size: 32 bits)
ISPMMADR Type: PCI Configuration Register (Size: 32 bits)
ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h

Intel® Atom™ Processor E3800 Product Family

Datasheet 1029
 MIPI-Camera Serial Interface (CSI) & ISP

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

unused_IF_Left_Pad

IF_Left_Pad
Bit Default &
Description
Range Access

0h
31:6 unused_IF_Left_Pad: Unused
RW
0h
5:0 IF_Left_Pad: Left padding: pizel component to be padded at the beggining of each line
RW

15.8.116 reg_ifmt_ift_prim_IF_EOF_Offset_type
(ifmt_ift_prim_IF_EOF_Offset)—Offset 30024h
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) ifmt_ift_prim_IF_EOF_Offset: [ISPMMADR] + 30024h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_IF_EOF_Offset

IF_EOF_Offset

Bit Default &

Description
Range Access

0h
31:24 unused_IF_EOF_Offset: Unused
RW
0h IF_EOF_Offset: End of line offset in bytes: number of bytes to add at the address at
23:0
RW the end of a line

15.8.117 reg_ifmt_ift_prim_IF_Start_addr_type
(ifmt_ift_prim_IF_Start_addr)—Offset 30028h
Access Method

Intel® Atom™ Processor E3800 Product Family

1030 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

Type: Memory Mapped I/O Register

ifmt_ift_prim_IF_Start_addr: [ISPMMADR] + 30028h
(Size: 32 bits)
ISPMMADR Type: PCI Configuration Register (Size: 32 bits)
ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_IF_Start_addr

IF_Start_addr
Bit Default &
Description
Range Access

0h
31:24 unused_IF_Start_addr: Unused
RW
0h
23:0 IF_Start_addr: Start address in bytes: memory buffer start address
RW

15.8.118 reg_ifmt_ift_prim_IF_End_addr_type
(ifmt_ift_prim_IF_End_addr)—Offset 3002Ch
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) ifmt_ift_prim_IF_End_addr: [ISPMMADR] + 3002Ch

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_IF_End_addr

IF_End_addr

Bit Default &

Description
Range Access

0h
31:24 unused_IF_End_addr: Unused
RW
0h
23:0 IF_End_addr: End address in bytes: memory buffer end address
RW

Intel® Atom™ Processor E3800 Product Family

Datasheet 1031
 MIPI-Camera Serial Interface (CSI) & ISP

15.8.119 reg_ifmt_ift_prim_IF_incr_type (ifmt_ift_prim_IF_incr)—

Offset 30030h
Access Method
Type: Memory Mapped I/O Register
ifmt_ift_prim_IF_incr: [ISPMMADR] + 30030h
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_IF_incr

IF_incr
Bit Default &
Description
Range Access

0h
31:24 unused_IF_incr: Unused
RW
0h IF_incr: Word increment in memory word: word increment value after writting each
23:0
RW word

15.8.120 reg_ifmt_ift_prim_IF_YUV_420_format_type
(ifmt_ift_prim_IF_YUV_420_format)—Offset 30034h
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) ifmt_ift_prim_IF_YUV_420_format: [ISPMMADR] + 30034h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_IF_YUV_420_format

IF_YUV_420_format

Intel® Atom™ Processor E3800 Product Family

1032 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

Bit Default &

Description
Range Access

0h
31:1 unused_IF_YUV_420_format: Unused
RW
0h
0 IF_YUV_420_format: YUV 420 format: set to work on legacy format YUV420
RW

15.8.121 reg_ifmt_ift_prim_IF_Vsynch_active_low_type
(ifmt_ift_prim_IF_Vsynch_active_low)—Offset 30038h
Access Method
Type: Memory Mapped I/O Register
ifmt_ift_prim_IF_Vsynch_active_low: [ISPMMADR] + 30038h
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IF_Vsynch_active_low
unused_IF_Vsynch_active_low

Bit Default &

Description
Range Access

0h
31:1 unused_IF_Vsynch_active_low: Unused
RW

0h IF_Vsynch_active_low: Vertical synch active low: set to 1 if Vsynch and EndOfFrame

0
RW are active low

15.8.122 reg_ifmt_ift_prim_IF_Hsynch_active_low_type
(ifmt_ift_prim_IF_Hsynch_active_low)—Offset 3003Ch
Access Method
Type: Memory Mapped I/O Register
ifmt_ift_prim_IF_Hsynch_active_low: [ISPMMADR] + 3003Ch
(Size: 32 bits)
ISPMMADR Type: PCI Configuration Register (Size: 32 bits)
ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h

Intel® Atom™ Processor E3800 Product Family

Datasheet 1033
 MIPI-Camera Serial Interface (CSI) & ISP

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

unused_IF_Hsynch_active_low

IF_Hsynch_active_low
Bit Default &
Description
Range Access

0h
31:1 unused_IF_Hsynch_active_low: Unused
RW

0h IF_Hsynch_active_low: Horizontal synch active low: set to 1 if Hsynch and EndOfLine

0
RW are active low

15.8.123 reg_ifmt_ift_prim_IF_ReEnable_type
(ifmt_ift_prim_IF_ReEnable)—Offset 30040h
Access Method
Type: Memory Mapped I/O Register
ifmt_ift_prim_IF_ReEnable: [ISPMMADR] + 30040h
(Size: 32 bits)
ISPMMADR Type: PCI Configuration Register (Size: 32 bits)
ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IF_ReEnable
unused_IF_ReEnable

Bit Default &

Description
Range Access

0h
31:1 unused_IF_ReEnable: Unused
RW
0h IF_ReEnable: Re-enable status update: set to 1 to re-enable status update after an
0
RW error situation

15.8.124 reg_ifmt_ift_prim_IF_block_input_type
(ifmt_ift_prim_IF_block_input)—Offset 30044h
Access Method

Intel® Atom™ Processor E3800 Product Family

1034 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

Type: Memory Mapped I/O Register

ifmt_ift_prim_IF_block_input: [ISPMMADR] + 30044h
(Size: 32 bits)
ISPMMADR Type: PCI Configuration Register (Size: 32 bits)
ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

unused_IF_block_input

IF_block_input
Bit Default &
Description
Range Access

0h
31:1 unused_IF_block_input: Unused
RW
0h IF_block_input: Block input when no req: set to 1 to block data streaming input when
0
RW no request is received

15.8.125 reg_ifmt_ift_prim_IF_Vert_Deinter_type
(ifmt_ift_prim_IF_Vert_Deinter)—Offset 30048h
Access Method
Type: Memory Mapped I/O Register ifmt_ift_prim_IF_Vert_Deinter: [ISPMMADR] + 30048h
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_IF_Vert_Deinter

IF_Vert_Deinter

Bit Default &

Description
Range Access

0h
31:3 unused_IF_Vert_Deinter: Unused
RW
0h
2:0 IF_Vert_Deinter: Vertical deinterleaving factor
RW

Intel® Atom™ Processor E3800 Product Family

Datasheet 1035
 MIPI-Camera Serial Interface (CSI) & ISP

15.8.126 reg_ifmt_ift_prim_IF_FSM_Sync_status_type
(ifmt_ift_prim_IF_FSM_Sync_status)—Offset 30100h
FSM Sync status

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) ifmt_ift_prim_IF_FSM_Sync_status: [ISPMMADR] + 30100h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

unused_IF_FSM_Sync_status

FSM_Sync_error

FSM_Sync_State
Bit Default &
Description
Range Access

0h
31:4 unused_IF_FSM_Sync_status: Unused
RW
FSM_Sync_error: Error flag: when set in combination with: Idle state an unknown
0h command has been received; Req. Lines state an unexpected vsynch or eof has been
3
RO received; Req. Vectors state an unexpected vsynch or eof has been received; another
state an illegal state transition has occured.

0h FSM_Sync_State: FSM State: State: 0)Idle -- 1)Req Frame -- 2)Req. Lines -- 3)Req.
2:0
RO Vectors -- 4)Send Acknowledge

15.8.127 reg_ifmt_ift_prim_FSM_Sync_counter_type
(ifmt_ift_prim_FSM_Sync_counter)—Offset 30104h
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) ifmt_ift_prim_FSM_Sync_counter: [ISPMMADR] + 30104h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h

Intel® Atom™ Processor E3800 Product Family

1036 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

unused_FSM_Sync_counter

FSM_Sync_counter
Bit Default &
Description
Range Access

0h
31:16 unused_FSM_Sync_counter: Unused
RW

0h FSM_Sync_counter: FSM Sync counter: counts the pixel components of the request
15:0
RO being served (starting from value 1)

15.8.128 reg_ifmt_ift_prim_FSM_Crop_status_type
(ifmt_ift_prim_FSM_Crop_status)—Offset 30108h
FSM Crop status

Access Method
Type: Memory Mapped I/O Register ifmt_ift_prim_FSM_Crop_status: [ISPMMADR] + 30108h
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FSM_Crop_State
FSM_Crop_error
unused_FSM_Crop_status

Bit Default &

Description
Range Access

0h
31:4 unused_FSM_Crop_status: Unused
RW
FSM_Crop_error: Error flag: when set in combination with: Crop Line state
0h unexpected vsynch or eof has been received; Req. Lines state unexpected vsynch or eof
3
RO has been received; Req. Vectors state unexpected vsynch or eof has been received;
another state an illegal state transition has occured.

Intel® Atom™ Processor E3800 Product Family

Datasheet 1037
 MIPI-Camera Serial Interface (CSI) & ISP

Bit Default &

Description
Range Access

0h FSM_Crop_State: FSM State: State: 0)Idle -- 1)Wait Line -- 2)Crop Line -- 3)Crop
2:0
RO Pixel -- 4)Pass pixel -- 5) Pass Line

15.8.129 reg_ifmt_ift_prim_FSM_Crop_line_counter_type
(ifmt_ift_prim_FSM_Crop_line_counter)—Offset 3010Ch
Access Method
Type: Memory Mapped I/O Register ifmt_ift_prim_FSM_Crop_line_counter: [ISPMMADR] +
(Size: 32 bits) 3010Ch

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_FSM_Crop_line_counter

FSM_Crop_line_counter

Bit Default &

Description
Range Access

0h
31:15 unused_FSM_Crop_line_counter: Unused
RW
0h
14:0 FSM_Crop_line_counter: FSM Crop line counter
RO

15.8.130 reg_ifmt_ift_prim_FSM_Crop_pixel_counter_type
(ifmt_ift_prim_FSM_Crop_pixel_counter)—Offset 30110h
Access Method
Type: Memory Mapped I/O Register ifmt_ift_prim_FSM_Crop_pixel_counter: [ISPMMADR] +
(Size: 32 bits) 30110h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h

Intel® Atom™ Processor E3800 Product Family

1038 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

unused_FSM_Crop_pixel_counter

FSM_Crop_pixel_counter
Bit Default &
Description
Range Access

0h
31:16 unused_FSM_Crop_pixel_counter: Unused
RW

0h
15:0 FSM_Crop_pixel_counter: FSM Crop pixel component counter
RO

15.8.131 reg_ifmt_ift_prim_FSM_Deinterl_idx_buffer_type
(ifmt_ift_prim_FSM_Deinterl_idx_buffer)—Offset 30114h
Access Method
Type: Memory Mapped I/O Register ifmt_ift_prim_FSM_Deinterl_idx_buffer: [ISPMMADR] +
(Size: 32 bits) 30114h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_FSM_Deinterl_idx_buffer

FSM_Deinterl_idx_buffer

Bit Default &

Description
Range Access

0h
31:2 unused_FSM_Deinterl_idx_buffer: Unused
RW

Intel® Atom™ Processor E3800 Product Family

Datasheet 1039
 MIPI-Camera Serial Interface (CSI) & ISP

Bit Default &

Description
Range Access

0h
1:0 FSM_Deinterl_idx_buffer: FSM Deinterleaving idx buffer
RO

15.8.132 reg_ifmt_ift_prim_FSM_Horiz_Decim_cnt_type
(ifmt_ift_prim_FSM_Horiz_Decim_cnt)—Offset 30118h
Access Method
Type: Memory Mapped I/O Register
ifmt_ift_prim_FSM_Horiz_Decim_cnt: [ISPMMADR] + 30118h
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_FSM_Horiz_Decim_cnt

FSM_Horiz_Decim_cnt
Bit Default &
Description
Range Access

0h
31:12 unused_FSM_Horiz_Decim_cnt: Unused
RW
0h
11:0 FSM_Horiz_Decim_cnt: FSM Horizontal Decimation counter
RO

15.8.133 reg_ifmt_ift_prim_FSM_Vertic_Decim_cnt_type
(ifmt_ift_prim_FSM_Vertic_Decim_cnt)—Offset 3011Ch
Access Method
Type: Memory Mapped I/O Register ifmt_ift_prim_FSM_Vertic_Decim_cnt: [ISPMMADR] +
(Size: 32 bits) 3011Ch

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h

Intel® Atom™ Processor E3800 Product Family

1040 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

unused_FSM_Vertic_Decim_cnt

FSM_Vertic_Decim_cnt
Bit Default &
Description
Range Access

0h
31:12 unused_FSM_Vertic_Decim_cnt: Unused
RW
0h
11:0 FSM_Vertic_Decim_cnt: FSM Vertical decimation counter
RO

15.8.134 reg_ifmt_ift_prim_FSM_Vertic_Block_Decim_cnt_type
(ifmt_ift_prim_FSM_Vertic_Block_Decim_cnt)—Offset 30120h
Access Method
Type: Memory Mapped I/O Register ifmt_ift_prim_FSM_Vertic_Block_Decim_cnt: [ISPMMADR] +
(Size: 32 bits) 30120h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_FSM_Vertic_Block_Decim_cnt

FSM_Vertic_Block_Decim_cnt

Bit Default &

Description
Range Access

0h
31:2 unused_FSM_Vertic_Block_Decim_cnt: Unused
RW

Intel® Atom™ Processor E3800 Product Family

Datasheet 1041
 MIPI-Camera Serial Interface (CSI) & ISP

Bit Default &

Description
Range Access

0h
1:0 FSM_Vertic_Block_Decim_cnt: FSM Vertical block decimation counter
RO

15.8.135 reg_ifmt_ift_prim_IF_FSM_Padding_status_type
(ifmt_ift_prim_IF_FSM_Padding_status)—Offset 30124h
FSM Padding status

Access Method
Type: Memory Mapped I/O Register ifmt_ift_prim_IF_FSM_Padding_status: [ISPMMADR] +
(Size: 32 bits) 30124h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_IF_FSM_Padding_status

FSM_Padding_error

FSM_Padding_State
Bit Default &
Description
Range Access

0h
31:4 unused_IF_FSM_Padding_status: Unused
RW
FSM_Padding_error: Error flag: when set in combination with: Left Padding state an
0h unexpected vsynch or hsync has been received; Write state an unexpected vsynch or
3 hsync has been received; Right padding state unexpected vsynch has been received;
RO Send EOL state an unexpected vsynch has been received; another state an illegal state
transition has occured.

0h FSM_Padding_State: FSM State: State: 0)Idle -- 1)Left Padding -- 2)Write -- 3)Right

2:0
RO padding -- 4)Sending EOL

15.8.136 reg_ifmt_ift_prim_IF_FSM_Padding_elem_idx_type
(ifmt_ift_prim_IF_FSM_Padding_elem_idx)—Offset 30128h
Access Method
Type: Memory Mapped I/O Register ifmt_ift_prim_IF_FSM_Padding_elem_idx: [ISPMMADR] +
(Size: 32 bits) 30128h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Intel® Atom™ Processor E3800 Product Family

1042 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

unused_IF_FSM_Padding_elem_idx

IF_FSM_Padding_elem_idx
Bit Default &
Description
Range Access

0h
31:6 unused_IF_FSM_Padding_elem_idx: Unused
RW
0h
5:0 IF_FSM_Padding_elem_idx: FSM Padding element index counter
RO

15.8.137 reg_ifmt_ift_prim_IF_FSM_Vec_Sup_type
(ifmt_ift_prim_IF_FSM_Vec_Sup)—Offset 3012Ch
Access Method
Type: Memory Mapped I/O Register ifmt_ift_prim_IF_FSM_Vec_Sup: [ISPMMADR] + 3012Ch
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_IF_FSM_Vec_Sup

IF_FSM_Vec_Sup

Bit Default &

Description
Range Access

0h
31:1 unused_IF_FSM_Vec_Sup: Unused
RW
0h IF_FSM_Vec_Sup: FSM Vector support error state: if set the FSM Vector support is in
0
RO error state

Intel® Atom™ Processor E3800 Product Family

Datasheet 1043
 MIPI-Camera Serial Interface (CSI) & ISP

15.8.138 reg_ifmt_ift_prim_IF_FSM_Vec_Sup_Buf_full_type
(ifmt_ift_prim_IF_FSM_Vec_Sup_Buf_full)—Offset 30130h
Access Method
Type: Memory Mapped I/O Register ifmt_ift_prim_IF_FSM_Vec_Sup_Buf_full: [ISPMMADR] +
(Size: 32 bits) 30130h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

unused_IF_FSM_Vec_Sup_Buf_full

IF_FSM_Vec_Sup_Buf_full
Bit Default &
Description
Range Access

0h
31:3 unused_IF_FSM_Vec_Sup_Buf_full: Unused
RW
0h IF_FSM_Vec_Sup_Buf_full: FSM Vector support buf full: one-hot encoding flag
2:0
RO signaling that the correspondent buffer is full

15.8.139 reg_ifmt_ift_prim_IF_FSM_Vec_Sup_rd_accept_type
(ifmt_ift_prim_IF_FSM_Vec_Sup_rd_accept)—Offset 30134h
Access Method
Type: Memory Mapped I/O Register ifmt_ift_prim_IF_FSM_Vec_Sup_rd_accept: [ISPMMADR] +
(Size: 32 bits) 30134h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000001h

Intel® Atom™ Processor E3800 Product Family

1044 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

unused_IF_FSM_Vec_Sup_rd_accept

IF_FSM_Vec_Sup_rd_accept
Bit Default &
Description
Range Access

0h
31:1 unused_IF_FSM_Vec_Sup_rd_accept: Unused
RW

1h
0 IF_FSM_Vec_Sup_rd_accept: FSM Vector Support fifo rd accept flag
RO

15.8.140 reg_ifmt_ift_prim_IF_Pixel_Fifo_status_type
(ifmt_ift_prim_IF_Pixel_Fifo_status)—Offset 30138h
Pixel Fifo status

Access Method
Type: Memory Mapped I/O Register ifmt_ift_prim_IF_Pixel_Fifo_status: [ISPMMADR] + 30138h
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000001h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Pixel_Fifo_rd_accept

Pixel_Fifo_wr_accept
unused_IF_Pixel_Fifo_status

Pixel_Fifo_rd_valid

Pixel_Fifo_wr_valid

Bit Default &

Description
Range Access

0h
31:4 unused_IF_Pixel_Fifo_status: Unused
RW

Intel® Atom™ Processor E3800 Product Family

Datasheet 1045
 MIPI-Camera Serial Interface (CSI) & ISP

Bit Default &

Description
Range Access

0h
3 Pixel_Fifo_rd_valid: Fifo has an element to be read
RO
0h
2 Pixel_Fifo_rd_accept: IF accepts Pixel(s)
RO
0h
1 Pixel_Fifo_wr_valid: There is an element to write into the Fifo
RO
1h
0 Pixel_Fifo_wr_accept: Fifo is not full(1), Fifo is Full(0)
RO

15.8.141 reg_ifmt_ift_prim_b_IF_sw_rst_type
(ifmt_ift_prim_b_IF_sw_rst)—Offset 30200h
Access Method
Type: Memory Mapped I/O Register ifmt_ift_prim_b_IF_sw_rst: [ISPMMADR] + 30200h
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_IF_sw_rst

IF_sw_rst
Bit Default &
Description
Range Access

0h
31:1 unused_IF_sw_rst: Unused
RW
0h
0 IF_sw_rst: Software Reset
RW

15.8.142 reg_ifmt_ift_prim_b_IF_start_line_type
(ifmt_ift_prim_b_IF_start_line)—Offset 30204h
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) ifmt_ift_prim_b_IF_start_line: [ISPMMADR] + 30204h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h

Intel® Atom™ Processor E3800 Product Family

1046 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

unused_IF_start_line

IF_start_line
Bit Default &
Description
Range Access

0h
31:16 unused_IF_start_line: Unused
RW
0h
15:0 IF_start_line: Start line: number of line to skip before passing the 1st line
RW

15.8.143 reg_ifmt_ift_prim_b_IF_start_column_type
(ifmt_ift_prim_b_IF_start_column)—Offset 30208h
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) ifmt_ift_prim_b_IF_start_column: [ISPMMADR] + 30208h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_IF_start_column

IF_start_column

Bit Default &

Description
Range Access

0h
31:16 unused_IF_start_column: Unused
RW
0h IF_start_column: Start column: number pixel component to skip before passing the
15:0
RW 1st of a line

15.8.144 reg_ifmt_ift_prim_b_IF_Cropped_height_type
(ifmt_ift_prim_b_IF_Cropped_height)—Offset 3020Ch
Access Method

Intel® Atom™ Processor E3800 Product Family

Datasheet 1047
 MIPI-Camera Serial Interface (CSI) & ISP

Type: Memory Mapped I/O Register

ifmt_ift_prim_b_IF_Cropped_height: [ISPMMADR] + 3020Ch
(Size: 32 bits)
ISPMMADR Type: PCI Configuration Register (Size: 32 bits)
ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

unused_IF_Cropped_height

IF_Cropped_height
Bit Default &
Description
Range Access

0h
31:16 unused_IF_Cropped_height: Unused
RW
0h
15:0 IF_Cropped_height: Cropped height: number of lines of the cropped image
RW

15.8.145 reg_ifmt_ift_prim_b_IF_Cropped_width_type
(ifmt_ift_prim_b_IF_Cropped_width)—Offset 30210h
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) ifmt_ift_prim_b_IF_Cropped_width: [ISPMMADR] + 30210h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_IF_Cropped_width

IF_Cropped_width

Bit Default &

Description
Range Access

0h
31:16 unused_IF_Cropped_width: Unused
RW

Intel® Atom™ Processor E3800 Product Family

1048 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

Bit Default &

Description
Range Access

0h
15:0 IF_Cropped_width: Cropped width: number of pixel component of the cropped image
RW

15.8.146 reg_ifmt_ift_prim_b_IF_Vert_Decim_type
(ifmt_ift_prim_b_IF_Vert_Decim)—Offset 30214h
Access Method
Type: Memory Mapped I/O Register
ifmt_ift_prim_b_IF_Vert_Decim: [ISPMMADR] + 30214h
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_IF_Vert_Decim

IF_Vert_Decim
Bit Default &
Description
Range Access

0h
31:12 unused_IF_Vert_Decim: Unused
RW
0h
11:0 IF_Vert_Decim: Vertical decimation factor
RW

15.8.147 reg_ifmt_ift_prim_b_IF_Horiz_Decim_type
(ifmt_ift_prim_b_IF_Horiz_Decim)—Offset 30218h
Access Method
Type: Memory Mapped I/O Register ifmt_ift_prim_b_IF_Horiz_Decim: [ISPMMADR] + 30218h
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h

Intel® Atom™ Processor E3800 Product Family

Datasheet 1049
 MIPI-Camera Serial Interface (CSI) & ISP

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

unused_IF_Horiz_Decim

IF_Horiz_Decim
Bit Default &
Description
Range Access

0h
31:12 unused_IF_Horiz_Decim: Unused
RW
0h
11:0 IF_Horiz_Decim: Horizontal decimation factor
RW

15.8.148 reg_ifmt_ift_prim_b_IF_Horiz_Deinter_type
(ifmt_ift_prim_b_IF_Horiz_Deinter)—Offset 3021Ch
Access Method
Type: Memory Mapped I/O Register ifmt_ift_prim_b_IF_Horiz_Deinter: [ISPMMADR] + 3021Ch
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_IF_Horiz_Deinter

IF_Horiz_Deinter

Bit Default &

Description
Range Access

0h
31:3 unused_IF_Horiz_Deinter: Unused
RW

0h
2:0 IF_Horiz_Deinter: Horizontal deinterleaving factor
RW

15.8.149 reg_ifmt_ift_prim_b_IF_Left_Pad_type
(ifmt_ift_prim_b_IF_Left_Pad)—Offset 30220h
Access Method

Intel® Atom™ Processor E3800 Product Family

1050 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

Type: Memory Mapped I/O Register

ifmt_ift_prim_b_IF_Left_Pad: [ISPMMADR] + 30220h
(Size: 32 bits)
ISPMMADR Type: PCI Configuration Register (Size: 32 bits)
ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

unused_IF_Left_Pad

IF_Left_Pad
Bit Default &
Description
Range Access

0h
31:6 unused_IF_Left_Pad: Unused
RW

0h
5:0 IF_Left_Pad: Left padding: pizel component to be padded at the beggining of each line
RW

15.8.150 reg_ifmt_ift_prim_b_IF_EOF_Offset_type
(ifmt_ift_prim_b_IF_EOF_Offset)—Offset 30224h
Access Method
Type: Memory Mapped I/O Register
ifmt_ift_prim_b_IF_EOF_Offset: [ISPMMADR] + 30224h
(Size: 32 bits)
ISPMMADR Type: PCI Configuration Register (Size: 32 bits)
ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_IF_EOF_Offset

IF_EOF_Offset

Bit Default &

Description
Range Access

0h
31:24 unused_IF_EOF_Offset: Unused
RW
0h IF_EOF_Offset: End of line offset in bytes: number of bytes to add at the address at
23:0
RW the end of a line

Intel® Atom™ Processor E3800 Product Family

Datasheet 1051
 MIPI-Camera Serial Interface (CSI) & ISP

15.8.151 reg_ifmt_ift_prim_b_IF_Start_addr_type
(ifmt_ift_prim_b_IF_Start_addr)—Offset 30228h
Access Method
Type: Memory Mapped I/O Register
ifmt_ift_prim_b_IF_Start_addr: [ISPMMADR] + 30228h
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_IF_Start_addr

IF_Start_addr
Bit Default &
Description
Range Access

0h
31:24 unused_IF_Start_addr: Unused
RW

0h
23:0 IF_Start_addr: Start address in bytes: memory buffer start address
RW

15.8.152 reg_ifmt_ift_prim_b_IF_End_addr_type
(ifmt_ift_prim_b_IF_End_addr)—Offset 3022Ch
Access Method
Type: Memory Mapped I/O Register
ifmt_ift_prim_b_IF_End_addr: [ISPMMADR] + 3022Ch
(Size: 32 bits)
ISPMMADR Type: PCI Configuration Register (Size: 32 bits)
ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_IF_End_addr

IF_End_addr

Intel® Atom™ Processor E3800 Product Family

1052 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

Bit Default &

Description
Range Access

0h
31:24 unused_IF_End_addr: Unused
RW
0h
23:0 IF_End_addr: End address in bytes: memory buffer end address
RW

15.8.153 reg_ifmt_ift_prim_b_IF_incr_type (ifmt_ift_prim_b_IF_incr)—

Offset 30230h
Access Method
Type: Memory Mapped I/O Register
ifmt_ift_prim_b_IF_incr: [ISPMMADR] + 30230h
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_IF_incr

IF_incr

Bit Default &

Description
Range Access

0h
31:24 unused_IF_incr: Unused
RW
0h IF_incr: Word increment in memory word: word increment value after writting each
23:0
RW word

15.8.154 reg_ifmt_ift_prim_b_IF_YUV_420_format_type
(ifmt_ift_prim_b_IF_YUV_420_format)—Offset 30234h
Access Method
Type: Memory Mapped I/O Register ifmt_ift_prim_b_IF_YUV_420_format: [ISPMMADR] +
(Size: 32 bits) 30234h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h

Intel® Atom™ Processor E3800 Product Family

Datasheet 1053
 MIPI-Camera Serial Interface (CSI) & ISP

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IF_YUV_420_format
unused_IF_YUV_420_format
Bit Default &
Description
Range Access

0h
31:1 unused_IF_YUV_420_format: Unused
RW
0h
0 IF_YUV_420_format: YUV 420 format: set to work on legacy format YUV420
RW

15.8.155 reg_ifmt_ift_prim_b_IF_Vsynch_active_low_type
(ifmt_ift_prim_b_IF_Vsynch_active_low)—Offset 30238h
Access Method
Type: Memory Mapped I/O Register ifmt_ift_prim_b_IF_Vsynch_active_low: [ISPMMADR] +
(Size: 32 bits) 30238h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_IF_Vsynch_active_low

IF_Vsynch_active_low

Bit Default &

Description
Range Access

0h
31:1 unused_IF_Vsynch_active_low: Unused
RW
0h IF_Vsynch_active_low: Vertical synch active low: set to 1 if Vsynch and EndOfFrame
0
RW are active low

Intel® Atom™ Processor E3800 Product Family

1054 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

15.8.156 reg_ifmt_ift_prim_b_IF_Hsynch_active_low_type
(ifmt_ift_prim_b_IF_Hsynch_active_low)—Offset 3023Ch
Access Method
Type: Memory Mapped I/O Register ifmt_ift_prim_b_IF_Hsynch_active_low: [ISPMMADR] +
(Size: 32 bits) 3023Ch

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

unused_IF_Hsynch_active_low

IF_Hsynch_active_low
Bit Default &
Description
Range Access

0h
31:1 unused_IF_Hsynch_active_low: Unused
RW

0h IF_Hsynch_active_low: Horizontal synch active low: set to 1 if Hsynch and EndOfLine

0
RW are active low

15.8.157 reg_ifmt_ift_prim_b_IF_ReEnable_type
(ifmt_ift_prim_b_IF_ReEnable)—Offset 30240h
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) ifmt_ift_prim_b_IF_ReEnable: [ISPMMADR] + 30240h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IF_ReEnable
unused_IF_ReEnable

Intel® Atom™ Processor E3800 Product Family

Datasheet 1055
 MIPI-Camera Serial Interface (CSI) & ISP

Bit Default &

Description
Range Access

0h
31:1 unused_IF_ReEnable: Unused
RW
0h IF_ReEnable: Re-enable status update: set to 1 to re-enable status update after an
0
RW error situation

15.8.158 reg_ifmt_ift_prim_b_IF_block_input_type
(ifmt_ift_prim_b_IF_block_input)—Offset 30244h
Access Method
Type: Memory Mapped I/O Register
ifmt_ift_prim_b_IF_block_input: [ISPMMADR] + 30244h
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_IF_block_input

IF_block_input
Bit Default &
Description
Range Access

0h
31:1 unused_IF_block_input: Unused
RW
0h IF_block_input: Block input when no req: set to 1 to block data streaming input when
0
RW no request is received

15.8.159 reg_ifmt_ift_prim_b_IF_Vert_Deinter_type
(ifmt_ift_prim_b_IF_Vert_Deinter)—Offset 30248h
Access Method
Type: Memory Mapped I/O Register ifmt_ift_prim_b_IF_Vert_Deinter: [ISPMMADR] + 30248h
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h

Intel® Atom™ Processor E3800 Product Family

1056 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

unused_IF_Vert_Deinter

IF_Vert_Deinter
Bit Default &
Description
Range Access

0h
31:3 unused_IF_Vert_Deinter: Unused
RW
0h
2:0 IF_Vert_Deinter: Vertical deinterleaving factor
RW

15.8.160 reg_ifmt_ift_prim_b_IF_FSM_Sync_status_type
(ifmt_ift_prim_b_IF_FSM_Sync_status)—Offset 30300h
FSM Sync status

Access Method
Type: Memory Mapped I/O Register ifmt_ift_prim_b_IF_FSM_Sync_status: [ISPMMADR] +
(Size: 32 bits) 30300h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_IF_FSM_Sync_status

FSM_Sync_error

FSM_Sync_State

Bit Default &

Description
Range Access

0h
31:4 unused_IF_FSM_Sync_status: Unused
RW
FSM_Sync_error: Error flag: when set in combination with: Idle state an unknown
0h command has been received; Req. Lines state an unexpected vsynch or eof has been
3
RO received; Req. Vectors state an unexpected vsynch or eof has been received; another
state an illegal state transition has occured.

Intel® Atom™ Processor E3800 Product Family

Datasheet 1057
 MIPI-Camera Serial Interface (CSI) & ISP

Bit Default &

Description
Range Access

0h FSM_Sync_State: FSM State: State: 0)Idle -- 1)Req Frame -- 2)Req. Lines -- 3)Req.
2:0
RO Vectors -- 4)Send Acknowledge

15.8.161 reg_ifmt_ift_prim_b_FSM_Sync_counter_type
(ifmt_ift_prim_b_FSM_Sync_counter)—Offset 30304h
Access Method
Type: Memory Mapped I/O Register
ifmt_ift_prim_b_FSM_Sync_counter: [ISPMMADR] + 30304h
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_FSM_Sync_counter

Bit Default & FSM_Sync_counter

Description
Range Access

0h
31:16 unused_FSM_Sync_counter: Unused
RW
0h FSM_Sync_counter: FSM Sync counter: counts the pixel components of the request
15:0
RO being served (starting from value 1)

15.8.162 reg_ifmt_ift_prim_b_FSM_Crop_status_type
(ifmt_ift_prim_b_FSM_Crop_status)—Offset 30308h
FSM Crop status

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) ifmt_ift_prim_b_FSM_Crop_status: [ISPMMADR] + 30308h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h

Intel® Atom™ Processor E3800 Product Family

1058 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

unused_FSM_Crop_status

FSM_Crop_error

FSM_Crop_State
Bit Default &
Description
Range Access

0h
31:4 unused_FSM_Crop_status: Unused
RW
FSM_Crop_error: Error flag: when set in combination with: Crop Line state
0h unexpected vsynch or eof has been received; Req. Lines state unexpected vsynch or eof
3
RO has been received; Req. Vectors state unexpected vsynch or eof has been received;
another state an illegal state transition has occured.

0h FSM_Crop_State: FSM State: State: 0)Idle -- 1)Wait Line -- 2)Crop Line -- 3)Crop
2:0
RO Pixel -- 4)Pass pixel -- 5) Pass Line

15.8.163 reg_ifmt_ift_prim_b_FSM_Crop_line_counter_type
(ifmt_ift_prim_b_FSM_Crop_line_counter)—Offset 3030Ch
Access Method
Type: Memory Mapped I/O Register ifmt_ift_prim_b_FSM_Crop_line_counter: [ISPMMADR] +
(Size: 32 bits) 3030Ch

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_FSM_Crop_line_counter

FSM_Crop_line_counter

Bit Default &

Description
Range Access

0h
31:15 unused_FSM_Crop_line_counter: Unused
RW

Intel® Atom™ Processor E3800 Product Family

Datasheet 1059
 MIPI-Camera Serial Interface (CSI) & ISP

Bit Default &

Description
Range Access

0h
14:0 FSM_Crop_line_counter: FSM Crop line counter
RO

15.8.164 reg_ifmt_ift_prim_b_FSM_Crop_pixel_counter_type
(ifmt_ift_prim_b_FSM_Crop_pixel_counter)—Offset 30310h
Access Method
Type: Memory Mapped I/O Register ifmt_ift_prim_b_FSM_Crop_pixel_counter: [ISPMMADR] +
(Size: 32 bits) 30310h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_FSM_Crop_pixel_counter

FSM_Crop_pixel_counter

Bit Default &

Description
Range Access

0h
31:16 unused_FSM_Crop_pixel_counter: Unused
RW
0h
15:0 FSM_Crop_pixel_counter: FSM Crop pixel component counter
RO

15.8.165 reg_ifmt_ift_prim_b_FSM_Deinterl_idx_buffer_type
(ifmt_ift_prim_b_FSM_Deinterl_idx_buffer)—Offset 30314h
Access Method
Type: Memory Mapped I/O Register ifmt_ift_prim_b_FSM_Deinterl_idx_buffer: [ISPMMADR] +
(Size: 32 bits) 30314h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h

Intel® Atom™ Processor E3800 Product Family

1060 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

unused_FSM_Deinterl_idx_buffer

FSM_Deinterl_idx_buffer
Bit Default &
Description
Range Access

0h
31:2 unused_FSM_Deinterl_idx_buffer: Unused
RW
0h
1:0 FSM_Deinterl_idx_buffer: FSM Deinterleaving idx buffer
RO

15.8.166 reg_ifmt_ift_prim_b_FSM_Horiz_Decim_cnt_type
(ifmt_ift_prim_b_FSM_Horiz_Decim_cnt)—Offset 30318h
Access Method
Type: Memory Mapped I/O Register ifmt_ift_prim_b_FSM_Horiz_Decim_cnt: [ISPMMADR] +
(Size: 32 bits) 30318h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_FSM_Horiz_Decim_cnt

FSM_Horiz_Decim_cnt

Bit Default &

Description
Range Access

0h
31:12 unused_FSM_Horiz_Decim_cnt: Unused
RW

0h
11:0 FSM_Horiz_Decim_cnt: FSM Horizontal Decimation counter
RO

Intel® Atom™ Processor E3800 Product Family

Datasheet 1061
 MIPI-Camera Serial Interface (CSI) & ISP

15.8.167 reg_ifmt_ift_prim_b_FSM_Vertic_Decim_cnt_type
(ifmt_ift_prim_b_FSM_Vertic_Decim_cnt)—Offset 3031Ch
Access Method
Type: Memory Mapped I/O Register ifmt_ift_prim_b_FSM_Vertic_Decim_cnt: [ISPMMADR] +
(Size: 32 bits) 3031Ch

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_FSM_Vertic_Decim_cnt

FSM_Vertic_Decim_cnt
Bit Default &
Description
Range Access

0h
31:12 unused_FSM_Vertic_Decim_cnt: Unused
RW
0h
11:0 FSM_Vertic_Decim_cnt: FSM Vertical decimation counter
RO

15.8.168 reg_ifmt_ift_prim_b_FSM_Vertic_Block_Decim_cnt_type
(ifmt_ift_prim_b_FSM_Vertic_Block_Decim_cnt)—Offset
30320h
Access Method
Type: Memory Mapped I/O Register ifmt_ift_prim_b_FSM_Vertic_Block_Decim_cnt: [ISPMMADR]
(Size: 32 bits) + 30320h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h

Intel® Atom™ Processor E3800 Product Family

1062 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

unused_FSM_Vertic_Block_Decim_cnt

FSM_Vertic_Block_Decim_cnt
Bit Default &
Description
Range Access

0h
31:2 unused_FSM_Vertic_Block_Decim_cnt: Unused
RW
0h
1:0 FSM_Vertic_Block_Decim_cnt: FSM Vertical block decimation counter
RO

15.8.169 reg_ifmt_ift_prim_b_IF_FSM_Padding_status_type
(ifmt_ift_prim_b_IF_FSM_Padding_status)—Offset 30324h
FSM Padding status

Access Method
Type: Memory Mapped I/O Register ifmt_ift_prim_b_IF_FSM_Padding_status: [ISPMMADR] +
(Size: 32 bits) 30324h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_IF_FSM_Padding_status

FSM_Padding_error

FSM_Padding_State

Intel® Atom™ Processor E3800 Product Family

Datasheet 1063
 MIPI-Camera Serial Interface (CSI) & ISP

Bit Default &

Description
Range Access

0h
31:4 unused_IF_FSM_Padding_status: Unused
RW
FSM_Padding_error: Error flag: when set in combination with: Left Padding state an
0h unexpected vsynch or hsync has been received; Write state an unexpected vsynch or
3 hsync has been received; Right padding state unexpected vsynch has been received;
RO Send EOL state an unexpected vsynch has been received; another state an illegal state
transition has occured.
0h FSM_Padding_State: FSM State: State: 0)Idle -- 1)Left Padding -- 2)Write -- 3)Right
2:0
RO padding -- 4)Sending EOL

15.8.170 reg_ifmt_ift_prim_b_IF_FSM_Padding_elem_idx_type
(ifmt_ift_prim_b_IF_FSM_Padding_elem_idx)—Offset 30328h
Access Method
Type: Memory Mapped I/O Register ifmt_ift_prim_b_IF_FSM_Padding_elem_idx: [ISPMMADR] +
(Size: 32 bits) 30328h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_IF_FSM_Padding_elem_idx

IF_FSM_Padding_elem_idx

Bit Default &

Description
Range Access

0h
31:6 unused_IF_FSM_Padding_elem_idx: Unused
RW
0h
5:0 IF_FSM_Padding_elem_idx: FSM Padding element index counter
RO

15.8.171 reg_ifmt_ift_prim_b_IF_FSM_Vec_Sup_type
(ifmt_ift_prim_b_IF_FSM_Vec_Sup)—Offset 3032Ch
Access Method
Type: Memory Mapped I/O Register
ifmt_ift_prim_b_IF_FSM_Vec_Sup: [ISPMMADR] + 3032Ch
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Intel® Atom™ Processor E3800 Product Family

1064 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

unused_IF_FSM_Vec_Sup

IF_FSM_Vec_Sup
Bit Default &
Description
Range Access

0h
31:1 unused_IF_FSM_Vec_Sup: Unused
RW

0h IF_FSM_Vec_Sup: FSM Vector support error state: if set the FSM Vector support is in
0
RO error state

15.8.172 reg_ifmt_ift_prim_b_IF_FSM_Vec_Sup_Buf_full_type
(ifmt_ift_prim_b_IF_FSM_Vec_Sup_Buf_full)—Offset 30330h
Access Method
Type: Memory Mapped I/O Register ifmt_ift_prim_b_IF_FSM_Vec_Sup_Buf_full: [ISPMMADR] +
(Size: 32 bits) 30330h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_IF_FSM_Vec_Sup_Buf_full

IF_FSM_Vec_Sup_Buf_full

Bit Default &

Description
Range Access

0h
31:3 unused_IF_FSM_Vec_Sup_Buf_full: Unused
RW
0h IF_FSM_Vec_Sup_Buf_full: FSM Vector support buf full: one-hot encoding flag
2:0
RO signaling that the correspondent buffer is full

Intel® Atom™ Processor E3800 Product Family

Datasheet 1065
 MIPI-Camera Serial Interface (CSI) & ISP

15.8.173 reg_ifmt_ift_prim_b_IF_FSM_Vec_Sup_rd_accept_type
(ifmt_ift_prim_b_IF_FSM_Vec_Sup_rd_accept)—Offset 30334h
Access Method
Type: Memory Mapped I/O Register ifmt_ift_prim_b_IF_FSM_Vec_Sup_rd_accept: [ISPMMADR]
(Size: 32 bits) + 30334h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000001h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

unused_IF_FSM_Vec_Sup_rd_accept

IF_FSM_Vec_Sup_rd_accept
Bit Default &
Description
Range Access

0h
31:1 unused_IF_FSM_Vec_Sup_rd_accept: Unused
RW

1h
0 IF_FSM_Vec_Sup_rd_accept: FSM Vector Support fifo rd accept flag
RO

15.8.174 reg_ifmt_ift_prim_b_IF_Pixel_Fifo_status_type
(ifmt_ift_prim_b_IF_Pixel_Fifo_status)—Offset 30338h
Pixel Fifo status

Access Method
Type: Memory Mapped I/O Register ifmt_ift_prim_b_IF_Pixel_Fifo_status: [ISPMMADR] +
(Size: 32 bits) 30338h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000001h

Intel® Atom™ Processor E3800 Product Family

1066 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

Pixel_Fifo_rd_accept

Pixel_Fifo_wr_accept
unused_IF_Pixel_Fifo_status

Pixel_Fifo_rd_valid

Pixel_Fifo_wr_valid
Bit Default &
Description
Range Access

0h
31:4 unused_IF_Pixel_Fifo_status: Unused
RW
0h
3 Pixel_Fifo_rd_valid: Fifo has an element to be read
RO
0h
2 Pixel_Fifo_rd_accept: IF accepts Pixel(s)
RO
0h
1 Pixel_Fifo_wr_valid: There is an element to write into the Fifo
RO
1h
0 Pixel_Fifo_wr_accept: Fifo is not full(1), Fifo is Full(0)
RO

15.8.175 reg_ifmt_ift_sec_IF_sw_rst_type (ifmt_ift_sec_IF_sw_rst)—

Offset 30400h
Access Method
Type: Memory Mapped I/O Register ifmt_ift_sec_IF_sw_rst: [ISPMMADR] + 30400h
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_IF_sw_rst

IF_sw_rst

Bit Default &

Description
Range Access

0h
31:1 unused_IF_sw_rst: Unused
RW

Intel® Atom™ Processor E3800 Product Family

Datasheet 1067
 MIPI-Camera Serial Interface (CSI) & ISP

Bit Default &

Description
Range Access

0h
0 IF_sw_rst: Software Reset
RW

15.8.176 reg_ifmt_ift_sec_IF_start_line_type
(ifmt_ift_sec_IF_start_line)—Offset 30404h
Access Method
Type: Memory Mapped I/O Register
ifmt_ift_sec_IF_start_line: [ISPMMADR] + 30404h
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_IF_start_line

IF_start_line
Bit Default &
Description
Range Access

0h
31:16 unused_IF_start_line: Unused
RW
0h
15:0 IF_start_line: Start line: number of line to skip before passing the 1st line
RW

15.8.177 reg_ifmt_ift_sec_IF_start_column_type
(ifmt_ift_sec_IF_start_column)—Offset 30408h
Access Method
Type: Memory Mapped I/O Register
ifmt_ift_sec_IF_start_column: [ISPMMADR] + 30408h
(Size: 32 bits)
ISPMMADR Type: PCI Configuration Register (Size: 32 bits)
ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h

Intel® Atom™ Processor E3800 Product Family

1068 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

unused_IF_start_column

IF_start_column
Bit Default &
Description
Range Access

0h
31:16 unused_IF_start_column: Unused
RW

0h IF_start_column: Start column: number pixel component to skip before passing the
15:0
RW 1st of a line

15.8.178 reg_ifmt_ift_sec_IF_Cropped_height_type
(ifmt_ift_sec_IF_Cropped_height)—Offset 3040Ch
Access Method
Type: Memory Mapped I/O Register
ifmt_ift_sec_IF_Cropped_height: [ISPMMADR] + 3040Ch
(Size: 32 bits)
ISPMMADR Type: PCI Configuration Register (Size: 32 bits)
ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_IF_Cropped_height

IF_Cropped_height

Bit Default &

Description
Range Access

0h
31:16 unused_IF_Cropped_height: Unused
RW
0h
15:0 IF_Cropped_height: Cropped height: number of lines of the cropped image
RW

Intel® Atom™ Processor E3800 Product Family

Datasheet 1069
 MIPI-Camera Serial Interface (CSI) & ISP

15.8.179 reg_ifmt_ift_sec_IF_Cropped_width_type
(ifmt_ift_sec_IF_Cropped_width)—Offset 30410h
Access Method
Type: Memory Mapped I/O Register
ifmt_ift_sec_IF_Cropped_width: [ISPMMADR] + 30410h
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_IF_Cropped_width

IF_Cropped_width
Bit Default &
Description
Range Access

0h
31:16 unused_IF_Cropped_width: Unused
RW

0h
15:0 IF_Cropped_width: Cropped width: number of pixel component of the cropped image
RW

15.8.180 reg_ifmt_ift_sec_IF_Vert_Decim_type
(ifmt_ift_sec_IF_Vert_Decim)—Offset 30414h
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) ifmt_ift_sec_IF_Vert_Decim: [ISPMMADR] + 30414h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_IF_Vert_Decim

IF_Vert_Decim

Intel® Atom™ Processor E3800 Product Family

1070 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

Bit Default &

Description
Range Access

0h
31:12 unused_IF_Vert_Decim: Unused
RW
0h
11:0 IF_Vert_Decim: Vertical decimation factor
RW

15.8.181 reg_ifmt_ift_sec_IF_Horiz_Decim_type
(ifmt_ift_sec_IF_Horiz_Decim)—Offset 30418h
Access Method
Type: Memory Mapped I/O Register
ifmt_ift_sec_IF_Horiz_Decim: [ISPMMADR] + 30418h
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_IF_Horiz_Decim

IF_Horiz_Decim
Bit Default &
Description
Range Access

0h
31:12 unused_IF_Horiz_Decim: Unused
RW

0h
11:0 IF_Horiz_Decim: Horizontal decimation factor
RW

15.8.182 reg_ifmt_ift_sec_IF_Horiz_Deinter_type
(ifmt_ift_sec_IF_Horiz_Deinter)—Offset 3041Ch
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) ifmt_ift_sec_IF_Horiz_Deinter: [ISPMMADR] + 3041Ch

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h

Intel® Atom™ Processor E3800 Product Family

Datasheet 1071
 MIPI-Camera Serial Interface (CSI) & ISP

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

unused_IF_Horiz_Deinter

IF_Horiz_Deinter
Bit Default &
Description
Range Access

0h
31:3 unused_IF_Horiz_Deinter: Unused
RW
0h
2:0 IF_Horiz_Deinter: Horizontal deinterleaving factor
RW

15.8.183 reg_ifmt_ift_sec_IF_Left_Pad_type
(ifmt_ift_sec_IF_Left_Pad)—Offset 30420h
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) ifmt_ift_sec_IF_Left_Pad: [ISPMMADR] + 30420h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_IF_Left_Pad

IF_Left_Pad

Bit Default &

Description
Range Access

0h
31:6 unused_IF_Left_Pad: Unused
RW
0h
5:0 IF_Left_Pad: Left padding: pizel component to be padded at the beggining of each line
RW

15.8.184 reg_ifmt_ift_sec_IF_EOF_Offset_type
(ifmt_ift_sec_IF_EOF_Offset)—Offset 30424h
Access Method

Intel® Atom™ Processor E3800 Product Family

1072 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

Type: Memory Mapped I/O Register

ifmt_ift_sec_IF_EOF_Offset: [ISPMMADR] + 30424h
(Size: 32 bits)
ISPMMADR Type: PCI Configuration Register (Size: 32 bits)
ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_IF_EOF_Offset

IF_EOF_Offset
Bit Default &
Description
Range Access

0h
31:24 unused_IF_EOF_Offset: Unused
RW

0h IF_EOF_Offset: End of line offset in bytes: number of bytes to add at the address at
23:0
RW the end of a line

15.8.185 reg_ifmt_ift_sec_IF_Start_addr_type
(ifmt_ift_sec_IF_Start_addr)—Offset 30428h
Access Method
Type: Memory Mapped I/O Register
ifmt_ift_sec_IF_Start_addr: [ISPMMADR] + 30428h
(Size: 32 bits)
ISPMMADR Type: PCI Configuration Register (Size: 32 bits)
ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_IF_Start_addr

IF_Start_addr

Bit Default &

Description
Range Access

0h
31:24 unused_IF_Start_addr: Unused
RW
0h
23:0 IF_Start_addr: Start address in bytes: memory buffer start address
RW

Intel® Atom™ Processor E3800 Product Family

Datasheet 1073
 MIPI-Camera Serial Interface (CSI) & ISP

15.8.186 reg_ifmt_ift_sec_IF_End_addr_type
(ifmt_ift_sec_IF_End_addr)—Offset 3042Ch
Access Method
Type: Memory Mapped I/O Register
ifmt_ift_sec_IF_End_addr: [ISPMMADR] + 3042Ch
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_IF_End_addr

IF_End_addr
Bit Default &
Description
Range Access

0h
31:24 unused_IF_End_addr: Unused
RW
0h
23:0 IF_End_addr: End address in bytes: memory buffer end address
RW

15.8.187 reg_ifmt_ift_sec_IF_incr_type (ifmt_ift_sec_IF_incr)—Offset

30430h
Access Method
Type: Memory Mapped I/O Register ifmt_ift_sec_IF_incr: [ISPMMADR] + 30430h
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_IF_incr

IF_incr

Bit Default &

Description
Range Access

0h
31:24 unused_IF_incr: Unused
RW

Intel® Atom™ Processor E3800 Product Family

1074 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

Bit Default &

Description
Range Access

0h IF_incr: Word increment in memory word: word increment value after writting each
23:0
RW word

15.8.188 reg_ifmt_ift_sec_IF_YUV_420_format_type
(ifmt_ift_sec_IF_YUV_420_format)—Offset 30434h
Access Method
Type: Memory Mapped I/O Register
ifmt_ift_sec_IF_YUV_420_format: [ISPMMADR] + 30434h
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

unused_IF_YUV_420_format

IF_YUV_420_format
Bit Default &
Description
Range Access

0h
31:1 unused_IF_YUV_420_format: Unused
RW

0h
0 IF_YUV_420_format: YUV 420 format: set to work on legacy format YUV420
RW

15.8.189 reg_ifmt_ift_sec_IF_Vsynch_active_low_type
(ifmt_ift_sec_IF_Vsynch_active_low)—Offset 30438h
Access Method
Type: Memory Mapped I/O Register
ifmt_ift_sec_IF_Vsynch_active_low: [ISPMMADR] + 30438h
(Size: 32 bits)
ISPMMADR Type: PCI Configuration Register (Size: 32 bits)
ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h

Intel® Atom™ Processor E3800 Product Family

Datasheet 1075
 MIPI-Camera Serial Interface (CSI) & ISP

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

unused_IF_Vsynch_active_low

IF_Vsynch_active_low
Bit Default &
Description
Range Access

0h
31:1 unused_IF_Vsynch_active_low: Unused
RW
0h IF_Vsynch_active_low: Vertical synch active low: set to 1 if Vsynch and EndOfFrame
0
RW are active low

15.8.190 reg_ifmt_ift_sec_IF_Hsynch_active_low_type
(ifmt_ift_sec_IF_Hsynch_active_low)—Offset 3043Ch
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) ifmt_ift_sec_IF_Hsynch_active_low: [ISPMMADR] + 3043Ch

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_IF_Hsynch_active_low

IF_Hsynch_active_low

Bit Default &

Description
Range Access

0h
31:1 unused_IF_Hsynch_active_low: Unused
RW
0h IF_Hsynch_active_low: Horizontal synch active low: set to 1 if Hsynch and EndOfLine
0
RW are active low

Intel® Atom™ Processor E3800 Product Family

1076 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

15.8.191 reg_ifmt_ift_sec_IF_ReEnable_type
(ifmt_ift_sec_IF_ReEnable)—Offset 30440h
Access Method
Type: Memory Mapped I/O Register
ifmt_ift_sec_IF_ReEnable: [ISPMMADR] + 30440h
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

unused_IF_ReEnable

IF_ReEnable
Bit Default &
Description
Range Access

0h
31:1 unused_IF_ReEnable: Unused
RW

0h IF_ReEnable: Re-enable status update: set to 1 to re-enable status update after an

0
RW error situation

15.8.192 reg_ifmt_ift_sec_IF_block_input_type
(ifmt_ift_sec_IF_block_input)—Offset 30444h
Access Method
Type: Memory Mapped I/O Register
ifmt_ift_sec_IF_block_input: [ISPMMADR] + 30444h
(Size: 32 bits)
ISPMMADR Type: PCI Configuration Register (Size: 32 bits)
ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IF_block_input
unused_IF_block_input

Intel® Atom™ Processor E3800 Product Family

Datasheet 1077
 MIPI-Camera Serial Interface (CSI) & ISP

Bit Default &

Description
Range Access

0h
31:1 unused_IF_block_input: Unused
RW
0h IF_block_input: Block input when no req: set to 1 to block data streaming input when
0
RW no request is received

15.8.193 reg_ifmt_ift_sec_IF_Vert_Deinter_type
(ifmt_ift_sec_IF_Vert_Deinter)—Offset 30448h
Access Method
Type: Memory Mapped I/O Register
ifmt_ift_sec_IF_Vert_Deinter: [ISPMMADR] + 30448h
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_IF_Vert_Deinter

IF_Vert_Deinter
Bit Default &
Description
Range Access

0h
31:3 unused_IF_Vert_Deinter: Unused
RW

0h
2:0 IF_Vert_Deinter: Vertical deinterleaving factor
RW

15.8.194 reg_ifmt_ift_sec_IF_FSM_Sync_status_type
(ifmt_ift_sec_IF_FSM_Sync_status)—Offset 30500h
FSM Sync status

Access Method
Type: Memory Mapped I/O Register
ifmt_ift_sec_IF_FSM_Sync_status: [ISPMMADR] + 30500h
(Size: 32 bits)
ISPMMADR Type: PCI Configuration Register (Size: 32 bits)
ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h

Intel® Atom™ Processor E3800 Product Family

1078 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

unused_IF_FSM_Sync_status

FSM_Sync_error

FSM_Sync_State
Bit Default &
Description
Range Access

0h
31:4 unused_IF_FSM_Sync_status: Unused
RW
FSM_Sync_error: Error flag: when set in combination with: Idle state an unknown
0h command has been received; Req. Lines state an unexpected vsynch or eof has been
3
RO received; Req. Vectors state an unexpected vsynch or eof has been received; another
state an illegal state transition has occured.

0h FSM_Sync_State: FSM State: State: 0)Idle -- 1)Req Frame -- 2)Req. Lines -- 3)Req.
2:0
RO Vectors -- 4)Send Acknowledge

15.8.195 reg_ifmt_ift_sec_FSM_Sync_counter_type
(ifmt_ift_sec_FSM_Sync_counter)—Offset 30504h
Access Method
Type: Memory Mapped I/O Register
ifmt_ift_sec_FSM_Sync_counter: [ISPMMADR] + 30504h
(Size: 32 bits)
ISPMMADR Type: PCI Configuration Register (Size: 32 bits)
ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_FSM_Sync_counter

FSM_Sync_counter

Bit Default &

Description
Range Access

0h
31:16 unused_FSM_Sync_counter: Unused
RW

Intel® Atom™ Processor E3800 Product Family

Datasheet 1079
 MIPI-Camera Serial Interface (CSI) & ISP

Bit Default &

Description
Range Access

0h FSM_Sync_counter: FSM Sync counter: counts the pixel components of the request
15:0
RO being served (starting from value 1)

15.8.196 reg_ifmt_ift_sec_FSM_Crop_status_type
(ifmt_ift_sec_FSM_Crop_status)—Offset 30508h
FSM Crop status

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) ifmt_ift_sec_FSM_Crop_status: [ISPMMADR] + 30508h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_FSM_Crop_status

FSM_Crop_error

FSM_Crop_State
Bit Default &
Description
Range Access

0h
31:4 unused_FSM_Crop_status: Unused
RW

FSM_Crop_error: Error flag: when set in combination with: Crop Line state
0h unexpected vsynch or eof has been received; Req. Lines state unexpected vsynch or eof
3
RO has been received; Req. Vectors state unexpected vsynch or eof has been received;
another state an illegal state transition has occured.
0h FSM_Crop_State: FSM State: State: 0)Idle -- 1)Wait Line -- 2)Crop Line -- 3)Crop
2:0
RO Pixel -- 4)Pass pixel -- 5) Pass Line

15.8.197 reg_ifmt_ift_sec_FSM_Crop_line_counter_type
(ifmt_ift_sec_FSM_Crop_line_counter)—Offset 3050Ch
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) ifmt_ift_sec_FSM_Crop_line_counter: [ISPMMADR] + 3050Ch

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h

Intel® Atom™ Processor E3800 Product Family

1080 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

unused_FSM_Crop_line_counter

FSM_Crop_line_counter
Bit Default &
Description
Range Access

0h
31:15 unused_FSM_Crop_line_counter: Unused
RW
0h
14:0 FSM_Crop_line_counter: FSM Crop line counter
RO

15.8.198 reg_ifmt_ift_sec_FSM_Crop_pixel_counter_type
(ifmt_ift_sec_FSM_Crop_pixel_counter)—Offset 30510h
Access Method
Type: Memory Mapped I/O Register ifmt_ift_sec_FSM_Crop_pixel_counter: [ISPMMADR] +
(Size: 32 bits) 30510h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_FSM_Crop_pixel_counter

FSM_Crop_pixel_counter

Bit Default &

Description
Range Access

0h
31:16 unused_FSM_Crop_pixel_counter: Unused
RW

0h
15:0 FSM_Crop_pixel_counter: FSM Crop pixel component counter
RO

Intel® Atom™ Processor E3800 Product Family

Datasheet 1081
 MIPI-Camera Serial Interface (CSI) & ISP

15.8.199 reg_ifmt_ift_sec_FSM_Deinterl_idx_buffer_type
(ifmt_ift_sec_FSM_Deinterl_idx_buffer)—Offset 30514h
Access Method
Type: Memory Mapped I/O Register ifmt_ift_sec_FSM_Deinterl_idx_buffer: [ISPMMADR] +
(Size: 32 bits) 30514h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

unused_FSM_Deinterl_idx_buffer

FSM_Deinterl_idx_buffer
Bit Default &
Description
Range Access

0h
31:2 unused_FSM_Deinterl_idx_buffer: Unused
RW
0h
1:0 FSM_Deinterl_idx_buffer: FSM Deinterleaving idx buffer
RO

15.8.200 reg_ifmt_ift_sec_FSM_Horiz_Decim_cnt_type
(ifmt_ift_sec_FSM_Horiz_Decim_cnt)—Offset 30518h
Access Method
Type: Memory Mapped I/O Register ifmt_ift_sec_FSM_Horiz_Decim_cnt: [ISPMMADR] + 30518h
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h

Intel® Atom™ Processor E3800 Product Family

1082 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

unused_FSM_Horiz_Decim_cnt

FSM_Horiz_Decim_cnt
Bit Default &
Description
Range Access

0h
31:12 unused_FSM_Horiz_Decim_cnt: Unused
RW

0h
11:0 FSM_Horiz_Decim_cnt: FSM Horizontal Decimation counter
RO

15.8.201 reg_ifmt_ift_sec_FSM_Vertic_Decim_cnt_type
(ifmt_ift_sec_FSM_Vertic_Decim_cnt)—Offset 3051Ch
Access Method
Type: Memory Mapped I/O Register
ifmt_ift_sec_FSM_Vertic_Decim_cnt: [ISPMMADR] + 3051Ch
(Size: 32 bits)
ISPMMADR Type: PCI Configuration Register (Size: 32 bits)
ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_FSM_Vertic_Decim_cnt

FSM_Vertic_Decim_cnt

Bit Default &

Description
Range Access

0h
31:12 unused_FSM_Vertic_Decim_cnt: Unused
RW
0h
11:0 FSM_Vertic_Decim_cnt: FSM Vertical decimation counter
RO

Intel® Atom™ Processor E3800 Product Family

Datasheet 1083
 MIPI-Camera Serial Interface (CSI) & ISP

15.8.202 reg_ifmt_ift_sec_FSM_Vertic_Block_Decim_cnt_type
(ifmt_ift_sec_FSM_Vertic_Block_Decim_cnt)—Offset 30520h
Access Method
Type: Memory Mapped I/O Register ifmt_ift_sec_FSM_Vertic_Block_Decim_cnt: [ISPMMADR] +
(Size: 32 bits) 30520h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

unused_FSM_Vertic_Block_Decim_cnt

FSM_Vertic_Block_Decim_cnt
Bit Default &
Description
Range Access

0h
31:2 unused_FSM_Vertic_Block_Decim_cnt: Unused
RW
0h
1:0 FSM_Vertic_Block_Decim_cnt: FSM Vertical block decimation counter
RO

15.8.203 reg_ifmt_ift_sec_IF_FSM_Padding_status_type
(ifmt_ift_sec_IF_FSM_Padding_status)—Offset 30524h
FSM Padding status

Access Method
Type: Memory Mapped I/O Register ifmt_ift_sec_IF_FSM_Padding_status: [ISPMMADR] + 30524h
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h

Intel® Atom™ Processor E3800 Product Family

1084 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

unused_IF_FSM_Padding_status

FSM_Padding_error

FSM_Padding_State
Bit Default &
Description
Range Access

0h
31:4 unused_IF_FSM_Padding_status: Unused
RW
FSM_Padding_error: Error flag: when set in combination with: Left Padding state an
0h unexpected vsynch or hsync has been received; Write state an unexpected vsynch or
3 hsync has been received; Right padding state unexpected vsynch has been received;
RO Send EOL state an unexpected vsynch has been received; another state an illegal state
transition has occured.

0h FSM_Padding_State: FSM State: State: 0)Idle -- 1)Left Padding -- 2)Write -- 3)Right

2:0
RO padding -- 4)Sending EOL

15.8.204 reg_ifmt_ift_sec_IF_FSM_Padding_elem_idx_type
(ifmt_ift_sec_IF_FSM_Padding_elem_idx)—Offset 30528h
Access Method
Type: Memory Mapped I/O Register ifmt_ift_sec_IF_FSM_Padding_elem_idx: [ISPMMADR] +
(Size: 32 bits) 30528h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_IF_FSM_Padding_elem_idx

IF_FSM_Padding_elem_idx

Intel® Atom™ Processor E3800 Product Family

Datasheet 1085
 MIPI-Camera Serial Interface (CSI) & ISP

Bit Default &

Description
Range Access

0h
31:6 unused_IF_FSM_Padding_elem_idx: Unused
RW
0h
5:0 IF_FSM_Padding_elem_idx: FSM Padding element index counter
RO

15.8.205 reg_ifmt_ift_sec_IF_FSM_Vec_Sup_type
(ifmt_ift_sec_IF_FSM_Vec_Sup)—Offset 3052Ch
Access Method
Type: Memory Mapped I/O Register
ifmt_ift_sec_IF_FSM_Vec_Sup: [ISPMMADR] + 3052Ch
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_IF_FSM_Vec_Sup

IF_FSM_Vec_Sup
Bit Default &
Description
Range Access

0h
31:1 unused_IF_FSM_Vec_Sup: Unused
RW
0h IF_FSM_Vec_Sup: FSM Vector support error state: if set the FSM Vector support is in
0
RO error state

15.8.206 reg_ifmt_ift_sec_IF_FSM_Vec_Sup_Buf_full_type
(ifmt_ift_sec_IF_FSM_Vec_Sup_Buf_full)—Offset 30530h
Access Method
Type: Memory Mapped I/O Register ifmt_ift_sec_IF_FSM_Vec_Sup_Buf_full: [ISPMMADR] +
(Size: 32 bits) 30530h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h

Intel® Atom™ Processor E3800 Product Family

1086 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

unused_IF_FSM_Vec_Sup_Buf_full

IF_FSM_Vec_Sup_Buf_full
Bit Default &
Description
Range Access

0h
31:3 unused_IF_FSM_Vec_Sup_Buf_full: Unused
RW
0h IF_FSM_Vec_Sup_Buf_full: FSM Vector support buf full: one-hot encoding flag
2:0
RO signaling that the correspondent buffer is full

15.8.207 reg_ifmt_ift_sec_IF_FSM_Vec_Sup_rd_accept_type
(ifmt_ift_sec_IF_FSM_Vec_Sup_rd_accept)—Offset 30534h
Access Method
Type: Memory Mapped I/O Register ifmt_ift_sec_IF_FSM_Vec_Sup_rd_accept: [ISPMMADR] +
(Size: 32 bits) 30534h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000001h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
unused_IF_FSM_Vec_Sup_rd_accept

IF_FSM_Vec_Sup_rd_accept

Bit Default &

Description
Range Access

0h
31:1 unused_IF_FSM_Vec_Sup_rd_accept: Unused
RW

Intel® Atom™ Processor E3800 Product Family

Datasheet 1087
 MIPI-Camera Serial Interface (CSI) & ISP

Bit Default &

Description
Range Access

1h
0 IF_FSM_Vec_Sup_rd_accept: FSM Vector Support fifo rd accept flag
RO

15.8.208 reg_ifmt_ift_sec_IF_Pixel_Fifo_status_type
(ifmt_ift_sec_IF_Pixel_Fifo_status)—Offset 30538h
Pixel Fifo status

Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) ifmt_ift_sec_IF_Pixel_Fifo_status: [ISPMMADR] + 30538h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000001h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
unused_IF_Pixel_Fifo_status

Pixel_Fifo_rd_valid

Pixel_Fifo_wr_valid
Pixel_Fifo_rd_accept

Pixel_Fifo_wr_accept
Bit Default &
Description
Range Access

0h
31:4 unused_IF_Pixel_Fifo_status: Unused
RW

0h
3 Pixel_Fifo_rd_valid: Fifo has an element to be read
RO

0h
2 Pixel_Fifo_rd_accept: IF accepts Pixel(s)
RO

0h
1 Pixel_Fifo_wr_valid: There is an element to write into the Fifo
RO

1h
0 Pixel_Fifo_wr_accept: Fifo is not full(1), Fifo is Full(0)
RO

15.8.209 reg_ifmt_mem_cpy_MemCopy_sw_rst_type
(ifmt_mem_cpy_MemCopy_sw_rst)—Offset 30600h
Access Method
Type: Memory Mapped I/O Register ifmt_mem_cpy_MemCopy_sw_rst: [ISPMMADR] + 30600h
(Size: 32 bits)
ISPMMADR Type: PCI Configuration Register (Size: 32 bits)
ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Intel® Atom™ Processor E3800 Product Family

1088 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

unused_MemCopy_sw_rst

MemCopy_sw_rst
Bit Default &
Description
Range Access

0h
31:1 unused_MemCopy_sw_rst: Unused
RW
0h
0 MemCopy_sw_rst: Software Reset
RW

15.8.210 reg_ifmt_mem_cpy_MemCopy_in_endian_type
(ifmt_mem_cpy_MemCopy_in_endian)—Offset 30604h
Access Method
Type: Memory Mapped I/O Register ifmt_mem_cpy_MemCopy_in_endian: [ISPMMADR] + 30604h
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_MemCopy_in_endian

MemCopy_in_endian

Bit Default &

Description
Range Access

0h
31:1 unused_MemCopy_in_endian: Unused
RW
0h
0 MemCopy_in_endian: Input endianness : set to 1 if input is big endian
RW

Intel® Atom™ Processor E3800 Product Family

Datasheet 1089
 MIPI-Camera Serial Interface (CSI) & ISP

15.8.211 reg_ifmt_mem_cpy_MemCopy_out_endian_type
(ifmt_mem_cpy_MemCopy_out_endian)—Offset 30608h
Access Method
Type: Memory Mapped I/O Register ifmt_mem_cpy_MemCopy_out_endian: [ISPMMADR] +
(Size: 32 bits) 30608h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

unused_MemCopy_out_endian

MemCopy_out_endian
Bit Default &
Description
Range Access

0h
31:1 unused_MemCopy_out_endian: Unused
RW

0h MemCopy_out_endian: Output endianness : set to 1 to deliver output input in big

0
RW endian

15.8.212 reg_ifmt_mem_cpy_MemCopy_bit_swap_type
(ifmt_mem_cpy_MemCopy_bit_swap)—Offset 3060Ch
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits) ifmt_mem_cpy_MemCopy_bit_swap: [ISPMMADR] + 3060Ch

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h

Intel® Atom™ Processor E3800 Product Family

1090 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

unused_MemCopy_bit_swap

MemCopy_bit_swap
Bit Default &
Description
Range Access

0h
31:1 unused_MemCopy_bit_swap: Unused
RW
0h
0 MemCopy_bit_swap: Bit swapping : set to 1 to swap the bit of the incoming byte
RW

15.8.213 reg_ifmt_mem_cpy_MemCopy_block_synch_type
(ifmt_mem_cpy_MemCopy_block_synch)—Offset 30610h
Access Method
Type: Memory Mapped I/O Register ifmt_mem_cpy_MemCopy_block_synch: [ISPMMADR] +
(Size: 32 bits) 30610h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_MemCopy_block_synch

MemCopy_block_synch

Bit Default &

Description
Range Access

0h
31:1 unused_MemCopy_block_synch: Unused
RW
0h MemCopy_block_synch: Block synchronization pulse active low: set to 1 if start of
0
RW block and end of block are active low

Intel® Atom™ Processor E3800 Product Family

Datasheet 1091
 MIPI-Camera Serial Interface (CSI) & ISP

15.8.214 reg_ifmt_mem_cpy_MemCopy_packet_synch_type
(ifmt_mem_cpy_MemCopy_packet_synch)—Offset 30614h
Access Method
Type: Memory Mapped I/O Register ifmt_mem_cpy_MemCopy_packet_synch: [ISPMMADR] +
(Size: 32 bits) 30614h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

unused_MemCopy_packet_synch

MemCopy_packet_synch
Bit Default &
Description
Range Access

0h
31:1 unused_MemCopy_packet_synch: Unused
RW
0h MemCopy_packet_synch: Packet synchronization pulse active low: set to 1 if start of
0
RW packet and end of packet are active low

15.8.215 reg_ifmt_mem_cpy_MemCopy_rd_post_wr_sync_type
(ifmt_mem_cpy_MemCopy_rd_post_wr_sync)—Offset 30618h
Access Method
Type: Memory Mapped I/O Register ifmt_mem_cpy_MemCopy_rd_post_wr_sync: [ISPMMADR] +
(Size: 32 bits) 30618h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h

Intel® Atom™ Processor E3800 Product Family

1092 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MemCopy_rd_post_wr_sync
unused_MemCopy_rd_post_wr_sync
Bit Default &
Description
Range Access

0h
31:1 unused_MemCopy_rd_post_wr_sync: Unused
RW
0h MemCopy_rd_post_wr_sync: Enable read post write synchronization: set to 1 to
0
RW enable read post write check before sending acknowledge

15.8.216 reg_ifmt_mem_cpy_MemCopy_dual_input_type
(ifmt_mem_cpy_MemCopy_dual_input)—Offset 3061Ch
Access Method
Type: Memory Mapped I/O Register ifmt_mem_cpy_MemCopy_dual_input: [ISPMMADR] +
(Size: 32 bits) 3061Ch

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_MemCopy_dual_input

MemCopy_dual_input

Bit Default &

Description
Range Access

0h
31:1 unused_MemCopy_dual_input: Unused
RW

Intel® Atom™ Processor E3800 Product Family

Datasheet 1093
 MIPI-Camera Serial Interface (CSI) & ISP

Bit Default &

Description
Range Access

0h
0 MemCopy_dual_input: Enable dual byte inputs: set to 1 to enable dual byte input
RW

15.8.217 reg_ifmt_mem_cpy_MemCopy_ReEnable_type
(ifmt_mem_cpy_MemCopy_ReEnable)—Offset 30620h
Access Method
Type: Memory Mapped I/O Register
ifmt_mem_cpy_MemCopy_ReEnable: [ISPMMADR] + 30620h
(Size: 32 bits)

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

unused_MemCopy_ReEnable

MemCopy_ReEnable
Bit Default &
Description
Range Access

0h
31:1 unused_MemCopy_ReEnable: Unused
RW

0h MemCopy_ReEnable: Re-enable status update: set to 1 to re-enable status update

0
RW after an error situation

15.8.218 reg_ifmt_mem_cpy_MemCopy_token_data_type
(ifmt_mem_cpy_MemCopy_token_data)—Offset 30700h
Access Method
Type: Memory Mapped I/O Register ifmt_mem_cpy_MemCopy_token_data: [ISPMMADR] +
(Size: 32 bits) 30700h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h

Intel® Atom™ Processor E3800 Product Family

1094 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MemCopy_token_data
Bit Default &
Description
Range Access

0h
31:0 MemCopy_token_data: Token data on command port
RO

15.8.219 reg_ifmt_mem_cpy_MemCopy_FSM_Sync_status_type
(ifmt_mem_cpy_MemCopy_FSM_Sync_status)—Offset 30704h
Access Method
Type: Memory Mapped I/O Register ifmt_mem_cpy_MemCopy_FSM_Sync_status: [ISPMMADR] +
(Size: 32 bits) 30704h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_MemCopy_FSM_Sync_status

MemCopy_FSM_Sync_status

Bit Default &

Description
Range Access

0h
31:3 unused_MemCopy_FSM_Sync_status: Unused
RW
0h MemCopy_FSM_Sync_status: FSM Synchronization Status: 0)Idle -- 1)Request
2:0
RO Blocks -- 2)Request Packets -- 3)Request Bytes -- 4)Send Acknowledge

Intel® Atom™ Processor E3800 Product Family

Datasheet 1095
 MIPI-Camera Serial Interface (CSI) & ISP

15.8.220 reg_ifmt_mem_cpy_MemCopy_FSM_Sync_bytes_cnt_type
(ifmt_mem_cpy_MemCopy_FSM_Sync_bytes_cnt)—Offset
30708h
Access Method
Type: Memory Mapped I/O Register ifmt_mem_cpy_MemCopy_FSM_Sync_bytes_cnt:
(Size: 32 bits) [ISPMMADR] + 30708h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unused_MemCopy_FSM_Sync_bytes_cnt

Bit Default & MemCopy_FSM_Sync_bytes_cnt

Description
Range Access

0h
31:16 unused_MemCopy_FSM_Sync_bytes_cnt: Unused
RW
0h MemCopy_FSM_Sync_bytes_cnt: FSM Synchronization bytes counter: counts the
15:0
RO number of bytes received and packed

15.8.221 reg_ifmt_mem_cpy_MemCopy_FSM_Sync_token_cnt_type
(ifmt_mem_cpy_MemCopy_FSM_Sync_token_cnt)—Offset
3070Ch
Access Method
Type: Memory Mapped I/O Register ifmt_mem_cpy_MemCopy_FSM_Sync_token_cnt:
(Size: 32 bits) [ISPMMADR] + 3070Ch

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h

Intel® Atom™ Processor E3800 Product Family

1096 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

unused_MemCopy_FSM_Sync_token_cnt

MemCopy_FSM_Sync_token_cnt
Bit Default &
Description
Range Access

0h
31:16 unused_MemCopy_FSM_Sync_token_cnt: Unused
RW

0h MemCopy_FSM_Sync_token_cnt: FSM Synchronization token amount: counts the

15:0
RO number of token processed

15.8.222 reg_ifmt_mem_cpy_MemCopy_FSM_Pack_idx_cnt_type
(ifmt_mem_cpy_MemCopy_FSM_Pack_idx_cnt)—Offset 30710h
Access Method
Type: Memory Mapped I/O Register ifmt_mem_cpy_MemCopy_FSM_Pack_idx_cnt: [ISPMMADR]
(Size: 32 bits) + 30710h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MemCopy_FSM_Pack_idx_cnt
unused_MemCopy_FSM_Pack_idx_cnt

Intel® Atom™ Processor E3800 Product Family

Datasheet 1097
 MIPI-Camera Serial Interface (CSI) & ISP

Bit Default &

Description
Range Access

0h
31:2 unused_MemCopy_FSM_Pack_idx_cnt: Unused
RW
0h
1:0 MemCopy_FSM_Pack_idx_cnt: FSM Pack idx counter: element index
RO

15.8.223 reg_ifmt_mem_cpy_MemCopy_FSM_Buf_Sup_status_type
(ifmt_mem_cpy_MemCopy_FSM_Buf_Sup_status)—Offset
30714h
Buffer Full and mask

Access Method
Type: Memory Mapped I/O Register ifmt_mem_cpy_MemCopy_FSM_Buf_Sup_status:
(Size: 32 bits) [ISPMMADR] + 30714h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

field_mask
unused_MemCopy_FSM_Buf_Sup_status

field_full

Bit Default &

Description
Range Access

0h
31:3 unused_MemCopy_FSM_Buf_Sup_status: Unused
RW
0h
2 field_mask: FSM Buffer support mask buffers full to the FSM CioWr
RO
0h
1:0 field_full: FSM Buffer support one-hot encoding flagging when the buffer are full
RO

15.8.224 reg_ifmt_mem_cpy_MemCopy_FSM_Buf_Sup_cnt_type
(ifmt_mem_cpy_MemCopy_FSM_Buf_Sup_cnt)—Offset 30718h
Access Method

Intel® Atom™ Processor E3800 Product Family

1098 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

Type: Memory Mapped I/O Register ifmt_mem_cpy_MemCopy_FSM_Buf_Sup_cnt: [ISPMMADR]

(Size: 32 bits) + 30718h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

unused_MemCopy_FSM_Buf_Sup_cnt

MemCopy_FSM_Buf_Sup_cnt
Bit Default &
Description
Range Access

0h
31:1 unused_MemCopy_FSM_Buf_Sup_cnt: Unused
RW
0h
0 MemCopy_FSM_Buf_Sup_cnt: FSM Buffer support: counter for buffer index
RO

15.8.225 reg_ifmt_mem_cpy_MemCopy_FSM_CioWr_status_type
(ifmt_mem_cpy_MemCopy_FSM_CioWr_status)—Offset 3071Ch
FSM CioWr Status

Access Method
Type: Memory Mapped I/O Register ifmt_mem_cpy_MemCopy_FSM_CioWr_status: [ISPMMADR]
(Size: 32 bits) + 3071Ch

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000004h

Intel® Atom™ Processor E3800 Product Family

Datasheet 1099
 MIPI-Camera Serial Interface (CSI) & ISP

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0

unused_MemCopy_FSM_CioWr_status

MemCopy_FSM_CioWr_state
MemCopy_FSM_CioWr_rvalid
MemCopy_FSM_CioWr_run
MemCopy_FSM_CioWr_we_n
MemCopy_FSM_CioWr_cs
Bit Default &
Description
Range Access

0h
31:5 unused_MemCopy_FSM_CioWr_status: Unused
RW
0h
4 MemCopy_FSM_CioWr_state: 0)Idle - 1)Writing
RO
0h
3 MemCopy_FSM_CioWr_rvalid: Read valid flag
RO
1h
2 MemCopy_FSM_CioWr_run: Run flag
RO
0h
1 MemCopy_FSM_CioWr_we_n: Write enable flag, active low
RO
0h
0 MemCopy_FSM_CioWr_cs: CS flag
RO

15.8.226 reg_ifmt_mem_cpy_MemCopy_FSM_CioWr_addr_type
(ifmt_mem_cpy_MemCopy_FSM_CioWr_addr)—Offset 30720h
Access Method
Type: Memory Mapped I/O Register ifmt_mem_cpy_MemCopy_FSM_CioWr_addr: [ISPMMADR] +
(Size: 32 bits) 30720h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h

Intel® Atom™ Processor E3800 Product Family

1100 Datasheet
MIPI-Camera Serial Interface (CSI) & ISP

31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MemCopy_FSM_CioWr_addr
Bit Default &
Description
Range Access

0h
31:0 MemCopy_FSM_CioWr_addr: FSM CioWr: write address in byte
RO

15.8.227 reg_ifmt_gp_reg_IFMT_input_switch_lut_reg0_type
(ifmt_gp_reg_IFMT_input_switch_lut_reg0)—Offset 30800h
Access Method
Type: Memory Mapped I/O Register ifmt_gp_reg_IFMT_input_switch_lut_reg0: [ISPMMADR] +
(Size: 32 bits) 30800h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IFMT_input_switch_lut_reg0

Bit Default &

Description
Range Access

0h IFMT_input_switch_lut_reg0: GP reg input switch data and hsync look-up table

31:0
RW Register 0

15.8.228 reg_ifmt_gp_reg_IFMT_input_switch_lut_reg1_type
(ifmt_gp_reg_IFMT_input_switch_lut_reg1)—Offset 30804h
Access Method

Intel® Atom™ Processor E3800 Product Family

Datasheet 1101
 MIPI-Camera Serial Interface (CSI) & ISP

Type: Memory Mapped I/O Register ifmt_gp_reg_IFMT_input_switch_lut_reg1: [ISPMMADR] +

(Size: 32 bits) 30804h

ISPMMADR Type: PCI Configuration Register (Size: 32 bits)

ISPMMADR Reference: [B:0, D:3, F:0] + 10h

Default: 00000000h
31 28 24 20 16 12 8 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0