Architectural Overview

Architectural Overview 2

2.1 Introduction
This section provides an overview of the PCI/PCI-X Family of Gigabit Ethernet Controllers. The
following sections give detailed information about the Ethernet controller’s functionality, register
description, and initialization sequence. All major interfaces of the Ethernet controllers are
described in detail.

The following principles shaped the design of the PCI/PCI-X Family of Gigabit Ethernet
Controllers:
1. Provide an Ethernet interface containing a 10/100/1000 Mb/s PHY that also supports 1000
Base-X implementations.
2. Provide the highest performance solution possible, based on the following:
— Provide direct access to all memory without using mapping registers
— Minimize the PCI target accesses required to manage the Ethernet controller
— Minimize the interrupts required to manage the Ethernet controller
— Off-load the host processor from simple tasks such as TCP checksum calculations
— Maximize PCI efficiency and performance
— Use mixed signal processing to assure physical layer characteristics surpass specifications
for UTP copper media
3. Provide a simple software interface for basic operations.
4. Provide a highly configurable design that can be used effectively in different environments.

The PCI/PCI-X Family of Gigabit Ethernet Controllers architecture is a derivative of the 82542
and 82543 designs. They take the MAC functionality and integrated copper PHY from their
predecessors and adds SMBus-based manageability and integrated ASF controller functionality to
the MAC1. In addition, the 82546GB/EB features this architecture in an integrated dual-port
solution comprised of two distinct MAC/PHY instances.

1. Not applicable to the 82544GC/EI or 82541ER.

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2.2 External Architecture

Figure 2-1 shows the external interfaces to the 82546GB/EB.
MDI MDI
Interface A Interface B
1000Base-T PHY Interfaces

Design for
10/100/1000 10/100/1000
Test Interface
PHY PHY SMBus
External Interface
GMII/ GMII/
TBI Interface MDIO MDIO EEPROM
MII MII
Interface

Device Device Flash Interface

Function 0 Function 1
MAC/Controller MAC/Controller
LEDs (LAN A) LEDs
(LAN B)
Software Software
Defined Pins Defined Pins

PCI (64-bit, 33/66 MHz)/PCI-X (133 MHz)

Figure 2-1. 82546GB/EB External Interface

Figure 2-2 shows the external interfaces to the 82545GM/EM, 82544GC/EI, 82540EP/EM, and
82541xx.
MDI
Interface
1000Base-T PHY Interface

Design for
10/100/1000
Test Interface
PHY SMBus
External Interface
GMII/
TBI Interface MDIO EEPROM
MII
(82545GM/EM only) Interface

Flash Interface
Device
Function 0
LEDs MAC/Controller

Software
Defined Pins

PCI (64-bit, 33/66 MHz)/PCI-X (133 MHz)

Note: 82540EP/EM and 82541xx do not support PCI-X; 82544GC/EI and 82541ER do not support SMBus interface

Figure 2-2. 82545GM/EM, 82544GC/EI, 82540EP/EM, and 82541xx External Interface

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Figure 2-3 shows the external interfaces to the 82547GI/EI.

CSA Port
PCI Core EEPROM FLASH

Slave
DMA Function
Access
Descriptor Management
Logic
40KB
Packet
RAM
RX Filters
Control
TX/RX MAC (Perfect,
Status
CSMA/CD Multicast,
Logic
VLAN)
VLA
N

Statistics

8 bits

Management
8 bits
Interface
Trellis Viterbi Side-stream
Encoder/Decoder Scrambler/
Descrambler
PHY
4 bits
Control
4 bits

ECHO, NEXT,
4DPAM5
FEXT
Encoder
Cancellers

AGC, A/D
Pulse Shaper,
Timing
DAC, Filter
Recovery

Hybrid Line Driver

Media Dependent Interface

Figure 2-3. 82547GI(EI) External Interface

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2.3 Microarchitecture
Compared to its predecessors, the PCI/PCI-X Family of Gigabit Ethernet Controller’s MAC adds
improved receive-packet filtering to support SMBus-based manageability, as well as the ability to
transmit SMBus-based manageability packets. In addition, an ASF-compliant TCO controller is
integrated into the controller’s MAC for reduced-cost basic ASF manageability.

Note: The 82544GC/EI and 82541ER do not support SMBus-based manageability.

For the 82546GB/EB, this new functionality is packaged in an integrated dual-port combination.
The architecture includes two instances of both the MAC and PHY along with a single PCI/PCI-X
interface. As a result, each of the logical LAN devices appear as a distinct PCI/PCI-X bus device.

The following sections describe the hardware building blocks. Figure 2-4 shows the internal
microarchitecture.

2.3.1 PCI/PCI-X Core Interface

The PCI/PCI-X core provides a complete glueless interface to a 33/66 MHz, 32/64-bit PCI bus or a
33/66/133 MHz, 32/64 bit PCI-X bus. It is compliant with the PCI Bus Specification Rev 2.2 or 2.3
and the PCI-X Specification Rev. 1.0a. The Ethernet controllers provide 32 or 64 bits of addressing
and data, and the complete control interface to operate on a 32-bit or 64-bit PCI or PCI-X bus. In
systems with a dedicated bus for the Ethernet controller, this provides sufficient bandwidth to
support sustained 1000 Mb/s full-duplex transfer rates. Systems with a shared bus (especially the
32-bit wide interface) might not be able to maintain 1000 Mb/s, but can sustain multiple hundreds
of Mbps.

Host Arbiter

TX MAC
TX
(10/100/ Link I/F
Switch
DMA 1000 Mb) GMII/
Engine MII
PCI/ RX MAC
PCI Interface PCI-X (10/100/
Packet/
Core Manageability 1000 Mb)
Filter

MDIO
Packet ASF
MDIO
Buffer Manageability RMON
Statistics

SM Bus

EEPROM Flash

Figure 2-4. Internal Architecture Block Diagram

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When the Ethernet controller serves as a PCI target, it follows the PCI configuration specification,
which allows all accesses to it to be automatically mapped into free memory and I/O space at
initialization of the PCI system.

When processing transmit and receive frames, the Ethernet controller operates as master on the PCI
bus. As a master, transaction burst length on the PCI bus is determined by several factors, including
the PCI latency timer expiration, the type of bus transfer being made, the size of the data transfer,
and whether the data transfer is initiated by receive or transmit logic.

The PCI/PCI-X bus interfaces to the DMA engine.

2.3.2 82547GI/EI CSA Interface

CSA is derived from the Intel® Hub Architecture. The 82547EI Controller CSA port consists of 11
data and control signals, two strobes, a 66 MHz clock, and driver compensation resistor connec-
tions. The operating details of these signals and the packet data protocol that accompanies them are
proprietary. The CSA port has a theoretical bandwidth of 266 MB/s — approximately twice the
peak bandwidth of a 32-bit 33 MHz PCI bus.

The CSA port architecture is invisible to both system software and the operating system, allowing
conventional PCI-like configuration.

2.3.3 DMA Engine and Data FIFO

The DMA engine handles the receive and transmit data and descriptor transfers between the host
memory and the on-chip memory.

In the receive path, the DMA engine transfers the data stored in the receive data FIFO buffer to the
receive buffer in the host memory, specified by the address in the descriptor. It also fetches and
writes back updated receive descriptors to host memory.

In the transmit path, the DMA engine transfers data stored in the host memory buffers to the
transmit data FIFO buffer. It also fetches and writes back updated transmit descriptors.

The Ethernet controller data FIFO block consists of a 64 KB (40 KB for the 82547GI/EI) on-chip
buffer for receive and transmit operation. The receive and transmit FIFO size can be allocated
based on the system requirements. The FIFO provides a temporary buffer storage area for frames
as they are received or transmitted by the Ethernet controller.

The DMA engine and the large data FIFOs are optimized to maximize the PCI bus efficiency and
reduce processor utilization by:
• Mitigating instantaneous receive bandwidth demands and eliminating transmit underruns by
buffering the entire out-going packet prior to transmission
• Queuing transmit frames within the transmit FIFO, allowing back-to-back transmission with
the minimum interframe spacing
• Allowing the Ethernet controller to withstand long PCI bus latencies without losing incoming
data or corrupting outgoing data
• Allowing the transmit start threshold to be tuned by the transmit FIFO threshold. This
adjustment to system performance is based on the available PCI bandwidth, wire speed, and
latency considerations

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• Offloading the receiving and transmitting IP and TCP/UDP checksums

• Directly retransmitting from the transmit FIFO any transmissions resulting in errors (collision
detection, data underrun), thus eliminating the need to re-access this data from host memory

2.3.4 10/100/1000 Mb/s Receive and Transmit MAC Blocks

The controller’s CSMA/CD unit handles all the IEEE 802.3 receive and transmit MAC functions
while interfacing between the DMA and TBI/internal SerDes/MII/GMII interface block. The
CSMA/CD unit supports IEEE 802.3 for 10 Mb/s, IEEE 802.3u for 100 Mb/s and IEEE 802.3z and
IEEE 802.3ab for 1000 Mb/s.

The Ethernet controller supports half-duplex 10/100 Mb/s MII or 1000 Mb/s GMII mode and all
aspects of the above specifications in full-duplex operation. In half-duplex mode, the Ethernet
controller supports operation as specified in IEEE 802.3z specification. In the receive path, the
Ethernet controller supports carrier extended packets and packets generated during packet bursting
operation. The 82554GC/EI, in the transmit path, also supports carrier extended packets and can
be configured to transmit in packet burst mode.

The Ethernet controller offers various filtering capabilities that provide better performance and
lower processor utilization as follows:
• Provides up to 16 addresses for exact match unicast/multicast address filtering.
• Provides multicast address filtering based on 4096 bit vectors. Promiscuous unicast and
promiscuous multicast filtering are supported as well.
• The Ethernet controller strips IEEE 802.1q VLAN tag and filter packets based on their VLAN
ID. Up to 4096 VLAN tags are supported1.

In the transmit path, the Ethernet controller supports insertion of VLAN tag information, on a
packet-by-packet basis.

The Ethernet controller implements the flow control function as defined in IEEE 802.3x, as well as
specific operation of asymmetrical flow control as defined by IEEE 802.3z. The Ethernet controller
also provides external pins for controlling the flow control function through external logic.

2.3.5 MII/GMII/TBI/Internal SerDes Interface Block

The Ethernet controller provides the following serial interfaces:
• A GMII/MII interface to the internal PHY.
• Internal SerDes interface2 (82546GB/EB and 82545GM/EM)/Ten Bit Interface (TBI)2 for the
82544GC/EI: The Ethernet controller implements the 802.3z PCS function, the Auto-
Negotiation function and 10-bit data path interface (TBI) for both receive and transmit
operations. It is used for 1000BASE-SX, -LX, and -CX configurations, operating only at 1000
Mb/s full-duplex. The on-chip PCS circuitry is only used when the link interface is configured
for TBI mode and it is bypassed in internal PHY modes.

1. Not applicable to the 82541ER.

2. Not applicable to the 82544GC/EI, 82540EP/EM, 82541xx, and 82547GI/EI.

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Note: Refer to the Extended Device Control Register (bits 23:22) for mode selection (see Section 13.4.6).

The link can be configured by several methods. Software can force the link setting to Auto-
Negotiation by setting either the MAC in TBI mode (internal SerDes for the 82546GB/EB and
82545GM/EM), or the PHY in internal PHY mode.

The speed of the link in internal PHY mode can be determined by several methods:
• Auto speed detection based on the receive clock signal generated by the PHY.
• Detection of the PHY link speed indication.
• Software forcing the configuration of link speed.

2.3.6 10/100/1000 Ethernet Transceiver (PHY)

The Ethernet controller provides a full high-performance, integrated transceiver for 10/100/
1000 Mb/s data communication. The physical layer (PHY) blocks are 802.3 compliant and capable
of operating in half-duplex or full-duplex modes.

Highlights of the PHY blocks are as follows:

• Data stream serializers and encoders. Encoding techniques include Manchester, 4B/5B and
4D/PAM5. These blocks also perform data scrambling for 100/1000 Mb/s transmission as a
technique to minimize radiated Electromagnetic Interference (EMI).
• A multi-mode transmit digital to analog converter, which produces filtered waveforms
appropriate for the 10BASE-T, 100BASE-TX or 1000BASE-T Ethernet standards.
• Receiver Analog-to-Digital Converter (ADC). The ADC uses a 125 MHz sampling rate.
• Receiver decoders. These blocks perform the inverse operations of serializers, encoders and
scramblers.
• Active hybrid and echo canceller blocks. The active hybrid and echo canceller blocks reduce
the echo effect of transmitting and receiving simultaneously on the same analog pairs.
• NEXT canceller. This unit removes high frequency Near End Crosstalk induced among
adjacent signal pairs.
• Additional wave shaping and slew rate control circuitry to reduce EMI.
Because the Ethernet controller is IEEE-compliant, the PHY blocks communicate with the MAC
blocks through an internal GMII/MII bus operating at clock speeds of 2.5 MHz up to 125 MHz.

The Ethernet controller also uses an IEEE-compliant internal Management Data interface to
communicate control and status information to the PHY.

2.3.7 EEPROM Interface

The PCI/PCI-X Family of Gigabit Ethernet Controllers provide a four-wire direct interface to a
serial EEPROM device such as the 93C46 or compatible for storing product configuration
information. Several words of the data stored in the EEPROM are automatically accessed by the
Ethernet controller, after reset, to provide pre-boot configuration data to the Ethernet controller
before it is accessible by the host software. The remainder of the stored information is accessed by
various software modules to report product configuration, serial number and other parameters.

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2.3.8 FLASH Memory Interface

The Ethernet controller provides an external parallel interface to a FLASH device. Accesses to the
FLASH are controlled by the Ethernet controller and are accessible to software as normal PCI
reads or writes to the FLASH memory mapping area. The Ethernet controller supports FLASH
devices with up to 512 KB of memory.

Note: The 82540EP/EM provides an external interface to a serial FLASH or Boot EEPROM device. See
Appendix B for more information.

2.4 DMA Addressing

In appropriate systems, all addresses mastered by the Ethernet controller are 64 bits in order to
support systems that have larger than 32-bit physical addressing. Providing 64-bit addresses
eliminates the need for special segment registers.

Note: The PCI 2.2 or 2.3 Specification requires that any 64-bit address whose upper 32 bits are all 0b
appear as a 32-bit address cycle. The Ethernet controller complies with the PCI 2.2 or 2.3
Specification.

PCI is little-endian; however, not all processors in systems using PCI treat memory as little-endian.
Network data is fundamentally a byte stream. As a result, it is important that the processor and
Ethernet controller agree about the representation of memory data. The default is little-endian
mode.

Descriptor accesses are not byte swapped.

The following example illustrates data-byte ordering for little endian. Bytes for a receive packet
arrive in the order shown from left to right.

01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e

Example 2-1. Byte Ordering

There are no alignment restrictions on packet-buffer addresses. The byte address for the major
words is shown on the left. The byte numbers and bit numbers for the PCI bus are shown across the
top.

Table 2-1. Little Endian Data Ordering

63 0
7 6 5 4 3 2 1 0

Byte 0 08 07 06 05 04 03 02 01
Address 8 10 0f 0e 0d 0c 0b 0a 09
10 18 17 16 15 14 13 12 11
18 20 1f 1e 1d 1c 1b 1a 19

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2.5 Ethernet Addressing

Several registers store Ethernet addresses in the Ethernet controller. Two 32-bit registers make up
the address: one is called “high”, and the other is called “low”. For example, the Receive Address
Register is comprised of Receive Address High (RAH) and Receive Address Low (RAL). The least
significant bit of the least significant byte of the address stored in the register (for example, bit 0 of
RAL) is the multicast bit. The LS byte is the first byte to appear on the wire. This notation applies
to all address registers, including the flow control registers.

Figure 2-5 shows the bit/byte addressing order comparison between what is on the wire and the
values in the unique receive address registers.

Preamble & SFD Destination Address Source Address

...55 D5 00 AA 00 11 22 33 ...XXX

Bit 0 of this byte is first on the wire

dest_addr[0]

33 22 11 00 AA 00
Destination address stored
internally as shown here Multicast bit

... 33 22 11 00 AA 00

Figure 2-5. Example of Address Byte Ordering

The address byte order numbering shown in Figure 2-5 maps to Table 2-2. Byte #1 is first on the
wire.

Table 2-2. Intel® Architecture Byte Ordering

IA Byte # 1 (LSB) 2 3 4 5 6 (MSB)

Byte Value (Hex) 00 AA 00 11 22 33

Note: The notation in this manual follows the convention shown in Table 2-2. For example, the address in
Table 2-2 indicates 00_AA_00_11_22_33h, where the first byte (00h_) is the first byte on the wire,
with bit 0 of that byte transmitted first.

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2.6 Interrupts
The Ethernet controller provides a complete set of interrupts that allow for efficient software
management. The interrupt structure is designed to accomplish the following:
• Make accesses “thread-safe” by using ‘set’ and ‘clear-on-read’ rather than ‘read-modify-write’
operations.
• Minimize the number of interrupts needed relative to work accomplished.
• Minimize the processing overhead associated with each interrupt.
Intel accomplished the first goal by an interrupt logic consisting of four interrupt registers. More
detail about these registers is given in sections 13.4.17 through 13.4.21.
• Interrupt Cause ‘Set’ and ‘Read’ Registers
The Read register records the cause of the interrupt. All bits set at the time of the read are auto-
cleared. The cause bit is set for each bit written as a 1b in the Set register. If there is a race
between hardware setting a cause and software clearing an interrupt, the bit remains set. No
race condition exists on writing the Set register. A ‘set’ provides for software posting of an
interrupt. A ‘read’ is auto-cleared to avoid expensive write operations. Most systems have
write buffering, which minimizes overhead, but typically requires a read operation to
guarantee that the write operation has been flushed from the posted buffers. Without auto-
clear, the cost of clearing an interrupt can be as high as two reads and one write.
• Interrupt Mask ‘Set’ (Read) and ‘Clear’ Registers
Interrupts appear on PCI only if the interrupt cause bit is a 1b, and the corresponding interrupt
mask bit is a 1b. Software can block assertion of the interrupt wire by clearing the bit in the
mask register. The cause bit stores the interrupt event regardless of the state of the mask bit.
The Clear and Set operations make this register more “thread-safe” by avoiding a ‘read-
modify-write’ operation on the mask register. The mask bit is set to a 1b for each bit written in
the Set register, and cleared for each bit written in the Clear register. Reading the Set register
returns the current value.

Intel accomplished the second goal (minimizing interrupts) by three actions:

• Reducing the frequency of all interrupts (see Section 13.4.17). Not applicable to the
82544GC/EI.
• Accepting multiple receive packets before signaling an interrupt (see Section 3.2.3)
• Eliminating (or at least reducing) the need for interrupts on transmit (see Section 3.2.7)
The third goal is accomplished by having one interrupt register consolidate all interrupt
information. This eliminates the need for multiple accesses.

Note that the Ethernet controller also supports Message Signaled Interrupts as defined in the PCI
2.2, 2.3, and PCI-X specifications. See Section 4.1.3.1 for details.

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2.7 Hardware Acceleration Capability

The Ethernet controller provides the ability to offload IP, TCP, and UDP checksum for transmit.
The functionality provided by these features can significantly reduce processor utilization by
shifting the burden of the functions from the driver to the hardware.

The checksum offloading feature is briefly outlined in the following sections. More detail about all
of the hardware acceleration capabilities is provided in Section 3.2.9.

2.7.1 Checksum Offloading

The Ethernet controller provides the ability to offload the IP, TCP, and UDP checksum require-
ments from the software device driver. For common frame types, the hardware automatically
calculates, inserts, and checks the appropriate checksum values normally handled by software.

For transmits, every Ethernet packet might have two checksums calculated and inserted by the
Ethernet controller. Typically, these would be the IP checksum, and either the TCP or UDP
checksum. The software device driver specifies which portions of the packet are included in the
checksum calculations, and where the calculated values are inserted via descriptors (refer to
Section 3.3.5 for details).

For receives, the hardware recognizes the packet type and performs the checksum calculations and
error checking automatically. Checksum and error information is provided to software through the
receive descriptors (refer to Section 3.2.9 for details).

2.7.2 TCP Segmentation

The Ethernet controller implements a TCP segmentation capability for transmits that allows the
software device driver to offload packet segmentation and encapsulation to the hardware. The
software device driver can send the Ethernet controller the entire IP, TCP or UDP message sent
down by the Network Operating System (NOS) for transmission. The Ethernet controller segments
the packet into legal Ethernet frames and transmit them on the wire. By handling the segmentation
tasks, the hardware alleviates the software from handling some of the framing responsibilities. This
reduces the overhead on the CPU for the transmission process thus reducing overall CPU
utilization. See Section 3.5 for details.

2.8 Buffer and Descriptor Structure

Software allocates the transmit and receive buffers, and also forms the descriptors that contain
pointers to, and the status of, those buffers. A conceptual ownership boundary exists between the
driver software and the hardware of the buffers and descriptors. The software gives the hardware
ownership of a queue of buffers for receives. These receive buffers store data that the software then
owns once a valid packet arrives.

For transmits, the software maintains a queue of buffers. The driver software owns a buffer until it
is ready to transmit. The software then commits the buffer to the hardware; the hardware then owns
the buffer until the data is loaded or transmitted in the transmit FIFO.

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Descriptors store the following information about the buffers:

• The physical address
• The length
• Status and command information about the referenced buffer
Descriptors contain an end-of-packet field that indicates the last buffer for a packet. Descriptors
also contain packet-specific information indicating the type of packet, and specific operations to
perform in the context of transmitting a packet, such as those for VLAN or checksum offload.

Section 3 provides detailed information about descriptor structure and operation in the context of
packet transmission and reception.

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