A MULTI-BAND PHASE-LOCKED LOOP FREQUENCY SYNTHESIZER

A Thesis

by

SAMUEL MICHAEL PALERMO

Submitted to the Office of Graduate Studies of

Texas A&M University
in partial fulfillment of the requirements for the degree of

MASTER OF SCIENCE

August 1999

Major Subject: Electrical Engineering

 A MULTI-BAND PHASE-LOCKED LOOP FREQUENCY SYNTHESIZER

A Thesis

by

SAMUEL MICHAEL PALERMO

Submitted to Texas A%M University

in partialfulfillment ol the requirements
for the degree of

MASTER OF SCIENCE

Approved as to style and content by:

Jo e Pineda d Gyves gar anchez-Sinencio

'
(C ommtttee) (Member)

Sh if H. K. Embabi Duncan M. H. Walker

(Member) (Member)

'Chanan Singh
(Head of Department)

August 1999

Maior Subject: Electrical Engineering

 ABSTRACT

A Multi-Band Phase-Locked Loop Frequency Synthesizer. (August 1999)

Samuel Michael Palermo, B.S., Texas A&M University

Chair of Advisory Committee: Dr. Jose Pineda de Gyvez

A phase-locked loop (PLL) frequency synthesizer suitable for multi-band transceivers is

proposed. The multi-band PLL frequency synthesizer uses a switched tuning voltage-

controlled oscillator (VCO) that covers a frequency range of 111 to 297MHz with a low

average conversion gain of 41.71MHz/V. A key design feature of the multi-band PLL
frequency synthesizer is that the VCO tuning switches are controlled only by the normal

loop dynamics. No external control is needed for the synthesizer to switch to different

bands of operation. The multi-band PLL frequency synthesizer is implemented in a

standard L2ttm CMOS technology using a 2. 7V supply. The frequency synthesizer has

a measured frequency range of I 1 1 to 290MHz with phase noise up to —96dBc/Hz at a

SOkHz carrier offset. Experimental comparisons of the multi-band PLL frcqucncy
synthesizer with a similar classic digital PLL frequency synthesizer show the multi-band

synthesizer to have a 20% greater frequency range, an average 7.3dB superior phase
noise performance, and similar acquisition time.
 DEDICATION

This work is dedicated to my wife, Shawn. Her gracious support and countless

sacrifices have allowed me to complete this great task.

 ACKNOWLEDGMENTS

I would like to thank my family for the support they have given over the years.
Especially my wife for providing me the gift of her infinite love. My mother deserves
special thanks for the endless encouragement. The support from my father is also

greatly appreciated.

I am extremely grateful for the contributions of all my committee members to my

research. They have provided me with the tools necessary for the research through their
courses and technical discussions. My advisor, Dr. Jose Pineda de Gyvez, deserves
special acknowledgment for thc support and guidance he has provided me throughout
the years.

1 thank all of the students in the Analog and Mixed Signal Group for their friendship and
technical support. I am extremely indebted to Antonio Mondragon for the CADFNCE

support, Fikret D(tiger for the high frequency design and testing suggestions, and Ajay

Kanji for the printed circuit board help.

 TABLE OF CONTENTS

Page

ABSTRACT
DEDICATION. . 1V
ACKNOWLEDGMENTS
TABLE OF CONTENTS . .. VI
LIST OF FIGURES . . . 1X

LIST OF TABLES. . XV1

INTRODUCTION .
Phase-Locked Loops. . .1
Phase-Locked Loop Frequency Synthcsizcrs .. . . . .. 3
Research Objectives. . .8

PLL DESIGN THEORY . 12

PLL Operation . . 12
Frcqucncy Synthesizer Architectures . . . . . 15
Frcqucncy Synthesizers with Prescalers . . . 16

Frequency Synthesizers with Dual-Modulus Prescalers. . . . ... . . . 17

Frequency Synthesizers with Four-lvlodulus Prescalers. . . . . . . . 19
Fractional N-Loop Frequency Synthesis. 21
Linear PLL Analysis. . 23
PLI Noise Analysis. .. 36
Input Phase Noise 37
VCO Phase Noise 39
Phase Detector Dead Zone ..41
Charge Pump PLLs. . ..42
Charge Pump PLL Linear Analysis . . . .44
Stability Analysis. . .45
Charge Pump PLL Building Blocks. . .47
Phase/Frequency Detector ..47
Charge Pump . 50
Loop Filter 52
Voltage-Controlled Oscillator
Loop Divider Circuitry . 56
A General Fully Integrated PLL Design Procedure 56
 Page
A MULTI-BAND PHASE-LOCKED LOOP FREQUENCY SYNTHESIZER ........, ... 61
The Multi-Band PLL System . .61
Multi-Band PLL Switch Conhol Mechanism .62
Multi-Band PLL Channel Design .. .65
The Multi-Band PLL System Design Methodology. .74
Mathematical Design and Modeling. . .77
Mathematical Design Procedure .77
Mathematical Model. .. ..80
Behavioral Model .83
Transistor Level Block Design. .88
Phase/Frequency Detector .88
Charge Pump . .94
Loop Filter . . 97

Switched Tuning VCO . . 100

VCO Switch Control System. . . 113
Loop Divider .. 122
Multi-Band PLL System Simulation Results .. 129
Case A. 130
Case B. . 132
Case C 133
Case D. 135
Case F 137
Classic Digital PLL Design and Simulation Results 138
Case A. 140
Case B. 142
Case C 144
EXPERIMENTAL RESULTS . .. .. 147
Building Block Verification . 147
Phase/Frequency Detector 148
Charge Pump . 150
Switched Tuning VCO .. 151
Switch Control State Machine . 157
Comparators with Hysterisis 159
Loop Di vi der. 161
Multi-Band PLL Frequency Synthesizer . . 164
Case A. 167
Case B. 169
Case C 171
Case D. 173
Case E 176
Classic Digital PLL Frequency Synthesizer 181
 ix

LIST OF FIGURES

FIGURE Page

PLL Block Diagram

Phase-Locked Loop Frequency Synthesizer.
Utilizing Switched Tuning to Achieve a Wide Tuning Range. ...
Multi-Band Phase-Locked Loop Frequency Synthesizer Block Diagram .....
Analog PLL Block Diagram. . . 12

PLL Regions of Operation. . 14

Classic Digital PLL Frequency Synthesizer Block Diagram .. .

PLL Frequency Synthesizer with Prescaler. . . 16

PLL Frequency Synthesizer with Dual-Modulus Prescaler .. . . . . . . . 17

10 PLL Frequency Synthesizer with Four-Modulus Prcscalcr. ... . . .... 20

Fractional N-Loop Frequency Synthesizer. 21
12 Linear PLL Model
13 Passive Lag Filter.
14 Pair of Complex Poles S-Plane Plot 27
Second Order PLL Frequency Response for Different Damping Factors. .. . .
16 Phase Step Applied to the Input Reference Signal
17 Phase Error Transient Response - Unit Phase Step Input. . . . .
18 VCO Control Transient Response — Unit Phase Step Input. .. .. .32
Frequency Step Applied to thc Input Rcfcrcncc Frequency. . . .. 32
20 Iffhase Error Transient Response —
Frequency Step Input 34
21 VCO Control Transient Response —
Frequency Step Input . . .
22 Periodic Signal with litter "6
23 Frequency Spectrum of' a Signal with Phase Noise
PLL Input Phase Noise Model
25 Input Phase Noise Frequency Response
26 PLL VCO Phase Noise Model
FIGURE Page
27 VCO Phase Noise Frequency Response. .41
28 Phase Detector Dead Zone .42
29 Charge Pump PLL .. ..43
30 Charge Pump PLL VCO Control Voltage Transient Response ... ........44
31 Addition of Cz in Loop Filter to Suppress Ripple ...46
32 Phase/Frequency Detector. ..47
33 Phase/Frequency Detector Signal Diagram. .
34 PFD Charge Pump Output Stage. 50
35 PFD, Charge Pump, and Loop Filter Interaction.
36 Loop Filter Frequency Response. 53
37 VCO Transfer Charactenstic.
38 LC Voltage-Controlled Oscillator. 55
39 Ring Oscillator. 55
40 Multiple Frequency Band Systems. . . .61
41 Multi-Band Phase-Locked Loop Frequency Synthesizer. .. . . .. .
42 VCO Control Voltage Response io a Frequency Step Input ...
43 Discrete Tuning System Mechanism. .. 64
44 Overshoot Causing Oscillation Between Frequency Bands. . . .. . . . . .65

45 Frequency Overlap and Cushion Introduced For Stability. .. . .

46 Determination of Frequency Overlap or Cushion . .67

4'7 Charge Pump and Loop Filter Interaction.

48 VCO Control Voltage Ripple Function. 70
49 Effect of Ripple on the VCO Control Voltage . 7l
50 PLL Oscillating Due to Insufficient Channel Overlap
51 PLL Locking with Sufficient Channel Overlap. . 74
S2 Multi-Band PLL Frequency Synthesizer Design Flow . . 76
S3 Multi-Band PLL Frequency Synthesizer Frequency Bands. . . . .. . . . .. . ..... . ....
54 Mathematical Macromodel of the Multi-Band PLL in the Lock Range . .. . . .8l
 xi

Page
55 Frequency Response of the Multi-Band PLL. .. .81
56 VCO Phase Noise Frequency Response of the Multi-Band PLL. ..... ....82
57 VCO Control Response to a Frequency Step Showing the Lock-In Time. . ...
58 Behavioral Macromodel of the PLL - Pull-In Process. .85
59 Linear PLL Model - Pull-In Process (No Cycle Slips). . .86
60 Behavioral PLL Macromodel with Switch Control Circuitry ..... .... 87
61 Multi-Band PLL Phase/Frequency Detector Circuit. .89
62 PFD D Flip-Flop Schematic .. ... .. .. 89
63 PFD AND Gate. 90
64 PFD D Fhp-Flop Design Flow Diagram 90
Phase/Frequency Detector Simulation Results.
66 Charge Pump Schematic. 95
Charge Pump Simulation Results. . 97
68 Fully Integrated Loop Filter 98
69 Loop Filter Capacitors . .. ..
70 Loop Filter 31.8kO Resistor Layout. .
71 Layout Extracted Frequency Response. 100
72 Switched Tuning VCO. 100
73 CMOS lnvertcr Delay Cell. 101
74 Ring Oscillator Model . . .. . 101

75 Capacitive Tuning
Switched Tuning VCO Design Flow Diagram. .. 106
77 Switched Tumng VCO Output Signal.
78 Switched Tuning VCO Transfer Curves . . . 113

VCO Switch Control System. . . . 114

80 Switch Control State Diagram. . . . 115

81 Switch Control State Machine .. 115

Switch Control State Machine Simulation Results . . 116
FIGURE Page
83 Positive Threshold NMOS Comparator. . 117
84 Negative Threshold PMOS Comparator . 117
85 Transfer Characteristic of a Comparator with Hysterisis ..... .... 118
86 NMOS Comparator with Hysterisis Transfer Characteristic. .... .... 121
87 PMOS Comparator with Hysterisis Transfer Characteristic . .... 122
88 Loop Divider Schematic. . 122
89 Dynamic D Flip-Flop Schematic. . . 123
90 Dynamic Divide-by-2 D Flip-Flop. . . . 123
91 Loop Divider D Flip-Flop Design Flow Diagram. . 124

92 Loop Divider Simulation Results. . .. , ... . . ... . . ... . . .. . . .. . . . . . . . . . . . . . . . . .. , 129

93 VCO Control Signals for Multi-Band PLL 310MHz Output. .. . . .... I 3 I
94 310MHz Multi-Band PLL Output Signal. I3I
95 VCO Control Signals for Multi-Band PLL 190MHz Output. .. .. . .. . . 132
96 190MHz Multi-Band PLL Output Signal.
97 VCO Control Signals for Multi-Band PLL 100MHz Output. .. . . . . . . 134

98 100MHz Multi-Band PLL Output Signal. . 135

99 VCO Control Signals for the Multi-Band PLL 340MHz Output. . ... ... .. 136
100 340MHz Multi-Band PLL Output Signal . . 136
101 VCO Control Signals for Multi-Band PLL 160MHz Output. . . .. . . .. . 137

102 160MHz Multi-Band PLL Output Signal . . 138

103 Classic Digital PLL V CO. 139
104 Classic Digital PLL VCO Transfer Curve. 139
105 VCO Control Voltage for Classic Digital PLL 380MHz Output. . .. . . . . . . 141

106 380MHz Classic Digital PLL Output Signal 142

107 VCO Control Voltage for Classic Digital PLL 230MHz Output. ....
108 230MHz Classic Digital PLL Output Signal 143
109 VCO Control Voltage for Classic Digital PLL Z60MHz Output. . . .. .... 144
110 260MHz Classic Digital PLL Output Signal. . . 145
FIGURE Page
111 Multi-Band PLL Building Blocks Prototype Chip. . . 147
112 Multi-Band PLL Building Blocks Test Board. . 148
113 Phase/Frequency Detector Experimental Results. .. . 149
114 Measured Average I» Output Current. . 150

115 Measured Average I»„~ Output Current. .151

116 Minimum Frequency VCO Output. . 152
117 Minimum Frequency VCO Output Frequency Spectrum .... .... 153
118 Maximum Frequency VCO Output. 154
119 Maximum Frequency VCO Output Frequency Spectrum. . .. . . .. 154

120 Experimental Switched Tuning VCO Transfer Curves. 156

121 Mid-Band Frequency VCO Output. 156
122 Mid-Band Frequency VCO Output Frequency Spectrum. . . . ... . 157
123 Non-Overlapping Clock Circuit 158
124 Switch Control State Machine Experimental Results . 159
125 Positive NMOS Comparator with Hysterisis Measurement Results. . .. . .. . .. 160
126 Negative PMOS Comparator with Hysterisis Measurement Results . .. . .. . . . 161
i 27 Loop Divider Operating at 510MHz . 162
128 Loop Divider Operating at 110MHz . 163
129 Multi-Band PLL Frequency Synthesizer Prototype Chip . .. ... . 164
130 Multi-Band PLL Frcqucncy Synthesizer Test Board. . 165
131 Initial Experimental 240MHz Multi-Band PLL Output Signal. . . .
132 Initial Experimental 240MHz Multi-Band PLL Output Frequency Spectrum. .. . ... . 166
133 Continuous VCO Control Voltage l'or Multi-Band PLL 270MHz Output .. .. . . .. . . .. . 167
134 Experimental 270MHz Multi-Band PLL Output Signal . . . . . .. . . . . . . . . . . . .. . . .. . . . . ... 168

135 Experimental 270MHz Multi-Band PLL Output Frequency Spectrum . . . . . . .. 168

136 Contmuous VCO Control Voltage for Multi-Band PLL 190MHz Output . . .. . . . . . . . .. 169

137 Experimental 190MHz Multi-Band PLL Output Signal . . . . . . . . . . 170

138 Experimental 190MI-Iz Multi-Band PLL Output Frequency Spectrum .. . . . .. 170

 xtv

Page
139 Continuous VCO Control Voltage for Multi-Band PLL 111MHz Output .............171
140 Experimental 111MHz Multi-Band PLL Output Signal ... .... 172
141 Experimental 111MHz Multi-Band PLL Output Frequency Spectrum ... .... 172
142 Experimental 110MHz Multi-Band PLL Output Frequency Spectrum ... .... 173
143 Continuous VCO Control Voltage for Multi-Band PLL 290MHz Output ............. 174
144 Experimental 290MHz Multi-Band PLL Output Signal .... ... ... . ........ ..... .. .... 175
145 Experimental 290MHz Multi-Band PLL Output Frequency Spectrum .. . .. .. 175
146 Experimental 291MHz Multi-Band PLL Output Frequency Spectrum ... .. . . 176
147 Continuous VCO Control Voltage for Multi-Band PLL 160MHz Output ....... .. .... 177
148 Experimental 160MHz Multi-Band PLL Output Signal . . . . . . . . . . . . .. . . . .. . . .. . . . . .. . 177

149 Experimental 160MHz Multi-Band PLL Output Frequency Spectrum . . . . . . .. 178

150 Experimental Multi-Band PLL Frequency Response 179

151 Experimental Multi-Band PLL Phase Noise Performance. .... . .. . . 180

152 Classic Digital PLL Prototype Chip. , 181

I 53 Classic Digital PLL Test Board. 182
154 Initial Expcrimcntal 340MHz Classic Digital PLL Output Signal. . ... . . . .. 183

155 Initial Experimental 340MHz Classic Digital PLL Output Frequency Spectrum. . . 183
156 VCO Control Voltage I'or Classic Digital PLL 370MHz Output . .. . . . . . . . 184

157 Experimental 370MHz Classic Digital PLL Output Signal . .. . . .. . . ... .

158 Experimental 370MHz Classic Digital PLL Output Frequency Spectrum ...... . ...... 185
159 Classic Digital PLL Failing To Synthesize 371MHz. . . 186

160 VCO Control Voltage for Classic Digital PLL 221MHz Output. .. .. . .. . . 187

161 Expcrimcntal 221 MHz Classic Digital PLL Output Signal . . . . . . . . . . .. . .. . . 187

162 Experimental 22IMFIz Classic Digital PLL Output Frequency Spectrum ....... . . ... . 188
163 Experimental 220MHz Classic Digital PLL Output Frequency Spectrum . ... . ... . ... . 189
164 VCO Control Voltage for Classic Digital PLL 250MHz Output. . . .. ... . 190
165 Experimental 250MHz Classic Digital PLL Output Signal . . . ... . ... .. . . . .. . 190

166 Experimental 250MHz Classic Digital PLL Output Frequency Spectrum . . ... ... . . ... 19 I
 xv

FIGURE Page
167 Experimental Classic Digital PLL Frequency Response. .... .... 192
168 Experimental Classic Digital PLL Phase Noise Performance. .... .... 193
 xv1

LIST OF TABLES

TABLE Page
State-of-the-Art PLL Implementations.
Dual-Modulus Prescaler FS Modulus Combinations with V=10...... .... 19
Four-Modulus Prescaler FS Scaling Factors Truth Table . .. ....20
Recent Integrated LC Voltage-Controlled Oscillator Results ..... ....55
Recent Integrated Ring Voltage-Controlled Oscillator Results ... ....56
Multi-Band PLL Frequency Synthesizer Specifications. .74
Summary of Multi-Band PLL Frequency Synthesizer System Parameters . .. . ... 80

AMII. 2lt CMOS Process Technology Parameters. .. .. ... . ..88

PFD D Flip-Flop Size Ratios.
10 PFD AND Gate Size Ratios 93
Charge Pump Size Ratios.
12 Switched Tuning VCO Transistor Sizes and Capacitor Values . . . .. ... . 110
Switched Tuning VCO Frequency Response 112
14 Comparators with Hysterisis Transistor Sizes. . 120
15 Dynamic Flip-Flop Transistor Sizes. . 128
16 Multi-Band PLL Frequency Synthesizer Case Studies. 130
17 Classic Digital PLL Frequency Synthesizer Case Studies . . . .. . . . 140
18 Comparison of Multi-Band PLL and Classic Digital PLL Systems. . . . .. . . . 146
19 Experimental Switched Tuning VCO Performance 155
20 Multi-Band PLL Frequency Synthesizer Experimental Case Studies. . .. . . .. . . 165

Experimental Multi-Band Pl I Results. . . 179

22 Classic Digital PLL Frequency Synthesizer Experimental Case Studies. ... ..... 182
23 Multi-Band and Classic Digital PLL Experimental Performance Comparison 194
 INTRODUCTION
The explosion of the wireless communications industry into areas such as cellular
telephony, wireless local area networks, and the Global Positioning System has led to
several wireless standards operating at frequencies ranging from 900-5200MHz. Multi-
standard transceivers used for these systems should be able to operate over a wide

frequency range with minimal amounts of duplicated hardware[1]. A critical element of

any transceiver is the frequency synthesizer(FS). A multi-standard frequency
synthesizer must be able to synthesize different bands of frequencies for the different
wireless standards. Instead of a typical single-band frequency synthesizer that is

commonly used to synthesize a narrow frequency hand, a multi-band frequency

synthesizer is needed to synthesize multiple frequency bands. A multi-band frequency
synthesizer must be able to synthesize a wide range of frequencies while satisfying strict
phase noise specifications. This poses a challenging design problem. The typical phase-
locked loop (PLL) frequency synthesizers used in transceivcrs are normally designed
and optimized for narrow band operation. Architectural changes should be made to the
typii:al loop structure in order to achicvc operation over a v'ide I'requency range for
multi-band transceivers.

Phase-Locked Loops
The phase-locked loop circuit has been around for quite some time. Appleton's work on
oscillator synchronization in the early 1920s and de Bellescize's work in the area of
coherent communications in the early 1930s introduced the phase-locked loop to the
scientific community[2]. The basic phase-locked loop circuit synchronizes an output

signal with an input reference signal. The output signal has the s:ime frequency as the

input reference signal and also a constant. phase difference. A block diagram of a simple

phase-locked loop is given in Figure I.

This thesis lollows the style and format of IEEE Transactions an Circuits and Systems.
 Low
Phase "8 "Oui
Pass VCO
Detector Filter

Figure 1 - PLL Block Diagram

The phase-locked loop works by comparing the reference signal, v y, with the voltage-
controlled oscillator's (VCO) output, v, „, . An error signal, v, , is produced that is

proportional to the phase difference of the reference signal and the output signal. This
error signal is filtered to generate the voltage-controlled oscillator control voltage, v, .
The loop is setup in a negative feedback fashion so the voltage-controlled oscillator
control voltage will force the output of the voltage-controlled oscillator to lock with thc
input reference signal within certain frequency hmits.

Advances in integrated circuit technology allowed phase-locked loop circuits to be used

commonly in many areas such as communications, wireless systems, consumer
electromcs, and motor control[2-7]. The phase-locked loop is used in motor control to
synchronize the motor speed to a reference frequency with estreme accuracy[2, 8]. The
phase-locked loop is used in the area of consumer electronics for applications ranging
from television sets to microprocessors. The phase-locked loop performs the horizontal
and vertical synchronization and color subcarrier reconstruction in television sets[7].
The phase-locked loop is used in microprocessors and other digital circuits to generate a

low )itter clock signal[3]. Typical communications applications include clock and data

recovery, coherent demodulation of amplitude (AM), frequency (FM), and phase-

modulated (BPSK) signals, phase-locked loop receivers, and frequency synthesis[3, 5, 9].
Phase-Locked Loop Frequency Synrhesizers
The PLL can be used as a frequency synthesizer by placing a loop divider in the

feedback path as shown in Figure 2.

Phase V Low v OUI

V
ref
Detector Pass VCO
Filter

l /N

Figure 2 - Phase-Locked Loop Frequency Synthesizer

Here the output frequency, f„„,, is related to the input reference frequency, f e, by the
I'ollowing equation:

f„„, = &f„, = f0+ v,

~
Kvio

where f„ is the VCO center frequency and K,,co is the VCO conversion gain.

Adjusting the division factor or modulus can change the frequency that the PLL

synthesizes.

The economics of the electronics industry has led to a trend towards mcreased
integration. One goal of many communications system engineers and integrated circuit
designers is to have a smgle-chip transceiver. This chip would perform functions such
as radio frequency (RF) up/down conversion and baseband digital signal processing on

the same die with no external components. At the present time this goal has not yet been
achieved at the production level. This is duc to the fact that many of the filtering
components used in the RF up/down conversion remain off-chip. Also, the majority of
the RF up/down conversion is done in bipolar technology, while most of the digital
signal processing is performed with a complementary metal-oxide semiconductor
(CMOS) technology. Combining these two technologies is costly.

The quality of the frequency synthesizer is a key element in the design of a transceiver.
Typically, the frequency synthesizers used in radio frequency communications are
designed in a bipolar technology with off-chip filtering components. Recent research
efforts have been directed towards achieving a fully integrated RF CMOS frequency
synthesizer. Table 1 shows the recent research done in the area of PLL frequency
synthesizer design.

With the increased interest in multi-band systems, a frequency synthesizer that operates

over multiple bands becomes a necessity. There are many challenges faced in designing
a multi-band CMOS frequency synthesizer. The research efforts in [10-15]
concentrating on narrow (single) band frequency synthesizcrs and do not have the

frequency range necessary for multi-hand systems. A wide frequency range is achieved
in [16]. However, this is still not wide enough to synthesize the frequencies necessary in
multi-band systems. A suitable frequency range is achieved in [17]. However, the

power supply of 5V is noi. suitable I'

or many portable applications. The work done m
[I g] achieved a very wide frequency range. However, it was achieved with a translinear
architecture that cannot be realized effectively in a typical CMOS process. In [19],
complex digital to analog converter control is used to achieve a wide frequency range.
A double-loop architecture is used to achieve a wide frequency range in [20]. However,
this double-loop architecture requires elfectively twice the circuitry as the standard

single-loop phase-locked loop. This is also observed in typical dual-band synthesizers

on the market today. They utilize multiple phase-locked loops with narrow band

voltage-controlled oscillators that operate at different center frequencies[21].

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A multi-band frequency synthesizer should be realized in a manner that does not
increase the loop complexity significantly. An optimal design would be implemented in

a typical CMOS process using the power supplies typically found in portable products.

A design approach that minimizes the amount of replicated circuitry is to increase the
VCO tuning range in such a way that the PLL loop dynamics are not drastically affected.

The integrated VCOs used in frequency synthesizers generally have limited tuning

ranges or conversion gain, K«e. The most common integrated VCO used in RF

systems is the LC oscillator because of superior phase noise performance[22]. However,

this type of oscillator suffers from a very limited tuning range because it is tuned with

varactor capacitors that generally make up only 25% of thc total tank capacitance. One

way lo increase the tuning range of the oscillator is to discretely switch in different

capacitive or inductive loads. The use of switched tuning elements to increase the
oscillator's tuning range is an old design tcchmque that been seen in recent
research[]0, 23,24]. The concept of switched tuning is illustrated in Figure 3.

High K „ Channel 4

Channel 3

Channel 2

O
C Channel 1
0)
CT
Q) Low I(„,
LL

VCO Control Voltage

Figure 3 - Utilizing Switched Tuning to Achieve a Wide Tuning Range

Here a wide frequency range is realized by splitting the entire range into four bands of
operation. The oscillator changes between the different bands of operation by discretely
switching in the different loads. The low K«c multi-band voltage-controlled oscillator

can be used to synthesize the same frequencies as a high K«p oscillator through the use

of switched tuning. This property of switched tuning also aids in the noise performance

of the oscillator.

Noise in the control path of a voltage-controlled oscillator translates directly into phase
noise in the output signal by frequency modulation. This phase noise degrades the
synthesizer's peiformance and causes the communication system to have a higher bit
error rate (BER). If the noise on the control line of the voltage-controlled oscillator is

modeled as V, „cosrti, „t, the output of the voltage-controlled oscillator will be the

followmg assuming a narrow band frequency modulation approximation[22]:

AV "' K
v„„,(i)= A, cosrii t+ [cos(ru +m )r —cos(ru„—ni )tL (2)
2iu

The noise power at ni„+ tii„, with respeci to the carrier power is equal to the following:

Therefore, the phase noise due to control linc noise is directly proportional to the square

of the voltage-controlled oscillator's conversion gain, K,, «.

The voltage-controlled oscillator's conversion gain must be very large to synthesize a

wide range of frequencies if the architccturc of Figure 2 is used for a multi-band

frequency synthesizer. However, such large conversion gains are not available with

conventional integrated voltage-controlled oscillators. Also, the previous analysis shows

that this will result in poor phase noise performance. This makes a phase-locked loop
with a switched tuning voltage-controlled oscillator ideal for a multi-band frequency
synthesizer because it can tune over a wide range while maintaining a low conversion
gain, The system is to be designed with sufficient overlap between the frequency bands.
This insures that no switching will take place after the multi-band phase-locked loop has
acquired lock. The block diagram of a multi-band phase-locked loop frequency
synthesizer utilizing a switched-tuning or multi-band voltage-controlled oscillator is
shown in Figure 4.

Switch Control

Phase v Low v Switched v„,

Detector Pass Tuning
Filter VCO

/N

Figure 4 - Multi-IIand Phase-Locked Loop Frequency Synthesizer Block Diagram

Here the output frequency, f„„,, is related to thc input refcrcncc frequency, f„, , by the

fogowing:

f„„, = Nf„q f„+v, K)s.n

——
(4)
where f„ is the VCO center frequency for n = 1.2, . . . , n bands.

Research Objectives
Most of the work presented up to date in fully integrated frequency synthesizer

design has been with the traditional (single-band) VCOs [11-13]. Whde some work has

been done with switched tuning oscillators [10,24), their effort was mostly concentrated
on overcoming process variations and not in designing multi-band frequency
synthesizers. A multi-band frequency synthesizer realized using a PLL with a switched
tuning VCO should be done in a manner that does not increase the loop complexity
significantly. The synthesizer should be designed in a typical CMOS process using the
power supplies typically found in portable products.

The main objective of this research is to design and implement a multi-band phase-
locked loop frequency synthesizer. A synthesizer that operates from 100 to 300MHz is

designed in a 1.21t nwell CMOS process as a proof of concept that the switched-tuning
VCO structure is suitable for a multi-hand synthesizer. A key design feature in the
multi-band phase-locked loop frequency synthesizer is that thc switch control will be
controlled only by the loop dynamics (VCO control voltage) —no external control is
needed. This multi-band PLL frequency synthesizer poses several open-ended questions
that need addressing for the optimal silicon implementation. Thc main research
objectives can bc enumerated in the following manner:

1. Mathematical formulation of the first integrated single-loop multi-band PLL

frequency synthesizer.
2. Design of a fully integrated multi-band PLL frequency synthesizer.
3. IC Fabrication and testing of the multi-band PLL frequency synthesizer.
4. Experimental performance analysis of the multi-band PLL frequency synthesizer.

The first iwo objectives involve the analysis, design, and simulation of the multi-hand
phase-locked loop frequency synthesizer. Trade-offs regarding noise performance,
frequency range, stability, and silicon area are studied. The design parameters arc
obtained through mathematical analysis and behavioral simulation. These design
parameters are used to implement the multi-band PI, L I'requency synthesizer in a 1.2N
nwell CMOS process.
 10

The third objective involves the layout, fabrication, and testing of the multi-band PLL
frequency synthesizer. This objective is undertaken after the design of the system has
been completed through the first objective. The layout is accomplished with good

matching and high-frequency techniques. The integrated circuits are fabricated through
the MOSIS foundry using the AMI1. 21t CMOS process. Three prototype chips are sent
for fabrication. The first prototype chip includes the multi-band frequency synthesizer
blocks for individual characterization. The second prototype chip includes the multi-
band PLL frequency synthesizer. The third prototype chip has both the multi-band PLL
frequency synthesizer and a wide band classic digital PLL frequency synthesizer for
comparison. The prototype circuits will be tested in the Analog and Mixed Signal Group
Laboratory. High frequency printed circuit boards will be developed to test the

prototypes. The prototypes will be tested with the aid of external components and

through measurement equipment.

The fourth objective involves the performance evaluation of the experimental

prototypes. The building blocks will be cvaluatcd for individual performance outside of
the system. The multi-band PLL frequency synthesizer will be evaluated in terms of
frequency range and phase noise performance. A comparison between the multi-band

PI.L frequency synthesizer and a wide band classic digital PLL frequency synthesizer
will be made.

The following topics will be discussed in the remiunder of the thesis:

~ PLI. Design Theory- The mathematics behind the linear and charge pump PLL are

developed. PLL noise analysis is discussed. The charge pump PLL building blocks
are descnbed. Also, a general fully integrated PLL design procedure is presented.
~ A Multi-Band Phase-Locked Loop Frequency Synthesizer- The multi-band PLL
frequency synthesizer design methodology is presented. The mathematical and

behavioral model is explained. The transistor level design and layout is also

prcscntcd.
 11

~ Experimental Results- The experimental results of the three prototype chips are
presented. A performance comparison is made between the multi-band and the

classic digital PLL frequency synthesizers.

~ Conclusions- The goals accomplished through the work of this thesis are
summarized.
 12

PLL DESIGN THE()RY

In this section the basic operation of the phase-locked loop is explained, along with a
presentation of frequency synthesizer architectures. A formal mathematical analysis for
the linear and charge pump PLL is shown as well. It includes stability conditions and
noise performance characteristics that shape the way the PLL is designed. These overall
system design considerations are given in this section. Finally, the building blocks for a

charge pump PLL are explained and a general fully integrated PLL system level design
procedure is included.

pLL Operari on
The phase-locked loop is a circuit that synchronizes the frequency generated by an
oscillator with the frequency of a reference signal by means of the phase difference of
the two signals. The oscillator's output has the same frequency as the mput reference

frequency and also a constant phase difference. The PLL utilizes three basic blocks to
perform this phase and frequency synchronization.

The first block is the phase detector. The phase detector compares the phase difference
between the input reference signal and the oscillator's output signal. Thc output of the
phase detector is a function of the phase difference between the reference and output
signal. The main difference between the classic digital PLL and the analog PLL is that
the classic digital PLL uses logic gates to realize the phase detector, while the analog

PLL uses a multiplier. A classic analog PI.L is shown in Figure 5.

Phase Loop VCO

Detector Filter
v ref

Figure 5 - Analog Pl. l. Sleek Diagram

 I3

Assuming a sinusoidal reference frequency, u z(t)= Acus(co, r+8, ), and a sinusoidal

output signal, v, „, (r)= Bcos((u. r+8, ), the phase detector output, v„, is equal to the

following:

u (I)= (cos[(N —ru ) I'+8 8 ]+cps[(iu +N ) i+8 +8 ] I

2

where K „„ is the conversion gain of the multiplier. This phase detector output has a

low frequency component that is a function of the phase difference of the two signals
and a high frequency component that is a function of the phase summation of the two
signals,

The second block is the loop filter. The loop filter is a low pass filter that filters the

output of the phase detector to produce the VCO control voltage, v„. For the analog
PLL, the loop filter removes the term in the phase detector output that is a function of
the phase summation of the two signals in ( 5 ). In the classic digital PLL the loop filter
averages the phase detector output.

The third block is the voltage-controlled oscillator. The voltage-controlled oscillator

produces an output signal, u„„, , with an angular frequency, riiu„, , that is controlled by the

output voltage of the loop filter, v, , by the following relationship:

n„. (i)=rp, +Aalu„„(r)=m, +Ku, pi

, (r)

where m, is thc center frequency of the VCO and Kicp is the voltage-controlled
oscillator's conversion gain. The output phase is equal to the integral over the frcqucncy

variation Ani„, u (t ) .

()„„(r)=JAr~„„, (r)dt = Ku„ f u (r)dt

 14

The PLL has four basic regions of operation shown in Figure 6. These regions describe
the PLL in dynamic and static states. The PLL is in a dynamic state when the output
signal is not locked or synchronized with the reference frequency in frequency and

phase. The PLL is in a static state when the output signal is locked with the reference
frequency. The four regions of operation are the hold range, pull-in range, pull-out
range, and the lock range.

—--—— -Static Stability Limit

Dynamic Stability Limit

aac& e

M(c i

Conditionally Stable
Dynamicaliy Unstable

Figure 6 - PLL Regions of Operation

The hold range, Lt, ro», describes the PLL in a static or locked state. The hold range is

the frequency range in which a PLL can statically maintain phase tracking[7). The PLL
is initially locked with the reference signal. If the rcfcrcnce signal's frequency is slowly
reduced or increased too much the PLL will loose lock at the edge of the hold range.
The PLL is conditionally stable only within the hold range.

The pull-out range, tt co«, also describes the PLL in a static state. The pull-out range is

the dynamic limit l'or stable operation/7). Thc pull-out range is the value of a frequency
step applied to the reference frequency that causes the PLL to unlock. Thc PLL is
imtially locked with the reference signal. If a frequency step that is less then thc pull-out
range is applied to the reference signal the PLL will remam in lock. However, if the
frcqucncy step exceeds the pull-out range, the PLL will not be able to track the output
 15

signal and will fall out of lock. The PLL may acquire lock again, but it may be a slow
pull-in process.

The pull-in range, Atu«, describes the PLL in a dynamic state or an acquisition mode.

The pull-in range is the range within which a PLL will always become locked through
the acquisition process[7]. The PLL is initially unlocked. The PLL will acquire lock if a
reference frequency within the pull-in range is applied. However, if the reference

frequency is outside the pull-in range, the PLL will not be able to lock onto the reference
signal. The process of acquiring lock in thc pull-in range may be a slow pull-in process.
However, if the reference frequency is inside a subset of the pull-in range, the lock
range, the PLL will acquire lock rapidly.

The lock range, Auric, is a subset of the pull-in range. The lock range is the frequency

range in which a PLL locks within a single-beat note between the reference frequency
and output frequency. The PLL is initially unlocked. The PLL will acquire lock within
a beat-note between the reference frequency and the output frequency if a reference
frequency within the lock range is applied. The lock time will be a slower pull-in
process if a reference frequency outside of the lock range is applied. Thc normal
operation of thc PLL is generally restricted to the lock range.

Frequency Synthesizer Architectures

A frequency synthesizer is a system that generates different output frequencies from a

given input refcrcncc frequency. The majority of frequency synthesizers utilize a classic

digital PLL with a loop divider m thc feedback path as shown in Figure 7. This system
produces an output frequency equal to the input rcfcrcncc frequency times the division

factor, 1V . The division factor or modulus can be changed to synthesize different

frequencies. The technique used to vary the modulus difl'ers with the type of frequency
synthesizer architecture that is used.
 16

Phase Low vc v
Detector Pass vco
Filter

Programmable
Divider
1/N

Modulus Control

Figure 7 - Classic Digital PLL Frequency Synthesizer Block Diagram

Fre uenc S nthesizers with Prescalers

PLL frequency synthesizers with prescalers can be used lo generate higher output
I'requencies. The prescaler is a frequency divider that is capable of operating at high
VCO output frequencies. The prescaler divides the VCO output frequency by a factor of
V . This value V is not tunable. These prescalers are typically designed using dynamic
or current mode logic techniques[1L2S-30]. Generally 1'ollowing the prescaler is

another divider stage that is programmable. A block diagram of a PLL frequency

synthesizer with a prescaler is shown in Figure 8.

Phase Low v OUI

Detector Pass vco

Filter

vrs

Programmable Prescaler
Divider /v
1/N

Modulus Control

Figure 8 - PLL Frequency Synthesizer with Prescaler

 17

This system produces an output frequency related to the input reference frequency by the
following:

f. = VNf„/ (8)
The addition of the prescaler allows for the synthesis of frequencies well into the GHz

range with state-of-the-art submicron technologies.

Fre uenc S nthesizers with Dual-Modulus Prescalers

Prescaler frequency synthesizers only generate frequencies that are multiples of Vf„z . A

dual-modulus prcscaler can be used in order to get higher resolution. A dual-modulus

prescaler allows the prescaling factor to be changed between V and V+1. A block
chagram of a PLL frequency synthesizer with a dual-modulus prcscalcr is shown in
Figure 9[7,3 l ].

Phase v Low v e
v ref VCO
Detector Pass
Filter

tb

Divider /N,
2-Modulus
Prescaler
Load V/V+1

Divider/Nz
Control; Add+I

I'igure 9 - PLL Frequency Synthesizer with Dual-Modulus Prescaler

Thc frequency synthesizer uses the /N, and the /N, down counters. The output of

these counters is HIGH if the counter content has not reached zero. The counters are
loaded with their preset values, N, and N, , when the /N, counter counts to zero and its
 18

output goes LOW. N, must be greater than or equal to N, . N, must be less than V for

correct operation. The IN, counter stops counting when it reaches zero and its output

remains LOW until it is loaded. While the output of the IN, is not zero, the prescaler

divides by V+1, and the VCO generates N, (V +1) pulses. The prescaler divides by V

when the output of the IN, counter reaches zero and the VCO generates (N, —N, ) V

pulses until the I N, counter counts to zero. This causes the total number of pulses, N„„
generated by the VCO during a full cycle of the reference signal to be equal to the

following:

N( ( Nz (V + 1) + (Ni Ni )V: NiV + Ns

This results in an output frequency, f,„, , equal to the following:

J, , = (N, V + N, )A„, (10)

~Exam le: Assume a prescaler with V =10
From ( 9 ), this results in the total number of pulses generated by the VCO during
a full cycle to be equal to thc following:

N„„=ION, +N, (11)

The valid ranges for the counters are the following:

0&N, &9kN, &9 (12)

The smallest modulus is 90. This means the lowest possible output frequency is
90 times the refcrencc frcqucncy. Table 2 gives some ol' the possible modulus

and frequencies that can be generated with different combinations of N, and N,

using a reference frcqucncy of 10kHz.
 Table 2 - Dual-Modulus Prescaler FS Modulus Combinations with V=10

Output Frequency
Modulus
(F„r —10kHz)
90 900kHz
910kHz

99 990kHz
100 10 1MHz
101 10 1.01MHz

108 10 1.08MHz
109 10 1.09MHz

If there is a nccd to increase the frequency, either N, or V has to be increased.

Typically, V is increased because of the technology limitations of the /N, down

counter. If V is increased to 100 (which implies N, is in the range from 0-99, and N,
& 99) the minimum modulus would bc 9900. This results in a minimum output

frequency of 99MHz with a reference frequency of l 0kHz. The dual-modulus FS allows

for increasing the frequency resolution, but it also causes the minimum frequency to
increase.

Fre uenc Svnthesizers with Four-Modulus Prescalers

The four-modulus prescaler frequency synthesizer is able to extend thc upper frequency

range, while still allowing the lower frequencies to be synthesized. The four-modulus
prescaler provides four different scaling values controlled by two signals. A block

diagram of a four-modulus prescaler frcqucncy synthesizer is shown in Figure 10[7,31].

 20

Phase Low vc
Detector Pass 1/co
Filter

Divider /N, si Modulus

Prescaler
Load 100/101/1 10/111

Divider /N, Add+10 Add+1

A B

Load

Divider /Ns

Figure 10 - PLL Frequency Synthesizer with Four-Modulus Prescaler

The four-modulus prescaler has the decimal scaling factors 100, 101, 110, and 111.
These scaling factors are selected based on the control signals A & 8 according to the
truth table shown in Table 3.

Table 3 - Four-Modulus Prescaler FS Scaling Factors Truth Table

B Scalin Factor
100
101
110

Thc frequency synthesizer uses three down counters: IN, , IN, , and IN, . The

operation is similar to the dual-modulus prescaler frequency synthesizer. Thc total

number of pulses, N„„, generated by the VCO during a full cycle of the reference signal
is equal to the following:

N„v =100*N, +10*N, + N, (13)

 21

This results in an output frequency, f.„, , equal to the following:

f w
= (100N, +10N2 + 3)AJ (14)
N, and N, must be in the range from 0-9 and N, must be greater than or equal to both

N, and N, for correct operation. This results in a minimum division factor of 900.
This means that with a 10kHz reference signal the lowest frequency that could be

synthesized is 9MHz. A dual-modulus prescaler frequency synthesizer with the same

resolution would result in the lowest synthesizable frequency of 99MHz.

Fractional N-Loo Fre uenc S nthesis

The previous frequency synthesis techniques all descrtbed ways to synthesize
frequencies that are integer multiples of the reference signal. Fractional N-Loop
Frequency Synthesizers allow the synthesis of frequencies that are fractional multiples of
thc reference signal. A block dtagram of a fractional N-loop frequency synthesizer ts

shown in Figurc 1 1[7, 31].

Phase Low
v, i
Detector Pass vco
Filter
etre

Pulse
vi /N Removing
Counter Circuit
mcdulus control remove control

DAC

OVF
ADD ACCU

F Register N Register

Scale Factor

Ftigure 11 - Fractional N-Loop Frequency Synthesizer

 22

The fractional n-loop frequency synthesizer works by varying the scaling factor between
different values and using its average.

~Exam le: It is desired that the VCO generates 67 pulses for every 10 full
cycles of the reference signal. This corresponds to the following scale factor.

Scale Factor = 6.7 (15)

This resolution could not be realized by only using integer prescalers. Integer
prescalers would only allow a modulus of 6 or 7, which would result in 60 or 70
pulses generated for 10 reference cycles. Fractional N synthesis allows dividing

by 6 during three of the ten reference cycles and dividing by 7 during seven
reference cycles to realize the scale factor of 6.7.

Thc mteger of the scaling factor (6.7) is stored in the N register and the fraction
is stored in the F register. The IN counter divides by 6 during the first

reference cycle. An error of 0.7 is added to the accumulator at the beginning of

every cycle. The accumulator's contents overflow during the second cycle. The
overflow signal is sent to a pulse removing circuit that removes onc of thc pulses
generated by the VCO. The pulse removal effectively increases the division to 7
instead of 6. Seven overflow pulses will be generated during the duration of ten
reference cycles. This corresponds to dividing by 6 during three of the ten cycles
and dividing by 7 during seven cycles.

One problem associated with fractional n-loop frequency synthesizers is that spurs get
generated at the VCO output due to thc time-manipulation of the divider modulus.
These spurs can be compensated using various techniques. DAC analog compensation,
shown in Figure 11, can yield a typical 10 to 20 dB improvement in spurs[7, 30,31J. This
type ol compensation is dependent on the divisor and the phase detector gain. The spurs

can also be compensated digitally by using a DSP to generate compensating

 23

waveforms[30]. This digital compensation has an advantage over the analog technique

by being independent of the divisor.

Linear PLL Analysis

The PLL is a highly non-linear system[32]. However, it can be described with a linear
model if the loop is in lock. The loop is in lock when the phase error signal produced by

the phase detector settles on a constant value. This implies that the output signal has the

same frequency as the input reference signal. A phase difference between the reference
and output signal may exist depending on the type of PLL used. However, this phase
difference remains constant while the loop is in lock. If the PLL is used as a frequency

synthesizer, the output signal will have a frequency N times the refcrcncc frequency.
The butlding blocks of Figurc 12 are taken as basis for the mathemattcal model of a PLL
in lock. A loop chvision factor, N, is included in this model. N can be considered

equal to one for PLLs with no loop dividers. The following analysis shows step by step
how to obtatn the PLL transfer function:

H (,) Ital
(16)
0„,

Phase Loop
Detector Filter VCO

e. V
Kvco eoa
Krc F(s) s
J
0|b

Loop
Divider

Figure 12 - Linear PLL Model

 24

Note that the phase detector sums the input reference phase, 0„r, with the feedback

phase, 0&, and amplifies the difference with a gain Ksn to produce an error voltage,

V, (s), equal to:

(17)
V, (s)= K [0„r (s)—0,„, (s)]= K, 0, (s)

This error voltage is filtered by the loop filter to produce the VCO control voltage that is
equal to the following:

V, (s) = V„(s)F(s) (18)

Recall from ( 7 ) that the VCO can be modeled as a phase integrator. This results in an

output phase, 0,„, , equal to the following:

V„(s)Kvco (19)
() s

The output phase is fed back and passes through a loop divider where it is divided by a

factor of N to generate the feedback phase, 0&, , equal to the following.

0„. () (20)
0 () ,

The transfer function of the PLL, FI(s), is equal to the following:

0„„,(s) Kr„K„,F(.)
(21)
N

The phase error transfer function is equal io the following:

O,, (s) s
K„KK/'K ( 22 )
si
N
 25

The VCO control voltage transfer function is equal to the following:

V (S) SKpnF(S)
() KKK, F K
(23)
N

The following observations are made from the transfer functions given in ( 21 ), ( 22 ),
and ( 23 ). The PLL transfer function, given in ( 21 ), has a low-pass characteristic with
a gain of N . This means that for slow (low frequency) variations in the reference phase,
the loop will basically track the input signal and produce an output phase that is N
times larger. Thus the output frequency is N times the input reference frequency. The
phase error transfer function, given in ( 2" ), has a high-pass characteristic. This imphes
that for slow variations in the reference phase, the phase error will be small. However,
fast (high frequency) variations in the reference phase will not be filtered and shovv up as
a phase error. The VCO control voltage transfer function can be viewed as the filtered
phase error output. It also has a high-pass characteristic. However, depending on the

parameters of the loop l'ilter, it can take on a more band-pass shape.

The dynamics of the PLL are depcndcnt on the type of loop filter used. Without loss of
generahty consider the passive lag filter shown in Figure 13 which is a common filter
used in PLL design[7].

R,
v ~ v
hfdf

Rs

Figure 13 - Passive Lag Filter

 26

This filter is very simple to build and proves to be adequate in most applications. If
filter gain is necessary for increased tracking accuracy, active filters with a high gain
opamp may be used. The transfer function of the passive lag filter is the following:

V, (s) sCR, +1
V (s) sC(R] + Ri )+ 1 (24)

Substituting ( 24 ) into ( 21 ) we obtain the PLL's transfer function.

sCR, +1
K po Kvco
C(R, +R, )
FI (s)—
p]oCR + N
(2S)
z Kpo KpoKpco
NC(R] + R
) NC(R] + Ri )

lt can bc observed that using a first order filter in the PLL results in a second order
system. In fact, the order of a PLL ]s equal to the loop filter order plus one.

The second order PLL system can be described in a standard control system format as
follows:

2' — Nco, ',—

po pco
— + Oi, p

() (26)
s ' + 2/to„s + oi„'

where

1 KpnKvco N
CR, + (27)
2 NC(R] + R, ) K paKp„o

and

K] o Kvco
p (28)
NC(R, + R, )
 27

The parameter ( is the damping factor and ru„ is the natural frequency. An s-plane plot

shown in Figure 14 is used to explain these parameters [33].

Im(s)

0 =sin-ti;

Re(s)

Figure 14 - Pair of Complex Poles S-Plane Plot

One can observe that the poles are located at a distance gati„ from the origin and at an

angle 0=sin 'g. Thc damping factor, j, is a measure of stability. If f is equal to

zero, then the poles of the system lie on the imaginary axis at a distance rii„ from the

origin. For this case the impulse response of the system results in a steady oscillation at
a frequency rii„. On the other hand, as j is incrcascd, the poles move to the left. -hand

plane and the system becomes stable. For this particular situation the impulse response
of the system becomes a damped oscillation at a frequency ru„. Using ( 26 ), a plot of

the second order PLL frequency response for different damping factors is shown in

Figure 15.
 28

Freqeency Response of s Second Order PLL for Oqfemnt compete Fectom

00

= 0.1
/,

0$ '-
E 0707
00
=2
10
e,l &
i;m 1

0 Lt

ze F

10 Kpo 2SUA/255
Kvco = 250foMHzFV L
5 N =32
rq, = i (normalized)
c
10 1O 10
reqnsncy worn (rsdrsce)

Figure 15 - Second Order PLL Frequency Response for Different Damping Factors

The PLL frequency response shows the expected second-order low-pass characteristic.
The Q value of a PLL is inversely proportional to the damping factor, j. High Q

values display a frequency response with a sharp peak at ru . This resuhs m an

oscillatory transient response. If the damping factor is high, the Q value of the system

is low and the lrequency response is flat across a wide bandwidth. This results in a slow,

sluggish transient response. Generally, an optimally flat frequency transier Function is

desired[7]. This occurs when j = i@2 = 0.707, which corresponds to a second-order

Butterworth low-pass filter. The values of ( and rff„also has an effect on thc

bandwidth of the PLL. The 3-dB bando:idth is equal to the following[34]:

(29)
where a is equal to the following:
 29

(30)
+PD VCO
i PD+VCO

The values of ( and ro„have a noticeable effect on the transient response of the PLL.

The effect of ( and ro„can be seen by applying a phase step to the reference signal of a
locked PLL as shown in Figure 16.

Phase Step

Figure 16 - Phase Step Applied to the Input Reference Signal

The following time domain function descnbes the input reference signal when a phase
step is applied at t = 0.

(31 )

A phase step applied to a locked PLL can bc modeled as the following:

(32)
 30

This results in the following response for the phase error.

ru„N
S+
g() ~(I ro vco (33)
s'+2gcu„s+nt„'

The VCO control voltage has the following response.

Nrtt„'"
s 2scu — +rrt'
+ro +vco (34)
&,c, s'+ 2sru„s+ cu„'-

When a phase step is applied to a locked PLL a phase error will result. However, the
PLL will remain in the lock range and the loop dynamics will force this phase error to

zero. The umt phase step transient response of the phase error for different damping
factors is shown in Figure 17, while the VCO control voltage response is shown in

Figure 18.

The following observattons can be made from the transient response of the phase error
and VCO control voltage to a normalized phase step input. Both waveforms respond
with a dampened oscillation at a frequency of f = I((2rt). This corresponds to a

normalized natural frequency ru =1. It can bc observed for a low damping factor the

oscillation takes a v hile to die out. The phase error signal initially has a value ol' 1

because a unit phase step is applied to the input. This phase error eventually dies down
to zero after the loop has acquired lock. The VCO control voltage initially has a small
value. This small value allows the output s&gnat to catch up wtth the mput reference
phase step. The reason why the value ts so small is that the VCO gatn is very high. The
VCO control voltage eventually returns to zero because the reference frequency has n&&t

changed.
 31

—r—
phase Error Tranalcnt Rcaoonac for onfcrcnt oamnlnp Factors
1 1
phase step Input: o,(s)=-
/to

r, = 0.1

/
/
/

/(;m05 ' /
I
/. /

-o 2. l; = 1~, ' F=
0.707
/
/
/
/
/
/

-oc- /

0. 6-
—
Kno —25uA/216
-0. 8 Kvco 5 21140Mtfz/V
N = 32
c), = 1 (norma)ized)
2 6 8 10 12 1a 16 18 26
7 en/n

Figure 17 - Phase Frror Transient Response - Unit Phase Step Input

 32

-7
610 vco careal rrsnstant Rcspansa tar Dnrarcnt Damping Fsatars
7 7
~e
phase Step Input: o,(s)=-

ai
=os/
0 /
—1
r, = 0.1

Kpo = 25uA/276
-6',
coo tt
= 32
N
tq, = I (normalized)

2 'i 6 0 10 12 1s 16 10 za
rima cnt

Figure 18 - VCO Control Transient Response - Unit Phase Step Input

Thc effect of s and ctt„can also be seen by applying a I'requency step to the reference

signal of a locked PLL as shown in Figure 19.

V
,(t)
Frequency Step

Figure 19 - Frequency Step Applied to the Input Reference Frequency

 33

The following time domain function describes the input reference signal when a
frequency step is applied at r = 0.

(35)
v
f (t) = sin ((rff + Arri„, (r)) r j

A frequency step input is equivalent to a phase ramp input. Therefore the input to a
locked PLL can be modeled as the following:

(36)

This results in the following response for the phase error.

ro.'N
s+
K ro Kvco
0() A (37 )

The VCO control voltage has the following response.

Nrff„'"
s 2gnf„— +to,
',

I i fsn)N pDKUoo (38)

Kvoo s s +2Cru„s+rjf, ,

The frequency step transient response of the phase error for different damping factors is
shown in Figure 20, while the VCO control voltage response is shown in Figure 21.
 34

I ~
posse Error Trsnstsnt Response for eteerent oenpine Footers
1
—
zs4o
ri( m G' FrequenCy Step lhput: O~(S)m
S2
00, \
'
/

(
Cmos

0.44&
F
l/' ~s( mG. 707

e.(t)
/pro/r// S /

-0 2.
/
/
I
!
/
—04
/

Kpp 25UA/2rt
Kv~ = 21040MtfzN
N = 32
o), = 1 (normalized)
0 'le 12 14 lr 10 20
Time nnt

Figure 20 - Phase Error Transient Response - Frequency Step Input

Thc following observations can be made from the transient response of the phase error
and VCO control voltage to a normalized frequency step input. Both waveforms
respond with a dampened oscillation at a frequency of f = (/(2/t ). This corresponds to

a normalized natural frequency /dn ms l. The phase error is imtially zero because the

loop is locked on thc VCO cenler frequency. As the input reference frequency
expenences a frequency step, the phase error responds with the dampened oscillation.
The phase error eventually dies down to the following value:

NAat (39)
limo, (r) =
+rr/+v/'o
 35

010 VCO Cantral Tmnsiere Rcspansc sar Dprcrent Demprna Fnefam

Z5 r — —
n —
Frequency Step input: 0~(e)u
Zs00
—,
5

/
rtq01
/
Zn 1
/

Iq=0. a, /
/
I

u 15
'—0 707
r, /
m
sl
a /

u
/" t
/
/

K» —
—25uA/210
Kwco —21000IVIHZ/V
N = 32
/
/ rrt = 1 (normeiized)
0'
0 Z 6 0 10 1Z 14 16 10 Za
Time ant

Figure 21 - VCO Control Transient Response - Frequency Step Input

It can be observed that the low damping factor systems are very oscillatory. The high
damping factor systems are more stable. However, their settling time to the final value

can be long. The optimal damping factor is found to be S" = I/E2 = 0.707. The VCO

control voltage is initially zero because the loop is locked on the center frequency of the
VCO. After a frequency step is applied to the input, the VCO control voltage rises to
increase the output frequency to allow the output signal to synchronize with the input

reference signal. The VCO control signal has a step response with a dampened
oscillation. The VCO control voltage eventually settles on the following value:

limV, (r)=
/1/A///
(40)
0('0
 36

1n summary, the dynamic response of the second-order PLL is dependent on the natural

frequency and the damping factor. Generally, the damping factor is set equal to I/J2 as

a compromise between stability and speed. The natural frequency plays an important
role in determining the bandwidth of the PLL. How the bandwidth of the PLL is
designed depends on the desired noise performance of the PLL and the dominant sources
of noise in the PLL

PLL Noise Analysis

The job of any frequency synthesizer is to generate a spectrally pure output signal. An

ideal periodic output signal in the frequency domain has only an impulse at the

fundamental frequency and perhaps some other impulse energy at DC and harmonics. In

the actual oscillator implementation, the zero crossings of the periodic wave vary with
time as shown in Figure 22. This varying of the zero crossings is known as dme-domain

jitter.

v(t) Jitter

Figure 22 - Periodic Signal with Jitter

A signal with jitter no longer has a nice impulse spectrum. Now the frequency spectrum

consists of impulses with skirts of energy as shown in Figure 23. These skiits are known
as phase noise.
 37

P(ttt)

Carrier Power

Noise Power

(no co&+Ao)

Figure 23 - Frequency Spectrum of a Signal with Phase Noise

Phase noise is generally measured in units of dBc/Hz at a certain offset from the desired
or carrier signal. The formal definition of phase noise is the ratio of the sideband noise
power in a 1Hz bandwidth at a given frequency offset Atii from the carrier over the
carrier power as shown in the following.

(cu„+ /tru, 1Hz Bandwidth)

P„„„„„„, (41)
s(Aru)-
P, „,„„,„

The PLL can be designed in such a way as to minimize the phase noise of the output

signal. Generally, the dominant sources of phase noise are from a noisy reference signal
or from a noisy oscillator. Also other loop non-idealities, such as phase-detector dead
zone and power supply fluctuations can contribute to phase noise. The way the PLL is
designed depends on what is the dominant source of noise in the loop.

t Ph ~
An input rcfcrence signal with phase noise can be modeled in the PLL as shown in
Pigurc 24[22]. Without loss ol' generality, the loop filter is assumed to be the passive lag
filter discussed in the previous section.
 Phase Loop
Detector Filter VCO

vin
I
I + e,
Kao
I

F(s)
v Kvco e,„,
s
I
I
I
J

Loop
Divider

Figure 24 - PLL Input Phase Noise Model

The input noise, 8,„„,is treated as an input signal and the same PLL transfer function

I'rom ( 26 ) is derived for the input noise transfer function. The input phase noise
transfer function is plotted in Figure 25.

Nru„'"
s 2jru„— +at„'
~oui() PO ICO (42)
0,„„(s) si+ 2szu„s+ u, "-,

The input phase noise is shaped by the low-pass characteristic of the second-order PLL.
In order to reduce the phase noise in the output signal due to the input phase noise it is
desirable to make the PLL bandwidth as narrow as possible. Notice that the input noise
is amplified by a factor of iv . If input noise is a concenh the lowest possible value of
rV should be used. Usually in frequency synthesizer design the input phase noise is not

a concern because thc reference signal generally comes from a low phase noise crystal
oscillator.
 39

Inpnf Noae Prnqnenny Response of 0 Seeonn Onfer PLL

30

20tog
les
15

10'
K„= 25uA/21I
354
vs o
5— N/ 22
ot = 1 (normalized)
r, = 0.707

0 1
10 10 10
Sreqneney wnsn (ren/sen)

Figure 25 - Input Phase Noise Frequency Response

VCO Phase Noise

The VCO phase noise can be modeled in the PLL as shown in Figure 26[ZZJ. Without
loss of generality, the loop I'ilter ts assumed to be the passive lag filter discussed in the
previous section.

Phase Loop
Detector Filter VCD
+
+ 0,
Kro F(s) voo OUI

5 +
s

Loop
Divider

Figure 26 - PLL VCO Phase Noise iVIodel

 40

The VCO phase noise, 6t,„, is treated as an input signal and the following transfer

function is derived. The VCO phase noise transfer function is plotted in Figure 27.

(43)

The VCO phase noise is shaped by a high-pass characteristic by the second-order PLL.
In order to reduce the phase noise in the output signal due to the VCO phase noise it is

desirable to make the PLL bandwidth as wide as possible. Here a tradeoff regarding
loop bandwidth position and its effect on input phase noise contribution and VCO phase

noise contribution is observed. The optimum loop bandwidth depends on the

application. It is optimal to have a narrow loop bandwidth for input noise performance.
Narrow band loops aid in the cases where the PLL is operating with a noisy reference

signal. It is optimal to have a wide loop bandwidth for VCO noise performance.
Usually the dominant source of noise is the VCO in fully integrated frequency
synthesizer design[35]. The VCO phase noise is caused by such things as the

upconverted 1/ f noise from the transistors used to design the VCO, noise in the control

path, and cycle-to-cycle fluctuations in the power supply[36, 37]. With the VCO

contributing significant phase noise it is optimal to make the loop bandwidth as wide as

possible.
 41

VCO None FNrotencr Rcenonec ore Second Order FLL

-dt

to
I-

-15I-
20log o
0 „(e) cs -50

-35

-30 Kno = 2SOA/235

—25140MHzN
K, co —
ter = 32
-35 . e) = i (normaltzed)
C= 0 707
h
10 10 10
Ftcchchcr wttvh ffcdlecc)

Figure 27 - VCO Phase Noise Frequency Response

Phase Detector Dead Zone

Another source of noise in PLLs is the phase detector dead zone. The dead zone is a

region over which the phase detector gain, ft'Fo, hecomes very small. The dead zone is

illustrated in Figure 28.

 42

v, (/kQ

Dead Zone

Figure 28 - Phase Detector Dead Zone

This region occurs when the loop is essentially locked. However, the reference and
feedback signal still should produce a phase error. Because little phase error is
generated for variations in the reference or feedback signal a peak-to-peak jitter
approximately equal to the width of thc dead zone arises in the output signal[3]. Proper
phase detector design techniques minimize this dead zone.

Charge Pump PLLs

The charge pump PLL is popular for integrated circuit applications for the following
reasons. The phase/frequency detector used in the charge pump PLL allows the PLL to
have a pull-in range that is only limited by the VCO's tuning range[7]. The static phase
error is rero between the input reference signal and the feedback signal even if the
reference signal is not equal to the center frequency of the VCO[3, 38], The charge
pump PLL also displays incrcascd immunity to power supply variations[39].

The charge pump PLL is a digital PLL that uses a charge pump as thc output of the
phase/frequency detector as shown in Ptgure 29. The phase/frequency detector
compares the input reference signal and the feedback signal to produce two control

signals UP and DOWN . These control stgnals control how much error current flows
 43

into the loop filter. The loop filter consists of a minimum of one capacitor C, in series

with a resistor R. The charge pump current charges and discharges the loop filter to
produce the VCO control voltage. The VCO signal is then divided in frequency and fed
back to the phase/frequency detector.

Charge Pump
VDD

UP Loop Filter
Phase v vo. i
Frequency VCO
Detector DOWN
C,

VSS

Loop
Divider
1/N

Figure 29 - Charge Pump PLL

The main difference between the digital charge pump PLL and the classic analog PLL is
the phase detection circuitry. A multiplier is used as a phase detector in the analog PLL

This produces a non-zero static phase error if the input reference frequency is not equal
to the center frequency of the VCO. The charge pump PLL uses a digital

phase/frequency detector (PFD) that switches;i charge pump's current sources to charge
or discharge the loop filter. The type of PFD used allows for a zero static phase error
even when the input reference frequency is noi equal to the center frequency of the
VCO.
 44

Char e Pum PLL Linear Anal sis

The switching interaction between the phase/frequency detector and the charge pump
make the charge pump PLL a discrete time system. A plot of this interaction for a
frequency step input is shown in Figure 30. This is a plot of the VCO control voltage
when the charge pump PLL has a frequency step input.

Charge Pump PLL VCO Control Transient Response

Frequency Step Input

1,48

1.28

I.BB

688m

688m

488m

288m

4 Bu 6.8u 12u 16u 28u

time i et

Figure 30 - Charge Pump PLL VCO Control Voltage Transient Response

Notice the ripple on the VCO control voltage that is not evident in the earlier linear PLL
analysis in Figure 2l. This ripple is due to the charge pump charging and discharging
the loop filter. However, even though this is a discrctc time system, the response is very

similar to the lmear PLL. In fact, a linear analysis can be assumed for the charge pump
PLL if the loop bandwidth is much less than the input reference frequency[40].

Using the linear PLL model, the same PLL transfer function found in ( 2l ) is derived

for the charge pump PLL transfer function //r. r (s).

 45

8, (s) K K, F(s)
g () ~KE, , F (44)
N

SStbil t SA8
There are certain conditions that must be satisfied for the charge pump PLL to be a
stable system. Care must be taken in choosing the type of loop filter that is used in the
PLL and also in designing the bandwidth of the loop.

The loop filter converts the charge pump current into a voltage for the VCO. One may
be tempted to only use a capacitor as the loop filter. However, if only a capacitor is used
as the loop filter, the following transfer function is obtained.

„()=
Htv s)= KvoKvco/Ci (45)
NC,

It can bc obscrvcd that this is an unstable system because there are two poles on the
imaginary axis. This means the damping factor is zero. Any excitation input. to the

system will result in a steady "phase oscillation" with a frcqucncy equal to the natural

frequency of thc system.

In order for the loop to be stable a zero must be added to the loop filter m order to move

the loop's poles from the imaginary axis into the left plane. This is typically done by
adding a series resistor to the loop filter as shov'n in Figure 29. With the resistor m the

loop filter the charge pump PLL transfer function becomes the following:

KvoKvcoR s+—1
RC, (46)
II „(s)
s
i +s vo vco +- vo Kvco
N NC,
 46

Here there is an s term in the denominator. This means that there is a non-zero damping
factor. Now, any excitation to the system will result in a dampened oscillation with a
natural frequency equal to the following.

+r o+vco
(47)
NC,

The damping factor of the system is equal to the following:

rrr„RC, (48)
2

The switching tnteraction betwccn the charge pump and the loop filter causes a great
deal of ripple on the VCO control voltage with the series RC loop filter. This npple may
be suppressed by adding a small capacitor, C, , tn parallel with the loop fdter as shown

in Figurc 31.

VCO Control
Voltage

Figure 31 - Addition of Cz in Loop Filter to Suppress Ripple

The addition of thts capacitor adds another pole to the PLL transfer function and makes
it a third-order system. However, if the capacitor is small enough the system can be
analyzed as a second order system. If C, is made smaller then O. IC, tt may be

neglected in the loop analysis because it is at a frequency greater then a decade Irom the
zero of the filter[39].
 47

The previous analysis assumes that the charge pump PLL is a linear system, when in fact
it is a discrete time system. The linear approximation holds only when the input

reference frequency is significantly higher then the loop bandwidth. Generally this

means an input reference frequency about 10 times greater then the loop bandwidth,

Because the loop bandwidth is closely related to the natural frequency, a stability limit
can be derived that is a function of co„. A formal stability limit is given in the following

inequality[3, 40].

co„~
(4&)
n RCro, a +rr

Charge Pump PLL Building Blocks

The building blocks that make up the charge pump PLL consist of the phase frequency
detector, charge pump, loop filter, VCO, and the loop divider. The following explains
each block and discusses its role in the loop's performance.

Phase/Fre uenc Detector

The phase detector is a digital phase/frequency detector (PFD) with a charge pump
output stage. Thc digital phase/frequency detector consists of two D Flip-Flops and an
AND gate. A schematic of thc phase/frequency detector is shown in Figure 32.

i D Q UR
DFFR
v„, CLK
R

R
D Q DOWN
DFFR
CLK

Figure 32 - Phase/Frequency Detector

 48

The phase/frequency detector produces two output signals, UP and DOWN, that are

dependent on the phase and frequency relationship of the two inputs, v &
and v». The
UP and DOWN outputs control the charge pump which acts as the phase frequency
detector's output stage. The charge pump outputs a current into the loop filter to
generate the control signal of the VCO.

The UP output signal of the PFD goes high on the rising edge of v„&. The DOWN

output signal goes high on the rising edge of v». The UP and DOWN signals remain

high until they are reset by the AND combination of UP and DOWlV . In other words,
the reset signal is produced when both v„u and v» clock inputs are high. Both Q

outputs will be essentially low when both signals are in phase and of the same

frequency. An example is shown in Figure 33.

ba

ib

UP

DOWN

RESET

Figure 33 - Phase/Frequency Detector Signal Diagram

In this example, the rising edge of v» occurs first. This causes the DOWN signal to go

high. The DOWN signal then remains high until reset. The nsing edge of v„,, occurs

later. This causes the UP signal to go high. The UP signal only remains high for an
instance. The reason for this is that now both UP and DOWN are high. The AiVD

output of these two signals causes the reset signal to go high. This causes both (/P and
 49

DOWN to return low. After sometime the rising edge of v~ occurs. This causes the
UP signal to go high and remain high until reset. The rising edge of v» occurs later.

This causes the DOWN signal to go high. Now both outputs are high and the PFD

outputs are reset low. This is repeated again in this example.

The UP and DOWN output voltages of the phase/frequency detector depend on both
the relative frequency difference and the phase error if the two input frequencies are the
same. The phase error is the phase difference bctv ccn the v„z and v» signals given in

the following:

0, = 0,& —0» (radians) (50)

The phase/frequency detector's outputs go high on the leading edge of their clock inputs
and remain high until they are reset. The time the outputs are high, t„,„,is related to the

phase error, 0, , by the following[40]:

(51)

An advantage of the digital phase/frequency detector is that it uses only the rising edges
of the input reference signal and the VCO feedback signal to generate the output signals,

This means that the width of the input reference signal and thc VCO feedback signal are
irrelevant. A 50% duty cycle signal is not necessary for this phase frequency detector.
Other types of phase detectors, like the XOR gate phase detector, require 50% duty cycle

signals[7].

Another advantage of the PFD over the XOR phase detector is that the PFD will not

allow the loop to lock on harmonics. This allows the hold range of a PLL using the PFD
to be very large. The hold range is only limited by thc VCO tuning range.
 50

One potential problem that this phase detector may have is a dead zone. The dead zone
occurs when the rising edges of the input reference and VCO feedback signals are
almost aligned. If the delay through the reset path is shorter than the delay to the charge
pump that the PFD is driving then the charge pump will not get switched even though
there is a phase error present. This will result in jitter in the output signal as discussed
earlier[3]. The PFD must be designed in such a way as to ensure that the delay through
the reset path is longer then the delay to the charge pump.

~Ch P
Figure 34 shows the charge pump output stage of the phase/frequency detector. It

supplies current to the loop filter to produce the VCO control voltage.

Charge Pump
VDD

UP
DFFR
VCO Control
CLK
R Voltage

DOWN
1
DFFR
CLK

VSS

I'igure 34 - PFD Charge Pump Output Stage

 5I

The UP signal is high when the reference signal is operating at a higher frequency than
the feedback signal. The charge pump forces current into the loop filter when the UP
signal is high. This causes the VCO control voltage to rise. This increases the VCO
frequency and brings the feedback signal to the same frequency as the reference signal.

The DOWN signal is high when the reference signal is operating at a lower frequency
then the feedback signal. The charge pump forces current out of the loop filter when the
DOWN signal is high. This causes the VCO control voltage to fall. This decreases the
VCO frequency and brings the feedback signal to the same frequency as the reference
signal.

This interaction between the PFD, charge pump, and loop filter is shown in Figure 35.
Here the UP signal is high. This forces current into the loop filter and causes the VCO
control voltage to rise.

PFD, Charge Pump, 6gc Loop I-i ter interaction

DC IVN

588m

8.8

i8 UP

588m

VCO Control Voltage

488m

288m

188n BBn 588n 488n 588n 688n

time ( a )

Figure 35 - PFD, Charge Pump, and Loop Filter Interaction

 52

The value of the charge pump current determines the phase detector gain, Kpa. Each

reference cycle has a duration of 2rr/zu„/ seconds. The time that the UP or DOWN

signals are high determine the amount of current that gets delivered to the loop filter.
Using the time that the UP and DOWN signals are high, given in ( 51 ), gives the

average error current, i„over a cycle[40].

i, =
t~„
"
rittgh
(Charge Pump Current)= —
'18,
2rr
(52)

This means that the phase detector gain is the following.

/
Kp~: (amps/radian) (53)
271

~LF It
The loop filter converts the charge pump error current, /, , into the VCO control voltage

v, . Ignoring the smaller capacitor C, as explained earlier, the loop filter has thc

followmg transfer function.

I
R s+
V (s) RC, (54)
/, , (s) s

The frequency response of the loop filter is plotted in Figure 36. The effect of the pole
at zero is seen by a very high low frequency gain. The zero causes the transfer function

to level off at high frequencies.

 53

Loop Filter Frcqocncy Response

100,

160 6

.6

120

100;
R = 31.akron
C = 62.2pF
60 '1
10 10 10 10 10 10 10 10
Frequency (red.'seei

Figure 36 - Loop Filter Frequency Response

The loop filter is the critical building block that dctcrmines the loop dynamics. In a

charge pump PLL, the natura! frequency and the damping factor is set independently by

the values of the components used in the loop filter. The capacitor, C, , sets the natural

frequency. The resistor sets the damping factor.

Voltaoe-Controlled Oscillator
The voltage-controlled oscillator generates an output signal with a frcqucncy that is

dependent on the input control voltage by the following:

(55)
 54

The transfer characteristic of the VCO is given in Figure 37. It has a center frequency of

rzi0. The slope of the transfer characteristic in the linear region is equal to the VCO

conversion gain Kvco.

Kvco

0 VDD/2 VDD

Figure 37 - VCO Transfer Characteristic

There are several different types of VCOs. Some VCO architectures include RC,
switched-capacitor, LC, crystal, relaxation, and ring osci]lators[38]. The oscillators most
commonly used in integrated PLL design are thc LC tuned and the ring
osci l lator[10, 22, 23, 35,41].

The LC oscillator is shown in Figurc 38[11]. This circuit is generally preferred in high
performance frequency synthesizers because of its superior phase noise performance.
Recent iniegraied LC oscillator results are shown in Table 4.
 55

VDD

v+

VSS

Figure 38 - LC Voltage-Controlled Oscillator

Table 4 - Recent Integrated LC Voltage-Controlled Oscillator Results

Source Fre uenc Ran~e Phase Noise

1.62-1.99GHz -113dBc/Hz 0 200kHz
[35]
0.84-1.03GHz -108dBc/Hz I
100kHz
[42] 1.885-2.035 GHz -136dBc/Hz Q 4.7MHz
[43) 4.9-5.25 GHz -104.SdBc/Hz @ 5MHz
[44] 5.51-6.53GHz -98.4dBc/Hz 0 1MHz

A nng oscillator is shown in Figurc 39[38]. This circuit consists of an odd number of
inverting amplifiers placed in a feedback loop. Recent integrated ring oscillator results
arc shown in Table S.

OUt

Figure 39 - Ring Oscillator

 56

Table 5 - Recent Integrated Ring Voltage-Controlled Oscillator Results

Source Pre uenc Ran e Phase Noise

[41] 320-926MHz -83dBc/Hz 0
100kHz
[45] 660-900MHz -83dBc/Hz 0
100kHz
[46] 350k —707MHz -82dBc/Hz 0
100kHz

The integrated ring voltage-controlled oscillators typically have a wider tuning range
then the LC oscillators. However, this increased tuning range comes at the price of
poorer phase noise performance when compared to LC oscillators.

Loo Divider Circuitr

The loop divider divides the VCO output frequency to produce the VCO feedback
signal. The loop division factor determines the output frequency relation with the input
reference frequency. The loop divider can be realized in many different ways depending
on the type of synthesizer architecture used. Thc most common circuits used in the loop

divider are prcscaler circuits, dual-modulus prescalers, and counters. Detailed

applications of these circuits are included in the earlier I'requency synthesizer
architectures section.

A General Fully integrated PLL Design Procedure

The PLL is a complex system to design. Performance and stability considerations must

be accounted for in the design procedure. The entire design procedure for a fully
integrated PLL is generally an iterative process. Typically design parameters are
adjusted from the mathematical model to the system level model to the transistor level

design. The following design procedure describes how to define the system level
parameters for a fully integrated charge pump PLL. As an cxamplc, thc charge pump
PLL will be used as a frequency synthesizer in the GSM cellular communications
system. It will be required to synthesize 890 to 960MHz with a resolution of
 57

200kHz[47] using a power supply of 2.7V. The following system level parameters need
to be defined.
1. Charge Pump Current I
2. Loop Filter Components R, Co & C,
3. VCO Tuning Range
4. VCO Gain +4 co

5. Loop Division Factor N

~Ste l Determine VCO Tuning Range

The maximum and minimum output frequencies detcrmme the PLL frequency range.
This is thc range of frequencies under which the PLL is operating. The frequency range
for this PLL is 890 to 960MHz. This requires that the VCO have a tuning range at least
890 to 960MHz.
VCO Tuning Range & 890 —960MHz (56)

~Ste 2 Determine Loop Division Ratio Range.

The loop division ratio range is the range that the modulus, N, is operating. This is
largely determined by the synthesizer's frequency resolution. Here thc frequency
resolution is the channel spacing of 200kHz. If it is assumed that a 200kHz reference is

used to achieve a 200kHz resolution, N will have the following range.

4450 & N & 4800 (57)

The value of N has an effect on other loop parameters. Therefore, in defining the other
parameters the geometric mean of N will be used.

N —~N N —
4622„„„„,„ (58)

~Ste 3 Determine Damping Factor, j„„,„,

The damping factor, S,„,„„,has an effect on the speed and stability of the system. As a

compromise between speed and stability, j„„„„is optimally set to the following value.
 58

1
= 0.707
(59)

~Ste 4 Determine Natural Frequency, rti„

The natural frequency has a significant effect on the loop bandwidth. For a charge pump
PLL with a passive loop filter, the loop bandwidth, rtt3JQ is related to the natural

frequency by the following[34]:

.I2r' I+ 12 r'+11+1] (60)

lf ( = 0.707 is assumed, this results in the following:

m, „, = 2.06ru, (61)
It is desirable to make the loop bandwidth less then I/10 of the input reference

frequency (200kHz) in order to avoid the continuous time approximations of the charge
pump PLL breaking down. However, it is desirable to make the loop bandwidth as wide
as possible in order to suppress the VCO phase noise that is the dominant source of
phase noise I'or the integrated PLLs. As a compromise between stability and noise

performance, the loop bandwidth is set to the following:

idB
"r
(0 75) 942krad j (62)
This results in the natural frequency equal to the I'ollowing for j = 0.707 .

"" = 4S.8«ride (63)

2.06

~Ste 5 Determine VCO Gain

The tuning range of the VCO and the VCO control voltage range set the VCO gain.
Fiom step 1 it was shown that the VCO needs to tune a minimum frequency range of
890 to 960MHz. The VCO control voliage range is limited by the pov, 'er supply and the
voltage levels necessary to keep the charge pump in saturation. The charge pump will
 59

no longer behave ideally if the VCO control voltage rises too high or falls too low.
Therefore, the VCO control voltage is limited to a minimum of a Vo~r from the supply
rails. With a power supply of 2.7V, a VCO control range of 1.6V can be assumed with

sufficient margin to handle process variations. This results in the following VCO gain.
2rr (960MHz —890MHz) rad Mrad
VCO
1.6V (64)

~Ste 6 Determine Charge Pump Current and Loop Filter Capacitor

The charge pump current and the loop filter capacitor can be determined by the
relationship between the natural frequency, the loop division factor, and the VCO gain.

It is desirable to have a high charge pump current because this will result in a higher
loop gain and thus a more stable system. However, having a large charge pump current
will result in a large capacitor as shown in the following equation which is derived from

equations ( 47 ) and ( 53 ).
IK VOO
ZrrNra„ ( 65 )

A large capacitor will translate into increased circuit area. Thcrcfore a design tradeoff
between loop gain and silicon area arises. The charge pump current can be set so that it
will result in a decent loop gain without producing too large ol' a capacitor as shown in
thc following:
Set I =10pA
(10pA 275 (66)
sV
C, — , —45. pF
1

2rr(4622 &S.8
'"'
S
 60

~Ste 7 Determine Other Loop Filter Components

The loop filter resistor is used to set the damping factor as shown in the following
equation which is derived from ( 48 ).
2( 2(0.707)
(67)
45, 8 (45. 1pF)
S

The second loop filter capacitor, C, , used to supress ripple in the control voltage is fixed

to be less than a tenth of the main loop filter capacitor C, so that the loop can still be
considered a second order system.

C, (—
C,'=4.
10
51pF (68)
A ~slue of 4pF would be appropriate for C, in this design.

This design procedure has defined all the kcy system level parameters required to start
the design. The next step in the circuit design is to construct a system level macromodel
which allows simulation of thc loop dynamics. Then transistor level design is started.

The design process is generally an iterative process. For example, non-idealities

introduced by the transistors can be compensated by adjusting parameters in the system

level macromodel and then translating those adjustments back to the transistor level.
There are usually many design iterations involved in such a complex system level design
as a PLL.
 A MULTI-BAND PHASE-LOCKED LOOP FREQUENCY SYNTHESIZER
This section describes the development of a multi-band phase-locked loop frequency
synthesizer. The design process is explained from the project definition down to the

transistor level design. The building block and system level simulations are presented.
A design of a classic digital PLL is also produced for comparison.

The Multi-Band PLL System

Unlike typical phase-locked loops which cover a given frequency range with only one
band of operation, the multi-band PLL is a phase-locked loop circuit that covers a given
frequency range with multiple hands of operation. These bands are cascaded in

frequency to cover the entire frequency spectrum of interest. The frequency synthesizer
may be designed to synthesize a continuous frequency spectrum or to synthesize discrete
bands of frequencies as shown in Figure 40.

Frequency Overlap Frequency Deadzone

dd
'U
c
Cd
c
di
cd

cd
Cd
~ ~

cd(red/s) ie(red/s)
Continuous Frequency Spectrum Discrete Frequency Spectrum

Figure 40 - Multiple Frequency Band Systems

These different frequency bands are realized in the multi-band PLL with a switched
tuning VCO shown in Figure 41.
 62

Switch
Control

UP
Charge v, Switched v „,
vie PFD Tuning
Pump Filter
VCO
DOWN

ve

/N

Figure 41 - Multi-Band Phase-Locked Loop Frequency Synthesizer

The switched tuning VCO is a voltage-controlled oscillator that is controlled

continuously with a controlling voltage and discretely by switching in different tuning
loads. The discrete tuning can be thought of as changing the channel or band of the
oscillator. One advantage of using a switched tuning oscillator is that a wide frequency
range can bc achieved while maintainmg a relatively low VCO conversion gain, K«n.
This is cntical in high frequency integrated circuit design because it is difficult to design

a VCO with a high K«n. A low VCO conversion gain also aids in the phase noise

performance of the PLL system because VCO control line noise is directly proportional
to the square of Kvc0 .

Multi-Band PLL Switch Control iVlechanism

The switch control network works by monitoring the VCO control voltage. If the PLL is
in a dynamic state trying to acquire lock, the VCO control voltage will rise or fall. This

is illustrated in Figurc 42 that shows the PLL's VCO control voltage response to a
frequency step input.
 63

VCO Control Tnmmont Response for e Frequency Stop Input

r

~Overshoot
T
Frequency Step Input: 8~(S)m
= 2106
~= ~
I.zl-

/
j
/

U 06-t

I; = 0 707
= 25uA/2rr,
0.2— Kno
Kvco —21020MHz/V
N = 32
o), = 1 (normalized)
0
0 10 12 10 16 10 20
Time ont

Figure 42 - VCO Control Voltage Response to a Frequency Step Input

The switch control network detects when thc VCO control voltage crosses a certain
positive or negative threshold and changes the VCO channel hy switching in or out

dil'ferent tuning loads. The VCO control voltage is then grounded to set the VCO m the

middle of the next channel and to reset thc system. This sv, Itch control mechanism is
shou n in Figure 43.
 64

swach lo Higher
Frequency Channel
VREFF

VCO Conlrol Vohage

ov l

VREFN

Figure 43 - Discrete Tuning System Mechanism

In this case the output of the PLL is initially oscillating too slow. The VCO control
voltage nses as the loop dynamics will take over. After the VCO control voltage passes
the positive voltage threshold, VREFP, the channel of the oscillator is changed to the
next higher frequency channel. The VCO control voltage is then grounded to set the
oscillator operating in the mid-band of the new channel. However, the oscillator is still
not in the right channel. Therefore the mechanism repeats. The VCO control voltage
rises and crosses the positive threshold, the oscillators channel is changed to thc next
highest frequency channel, and the VCO control voltage is grounded. Finally, the
oscillator is in the right channel and the system locks.

This type of switch control mechanism always keeps the VCO control voltage between
the posiuve and negative thresholds. This mechanism aids in low voltage applications
because the VCO control voltage doesn't have to cover a wide range to output a wide
frequency range. Instead, the different tuning elements are switched in and the VCO
control voltage just sweeps bctwccn thc two thresholds.

Also, this type of switch mechanism aids in the acquisition time of thc PLL. The VCO
control voltage doesn't have to climb slowly up or down like in a regular PLL. Instead,
the VCO is switched rapidly to the mid-band of the next channel anti is able to acquire

lock quicker.
 65

Multi-Band PLL Channel Desi

It can be seen from Figure 42 that the PLL has a characteristic overshoot when acquiring
lock. Attempting to synthesize an edge of band frequency can cause oscillation between
the different bands. This is because the overshoot will cause the PLL to jump to the next

highest or lowest frequency band that cannot synthesize the desired frequency. The PLL
will then return to the previous band. However, the overshoot will again push it out of
the band and the system will oscillate between adjacent bands. This is illustrated in

Figure 44.

o OV (3) Band 3
o OV (2) Band 2 Thresholds

o OV (1) Target (Edge of &and)

O
0
O
Time

Figure 44 - Overshoot Causing Oscillation Between Frequency Bands

The solutton to this stability problem is to force the PLL to always lock away from the
edges of the band. This is achteved by providing a frequency overlap for a continuous
frequency system and by providing a frequency cushion for a discrete system. In a
continuous frequency system the frequency overlap conststs of spectrum that is shared

by adlacent channels. In a discrete frequency system thc frequency cushion is the

unusable spectrum at thc edges of the dhscrete bands. This is illustrated in Figure 4S.
 66

Frequency Overlap Frequency Cushion

C9 Ol c
'u
c o ca
aj Cl
in IXl io

co(rad/s) io(rad/s)
Continuous Frequency Spectrum Discrete Frequency Spectrum

Figure 45 - Frequency Overlap and Cushion Introduced For Stability

The charactenstic overshoot of the PLL's VCO control voltage to a frequency step input
is used to partly determine the amount of channel overlap or frequency cushion by
converting this overshoot voltage into a frequency value. This conversion can be made

by knowing the VCO's conversion gain, Kico. The overshoot is a function of the

damping factor, (, and can be determined with the aid of a mathematical model of the
PLL in the lock range. The characteristic overshoot of a system with ii dampmg factor
of 0.707 is 21% greater then the final value as shown before in Figure 42.

A positive threshold, L', and a negative threshold, L, can be assumed to determine the
required frequency overlap based on the VCO control voltage's overshoot. Without loss
of generality consider the case of Figure 46. This example is of a PLL with a damping
factor of 0.707. Thc PLL's channel one has a center frequency, f„, that corresponds to

a voltage of OV. One can see that the VCO control voltage settles onto a value of
0.831.' in channel one. The peak channel one VCO control voltage reaches a value of
L' = IV . The actual overshoot voltage from the final value is the following.

Overshoot Voltage0 = L' (I —0.83)= 0. )7L' (69)

Observe that in this case the PLL would tend to go to the next band when attempting to

synthesize frequencies that require a VCO control voltage greater than 0.831'.
 67

vco control Trurucrn aceponec for e Frequency step Input

1.6 Frequency Step Input: Onn(s)=

sr
—
= 0.83NNO
K
Ns
fco = 1.66L+

Ch 2 VCO
t Control Voltage

ry/ 0, Region Ch 1 Cannot Synthesize

0.83L+
/ Ch2 Region Necessary to Synthesize 0 —0 66L+
/ L

o
o
C61 VCO Channel 1 Width = (L L)ftvcc (Henz)
o ( Control Voltage
= 2Kvco
V
0 p
( -fcr
t/

—pn L= 0.707
Knc = 25uA/2n
Kvcc =
N = 32
ct = 1 (normalized)
-L
10 re
T

Figure 46 - Determination of Frequency Overlap or Cushion

The frequencies that correspond to the voltage values between 0.83L' and L' cannot be

synthesized by channel one because of the overshoot. Thc next higher channel must
synthesize these frequencies. Channel two Is centered at a higher frequency f, z.
Mapping channel two to the voltage range of channel one results In f„having a

positive voltage value. Thc center Irequency of channel two must be placed so that the

frequencies that correspond to 0.83L' and L' can be synthesized. Knowing that the

overshoot 0 is equal to 0. 17L', L of the second channel must be placed at 0.66L' in

order to synthesize the frequency that corresponds to 0.83L'. This implies that the

amount of frequency overlap between ad)acent channels is equal to the following.

 Frequency Overlap (Due to Overshoot) =
2flKvco = ( 7 gvco = vco

This frequency overlap is represented as a percentage of the total channel frequency

range by the following.
% Frequency Overlap (Due to Overshoot) =
Frequency Overlap 28K«o 2(0. 17L" )Lvco
vco
17%%u
(71)
Channel Frequencies 2L' K,co 2L'K«o

For a discrete frequency system, the frequencies between +0.83V and +1V cannot be
synthesized. This area is the frequency cushion of the system. The percentage of
frequency cushion due to overshoot is equivalent to the following.
% Frequency Cushion (Due to Overshoot) =
Frequency Cushion 2(L' —0.83L')K«o (72)
17%
Channel Frequencies 2L'K«o

However, the above analysis assumes a continuous time system. The i.'harge pump PLL
is in fact a discrctc time system. A result of this is the ripple of the VCO control voltage
due to the charging and dischargmg of the loop filter by the charge pump. This ripple
effectively increases the frequency overlap or cushion in a multi-band PLL design. This
ripple will bc worse when the input frequency is lowered to close to ten times the loop
bandwidth. Here the loop becomes a very strong discrete time system 'md granularity
problems occur[40]. The reason for this is as the input frequency drops, the time thc
charge pump is charging or discharging the loop filter is increasing. This causes larger

ripple. Thc interaction between the charge pump and thc loop filter is illustrated in

Figure 47.
 VDD

I l
Charging VCO Control
Voltage

Discharging
C,
T"
I l R$
VSS

Figure 47 - Charge Pump and Loop Filter Interaction

Here the filter impedance is equal to the following:

I I
s+
C, RC, (73)
() sC, +C,
s +
RC, C,

The charge pump current is modeled as a step function g~ . This yields the following

voltage function.

I I
s+
V(s) = f(s)Z(s) =- C, RC, ( 74)
s +
RC, C,
In the time domain this is the following function.

',
C, IC„

RC,
' RC 2 RcIc,
I

v(t)=f + ( 75)
(c, +c, )' c, +c, (C, +C, )'

This function is plotted in Figure 48.

 70

YCO Conleol Y011000 Ripple

1.2

ee 0.0 )-

0
0. 6-
0
Ce
0
ep

0. 4,—

I = 25)IA
0. 9
R = 31.8ksz
/ CIm62. 2pF
/
'/ CemapF
D
0 00 09 03 04 0.6 06 DT D. D 0. 9 1
Tmie (seconds)

Figure 48 - VCO Control Voltage Ripple Function

It can be observed that for short values of t, which correspond to a high input reference

frequency, v(r) is an exponent)ally rising function. As r increases, with a lower input

reference frequency, v(t) becomes more linear with greater amplitude. This results ln

higher ripple for a low input rel'erence frequency.

The value of overshoot duc to thc ripple must then be analyzed at the lowest input

reference frequency. Simulating an input frequency of thirteen times the loop bandwidth
with a behavioral model that correctly models the charge pump yields an overshoot with
the following ripple characteristic shown in Figure 49.
 71

Ripple Effect on the VCO Control Voltage

-0.6675 Kvco
v 5 ,y pw i v: e i i=
tsro
s Ns
L'= tv
s= 0.707
Kpp 25UA/21r
55eie
Kvco = 2ttrtOMHB/V
N = 32
rq, = 7t skrad/6
VCO Controlling
Voltage Range = 2V
Frequency Range = 60MHz

'Continuous"
Overshoot = - 632L'
Final Value = -.6675L'

Maximum Overshoot
with Ri le = -L' L =-1V
1
B.B 3.eu 6 Bv 9 Bx all 15 ~
1 I mi ( s 1

Figure 49 - Effect of Ripple on the VCO Control Voltage

This system settles on a final value of —0.6873L'. This results in a "continuous"

overshoot of —0.832L' for a damping factor of 0.707. However the ripple due to the

charge pump PLL pushes the overshoot to —L'. The amount of frequency overlap or
cushion due to the ripple can be represented as a percentage of the total channel
frequency range by the following:
% Frequency Overlap(Duc to Ripple) =
j(Maximum Ripple — Continuous Overshoot)Kvoo
Channel Frequencies
(76)
(L' .832L gvro
2L' K, oo

One tmpottant characteristic of the ripple is that it is not a function of the final value like
thc characteristic overshoot. Rather, it is a function of the time that the charge pump is

charging or discharging the loop filter. The important thing to be observed here is that

thc ripple will have similar magnitude if it is near the channel edge or in the middle
 72

range of the channel. Therefore, the percentage of frequency overlap due to the VCO
control voltage ripple is a strong function of the channel's controlling voltage range or
correspondingly the channel's frequency range. A wide frequency channel will have a

large controlling voltage range for a given K«~. A large controlling voltage range

means the voltage ripple will not be a significant percentage of the controlling voltage
range. However, as the controlling voltage range is decreased, meaning a lower
frequency range channel, the ripple becomes a greater percentage of the controlling
voltage range. Therefore, it is helpful in knowing the controlling range of the VCO
when designing thc channels.

In summary, the overlap value is a summation of the continuous overshoot and the ripple
as given in thc following equation.

% Overlap(Total) = % Continuous Overlap+ % Ripple (77)

In this equation the percentage due to continuous overlap is only a function of the
damping factor. 17% continuous overlap is found for a typical damping factor of 0.707.
The percentage due to the ripple is a more complex function. The maximum overlap
necessary must be evaluated at the lowest frequency and thc percentage is largely a
function of the channel voltage width. In the example presented earlier a value of 8.4%
was found for an input reference frequency thirteen times the loop bandwidth. This
gives a total of 25.4%, If this overlap is not met the PLL will oscillate between bands as
shown in Figure 50.
 73

Insufficient Channel Overlap of 20% — PLL Oscillating

VCO Control Voltage

Oscillating Between Higher
& Lower Frequency
788m
Channels
588m

188m
)—
188m

—188m

8 8 In 1

—988m
88 8 Bu 12u 28u
time ( e l

Figure 50 - PLL Oscillating Due to Insufficient Channel Overlap

Here there is only a channel overlap of 20'7o. As this overlap is increased to 30% it is
observed m Figure 51 that the PLL becomes a stable system.

A value of 30"7o is a good value to start with in the design procedure. This value may be
changed due to the application. If extremely low voltage tuning ranges are used or if
input reference frequencies near ten times the loop bandwidth are used there may need to
be more then 30% overlap due to a large apple efl'ect. If the input reference frequency is
well above ten time the loop bandwidth then the overlap condition may be lowered
because thc loop approaches more of a continuous time behavior and the ripple is not as
evident.
 74

Sufficient Channel Overlap of 30% — PLL Stable

1.8 vCO Control voltage

688m PLL Switches Up One

Chan el and Locks
688m

288m

88
—288m

—488m

—688m

—688m
8. ' Bu 6gu 12U 16u 28()
um (e)
Figure 51 - PLL Locking with Sufficient Channel Overlap

The Multi-Band PLL System Design Methodology

A top-down design procedure is implemented for the multi-band PLL freq;iency
synthesizer as shown in Figure 52. Thc project is first defined and specifications arc
decided upon. The specifications are given in Table 6.

Table 6 - Multi-Band PLL Frequency Synthesizer Specifications

Fre uency Ran e I 00 —300MHz

Phase Noise @ 60kHz Offset & -90dBC/Hz
Lock-In Time & 15ps
Power Su 2.7V

A mathematical macromodel is lhen generated using MATLAB to investigate the PI.L's

performance in thc locked state and to perform stability analysis. This mathematical
macromodel aids in defining design parameters such as charge pump current, VCO gain,
 75

loop filter components, and the division ratio. A behavioral macromodel is then
generated using SpectreHDL. The behavioral macromodel models the thfferent blocks
of the PLL with HDL code. The behavioral macromodel aids in an increased
understanding of the loop dynamics and allows the switch control logic to be designed at
a behavioral level. The amount of frequency overlap in the channels is determined with
the aid of the behavioral macromodel. This macromodel allows for quick design
changes without the hassle of transistor level design. The transistor level design is

started after the behavioral macromodel is well defined and considered an ideal system.
The transistor level designs of each block are performed using CADENCE. The
transistor level blocks are substituted into the behavioral macromodel block by block to
investigate their performance in the system. The abihty to interface transistor level

blocks with the behavioral macromodel is very powerful. The non-idealities of the
transistor level blocks cause some changes in the system level that are rapidly

accommodated with the behavioral macromodel. Layout begins after the transistor level
design is completed. Thc blocks of the PLL are laid out as individual cells. The
extracted layout blocks are substituted into thc transistor level system block by block in
a method similar to what is done with the transistor level and behavioral macromodel.
After the layouts are completed a final chip level simulation is run on the prototype chips
to verify adequate circuit performance. The final designs are then sent for fabrication.
 76

Project
Definition

Mathematical
Model

Behavioral
Model

Transistor
Level
Design

Layout

Post-Layout
Verification
& Simulation

Fabrication

Figure 52 - Multi-Band PLL Frequency Synthesizer Design Flow

 77

Mathematical Design and Modeling

Inidal design parameters are computed through a mathematical procedure similar to the
one outlined in the previous section. The parameters' effects on loop performance are

then analyzed with a mathematical model of the loop.

Mathematical Desi n Procedure

The design procedure of the multi-band PLL frequency synthesizer is the one described
in the previous section with some modifications to handle the switched tuning VCO.

S~te 1 Determine VCO Tuning Range

The range of frequencies that the synthesizer must output defines the VCO tuning range.

The synthesizer must output between 100 to 300MHz in this design. Therefore, the
VCO tuning range is the following.
VCO Tuning Range =100-300MHz (78)

~Ste 2 Determine Loop Division Ratio, N

The loop division factor is sct to an integer value N in this prototype design. The value
of N =32 is chosen such that it is a typical value used in prescalers. Adjusting the

input reference frcqucncy changes the output frequency of the synthesizer,

~Ste 3 Determine Damping Factor, j

The damping factor is set to yield an optimally flat frequency response. This results in

j heing equal to the following.

1
= 0.707
(79)

~Ste 4 Determine Natural Frequency, ro„

The PLL*s phase error responds to any stimulus with a dampened oscillation that has a

Frequency equal to the natural frequency. The natural Frequency has a strong effect on
the loop 3dB bandwidth ap3js In order to insure that the loop's continuous time

approximations hold, ca»a must be set less than or equal to a tenth of the lowest input

reference frequency. In this design the lowest output frequency will be 100MHz. This
means that the lowest input reference frequency will be the following.

100MHz
Lowest Input Reference Frequency = = 3.125MHz
32 ( 80 )
This means that the absolute widest loop bandwidth can be 312.5kHz for the continuous
time approximations to hold up. A loop bandwidth 25% lower than this is chosen in the

design to allow sufficient margins for process and temperature variations.

m, „=(0.75$2rr)312. 5kHz = 1.47 Mrady (81)

The natural frequency is equal to the following for a damping factor of 0.707.

1 ' 47 Mradv
c&i~s I s —714 fcrad/ ( 82 )
2 06 2 06 v's

~Ste 5 Determine Frequency Bands and Average VCO Gain, Kvca

This part of the design procedure differs from the earlier design procedure because the
wide frequency spectrum has been split up tnto different frequency bands. The 200MHz
frequency spectrum is split into four 65MHz bands of operation. A frequency overlap of
approximately 30% or 20MHz between the channels is chosen to avoid oscillation when
attempting to acquire lock along the edges of the channels. Assuming a tuning range of
approximately 60% of the power supply gives a voltage tumng range of 1.6V. This
yields the following average VCO conversion ga&n.

255Mradr
vca
1 6V (83)
The spectrum allocation is illustrated in F&gure 53.
 79

K„=40MHz/V 300
Channel 4 (235 - 300MHz)
N
Z 55
Channel 3 (190 - 255MHz)
235
10
O Channel 2 (145 - 210MHz)
+~ 190
165
Channel 1 (100 - 165MHz)
6 145
U
100
Voltage Range = 1.6V
VCO Control Voltage

Figure 53 - Multi-Band PLL Frequency Synthesizer Frequency Bands

~Stc 6 Determine Charge Pump and Loop Filter Capacitor

The charge pump current is set so that a decent loop gain is obtamcd without producing
too large of a capacitor as shown in the following.
Set I = 25pA
(25' 255
sV (84)
C, = =62.2pF
/ra/'/ )',
2/r(32 714

~Ste 7 Determine Other Loop Filter Components

The loop filter resistor is used to set the damping factor of the PLL. Thc resistor is
computed to be the following.

2( 2(0.707)
(8&)
714 (62.2pF)

Thc secondary loop filter capacitor C, is set to less then a tenth of the main loop filter

capacitor C, .

C, (—
10
'= 6.22pF m C, = 6 pF
(86)
 80

Now all of the system level loop design parameters have been computed. Table 7
stunmarizes the system level parameters.

Table 7 - Summary of Multi-Band PLL Frequency Synthesizer System Parameters

Loop Bandwidth ru„= 1.47 Mrad/s

Damping Factor j =0.707
Natural Frequency cu„= 714 krad/s
VCO Tunin Ran e 100 —300MHz
VCO Conversion Gain K yap 25 5 Mrad/ s V
Loop Division Ratio N =32
Charge Pump Current I = 25pA
Primary Loop Filter Capacitor C, = 62.2pF
Loop Filter Resistor R = 3L8kQ
Secondary Loop Fi I ter Capacitor C, =6pF

Mathematical Model
The PLL is a highly non-ltnear system. However, the PLL can be described wtth a

Imcar model if the loop is operating in the lock range. The design parameters' effects on
the loop performance arc analyzed with a mathematical macromodel generated in

MATLAB. This mathemattcal model assumes the PLL is operating only in the lock
range. The mathematical model is not valid for other regions of opcratton because of the
non-linearity of thc PLL. An illustration of the macromodel is given in Figure 54.
 R(9+Ii'(R'C1 )) Nyco
e,
t(rpr)
Prose Input 9
Posse Detector VC0

Prose Gctec&r Gon loop Biter

(DDp Dlvlclcf

Figure 54 - Mathematical Macromodel of the Multi-Band PLL in the l.ock Range

The loop bandwidth (s verified with this macromodel as shown in Figure 55.

FICDDCDCy RC9pon9C 01 MURI-Bend PLL

I

25

2D-
e,„,(B) CI
20logto
0 [(5) 19
15-

10

1D 10 10 10
Frequency I (red(sec)

1'igure 55 - Frequency Response of the Multi-Band PLL

 82

This wide PLL bandwidth is beneficial to the noise performance of the PLL. The
dominant source of noise in integrated PLLs is the VCO. The VCO noise transfer
function has a high pass shape. If the loop bandwidth of the PLL is made sufficiently
high, the VCO noise contribution can be minimized. The VCO noise transfer function
of the multi-band PLL is shown in Figure 56 using the mathematical macromodel.

VCO Noioo Froquonou Rooponoo ot Midu-Bond FLL

-33
zolog "e ts)
43

eo—
10 1O 1~

Ffouuono'/ 4 (Iodfooo)

Figure 56 - VCO Phase Noise Frequency Response of the Multi-Band PLL

Another important performance parameter that can bc investigated with the

mathematical macromodel is the lock-in time. This is the time it takes thc PLL to
acquire lock assuming it is in the lock range. The lock-in time is shown in Figure 57 as
thc ttmc tt takes the PLL's VCO control voltage to settle within 1% of the final value
when a frequency step is input into the system.
 83

VCO Control Transient Response or Ltaln-Bend PLL

nap 1 I

n zato /5163 Mrad/sec

P' p esp pl"p"k P, ( 1=

0. 7 I- /
/
/'

/ Lock-In Time & I Oias

e 0. 5h

=. a. - I
,

8 03- /

0. 1—

05 15 35
Time lace)
a 10

Figure 57 - VCO Control Response to a I'requency Step Showing the Lock-In Time

Behavioral Model
A time-domain behavioral model of thc multi-band PLL frequency synthesizer was

created to gain an increased understanding of the loop dynamics. This model was
realized usmg Spectre and SpectreHDL. SpectreHDL is a C like programming language
that can be used to program behavioral modules ol' analog or digital circuits.
SpectreHDL can also be interfaced with normal Spice or Spectre circuit netlists. This
allows for a simulation to mix behavioral code and circuit nctlists.

Behavioral modules ol' all the loop blocks were produced and ~oined together to make up
the behavioral system macromodel. These modules were either SpectreEIDL code or
 84

ideal Spectre circuit components. The ideal Spectre components consist of elements
such as ideal current and voltage sources, switches, resistors, and capacitors.

The initial behavioral model of the PLL is of a classical charge pump PLL. The model
of the phase/frequency detector, VCO, and loop divider consists of behavioral code. The
charge pump is modeled as ideal current sources and ideal switches that are controlled

by the PFD. The loop filter is modeled as an ideal resistor and two capacitors. The
switch control logic for the switched tunable VCO is added as behavioral code to the
initial PLL behavioral model to complete the multi-band PLL frequency synthesizer
behavioral model. Appendix A shows the actual SpectreHDL code.

This behavioral time-domain model is different then the frequency-domain model

produced in MATLAB. Time domain simulations are made with the behavioral model

that realistically model the PLL in all regions of operation. This is different from thc
mathematical model that only simulates the linear model of the PLL in the lock range.

The other regions of PLL operation are not visible in thc rnathcmatical model because of
the non-linearity of the actual PLL system. Events such as cycle slipping that occur
when the PLL is undergoing a pull-in process are not visible with the mathematical
model. An example of the behavioral model working in the non-lock range is given in

Figure S8 and compared to the linear mathematical model response to the same input in

Figure 59. Notice specifically thc way the VCO control vohage rises to its final value.

These two simulation results show the impoixant differences between the behavioral and

lmcar model. The behavioral model is able to model the PLL in all regions of operation.

This is verified by noticing the cycle slips visible in the pull-in process of Figure 88.
The same input is applied to thc linear model. However, the linear model cannot model
this pull-in process because it only models the lock range corrcctl. Thcrc arc no cycle

slips observed in Figure 59. Also, the behavioral model is an actual discrete time system

like the real PLL, This can be seen in the behavioral simulations by the tipple on the
 85

VCO control voltage that comes from the interaction between the charge pump and loop
filter. No ripple is observed in the linear model because a continuous time system is
assumed. The ripple on the control voltage is an important property that needs to be

modeled when considering the design of the channels for the multi-band PLL frequency
synthesizer because it adds to the minimum frequency overlap necessary to msure a
stable system.

Behaviorol Macromodel of the PLL

Frequency Step Input u( 2 5MHz

VCO Centre v& tuq

/i

Cycle Slips

4 ei. 6 rziu 12& 1 su ne i

time ( e I

Figure 58 - Sehavioral Macromodel of the PLL - Pull-In Process

The behavioral macromodel is extremely useful because many of the circuit simulations
can be made without having to do the transistor level design. This allows new ideas to
be added to the conventional loop structure with minimal design effort. The behavioral
macromodel is very useful in modeling the switched tuning oscillator and the switch
control network.
 vco cmrnol Treneieni Reenonee of Mnlli-Bnnf pLL
B5
Frequency Step Input: tt„f(s)= — =
Iseo a51OMrad/sec
r
/
/
I

/+ No Cycle Slips Observed

15 I- with Linear Model
L
o

55 1.5 25
Time ieee)
x le

Figure 59 - Linear PLL Model - Pull-In Process (No Cycle Slips)

This switch control mechanism was added to the behavioral macromodel. Figure 60
displays the simulation results with the switch control mcchamsm added to the
behavioral macromodel. This simulation is showing the multi-band PLL acquiring lock
to synthesize a 222. 5MHz signal. Initially the PLL is synthesizing a 132.5MHz signal.
This is the mid-band signal of the first band. The input reference signal is approximately
4. 14MHz. The input reference frequency has a frequency step to approximately
6.95MHz at time zero in order to generate 222. 5MHz at the output. The acquisition
process of the PLL then takes place. The VCO control voltage rises and crosses thc
positive voltage threshold of 0 SV. The oscillator is then changed to the next higher
frequency channel. The VCO control voltage is then grounded to set it oscillating in the
mid-band of the second channel. Now the output signal is approximately 177.5MHz.
 87

The VCO control voltage rises again and crosses the positive threshold of 0.8V. The
oscillator is then changed to the third channel. The VCO control voltage is then
grounded to set it oscillating in the mid-band of the third channel. Now the output signal
is approximately 222. 5MHz. This is the correct frequency. However, there is still a
phase error present in the PLL system. The PLL undergoes some settling to force this
phase error to zero and the control voltage locks to synthesize the 222. 5MHz signal.

Behavioral Macromodel of the PLL with Switch Control Added

PLL 6 itching Up 7 o Channels

988m vCO Control voltage

Switch to Higher
688m F so
788m

688m

388m

488m
) 388m

288 In

188m

—188m

—288m
8 6.8u 9 Bu 12U su
(e
1

time )

Figure 60 - Behavioral PLL Macromodel with Switch Control Circuitry

Another key advantage ta using a behavioral macromodel such as the onc discussed is
the ability to interface transistor level design with behavioral code. The behavioral
macromodel is considered an ideal system. The transistor level blocks will mtroduce
non-idealities into the system. The ability to interface transistor level blocks with an
ideal system is very important because tt allows onc to see the direct effects of that
specific block's non-ideal)ties on the loop performance. Design changes can be made
rapidly with the behavioral macromodel to account for the non-idealities of the transistor
level blocks.

Transistor Level Block Design

The multi-band PLL frequency synthesizer system is designed using the AMI1. 2p.

CMOS process through the MOSIS foundry. This is an nwell process. It has double
metal and double poly layers. The threshold voltage and transconductance technology
parameters are given for this process in Table 8.

Table 8 —AMI1. 2p CMOS Process Technolo10 Parameters

Transistor Vro KP
NMOS 0, 7194V
PMOS -0.8165 21.500ttA/V

Phase/Frc uenc Detector

The PFD circuit used is bastcally thc same as the one presented in the previous section,
with only a few modificattons. The most important modtfication is that the VCO

feedback signal, v», is dnvtng the UP signal, while thc input reference signal, v„, ,
dttvcs the DOWiV signal. Thts connection is reversed in the one presented m the

previous section. The reason for this modification is that the designed VCO has a
negative converston gain. To cancel this negative conversion gain the connections arc
flipped into the PFD as shown in Figurc 61.
 89

VDD UP
D Q
DFFR
UP
Ib CLK Q
R

VDD R DOWN
D Q
DFFR
DOWN
CLK

Figure 61 - Multi-Sand PLL Phase/Frequency Detector Circuit

Thc D Flip-Flops used are optimized specifically for operation in the PFD[1 1). The
schematic is given in Figure 62. The flip-flops are designed with a small number of
devices in the signal path to increase speed. The flip-flop has no D input because it is
designed specifically for a PFD application where the D mput is always high. The flip-
flop's Q output goes high on a rising CLK edge as long as thc R input is low. The Q

output stays high until it is forced low by the R signal going high. The Q output will

remain low as long as the R input is high. The 0 output returns high on the next rising

edge of the CLK after the R input returns low.

VDD

M1 M6 M10
M13

ci K M2 Q Ms M7 Ms

M12
M3 M4 MB M11

VSS

Figure 62 - PFD D Flip-1 lop Schematic

 90

The schematic of the AND gate is shown in Figure 63.

voD

A Ms M4 Ms

M2

M1 MS

vss

Figure 63 - PFD AND Gate

PFD Desi n Procedure and Simulation Results

The PFD D flip-flop design flow diagram is shown in Figurc 64. Thts circuit is designed
to operate between I-15MHz to insure that it will operate correctly in the 100-300MHz
PLL system.

Design First Stage (M1, M2, & M3)

to Dnve M5

Design Second Stage (M4, M5, MB & M7)

to Drive M10 & MB
J
Design Third Stage (MB, Mg, M10 & M11)
to Dnve M3, M6, M7, M12 & M13

Design Output Stage (M12 & M13) to

Dnve Charge Pump & AND Gate

Venfy Circuit Operation at 1 5 1 5MHz

Circuit Operating Reset Path

Works
Too Slow Too Fast

Increase M2, Design

Reduce M11
M5, & M10 Finished

Figure 64 - PFD D Flip-Flop Design Flow Diagram

 91

The first stage consists of transistors Ml, M2, and M3. It is designed to drive M5. This
first stage only has to drive one transistor gate. Therefore Ml, M2, and M3 are made the
practical minimum size.

(87)

The second stage consists of transistors M4, M5, M6 and M7. It is designed to drive
MIO and M8. M4 and M5 are made twice the practical minimum size because they are
in series. M6 and M7 are made the practical minimum size.

L „12@ L, , 12p (88)

The third stage consists of transistors M8, M9, M10, and Ml1. It is designed to drive
M3, M6, M7, M12, M13, the AND gate, and the charge pump switches. M8 and M10
act as the Q signal path inverter. M9 and Ml1 operate as the reset invertcr. The M8

and M10 inverter is designed for symmetric output drive[48J. This involves matching
the effective pull-up resistance of M10 in series with the reset switch M9 to the pull-
down resistance of M8. The resistance of thc transistors is proportional to the following:

L~ s
R~ r (89)
Ws pKP~ p

Transistor M9 is set equal to twice the practical minimum length in order to lower its on

resistance. Selling R, and Rip equal yields the following relation between thc aspect

ratios ol' M8 and M10.

W KP~ W 69.559@6/ V W W

This nitio is incrcascd to 4 to compensate for the on resistance of M9. Transistor Ml 1 is

sized to pull thc output of the third stage low when the reset signal goes high.
 92

W 2.4/t
(91)

The output inverter stage consists of M12 and M13. It is optimized to switch on the
logic levels of the third stage and to drive the charge pump switches.

W 4 8/t W 7 2/t
(92)
Table 9 summarizes the sizes of the transistors used in the PFD D Flip-Flop.

Table 9 - PFD D Flip-Flop Size Ratios

(W/L)i t is 7 s (W/L)gs a i2 (W/L)m (W/L) „(W/L) i3

2.4tt/1. 2tt 4. 8tt/1. 2p 9.6tt/1. 2tt 12ti/1. 2tr 7.2 i/1. 2

This circuit can I'ail at high frequencies due to delays in the signal path. Increasing the
drive strength of thc transistors in the signal path can alleviate this problem. This is
accomplished by increasing the aspect ratio of M2, M5, and MIO. It is preferable to
increase the dimensions in an order from M2 to M5 to MIO so that the input stages are

not overloaded.

This circuit can fail at low frequencies due to the reset path being too fast. This could

result in thc circuit not resetting properly. This also contributes to the PFD dead zone
that increases the phase noise or )itter in the output signal as discussed in the previous

section. Reducing the aspect ratio of Ml I can alleviate this problem. This increases the
reset time.
 93

The AND gate consists of a four transistor NAND input stage and an inverter output.
The AND gate is designed for symmetric output drive. The inverter output stage is sized
the same as M12 and M13 of the D Flip Flop. The input NAND stage can be viewed as
2 PMOS switched in parallel and 2 NMOS switches in series. Setting the pull-up
resistance equal to the pull-down resistance yields the following relationship between the

input PMOS and NMOS transistors.

L 4 21 5/t/t/V L ~ L
(93)
v 4K'
This relationship is rounded to set all the PMOS input transistors equal to the NMOS

input transistors. Table 10 summarizes the sizes of the transistors used in the PFD AND
gate.

Table 10 - Pl'D AND Gate Size Ratios

(W/L) i z a» s (W/L)s
2.4(t/L2lt 7.2p/L2p

Some simulation results of the PFD are shown in Figure 65. Refernng back to Figure
61, there is a 9.375MHz v, u signal and a 6.25MHz v» signal in this simulation. The

v„„/ signal corresponds to the input reference frequency of the PLL. The v» signal

corresponds to the frequency divided VCO feedback signal. A rising edge on the v„,,

signal causes the DOWN signal to go high first. The DOWN signal stays high until a

rising edge of v» causes UP to go high. UP and DOWN are now both high for a short

period. '1'his causes thc AND gate reset output to go high and force (/P and DOWN

low. This cycle is repeated with another rising edge of v u. The overall effeci. of this is

that with a significantly faster v„,,

&
signal the DOWN signal is high I'or a significant

period of time. This will force the charge pump to discharge thc loop filter and the VCO
 94

control voltage will drop. This wi]l increase the VCO output's frequency and in turn the

v& signal's frequency.

Phase/Frequency Detector Simulation Results

DOwN
?a

soam UP

) —isa»i I

1»0c ?sa ~ -' lc1

lj&i U ~JL
S O ll ?Doc
I
»m is)
Figure 65 - Phase/Frequency Detector Simulation Results

~Ch P
The charge pump designed in this system is shown in Figure 66. The circuit consists of

a PMOS current mirror (MS and M6) to mirror I»P into the charge pump. This ID,

current either goes into the loop filter or into the ground node depending on the position

of the two PMOS switches (M I and Mg). An NMOS current mirror (M7 and M8) is

used to mirror 1„»wv into the charge pump. This 1»»w„current either discharges the

loop filter or pulls current from the ground node depending on the position of the two
NMOS switches (M3 and M4).
 95

VDD

M6 M5

loowN

Upi M1 M2 6 Up
lour

DOWN g M3 M4
I DOWN

1„, l

VSS

Figure 66 - Charge Pump Schematic

lap and lnc~yg are both set equal to insure a constant phase detector gain. These

currents are set to the following value.

le = Ioowv 25' (94)

The charge pump must satisfy a certain voltage compliance to generate a relatively
constant output current over the output range of the VCO control voltage. The VCO has
a tuning range of 1.6V with a 2.7V supply. This implies the following compliance
voltage.
3l
Charge Pump Voltage Compliance = 550mV From Each Ratl ( 95 )

Char~c Pum Desi on Procedure and Simulation Results

The design procedure for thc charge pump is presented. The charge pump sources or
sinks 25ttA of current over an output voltage range of+0.8V.
 96

1. Set the proper Va~r values for transistors M5 and M7 to satisfy the voltage
0, $
compliance range. The Va~r for M5 and M7 is set to 0.3V to insure that they do not
tt 6
go out of saturation when the output node swings from +0.8V. This Vc,„r value also
o, 4
allows for a possible 0.25V drop across the switch transistors Ml-4. A Va~r value

of 0.3V results in the following minimum sizes for M5, M6, M7, and M8.

2. Size the switch transistors Ml-4 io insure that the voltage drop across the switches
does not exceed 0.25V. In order to meet this requirement a value of 0. 15V is used
for the calculation. This results in the following minimum sizes for Ml-4.

W'I
(
wf 25/tA (97)
( L J, , 21.5/tA/ V 2. 25V —.8165VS0. 15V)
w) 25/tA

c
The transistor sizes were optimized through computer simulation in Spectre. Thc final
sizes are given in Table I l.

Table 11 - Charge Pump Size Ratios

(W/L), 2 (W/L)3 a (W/L)s s (W/L)r s

6.6 Ii/1. 2 Ii 3 Ii/I .Zp 55.2lt/1. 8It 51.6p/2. 4It

Some simulation results of the charge pump are shown in Figure 67. In this simulation

the UP and DOWN signals are ~I.35V 200Hz square waves. (/P and DOWN are

logic c&&mplements. A 10nF capacitor loads the output of the charge pump. The charge
 97

pump positively charges the load capacitor with I» when UP is high and negatively

charges the load capacitor with Ieo~N when DOWN is high. The output current will

vary slightly with the output voltage level due to channel length modulation effects. The
average output c(urent is measured from the voltage slope over the W. 8V region of
interest for the multi-band PLL system. When UP is high the charge pump sources
24.0(iA of current into the loop filter. The charge pump sinks —25.0(iA of current from
the loop filter when DOWN is high.

' Irrg(-qe Pu(Tp SLOLOulat(L-rrn Fuge LltS

Output Current A 18nr Cupu
Charging iar

Charge Pum Oulp it Voltage

UP = OOWNBrLP

758m

'
. Average Iup = 24.0(tA Average I = p25. 0(7A

/
/
—758m /
/
/

—15
2.8m neo 4 em 5.8m 5 8 la 7.8m
time ( e )

I'igure 67 - Charge Pump Simulation Results

L~el i

The loop filter is I'ully integrated on chip by using poly2 —polyl capacitors and a poly I

resistor as shown in Figure 68. The key issue here is (he silicon area associated with (he
filter components.
 poly2 - poly 1
Capacitor

C, i2~ C,

poly i

poly l Reaiator

Figure 6S - Fully Integrated Loop Filter

2
The capacitance per area parameter for poly2 —polyl capacitors is 61 laF/ttm . This
yields the following area for the two capacitors.

62.2 FF
C, Area= . =101.8x106pm' m 320pmx320pm
p (98)
6pF = 9.82xl0 pm m100pmx 100pm
C, Area=
611&F
r

A picture of the loop filter capacitors is shown in Figure 69.

62 apF Capaotor 6pF Capaolor

Figure 69 - Loop Filter Capacitors

 99

The polyl resistor also occupies significant area. However, the resistor area is not on the
same scale as the capacitor area. The sheet resistance for polyl is 29 ohms/square and

the polyl contact resistance is 36.2 ohms. The resistor required for the loop filter is
3LgkQ. Placing several contacts in parallel at both ends of the resistor allows the
contact resistance to be effectively neglected in computing the number of squares.
Neglecting the contact resistance results in the following number of squares for the
resistor.

= 3 L8kQ = 1097 squares

¹ squares (99)
29ohm/s
/square
This results in a resistor of 1316lim long using minimum polyl width of' 1.2pm. A
picture of the loop filter resistor is shown in Figure 70.

Figure 70 - Loop Filter 3Lgkf 1 Resistor Layout

The I'requency response of the layout extracted loop filter is shown in Figure 71. The

filter has a pole at zero and a zero at approximately 80.5kHz. The capacitor Ci in the

loop filter causes the high frequency second pole.

 100

Layout Extracted Loop Filter Frequency Response

r: Filter Output

88.8
~Pote at OHz

Second Pole at f =
C,' +Ce ' = 915kHz
i 2aHC Ice
Zero at f = = 80.5kHz
28RC I

38 8
I IK 18K 188K IM 18M 188M
l ~z )

Figure 71 - Layout Extracted Frequency Response

Switched Tunin VCO

The switched tuning VCO designed in this system is shown in Figure 72. The VCO is a
three-stage ring VCO. The inverter stages are loaded with one contmuously l. uned

capacitor, Cc, and three discretely tuned capacitors, Col 3.

I v,
cc

MD MD

e vss 4 e
Di D2 D3 DI O' D:1 Di DZ D3

Figure 72 - Switched Tuning VCO

 101

The VCO inverter stages consist of single-ended CMOS inverters shown in Figure 73.

VDD

MN

VSS

Figure 73 - CMOS Inverter Delay Cell

Thc model shown in Figurc 74 can be used to analyze thc ring oscillator. The output
capacitors are lumped into one output capacitance Co .

Feedback Factor B(s)=1

A(s)

H(s) H(s)

"T
VSS

Figure 74 - Ring Oscillator Model

 102

The inthvidual invetter stages have the following transfer function.

gm +gm K
gop + gopi + sCO 1 + sT
(100)
gmp + gms
T=
gop + goir gop + gos
Here K is the DC gain and T is the inverse of the 3-cU3 bandwidth. This results in the
following open loop transfer function A(s).

A(s) = [a(s)J (101)

The oscillator's closed loop u. ansfer function is the following:

A(s) A(s) (102)

Closed Loop Transfer Function =
l —A(s)B(s) 1 —A(s)

The Barkhausen criteria for constant amplitude oscillation is the fogowing[49].

1. The phase of the loop gain should be zero at the Irequency of oscillation.
2. The magnitude of the loop gain should be unity at the frequency of oscillation.

The loop gain must be equal to the follovving in order for the circuit to oscillate.

A(s] (103)
This implies the following for the individual stages.

A(s] = [0 (s)]'~ (104)

td„,

The following equality can be solved for K and T.

+ ro„„T) + K ' = 0
(l j
3',„,T —K" = 1, ro,„,T' = 3to„„T (105)
K=2, T= —
8 wm„, =
 103

The frequency of oscillation is the square root of three times the inverter stage's 3-dB
bandwidth. Notice also that this implies that the inverter's DC gain must be exactly two
for constant amplitude oscillation. However, this exact value cannot be designed for.
Therefore, the inverters should be designed for a gain greater than two and the amplitude
will be controlled by a limiter. In this case the power supplies are the limiter. The
following equations can be used to achieve a desired frequency of oscillation.

Q3 s6(go + go„)
(106)
T C0

gnip + gm„
K= &2 (107)
gop + goN

The previous analysis assumes small-signal operation of the transistors. The oscillator is
actually a large signal oscillator because the output signal swings rail-to-rail. This large
signal operation allows the oscillator to be analyzed using propagation delays.

The VCO output signal propagates through thc ring oscillator each half period with an
inversion. If the output of thc third stage is low, the signal will propagate through the
three invcrters bel'ore the output of the third stage goes high. Each inverter has a

propagation delay t, . The time it takes for the output signal to go high is equal to the

sum of the propagation delays of the three invertcr stages. This time is equal to one half
T
period of oscillation, ' —,
2' as shown in the following:

—
T
=nt (108)
2

Thc VCO's angular frequency of oscillation, to„„, is derived from ( 108 ) to be the

I'ollowing. Herc n is the number of inverting stages.

nt 3t„ (109)
 104

The propagation delay is the average of the rise time, t ~, and the fall time, r, „z, as
shown in the following:

rP ~+r, m
2
(110 )
The fall time, r, „,, is mostly a function of the NMOS transistor in the inverter cell and

the total output capacitance, Cu, as shown in the following[50].

( "--'-'- 'll

The rise time. r, ~, is mostly a function of the PMOS transistor in the inverter cell and

the total output capacitance, Cu, as shown in the following[50].

c, i 2 v„ i
['4(vDD -iv„i]
Ice, (voa-Iv
P

Equations ( (06 ), ( 107 ), ( 111 ), and ( 112 ) can bc used to design the inverter stages
for a desired frequency response. These equations yield initial values that arc optimized
through simulations.

Changing the propagation delay of the inverter cells is used to tune the &CO's output
frequency. lt can be observed from thc following equations that the propagation delay is

proportional to the load capacitance Cn. This load capacitance is the summauon of any

loading capacitance, Cigar/s intentionally placed at the output of the inverting cells and

the parasitic capacitances associated with the otitput node of the inverting cell and the

mput node of the next inverting cell. The capacitors that make up Cn are given in thc

following equation whcrc the subscript 1 indicates the inverting cell and the subscript 2
indicates the next inverting cell.

u Twvr avl li'i al xi dirl rivi eei

( 113)
+ Ca»'~ + C ari + Crea~ + Cxiri = t ruvs + Cx, v~ + C, e~
 105

The output capacitance is simplified because the C„of the next inverter stage

dominates the parasitic capacitance.

Changing the propagation delay, and in turn the frequency of oscillation, is achieved
through capacitive tuning. Capacitive tuning loads the inverter stages with an RC
network as shown in Figure 75.

Figure 75 - Capacitive Tuning

The effective value of capacitance, C„&&, that the inverter sees at the output is equal to

the following.

C
1+ sCR (114)
This means that the effective capacitance is small for high values of R and the

propagation delay will be relatively low. This makes sense because as R becomes
large, the invcrter simply sees an open circuit output with little capacitance. As R

approaches zero, C, s approaches

, C and the propagation delay will increase. This

makes sense because if R is zero the inverter simply sees a capacitor shorted to ground.

Capacitive tumng is implemented in the switched tumng VCO with capacitors C, and

the NMOS active resistors MC. Thc capacitor Cc is the capacitor in ( 114 ) 1'or the

above oscillator analysis. This capacitor is the tuning capacitor and should he made as
large as possible compared the parasitic capacitances of the invertcr transistors in iirder

to have a wide tuning range. The active resistor*s resistance is tuned with the VCO
 106

controlling voltage v„. The frequency bands of operation are changed by discretely

switching in the capacitors Cp with the NMOS switches MD. Switching in the discrete

capacitors increases the tuning range of the oscillator. However, the VCO gain, K«o,
drops from the high frequency channel when there are no discrete capacitors to the low
frequency channel when all the discrete channels are switched in because the value of
the tuning capacitance is now a smaller percentage of the total capacitance.

Switched Tunin VCO Desi n Procedure and Simulation Results

The switched tuning VCO design flow diagram ls shown in Figure 76. This circuit is
designed to operate over a minimum frequency range of 100-300MHz.

Determine Optimal Aspect Ratios for

Inverter Cells to Maximize Osmllation
Frequency and Tuning Range

Determine Continuous and Discrete

Tuning Capacitors Sized to
Maximize Tuning Range

Determine Active Resistor Aspect

Ratio for a Significant Variation in
the Resistance Value

Determine Discrete Switches Aspect

Ratios for Minimal On Resistance

Verify Circuit Operation from

100 to 300MHz

Circuit Oscillating Tuning Range Not Enough

Works
W k
Too Slow Too Low Overlap

Increase Inverter Decrease Inverter Design Increase Continuous

Aspect Ratio Increase Tuning Caps Finished Tuning Capacitor

l'igure 76 - Switched Tuning VCO Design Flow Diagram

 107

The inverter aspect ratios are designed to yield a maximum oscillation frequency of
300MHz and a wide tuning range. Equations ( 106 ) and ( 113 ) are used to initially
determine the inverter aspect ratios for 300MHz operation. At this maximum frequency

C~« is the minimum tuning capacitance. It is assumed to be 40fF. Equation ( 106 ) is

simplified with ( 113 ) to yield the following.

rsr = sl3(go, + go„)

0

/nKr„( ) v, „)
t——v, +n, np, J ) I— —iv„if v, i

)N )p
2
C„, (Wn Ln + Wr I r )+ Crane
3

Minimum length transistors should be used in order to achieve maximum oscillation

frequency with minimum area. This allows equation ( 115 ) to be simplified to the
following.

3Z&Jt/, , KP,, W (Vs Vrn) +A,, KPpW (Vos -lVo, ~) j

4C„,L (W +Wr )+ LCr~a

The minimum length /I parameters were determined through computer simulation to be

the following.

/1Ã = 0. I I IV', /Ip

—0.300V' (117)
The Vos values are assumed to be 1.35V because of large signal operation. Substituting

the technology parameters into equation ( 116 ) yields the following.

16.0 x10 'Wn + 9.55 x Wr

605x10 "(W +Wr)+48xl0 (118)

Increasing the transistor widths increases the oscillation frequency until the denominator
width term becomes much larger than the lowest tunable capacitance term. However,
increasing the transistors' widths will lower the tuning range because the parasitic
 108

capacitance becomes comparable to the tuning capacitance even when the tuning

capacitance is not minimal. Thus, changing the effective value of the tuning capacitance
has less of an effect on the total inverter load capacitance. The PMOS transistor
degrades the maximum frequency versus tuning range tradeoff because it only
contributes 37.4% to the maximum frequency, while contributing 50% of the parasitic
capacitance. The PMOS transistor width is set to be the following relation with the
NMOS in order to allow the PMOS to contribute 50% to the maximum frequency.

'
W = W =1.68W (119)
9.55 x10
Substituting equation ( 119 ) into equation ( I l8 ) and solving for 300MHz operation
yields the following initial values for W, and W,

Imtial Ws = 61.8p, Initial W„= I03.8p (120 )

These inverter aspect ratios must also satisfy the DC gain given in equation ( 107 ).
Equation ( 107 ) can be simplified to yield the following.

'
K- ,, g „. 2(~KI'ra
i ', ",t', -'„)'t*,
,
~KPW, )
". )
—13.3 & 2 (121)

The circuit will oscillate because it has a gain greater than two. The initial values were
optimized through simulation to yield the following aspect ratios.

W 60p W 88. 8p
(122)

The values of thc tuning capacitors, Cr, are chosen to be large enough to be

significantly greater than the parasitics, but not too big to significantly limit the

maximum frequency of oscillation. The continuous tuning capacitors, Cc, are chosen

larger than the discrete tuning capacitors, Cn m order to maximize the tumng range.
 109

The following capacitor values are chosen to cover the frequency range from 100—
300MHz.

Cc =600fF Cu =300fF (123)

The active resistor's aspect ratio is determined to provide a significant variation in the
resistance in order to vary the loading capacitance of the inverter cell. Making the
w'i
of the active resistor MC greater increases the variation in the resistance and thus
(
(w't
results in a larger tuning effect. However, a larger also produces more parasitic

capacitance and lowers the maximum output frequency. This is because the C,», and

C,„ofthe active resistor add to the total capacitance the inverter stages have to charge.

The aspect ratio of MC is chosen to provide a sigmficant variation in the resistance and
to not signilicantly limit the maximum frequency of oscillation. The resistani. e of the
active resistor is approximated by the following formula.
I
R
W
L
(V., —v, .)
( 124)

As the VCO control voltage varies from —0.8V to 0.8V the resistance varies from the

GQ range when the transistor is cut-off to approximately

. (Wi
10kQ(L/W)c. This can
I ),
be increased to provide minimal resistance when v, is equal to 0.8V. However. this
increases C,», and C, , The aspect ratio is chosen to be the following to yield a

minimum resistance of approximately 500Q.

W 26.4p
( 125 )
 110

The other NMOS switches, MD, are designed such that their on resistance is minimal
and that their parasitic capacitance is not significant. The parasitic capacitors C» and

C,„reduce the maximum frequency of oscillation. Again, the resistance is

approximated by equation ( 124 ). The transistor is on when the controlling voltage,

Dl —D3, is equal to 1.3SV. This provides an on resistance of approximately

7.26kQ(L/W) D . This — can

(W'I
be increased to provide minimal on resistance.

However, this increases C» and C gd „. The aspect ratio is chosen to be the followmg to

yield an on resistance of approximately 5008.

W 16.8/t
(126)

Table 12 summarizes the transistor sizes and capacitor values used in the switched
tuning VCO design.

Table 12 - Switched Tuning UCO Transistor Sizes and Capacitor Ualues

(W/L)N (W/L)p (W/L)i (W/L)p Cc Co

60lt/1. 2li 88. 8lt/1. 2P 26.4li/1. 2 16.8lt/1. 2lt 600/F 300fl

The circuit oscillates too slow if the inverter propagation delay is too long. Increasing
the aspect ratios of the inverter transistors reduces the inverter propagation delay
because the delay is inversely proportional to the invertcr transistor aspect ratios. Care
should be taken not too increase the inverters too large as this increases the parasitic
capacitance at the output node and thus reduces the tuning range.

The circuit's tuning range becomes low when the parasitic capacitance of the inverter
transistors becomes comparable to thc tunmg capacitance. Reducing the inverter aspect
 111

ratios increases the tuning range because it reduces the parasitic capacitance. However,
the maximum frequency of oscillation is lowered due to a larger propagation delay.
Increasing the tuning capacitor's size will increase the tuning range because the inverters
will see a higher range of capacitance at the output node. This does not affect the
maximum frequency too much because these capacitors are not seen when the active
resistors are a large value.

The overlap between frequency bands becomes low when the parasitic and discrete

capacitance becomes comparable tn size to the continuous tuned capacitors Cc. The
continuous tuned capacitors should be increased in order to increase the frequency

overlap between I'requency bands.

A near maximum buffered VCO output frequency is shown in Figure 77. The VCO
oscillates at 340MHz when the continuous VCO control voltage, v, , is at —0.8V and the

three digital control signals, Dl —D3, are all low.

Post Ltgyoul .3:B t, . - I Tctntnq VCO Stf. tultg et nft I ctstglts

34BMtfe Signal

Buff ned MOO Output

(R
(

ig
L
127 n 129n 133n 1397 17n 139 n
trna(e)

Ii'igure 77 - Switched Tuning VCO Output Signal

 112

The switched tuning VCO's frequency response and phase noise performance over the
different bands of operation is given in Table 13. The transfer curves of the switched
tuning VCO are shown in Figure 78. The frequency bands of the actual designed VCO
are not as ideal as the ones in the design calculations. However, they do cover the entire
frequency range with enough spectrum overlap to provide a stable system. The
SpectreRF simulated phase noise values seem quite optimistic. While these phase noise
absolute values may not be correct, it is assumed that the relative values are correct and

design optimization was performed based on the changes in the phase noise values. The
phase noise performance of the VCO ts optimal at the edges of the bands where the
VCO conversion gain is the lowest. The worst VCO phase noise performance occurs in
the mid-band range where the VCO conversion gain is highest.

Table 13 - Switched Tuning VCO Frequency Response

Band Description Frequency Range (MHzi

Phase Noise 0
50kHz Offset (dBc/Hzl
All Switches Closed 99.8 —146.8 ~
-91.77 -103.7
2 Switches Closed I 21. 1 —185.2 -89.32 ~ -102
1 Switch Closed 148.2 —246. 5 86.01 ~ -99.75
All Switches en0 191.4 —341.8 -82.63 ~ -96.67
 113

Snaaned rtststg VCO Transfer Curves

000 t—

Band 4

+ 250- Band 3

o'
200-

Band 3
15D

Band I

10D

-0 5 0 05
VCO Control Voltage (V)

Figure 78 - Switched '1'uning VCO Transfer Curves

VCO Switch Control S stem

The VCO switch control system is shown in Figure 79. The switch control network
detects when the VCO control voltage crosses a positive threshold, VRFFP, or negative
threshold, VREFN, and changes the VCO channel by switching in or out different
tuning loads. The VCO control voltage is then grounded to set the VCO ln the middle of

thc next channel and to reset the system.

The tv, o comparators are used to detect when thc VCO control voltage crosses the

VREFP or VRFFN threshold. This provides a rising edge on the VP or DOWN

signal. The OR combination of the UP and DOWN signals is used as the CLK for a

state machlnc that changes the switch control signals accordingly. This CLK signal is
 114

also fed back to close a switch to ground the VCO control voltage to reset the tuning
system and insure loop stability. When the VCO control voltage has returned within the
thresholds sufficiently the switch to ground is opened and the UP or DOWN signals
return low. Comparators with hysteresis are used to avoid unnecessary switching due to
ripple in the VCO control voltage.

Switch
VCO Control Control
Voltage
VREFP
DOWN Dt
CL &tate
Machine D3
VREFN

Figure 79 - VCO Switch Control System

Switch Control State Machine Desi n Procedure and Simulation Results

The switch control state machine is designed by first forming the state diagram and then
synthesizing it into a sequential logic circuit. The state diagram for the state machine is
given in Figure 80. State zt corresponds to the lowest frequency hand l. All of the
VCO control signals Dl —D3 are high. This means that all of the discrete tuning
capacitors are loading each inverter cells of the VCO. State B corresponds to frequency
band 2. The VCO control signals Dl and D2 are high and D3 is Iow This means thai
two of the discrete tuning capacitors are loading each mverter cell of the VCO. State C

corresponds to frequency band 3. The VCO control signals Dl is high and D2 and D3
are low. This means that one of thc discrete tuning capacitors is loading each mverter
cell of the VCO. State D corresponds
to frequency band 4. The VCO control signals
Dl —D3 are low. This means that none of the discrete tuning capacitors are loading
 115

each inverter cell of the VCO. This state diagram is synthesized into the synchronous

logic circuit shown in Figure 81.

UP=0 UP=0
UP=0 DOWN = 0 DOWN =0 DOWN = 0

UP =1 UP =1 UP =1
State State State State
A B C D
DOWN =1 DOWN = 1 DOWN = 1
D1 =1 D1 =1 D1 =1 D1=0
D2 = 1 D2 = 1 D2 = 0 D2=0
D3 = 1 D3 = 0 D3= 0 D3=0

Figure 80 - Switch Control State Diagram

uv

D Q 'i
l Dl

?
ccv. Q

[iowa

D l)3
Q

&:i.v. Q -i

Figure 81 - Switch Control State Machine

Some simulation results of the state machine circuit are shown in Figure 8'2. This
simulation shows the stale machine circuit cycling from the initial state A when the
Dl —D3 outputs are high to state D when the Dl —D3 outputs are Iow because the UP
signal is high and the circuit is clocked 3 times. UP then goes low and DOWN

becomes high. The circuit then cycles from state D to state A because the DOWN
signal is high and the circuit is clocked 3 times.
 116

State Machine Simulation Results

D3

—28

D2

—2.8

2, 8
—28

28 DOWN

—2.8

28 UP

8 CLK

—28
4. 88u 6. 28u 6 48 ~ 18 6u 12.6u 15 Bu
Orne(e)

Figure 82 - Switch Control State Machine Simulation Results

Switch Control Com Orators wtth H sterisis Desion Procedure and Simulation Results

The comparators with hystensis used in the switch control system are shown in Figure
83 and Figure 84[39,48, 51,62]. Due to the low power supply of 2.7V, an NMOS
comparator is used to compare the VCO control voltage, v, , with the 0.8V VREFP
signal and a PMOS comparator is used to compare v, with the —0.8V VREFNV signal.

Two comparators are destgncd to insure ihat the transistor with the threshold voltage

inPut does not always oPerate in cutoff duc to ~VDB ~

being less than ~Vr .
 117

VDD

M3 M10 M11

25@A M8

VREFP g M1 M2 P v,

DOWN

M12 M7

M9 M6

VSS

Figure 83 - Positive Threshold NMOS Comparator

VDD

M12 M7

UP

v, g M1 M2 P VREFN

25pA L~ M8 M5

M3 M10 M11

VSS

Figure 84 - Negative Threshold PMOS Comparator

 118

The comparators consist of a differential input stage formed by Ml-M2. M7 is the tail
current source. The differential input stage is loaded with the cross-coupled transistors
M3-M4 and M10-Mll. There are two feedback paths associated with this circuit.
Negative current feedback is achieved by the common source node of Ml-M2[51, 52].
Positive voltage-shunt feedback is formed by M10-M11[51,52]. Hysterisis is formed
when the positive feedback is greater then the negative feedback. This is achieved under

the following condition[39].

('j. /I-:l. " (127)

Thts hysterisis is illustrated in Figure 85 that displays the transfer characteristic of the
NMOS comparator.

DOWN

1'igure 85 - Transfer Characteristic of a Comparator with Hysterisis

When hysterisis occurs the rising mput signal, v, , must pass the VRFFP signal by Vr«,

before the output switches from low to high. When v, is falhng &t must be lower than

the VRFFP signal by Vrs~ before the output switches from high to low. The trip points
 119

are a function of the positive feedback factor, —

10
—, 3
and the tail current I
TAIL

as given in the following expressions[51, 52].

VTRe+

(128)

VrRe-

Based on thc value of the ripple on the VCO control voltage, the trip points are set at a
minimum of 100mV from the reference voltage. In the design of the comparators a

fccdback factor of 8 is chosen for the NMOS comparator and a feedback factor of 40 is
used for thc PMOS comparator in order to achieve the desired hystcrisis. This results in
the I'ollowing relationship betwccn M3-M4 and M I 0-M11.

(129)

A significant gain is needed for the comparators to switch hard. Therefore, a large gain
is assigned to the M3-M6 and M4-M5 mirror stage. A gain of 24 is chosen for the
NMOS comparator and a gain of 110 is chosen for the PMOS comparator. This results
in the followmg relationship betwccn M3-M4 and MS-M8.

(130)

A ratio of 16 is used in the NMOS differential pair to achieve the desired gain and a ratio
of 37 is used in the PMOS differential pair.
 120

=16, — = 37
(131)

The tail current transistor M7 is sized to stay in saturation with a compliance voltage of
400mV from the power rail. This results in the following minimum values for M7.

(132)

A summary of the transistor sizes for the two comparators is given m Table 14.

Table 14 - Comparators with Hysterisis Transistor Sizes

Ty e (W/L)t q (W/L)s q (W/L)tp tt (W/L)s s (W/L)&, 9 (W/L)z tz

NMOS 48 3 3p/1. 2p 24p/1. 2p 72 t/L2 24p/1. 2u 90p/12
PMOS 44.4p/1. 2p 2.4p/24p 4. 8p/1. 2p 13.2p/1. 2p 24p/1. 2p 90p/2. 4p

The simulated transfer characterist&c for the NMOS comparator is given in Figure 86.
Thc VRFFP value is set to 0.8V and applied to the negative input. The VCO control
voltage is swept from the negative rail to the positive rail and then back to the negative

rail. The positive trip point, Vr„~, , is found to be 945mV. The negative trip point, Vrsp

is tound to be 656mV. This exceeds the desired ripple margin of 100mV from the
threshold.
 121

Positive NMOS Comparator with Hysterisis

Corooarator Output

v, ,= 945mv
7 5 itm

—75ttm

a (v)

Figure 86 - NMOS Comparator with Hysterisis Transfer Characteristic

The simulated transfer characteristic lor the PMOS comparator is given in Figure 87.
Thc VREFW value is set to -0.8V and applied to the positive input. The VCO control
voltage is swept from the positive rail to the negative rail and then back to the positive

rail. The negative trip point, V«„, is found to be —1.05V. The positive trip point, Vrsp,

is found to he -550mV. This exceeds the desired ripple margin of 100mV from the
threshold.
 122

Negative PfvtOS Camparator with Hysteasis

Camparatar Output

zse Vmp. = '»

—55pm

V„„=-550mv

1 5
—15 a. tt 15
dc (v)

Figure 87 - PMOS Comparator with Hysterisis Transfer Characteristic

L~DD d

The multi-band PLL frequency synthesizer has a fixed division ratio of JV = 32. The
loop divider conststs of five cascaded divide-by-two circuits as shown tn Figure 88. The

dtvtdc-by-two circuits are implemented with D Flip-Flops that have the Q outputs fed

back tnto the D inputs. The CLK signal is the input signal and the Q signal is the

divide-by-two output.

LD [
l

Q Q D Q D Q 'D Q fvcorat
1

fuco ~ CLK Q CLK Q L !D CLK JQ ' mr' CLK Q i& CLK Q

Figure 88 - Loop Divider Schematic

 123

The schematic of the flip-flops that are used in the loop divider is shown in Figure
89[26]. These are dynamic flip-flops that operate at very high frequencies. The loop
divider is the second most difficult circuit to design in the PLL after the VCO. The first

flip-flop is especially difficult to design because it must operate at the same frequencies
as the VCO.

VDD

M7
CLK f M1
~+ M4 ~
D QBAR
M10

4 t,--
Does/ I 9L 5

Msg
VSS

Figure 89 - Dynamic D Flip-I'lop Schematic

The dynamic flip-flop used as a divide-by-2 can be looked at as the circuit shown in
Figure 90. It is basically three clocked inverters cascaded with an output inverter. Thc
first inverter operates when the clock is low, while the second and third inverters operate

when the clock is high. This staggenng of the clock control signals produces an output

frequency half of the clock frequency.

CLK
2

CLK CLK CLK

Figure 90 - Dynamic Divide-by-2 D Flip-Flop

 Loo Divider Desi n Procedure and Simulation Results
The design of the loop divider is nontrivial due to the high frequency of operation of the
dynamic flip-flops and the wide range of operation. The circuit is designed such that it
is fast enough to operate at the highest frequency, but not too fast as to work improperly
at the lower frequencies due to the early discharge of some nodes. This requires not all
the flip-flops to have the same transistor sizes. The first two flip-flops are optimized for

high speed, while the last three are optimized for mid to low frequency operation. In
discussing the design of the flip-flop's transistors the subscript A refers to the first two

flip-flops and B refers to the last three. The design procedure of the flip-flops is similar
to the design procedure of the VCO where the circuit is designed and opttmized through
computer simulation while understandmg the basic operation of thc circuit. The loop
divider D flip-flop design flow diagram is shown in Figure 91. The loop divider must
operate from 100-300MHz.

Design First Stage (M1, M2, & M3)

to Drive M5

Design Second Stage (M4, M5, & M6)

to Dnve M7 & MB

Design Third Stage (M7, MB, & M9)

to Dnve M10 8 M11

Design Output Stage (M10 & M11) to

Drive Next M1, M6, M4, & M9 or PFD

Venfy Circuit Operation from

100 to 300MHz
z
Circuit Operating Circuit Nodes
Works
Too Slow Discharging

Reduce M2 & M3 Design Reduce M3,

Increase M5, M7 & MB Finished M4, & M7

Figure 91 - Loop Divider D Flip-Flop Design Flow Diagram

 125

The first stage of the flip-flop consists of Ml, M2, and M3. This stage is active when
the clock signal is low. Ml acts as a switch to VDD which is used to power the M2-M3
inverter. This inverter must drive the following parasitic capacitors in a minimum of
four times the maximum CLK frequency in order to switch M5.

Cr&r~&(ai: Ciai + C~i& C~~i +

(133)
C~„+C,~, +C„, +C„, = C„,
This parasitic capacitance is assumed to be 50fF. A switching current of approximately
ImA is needed to charge the parasitic capacitors in approximately 135ps to switch M5.
This insures the flip-flop will operate at the maximum CLK of 300MHz. This implies
the followmg aspect ratio for M3.

w) 21
—VSS —Vr„)
( L Ji KPv (VDD (134)
2(le) 9.6p

M2 is designed for symmetric output drive. This implies the following aspect ratio for
M2.

H, =:::H- (135 )
69.559~/V (9.6p) $9.6p) 28.8)t
21'5 pA/V
l I'2p ) 7 I '2p ) I'2p
Ml is sized so that it can supply enough cunent fast enough to power the inverter when
the clock goes low. Thc charge time is noi as critical in the cascaded stages so Ml is

made smaller in the B cell.

IV lb. 8p W 4. 8p
(136)

The second stage of the flip-flop consists of M4, M5, and M6. This stage is active when
the clock is high. M4 prechargcs the output of this stage to VDD when the clock is low.
When the clock goes high M6 supplies power to M5 which acts as an inveitcr. If the
 126

gate of MS is high the output will get pulled low. If the gate of MS is low the output will
stay high due to prechar~ng by M4. MS must drive the following parasitic capacitors in
a minimum of four times the maximum CLK frequency in order to switch M7 and Mg.

ptsstU///s2 gd5 db5 gd4 dbd g/7

(137)
Cg„+ Cg„Cg„+ gd, + g„—,+ g„
This parasitic capacitance is assumed to be 100fF. A switching current of approximately
2.SmA is needed to charge the parasitic capacitors in approximately 108ps to switch M7
and M8. This insures the flip-flop will operate at the maximum CLK frequency of
300MHz. This implies the following aspect ratio for MS.

Wi 227

( KPN (VDD —VSS —Viv )

Jg (138)
2(2.SmA) 21.6p
, —18.3 m

M4 and M6 are sized so that they can charge their drain nodes quickly. The charge
times are not as critical in the cascaded stages so M4 and M6 are made smaller in the B
cell.

W 43.2p W 16.8p
(139)
W) 33p I
W I
312p

The third stage of the flip-flop consists of M7, M8, and M9. This stage is active when
the clock is high. M9 acts as a switch to VSS which is used to power thc M7-M8
inverter This inverter must drive the following parasitic capacitor m a minimum of four
times the maximum CLK frequency in order to switch M10, Ml 1, M2, and M3.
C st s s stt 5 47 + C4 7 + C
/ /4 45 +C f/ 5 +C t lQ
+C 4 l l7

i//f s/l d/l bll Cgt2 d2 gb2 (140)

 127

This parasitic capacitance is assumed to be 100fF. A switching current of approximately

2mA is needed to charge the parasitic capacitors in approximately 135ps for the high
frequency flip-flops. Approximately lmA switching current is required to charge the
parasitic capacitors in approximately 270ps for the lower frequency flip-flops. This
implies the following aspect ratio for Mg.

w) 2I
—VSS —V~ )'
( L ), KP~ (VDD (141)

L,„L2P L, o L2P
M7 is designed for symmetric output drive. This implies the following aspect ratio for
M7.

KP„(W'I 69119pA/Vr(W)
(W) $wj (142)

M9 is sized so that it can supply enough current fast enough to power the inverter when
thc clock goes low. The charge time is not as critical in the cascaded stages so M9 is

made smaller in the B cell.

L,„L2p L, o L2Iz
(143)

The output inveigler stage consists of M10 and Ml1. This inverter must drive the

following parasitic capacitors in a minimum of four times the maximum CLK

frequency in order to switch Ml, M4, M6, and M9 or the PFD input transistors

C»i 0 Ceio+Cdoio+Cidu+Can, +C»+

( 144 )

Co„, +C„„,+C„„,+Cx„= C,„, +C„, +C„, +Cr o

This parasitic capacitance is assumed to be 100fF. A switching current of approximately

2mA is needed in order to dove the parasitic capacitors in approximately l35ps. This
implies the following aspect ratio for Ml I.
 128

w'I 2I
—VSS —V~ )
( L )u KPg (VDD (145)
2(2m')
69.559/zA/V' 2.7V —.
7194V)
The NMOS transistor M11 in the first two stages is made slightly larger to aid in driving
the following stages.

W 19.2/z W 16.8/z
(146)
M10 is designed for symmetric output drive. This implies the following aspect ratio for
M10.

L KPP I-
io (147)
69.559 pA/V ' W W 50.4/t

Table 15 summanzcs the transistor sizes or the dynamic

1 fli-flops.

Table 15 - Dynamic Flip-Flop Transistor Sizes

Fli -Flo (W/L) i (W/L). (W/L)s (W/L)p

A 16.8p/1. 2B. 28. 8 i/1. 2 9.6 /1. 2 43.2p/1. 2p
4. 8p/1. 2p 28.8p/1. 2p 9.6 /1. 2B 16.8p/1. 2p
Fli -Flo (W/L)s (W/L)s (W/L)t (W/L)8
21.6p/1. 2p 33B/1.2p. 40. 8p/1. 2p 16.8B/1. ZB.
21.6p/1. 2p 31.2p/1. 2p 28.2p/1. 2 p 9.6p/1. 2p
Fli -Flo (W/L)v (W/L) in (W/L) i,
24p/1. 2p 50.4 /1. 2B 19.2p/1. 2p
B 12p/1. 2B 50.4p/1. 2p 16.8B/1. 2p

This circuit can fail at high frequencies duc to delays in the signal path. Optimizing the

drive ratios ol' stages one through three can alleviate this problem. M2 and M3 can be
made slightly smaller because they dove only M5. M5 can be incrcascd to dove M7 and
 129

M8 faster. M7 and M8 can be increased to drive the output stage faster. The sizes
should be adjusted in the mentioned order to achieve optimal frequency performance.

This circuit can fail at low frequencies due to the discharge of the stages' output nodes.
Increasing the output resistance of the stages alleviates this problem. Reducing M3, M4,
and M7 accomplishes this.

Figure 92 shows the simulation of the loop divider operating at 300MHz.

Loop Divider : rr
. i. ation Results
Loop Oi eer Operat ng a. 388M¹
9 37313Hz Output Signal

388M-I I pu: S gnal

18 g 1
i]

1.8
ILII!
lan 1.38n 158n 1781n lg8n 2 18n 238n agn
i
I "1el ~

Figure 92 - Loop Divider Simulation Results

Multi-Band Pl L System Simulation Results

The transistor level building blocks are combined to form the multi-band PLL system.
System level simulattons are done to vent'y the Functionality of the multi-band PLL
system. The performance of the multi-band PLL system is illustrated through 5 case
studies. These case studies range from synthegiznng a signal in-band to more complex
 130

situations such as synthesizing an edge-of-band signal or a signal that falls in the channel

overlap. The multi-band PLL is initially operating in the multi-band region of band 4 at

a frequency of 280MHz for all cases. Table 16 summarizes the setup for each case.

Table 16 - Multi-Band PLL Frequency Synthesizer Case Studies

Initial Simulation Acquisition

Case Final Frequency
Fre uenc T e Time
A 280MHz 310MHz 30MHz Mid-Band 5 s
Mid-Band
B 280MHz 190MHz -90MHz 13tis
(Band Change)
Lowest Edge-
280MHz 100MHz -180MHz 18ps
of-Band
Highest Edge-
D 280MHz 340MHz 60MHz 19tts
of Band
E 280MHz 160MHz -120MHz Overl a 14tis

Case A
Thc first system level simulation presented shows the PLL synthesizing a 310MHz

signal. This illustrates a situation where a mid-band frequency in the current hand is

heing synthesized. Figure 93 shows the VCO control signals. All three digital inputs are

initially low which means the PLL is in the correct band of operation. The initial output
is approximately 280MHz. The VCO control voltage then settles to synthesize 310MHz
without triggering the switch control mechanism. The acquisition time is approximately
5ps. This acquisition time is low because the frequency change is within the lock range.
Figure 94 shows thc 310MHz output signal and its frequency spectrum.
 131

Multi —Band PLL Synthesizing a 310MHz Signal

VCO Control Signals
D3 D2
288m -. Dt VCD Control Voltage

VCO Control Voltage

—288m

—488m

—688m
&

—688m

—1 28
Dl, D2, & D3
— 48
1

8 2 8u 4 8u 6 ou 68u 18
t laze ( s )

Figure 93 - VCO Control Signals for Multi-Band PLL 310MHz Output

Multi--Band -'LL Synti esjzjnq a 3i8MBz Siar, al

vCO Outrzut VCO 0itnur Fr*au*ncy Fcctrum
F

jt
/!

io
—48

—28
1888u 4 885u 4 818u ' 8'Su
— '1 828u 218M 26af' 318M 3681) 418M
time j "=) rr uuency ( Hz )

Figure 94 - 310MHz Multi-Band PLL Output Signal

 132

Case B
The second system level simulation presented shows the PLL synthesizing a 190MHz
signal. This illustrates a situation where a mid-band frequency out of the current band is

being synthesized. Figure 95 shows the VCO control signals. All three digital inputs are
initially low which means the PLL is not in the correct band of operation. The initial
output is approximately 280MHz. The VCO control voltage rises and triggers the switch
control mechanism. The digital control signal Dl then goes high and the VCO control
voltage is grounded. The PLL is now in the correct band of operation. The VCO connol
voltage then settles to synthesize 190MHz. The acquisition time is approximately 13fts.
This acquisition time is longer because thc frequency change is outside the lock range
and thc acquisition process becomes a pull-in process. Figure 96 shows the 190MHz
output signal and its frequency spectrum.

Multi Band PLL Bynt iesizinq a 190MHz Biqnal

VCD C otrot Stttoolu
D3 D2
ID I VCD Cortrot Vot!uS '

VCO Control Voltage

D1

D2 & D3

4. eu e eu 12U 22 ~
tletu (

Figure 95 - VCO Control Signals for Multi-Band PLL l 90MHz Output

 133

Multi —Band PLL Synthesizing a 190MHz Signal

VCO Output VCO Output Frequency Spectrum

zn
—48

—28
19.888u 19 885 u 19 818c 19 815u 19.828u IBBM 158M 228M z SBM
tme(e) frequency ( ttz )

Figure 96 - 190MHz Multi-Band PLL Output Signal

Case C
The third system level simulation presented shows the PLL synthesizing a 100MHz

signal. This illustrates a situation where close to the lowest edge-ol-band frequency is

being synthesized. Figure 97 shows the VCO control signals. All three digital inputs are

mitially low which means the PLL is not in the correct band of operation. 1'he initial

output is approximately 280MHz. The VCO control voltage rises and triggers the switch
control mechamsm. The digital control signal Dl then goes high and the VCO control
voltage is grounded. The PLL is still not in the correct band of operation. Thc VCO
control voltage nses and triggers the switch control mechanism. The digital control
signal DZ then goes high and the VCO control voltage is grounded. The PLL is still not

in the conect band of operation. The VCO control voltage rises and triggers the switch
control mechanism. Thc digital control signal D3 then goes high and the VCO control
voltage is grounded. The PLL is now in the correct band of operation. The VCO control
voltage then settles to synthesize 100MHz. The acquisition time is approximately 18ps.
 134

This acquisition time is longer because the frequency change is outside the lock range
and the acquisition process becomes a pull-in process. Figure 98 shows the 100MHz
output signal and its frequency spectrum.

Multi —Band PLL Synthesizing a 100MHz Signal

VCO Control Signals
D3 D2
14 - Dl VCO Control Voltage

VCO Control Voltage

Dt D2

lou 28u

Figure 97 - VCO Control Signals for Yllulti-Band PLL 100MHz Output

 135

Multi —Band PLL Synthesizing a 100MHz Signal

VCO Output 18, VCO Output Frequency Spectrum

1.8

—28

—28 —r8
19 888 u 19 885u 19 818u 19 815u 19 828u I pea 158ty
ume ( e) reqcency ( 1qz i

Figure 98 - 100MHz 1VIulti-Iland PLL Output Signal

Case D
Thc fourth system level simulation presented shows the PLL synthesizing a 340MHz
signal. This illustrates a situation where close to the highest edge-of-band frequency is

being synthesized. Figure 99 shows the VCO control signals. All three digital inputs are

initially low which means the PLL is in the correct band of operation. The initial output
is approximately 280MHz. Even though the PLL is in the correct band of operation, the
VCO control voltage still drops low enough to trigger the switch control mechanism

several times because the frequency that is attempted to synthesize is on thc edge of the
synthesizer*s performance. This unnecessary tnggenng of the switch control mechanism
does not change thc band of operation because the state machine is in the highest state.
The VCO control voltage finally settles to synthesize 340MHz. The acquisition time is
approximately 19ps. This acquisition time is longer because the 1'requency change is
outside the lock range and the acquisition process becomes a pull-in process. Figure 100
shows the 340MHz output signal and its frequency spectrum.
 136

Multi —Band PLL Synthesizing a 340MHz Signal

VCO Conlrol Signals
83 82
Oi VCO Control Voltage
Unnecessary Triggering Due to
Edge of Synthesizer's Range

—288m

—488m VCO Control Voltage

—688m

12
D1, D2, (t D3
—14
BB 4.8u 6 iu 12u 16u 28u
tme(sl

Figure 99 - VCO Control Signals for the Multi-Band PLL 340MEIz Output

lvl u ti
l Band PL' S -ilhesiz(ng a 3&0MHz Signa

uCO Outpul vCO Output Frequency t, p t us

I 8

jj

—28
Biiau 19 885 ~ 19 818u 19 816u lo Bpsu 248M 298M .3488 398M 448M
time i 4) lrequ*ncy ( 4 l

Figure 100 - 340MHz Multi-Rand PLL Output Signal

 137

Case E
The fifth system level simulation presented shows the PLL synthesizing a 160MHz
signal. This illustrates a situation where a frequency that lies in the overlap between two
channels is being synthesized. Figure 101 shows the VCO control signals. All three

digital inputs are initially low which means the PLL is not in the correct band of

operation. The initial output is approximately 280MHz. The VCO control voltage rises
and triggers the switch control mechanism. The digital control signal Dl then goes high
and the VCO control voltage is grounded. The PLL is now in the correct band of
operation. The VCO control voltage then settles to synthesize 160MHz. The acquisition
time is approximately 14tts. This acquisition process is a pull-in process. Figure 102
shows the 160MHz output signal and its frequency spectrum.

Muia —Lt:tnd PLL Synthesizing 3 1oOM&z Signal

vCO Cuntrul Siunulu
Oo O
Ot uCO r. on, rol Joltoge

tr Lttv
rasrnr ~/v,
if

D1

D2& Ds
—i 4
Oe I
"u I tiu
tine ( e 1

Figure 101 - VCO Control Signals for Multi-Band PLL 160MHz Output
 138

Multi —Band PLL Synthesizing a 160M(-Iz Signal

2 8 MCO Output 18, uCO Output Frequency Spectrum

—18

—28

18

—78
19 888u 19.885u 19 818u 19 815u le 828u 188M 148I I 188M 228M
tl ne ( e ) Irequeycy ( F'z i

Figure 102 - 160MHz Multi-Band PLL Output Signal

Classic Digital PLL Design and Simulation Results

A classic digital phase-locked loop was designed for companson with thc multi-hand

phase-locked loop system. This PLL contains a single-band voltage-controlled oscillator

that is only tuned continuously. Thc PLL also does not have any switch control system
or discrete capacitors. The other PLL blocks are the same ones used in the multi-band

design.

The main difference between the performance of the two PLLs is due to the different

VCOs. Figure 103 shows the VCO used in the classic digital PLL.
 139

MC MC

Figure 103 - Classic Digital PLL VCO

This VCO is the same one used in the multi-band PLL except the discrete capacitors and
switch transistors have been removed. The same transistor aspect ratios and capacitor
sizes have been used. This VCO has a tuning range of 229. 8-385 MHz. Figure 104
shows the VCO transfer curve.

VCO Ttenefef Ctttee

600

300—

360

300

20-

300

200

260—

2'IO-

220

200
-0 3 0 06
VCO Control Voltage (V)

Figure 104 - Classic Digital PLL VCO Transfer Curve

 140

This VCO has a higher maximum frequency due to less parasitic capacitance associated
with the routing of the discrete capacitors. It has a conversion gain of —97MHz/V. This
is higher than any of the switched-tuned VCO channel's conversion gains. The
simulated phase noise performance of this VCO ranges from —83.74 to —93.6dBc/Hz at a
50kHz offset. Referring to Table 13, this is comparable to the switched tuning VCO's
band 4 simulated phase noise performance of —82.63 to —96.67dBc/Hz at a 50kHz offset,

Band 4 of the switched tuning VCO has a conversion gain of —94.75MHz/V. The other
switched tuning oscillator frequency bands have lower conversion gains. This results in
better simulated phase noise performance than the classic digital PLL VCO.

The performance of the classic digital PLL is illustrated through 3 case studies. These
case studies include synthesizing the edge of range frequencies and a mid-range
frequency. Table 17 shows the setup for each case.

Table 17 - Classic Digital PLL Frequency Synthesizer Case Studies

Initial Final Simulation Acquisition

Case
Fre uenc Fre uency TYpe Time
Near Maxi mum
A 350MHz 380MHz 30MHz 1 Otis
Frc ucnc
Near Minimum
B 350MHz 230MHz -120MHz 14tts
Fre uency
350MHz 260MHz -90MHz Mid-Band 51s

Case A
The classic digital PLL was simulated to synthesize a 380MHz signal. This is close to
the maximum frequency that the classic digital PLL can synthesize. Figure 105 shows
the VCO control voltage as the Pl I acquires lock. Initially the PLL is outputting a
350MHz signal. The loop dynamics take over and the VCO control voltage drops to
synthcsizc thc 380MHz signal. The acquisition time is approximately 10tts. The reason
for the length of the acquisition time is that the PLL is operatmg m a region where the
 14i

VCO gain has decreased due to non-linearity in the gain. Figure 106 shows the 380MHz

output and frequency spectrum.

PLL Synthesizing a 380MHz Signal

188m VCO Control Voltage

—188m

—288m

—388m

688m
48u 6 8u 12u 6u 28u
time ( e )

Figure 105 - VCO Control Voltage for Classic Digital PLL 380MHz Output
 142

PLL Synthesizing a 380MHz Signal

VCO Output vCO Output Frequency Spectrum

—414
u

—29 —98
19 888 19.885u 19 919~ 19 915. 19 929u 289M 33811 388M 439M 489M
5m*( ) 1 qucn y ( Hz )

Figure 106 - 380MHz Classic Digital PLL Output Signal

Case B
Thc classic digital PLL was simulated to synthesize a 230MFlz signal. This is close to
the minimum frequency that the classic digital PLL can synthesize. Figure 107 shows
the VCO control voltage as the PLL acquires lock. Initially thc PLL is outputting a
350MHz signal. The loop dynamics take over and the VCO control voltage rises to
synthesize the 230MHz signal. The acquisition time is approximately 14)ts. The length
of the acquisition time is due to the frequency change being outside of the lock range.
Thc acquisition process is a pull-m process. Figure 108 shows the 230MHz output and
frequency spectrum.
 143

PLL Synthesizing a 230MHz Signal

vCO Control voltage

1. 18

988m

788m

588m

188m

—188m
8 48u 6 Bu 12u 16 ~ Bu
tme(e)

Figure 107 - VCO Control Voltage for Classic Digital PLL 230MHz Output

238MHz Signa
vCO D !oi I tCO Output Frequency Bpectn. m

( —'8

—28
19 888 ~ e 88 u 19 818u 19.815u 19 828u (1M 238M '
8814
1 m* frequency ( qr )

Figure 100 - 230MHz Classic Digital PLL Output Signal

Case C
The classic digital PLL was simulated to synthesize a 260MHz signal. This is a mid-
range frequency. Figure 109 shows the VCO control voltage as the PLL acquires lock.
Initially the PLL is outputting a 350MHz signal. The loop dynamics take over and the
VCO control voltage rises to synthesize the 260MHz signal. The acquisition time is

approximately Sits. The acquisition time is short due to the frequency change being
inside the lock range. Figure 110 shows the 260MHz output and frequency spectrum.

PLL Synthesizing e 268MHz Signa

V GG oat ot Voltage

, tltlllItIII)lyt tt
488m

388m

288m

188tu

—188m
8. 2 Bu 48u 6 Bu 88u lnu
ttme (

Figure 109 - VCO Control Voltage for Classic Digital PLL 260MHz Output
 145

PLL Synthesizing a 260MHz Signal

vCO Output VCO Output Frequency Spectrum

—18.8
1.8 —28.8

—38.8

—188
19.888u 19.825 '3. 8 Bu 19 Bleu 19 828u 168M 218M 268M 318M 368M
ti:ne(ej 'requency ( Hz )

Figure 110 - 260MHz Classic Digital PLL Output Signal

Table lg provides a comparison between the multi-band PLL and the classic digital
PLL. The multi-band PLL achicvcd a 60% wider tuning range than the classic digital
PLL. The multi-band PLL was able to achieve a wider tuning range while maintaining a

lower VCO conversion gam. This allowed the switched tuning oscillator to have better
phase noise performance than the oscillator that was used in the classic digital PLL. The
phase noise of the PLL systems was unable to be simulated due to the high transistor

count. This comparison is made through experimental results. The acquisition time

depends on the region that the PLL operates in and is a strong function of the VCO
conversion gain. Case A of thc multi-band PLL and the classic PLL can be used to
compare the acquisition time for a frequency step of 30MHz. The multi-band PLL has
an acquisition time of Sits and the classic digital PLL has an acquisition time of 10(is.

However, the reason for the classic digital PLL to have a slow acquisition is because it is

operating near the edge of the synthesizer's range in a region where thc VCO gam is
low. Case E of the multi-band PLL and case B of the classic digital PLL can be used to
compare the acquisition time for a frequency step of —120MHz. Both synthesizers have

an acquisition time of 14ps. This is a pull-in process for both synthesizers, with the
multi-band PLL switching down one band. Case B of the multi-band PLL and case C of
the classic digital PLL can be used to compare the acquisition time for a frequency step
of —90MHz. The multi-band PLL has an acquisition time of 14lts and the classic digital
PLL has an acquisition time of 5Its. This is a pull-in process for the multi-band PLL and
the PLL switches bands. The acquisition time is much lower for the classic digital PLL
because the frequency step is within the lock range due to the large VCO conversion
gain of the PLL.

Table 18 - Comparison of Multi-Band PLL and Classic Digital PLL Systems

PLL Frequency VCO Phase Noise PLI System Acquisition

System Ran e (MHz) (dBc/Hz @ 50kHz) Phase Noise Time (Its)
Multi-Band 100 ~ 340 -82.63 ~ -103 7 Determined
Ex erimcntall
5 ~19
Classic 230 ~ 380 -83.74 ~ -93.6 Determmed
5 ~14
Experimentally
 147

EXPERIMENTALRESULTS
In this section the experimental results for the multi-band PLL building blocks, the
multi-band PLL frequency synthesizer system, and the classic digital PLL frequency
synthesizer are presented. These results are compared with mathematical and Specue

simulation results where applicable. A comparison is made between the multi-band and

the classic digital PLL frequency synthesizer.

Building Block Verification

The prototype chip shown in Figure ill contains the following multi-band PLL
frequency synthesizer building blocks:
l. Phase/Frequency Detector
Z. Charge Pump

3. Switched Tuning VCO

4. Switch Control State Machine
5. Comparators with Hysterisis
6. Loop Divider

S ilcned Loop Outp t

Tu g VCO Dmder Butlers

DC Blockmg
DC Blocktng
Cepaotor
Capaulors
Output
Buger
Ilgwu

Pos t e NMOS
Swttch Control Comparaior
State Machine

Negati e PhtOS
Comparator

Charge Output
Pump Butlers

$j L

Phase/Frequency
Detector

Figure 111 - Multi-Sand PI.L Building Blocks Prototype Chip

 148

The characterization of these blocks outside the PLL systems provides information that
is used to solve any problems encountered in the systems.

Phase/Fre uenc Detector

The functionality of the phase/frequency detector was verified on a high frequency test
board shown in Figure 112. BNC Connectors are used on the test board for high

frequency input and output signals. The test board is double-sided with a large ground

plane on both sides for optimal high frequency performance. Low frequency and power

signals are brought on to the hoard through headers. All of the multi-band PLL building
blocks can be tested on the test board. Potentiometers and resistors are used to generate
bias currents and reference voltage for other building blocks.

High Speed Output

Buffers with Integrated
50' Termination
Resistors
Headers for Low
Frequency and
Power Signals
~ BNC Connectors
for High Frequency
I/O Signals

Multi-Band Pl L
Building Blocks Chip
Potenaometers
and Resistor
Large Double-Sided Used for Biasmg
Ground Plane for
Optimal High Frequency
Performance

Figure 112 - Multi-Band PLL Building Blocks Test Board

A schematic diagram of thc PFD is shown in Figure 61. A ~I.3SV 9.375MHz square
wave signal is applied to the v, „r input. A +L3SV 6.26MHz square wave signal is

applied to the vf, input. The bul'fered outputs of the PFD are loaded with approximately

10pF from the HP1661CS Logic Analyzer/Oscilloscope used to measure the signals and

also pin and board capacitance associated with driving the output signals outside of the
chip.
 149

The experimental results for the phase/frequency detector are shown in Figure 113.
These experimental results reproduce the PFD simulation results presented in the

previous section in Figure 65. A HP1661CS Logic Analyzer/Oscilloscope is used to

obtain the results. After initial settling, a rising edge on the v / signal causes the

DOWN signal to go high. The DOWN signal stays high until a rising edge of v»

causes UP to go high. UP and DOWN are now both high for a short period. This
causes the AND gate reset ouqout to go high and forces UP and DOWN low. This

cycle is repeated with another rising edge of vav . The overall effect of this is that with a

significantly faster signal v, u, the DOWN signal is high for a significant period of time.

When the PFD is placed in the PLL system, these conditions will force the charge pump
to discharge the loop filter and the VCO control voltage will drop. This will increase the
VCO output'6 frequency and in turn the v» signal's frequency.

Anal ltzer Wavef arm NACHZNE I Acq Control Cancel Run

Accumulate Current Sampte period = zt000 ns

Off Next. Sample Period 4 000 ns

sec/Dtv Delag tlarkers Acqutsttton Time

50 ns 0 s Off tu Mag 1999 15 52 39
DOWN

UP Reset
VFB
6.25MHz
VREF
9.375MHz

/
vie Rising Edge
Edge
v, a Rising
Causing Reset

Figure 113 - Phase/Frequency Detector Experimental Results

 150

C~hhh
For a schematic diagram of this circuit refer to Figure 66 of the previous section. The
functionality of the charge pump was verified. The verification was performed by
loading the charge pump with a 10.8nF capacitor and studying the charge time to

calculate the average output current. The UP and DOWN control signals are
complementary+1. 35V 200Hz square waves. The charge pump positively charges the
load capacitor with 1«when UP is high and negatively charges the load capacitor with

I„«„when DOWN is high.

The experimental results for the charge pump are shown in Figure 114 and Figure l 1 S.
The average output current is measured from the voltage slope over a h0. 8125V region
with the following relation.

V
Averagelccr = CA
Ar
(148)
The off-chip bias currents are tweaked to yield average I«and I„c~~ output currents of

25ttA. A bias current of 30.411A is needed for lc, and 26.3ttA is needed for l„c~v.

j, 500 2 500 r 6108 500 sp $2 RUN

Avol age lop

(10:BnF)(1.625V)—:=
702tts
25~
I &
+

t 1 = ZOO . Ous tZ = 902. Ous at = 702. Ous n/at = 1 . 425kHz

Figure 114 - Measured Average I, , Output Current

 151

f 500 500„ C--tOOOIs 500s&

1
taiueragi IDQWN

(1Q'~j~ M-1~
7'00]ts
1:
I I I 1
I I I I

t1 = -2. 270ms t2 = —1.570ms Ot = 700.0us 1/rit = 1.429kHz

Figure 115 - Measured Average Iao„,„Output Current

Switched Tunin VCO

The performance of the switched tuning VCO was determined expenmenially on the

high frequency printed circuit board shown in Figurc 112. A schematic of the switched

tuning VCO is shown in Figure 72. MAXIM's MAX4201 high frequency output buffcrs
are used in order to measure the output with a 5012 input impedance Rohde k, Schwartz
FSEB30 Spectrum Analyzer. 50fl termination resistors are integrated in the buffer chips

to provide matching with the spectrum analyzer. These buffers have an input impedance
of approximately 500kf2 in parallel with a 2pF capacilor. The VCO is not designed to
drive a 5011 load because the design is intended for a fully integrated multi-standard

transceiver. The VCO would be driving a integrated high input impedance mixer in this
application and 50f2 matching is not necessary. The VCO output signal on chip

approximates a square wave as shov'n in the previous sections' simulation results. This
is optimal for switching a mixer in a transceiver system[22]. However, the signal

appears to be a sinusoid when driven outside the chip because of the liltenng associated
with the bond pad, pin, and board capacitance.
 152

In testing the switched tunable VCO, the continuous control voltage, v„was swept from
—0.8V to 0.8V. Digital control signals of e-1.35V were applied to the discrete control

De
signals Dl —D3. The minimum VCO output frequency is 111MHz. The VCO

oscillates at 111MHz when the continuous control voltage, v, , is at 0.8V and the three

digital control signals, Dl —D3 are all high. The output signal measured with the

HP1661CS Logic Analyzer/Oscilloscope is shown in Figure 116. The output frequency

spectrum obtained with the Rohde & Schwartz FSEB30 Spectrum Analyzer is shown in

Figure 117. The output signal phase noise is —84.33dBc/Hz at a 50kHz offset.

Scope Scope Au to lleesure Autoscol e Cancel Pun

Per tod 9. 01 ns Freq 110 96 tluz 163

O
Vp mV
Input 1. 47 4. 90 ns
p
3.54
Dl
Ptsettme ns +Wtdth Presho ~ i
Felltime 2. 13 ns -Width &. 12 ns Overshoot 0 %%d

1 e9 Dtsple9 S*mple Dote ecquired et: 1 ns

0 s Opttons Pertod Nest ecquzsition: 1 ns

Figure 116 - Minimum Frequency VCO Output

 I- I I ~ '

, 5$55555555
gggaaaaaaa
RRRNili TRRR
RREREJ'I' SEE
, 5555$l
5555FJ'I RHRHH
NI 88
R~.
5555~$5555
ymiaa RRLa, ,
,

ERROR
 154

Scope Scape Auto rleasure 4utoscale Cancel Run

Period 3. 37 ns Freq 297. 16 ttHB Vp p 137 mV

O
Input
Cl
Risetime 980 ps +Width 1.68 ns Preshoa 1 0
Falltime 990 s -Width 1.69 ns Overshoot 1. 15 S
6+1 rf Del ay Display Sample Data acquired att ns 1

2. 00 ns 0 s Options Perlad Next acquisltiant I ns

Cl

Figure 118 - Maximum Frequency VCO Output

0 I ta I IT I NQI I RBH I RHz RF Att 90 dB

kaf L I -71 Brt dec Hz trett 50 Hz
dB 50. 0 ~ 000000 kHz 511T 7. 6 a Ltnrt dern

-10

-20

70 -26. 111 d

I 'r I EH 15A

50

r10

Fza
100
C nt r 297. 1525 tIHz 15 LHz Spar I' 0 I-Hz

Ba t 22 MAY. BJ Br57r26

Figure 119 - Maximum Frequency VCO Output Frequency Spectrum

 155

The switched tuning VCO's frequency response over the different bands of operation is
given in Table 19. The transfer curves of the switched tuning VCO are shown in Figure

120. Note the high phase noise values for the switched tuning VCO. These high phase

noise values occur when the VCO is synthesizing a mid-band frequency where the

conversion gain, K«~, is highest. The high mid-band conversion gain degrades the

phase noise performance. Figure 121 shows a mid-band frequency of 208MHz. The
VCO oscillates at 208MHz when the continuous VCO control, v, , is at —0.2V, the

digital control signal Dl is high, and D2 —D3 are low. The output frequency spectrum
obtained with the spectrum analyzer is shown in Figure 122. The output signal phase
noise is —60.3dBc/Hz at a 50kHz offset.

Table 19 - Experimental Switched Tuning VCO Performance

Band Descrtption Frequency Range (MHz)

Phase Noise 0
50kHz
Offset (dBc/Hz)
Att Switches Closed 111 —149 -69.2 ~~ -86.91
2 Switches Closed 129 —181 -64.05 ~ -81.99
1 Switch Closed 155 —228 -60. 3 ~ -77.87
Al I S wi tches 0
en 193 —297 -65. 52 ~ -78.09
 experimental Switched Tunhrg vCo Trmefer corree
3RI r

300 I- 0~-rr
Band 4 +~
250 t

+
Banrte ~.
200—

De
X-~
Band 2 +-
l50
Band 1 +. 'r

+
100'

50
-0 5 0 05
VCC Cooeol Voltage (Vi

Figure 120 - Experimental Switched Tuning VCO Transfer Curves

Sr. ~ pe Scope Auto Neosure 4utoscole Cancel Run

Pertod 4. 01 ns Freq 207, BI HHS yp p 177 mV

O
Input
Cl
Rlsetime 1. 44 ns +Width 2. 54 ns Preshoat 0. 90
Folltime 1. T6 ns —Width 2. 27 ns Oversh ~ ot 0. 90
l V 1 eq 0tspteq Semple Dote ocqutred ot' 1 ns
2 00 ns 0 s ljptt ~ ns Period Next scquleltlan 1 ns

Figure 121 - Mid-Band Frequency VCO Output

 ~ I ~ ~
' I
III I

5555EIRRERE.
~ ~ ~ ~

~ESESISEISE
ggggglRRggg
~
, NE, . : illi
,
, PiLIE(%E EE
Illlklkt
'
EIHRI"i' "'
„,
RRR
~15
555IRR
55
'RR

55mm55 55
 158

~
non-overlapping square waves generated from a single s-2. 5V 10kHz square wave with
the following circuit shown in Figure 123.

10kHz ttk
10kHz 0 UP

10kHz 0tkz

DOWN

Figure 123 - Non-Overlapping Clock Circuit

The TTL outputs are scaled down to approximately s-L3SV square wave signals with
voltage dividers. The 10kHz inputs allow all of the states of the state machine to be
observed with a 100kHz clock input.

The experimental results for the swttch control state machine arc shown in Figure 124.
The results were obtained with the HP!661CS Logic Analyzer/Osci!loscope. The state
machine is initially in state A when the Dl-D3 outputs are high. The UP input then
goes high and the state machine cycles from state A to state D after the circuit is
clocked thrcc times. UP then goes!ow and DOWN becomes high. The state machine
cycles from state D to state A after the circuit is clocked three times.
 159

Anelgzer Weveform ttACHINE I Acq. control cancel Run

Accumulete Current Sample Period = 1 000 us

Off Next Sample Period = 1. 000 us
sec/Dtv Detag rierkers Acquisition Time
10.0 us 0 s Off 07 Meu 1999 13:35 07

State A State A

D2
State B State B
Dl
State C Slate D State C
DOWN

UP

CLK

Figure 124 - Switch Control State Machine Experimental Results

Com arators with H sterisis

Refer to Figure 83 and Figure 84 for the schematics of the comparators. An 800mV

reference signal was placed at thc negative input terminal ot the positive NMOS
comparator and a —800mV reference signal was placed at the positive input terminal of
the negative PMOS comparator. A rail-to-rail 2, 7Vpp 1kHz triangle wave input signal,

v„, , was applied to the positive terminal of thc positive NMOS comparator and the

negative terminal of the negative PMOS comparator.

The NMOS comparator experimental transfer characteristic is shown in Figure 12S.

This transfer characteristic was obtained with the XY function of the oscilloscope and is

a plot of v„„, versus v, „. The output is low when the input signal is below the 800mV

reference signal. The output is high when the input signal is above the 800mV reference
 160

signal. Two trip points are observed due to the hysterisis. The rising input signal must
pass the 800mV reference signal to approximately 990mV before the output goes high.
The falling input signal must fall below 800mV to approximately 635mU before the
output signal goes high. This amount of hysterisis satisfies the required minimum of
100mV due to the VCO control voltage ripple. The output levels are ~1.35V as
expected due to the clamping in the comparator.

Positive NMOS Comparator with Hysterisis Measurement Results

REF 0.8V

t, %600v 2 %600v RUN

I.

V-CRF 980mV:
-—

+ t ++V+ 9 I4 t+-I —I-+ 1 I+ H +I + 9+ v + + i++ t-++ v+ q++ t-++a.+ q — i

I I"

VrRF-=E35mV I,

V I C 1 ) = 636 . 0mv V2C I) = 990.0mV DVC 1) = 366. 0mv

Figure 125 - Positive NMOS Comparator with Hysterisis Measurement Results

Thc PMOS comparator expenmental transfer characteristic is shown in Figure 126. This
transfer characteristic was obtained with the XY function of the oscilloscope and is a

plot of v„„, versus v, „. The output is high when thc input signal is below the -800mV

relerence signal. The output is low when the input signal is above the -800mV reference
signal. Two trip points are observed clue to the hysterisis. The falling input signal must
pass Ihe -800mV reference signal Io approximately —1.02V before the output goes high.
 161

The rising input signal must rise above the -800mV to approximately -470mV before the
output signal goes low. This amount of hysterisis satisfies the required minimum of
100mV due to the VCO control voltage ripple. The output levels are st. 35V as

expected due to the clamping in the comparator.

Negative PMOS Comparator with Hysterisis Measurement Results

REs
= -0 SV

f 1'd&OOv 2 tdSOOv XY RUN

i;. . . . . . . . :I
—
--1.02V
VrRR
. (.

—I+++-I—I-+ d —I-+ d+ ——I-+

I
+-+ 11-I-+ d++ d+ I—I-+ d I + d+ I
—I-+ d++ —++-I-+ —
d t I

=-470m V

X 1(1) = —1.020 V X'2( 1) = —470. 0mv (dk(1) = SSO. Omv

Figure 126 - Negative PMOS Comparator with Hysterisis Measurement Results

~LDi id

The performance of the loop divider was determined experimentally on a high frequency

printed circuit board shown earlier in Figure 112. A 2.7V~& sine wave was applied to the

input of the loop divider. The actual shape of ihe input signal in the PLL systems would
be a square wave. However, due to the unavailability of a high frequency square wave
generator, a sine wave is used. This difference in the mput signal shape has little effect
on the loop divider performance. Thc mput signal frequency was swept to dctcrminc the
loop divider frequency range.
 162

The loop divider has a measured frequency range of 110-510MHz. Figure 127 shows
the loop tUvider operating at 510MHz. The bottom signal is the 510MHz input signal.

The 1Gsample/3 HP1661CS Logic Analyzer/Oscilloscope has problems displaying this

signal. The top signal is the divide-by-32 15.9375MHz output signal.

Scope Scope 4uto Measure 4utoscale Cancel Run

Input Period 62. 74 ns Freq 15.939 MHz Vp p 519 mV

CI
Risetime 1. 71 ns +Width 31.55 ns Preshoot 9.03
Falltime 1.44 ns —Width 31. 19 ns Overshoot 6. 25
5 iv De 1 aq Oisplas Sample Data acquired at: 1 ns
20. 0 ns 0 s options period Next acquisition: I ns
Cl

Inpul
32
15 9375MHz

C2

510MHz
Input
(Osmlloscope
Sampling
Problems)

Figure 127 - Loop Divider Operating at 510MHz

Figure 128 shows the loop divider operating at l 10MHz. The bottom signal is the
1 10MHz signal. The top signal is the divider-by-32 3.4375MHz output signal.
DeO Scope
Input

3
CI

100 ns
CI
iv
Scope
Period
Risetime
Fetltime
1 ag
0
4u

s
to Measure
290. 91ns
1.63 ns
1.57 ns
Otsptag
Options
Freq
4Width
-Width
4utoscale
3, 4375
145, 50 ns
145. 41 ns
Sample
Period
MHz
cence1

Data acquired
Next
Vp p
Preshoo l
Overshoot

acquisition
at:
Run

516 mal
4. 64 e
4. 64
1

I
163

ns
ns

Input
32

3.4375MHz

C2

iiOMHz
Inpul

Figure 128 - Loop Divider Operating at 110MHz

The loop divider fails for frequencies under 110MHz. The second flip-flop in the
divider fails to divide by two at low frequencies and the loop divider only divides by 16.
The inability of the flip-flop to operate at frequencies below 110MHz will cause the PLL
systems to fail when attempting to synthesize frequencies below 110MHz. This is
because when the VCO output frequency drops below 110MHz the loop will now
multiply the input frequency by 16 instead of 32. The VCO will not he able to

synthesize this low frequency and the loop will not lock. An example of this constraint
is attempting to synthcsizc 100MHz. The input frequency will be 3. 125MHz. The loop
will attempt to synthesize 100MHz until the VCO output frequency drops below
110MHz. Then the division factor will bc 16 and the loop will attempl to synthesize
50MHz. However, the limited VCO frequency range will not allow it lo lock on a
50MHz signal.
 164

Multi-Band PLL Frequency Synthesizer

The prototype chip shown in Figure 129 contains the multi-band PLL frequency
synthesizer.

Switched Loop Output DC Blocking

Tuning VCO Divider Buffers Capacitors

Switch Control Charge Phase/Frequency Loop

Circuitry Pump Detector Filter

Figure 129 - Multi-Band PLL Frequency Synthesizer Prototype Chip

Thc multi-band PLL frequency synthesizer was characterized to determine the frequency
range and phase noise performance on a high frequency test board shown in Figure 130.
 165

High Speed Output

Large Doubts-Sided Buders whh integrated
Ground Plane lor 50ss Teniiinatlon
Opimal High Frequency Resistors
Performance BNC Connectors
for High Frequency
I/O Signals

Potenliometers
and Resistor
Used for Biasing

Multi-Band PLL
Frequency
Synthesizer Chip Headers for Low
Frequency and
Power Signals

Figure 130 - Multi-Band PLL Frequency Synthesizer Test Board

The test cases presented in the previous section are reproduced experimentally to
illustrate the multi-band PLL frequency synthesizer performance. Table 20 summaiizes
the setup for each case. The frequencies have been adjusted from the previous section to

comply with the measured multi-band PLL regions.

Table 20 - Multi-Sand PI.L Frequency Synthesizer Experimental Case Studies

Initial Experiment Acquisition

Case Final Frequency
Fre uency T e Time
A 240MHz 270MHz 30MHz Mid-Band 4.5 its
Mid-Band
B 240MHz 190MHz -50MHz 8.56tts
(Band Change)
-129MHz Lowest Edge-
240MHz 111MHz 17.024tts
of-Band
Highest Edge-
D 240MHz 290MHz 50MI-Iz 16.036ps
of-Band
240MHz 160MHz -80MHz Overla 8.024ps

In all cases the multi-band PLL is initially operating in the mid-band region of band 4 at
a frequency of 240MHz. The initial output signal measured with an oscilloscope is

shown in Figure 131. The mitial output frequency spectrum is shown in Figure 132.

The initial output signal phase noise is —90.83dBc/Hz at a 50kHz offset.

 166

Scope Scape Auto rieosure Autascale cancel Run

Period 4. 17 ns Freq 239. 9I liHz 169

O
Vp mV
Input p
Cl
Risettme 1, 22 ns +Width 2. 18 ns Preshoat 0
Folltime 1.22 ns -Width 1.99 ns Overshoot 0 5
Del 69 » BPlou Sample Dots ocquired ot: I ns
2. 00 ns 0 s Optlone Per(ad Next acquisition: I ns
Cl

Figure 131 - Initial Fxperimental 240MHz Multi-Sand PLL Output Signal

De( te I (Tl No(3 RBN I kHz RF ntt 30 ds

Ref 6 I -90. 83 dBD Hz vsll 50 Hz
0 86m 50. (3(3 ~ 00 ~ 130 kHz 51(T 7 6 8 UnYt dBm
0

XD —I 1. 6 680

-20

-30
IV(Ekl 15m

-60

-90
Fx
10
Center 240 li¹ 35 kHz pe 150 I Hz

D te: 27 Ilnf 99 7 I:0'3: 18

I'igure 132 - Initial Experimental 240MHz Multi-Band PLL Output Frequency

Spectrum
 167

Case A
The first experimental result presented shows the multi-band PLL synthesizing a
270MHz signal. This illustrates a situation where a mid-band frequency in the current
band is being synthesized. Figure 133 shows the continuous VCO control voltage. All
three digital VCO control signals are initially low which means the multi-band PLL is in
the correct band of operation. The PLL was previously locked on a 240MHz signal.
This corresponds to a VCO control voltage of approximately 35mV in band 4. The
VCO control voltage then tunes down to approximately —.143V to synthesize 270MHz.
The measured acquisition time is 4. 5lts. This acquisition time is low because the

frequency change is within the lock range. The output signal measured with the

oscilloscope is shown in Figure 134. The output frequency spectrum obtained with the
spectrum analyzer is shown in Figure 135. The output signal phase noise is
96.14dBc/Hz at a 50kHz offset.

Scope Scope bannel 4utoscole Cancel Run

Input Y/Die Offset Probe Coupling Preset

CI 1'1 1M' / DC User

Delay ] Display
s Tx = -1xr0. 00 ns
1 00 us 3.8200 usl Options 4. 5e00 us
Cl
X 6. 25rnv
0 -150rnY '. Band 4 Operation

Figure 133 - Continuous VCO Control Voltage for Multi-Band PLL 270MHz
Output
 168

Scope Scape Auto lieasure Autoscale Cancel Run

Period 3. 70 ns Freq 269. 941 ttHz Vp p 142

O
mV
Input
Risetime 1.09 ns +Width 1.88 ns Preshoo 1 0
Cl Falltime 1. 09 ns -Width 1.82 ns Overshoot I. II x
Oel etj Displad Sample Oats acquired at 1 ns
2. 00 ns 0 s Options Periad Next acquisition: 1 ns
Cl

Figure 134 - Experimental 270MHz Multi-Sand PLL Output Signal

Bel ta i ITI Nol I RBII I kHz RF Att 30 dB

Ref 6 -96 14 dB Hz XBU 50 Hz
0 88m 50. CI ~ 0 00CI kHz 5kIT 7. 6 a Un&t dBm
0

-I ~
XD —I 813'3 d

-20

IVIEH 15A

-50

-60

-90
FX
—ICI0
Center 270 IIHz 15 kHz Bpa 150 kHz
Date. 28 MAY 99 0:24 'I

Figure 135 - Experimental 270MHz Multi-Band PLL Output Frequency Spectrum

 169

Case B
The second experimental result presented shows the multi-band PLL synthesizing a
190MHz signal. This is a situation where a mid-band frequency out of the current band
is being synthesized. Figure 136 shows the continuous VCO control voltage. All three

digital control signals are initially low which means the multi-band PLL is not in the
correct band of operation. The multi-band PLL was previously locked on a 240MHz
signal. This corresponds to a VCO control voltage of approximately 35mV in band 4.
The VCO control voltage then tunes up and switches to band 3 where it settles to —92mV
to synthesize 190MHz. The measured acquisition time is 8.56lts. This acquisition time
is longer because the frequency change is outside the lock range and the acquisition
process becomes a pull-in process. The output signal measured with the oscilloscope is
shown in Figure 137. The output frequency spectrum obtained with the spectrum

analyzer is shown in Figurc 138. The output signal phase noise is —92.76dBc/Hz at a
60kHz offset.

Scope

Inp

2. 00
CI
~ t

us
~II
De

4. 6000
Scope Channel
D

1 ag
~

us
O
O
Offset

Die ~ lag
O p'I
n n s
i
0 V
4utoscafe
Probe
1 1
Cancel

Coupling
fno / DC
Bun

Preset
user
T4 = —1.7400 us
To = 6. 8200 us
1
X 46. 9nfd Band 4 Operation Switch to Band:3
0 —85. 9rnv

Figure 136 - Continuous VCO Control Voltage for Multi-Sand PLL 190MHz
Output
DeO Scope
Input

5+1v
Cl

2. 00 ns
Cl
Scope
Period
Risetime
Falltime
1 a9
0
Au to rleosure

s
5. 25
1, 50
1.219
OIBPla9
Options
ns
ns
ns
Freq
+Width
-Width
Autosca1 e

Sample
Period
190, 54 ttHz
2. 95 ns
2. 50
Next
ns
Data acquired
Cancel
tip p
Preshoot
Overshoot

acquisition:
at:
Run

206
0
0
1

1
ns
ns
170

m'll

Figure 137 - Experimental 190MHz Multi-Band PLL Output Signal

Del ta I IT I NOI I RBN I RHz. RF Att 30 dB

Ref C I -92. 76 her H VBU 50 Hz
0 dem 511.00 ~ 00000 kHz 5RT 75 a 0 ~ It dBm

—10

-20

I VIEN 15A

-50

-ee

Fz
IL30
Center 19 ' IIHz 15 kHz, 5pan 150 kHz
0-1 27 MAY, 99 21: 15:09

Figure 138 - Experimental 190MHz Multi-Band PLL Output Frequency Spectrum

 171

Case C
The third experimental result presented shows the multi-band PLL synthesizing a
111MHz signal. This illustrates a situation in which a signal close to the lowest edge-of-
band frequency is being synthesized. Figure 139 shows the continuous VCO control
voltage. All three digital control signals are initially low which means the muln-band
PLL is not in the correct band of operation. The multi-band PLL was previously locked
on a 240MHz signal. This corresponds to a VCO control voltage of approximately
35mV in band 4. The VCO control voltage then tunes up and switches from band 4
through band 3 and 2 and finally settles in band 1 at approximately 0.295V to synthesize
111MHz. The measured acquisition time is 17.024tts. This acquisition time is longer
because the frequency change is outside the lock range and the acquisition process
becomes a pull-in process. The output signal measured with the oscilloscope is shown in
Figure 140. The output frequency spectrum obtained with the spectrum analyzer is
shown in Figure 141. The output signal phase noise is —87.68dBc/Hz at a 50kHz offset.

Scope Scope hannel Autoscale Cancel Run

Input V/Die Offset Probe Coupling Preset

CI 500 mV 0 V I I Itttt / DC User
s+i v De 1 ay Display Tx = -1.4B40 us
3 00 us 10.330 tis Dp'I'Lone To = 15.540 us
CI
117mV ' Band 4,
0 2 I tmV

Switch, lto Band 3, 2, I

Figure 139 - Continuous VCO Control Voltage for Multi-Band PLL 111MHz
Output
 172

Scope Scope Auto lleasure Autoscole Cancel Run

Period 9. 00 ns Freq 11. 15 lluz Vp p 227 mV

O
Input 1

Ct
Rlsetime 1.49 ns +Width 5. 07 ns Preshoot 0. 73 X
Falltime 1, 79 ns -Width 3.92 ns Overshoot 5.88 x
Del a9 BPle9 Sample » Data acquired at: 1 ns
2. 00 ns 0 s Options Period Hext acquisltiorl: ns 1

Figure 140 - Experimental 111MHz Multi-Band PLL Output Signal

Del ta I ITI NDI I RBLI I 1 Hz RF Att 30 hB

Ref 5 I -87. 88 dBD I-Iz vBU 50 Hz
0 dBm 50. 001300000 kkz 9k'T 7 6 m Unit dBm
0

-10 XD . 51do

-20

-30
iVIRH ]9A

-50

-90

—100
0 ~t T 111 nHz 15 I Hz Bpan 150 I. H
Da te 27 TIAV. 99 1~ :23.24

Figure 141 - Fxperimental 111MHz Multi-Sand PLL Output Frequency Spectrum

 ~ ~ ' I ~ ~ ~

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I ~

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5555555
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55 55555
5555555
 174

240MHz signal. This corresponds to a VCO control voltage of approximately 35mV in

band 4. The VCO control voltage then tunes down and unnecessarily triggers the switch
control mechanism due to operating at the edge of the synthesizer's range. The control
voltage finally settles to -.459V to synthesize 290MHz. The measured acquisition time
is 16.036ps. This acquisition time is longer because the frequency change is outside the
lock range and the acquisition process becomes a pull-in process. The output signal
measured with the oscilloscope is shown in Figure 144. The output frequency spectrum
obtained with the spectrum analyzer is shown in Figure 145. The output signal phase
noise is —89.97dBc/Hz at a 50kHz offset.

Scape

Inp ~;

Z. 50 us
CI
CI
D
QO
Scope Channel
V/D i v
500
De
10.040
lag
mV

us
Offset
0
Dtsptag
Opttnns
V
4utascale
Probe
1'1
Cancel

Coupling
1M' I DC I~

4
O Preset
user
64. 000 ns
16. '100 us
X 62. 5mV Band 4i'operation
0 -375rnV t
Unnecessary Tiiggering true to
1
Edge of Synthesizer's Range

t
1

Figure 143 - Continuous VCO Control Voltage for Multi-Band PLL 290MHz
Output
 175

Scope Scope Aut. o lleaeure Autoscale Cancel Run

Input Period 3. 45 ns Freq 290, 0I linz Vp p 137 mV

Cl
Risetime 1.00 ns +Width 1, 74 ns Preshool 1. 15
Falltime 1, 00 ns -Width 1.71 ns Overshoot 0 5
De 1 ap Displau sample Data acquired at: 1 ns
2. 00 ns 0 s Opttons Pertod MB7Kt acquisttion: 1 ns
Cl

Figure 144 - Experimental 290MHz Multi-Band PI.L Output Signal

Delta 1 lTl Nol 1 RBlt 1 kHz RF At t 30 dB

Ref 0 I -l39. 97 dec Hz KBtt 50 Hz
0 dBm 5 ' . 00000000 KKHz 5RT 7 6 m Unit dBm
0

XD —1 2. 2 dBm

-20

-30
1 KK 1 EP 15A

-90
FK
100
Center 290 MHz 15 k4 Bpen 150 kHz
Date: 2B MAY. 99 0:33

Figure 145 - Experimental 290MHz Multi-Sand PLL Output Frequency Spectrum

 176

The multi-band PLL cannot lock on frequencies much higher than 290MHz. Figure 146
shows the multi-band PLL output frequency spectrum when it is synthesizing a 291MHz
signal. Notice the high energy content at equal offsets of the fundamental. This is from
the multi-band PLL being on the edge of its frequency range.

Delta I ITI NDI ) Raki I hHz RF Att 30 da

Ref Lvt -75. 26 dBc Hz YBIJ 50 Hz
0 dBm 50. 00000000 kHz SIIT 7. 6 m Unit dBm

XD . 33 &IB

-30
1V I Ekf 15A

-50

-60

FX
100
Center 291 HHz 15 kHz Spe 150 kHz
Da ie 28 HAY. 99 8:36:19

Figure 146 - Experimental 291MHz Multi-Band PLL Output Frequency Spectrum

Case E
The final experimental result presented shows the multi-band PLL synthesizing a
160MHz signal. This is a situation where a frequency that lies in the overlap between
two channels is being synthesized. Figure 147 shows the continuous VCO control
voltage. All three digital control signals are initially low which means the PLL is not in
the correct band of operation. The multi-band PLL was previously locked on a 240MHz
 177

signal. This corresponds to a VCO control voltage of approximately 35mV in band 4.

The VCO connol voltage then tunes up and switches from band 4 to band 3. It settles on
.268V in band 3 to synthesize 160MHz. The measured acquisition time is 8.024ps. This
acquisition process is a pull-in process. The output signal measured with the
oscilloscope is shown in Figure 148. The output frequency spectrum obtained with the
spectrum analyzer is shown in Figure 149. The output signal phase noise is—

~
92.35dBc/Hz at a 50kHz offset.

Scope

1
Input

Cl
CI

50 us
D
O
Scape Channel
Y/0
500
i tl

De 1 ag
3. 7200
mV

us
Offset

Displag
0

Ciptlans
V
R t
Prabe
1 1
Coup~it ng
1Mo 7 DC

Tw
To
=
=
~R
Preset
User
—1.4840 us
6. 5400 us
8 4). 9lnV Band 4 Operdtion ~Switch to Band 3

Figure 147 - Continuous VCO Control Voltage for Multi-Band PLL 160MHz
Output

Scope R R

Period 626 ns Freq 159. 78 MHs 216

O
Input Vp p mV

Cl
Rtsettme 55 ns +Wtdth
—Width
3.57 ns Preshaat 0. 73
Palltime 65 ns 2. 69 ns Overshoot 0 s
Del kg ~ lsplag Sample Data acquired at: 1 ns
200 ns 0 s Options Perlad Newt acqulsltl ~ nt 1 ns

Figure 148 - Experimental 160MHz Multi-Band PLL Output Signal

 178

Dml ta \ I'rl Holi Raft l kHz RF At t 30 dB

Rmf i el -92. 35 aBc Hz vatf 50 Hz
0 asm 50. 0000ii000 knz 5lir 7. 6 m Unit aBm

tVIEH 15A

-6ti

-30

100
Canter l60 lfHz i5 kHz Span le kHz

Da t 27 MAY. 33 2i.'l7:29

Figure 149 - Experimental 160MHz Multi-Sand PLL Output Frequency Spectrum

The multi-hand PLL synthesizes a frequency range of 111 to 290MHz. The

experimental multi-band PLL frequency response and phase noise performance over the
different VCO bands of operation is summarized in Table 21. Thc multi-band PLL
frequency response over the different VCO bands is shown in Figure 150. The
frequency overlap between the VCOs and the tuning mechamsm insures that the

majority of thc frcqucncics are synthesized in the mid-band regions. This overlap also
makes it possible for the same frequency to be synthesized by two hands. The band a
frequency is synthesized in is a function of thc synthesizer's original band of operation.

If the synthesizer is originaSy operatmg in band 1 and attempts to synthcsizc a frequency

that is capable of being synthesized in band 1 or 2 it is more probablc to remain in band

I because the overshoot will not cause it to switch to band 2. The multi-hand PLL phase
 179

noise performance over the different VCO bands is shown in Figure 151. The

synthesizer's phase noise performance mostly lies in the —90 to —95dBc/Hz at a 50kHz
offset. A few points along the edges of the bands perform worse than —90dBc/Hz.

Table 21 - Experimental Multi-Band PLL Results

Phase Noise @ 50kHz

Band Description Frequency Range (MHz)
Offset (dBc/Hz)
All Switches Closed 111 —140 87.68 &-+ -94.06
2 Switches Closed 130 —175 -87.98 ~ -94.52
1 Switch Closed 155 —220 -87.54 ~ -93.99
All Switches 0 en 195 —290 -88.03 ~ -96.49

Expenmentcl uulc-Bend RLL Frcuucncy Rccponce

300
+
200 Band rt +.

260-

240—

220—
Z
Band 3 6
200

2
100
+

160- Band 2

140 + 4
'+
Band 1 1-,
120 o
+
100
05 0 05
VCO Control Volteue (V)

Figure 150 - Experimental Multi-Band PI.I. Frequency Response

 180

Bxprnrnernal Monl-Band pLL pnaac laoarc pcrlonnance

-90',

Br

-99,

100'
1Z0 1'10 160 180 200 ZZ0 2'10 Z60 280 800
Freqnency (MHz)

Eigure 151 - Experimental Multi-Band PLL Phase Noise Performance

 181

Classic Digital PLL Frequency Synthesizer

The prototype chip shown in Figure 152 contains the classic digital PLL frequency
synthesizer.

Buffer
Output Loop Output DC Blocking
t/CO
Buffer Divider Capacitors

Output
Buffers

Loop Charge Phase/Frequency

Filter Pump Detector

Figure 152 - Classic Digital PLL Prototype Chip

The classic digital PLL frequency synthesizer was characterized to determine the

frequency range and phase noise performance on a high frequency test hoard shown in

Figure 153.
 182

High Speed Output

Buffers with Integrated
sosz Termination BNC Connectors
Potentiometers Resistors for High Frequency
and Resistor I/O Signals
Used for Biasing

Headers for Low

Frequency and
Power Signals
Classic Digital
PLL Chip

Large Double-Sided
Ground Plane for
Optimal High Frequency
Performance

Figure 153 - Classic Digital PLL Test Board

The test cases presented in the previous section are reproduced experimentally to
illustrate the PLL frequency synthesizer performance. Table 22 summarizes the setup
for each case. The frequencies have been adjusted from the previous section to comply
with the measured multi-band PLL regions.

Table 22 - Classic Digital PLL Frequency Synthesizer Experimental Case Studies

Initial Experiment Acquisition

Case Final Frequency
Frequency T e Time
Maximum
A 340MHz 370MHz 30MHz 9.53fts
Fre uenc
Minimum
B 340MHz 221MHz — 119MHz 20. 548fts
Fre uency
C 340MHz 250MHz -90MHz Mid-Band 4. 004fts

In all cases thc classic digital PLL is lmtlally operating in the mid-band region at a
frequency of 340MHz. The initial output signal measured with the oscilloscope is
shown in Figurc 154. The initial output frequency spectrum is shown ln Figure 155.
The initial output signal phase noise is —89.38dBc/Hz at a 50kHz offset.
Deo Scope
Input

1.00
Cl
Cl

ns
Scope Auto lleasure
Period
Rlsettme
Falltime
1 au
0 s
2. 94
870 s
ns
t)70 ps

0 Isp)BV
Dpt)ons
Freq
+Width
-Width
Autoscale

Sample
Per)cd
339.95 r)Hz
1.48 ns
1.47 ns

Next
Cancel
Vp p
Preshoot
Overshoot
Data acquired
acquisition:
et:
Run

109
0
0
1

1
183

mY

x
ns
ns

Figure 154 - Initial Experimental 340MHz Classic Digital PLL Output Signal

Oe) te ' IT I NO! I RBH I RHz RF Att 30 de

Ref E I -09 30 dec Hz Ve(4 SO Hz
0 dBm 50. 0 ~ 0 ~ 000 ~ kHz SHT 7. 9 a Un&t dBm
0

-10

-20

-30
)VIEH ISA

-So

-eo

-90
Fx
—100
Center 340 MHz 19 kHz Span 150 kHz
0 te: 2'3 MAY. 99 2('49:19

Figure 155 - Initial Experimental 340MHz Classic Digital PLL Output Frequency
Spectrum
 184

Case A
The first experimental result presented shows the classic digital PLL synthesizing a
370MHz signal. This illustrates a situation where close to the maximum frequency is
being synthesized. Figure 156 shows the VCO control voltage. The PLL was
previously locked on a 340MHz signal. This corresponds to a VCO control voltage of
approximately -80mV. The VCO control voltage then tunes down to -.463V to
synthesize 370MHz. The measured acquisition time is 9.53lts. The reason for the length
of the acquisition time is that the PLL is operating in a region where the VCO gain has
decreased due to non-linearity in the gain. The output signal measured with an

oscilloscope Is shown in Figure 157. Figure l58 shows the output frequency spectrum
obtained with a spectrum analyzer. The output stgnal phase noise is —73.96dBc/Hz at a
50kHz offset.

Scope
Input
CI

2 00 us
O
O De

7. 3600
Scope Channel
V/Div
a00 mV

1 ag
us
Offset
0
Dtsplag
~ pttons
V
Autoscale
Probe
I'I
Cancel

Coupling
1M' / DC

Tx
To
Preset
~ set

-660. 00
8, 8800 us
ns

N
— CI
93. 7mv
0 —337mV

Figure 156 - VCO Control Voltage for Classic Digital PLI. 370MHz Output
 185

Scope Scope Auto tleesure Autoscele Cencel Run

Period 2. 70 ns Freq 370. 20 tthz 73

O
Input Vp p mV

Cl
Risetime EI10 ps +Widt. h 1, 37 ns Preshoot 1.75
Felltime 020 s -Width 1, 33 ns Overshoot 0
9+I v Deleii 019PleS Sample Dote Bcqutred et: 1 ns
1.00 ns 0 s Options Period Next Bcqutstti on: 1 ns
CI

Figure 157 - Experimental 370MHz Classic Digital PLL Output Signal

oct ta I ITI Nell RBN I kHz RF att 30 dl3

Ref U I -73. 96dBc Hz VBN 50 Hz
0 dBm 50. 09000000 kHz 9117 7 6 a U &I dBm
0

-I ~ xo 1. 726 d m

-30
I II I EH

—60

-60

-90
Fx

Center 370 n ~— 15 kHz Bpa 150 kHz

Ua te: 2'3 n47. 99 21 13 17

Figure 158 - Experimental 370MHz Classic Digital PLL Output Frequency

Spectrum
 186

The classic digital PLL cannot synthesize frequencies much higher than 370MHz due to
VCO tuning range limitations. Figure 159 shows the PLL failing to synthesize a

371MHz signal. The output frequency spectrum has a slight peak at 370.5MHz and the
majority of the energy is spread from 370 to 370.8MHz.

RBH IO kHz RF Rt t 30 ds
Rmf E I vBLI SQ Hz
0 dam SRT 20 a Unit dBm

30
IVIEH IAP

Center 37I IIHz 300 kHz Span X MHz

0 I»r 23 MAY. SS 2I:32:32

Figure 159 - Classic Digital PLL Failing To Synthesize 371MHz

Case B
Thc second experimental result presented shows the classic digital PLL synthesizing a

221MHz signal. This illustrates a situation where close to the minimum l'requency is

being synthesized. Figure l60 shows the VCO control voltage. The PLL was

previously locked on a 340MHz signal. This corresponds to a VCO control voltage of

approximately -80mV. Thc VCO control voltage then tunes up to approximately 0.97V
 187

to synthesize 22l MHz. The measured acquisition time is 20.548tts. The length of the
acquisition time is due to the frequency change being outside of the lock range. The
acquisinon process is a puH-in process. The output signal measured with an oscilloscope
is shown in Figure 161. The output frequency spectrum obtained with a spectrum

analyzer is shown in Figure 162. The output signal phase noise is —75.26dBc/Hz at a
50kHz offset.

Scape

O O Scape Channel Autascale Cancel

De
Offset Probe eeet

O
Input V/Div Coupling Pr
C1 700 mV 0 V 1Mn / DC User
De 1 ay Display Tx = -1.2BBD ~s
3. 00 us 12. 100 us Options To 19.260 us
Cl
X-54. 7mV '
0 930mV

Figure 160 - VCO Control Voltage for Classic Digital PLL 221MHz Output

Scope Scape Auto Measure Autosc ~ le Cancel Pun

Perte d 4, 52 Freq 221 00 MHz 219

D
I. nput ns Vp p mV

Cl
Risettme 1 39 ns +width 2. 22 ns Preshoot 0 sl
Fallttrne 1 29 ns -Width 2. 31 ns Overshoot 0 sI
1 ay Dtsplay Sample Data acqutred at 1 n.=, ]
1.00 ns 0 s OptlOnS Pertod Next acquisttton 1 ~ sJ

Cl

Figure 161 - Experimental 221 MHz Classic Digital Pl. l. Output Signal
 I-

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8 555~ E
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 189

Bet ta 1 1T1 Not 1 Ralt 1 kHz RF At t 30 dB

Ref Lvl -69. 27 dBc Hz VB11 50 Hz
0 dBm 50. 00000000 kHz 5117 7. 6 a Unit dBm

JvtEkr 15A

Fx
—100
Center 220 tfkz 15 kHz Span 150 kkz
De te: 29 11AY 99 7 03 16

Figure 163 - Experimental 220MHz Classic Digital PLL Output Frequency

Spectrum

Case C
The third experimental result presented shows the classic digital PLL synthesizing a
250MHz signal. This illustrates a situation where a mid-band frequency is being
synthesized. Figure 164 shows thc VCO control voltage. The previous signal the PLL
was locked on was 340MHz. This corresponds to a VCO control voltage of
approximately -80mV. The VCO control voltage then tunes up to approximately .378V
to synthesize 250MHz. The measured acquisition time is 4. 004ps. This acquisition time

is short because the frequency change is within the lock range, The output signal
measured with an oscilloscope is shown in Figure 165. The output frequency spectrum
 obtained with a spectrum analyzer is shown in Figure 166. The output signal phase
noise is —86. 15dBc/Hz at a 50kHz offset.

Scope
Input
Cl O
O O OScope Channel
Y/Oiv
500 mV
Offset
0 V
Autascale
Probe
1'1
Cancel

Coupling
tnt? / DC
Preset
User

De
Delag Displng Tx = -5d4. 00 ns
1 . 00 us 2. 4500 us Opttons To - 3.4600 us

X — Cl
62. 5mV:-.
0 391mV .

Figure 164 - VCO Control Voltage for Classic Digital PLL 250MHz Output

Scope Scape Auto rlensure Autosc ~ le Cancel Run

Per tod 4 00 ns Freq 250. 00 11Hz 205

O
Input Vp p mV

Cl
R&settme 1. 20 ns +W1dth 1.97 ns Preshao 1 0 x
Fnllttme 1 16 ns -Width 2. 03 ns Overshoot 0
1 ag » splaq Sample Dntn acquired nt: 1 ns
1.00 ns 0 s Opttans Pertod Next ncqutsttton: 1 ns
Cl

Figure 165 - Experimental 250MHz Classic Digital PLL Output Signal

C
I

RRERRRRRRR-
;RRERRi55555
,

RRRRR', RRRRR
RRRRR i55555
.
,

, 55lllRRR
5555RREE
&5RIIIRR
,
55 PRRRRlKI
t 5555
MR
, 55555 5555
 192

Espmimeniel Clesslc tgigimt PLL Frcqocnctt Response

360

360 r

32D

Z
3 300'
I

200
+

260-

m
22D—

200
-0 5 0 D6
VCO Control Voltage (V)

Figure 167 - Experimental Classic Digital PLL Frequency Response

 193

68PDBBnett38 Chettc t7igttet PLL P tteee NDIBD Pert0888003

70

-72

7'I-

-76-
3:
-78

cD -80

Z 02

(' l\

-frB—

30
400 ZZD Z40 260 230 300 320 34D 360 330 4DD
Frequency ifutHB)

Figure 168 - Experimental Classic Digital PLL Phase Noise Performance

A Perforynance Comparison between the iVlulti-Band and the Classic Digital PLL

Frequency Synthesizers
Table 23 provides a comparison between the experimental performance of the multi-
band PLL and the classic digital PLL. In summary, the multi-band PLL achieved a 20%
wider tuning range than the classic digital PLL. The multi-band PLL was able to
achieve a wider tuning range while maintaining a lower VCO conversion gain. This
lower VCO conversion gain allowed the multi-hand PLL frequency synthesizer to
outperform the classic digital PLL in thc area of phase noise performance by an average

of 7.3dB. The synthesizer's acquisition time depends on the region that the PLL
operates in and is a strong function of thc VCO conversion gain. Case A of the multi-
band PLL and the classic digital PLL can be used to compare the acquisition time for a
 194

frequency step of 30MHz. The multi-band PLL has an acquisition time of 4.5ps and the
classic digital PLL has an acquisition time of 9.53ps. However, the reason for the
classic digital PLL to have a slow acquisition is because it is operating near the edge of
the synthesizer's range in a region where the VCO gain is low. Case C of the multi-band
PLL and case B of the classic digital PLL can be used to compare the acquisition time
for a large frequency step to close to the minimum operating frequency. This is a pull-in
process for both synthesizers, with the multi-band PLL switching down three bands.
The multi-band PLL acquires lock in 17.024ps, while the classic digital PLL locks in
20.548(is. Case E of the multi-band PLL and case C of the classic digital PLL can be
used to compare the acquisition time for a mid-band frequency step. The multi-band
PLL has an acquisition time of 8.024ps and the classic digital PLL has an acquisition
time of 4.004ps. This is a pull-in process for the multi-band PLL, during which the PLL
switches bands. The acquisition time is much lower for the classic digital PLL because
the frequency step is within thc lock range due to the large VCO conversion gain of the
PLL.

Table 23 - Multi-Band and Classic Digital PLL Experimental Performance

Comparison

PLL Frequency Average PLL System Phase Noise Acquisition

S stem Ran c (MHz) (dBc/Hz 0
50kHz) 'I'ime ((is)
Multi-Band 111 —290 -92.29 4.5 —17
Classic 221 —370 -84.98 4 —20.5
 CONCLUSIONS
The implementation of a proposed multi-band phase-locked loop frequency synthesizer
was accomplished in this thesis work. This research was motivated by the necessity for
integrated multi-band frequency synthesizers for use in multi-standard transceivers. The
multi-band PLL frequency synthesizer uses a switched tuning VCO that allows a wide
frequency range with a low conversion gain. Experimental results show that the multi-
band PLL frequency synthesizer is superior over the classic digital frequency synthesizer
in terms of frequency range and phase noise performance. These results prove that the
switched tuning VCO structure is suitable for a multi-band synthesizer.

Future work could be performed to improve the performance of the multi-bund PLL
frequency synthesizer and make it easier to integrate into a multi-standard transceiver.
The use of a four-stage differential ring oscillator would improve the phase noise

performance due to the higher rejection of supply and common-mode noise. Also, a
four-stage oscillator provides quadrature outputs necessary in typical communication
systems. The usc of differential current-mode flip-flops in the loop divider would also
aid in noise performance and improve thc robustness of the loop divider. These flip-
flops could be integrated into a dual-modulus prescaler for use in fractional-iV frequency
synthesis.

The multi-band Pl.l. frequency synthesizer v'as implemented using a L2ltm technology.
The multi-band PLL frequency synthesizer can synthesize higher frequencies with the

use of sub-micron technology. Operating at higher frequencies with the use of sub-
micron technology would reduce thc area required to use a higher Q switched tuning LC

oscillator. A higher Q switched tuning LC oscfllator has better phase noise performance

over a low Q ring oscillator. The use of an LC oscillator would thus result in superior

synthesizer phase noise performance.

 196

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 201

APPENDIX A

SPECTREHDL MULTI-BAND PLL FREQUENCY SYNTHESIZER

BEHAVIORAL MACROMODEL

// Multi-Band Phase Locked Loop Frequency Synthesizer Macromodel

// Main Spectre File
// Samuel Palermo

simulator lang=spectre
include "/home/samuel/research/pl 1/macromodels/pd/diff d/dig~fd. def"
include "/home/samuel/research/pll/macromodels/lpf/lpf. def"
ahdl include "/home/samuel/research/pll/macromodels/vco/vco. def"
ahdl include "/home/samuel/reseacch/pll/macromodels/vco/switch vco. def"
ahdl include
+ "/home!samuel/research/pll/macromodels/divider/divider. def"
include "/home/samuel/research/pll/macromodels/vco/reference. def"
// Power Supply
vdd dd 0 vsource dc=1

// Reference Signal
xref 0 control fref reference
vcontrol control 0 vsource type=pwl wave=(0 0. 64 lu 0. 64]
// Digital Tri —State Phase/Frequency Comparator
xdig~fd 0 dd f ref fvco up upbar down downbar diff d
// Charge Pump
iup dd 1 isource dc=25u
idown 2 0 isource dc=25u

gup 1 vd up 0 relay vt1=0 vt2=1 ropen=lOOM rclosed=1m

gupbar 1 0 upbar 0 relay vt1=0 vt2=1 ropen=lOOM rclosed=1m
g clown vcl 2 down 0 relay vt1=0 vt2=1 ropen=lOOM rclosed=1m
gdownbar dd 2 downbar 0 relay vt. 1=0 vt2=1 ropen=lOOM rclosed=-lm

// Loop Filter
xfilter 0 vd lpf
gvdgnd vd 0 vd gnd 0 relay vt. 1=0 vC2=1 ropen=lOOM rclosed=10
// Voltage Controlled Oscilla. .or
//xvco vd out vco (gain=40e6 fc=2o6e6)
xvco 0 vd out nv temp vd gnd
+ switch vco (u=0. 8 d=-O. B gain=40e6 fc=256e6)

// Divider
xdivider 0 out fvco buffer n temp divider (divisor=32)
op c1c
 202

timedom tran stop=20u step=20p ic=all maxstep=20p skipdc=yes

relref=alllocal
simulator lang=spice
. ic vd=0
save vd control fref fvco nv temp vd gnd
. OPTIONS rawfmt=psfbin save=selected diagnose=yes vabsto1=. 01
+ relto1=. 99

// Digital Phase Frequency Detector Macromodel

// Samuel Palermo

subckt dig~fd (gnd dd fref fvco up upbar down downbaz)

ahdl include "/home/samuel/research/pll/macromodels/pd/dig~fd/dff. def"

ahdl include
"/home/samuel/research/pll/macromodels/pd/dig~fd/nand. def"
xdffup gnd dd fref up upbar r dff
xdffdown gnd dd fvco down downbar r dff
xnand gnd up down r nand

ends dig~fd
issa sssa sassssassssa a sa a ssa sssa ssssssssssasassssssa sssssssssssssa a

// D Flip Flop Macr. omodel

// Samuel Palermo

module dff(gnd, D, CLK, Q, QBAR, R) ()

node [V, I] gnd, D, CLK, Q, QBAR, R
(

zeal Q temp;
real QBAR temp;

initial (
Q temp=0;
QBAR temp=1;

analog
rf ($threshold (V(CLK, gnd)-l, I))
if (V(D, gnd)==1)
temp=1;
Q
QBAR temp=0;
)
else (
Q temp=0;
QBAR temp=1;
)

)
(V(R, gnd) ==0)
Q temp=0;
QBAR temp=1;
 203

)
V(Q, gnd) & — Q temp;
V(QBAR, gnd) &- QBAR temp;
)

// NAND Nacromodel
// Samuel Palermo

module nand(gnd, A, B, 0) ()
node [V, I] gnd, A, B, 0

real 0 temp;

analog (

if ((V(A, gnd)==1) && (V(B, gnd) ==1) ) (

0 temp=0;
)
else (
0 temp=1;
V(0, gnd) &— 0 temp;
)
)
gaea&pea; sesssesseeessseeeeaee 'eeee 'essgsssssgsssss8s
, , 'sew&is&see 'eegeee
, ,

// Low Pass Filter Macromodel

// Samuel Palermo

subckt lpf(gnd vd)

cl vd capacitor c=62. 2p
z
// DampingFactor = 0. 7
r z gndresistor r=31. 8k
//Damping Factor = 1
//r z gnd resistor r=45. 7k
//Damping Factor = 10
//r z gnd resistor r=457k
//Damping Factor = 0. 1
//r z gnd resistor r=4. 57k
//Damping Fact or = 2
//r z gnd. resistor r=91. 4k
//Damping Factor = 0. 5
//r z gnd resist. or r=22. 9k
c2 vd gnrl capacitor c=6p

ends lpf
eeeesesessesassssess, 'sssse, 'gee;a&seas. aee,'eesssess
,

// VCO Kacromodel
// Samuel Palermo
 204

¹define PI 3. 14159265359
module vco(IN, OUT) (gain, fc)
node [V, I] IN, OUT;
parameter real gain = 1, fc = 1;
(
analog
V(OUT) &- sin(2*PI*(integ(fc + gain*V(IN), 0)));
)

// Switched Tuning vCO Macromodel

// Samuel Palermo

¹define PI 3. 14159265359
module switch vco(gnd, vd, out, nv temp, vd gnd) (u, d, gain, fc)
node (V, I] gnd, vd, out, nv temp, vd gnd;
parameter real u = 1, d = 1, gain = 1, fc = 1;
(

integer n;
real vd gnd temp;
ini. rial (
n=0;
)

analog (
if((V(vd, gnd) & lm) && (V(vd, gnd) & —lm)) (
vd gnd temp = 0;
)
if (Sthreshold ( (V(vd, gnd) —(u) ), +11 ) (
n=n+1;
vd gnd temp=1;
)
if (Sthreshold ((V(gnd, vd)+(d)), +1))
n=n-1;
vd gnd temp=1;
)
V(out, gnd) s — 1.35*sin (2*PI* (integ ( ( fc+ (2*.7*u*n "gain) ) +
+ gain*V(vd, gnd), 0)));
V(nv temp, gnd) a- n;
V(vd gnd, gnd) &- vd gnd temp;
)
)
assssssssasaas, a, ss, saasgsggssssgssag kgb'

// Loop Divider Macromodel

// Samuel Pa)ermo

module divider(gnd, out, fvco, buffer, n temp) (divisor)

parameter integer divisor = 1;
 205

node (V, I) gnd, out, fvco, buffer, n temp

(
real buffer temp;
integer n;
real fvco temp;

initial (
buffer temp=Ol
n=l;
fvco temp=1;

analog (
if(V(out, gnd)~0) (
buffer temp=1;
)
else (
buffer temp=-1;
rf($threshold (V(buffer, gnd) —1, 1)) (
n=n+1;
)
lf ($threshold (V(buf fer, gnd)+1, -1) ) (
n=n+1;
)
if(n==divisor) (
n=0;
fvco temp=(-1*fvco temp)
)
V(fvco, gnd) &- fvco temp;
V(buffer, gnd) &- buffer temp;
V(n temp, gnd) & — n;
)

aaaasaassssaaaassssaagsaaaasgsaagsssssassssgsaasessa; ssssaasas
// Reference Macromodel
// Samuel Palermo

subckt z'eference(gnd control in)

ahdl include "/home/samuel/research/pll/macromodels/vco/buffer. def"
xvco control out vco (gain=1. 25e6 fc/ Be6)
xbuffer gnd out in buffer
ends reference

// Suffer Macromodel
// Samuel Palezmo

module buffer(gnd, in, out)

 206

node [V, I] gnd, in, out

real out temp;

initial (
out temp=0;
)

analog (
if(V(in, gnd)&0) (
out temp=1;
)
else (
out temp=-1;
)
V(out, gnd) ~— out temp;
)
)
 207

VITA
Samuel Michael Palermo was born in Bryan, TX, on October 28, 1974. He graduated
magna curn laude with a B.S. degree in electrical engineering from Texas A&M
University in May 1997. He will receive the M. S. degree in electrical engineering in

August 1999.

From 1995 to 1997, he worked as an intern for Texas Instruments, Dallas, TX, where he
designed SRAM's for ASIC designs and performed ESD and latch-up characterization.
During the summer of 1997, he was with Motorola, Austin, TX, where he performed
design work on integrated test circuitry for HC08 micro-controllers. He will soon join
Texas Instruments, Dallas, TX, where he will work on high-speed CMOS clock recovery
and data synchronization circuits.

Mr, Palermo ts a member of IEEE, Eta Kappa Nu, and Phi Eta Sigma. He received a
Texas ARM University Regents' Fellowship in 1997 and a National Science Foundation
Graduate Research Fellowship in 1999.

PERMANENT ADDRESS
1589 Palcrmo Lane
Bryan, TX 77808