Chapter 4

The Processor

Jiang Jiang
[email protected]
[Adapted from Computer Organization and Design,
4th Edition, Patterson & Hennessy, © 2008, MK]

Chapter 4 — The Processor — 2

 §4.1 Introduction
Introduction
n CPU performance factors
n Instruction Count
n Determined by ISA and compiler
n CPI and Cycle time
n Determined by CPU hardware
n We will examine two MIPS implementations
n A simplified version
n A more realistic pipelined version
n A basic MIPS implementation
n Simple ISA subset, shows most aspects
n Memory reference: lw, sw
n Arithmetic/logical: add, sub, and, or, slt
n Control transfer: beq, j

Chapter 4 — The Processor — 3

Instruction Execution
n For all instructions, the first 2 steps are identical
n PC → (instruction, Harvard) memory, fetch instruction
n Read one or two registers, using register numbers in fields of
instruction → register file, read registers
n Depending on instruction class, but the actions are
largely the same
n Use ALU to calculate
n Arithmetic result
n Memory address for load/store
n Branch target address
n Access data memory for load/store
n PC ← target address or PC + 4
n Simplicity favors regularity!

Chapter 4 — The Processor — 4

CPU Overview

Chapter 4 — The Processor — 5

Multiplexers
n Can’t just join
wires together
n Use multiplexers

Chapter 4 — The Processor — 6

Control

Chapter 4 — The Processor — 7

 §4.2 Logic Design Conventions
Logic Design Basics
n Information encoded in binary
n Low voltage = 0, High voltage = 1
n One wire per bit
n Multi-bit data encoded on multi-wire buses
n Combinational element
n Operate on data
n Output is a function of input
n State (sequential) elements
n Store information

Chapter 4 — The Processor — 8

Combinational Elements
n AND-gate n Adder A
Y
+
n Y = A && B n Y = A || B B

A
Y
B

n Arithmetic/Logic Unit
n Multiplexer n Y = F(A, B)
n Y = S ? I1 : I0
A
I0 M
u Y ALU Y
I1 x
B
S F

Chapter 4 — The Processor — 9

Sequential Elements
n Register: stores data in a circuit
n Uses a clock signal to determine when to
update the stored value
n Edge-triggered: update when Clk changes
from 0 to 1

Clk
D Q
D
Clk
Q

Chapter 4 — The Processor — 10

 Sequential Elements
n Register with write control
n Only updates on clock edge when write
control input is 1
n Used when stored value is required later

Clk

D Q Write
Write D
Clk
Q

Chapter 4 — The Processor — 11

Clocking Methodology
n Combinational logic transforms data during
clock cycles
n Between clock edges
n Input from state elements, output to state
element
n Longest delay determines clock period

Chapter 4 — The Processor — 12

 §4.3 Building a Datapath
Building a Datapath
n Computer Organization
n Datapath, control, memory, Input, output
n Datapath
n Elements that operate on or hold data and
addresses in the CPU
n Register file, ALUs, mux’s, I/D memories, …

n We will build a MIPS

datapath incrementally
n Refining the overview
design

Chapter 4 — The Processor — 13

Instruction Fetch

Increment by
4 for next
32-bit instruction
register

In MIPS, PC is affected only indirectly by certain

instructions - it is NOT an architecturally-visible register
Chapter 4 — The Processor — 14
R-Format Instructions
n Read two register operands (multi-port RF)
n Perform arithmetic/logical operation
n Write register result

32

32
32

Chapter 4 — The Processor — 15

Load/Store Instructions
n Read register operands
n Calculate address using 16-bit offset
n Use ALU, but sign-extend offset to byte address!
n LW rt, offset(base) : lw $t0, 32($s3)
n Load: Read memory and update register
n Store: Write register value to memory

Chapter 4 — The Processor — 16

Branch Instructions
n Read register operands
n beq $t0, $zero, L1
n Compare operands
n Use ALU, subtract and check Zero output (?)
n Calculate target address
n Sign-extend displacement: 16b -> 32b
n Shift left 2 places (word displacement)
n Add to PC + 4
n Already calculated by instruction fetch
n Reuse datapath with ld/st instructions
Chapter 4 — The Processor — 17
Branch Instructions
Just
re-routes
wires

Sign-bit wire
replicated

Chapter 4 — The Processor — 18

Composing the Elements
n The simplest datapath executes an
instruction in one clock cycle
n Each datapath element can only do one
function at a time
n Hence, we need separate instruction and data
memories (Harvard Architecture)
n Use multiplexers where alternate data
sources are used for different instructions

Chapter 4 — The Processor — 19

R-Type/Load/Store Datapath

ld?

ld/st?

Chapter 4 — The Processor — 20

Full Datapath

PC+4

Immediate/
Offset

Chapter 4 — The Processor — 21

 §4.4 A Simple Implementation Scheme
ALU Control
n Datapath + Control function
n ALU used for
n Load/Store: F = add
n Branch: F = subtract
n R-type: F depends on funct field

ALU control Function

0000 AND
0001 OR
0010 Add
0110 Subtract
0111 set-on-less-than
1100 NOR
Chapter 4 — The Processor — 22
ALU Control
n Combinational logic derives ALU control
n Assume 2-bit ALUOp derived from opcode
n add:00, sub:01, determined by funct field: 10
n Multiple levels of decoding
n 4-bit ALU control input ç 2-bit ALUOp field and 6-bit funct field

opcode ALUOp Operation funct ALU function ALU control

lw 00 load word XXXXXX add 0010
sw 00 store word XXXXXX add 0010
beq 01 branch equal XXXXXX subtract 0110
R-type 10 add 100000 add 0010
subtract 100010 subtract 0110
AND 100100 AND 0000
OR 100101 OR 0001
set-on-less-than 101010 set-on-less-than 0111
xxxxx: don’t care Chapter 4 — The Processor — 23
The Main Control Unit
n Control signals derived from instruction
n Simplicity favors regularity!
R-type 0 rs rt rd shamt funct
31:26 25:21 20:16 15:11 10:6 5:0

Load/
35 or 43 rs rt address
Store
31:26 25:21 20:16 15:0

Branch 4 rs rt address
31:26 25:21 20:16 15:0

opcode always read, write for R-type sign-extend

read, except for and load and add
base for load
load/store

Chapter 4 — The Processor — 24

Datapath With Control

opcode

data of st

ld? ld?

funct ld/st?

Chapter 4 — The Processor — 25

R-Type Instruction

R-type 0 rs rt rd shamt funct

31:26 25:21 20:16 15:11 10:6 5:0

Load/
35 or 43 rs rt address
Store
31:26 25:21 20:16 15:0

Branch 4 rs rt address
31:26 25:21 20:16 15:0

opcode always read, write for R-type sign-extend

read, except for and load and add
base for load
load/store

Chapter 4 — The Processor — 26

R-Type Instruction

Chapter 4 — The Processor — 27

Load Instruction

R-type 0 rs rt rd shamt funct

31:26 25:21 20:16 15:11 10:6 5:0

Load/
35 or 43 rs rt address
Store
31:26 25:21 20:16 15:0

Branch 4 rs rt address
31:26 25:21 20:16 15:0

opcode always read, write for R-type sign-extend

read, except for and load and add
base for load
load/store

Chapter 4 — The Processor — 28

Load Instruction

Chapter 4 — The Processor — 29

Branch-on-Equal Instruction

R-type 0 rs rt rd shamt funct

31:26 25:21 20:16 15:11 10:6 5:0

Load/
35 or 43 rs rt address
Store
31:26 25:21 20:16 15:0

Branch 4 rs rt address
31:26 25:21 20:16 15:0

opcode always read, write for R-type sign-extend

read, except for and load and add
base for load
load/store

Chapter 4 — The Processor — 30

Branch-on-Equal Instruction

Chapter 4 — The Processor — 31

Implementing Jumps
Jump 2 address
31:26 25:0

n Jump uses word address

n Update PC with concatenation of
n Top 4 bits of old PC
n 26-bit jump address
n 00 (word address to byte address)
n Need an extra control signal decoded from
opcode
Chapter 4 — The Processor — 32
Datapath With Jumps Added

Chapter 4 — The Processor — 33

Performance Issues
n The single-cycle implementation is not practical
n Longest delay determines clock period
n Critical path: load instruction
n Instruction memory → register file → ALU → data memory →
register file
n Not feasible to vary period for different
instructions
n Violates design principle
n Making the common case fast
n We will improve performance by pipelining

Chapter 4 — The Processor — 34

 §4.5 An Overview of Pipelining
Pipelining Analogy
n Pipelined laundry: overlapping execution
n Parallelism improves performance

n Four loads:
n Speedup
= 8/3.5 = 2.3
n Non-stop:
n Speedup
= 2n/(1.5 + 0.5n) ≈ 4
= number of stages

n-1:1.5
Chapter 4 — The Processor — 35
Parallelism
n The most fundamental ways to improve
performance
n Two types of parallelism
n Temporal parallelism
n Pipeline
n Less work per stage ⇒ shorter clock cycle
n More penalty in control hazard and interruption
n Spatial parallelism
n Multiple function units, multiple cores
n Replicate resource, multiple issue, multicore

Chapter 4 — The Processor — 36

MIPS Pipeline
n Five stages, one step per stage
1. IF: Instruction fetch from memory
2. ID: Instruction decode & register read
3. EX: Execute operation or calculate address
4. MEM: Access memory operand (load/store)
5. WB: Write result back to register

Chapter 4 — The Processor — 37

 Pipeline Performance
n Assume time for stages is
n 100ps for register read or write
n 200ps for other stages
n Compare pipelined datapath with single-cycle
datapath

Instr Instr fetch Register read ALU op Memory Register Total time
Decode access write
lw 200ps 100 ps 200ps 200ps 100 ps 800ps
sw 200ps 100 ps 200ps 200ps 700ps
R-format 200ps 100 ps 200ps 100 ps 600ps
beq 200ps 100 ps 200ps 500ps

Chapter 4 — The Processor — 38

Pipeline Performance
Single-cycle (Tc= 800ps)

Pipelined (Tc= 200ps)

Chapter 4 — The Processor — 39

Pipelined Datapath

Chapter 4 — The Processor — 40

Pipeline Speedup
n If all stages are balanced
n I.e., all take the same time
n Time between instructionspipelined
= Time between instructionsnonpipelined
Number of stages
n If not balanced, speedup is less
n Speedup due to increased throughput
n Latency (time for each instruction) does not
decrease

Chapter 4 — The Processor — 41

Pipelining and ISA Design
n MIPS ISA designed for pipelining
n All instructions are 32-bits
n Easier to fetch in one cycle
n C.f. x86: 1- to 17-byte instructions
n Few and regular instruction formats
n Can decode and read registers in one step
n Load/store addressing
n Can calculate address in 3rd stage, access memory
in 4th stage
n Alignment of memory operands
n Memory access takes only one cycle

Chapter 4 — The Processor — 42

Pipeline Hazards
n Situations that prevent starting the next
instruction in the next cycle
n 3 types of hazards
n Structure hazards
n A required resource is busy, e.g. memory
n Data hazard
n Need to wait for previous instruction to complete its
data read/write (Producer-Consumer problem)
n Control hazard
n Deciding on control action depends on previous
instruction, e.g. branch

Chapter 4 — The Processor — 43

Structure Hazards
n Conflict for use of a resource
n In MIPS pipeline with a single memory
n Load/store requires data access
n Instruction fetch would have to stall for that
cycle => Would cause a pipeline “bubble”
n Hence, pipelined datapath requires
separate instruction/data memories
n Or separate instruction/data caches (L1I, L1D)
n Modified Von Neumann, cf. Harvard
architecture
Chapter 4 — The Processor — 44
Pipelined Datapath

Chapter 4 — The Processor — 45

Data Hazards
n An instruction depends on completion of
data access by a previous instruction
n add $s0, $t0, $t1
sub $t2, $s0, $t3

WR

5-2=3, 2 bubbles!
Chapter 4 — The Processor — 46
Forwarding (aka Bypassing)
n Use result when it is computed
n Don’t wait for it to be stored in a register
n Requires extra connections in the datapath

No bubble!

4-3=1, no stall!

Chapter 4 — The Processor — 47

Load-Use Data Hazard
n Can’t always avoid stalls by forwarding
n If value not computed when needed
n Can’t forward backward in time!

IF ID EX

5-3=2, 1 bubble!

Chapter 4 — The Processor — 48

Code Scheduling to Avoid Stalls
n Reorder code to avoid use of load result in
the next instruction
n C code for A = B + E; C = B + F;

lw $t1, 0($t0) lw $t1, 0($t0)

lw $t2, 4($t0) lw $t2, 4($t0)
stall add $t3, $t1, $t2 lw $t4, 8($t0)
sw $t3, 12($t0) add $t3, $t1, $t2
lw $t4, 8($t0) sw $t3, 12($t0)
stall add $t5, $t1, $t4 add $t5, $t1, $t4
sw $t5, 16($t0) sw $t5, 16($t0)
13 cycles 11 cycles

Chapter 4 — The Processor — 49

Control Hazards
n Branch determines flow of control
n Fetching next instruction depends on branch outcome
n Pipeline can’t always fetch correct instruction, so
n Stall on branch and wait for the outcome of branch, or
n Fetch next instruction (predict none-taken) and go
n In MIPS pipeline
n Need to compare registers and compute target earlier
in the pipeline
n Add extra hardware to do it in ID stage (earliest ? )

..…. (I3) I2 I1
..…. (?) I2? beq
Chapter 4 — The Processor — 50
Stall on Branch
n Wait until branch outcome determined
before fetching next instruction
n 1 bubble when determine in ID
n Is no stall possible? IF, prediction

3-1=2, 1 bubble!

Chapter 4 — The Processor — 51

Branch Prediction
n Longer pipelines can’t readily determine branch
outcome early
n Stall penalty becomes unacceptable
n Predict outcome of branch in early stage
n Only flush pipeline if prediction is wrong
n As early as possible
n In MIPS pipeline
n (MIPS) Can predict branches not taken => sequential
n Fetch instruction after branch (PC+4), with no delay
n Where to predict? IF stage
n Where to compute outcome? ID stage or later
Chapter 4 — The Processor — 52
MIPS with Predict Not Taken

Prediction
correct:
reward

2-1=1, No bubble!

Prediction
incorrect:
penalty lw $3, 300($0) flush lw inst.

ID stage Chapter 4 — The Processor — 53

More-Realistic Branch Prediction
n Static branch prediction
n Based on typical branch behavior
n Example: loop and if-statement branches
n Predict backward branches taken
n Predict forward branches not taken
n Dynamic branch prediction
n Hardware measures actual branch behavior
n E.g., record recent history of each branch
n Assume future behavior will continue the trend
n When wrong, flush and re-fetching, and update history
n More than 90% accuracy

Chapter 4 — The Processor — 54

Pipeline Summary
The BIG Picture

n Pipelining improves performance by

increasing instruction throughput
n Executes multiple instructions in parallel
n Each instruction has the same latency
n Subject to hazards
n Structure, data, control
n Instruction set design affects complexity of
pipeline implementation
Chapter 4 — The Processor — 55
 §4.6 Pipelined Datapath and Control
MIPS Pipelined Datapath

Right-to-left WB
flow leads to
hazards

Chapter 4 — The Processor — 56

Pipeline registers
n Need pipeline registers between stages
n To hold information produced in previous cycle

1 2 3 4 5

5.5 5

Chapter 4 — The Processor — 57

Pipeline Operation Diagram
n Cycle-by-cycle flow through the pipelined datapath
n “Single-clock-cycle” pipeline diagram
n Snapshot of pipeline usage in a single cycle
n Temporal parallelism
n Highlight resources used
n “multi-clock-cycle” diagram
n Graph of operation over time

Chapter 4 — The Processor — 58

Pipeline Operation Diagram
n We highlight the right half of registers or
memory when they are being read and
highlight the left half when they are being
written
n We’ll look at “single-clock-cycle” diagrams
for load & store

WR

Chapter 1 — Computer Abstractions and Technology — 59

IF for Load, Store, …
WR

1 2 3 4 5 5.5

5.5 6 5

Chapter 4 — The Processor — 60

ID for Load, Store, …

1 2 3 4 5 5.5

5.5 6 5

Chapter 4 — The Processor — 61

EX for Load

1 2 3 4 5 5.5

5.5 6 5

Chapter 4 — The Processor — 62

MEM for Load

1 2 3 4 5 5.5

5.5 6 5

Chapter 4 — The Processor — 63

WB for Load

1 2 3 4 5 5.5

Wrong
register 5.5 6 5
number

Chapter 4 — The Processor — 64

Corrected Datapath for Load

1 2 3 4 5 5.5

5.5 6 5

Instruction[20-16]

Chapter 4 — The Processor — 65

EX for Store

1 2 3 4 5 5.5

5.5 6 5

Chapter 4 — The Processor — 66

MEM for Store

1 2 3 4 5 5.5

5.5 6 5

Chapter 4 — The Processor — 67

WB for Store

1 2 3 4 5 5.5

5.5 6 5

Chapter 4 — The Processor — 68

Multi-Cycle Pipeline Diagram
n Form showing resource usage

Temporal parallelism

Chapter 4 — The Processor — 69

Single-Cycle Pipeline Diagram
n State of pipeline in a given cycle

Chapter 4 — The Processor — 70

Pipelined Control (Simplified)
Why used here?

st data ld?

32

ld/st?

ld?
Chapter 4 — The Processor — 71
 Pipelined Control
n Control signals derived from instruction
n As in single-cycle implementation

Instruction[31-26]

Chapter 4 — The Processor — 72

The Main Control Unit
n Control signals derived from instruction
R-type 0 rs rt rd shamt funct
31:26 25:21 20:16 15:11 10:6 5:0

Load/
35 or 43 rs rt address
Store
31:26 25:21 20:16 15:0

Branch 4 rs rt address
31:26 25:21 20:16 15:0

opcode always read, write for R-type sign-extend

read, except for and load and add
base for load
load/store

Chapter 4 — The Processor — 73

Pipelined Control

32

ld? Why not select in ID stage? Chapter 4 — The Processor — 74

 §4.7 Data Hazards: Forwarding vs. Stalling
Data Hazards in ALU Instructions
n Consider this sequence
sub $2, $1,$3
and $12,$2,$5
or $13,$6,$2
add $14,$2,$2
sw $15,100($2)
n We can alleviate hazards by 2 means
n Data forwarding from preceding instructions
n Read and write a register in the same cycle

Chapter 4 — The Processor — 75

Dependencies & Forwarding

5.5 6.5
5 6
Alternatively,
Reg Value is
available here

Inner-register forwarding

Chapter 4 — The Processor — 76

Register File Access Hazard
n Fix register file access hazard
n Write in the first half of the cycle and
n Read in the second half
n Read and write a register in the same
cycle => no data hazard
n It’s the case for many implementation of
register file

Chapter 1 — Computer Abstractions and Technology — 77

 Register File Access?
Time (clock cycles)
1 2 3 4 5 6

ALU
sub $2,
Alternatively,

I IM Reg DM Reg Reg Value is

available
here

n
s

ALU
t Inst 2 IM Reg DM Reg
r.

ALU
O Inst 3 IM Reg DM Reg
r
d

ALU
e add $14,$2, IM Reg DM Reg
r

5.5


clock edges that control the
clock edge that controls the pipeline registers writing
register file writing
Detecting the Need to Forward
n Pass register numbers along pipeline
n E.g., ID/EX.RegisterRs = register number for Rs
sitting in ID/EX pipeline register
n ALU (consumer) operand register numbers in EX
stage are given by
n ID/EX.RegisterRs, ID/EX.RegisterRt
n Data hazards when
nBypassing from two stages to ID/EX
Fwd from
1a. EX/MEM.RegisterRd = ID/EX.RegisterRs EX/MEM
pipeline reg
1b. EX/MEM.RegisterRd = ID/EX.RegisterRt
2a. MEM/WB.RegisterRd = ID/EX.RegisterRs Fwd from
MEM/WB
2b. MEM/WB.RegisterRd = ID/EX.RegisterRt pipeline reg

Chapter 1 — Computer Abstractions and Technology — 79

Forwarding Paths

ld ? Why here ?

Chapter 4 — The Processor — 80

Detecting the Need to Forward
n But only if forwarding instruction will write
to a register!
n EX/MEM.RegWrite, MEM/WB.RegWrite
n And only if Rd for that instruction is not
$zero (why?)
n EX/MEM.RegisterRd ≠ 0,
MEM/WB.RegisterRd ≠ 0

Chapter 4 — The Processor — 81

Forwarding Conditions
n EX hazard (forwarding from EX/MEM register)
n if (EX/MEM.RegWrite and (EX/MEM.RegisterRd ≠ 0)
and (EX/MEM.RegisterRd = ID/EX.RegisterRs))
ForwardA = 10
n if (EX/MEM.RegWrite and (EX/MEM.RegisterRd ≠ 0)
and (EX/MEM.RegisterRd = ID/EX.RegisterRt))
ForwardB = 10
n MEM hazard (forwarding from MEM/WB register)
n if (MEM/WB.RegWrite and (MEM/WB.RegisterRd ≠ 0)
and (MEM/WB.RegisterRd = ID/EX.RegisterRs))
ForwardA = 01
n if (MEM/WB.RegWrite and (MEM/WB.RegisterRd ≠ 0)
and (MEM/WB.RegisterRd = ID/EX.RegisterRt))
ForwardB = 01

Chapter 4 — The Processor — 82

Double Data Hazard
n Consider the sequence:
add $1,$1,$2 ;instr 1 in WB
add $1,$1,$3 ;instr 2 in MEM
add $1,$1,$4 ;instr 3 in EX
n Both hazards occur
n Want to use the most recent value (closest producer
instruction)
n I.e. instruction 3 should get the value forwarding from
instruction 2 (EX/MEM), not instruction 1 (MEM/WB)
n Revise MEM hazard condition (forwarding from
WB Stage)
n Only forwd if EX hazard condition isn’t true
Chapter 4 — The Processor — 83
Revised Forwarding Condition
n MEM hazard (forwarding from MEM/WB register)
n if (MEM/WB.RegWrite and (MEM/WB.RegisterRd ≠ 0)
and not (EX/MEM.RegWrite and (EX/MEM.RegisterRd ≠ 0)
and (EX/MEM.RegisterRd = ID/EX.RegisterRs))
and (MEM/WB.RegisterRd = ID/EX.RegisterRs))
ForwardA = 01
n if (MEM/WB.RegWrite and (MEM/WB.RegisterRd ≠ 0)
and not (EX/MEM.RegWrite and (EX/MEM.RegisterRd ≠ 0)
and (EX/MEM.RegisterRd = ID/EX.RegisterRt))
and (MEM/WB.RegisterRd = ID/EX.RegisterRt))
ForwardB = 01

Chapter 4 — The Processor — 84

Datapath with Forwarding
RegWrite RegWrite

ld -> Rt
Chapter 4 — The Processor — 85
Load-Use Data Hazard

5.5

Need to stall
for one cycle

5-3=2, 1 bubble!

Chapter 4 — The Processor — 86

Load-Use Hazard Detection
n Check load-use hazard in ID stage (why?)
n Where to stall and insert bubble?
n ALU operand register numbers in ID stage are
given by
n IF/ID.RegisterRs, IF/ID.RegisterRt: consumers
n Load-use hazard when
n ID/EX.MemRead and
((ID/EX.RegisterRt = IF/ID.RegisterRs) or
(ID/EX.RegisterRt = IF/ID.RegisterRt))
Load/
35 or 43 rs rt address
Store
31:26 25:21 20:16 15:0

Chapter 4 — The Processor — 87

Load-Use Hazard Detection
n If the load-use hazard detected
n 1st cycle: stall and insert bubble from ID to EX stage
in the 1st cycle (current cycle), keep the “use”
instruction in ID stage
n 2nd cycle: the EX stage is a bubble in the 2nd cycle è
1 bubble
n Load instruction is in MEM now
n 3rd cycle: let the current “use” instruction go to EX
stage in the 3rd cycle, and forward the “load” data
from EX/MEM to EX stage
n Load instruction is in WB now

Chapter 4 — The Processor — 88

 Load-Use Hazard Detection
4IME IN CLOCK CYCLES
##  ##  ##  ##  ##  ##  ##  ##  ##  ## 

0ROGRAM
EXECUTION
1st 2nd 3rd
ORDER
IN INSTRUCTIONS

LW   )- 2EG $- 2EG

BUBBLE

AND BECOMES NOP )- 2EG $- 2EG

AND    Keep )-
! 2EG $- 2EG

OR    )- 2EG $- 2EG

ADD    )- 2EG $- 2EG

1, Ê{°x™Ê / iÊÜ>ÞÊÃÌ>ÃÊ>ÀiÊÀi>Þʈ˜ÃiÀÌi`ʈ˜ÌœÊÌ iÊ«ˆ«iˆ˜i°Ê! BUBBLE IS INSERTED BEGINNING IN CLOCK CYCLE  BY CHANGING THE
AND INSTRUCTION TO A NOP .OTE THAT THE AND INSTRUCTION IS REALLY FETCHED AND DECODED IN CLOCK CYCLES  Chapter
AND  BUT ITS4%8
—STAGE
TheIS Processor
DELAYED UNTIL — 89
CLOCK CYCLE  VERSUS THE UNSTALLED POSITION IN CLOCK CYCLE   ,IKEWISE THE /2 INSTRUCTION IS FETCHED IN CLOCK CYCLE  BUT ITS )$ STAGE IS DELAYED
How to Stall the Pipeline
n Force control values in ID/EX register to 0
n Check in ID stage, and insert bubble into EX stage
n EX, MEM and WB do nop (no-operation)
n Prevent update of PC and IF/ID register
n Keep current instruction in IF/ID, next instruction is PC
n Using (Current) instruction is decoded again
n Following instruction is fetched again (by same PC)
n 1-cycle stall allows MEM to read data for lw
n Can subsequently forward to EX stage in next cycle
n Alternative: valid signal for each instruction?

Chapter 4 — The Processor — 90

Datapath with Hazard Detection

Checking Forwarding

ld instr’s Rt, Instruction[20-16]

ID/EX.RegisterRt

Chapter 4 — The Processor — 91

Datapath with Hazard Detection
Stall !

ld instr’s Rt,
Instruction[20-16]

Chapter 4 — The Processor — 92

Stall/Bubble in the Pipeline

Check here: ID

Bubble inserted here: ID

Forward here: EX, from MEM/WB

Or, more accurately…

Chapter 4 — The Processor — 93
Stalls and Performance
The BIG Picture

n Stalls reduce performance

n But are required to get correct results
n Compiler can rearrange code to avoid hazards
and stalls
n Requires knowledge of the pipeline structure
n Data hazard doesn’t occur (no stalls) when
n For instructions: i (producer), ......, j (consumer)
InstrSeqNum(j) - InstrSeqNum(i) ≥
EarliestDataValidStageNum(i) - DataUseStageNum(j)

Chapter 4 — The Processor — 94

 §4.8 Control Hazards
Branch Hazards
n If branch outcome determined in MEM (why?)
n Compute in EX
n Assume branch Not Taken => pc + 4, fall-through

“5”-1 =4, 3 bubble!

Flush 3
instructions
(Set control
values to 0),
or clear the
valid signal

Chapter 4 — The Processor — 95

Datapath and Control

1 2 3 4

4 5
32

Chapter 4 — The Processor — 96

Reducing Branch Delay
n Move hardware to determine outcome to ID stage (why?)
n Target address adder
n Register comparator
n The outcome is sent to the mux before PC at the same cycle (2nd cycle), but
takes effect in next cycle (3rd cycle)

n The earlier, the better

n Determine in ID => 1 bubble (3 – 1 = 2)
n Can it be moved before ID ?
n Example: branch taken
36: sub $10, $4, $8
40: beq $1, $3, 7 ;if taken, what addr?
44: and $12, $2, $5
48: or $13, $2, $6
52: add $14, $4, $2
56: slt $15, $6, $7
...
72: lw $4, 50($7) Chapter 4 — The Processor — 97
 Example: Branch Taken-clk 3

1 2

3
IF.Flush

3–1=2, 1 bubble

Flush: bubble inserted

here, Zero è nop Chapter 4 — The Processor — 98
Example: Branch Taken-clk 4

Chapter 4 — The Processor — 99

Delayed Branches
n If the branch hardware has been moved to the ID
stage, then we can eliminate all branch stalls
with delayed branches
n Always executing the next sequential instruction after
the branch instruction
n No flush for IF/ID
n The branch takes effect after that next instruction
n MIPS compiler moves an instruction to
immediately after the branch that is NOT
affected by the branch (a safe instruction)
thereby hiding the branch delay

Chapter 1 — Computer Abstractions and Technology — 100

 Delayed Branches

IF.Flush

No flush: current instr. will

be executed definitely Chapter 4 — The Processor — 101
Scheduling Branch Delay Slots
A. From before branch B. From branch target C. From fall through
add $1,$2,$3 add $1,$2,$3
sub $4,$5,$6
if $2=0 then if $1=0 then
delay slot delay slot
add $1,$2,$3
if $1=0 then
delay slot sub $4,$5,$6
becomes becomes becomes
add $1,$2,$3
if $2=0 then if $1=0 then
add $1,$2,$3 sub $4,$5,$6
add $1,$2,$3
if $1=0 then
sub $4,$5,$6

Chapter 1 — Computer Abstractions and Technology — 102

Data Hazards for Branches
n If a comparison register is a destination of 2nd or
3rd preceding ALU instruction

add $1, $2, $3 IF ID EX MEM WB

add $4, $5, $6 IF ID EX MEM WB

… IF ID EX MEM WB

beq $1, $4, target IF ID EX MEM WB

n Can resolve using forwarding

n 3 (InstrDistance(1st add, beq)) ≥ 2 (4 (MEM) - 2 (ID)), no stall
n 2 (InstrDistance(2nd add, beq)) ≥ 2 (4 (MEM) - 2 (ID)), no stall
Chapter 4 — The Processor — 103
Data Hazards for Branches
n If a comparison register is a destination of
immediately preceding load instruction
n Need 2 stall cycles
n 1 (InstrDistance(lw, beq)) < 3 (5 (WB) - 2 (ID)), 2 stall

lw $1, addr IF ID EX MEM WB

beq stalled IF ID

beq stalled ID

beq $1, $0, target ID EX MEM WB

Chapter 4 — The Processor — 104

Data Hazards for Branches
n If a comparison register is a destination of preceding ALU
instruction or 2nd preceding load instruction
n Need 1 stall cycle
n 2 (InstrDistance(lw, beq)) < 3 (5 (WB) - 2 (ID)), 3 - 2 = 1 stall
1 (InstrDistance(add, beq)) < 2 (4 (MEM) - 2 (ID)), 2 - 1 = 1 stall

lw $1, addr IF ID EX MEM WB

add $4, $5, $6 IF ID EX MEM WB

beq stalled IF ID

beq $1, $4, target ID EX MEM WB

Chapter 4 — The Processor — 105

Dynamic Branch Prediction
n In deeper and superscalar pipelines, branch
penalty is more significant
n Calculate branch outcome in a later pipeline stage
n The earlier, the better è extra hardware è guess
n Use dynamic prediction
n Normally in 1st stage (IF)
n Prediction in earlier stage and verification in outcome
calculating stage
n Even with predictor, still need to calculate the target
address
n Where in MIPS? ID stage: read register for calculation
n 1-cycle penalty for a taken branch: address used in IF stage
n 3–1=2
Chapter 4 — The Processor — 106
Dynamic Branch Prediction
n Branch prediction buffer (branch history table)
n Stores outcome (taken/not taken)
n Indexed by recent branch instruction addresses
n Normally, by the lower portion of the branch address
n To execute a branch
n Check table, expect the same outcome
n Start fetching from fall-through or target
n If wrong, flush pipeline and flip prediction
n Where to verify in MIPS? (ID stage ?)
n Can calculate the target address in a later stage
n If use branch prediction, no need for delayed branch
Chapter 4 — The Processor — 107
1-Bit Predictor
n Inner loop branches mispredicted twice!
outer: …
…
inner: …
…
beq …, …, inner
…
beq …, …, outer

n Mispredict as taken on last iteration of inner loop

n The current state is T !
n Then mispredict as not taken on first iteration of
inner loop next time around
n The current state is NT !

Chapter 4 — The Processor — 108

2-Bit Predictor
n Only change prediction on two successive
mispredictions
n Mispredicted only once
n Mispredict as taken on last iteration of inner loop

3 2

0 1

Chapter 4 — The Processor — 109

Branch Target Buffer
n Cache of target addresses
n C.f. store outcome in branch prediction/history
buffer
n Indexed by PC when instruction fetched
n If hit and instruction is branch predicted taken,
can fetch target immediately
n Can be done in IF stage (why?)
n No penalty if prediction is correct
n How about the penalty if wrong?
n Depends on where to compute the outcome
Chapter 4 — The Processor — 110
The Final Datapath and Control
Load-Use Hazard

Branch Hazard

Chapter 1 — Computer Abstractions and Technology — 111

 §4.9 Exceptions
Exceptions and Interrupts
n “Unexpected” events requiring change
in flow of control
n Different ISAs use the terms differently
n Normally, two types
n Exception/Trap: arises within the CPU
n E.g., undefined opcode, overflow, syscall, …
n Interrupt: from external devices
n E.g., I/O controller
n In IA-64, interruption = exception + interrupt
n Dealing with them without sacrificing
performance is hard
Chapter 4 — The Processor — 112
 31 26 25 21 20 16 15 11 10 6 5 0

ISA and Exception

SPECIAL rs rt rd 0 ADDU
000000 00000 100001
6 5 5 5 5 6

ADD
Format: ADDU rd, rs, rt
Add Word
MIPS I
n Some languages
31
(e.g.,
Purpose:
SPECIAL
C) ignore
26 To
11 10
0
overflow
25 add 32-bit
6 5 21 integers.
ADD
0 20 16 15

n Use 0MIPS
0 0 0 0 0 addu, addiu, subu instructions
Description: rs + rt
rd ← rs rt rd
00000 100000
The 32-bit word value in GPR rt is added to the 32-bit value in GPR rs and the 32-bit
6 5 5 5 5 6
n Other languages (e.g., Ada, Fortran) require raising an
arithmetic result is placed into GPR rd.
No Integer Overflow exception occurs under any circumstances.
exception
Format:
Restrictions:
Purpose:
ADD rd, rs, rt
To add 32-bit integers. If overflow occurs, then trap.
MIPS I

n Use MIPS rdadd,

Description: ← rs
values (bits 63..31
addi, sub instructions
On 64-bit processors, if either GPR rt or GPR rs do not contain sign-extended 32-bit
+ rt then the result of the operation is undefined.
equal),
The 32-bit word value in GPR rt is added to the 32-bit value in GPR rs to produce a
Operation:
32-bit result. If the addition results in 32-bit 2’s complement arithmetic overflow then
ifthe
(NotWordValue(GPR[rs]) ormodified
destination register is not NotWordValue(GPR[rt])) then UndefinedResult()
and an Integer Overflow endif
exception occurs. If it
temp ←GPR[rs] + GPR[rt]
does not overflow, the 32-bit result is placed into GPR rd.
addu GPR[rd]← sign_extend(temp31..0)
Restrictions:
Exceptions:
On 64-bit processors, if either GPR rt or GPR rs do not contain sign-extended 32-bit
None
values (bits 63..31 equal), then the result of the operation is undefined.
Programming Notes:
Operation:
The term “unsigned” in the instruction name is a misnomer; this operation is 32-bit
if (NotWordValue(GPR[rs])
modulo arithmetic that doesornot
NotWordValue(GPR[rt])) then UndefinedResult()
trap on overflow. It is appropriate endif
for arithmetic
temp ←GPR[rs]
which + GPR[rt]
is not signed, such as address arithmetic, or integer arithmetic environments
if (32_bit_arithmetic_overflow)
that ignore overflow, such as “C”then
language arithmetic.
add else
SignalException(IntegerOverflow)

GPR[rd] ←sign_extend(temp31..0)
endif
Exceptions:
Integer Overflow
Programming Notes:
Chapter
ADDU performs the same arithmetic operation but, does 3 overflow.
not trap on — Arithmetic for Computers — 113
Handling Exceptions
n In MIPS, exceptions managed by a
System Control Coprocessor (CP0)
n CP0 provides the processor control, memory
management, and exception handling
functions
n C.f. FP is coprocessor 1 (CP1)
n mfc0 (move from coprocessor 0’s reg)
instruction can retrieve EPC value, to return
after corrective action

Chapter 4 — The Processor — 114

Handling Exceptions
n For the OS to handle the exception, HW
n Save PC of offending (or interrupted)
instruction
n In MIPS: Exception Program Counter (EPC)
n Save indication of the problem
n In MIPS: using status register – Cause Register
n We’ll assume 1-bit
n 0: undefined instruction
n 1: arithmetic overflow
n Jump to predefined handler (single entry
point) at 8000 0180hex

Chapter 4 — The Processor — 115

An Alternative Mechanism
n Vectored Interruption
n Handler address determined by the cause
n Normally by hardware
n Example:
n Undefined opcode: C000 0000
n Overflow: C000 0020
n …: C000 0040
n Instructions at handler address either
n Deal with the exception, or
n Jump to real handler

Chapter 4 — The Processor — 116

Handler Actions
n Read cause, and transfer to relevant
handler
n Determine action required
n If restartable
n Take corrective action
n Use EPC to return to program
n Otherwise
n Terminate program
n Report error using EPC, cause, …

Chapter 4 — The Processor — 117

Exceptions in a Pipeline
n Another type of control hazard
n Consider overflow on add in EX stage
add $1, $2, $1
n Prevent $1 from being clobbered

n Complete preceding instructions

n Flush add (current) and subsequent instructions

n Set Cause and EPC register values

n Transfer control to handler (how?)

n Similar to mispredicted branch

n Use much of the same hardware

Chapter 4 — The Processor — 118

 Pipeline with Exceptions
instr. 3 instr. 2 instr. 1

Load-Use Hazard

exception
address

IF.Flush
Flush to zero => nop
Chapter 4 — The Processor — 119
Exception Properties
n Restartable exceptions
n Handler executes, then refetched and
executed this instruction from scratch
n In IA-64
n Exception: returns to current instruction
n Interrupt: returns to next instruction
n PC saved in EPC register
n Identifies causing instruction
n In MIPS, actually PC + 4 is saved (why ?)
n SW handler must adjust

Chapter 4 — The Processor — 120

Exception Example
n Exception on add in
40 sub $11, $2, $4
44 and $12, $2, $5
48 or $13, $2, $6
4C add $1, $2, $1
50 slt $15, $6, $7
54 lw $16, 50($7)
…
n Handler
80000180 sw $25, 1000($0)
80000184 sw $26, 1004($0)
…

Chapter 4 — The Processor — 121

 Exception Example

generated
by HW

50, why? PC = 4C
Chapter 4 — The Processor — 122
 Exception Example

handler’s instr. preceding instr.

Chapter 4 — The Processor — 123

Multiple Exceptions
n Pipelining overlaps multiple instructions
n Could have multiple exceptions at the same time in
different pipeline stages
n Simple approach: deal with exception from
earliest instruction
n Flush subsequent instructions
n “Precise” exceptions
n In complex pipelines
n Multiple instructions issued per cycle
n Out-of-order completion
n Maintaining precise exceptions is difficult!

Chapter 4 — The Processor — 124

Imprecise Exceptions
n Just stop pipeline and save state
n Including exception cause(s)
n Let the software handler work out
n Which instruction(s) had exceptions
n Which to complete or flush
n May require “manual” completion
n Simplifies hardware, but more complex handler
software
n Not feasible for complex multiple-issue
out-of-order pipelines

Chapter 4 — The Processor — 125

 §4.10 Parallelism and Advanced Instruction Level Parallelism
Instruction-Level Parallelism (ILP)
n Pipelining: executing multiple instructions
in parallel
n To increase ILP ⇒ exploit parallelism
n Deeper pipeline (temporal parallelism)
n Less work per stage ⇒ shorter clock cycle
n More penalty in control hazard and interruption
n Multiple function units (spatial parallelism)
n Replicate resource, multiple issue
n Multiple pipelines
n Replicate pipelines
n Spatial parallelism + temporal parallelism
Chapter 4 — The Processor — 126
Multiple Issue
n Start multiple instructions per clock cycle
n Instructions Per Cycle (IPC)
n CPI < 1, so use IPC
n C.f. CPI in single pipeline
n E.g., 4GHz 4-way multiple-issue
16 BIPS, peak CPI = 0.25, peak IPC = 4
n But dependencies reduce this in practice
n Structure, data, control hazard

Chapter 4 — The Processor — 127

Multiple Issue
n Static multiple issue
n Compiler groups instructions to be issued together
n Packages them into “issue packets”
n Compiler detects dependencies and avoids hazards
n Dynamic multiple issue
n CPU examines instruction stream and chooses
instructions to issue each cycle
n Compiler can help by reordering instructions
n CPU resolves hazards using advanced techniques at
runtime
n Hybrid way: SW/HW synergy, e.g. IA-64

Chapter 4 — The Processor — 128

Speculation
n To improve performance
n Exploit parallelism
n Sole ILP è ILP, DLP, TLP, RLP
n Use prediction or speculation è ILP
n “Guess” what to do with an instruction
n Start operation as early as possible
n Check whether guess was right
n If so, complete the operation
n If not, roll-back and do the right thing

Chapter 4 — The Processor — 129

Speculation
n Common to static and dynamic multiple
issue
n Examples
n Speculate on branch outcome
n Roll back if path taken is different è flush and
refetch
n Speculate on load
n Roll back if location is updated or exception occurs
n E.g., IA-64 data speculation and control
speculation

Chapter 4 — The Processor — 130

Compiler/Hardware Speculation
n Compiler can reorder instructions
n E.g., move load before branch
n Should include “fix-up” instructions to recover from
incorrect guess
n Hardware can look ahead for instructions to
execute
n Buffer results until it determines they are actually
needed
n Flush buffers on incorrect speculation
n Energy saving?

Chapter 4 — The Processor — 131

Speculation and Exceptions
n What if exception occurs on a
speculatively executed instruction?
n E.g., speculative load before null-pointer
check
n Static speculation
n Can add ISA support for deferring exceptions
n Dynamic speculation
n Can buffer/defer exceptions until instruction
completion (which may not occur)

Chapter 4 — The Processor — 132

Static Multiple Issue
n Compiler groups instructions into “issue
packets”
n Group of instructions that can be issued on a
single cycle ⇒ no dependencies
n Determined by pipeline resources required
n Think of an issue packet as a very long
instruction
n Specifies multiple concurrent operations
n ⇒ Very Long Instruction Word (VLIW)

Chapter 4 — The Processor — 133

Scheduling Static Multiple Issue
n Compiler must remove some/all hazards
n Reorder instructions into issue packets
n No dependencies within a packet
n Possibly some dependencies between
packets
n Varies between ISAs; compiler must know !
n Pad with nop if necessary
n May increase instruction count significantly

Chapter 4 — The Processor — 134

MIPS with Static Dual Issue
n Two-issue packets: two pipelines
n One ALU/branch instruction
n One load/store instruction
n 64-bit aligned (2 instruction word)
n ALU/branch first, then load/store
n In order to simplify the decoding and instruction issue
n Pad an unused instruction slot with nop
Address Instruction type Pipeline Stages
n ALU/branch IF ID EX MEM WB
n+4 Load/store IF ID EX MEM WB
n+8 ALU/branch IF ID EX MEM WB
n + 12 Load/store IF ID EX MEM WB
n + 16 ALU/branch IF ID EX MEM WB
n + 20 Load/store IF ID EX MEM WB
Chapter 4 — The Processor — 135
MIPS with Static Dual Issue

extra RF port

Load/Store

Chapter 4 — The Processor — 136

Hazards in the Dual-Issue MIPS
n More instructions executing in parallel
n EX data hazard
n Forwarding avoided stalls with single-issue
n Now can’t use ALU result in load/store in same packet
add $t0, $s0, $s1
load $s2, 0($t0)
n Complier avoids all dependencies within a packet
n Split into two packets, a stall
n Load-use hazard
n Still one cycle use latency, but affects two instructions
n More aggressive scheduling required

Chapter 4 — The Processor — 137

Scheduling Example
n Schedule this for dual-issue MIPS
Loop: lw $t0, 0($s1) # $t0=array element
addu $t0, $t0, $s2 # add scalar in $s2
sw $t0, 0($s1) # store result
addi $s1, $s1,–4 # decrement pointer
bne $s1, $zero, Loop # branch $s1!=0

ALU/branch Load/store cycle

Loop: nop lw $t0, 0($s1) 1
addi $s1, $s1,–4 nop 2
addu $t0, $t0, $s2 nop 3
bne $s1, $zero, Loop sw $t0, 4($s1) 4

n IPC = 5/4 = 1.25 (cf. peak IPC = 2)

Chapter 4 — The Processor — 138
Loop Unrolling
n Replicate loop body to expose more parallelism
n Reduces loop-control overhead
n Use different registers per replication
n Called “register renaming”
n Avoid loop-carried “anti-dependencies”
n Store (r) followed by a load (w) of the same register (WAR)
n Aka “name dependence”
n Reuse of a register name

n Three cases of dependency

n True (data) dependence
n Anti-dependence
n Output dependence
Chapter 4 — The Processor — 139
Loop Unrolling Example
ALU/branch Load/store cycle
Loop: addi $s1, $s1,–16 lw $t0, 0($s1) 1
nop lw $t1, 12($s1) 2
addu $t0, $t0, $s2 lw $t2, 8($s1) 3
addu $t1, $t1, $s2 lw $t3, 4($s1) 4
addu $t2, $t2, $s2 sw $t0, 16($s1) 5
addu $t3, $t4, $s2 sw $t1, 12($s1) 6
nop sw $t2, 8($s1) 7
bne $s1, $zero, Loop sw $t3, 4($s1) 8

n IPC = 14/8 = 1.75

n Closer to 2, but at cost of registers and code size

Chapter 4 — The Processor — 140

Dynamic Multiple Issue
n “Superscalar” processors: multiple
pipelines
n CPU decides whether to issue 0, 1, 2, …
each cycle
n Issue criterion
n Avoid structural and data hazards
n Must in-order issue!
n Code semantics ensured by the CPU
n Avoids the need for compiler scheduling
n Though it may still help
Chapter 4 — The Processor — 141
Dynamic Pipeline Scheduling
n Allow the CPU to execute instructions out
of order to avoid stalls
n But commit result to registers in order
n Example
lw $t0, 20($s2)
addu $t1, $t0, $t2
sub $s4, $s4, $t3
slti $t5, $s4, 20
n Can execute sub while addu is waiting for lw

Chapter 4 — The Processor — 142

 Dynamically Scheduled CPU
Preserves
dependencies

Hold pending
operands

Results also sent

to any waiting
reservation
stations

Reorders buffer for

register writes
Can supply
operands for
issued instructions

Chapter 4 — The Processor — 143

Register Renaming
n Reservation stations and reorder buffer
effectively provide register renaming
n On instruction issue to reservation station
n If operand is available in register file or reorder
buffer
n Copied to reservation station
n No longer required in the register; can be
overwritten
n If operand is not yet available
n It will be provided to the reservation station by a
function unit
n Register update may not be required
Chapter 4 — The Processor — 144
Speculation
n Predict branch and continue issuing
n Don’t commit until branch outcome
determined
n Load speculation
n Advantage: avoid load and cache miss delay
n Predict the effective address
n Predict loaded value
n Load before completing outstanding stores
n Bypass stored values to load unit
n Don’t commit load until speculation cleared

Chapter 4 — The Processor — 145

Why Do Dynamic Scheduling?
n Why not just let the compiler schedule
code?
n Not all stalls are predicable
n E.g., cache misses
n Can’t always schedule around branches
n Branch outcome is dynamically determined
n Different implementations of an ISA have
different latencies and hazards

Chapter 4 — The Processor — 146

Does Multiple Issue Work?
The BIG Picture

n Yes, but not as much as we’d like

n Programs have real dependencies that limit ILP
n Some dependencies are hard to eliminate
n E.g., pointer aliasing
n Some parallelism is hard to expose
n Limited window size during instruction issue
n Memory delays and limited bandwidth
n Hard to keep pipelines full
n Speculation can help if done well
Chapter 4 — The Processor — 147
Power Efficiency
n Complexity of dynamic scheduling and
speculations requires power
n Multiple simpler cores may be better
Microprocessor Year Clock Rate Pipeline Issue Out-of-order/ Cores Power
Stages width Speculation
i486 1989 25MHz 5 1 No 1 5W
Pentium 1993 66MHz 5 2 No 1 10W
Pentium Pro 1997 200MHz 10 3 Yes 1 29W
P4 Willamette 2001 2000MHz 22 3 Yes 1 75W
P4 Prescott 2004 3600MHz 31 3 Yes 1 103W
Core 2006 2930MHz 14 4 Yes 2 75W
UltraSparc III 2003 1950MHz 14 4 No 1 90W
UltraSparc T1 2005 1200MHz 6 1 No 8 70W

Chapter 4 — The Processor — 148

 §4.11 Real Stuff: The AMD Opteron X4 (Barcelona) Pipeline
The Opteron X4 Microarchitecture

72 physical
registers

Chapter 4 — The Processor — 149

The Opteron X4 Pipeline Flow
n For integer operations

n FP is 5 stages longer
n Up to 106 RISC-ops in progress
n Bottlenecks
n Complex instructions with long dependencies
n Branch mispredictions
n Memory access delays

Chapter 4 — The Processor — 150

 §4.13 Fallacies and Pitfalls
Fallacies
n Pipelining is easy (!)
n The basic idea is easy
n The devil is in the details
n E.g., detecting data hazards
n Pipelining ideas can be implemented
independent of technology
n So why haven’t we always done pipelining?
n More transistors make more advanced techniques
feasible
n Pipeline-related ISA design needs to take account of
technology trends
n E.g., predicated instructions

Chapter 4 — The Processor — 151

Pitfalls
n Failure to consider instruction set design
can adversely impact pipelining
n E.g., complex instruction sets (VAX, IA-32)
n Significant overhead to make pipelining work
n IA-32 micro-op approach
n E.g., complex addressing modes
n Register update side effects, memory indirection

Chapter 4 — The Processor — 152

 §4.14 Concluding Remarks
Concluding Remarks
n ISA influences design of datapath and control
n Datapath and control influence design of ISA
n Pipelining improves instruction throughput
using temporal parallelism
n More instructions completed per second
n Latency for each instruction not reduced
n Hazards: structural, data, control
n Multiple issue and dynamic scheduling (ILP)
n Dependencies limit achievable parallelism
n Complexity leads to the power wall

Chapter 4 — The Processor — 153