American International University – Bangladesh (AIUB)

Faculty of Engineering
Department of CSE, EEE, and CoE
EEE3102 Digital Logic and Circuits LAB
PROJECT PROPOSAL FORM
SEMESTER: Fall 2023-2024
PROJECT TITLE: 2 MARKS (must be related to digital logic and circuits. Both hardware implementation
and simulation must be shown by the end of the semester. However, the proposal form should be
submitted within the next two weeks from now on.)
Survey to develop a process for complex engineering problems with a wide
range of conflicting requirements (use pie chart): 5 MARKS
AIMS AND OBJECTIVES OF THE PROJECT: 3 MARKS
EXPERIMENTAL BLOCK DIAGRAM: 4 MARKS
PROJECT TIMELINE (GANTT CHART): 4 MARKS
REFERENCES: (only published paper-based references are allowed with the IEEE format, don’t use you-tube,
Wikipedia, or any random website for references): 2 marks
Sample for the conference paper:
[1] M. H. Bhuyan and Q. D. M. Khosru, “Linear Asymmetric Pocket Profile Based Pinch Off Voltage Model for Nano
Scale n-MOSFET,” Proceedings of the IEEE sponsored International Conference on Electrical, Computer and
Communication Engineering (ICECCE2017), organized by the Chittagong University of Engineering and Technology
(CUET), Cox’s Bazar, Bangladesh, 16-18 February 2017, pp. 28-32.

© Department of EEE, Faculty of Engineering, American International University – Bangladesh (AIUB) 1

FACULTY USE ONLY
COMMENTS BY THE COURSE TEACHER:

COURSE TEACHER’S NAME COURSE TEACHER’S SIGNATURE DATE

© Department of EEE, Faculty of Engineering, American International University – Bangladesh (AIUB) 2

GROUP MEMBERS
(Maximum 5 students are permitted to carry out a single Project. However, depending on the capability of the students,
4 students may be allowed but not less than that)

NAME: ……………………………………………… NAME: ………………………………………………

ID……………………………… ID………………………………

PROGRAM: EEE/COE/CSE PROGRAM: EEE/COE/CSE

EMAIL: EMAIL:

NAME: ……………………………………………… NAME: ………………………………………………

ID……………………………… ID………………………………

PROGRAM: EEE/COE/CSE PROGRAM: EEE/COE/CSE

EMAIL: EMAIL:

NAME: ……………………………………………… NAME: ………………………………………………

ID……………………………… ID………………………………

PROGRAM: EEE/COE/CSE PROGRAM: EEE/COE/CSE

EMAIL: EMAIL:

REMARKS (for OFFICE use only)

© Department of EEE, Faculty of Engineering, American International University – Bangladesh (AIUB) 3

 Course Outcome Mapping with the Course Project Proposal:
Assessed Program BNQF Assessment
COs/CLOs Details K P A
Outcome Indicator Indicator Techniques

CO1 Apply proper information and concepts of different logic P1,

gates, digital ICs, transistors, and timers to implement P2, Course Project
K3 P.a.3.C3 FS.1
logical circuits considering a wide range of conflicting P6 Proposal Form
requirements.

Course Name: Digital Logic and Circuits Lab Course Code: EEE 3102
Semester: Spring 2022-2023 Section:
Faculty Member:

Course Project Title:

Project Group No.

SL Student ID # Student Name Obtained Marks

1.
2.
3.
4.
5.
6.

Assessment Materials and Marks Allocation:

COs Assessment Materials POIs Marks
CO1 Course Project Proposal form P.a.3.C3 20

Assessment Rubrics
No
Excellent Proficient Good Acceptable Unacceptable Secured
COs-POIs Response
[17-20] [13-16] [9-12] [5-8] [1-4] Marks
[0]
The survey developed
The survey developed The survey developed
The survey developed as a process for
as a process for as a process for
as a process for complex engineering
complex engineering complex engineering
The survey developed as complex engineering problems considering
problems considering a problems considering a
a process for complex problems considering a a wide range of
wide range of wide range of
engineering problems wide range of conflicting
conflicting conflicting
considering a wide conflicting requirements but the
requirements but the requirements but the
CO1 range of conflicting requirements but the conflicting No
conflicting conflicting
P.a.3.C3 requirements and conflicting requirements are Response
requirements are less in requirements are very
implementation process requirements are less in fewer in number and
number and few in number and
is clear and challenging number and implementation
implementation process implementation process
for future project implementation process process is not so clear
is not so clear but is not clear at all and
implementation. is clear and challenging and seems less
seems challenging for seems impractical for
for future project challenging for future
future project future project
implementation. project
implementation. implementation.
implementation.
Total
Comments marks
(20)

© Department of EEE, Faculty of Engineering, American International University – Bangladesh (AIUB) 4