2018 (( 24th INTERNATIONAL WORKSHOP September 2018, Stockholm / SE

on Thermal Investigations of ICs and Systems )) www.therminic2018.eu

Thermal Modeling and Experimental Validation of Heat Sink Design

for Passive Cooling of BEOL IC Structures
Assaad El Helou1, Peter E. Raad1,2, Dhishan Kande3, Archana Venugopal3
1
Mechanical Engineering Department, Southern Methodist University, Dallas, Texas 75275, USA
2
TMX Scientific, Inc., Richardson, Texas 75081, USA
3
Texas Instruments Incorporated, Dallas, Texas 75243, USA

* Corresponding Author: +1 (214) 768-4602 [email protected]

Abstract
Reducing the operating temperature of microelectronic devices is crucial for increasing reliability and extending lifetime. This
study presents a proposed embedded heat sink design for passive cooling of BEOL interconnects and IC structures. Sample
devices are fabricated and tested using thermoreflectance thermography to characterize the thermal response of the devices
and assess the added cooling effects of the heat structures. An experimentally validated thermal model is built to analyse the
thermal performance of the device and extract the thermal parameters of the structure.

1 Introduction
Temperature is a critical factor that affects the reliability of
microelectronic devices and interconnects by accelerating
electromigration failures. Electromigration (EM) is the
material transport that is associated with high electric current
densities. Subject to EM failure, Black’s equation
exponentially relates the lifetime of a device to the operating
temperature and shows that a 5°C rise causes a 30% reduction
in failure time [1].
Moreover, large temperature gradients in devices cause
thermal stresses that may lead to epitaxial, structural and
other mechanical device failures [2]. Thus, to reduce peak
operating temperatures, passive cooling technologies, such as Figure 1: Schematics of micro-resistor designs: (Left)
heat spreaders and thermal vias, have been implemented to without heat sink and (Right) with heat sink embedded in the
reduce thermal resistances in the microelectronic structure oxide layer. Top figure shows narrow heat sink design while
and facilitate the heat dissipation from the device to the sink. lower figure shows extended heat sink design (only center
resistor is active)
The thermal performance of a heat sink design is not just
assessed by its effectiveness in reducing the peak operating underlying arrays of AlCu and Polysilicon that extend to the
temperature but in increasing the current density allowance width of the device in one set of samples, and to four widths
for a certain interconnect. By increasing heat dissipation from in another set. The two designs will make it possible to assess
a device, the allowable current densities through an the heat spreading effectiveness and the enhancement of
interconnect increases for a certain tolerable temperature rise. transverse as well as through-plane heat conduction within
This thermally conscious design would utilize less fabrication the oxide layer.
material and would reduce the overall fabrication costs.
2.2 Thermal Model
2 Methodology
The model shown in Figure 2 is built in the TMX T°Solver®
The study presented in this paper assesses the thermal computational software, which is specifically designed for IC
performance of a proposed heat spreader design for BEOL thermal modelling [3]. The simulation software solves the full
interconnects. An experimentally validated thermal model is transient thermal conduction problem using an ultra-fast
built to understand the thermal properties of the heat sink and engine with a self-adaptive multigrid meshing that handles
the effects of different design parameters. large spatial and temporal gradients.
2.1 Sample Devices
The measured samples are micro-resistor devices fabricated
on an oxide layer with an embedded heat sink design as
shown in Figure 1. The heat sink design consists of two

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Figure 2: T°Solver thermal models showing resistor and

underlying heat sink structure in narrow configuration (Left)
and wide configuration (Right)

The conductive layers of the heat sink arrays are added to the
model and placed within the oxide layer beneath the resistor.
Interfacial effects are considered through a defined
intermediate oxide layer with an effective conductivity to
match the thermal conductance of the device under test.
2.3 Temperature Mapping
The model is validated with experimental temperature
mapping of the activated micro-devices. The temperature rise
is compared between the different configuration of devices
with and without the embedded heat sink. The devices are Figure 3: Thermal simulations of activated devices (Left)
activated at several power levels and the effective thermal compared to experimental temperature maps (Right) of
resistance of the stack is obtained from the temperature- device with narrow heat sink (Top) and that of wide heat
power relation and compared for the different configurations. sink (Bottom)
The temperature maps are obtained using the TMX
T°Imager® thermography system which uses a CCD based
͵ͲͲ
thermoreflectance method to measure temperature rise, as
‡’‡”ƒ–—”‡‹•‡ȋιȌ

described in [4]. The method is a non-contact, non- ʹͷͲ

destructive method suitable for sub-micron resolution T = 126.8 Q
thermal imaging of microelectronics. ʹͲͲ
‘ ‡ƒ–‹
ͳͷͲ
3 Results
ͳͲͲ
Thermal simulations for the different configurations are run T= 115.3 Q
at heat generation rates that match the Joule heating and ͷͲ
activation power levels used experimentally. The temperature ƒ””‘™ ‡ƒ–‹
rise in a central region inside the resistor is extracted for Ͳ
different activation power levels to calculate the effective ͲǤͲ ͲǤͷ ͳǤͲ ͳǤͷ ʹǤͲ
thermal resistance of the stack. The obtained temperature ‡ƒ–‹‰ƒ–‡ȋȀρȌ
slices are also compared to the temperature maps obtained
experimentally at the corresponding regions of the devices. ͵ͲͲ
‡’‡”ƒ–—”‡‹•‡ȋιȌ

The comparison of the temperature maps at a given activation

level is shown in Figure 3. ʹͷͲ  

The average temperature rise ȟܶ in a central region of the ʹͲͲ

resistor is plotted in Figure 4 against the heat generation rate ͳͷͲ
per unit length ܳԢ . The effective thermal resistance of the ‘ ‡ƒ–‹
stack ܴ௧௛ǡ௘௤ is extracted from a linear fit according to (1) ͳͲͲ
assuming the heat conduction equation reaches a quasi-steady T= 87.9 Q
ͷͲ
state. ‹†‡ ‡ƒ–‹
Ͳ
ᇱ
ܴ௧௛ǡ௘௤ ൌ ȟܶȀܳ  (1) ͲǤͲ ͲǤͷ ͳǤͲ ͳǤͷ ʹǤͲ
‡ƒ–‹‰ƒ–‡ȋȀρȌ
Figure 4: Temperature rise profile for device with narrow
heat sink (Top) and with wide heat sink (Bottom)

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Table 1: Effective Thermal Resistances and Cooling IEEE 61st (pp. 746–753). IEEE Publishing.
effectiveness of different device configurations doi:10.1109/ECTC.2011.5898596
Device ࡾᇱ࢚ࢎ ࢔࢕ࡴࡿ ࡾᇱ࢚ࢎ  with HS Cooling [3] P.E. Raad, J.S. Wilson, and D.C Price, “Adaptive
Config. ିଷ ିଷ Rate Modeling of the Transients of Submicron Integrated
ሺͳͲ ݉Ǥ ‫ܭ‬Ȁܹሻ ሺͳͲ ݉Ǥ ‫ܭ‬Ȁܹሻ
(%߂ܶȀܶ) Circuits,” IEEE Transactions on Components,
Packaging and Manufacturing Technology, 21.3 (1998):
Narrow 126.8 115.3 8.5 % 412-416
Heat Sink
[4] P.E Raad, P.L. Komarov, and M.A. Bettiati
Wide 117.0 87.9 30.2 % “Thermoreflectance Temperature Measurements for
Heat Sink Optically Emitting Devices,” Microelectronics Journal,
(2014) 45: 515-520

A summary of the thermal resistances and cooling effects of

the different configurations is presented in Table 1. The heat
sink designs show an appreciable improvement in the in-
plane heat conduction (reduction in thermal resistance) for
the wide heat sink which results in a 30% reduction in
operation temperature. The narrow heat sink design results in
a much lower cooling rate of around 8% showing that the
through-plane conduction is not improved as much. The
added AlCu and Poly layers have a higher thermal
conductivity than the replaced SiO2 but introduce additional
interface resistances when stacked in the oxide layer; which
offsets any gained reductions in material thermal resistance.
4 Conclusions
A full three-dimensional, transient simulation model has been
developed to assess the potential thermal improvements made
possible by embedding heat sink array designs in the back-
end-of-line structures used in commercial integrated circuits.
The computational model was validated with experimental
measurements using thermoreflectance temperature
measurements with deep submicron resolution. The results of
the matched studies show significant reductions in operating
peak temperatures. Now that this thermal model has been
developed, verified, and validated, it can be used to conduct
more general parametric studies to help identify designs that
optimize desirable thermal characteristics of stacked
structures.
Acknowledgements
AEH and PER would like to acknowledge the contributions
made by fab engineers and staff at Texas Instruments (TI) in
providing the sample devices used for testing and in giving
their expertise and insights to the project. They would also
like to thank TI for funding the research efforts at NETSL lab
in SMU.
Literature
[1] J.R. Black, “Electromigration—A Brief Survey and
Some Recent Results,” IEEE Transactions on Electron
Devices, 16.4 (1969): 338-47.
[2] M. Joydeep, J., Jung, M., Ryu, S., Huang, R., Lim, S.,
and Pan, D. (2011). A fast simulation framework for
full-chip thermo-mechanical stress and reliability
analysis of through-silicon-via based 3D ICs. Electronic
Components and Technology Conference (ECTC), 2011

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