8255:(Programmable Peripheral Interface)

Features:
• It is a programmable device.
• It has 24 I/O programmable pins like PA,PB,PC (3-8 pins).
• Improved dc driving capability

The 8255A is a general purpose programmable I/O device designed for use with any
microprocessors.
It consists of three 8-bit bidirectional I/O ports (24I/O lines) that can be configured
to meet different system I/O needs.
8255:(Programmable Peripheral Interface)
Pin Diagram
8255:(Programmable Peripheral Interface)
Function of pins:
• Data bus(D0 -D7 ): These are 8-bit bi-directional buses, connected to 8085 data bus
for transferring data.

• CS: This is Active Low signal. When it is low, then data is transfer from 8085.

• Read: This is Active Low signal, when it is Low read operation will be start.

• Write: This is Active Low signal, when it is Low Write operation will be start.

• Address (A0 -A1 ):This is used to select the ports. like this

A1 A0 Select
0 0 PA
0 1 PB
1 0 PC
1 1 Control reg.
8255:(Programmable Peripheral Interface)
Block Diagram
8255:(Programmable Peripheral Interface)
• The 8255 has 24 I/O pins divided into 3 groups of 8 pins each. The groups are
denoted by port A, port B and port C respectively. Every one of the ports can be
configured as either an input port or an output port.

•Advantage of this chip, that it can be operated in three different modes which are
basically not included in simple I/O interfacing; these different types of operation
extended the data transfer policies.
8255:(Programmable Peripheral Interface)
Data Bus Buffer
• It is a 8-bit bidirectional Data bus.
• Used to interface between 8255 data bus with system bus.
• The internal data bus and Outer pins D0-D7 pins are connected in internally.
• The direction of data buffer is decided by Read/Control Logic.

Read/Write Control Logic:

•This is getting the input signals from control bus and Address bus
•Control signal are RD and WR.
•Address signals are A0,A1,and CS.
•8255 operation is enabled or disabled by CS.
8255:(Programmable Peripheral Interface)
Group A and Group B control:
• Group A and B get the Control Signal from CPU and send the command to the
individual control blocks.
• Group A send the control signal to port A and Port C (Upper) PC7-PC4.
• Group B send the control signal to port B and Port C (Lower) PC3-PC0.

PORT A:
•This is a 8-bit buffered I/O latch.
•It can be programmed by mode 0 , mode 1, mode 2.

PORT B:
•This is a 8-bit buffer I/O latch.
•It can be programmed by mode 0 and mode 1.

PORT C:
•This is a 8-bit Unlatched buffer Input and an Output latch.
•It is splitted into two parts.
•It can be programmed by bit set/reset operation.
8255:(Programmable Peripheral Interface)
Operation modes:
BIT SET/RESET MODE:
•The PORT C can be Set or Reset by sending OUT instruction to the CONTROL
registers.
I/O MODES:
MODE 0
MODE1
MODE 2
8255:(Programmable Peripheral Interface)
I/O Port addressing:
8255:(Programmable Peripheral Interface)
Control Word register
8255:(Programmable Peripheral Interface)
Control Word register
8255:(Programmable Peripheral Interface)
Control Word register
• 8255A has 2 modes- Bit set/Reset (BSR)mode and I/O mode. The BSR mode is
used to set and reset the bits in port C. The I/O is further divided into 3 modes: Mode
0, Mode 1 and Mode 2.

• Using D7 bit, if D7 =0, port C operates in Bit set/reset modes.

• Using D7 bit, if D7 =1, bits D6-D0 determines I/O functions in various modes.

•There are three basic I/O modes of operation that can be selected by the system
software after properly sets the control word register format as per the requirements.
Mode 0 – Basic Input/ Output
Mode 1 – Strobe or Handshaking Input/ Output
Mode 2 – Bi-directional Bus
8255:(Programmable Peripheral Interface)
Control Word register
• In Mode 0 all ports (A, B and C) can be used as 8-bit I/O ports and configured by
the control word registers. When the RESET input goes “high” all ports will be set to
input mode and after revoked of this signal all ports remain in same mode until any
initialization established.

•In Mode 1 only Port A and B configured as I/O while the upper 4-bit of port C used
as strobe signal for port A and lower 4-bit of port C used as strobe signal for port B.

•Mode 2 is available only for port A while port B can be used as simple I/O mode
and bit’s of port C used as strobe signal. Except of these three modes of operation
8255A offers single Bit Set/ Reset (BSR) features of port bits, which is limited to
port C only. All of these operations are maintained by a 8-bit single register called
Control Word Register (CWR).

•Before using this PPI chip user must be initialize all of these 8 bit ports as input or
output with proper modes of operation according to the circuitry where it will be
placed. This initialization can be done by CWR register.
8255:(Programmable Peripheral Interface)
Control Word register
8255:(Programmable Peripheral Interface)
MODE 0: Simple Input or Output
In this mode, D7= 1 and ports A and B are used as two simple 8 bit ports and Port C
as two 4 bit ports(half port in C can be output/Input).

•Outputs are latched and input are not latched.

•Ports do not have handshake or interrupt capability.

•Disadvantage- In Mode-0, 8255A used as a receiver & transmitter to exchange the

data in between of microprocessor & input/output devices. But in this scheme
exchange data may be lost by the both of devices due to unknown timing of data
throwing in between them .
8255:(Programmable Peripheral Interface)
Example
8255:(Programmable Peripheral Interface)
Example
8255:(Programmable Peripheral Interface)
Example
8255:(Programmable Peripheral Interface)
Example
 BSR Mode

This mode is enabled by resetting the D7 bit =0 of control word register (CWR).

Any of the 8-bit of port C is selected by the combination of group of bits (D3, D2,
D1) as shown in fig.
 BSR Mode
Example
 Mode 1
Example
 Mode 1 (Input operations)
Figure shows the associated control
signals used for handshaking when
ports A and B are configured as input
ports.
Port A uses the upper three signals:
PC3, PC4, and PC5.
Port B uses the lower three signals PC2,
PC1, and PC0.
Mode 1 (Input operations)
Mode 1 (Input operations)
 Mode 1 (Input operations)
Let input device is
connected to port PA0
to PA7 and red box is
like 8 bit data which is
to be transferred to
MPC.. First strobe
signals(STB bar) is
made low then data is
transferred to input
device to 8255. Then
after data is with 8255
makes the IBF signals
as high ,also STB Bar
is made high. When
data is with 8255 , an
interrupt request is
generated by 8255, by
making INTR as high
 Mode 1 (Input operations)
Control and Status Word
 Mode 1 (Input operations)
Programming The 8255 in MODE1
 Mode 1 (Input operations)
Programming The 8255 in MODE1
Mode 1 (Output operations)
 Mode 1 (Output operations)
Programming The 8255 in MODE1
 Mode 1 (Output operations)
Programming The 8255 in MODE1
 Mode 1 (Output operations)
Control Status Word
 Mode 1
Illustration: An Application of the 8255A in the Handshake Mode (Mode 1)
 Mode 1
Illustration: An Application of the 8255A in the Handshake Mode (Mode 1)
 Mode 1
Illustration: An Application of the 8255A in the Handshake Mode (Mode 1)
 Mode 1
Illustration: An Application of the 8255A in the Handshake Mode (Mode 1)
 Mode 1
Illustration: An Application of the 8255A in the Handshake Mode (Mode 1)
 Mode 2
• This mode allows bidirectional data transfer over a single 8-bit data bus using
handshake signals.
• Only portA is used as a 8-bit bi-directional I/O bus.
•Handshaking signal for communication is provided by 5-bits of portC [PC3 to
PC7].
•PC0 to PC2 is used as a simple input or output, is set by mode-0 operation.
•PortB can be programmed either in mode-0 or mode-1 configuration with PC0-PC2
used as a handshaking signal where it is applicable.
• The data is sent by CPU through this port , when the peripheral request it.
Mode 2
Mode 2
 8279: Keyboard/Display Interface
WHY 8279???

What We Know,
• 8255 can be used in interfacing keyboards and displays.
•The disadvantages of this method of interfacing keyboard and display is that the
processor has to refresh the display and check the status of the keyboard
periodically using polling technique.
• Thus a considerable amount of CPU time is wasted, reducing the system
operating speed.
• Intel’s 8279 is a general purpose keyboard display controller that simultaneously
drives the display of a system and interfaces a keyboard with the CPU, leaving it
free for its routine task.
 8279: Keyboard/Display Interface
The 8279 is a 40-pin device with two major segments: keyboard and display.
The keyboard segment can be connected to a 64-contact key matrix.
Keyboard entries are denounced and stored in the internal FIFO memory; an
interrupt signal is generated with each entry.
The display segment can provide a 16 character scanned display interface with
such devices as LEDs. This segment has 16X8 R/W memory (RAM), which can be
used to read/write information for display purposes.
 8279: Keyboard/Display Interface
Features:
Simultaneous Keyboard and display operations
Scanned Keyboard mode
Scanned sensor mode
8-character keyboard FIFO
16-character display
8279: Block Diagram
 8279: Block Diagram
I/O Control and Data Buffers :
•The I/O control section controls the flow of data to/from the 8279
• The I/O section is enabled only if CS is low.
• The pins A0, RD and WR select the command, status or data read/write
operations carried out by the CPU with 8279.
• The data buffers interface the external bus of the system with internal bus of
8279.

Control and Timing Register and Timing Control :

• These registers store the keyboard and display modes and other operating
conditions programmed by CPU.
• The registers are written with A0=1 and WR=0. The Timing and control unit
controls the basic timings for the operation of the circuit.
• Scan counter divide down the operating frequency of 8279 to derive scan
keyboard and scan display frequencies.
 8279: Block Diagram
Scan Counter:
•The scan counter has two modes to scan the key matrix and refresh the display.
• In the encoded mode, the counter provides binary count that is to be externally
decoded to provide the scan lines for keyboard and display
• Four externally decoded scan lines may drive upto 16 displays.
• In the decode scan mode, the counter internally decodes the least significant 2 bits
and provides a decoded 1 out of 4 scan on SL0-SL3
• Four internally decoded scan lines may drive upto 4 displays.
• The keyboard and display both are in the same mode at a time.

Return Buffers and Keyboard Debounce and Control:

• This section scans for a key closure row wise. If a key closer is detected, the
keyboard debounce unit debounces the key entry (i.e. wait for 10 ms).
• After the debounce period, if the key continues to be detected, The code of key is
directly transferred to the sensor RAM along with SHIFT and CONTROL key
status.
 8279: Block Diagram
Display Address Registers and Display RAM :
• The display address register holds the address of the word currently being written
or read by the CPU to or from the display RAM.
• The contents of the registers are automatically updated by 8279 to accept the next
data entry by CPU.

FIFO/Sensor RAM and Status Logic:

In keyboard or strobed input mode, this block acts as 8-byte first-in-first-out
(FIFO) RAM.
• Each key code of the pressed key is entered in the order of the entry and in the
mean time read by the CPU, till the RAM become empty.
• The status logic generates an interrupt after each FIFO read operation till the
FIFO is empty.
In scanned sensor matrix mode, this unit acts as sensor RAM.
• Each row of the sensor RAM is loaded with the status of the corresponding row
of sensors in the matrix.
• If a sensor changes its state, the IRQ line goes high to interrupt the CPU.
 8279: Block Diagram
The block diagram has four major section:
Keyboard Section
Scan Section
Display Section and
MPU Interface
8279: Block Diagram
8279: Block Diagram
8279: Block Diagram
8279: Block Diagram
8279: Block Diagram
8279: Block Diagram
8279: Block Diagram
8279: Pin Diagram
8279: Pin Diagram
8279: Pin Diagram
8279: Pin Diagram
8279: Pin Diagram
8279: Pin Diagram
8279: Keyboard/Display Interface
8279: Keyboard/Display Interface
8279: Keyboard/Display Interface
8279: Keyboard/Display Interface
8279: Keyboard/Display Interface
8279: Keyboard/Display Interface
 8279: Keyboard/Display Interface
Scanned Keyboard Special Error Mode :

• This mode is valid only under the N-Key rollover mode.

• This mode is programmed using end interrupt / error mode set command.
• If during a single debounce period ( two keyboard scans ) two keys are found
pressed , this is considered a simultaneous depression and an error flag is set.
• This flag, if set, prevents further writing in FIFO but allows the generation of
further interrupts to the CPU for FIFO read.
• The error flag can be read by reading the FIFO status word. The error Flag is reset
by sending normal clear command with CF = 1.
 8279: Keyboard/Display Interface
Scanned Sensor Matrix :
• In this mode, a sensor array can be interfaced with 8279 using either encoded or
decoded scans. With encoded scan 8*8 sensor matrix or with decoded scan 4*8
sensor matrix can be interfaced.
• The sensor codes are stored in the CPU addressable sensor RAM.
• In the sensor matrix mode, the debounce logic is inhibited. The 8-byte FIFO
RAM now acts as 8 * 8 bit memory matrix.
• The status of the sensor switch matrix is fed directly to sensor RAM matrix. Thus
the sensor RAM bits contains the rowwise and column wise status of the sensors in
the sensor matrix.
• The IRQ line goes high, if any change in sensor value is detected at the end of a
sensor matrix scan or the sensor RAM has a previous entry to be read by the CPU.
• The IRQ line is reset by the first data read operation, if AI = 0,otherwise, by
issuing the end interrupt command. AI is a bit in read sensor RAM word.
 8279: Keyboard/Display Interface
Strobed input:
In this mode, if the control lines goes low, the data on return lines, is stored in the
FIFO byte by byte.
8279: Keyboard/Display Interface
 Command Words of 8279
All the command words or status words are written or read with A0 = 1 and CS =
0 to or from 8279.
 Command Words of 8279
All the command words or status words are written or read with A0 = 1 and CS =
0 to or from 8279.
 Command Words of 8279
B) Programmable clock :
• The clock for operation of 8279 is obtained by dividing the external clock input
signal by a programmable constant called prescaler.
• PPPPP is a 5-bit binary constant.
• The input frequency is divided by a decimal constant ranging from 2 to 31,
decided by the bits of an internal prescaler, PPPPP.
 Command Words of 8279
C) Read FIFO / Sensor RAM : The format of this command is given below.

• This word is written to set up 8279 for reading FIFO/ sensor RAM.
• In scanned keyboard mode, AI and AAA bits are of no use. The 8279 will
automatically drive data bus for each subsequent read, in the same sequence, in
which the data was entered.
• In sensor matrix mode, the bits AAA select one of the 8 rows of RAM.
• If AI flag is set, each successive read will be from the subsequent RAM location.
 Command Words of 8279
D) Read Display RAM :
This command enables a programmer to read the display RAM data.

• The CPU writes this command word to 8279 to prepare it for display RAM read
operation.
• AI is auto increment flag and AAAA, the 4-bit address points to the 16-byte
display RAM that is to be read.
• If AI=1, the address will be automatically, incremented after each read or write to
the Display RAM.
• The same address counter is used for reading and writing.
 Command Words of 8279
D) Read Display RAM :
This command enables a programmer to read the display RAM data.

• The CPU writes this command word to 8279 to prepare it for display RAM read
operation.
• AI is auto increment flag and AAAA, the 4-bit address points to the 16-byte
display RAM that is to be read.
• If AI=1, the address will be automatically, incremented after each read or write to
the Display RAM.
• The same address counter is used for reading and writing.
Write Display RAM :
This command enables a programmer to write the display RAM data.
 Command Words of 8279
F) Display Write Inhibit/Blanking :

• The IW ( inhibit write flag ) bits are used to mask the individual nibble.
• The output lines are divided into two nibbles ( OUTA0 – OUTA3 ) and (OUTB0
– OUTB3 ), those can be masked by setting the corresponding IW bit to 1.
• Once a nibble is masked by setting the corresponding IW bit to 1, the entry to
display RAM does not affect the nibble even though it may change the unmasked
nibble.
• The blank display bit flags (BL) are used for blanking A and B nibbles.
• D0, D2 corresponds to OUTB0 – OUTB3
• D1, D3 corresponds to OUTA0 - OUTA3 for blanking and masking.
• If the user wants to clear the display, blank (BL) bits are available for each nibble
as shown in format.
•Both BL bits will have to be cleared for blanking both the nibbles.
 Command Words of 8279
F) Clear Display RAM :

• CD2 must be 1 for enabling the clear display command.

• If CD2 = 0, the clear display command is invoked by setting CA(CLEAR ALL)
=1 and maintaining CD1, CD0 bits exactly same as above.
• If CF(CLEAR FIFO RAM STATUS) =1, FIFO status is cleared and IRQ line is
pulled down and the sensor RAM pointer is set to row 0.
•If CA=1, this combines the effect of CD and CF bits.
 Command Words of 8279
G) End Interrupt / Error mode Set :

• For the sensor matrix mode, this command lowers the IRQ line and enables
further writing into the RAM.
• Otherwise, if a change in sensor value is detected, IRQ goes high that inhibits
writing in the sensor RAM.
•For N-Key roll over mode, if the E bit is programmed to be ‘1’, the 8279 operates
in special Error mode
Command Words of 8279
8254 (8253)- Programmable interval timer
• It is software designed counters and timers.
•Widely used in clock driven digital circuits. With out timer there will not be proper
synchronization between two devices. So it is very useful chip.
•Also generates accurate time delays and can be used for real time clock, event
counter, digital one shot, square wave generator etc.
• The 8254 programmable Interval timer consists of three independent 16-bit and
used in any 6 modes.
•To operate a counter a 16-bit count is loaded in its register and on command, it
begins to decrement the count until it reaches 0. At the end of the count it generates
a pulse, which interrupts the processor.
•The count can count either in binary or BCD.
• In addition, 8254 count can be read by the MPU while counter is decrement but
8253 doesn’t have this feature.
8254 (8253)- Programmable interval timer
8254 vs 8253 Programmable interval timer
• The 8254 is upgraded version of 8253. They are pin compatible.
•Features are identical except
(i) 8254 operation frequency- DC to 8 MHz and 10Mhz for 8254-2, while for
8253 is 2 MHz.
(ii) 8254 has status read back command that can be latched the count and status of
the counter but 8253 does have it.
8254 (8253)- Programmable interval timer
Block Diagram
•It includes 3 counters 0,1,2, a
data bus, Read/write control logic
and a control register.
•Each counter has 2 input signals-
CLK, GATE and 1 output signal-
OUT.
• Control logic has 5 signals-
RD(bar), WR(Bar),CS(bar) and
address lines A0 and A1.
•In peripheral mode, RD (bar) and
WR(bar) are connected to
IOR(bar) and IOW(bar)
respectively. In memory mapped
I/O, , RD (bar) and WR(bar) are
connected to MEMR(bar) and
MEMW(bar) respectively.
8254 (8253)- Programmable interval timer
Block Diagram
•Data bus buffer- It is a
communication path between the
timer and the microprocessor. The
buffer is 8-bit and bidirectional. It
is connected to the data bus of the
microprocessor.
•The data bus buffer has three
basic functions,
(i). Programming the modes of
8253.
(ii). Loading the count value in
times
(iii).Reading the count value from
timers.
8254 (8253)- Programmable interval timer
Block Diagram
•CS(bar) : The chip select input is
used to enable the communicate
between 8253 and the
microprocessor by means of data
bus. A low an CS enables the data
bus buffers, while a high disables
the buffer.
•A0 & A1:- These two input lines
allow the microprocessor to
specify which one of the internal
register in the 8253 is going to be
used for the data transfer.
8254 (8253)- Programmable interval timer
8254 (8253)- Programmable interval timer
Control Word Register of 8254/8253

It is selected when A0 and A1= 1 .

It the accepts information from the data bus buffer and stores it in a register.
The information stored in then register controls the operation mode of each counter,
selection of binary or BCD counting and the loading of each counting and the
loading of each count register. This register can be written into, no read operation
of this content is available.
8254 (8253)- Programmable interval timer
Control Word Register of 8254/8253
8254 (8253)- Programmable interval timer
CLK, GATE, OUT
Each 16 counter has 2 input signals- CLK, GATE and 1 output signal- OUT.

•CLK- This clock input pin provides 16-bit times with the signal to causes the
times to decrement.
•GATE: The gate input pin is used to initiate or enable counting. The exact effect of
the gate signal depends on which of the six modes of operation is chosen.
•OUTPUT: The output pin provides an output from the timer. It actual use depends
on the mode of operation of the timer.
8254 (8253)- Programmable interval timer
Programming the 8254
8254 (8253)- Programmable interval timer
Programming the 8254
8254 (8253)- Programmable interval timer
MODES:
8254 (8253)- Programmable interval timer
MODES:
8254 (8253)- Programmable interval timer
MODES:
8254 (8253)- Programmable interval timer
MODES:
8254 (8253)- Programmable interval timer
MODES:
8254 (8253)- Programmable interval timer
MODES:
8254 (8253)- Programmable interval timer
READ BACK Command
8254 (8253)- Programmable interval timer
READ BACK Command
 Interfacing Data Converters
Digital to Analog Converters (DAC)
Digital to analog converters can be broadly classified in three categories: current
output, voltage output and multiplying type.
The current output DAC provides current as the output signal.
The voltage output DAC internally converts the current signal into the voltage
signal.
The voltage output is slower than the current output DAC because of the delay in
converting the current signal into the voltage signal.
The multiplying DAC is similar to the other two types except its iutput represents
the product of the input signal and the reference source, and the product is linear
over a broad range.
 Digital to Analog Converters (DAC)
Block Diagram
 Digital to Analog Converters (DAC)
Block Diagram
 Digital to Analog Converters (DAC)
Example
 Digital to Analog Converters (DAC)
DAC Circuits

For the input = 1112, the output is equal to either 7/8 mA

or 7/8 V, representing the D/A conversion process
 Digital to Analog Converters (DAC)
DAC Circuits
Vin is replaced by Vref, which can be turned on or off by the switches.
The output current Io can be generalized for any number of bits as
 Digital to Analog Converters (DAC)
DAC Circuits
 Digital to Analog Converters (DAC)
DAC Circuits
 Digital to Analog Converters (DAC)
The
The main disadvantage of previously discussed DAC is the requirement for various
The Th
precision resistors.
e

The
The
 Digital to Analog Converters (DAC)
Illustration: Interfacing an 8-bit DAC with 8085
The
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e

The
The
 Digital to Analog Converters (DAC)
Illustration: Interfacing an 8-bit DAC with 8085
The
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e

The
The
 Digital to Analog Converters (DAC)
Illustration: Interfacing an 8-bit DAC with 8085
The
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e

The
 Digital to Analog Converters (DAC)
Illustration: Interfacing an 8-bit DAC with 8085
The
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e

The
Digital to Analog Converters (DAC)
The
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e

The
Digital to Analog Converters (DAC)
The
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e

The
 Digital to Analog Converters (DAC)
Nowadays, D/A converters generally include
The a latch on the chip, thus eliminating the
need for external
The latch. Th
e

The
 Digital to Analog Converters (DAC)
It can be operated with one power supply voltage
The between +4.5V to +16.5 V.
To interfaceThe Th Chip Select
the AD558 with the microprocessor two signals are required:
(CS bar) and Chip Enable (CE bar). e
For example: The address line A7through an inverter is used for the Chip Select, which
assigns the port address 80H to the DAC port. The control signal IOW bar is used for
The
the Chip Enable
Digital to Analog Converters (DAC)
The
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e

The
Digital to Analog Converters (DAC)
The
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e

The
Digital to Analog Converters (DAC)
The
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e

The
 Digital to Analog Converters (DAC)
Interfacing a 12-Bit D/A Converter
The
In 12-bit D/A converter we use double buffering method.
Th
The 8- low The
order bits of the 12bit word are output to latch 1 First. The
e 4 high order
bits are then output to latch 3.
The device select pulse, which clocks the 4 bits from the data bus into latch 3, also
clocks the output of latch 1 into latch 2. The
Thus all 12 bits, B0-B11 appear at the input of the D/A converter simultaneously.
If memory mapped I/O is used, a single instruction SHLD transfer all 12 bits.
 Digital to Analog Converters (DAC)
Interfacing a 12-Bit D/A Converter
The
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e

The
 Digital to Analog Converters (DAC)
8-Bit microprocessor Compatible 12-Bit DAC AD7548
The AD7548 is a 12-bit monolithic CMOS The D/A converter for use with 8-bit bus
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microprocessors. e
The input control structure of the AD7548 is shown in figure.

The
 Digital to Analog Converters (DAC)
8-Bit microprocessor Compatible 12-Bit DAC AD7548
The
Th
Theinput registers, a least significant byte register and a most significant
There are two e
byte register.
Each register has its own chip select input. When CSLSB bar is low and WR bar
strobe occurs, the LSB register is written. The
When CSMSB bar is low and WR bar strobe occurs, the MSB register is written.
The use of the two input registers allows the 12-bit data value to be either left
justified or right justified with in the 2 bytes.
Data format is selected by the logic value of the CTRL input.
Loading the two input registers does not load the D/A. The D/A has its own register,
which is loaded from the input registers when LDAC bar is low and a WR strobe
occurs.
Digital to Analog Converters (DAC)
The
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e

The
Analog to Digital Converters (ADC)
The
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e

The
Analog to Digital Converters (ADC)
Analog to Digital Converters (ADC)
 Analog to Digital Converters (ADC)
Figure shows the block diagram of ADC, which consists of filter, sample and hold,
quantizer and digital processor.
The filter circuit is used to avoid the aliasing of high-frequency signals and passes
the baseband frequency signal of ADC. Sometimes this filter is also called
antialiasing filter.
After the filter, a sample and hold circuit is used to maintain constant the analog
input voltage of ADC during the period when the analog signal is converted into
digital. This time period is also called conversion time of ADC.
The quantizer circuit is used after sample and hold to segment the reference voltage
into different ranges. If ‘N’ number of digital bits represents analog voltage, there
are 2N possible subranges. The quantizer determines the specified subranges
corresponding to an analog input voltage.
The digital processor can encode the corresponding digital output.
 Analog to Digital Converters (ADC)
Counting-Type ADC
Counting-type ADCs are of two types; single-slope serial ADC and dual-slope
serial ADC.
The principle of operation of single-slope serial ADC is to generate a ramp voltage
using DAC, which is compared with the analog input voltage.
At the start of the ramp, the counter is started to count from the initial value. When
the ramp reaches the analog input voltage, the counter is stopped.
The digital value in the counter is directly related to the input voltage. This
converter takes longer time to convert a large voltage than a small one and some
control signals are required for the start of conversions and end of conversions.
The maximum conversion time is 2NT, when 2N clock pulses are required to
convert, where N is the number of bits, T is the clock period.

The disadvantage of this ADC is that it is unipolar due to single-slope ramp

generator.
 Analog to Digital Converters (ADC)
Counting-Type ADC
 Analog to Digital Converters (ADC)
Counting-Type ADC
 Analog to Digital Converters (ADC)

The most popular direct A/D conversion method is successive approximation, it has
the advantage of a fixed conversion time proportional to the number of bits, n, in the
code.
It has faster conversion time.
The successive approximation technique generates each bit of the code sequentially,
starting with the MSB.
Analog to Digital Converters (ADC)
 Analog to Digital Converters (ADC)

The most popular direct A/D conversion method is successive approximation, it has
the advantage of a fixed conversion time proportional to the number of bits, n, in the
code.
It has faster conversion time.
The successive approximation technique generates each bit of the code sequentially,
starting with the MSB.
Analog to Digital Converters (ADC)
Analog to Digital Converters (ADC)
Analog to Digital Converters (ADC)
Analog to Digital Converters (ADC)
Analog to Digital Converters (ADC)
Analog to Digital Converters (ADC)
Analog to Digital Converters (ADC)
Analog to Digital Converters (ADC)
Analog to Digital Converters (ADC)
Analog to Digital Converters (ADC)
 Analog to Digital Converters (ADC)
10-Bit A/D Converter AD573
FEATURES
• Complete 10-Bit A/D Converter with Reference, Clock and Comparator
• Full 8- or 16-Bit Microprocessor Bus Interface
• Fast Successive Approximation Conversion—20 ms typ
• Operates on +5 V and –12 V to –15 V Supplies
• Low Cost Monolithic Construction

The AD573 is a complete 10-bit successive approximation analog-to-digital

converter consisting of a DAC, voltage reference, clock, comparator, successive
approximation register (SAR) and three state output buffers—all fabricated on a
single chip. No external components are required to perform a full accuracy 10-bit
conversion in 20 µs.
 Analog to Digital Converters (ADC)
10-Bit A/D Converter AD573
 Analog to Digital Converters (ADC)
10-Bit A/D Converter AD573
Operation of the AD573 is controlled by the three input: CONVERT, LBE bar and
HBE bar
A conversion is initiated by a positive pulse, of at least 500ns duration, at the
CONVERT input. The rising edge of this pulse resets the internal logic of the
AD573 and within 1.5us sets DR bar high.
The falling edge of the CONVERT pulse starts the conversion cycle.
When the conversion is complete DR bar goes low, indicating that the data is ready.
LBE bar and MBE bar are used to enable the output buffers to read the low and high
bytes of the result.
The high byte contains the most significant 8 bits and bits D7 and D6 of the low
byte conation the least significant two bits, D1 and D0
 Analog to Digital Converters (ADC)
Interface of 10-Bit A/D Converter AD573 with 8085
The interface of an AD573 to an 8085A raises some important timing
considerations.
If the CONVERT pulse is generated from a device select pulse, it will meet the
500ns duration requirement of the AD573on;ly if the crystal frequency of the 8085A
is sufficiently low.
The width of WR bar and the device select strobe is given by the 8085 parameter tcc
is
tcc = (3/2 +N)*T -80
Since T = 2/Fc and N = 0 for no WAIT states, the crystal frequency must be less
than 5.2 MHz.
Wait states could be added to increase the WR bar strobe’s duration.
 Analog to Digital Converters (ADC)
Interface of 10-Bit A/D Converter AD573 with 8085
Another timing consideration involves the data access time of the AD573.
The AD573 requires as much as 250ns to provide stable data after LBEN bar or
HBEN bar goes low.
The corresponding timing parameter for the 8085 is tRD, the time from RD bar low
to valid data.
For the 8085, this parameter has a value of 300ns for the highest allowable clock
frequency and therefore no timing problem exists.
WAIT states must be introduced to increase tRD as necessary
tRD =(3/2+N)*T – 150 for 8085AH-2
tRD = (3/2+N)*T – 175 for 8085AH-1
 Analog to Digital Converters (ADC)
Interface of 10-Bit A/D Converter AD573 with 8085
The final timing consideration concerns the output float delay time of the AD573.
The AD573 requires as much as 200ns before its output buffer are completely in
their high impedance state after LBE bar or HBE bar goes high.
The time elapsed from the rising edge of RD bar until the 8085AH places the next
address on AD0-AD7 is given by the parameter tRAE .
tRAE = (1/2)*T-10
 Serial Communication Interface 8251
The serial data transfer is a method of data transfer in which one bit is transferred at
a time. This transmission is always used when the distance is greater than five
metres. This method of transmission requires very few data lines compared to
parallel transmission.

Serial data transmission can be classified as simplex, half-duplex and full-duplex

data transfer.
In the simplex serial-data-transfer system, data is transfer only in one direction.
In the half-duplex system, data can be transferred in either direction but in one
direction at a time only.
In the full-duplex system, data can be transmitted in both directions simultaneously.

The serial data-transfer systems can also be classified based on timing signals such
as synchronous and asynchronous data transfer.
Serial Communication Interface 8251
 Serial Communication Interface 8251
The Programmable Communication Interface 8251 is a programmable I/O device
designed for serial communication.
This IC can be used either in synchronous mode or asynchronous mode. Therefore,
it is called Universal Synchronous Asynchronous Receiver and Transmitter
(USART).

The 8251 can be used to transmit and receive serial data.

It accepts data in parallel format from the microprocessor and converts them into
serial data for transmission. This IC also receives serial data and converts them into
parallel and sends the data in parallel.

It is available in a 28-pin dual in-line package and has the following features:
• Synchronous and asynchronous operation
• Programmable data word length, parity and stop bits
• Parity, overrun and framing error-checking instructions and counting-loop
interactions
• Programmed for three different baud rates
• Supports up to 1.750 Mbps transmission rates
• Divide-by 1, 16, 64 mode
 Serial Communication Interface 8251
Functional Block Diagram

This IC consists of four

major sections, namely,
transmitter, receiver, modem
control and microprocessor
interface section.

These four sections are

communicated with each
other on an internal data bus
for serial data transfer.
 Serial Communication Interface 8251
Transmitter
The section consists of transmitter buffer register, output register and transmit
control logic. This section has one input and three outputs.
The transmitter buffer register accepts parallel data from the data bus of the
microprocessor. Then data can be shifted out of the output register on the T × D pin
after addition of framing bits.
The serial data bits are preceded by the START bit and succeeded by the STOP bit,
which are known as framing bits.
For this operation the transmitter must be enabled and CTS bar signal must be active
low. The signal is the transmitter clock signal which controls the bit rate on
the T × D line.

When there is no data in the

transmitter output register then it
raises a T × E signal to indicate that
the transmission is stopped. It
 Serial Communication Interface 8251
Receiver
This section consists of a receiver buffer register, receiver control logic and input
register.
The receiver section of 8251 USART accepts serial data on the R × D pin. Then it
converts the data into parallel data according to the required format.
When the 8251 is in the asynchronous mode and it is ready to accept a character, it
looks for a low level on the R × D line.
When it gets a low level, it assumes that it is a START bit and enables an internal
counter
 Serial Communication Interface 8251
Receiver
If the R × D line is high when it is sampled then either a noise pulse has occurred or
the receiver has become enabled in the middle of the transmission of a character.
In either case, the receiver aborts its operation and prepares itself to accept a new
character.
After the successful reception of a START bit, the 8251 clocks in the data, parity and
STOP bits in the input register, the data is separated and converted into parallel data
and then transfers the data to the receiver buffer register.
When this register is full, the R × RDY line becomes high. This line is then used
either to interrupt the microprocessor or to indicate its own status. The
microprocessor then accepts the data from the register.
 Serial Communication Interface 8251
Modem Control
The modem control section provides the generation of RTS bar (request to send) and
the reception of CTS bar (clear to send).
This section also provides a general-purpose output DTR bar (Data Terminal Ready)
and a general-purpose input DSR bar (Data Set Ready).
DTR bar is generally assigned to the modem, indicating that the terminal is ready to
communicate and DSR bar is a signal from the modem indicating that it is ready for
communication.
 Serial Communication Interface 8251
Pin Diagram
 Serial Communication Interface 8251
Pin Diagram
 Serial Communication Interface 8251
Pin Diagram
 Serial Communication Interface 8251
Pin Diagram
Status of Control signals for accessing the different registers.
CS C/Dba RD WR State
bar r bar bar
0 1 1 0 μp writes instruction in the control register
0 1 0 1 μp reads status from the status register
0 0 1 0 μp outputs data to the data buffer
0 0 0 1 μp accepts data to the data buffer
1 X X X USART is not selected for communication

T X E (Transmitter Empty)
When the T × E output is high, the 8251 has no characters to transmit. This
automatically goes low when a character is received from the CPU for further
transmission. If this pin is high in synchronous mode, it indicates that a character has
not been loaded and the SYNC character or characters are being transmitted or about
to be transmitted. The T × E signal can be used to indicate the end of a transmission
mode.
 Serial Communication Interface 8251
T X D (Transmit Data Output)
The serial data output from the output register is transmitted on T × D pin. The
transmitted data bits consist of data along with other informations such as start bit,
stop bits and parity bit.

T X C (Transmitter Clock Input)

The transmitter clock input T × C bar controls the rate at which the data is to be
transmitted. The baud rate is equal to the T × C frequency in synchronous
transmission mode. In asynchronous transmission mode, the baud rate is 1, 1/16 or
1/64 times the T × C. The serial data is transmitted out by the successive negative
edge of the T × C.

T X RDY (Transmitter Ready)

This is output signal, which indicates to the CPU that the transmitter buffer is empty.
The T × RDY signal is set only when CTS bar and T × E are active. The T × RDY is
reset when the CPU writes a byte into the buffer register by the rising edge of the
WR bar signal.
 Serial Communication Interface 8251
R X D (Receive Data Input)
This input pin of 8251A receives serial data from outside environment, and delivers
to the input register via R × D line which is subsequently put into parallel from and
placed in the receiver buffer register.

R X C bar (Receiver Clock Input)

The R × C bar receiver clock input pin controls the rate at which the bits are received
by the input register. In synchronous mode, the baud rate is equal to the R × C
frequency. In asynchronous mode, the baud rate can be set to either 1 or 1/16 or
l/64th of the R × C frequency.

R X RDY (Receiver Ready)

This is an output pin which indicates that 8251A contains a character to be read by
the CPU. This signal can be used to interrupt the CPU as well as polled by the CPU.
 Serial Communication Interface 8251
8251 Interface with Microprocessor
This circuit consists of eight data lines,
which are connected to the data bus of the
CPU.
The 8251 IC can be used either in I/O
mapped or memory mapped I/O mode.
In I/O mapped I/O interface mode, the RD
bar and WR bar lines are connected to IOR
bar and IOW bar control lines.
The CLK pin is connected with to the
CLK OUT of the microprocessor to
provide synchronization between the
microprocessor and 8251.
The address decoder output is connected to
the CS terminal of 8251.
C / D terminal is used to select internal
registers such as control register and data
register. Generally this is connected to the
A0 address bus.
 Serial Communication Interface 8251
Operating Modes of 8251
The 8251 can be operated in different modes based on mode control words. A set of
control words can be written into the internal registers of 8251A to make it operate in
the desired mode. The control words of 8251A are two functional types, namely,
• Mode Instruction Control word
• Command Instruction Control word

There are two 8-bit control registers in 8251 to load the mode word and command
word.
The mode instruction word informs about the initial parameters such as mode, baud
rate, stop bits and parity bit.
The command instruction word explains about enabling the transmitter and receiver
section.
 Serial Communication Interface 8251
Mode Instruction Control Word
Mode instruction control word defines the general operational characteristics of
8251A.
After reset by using internal reset command or external reset command, the mode
instruction control word must be loaded into 8251 to configure the device as per
requirements.
These control words are different for synchronous and asynchronous mode
operation.
Once the mode instruction control word has been written into 8251, SYNC
characters (synchronous mode only) or command instructions (synchronous or
asynchronous mode) may be programmed.
The mode of operation from synchronous to asynchronous or from asynchronous to
synchronous can be changed by resetting the 8251.
 Serial Communication Interface 8251
Mode Instruction Control Word
The mode instruction format for asynchronous mode is shown in Figure
 Serial Communication Interface 8251
Mode Instruction Control Word
Asynchronous mode (Transmission)
The transmission format consists of start bit, data character, parity bit and stop bits.
The 8251 starts to send data on the T × D pin after adding a start bit which is a 1 to 0
transmission. Then data bits are transmitted using the T × D pin on the falling edge
of the transmitter clock (T × C) followed by stop bits. When no data is transmitted
by the CPU to 8251, the T × D output pin remains ‘high’. If a ‘break’ has been
detected, T × D the line will go low.
 Serial Communication Interface 8251
Mode Instruction Control Word
Asynchronous mode (Transmission)
Data reception starts with a falling edge of R × D input which indicates the arrival of
start bit.
If R × D is low, it indicates a valid start bit which starts counting. Then the bit
counter locates data bits, parity bits and stop bits. If any error occurs during the
receiving of data with regard to parity, framing or overrun, the corresponding flags in
the status word will be set. The receiver requires only one stop bit to mark end of the
data bit string though the number of stop bits affects the transmitter.
 Serial Communication Interface 8251
Mode Instruction Control Word
Synchronous mode Instruction format
For synchronous transition/receiving of data both D0, D1 will be low. Bits D2 and
D3 indicate the character length. Bit D4 stands for Parity Enable (PEN) and D5
stands for Even Parity (EP). Bit D6 stands for External Synchronous Detect (ESD).
D6 = 1 for input and D6 = 0 for output.
Bit D7 = 1 indicates a Single
Synchronous Character (SCS).
But D7 = 0 represents double
synchronous characters.
 Serial Communication Interface 8251
Mode Instruction Control Word
Synchronous mode (Transmission)
 Serial Communication Interface 8251
Command Instruction Word
The command instruction controls the actual operations of the selected format like
enable transmit/receive, error reset and modem controls. Once the mode instruction
has been written into 8251A and the SYNC characters are loaded (only in
synchronous mode), the device is ready for data communication.
The command instructions can be accepted only after mode instruction in case of
asynchronous mode. A reset operation returns the 8251 back to mode instruction
format from the command instruction format.
 Serial Communication Interface 8251
Status Word Register Format
The status word can be read with C / D =1. The CPU requires various information to
operate properly. All required information are provided by the status word.
 Serial Communication Interface 8251
Status Word Register Format
The status word can be read with C / D =1. The CPU requires various information to
operate properly. All required information are provided by the status word.