UNBIASED ROUDING FOR HUB FLOATING-POINT

ADDITION

A Mini Project Report submitted to

JNTU Hyderabad in partial fulfillment
of the requirements for the award of the degree

BACHELOR OF TECHNOLOGY
In
ELECTRONICS AND COMMUNICATION ENGINEERING
Submitted by

A.BHAVANA 21S15A0408
SHIVARATHRI VIKRANTH 21S15A0434
AYYANKI SRUJALA 21S15A0429

Under the Guidance of

Mr.N.RAMESH
B. Tech, M. Tech,
Assistant Professor
DEPARTMENT OF ELECTRONICS AND COMMUNICATION
ENGINEERING
MALLA REDDY INSTITUTE OF TECHNOLOGY & SCIENCE
(Approved by AICTE New Delhi and Affiliated to JNTUH)
(Accredited by NBA & NAAC with “A” Grade)
An ISO 9001: 2015 Certified Institution
Maisammaguda, Medchal (M), Hyderabad-500100, T. S.
NOVEMBER 2023
 DEPARTMENT OF ELECTRONICS & COMMUNICATION
ENGINEERING
MALLA REDDY INSTITUTE OF TECHNOLOGY & SCIENCE
(Approved by AICTE New Delhi and Affiliated to JNTUH)
(Accredited by NBA & NAAC with “A” Grade)
An ISO 9001: 2015 Certified Institution
Maisammaguda, Medchal (M), Hyderabad-500100, T. S.
NOVEMBER 2023

CERTIFICATE

This is to certify that the mini project entitled “UNBIASED

ROUNDING FOR HUB FLOATING-POINT ADDITION” has been submitted by
A.BHAVANA (21S15A0408),SHIVARATHRI VIKRANTH (21S15A0434) ,
and AYYANKI SRUJALA (21S15A0429) in partial fulfillment of the
requirements for the award of BACHELOR OF TECHNOLOGY in
ELECTRONICS & COMMUNICATION ENGINEERING. This record of
bonafide work carried out by them under my guidance and supervision. The
result embodied in this mini project report has not been submitted to
any other University or Institute for the award of any degree.

Mr. N.RAMESH Mrs.G.Subhasini

Assistant Professor Head of the
Department Project Guide

External Examiner
 ACKNOWLEDGEMENT

The Mini Project work carried out by our team in the Department of
Electronics and Communication Engineering, Malla Reddy Institute of
Technology and Science, Hyderabad. This work is original and has not
been submitted in part or full for any degree or diploma of any other
university.

We wish to acknowledge our sincere thanks to our project guide

Mr. N. RAMESH, Assistant Professor of Electronics & Communication
Engineering for formulation of the problem, analysis, guidance and her
continuous supervision during the course of work.

We acknowledge our sincere thanks to Dr. Vaka Murali Mohan,

Principal and Mrs. G. Subhashini, Head of the Department and Coordinator,
faculty members of ECE Department for their kind cooperation in making
this Mini Project work a success.

We extend our gratitude to Sri. Ch. Malla Reddy, Founder

Chairman MRGI and Sri. Ch. Mahender Reddy, Secretary MRGI,
Dr.Ch. Bhadra Reddy, President MRGI, Sri. Ch. Shalini Reddy,
Director MRGI, Sri. P. Praveen Reddy, Director MRGI, for their kind
cooperation in providing the infrastructure for completion of our Mini Project.

We acknowledge our special thanks to the entire teaching faculty and

non-teaching staff members of the Electronics & Communication
Engineering Department for their support in making this project work a
success.
[

A.BHAVANA 21S15A0408
SHIVARATHRI VIKRANTH 21S15A0434
AYYANKI SRUJALA 21S15A0429 _

ii
 INDEX
Chapter Page No.
ABSTRACT v
LIST OF FIGURES vi
LIST OF TABLES vii
1. INTRODUCTION 1
1.1 INTRODUCTION 1
1.2 OBJECTIVES 2
1.3 CONTRIBUTIONS 2

2. LITERATURE SURVEY 4
2.1 IRREVERSIBILITY AND HEAT GENERATION IN THE COMPUTING
PROCESS 4
2.2 LOGIVAL IRREVERSIBILITY OF COMPUTATION 4
2.3 A COMPARATIVE STUDY OF REVERSIBLE LOGIC GATES 5
2.4 DESIGN OFA REVERSIBLE ALU BASED ON NOVEL PROGRAMMABLE
REVERSIBLE LOGIC GATE STRUCTURES 5
2.5 DESIGN OF A REVERSIBLE SINGLE PRECISION FLOATING POINT
MULTIPIER BASED ON OPERAND DECOMPOSITION 6

3. EXISTING SYSTEM 7
3.1 LOGIC COMPUTATION 7
3.1.1 TRADITIONAL LOGIC COMPUTATION 7
3.2.1 REVERSIBLE LOGIC COMPUTATION 10
3.2 LOGIC GATES 10
3.2.1 REVERSIBLE GATES 10
3.2.2 NOT GATES 11
3.2.3 CNOT GATES 11
3.2.4 TOFFOLI GATES 12
3.2.5 FREDKIN GATES 13
3.3 COST METRICS IN REVERSINBLE LOGIC 15
3.3.1 GATE COUNT(GC) 15
3.3.2 GARBAGE OUTPUT(GO) 15

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 3.3.3 CONSTANT INPUT(CI) 16
3.3.4 QUANTUM COST(QC) 16
3.4 FAULT,FAILURES AND ERRORS 17
3.5 FAULT TOLERANCE IN REVERSIBLE LOGIC 18
3.5.1 FAULT DETECTION 18
3.5.2 FAULT LOCATION 18
3.5.3 FAULT RECOVERY 19
3.5.4 FAULT MASKING 19
3.6 BASIC ADDERS 19

4. PROPOSED SYSTEM 21
5. REVERSIBLE MAJORITY VOTER CIRCUITS 26
5.1 FAULT TOLERANT REVERSIBLR CIRCUITS 26
5.1.1 REVERSIBLE MAJORITY VOTER CIRCUITS LITERATURE 27
5.2 PROPOSED REVERSIBLE VOTER CIRCUITS 30
5.2.1 FAULT TOLERANT REVERSIBLE CIRCUIT DESIGN 32

6. SOFTWARE REQUIREMENT 34
6.1 MIGRATING PROJECTS FROM PREVIOUS ISE SOFTWARE
RELEASE 34
6.2 PROPERTIES 34
6.3 IP MODULES 34
6.4 OBSOLUTE SOURCE FILE TYPES 35
6.5 USING ISE EXAMPLE PROJECTS 35
6.6 CREATING A PROJECT 36
6.7 DESIGN PANEL 36

7. RESULTS 39
8. CONCLUSION & FUTURE SCOPE 42
9. APPENDIX 43
10. BIBLIOGRAPHY 45
11. YUKTHI INNOVATION CERTIFICATE
12. PAPER PUBLISHED FROM THIS WORK

iv
 ABSTRACT
An exportable application-specific instruction-set elliptic curve cryptography processor based
on redundant signed digit representation is proposed. The processor employs extensive
pipelining techniques for Karatsuba–Of man method to achieve high throughput
multiplication. Furthermore, an efficient modular adder without comparison and a high
through put modular divider, which results in a short data path for maximized frequency, are
implemented. The processor supports the recommended NIST curve P256 and is based on an
extended NIST reduction scheme. The proposed processor performs single point
multiplication employing points in affine coordinates in 2.26 ms and runs at a maximum
frequency of 160 MHz in Xilinx Virtex 5 (XC5VLX110T) field-programmable gate array.

v
 LIST OF FIGURES

FIGURE NO FIGURE NAME PAGE NO

3.1 Reversible Logic Gates 11

3.2 Toffoli Gates 12
3.3 Reversible Fredkin gates 14
3.4 Critical path of 4-bit reversible adder and irreversible adder 20
4.1 HUB Floating-point adder 22
4.2 Overall processor architecture 23
4.3 Modular Addition Subtraction block diagram 24
5.1 Reversible majority voter circuit 27
5.2 Reversible fault tolerant multiplexing scheme 28
5.3 Reversible majority voter circuit 28
5.4 Majority voter with triplicated voter outputs proposed 29
5.5 Example of inputs assignments 30
5.6 MVC with two reversible gates 30
5.7 Reversible fault tolerant full adder circuit design 33

vi
 LIST OF TABLES

TABLE NO TABLE NAME PAGE NO

3.1 Truth Table of traditional logic functions 08

3.2 Truth Table of reversible logic functions 09
3.3 Truth table of a 3 ×3 positive-controlled Toffoli gate 13
3.4 Behavior of a 3 ×3 positive-controlled Fredkin gate 14
3.5 Quantum cost of some reversible gates 16
3.6 Comparsion of reversible and irreversible RCA 20
5.1 Truth table of the majority voter with two reversible gates 31

vii
 CHAPTER 1: INTRODUCTION

1.1 INTRODUCTION

Reversible logic has presented itself as a prominent technology which plays an imperative role
in Quantum Computing. Quantum computing devices theoretically operate at ultrahigh speed and
consume infinitesimally less power. Research done in this paper aims to utilize the idea of
reversible logic to break the conventional speed-power trade-off, thereby getting a step closer to
realise Quantum computing devices. To authenticate this research, various combinational and
sequential circuits are implemented such as a 4-bit Ripple-carry Adder, (8- bit X 8-bit) Wallace
Tree Multiplier, and the Control Unit of an 8-bit GCD processor using Reversible gates. The
power and speed parameters for the circuits have been indicated, and compared with their
conventional non- reversible counterparts. The comparative statistical study proves that circuits
employing Reversible logic thus are faster and power efficient. The designs presented in this
paper were simulated using Xilinx 9.2 software.

Reversible logic is widely used in low power VLSI. Reversible circuits are capable of back-
computation and reduction in dissipated power, as there is no loss of information [1]. Basic
reversible gates are employed to achieve the required functionality of a reversible circuit. The
uniqueness of reversible logic is that, there is no loss of information since there is one-to-one
correspondence between inputs and outputs. This enables the system to run backwards and while
doing so, any intermediate design stage can be thoroughly examined. The fan-out of each block in
the circuit has to be one. This research paper focuses on implementation of reversible logic
circuits in which main aim is to optimize speed of the design. A Reversible adder is designed
using basic reversible gates. Using this adder, an 8-bit reversible ripple-carry adder is devised and
then compared with the conventional 8-bit adder in terms of speed, critical paths, hardware used.
Then using the same reversible adder, a Wallace tree multiplier has been implemented, and
compared with the conventional Wallace tree multiplier. With the known fact that sequential
circuits are the heart of digital designing, the design for the control unit of a reversible GCD
processor has been proposed using Reversible logic gates.

1
1.2 Objectives

This thesis explores the existing work on designing fault tolerant reversible circuits and
presents a passive hardware redundancy technique for achieving fault tolerance in reversible
logic. gates and proposed synthesis methods incorporating these gates. Fault detection within
reversible circuits is presented in The use of the parity preserving property is a commonly used
fault detection technique and is still an active area However, the parity preserving property in
reversible circuits can only detect the presence of a fault. Most of the literature on fault tolerance
offers fault detection features which do not correct or mask the faulty output. To be labeled as
fault tolerant, a circuit should either correct or mask the fault at the output. • Our proposed
hardware fault tolerance technique uses the concept of traditional triple modular redundancy
(TMR). The TMR technique requires a majority voter circuit (MVC) for fault masking purposes.
The basic function of a MVC is to mask the faults and provide corrected output. Designing
reversible fault tolerant circuits using the concept of TMR is one of the main objectives of this
thesis. We propose two new designs for a reversible majority voter circuit for fault masking in
reversible logic.

In reversible logic, a one-to-one mapping between the inputs and outputs must be
maintained. This requirement often introduces design complexity to a reversible circuit. Design
complexity of a reversible circuit is measured by commonly used cost metrics such as gate
count, quantum cost, number of constant inputs and garbage outputs. We analyze the design
complexity of our proposed voter circuits and present the macro gate level circuit
implementation

Fault tolerance improves reliability by keeping the circuit operational in the event of a
failure. Therefore, it is important to assess the reliability of a design and study a circuit’s failure
probabilities. In a voting based fault masking technique, achieving fault tolerance largely
depends on the voter circuit operation. One of the objectives of this thesis is to determine the
voter circuit’s failure probabilities based on its components (i.e. the comprising gate failure
probabilities).

1.3 Contributions

2
The contributions of this thesis are listed below:

3
 In this thesis, we propose an approach to achieve fault tolerance in reversible logic circuits.
We offer a majority voting based TMR approach for masking faults that occur in the original
circuit.

TMR in reversible circuits requires the design of a reversible majority voter circuit. In our
work, we propose two new designs for a reversible majority voter circuit. We present a fault
tolerant design for a reversible full adder circuit and demonstrate how our proposed voter circuits
can be used to design any fault tolerant reversible circuits. We demonstrate the proposed
reversible majority voter circuit application for masking a single fault occurring in any of the
voter circuit’s inputs, i.e. before the voter circuit. A single fault assumption considers a situation
where at most one fault is present in a circuit. We present the fault masking capability of our
proposed voter circuits in the case of a single bit fault (SBF), a single gate fault (SGF), a
crosspoint fault and the family of missing gate fault. We propose a failure probability analysis of
the proposed majority voter circuits. We demonstrate that the methodology proposed in this thesis
can be used to determine a voter circuit’s failure probabilities based on the gate failure
probabilities.

4
 CHAPTER 2:LITERATURE SURVEY

2.1 Irreversibility and heat generation in the computing process:

It is argued that computing machines inevitably involve devices which perform logical
functions that do not have a single-valued inverse. This logical irreversibility is associated with
physical irreversibility and requires a minimal heat generation, per machine cycle, typically of the
order of kT for each irreversible function. This dissipation serves the purpose of standardizing
signals and making them independent of their exact logical history. Two simple, but representative,
models of bistable devices are subjected to a more detailed analysis of switching kinetics to yield
the relationship between speed and energy dissipation, and to estimate the effects of errors induced
by thermal fluctuations.

2.2 Logical Reversibility of Computation:

The usual general-purpose computing automaton (e.g.. a Turing machine) is logically
irreversible- its transition function lacks a single-valued inverse. Here it is shown that such
machines may he made logically reversible at every step, while retaining their simplicity and their
ability to do general computations. This result is of great physical interest because it makes
plausible the existence of thermodynamically reversible computers which could perform useful
computations at useful speed while dissipating considerably less than KT of energy per logical
step. In the first stage of its computation the logically reversible automaton parallels the
corresponding irreversible automaton, except that it saves all intermediate results, thereby avoiding
the irreversible operation of erasure. The second stage consists of printing out the desired output.
The third stage then reversibly disposes of all the undesired intermediate results by retracing the
steps of the first stage in backward order (a process which is only possible because the first stage
has been carried out reversibly), thereby restoring the machine (except for the now-written output
tape) to its original condition. The final machine configuration thus contains the desired output and
a reconstructed copy of the input, but no other undesired data. The foregoing results are
demonstrated explicitly using a type of three-tape Turing machine. The biosynthesis of messenger
RNA is discussed as a physical example of reversible computation.

5
2.3 A comparative study of Reversible logic gates:
Reversible Logic is becoming more and more prominent technology having its
applications in Low Power CMOS, Quantum Computing, Nanotechnology, and Optical
Computing. Reversible logic has emerged as one of the most important approaches for the
power optimization with its application in low power VLSI design .In contrast to conventional
gates, reversible logic gates have the same number of inputs and outputs, each of their output
function is equal to 1 and their fan-out is always equal to 1. It is interesting to compare both
reversible and conventional gates. In this paper the authors presented the major VLSI
limitations like power consumption, delay and area of different reversible logic gates which are
simulated in Xilinx9.2 and by writing the code in VERILOG HDL and also compared reversible
gates to conventional gates.
2.4 Design of a Reversible ALU Based on Novel Programmable Reversible
Logic Gate Structures:
Programmable reversible logic is emerging as a prospective logic design style for
implementation in modern nanotechnology and quantum computing with minimal impact on
circuit heat generation. Recent advances in reversible logic using and quantum computer
algorithms allow for improved computer architecture and arithmetic logic unit designs. In this
paper, a 2*2 Swap gate which is a reduced implementation in terms of quantum cost and delay to
the previous Swap gate is presented. Next, a novel 3*3 programmable UPG gate capable of
calculating the fundamental logic calculations is presented and verified, and its advantages over
the Toffoli and Peres gates are discussed. The UPG is then implemented in a reduced design for
calculating n-bit AND, n-bit OR and n-bit ZERO calculations. Then, two 3*3 RMUX gates
capable of multiplexing two input values with reduced quantum cost and delay compared to the
previously existing Fredkin gate is presented and verified. Next, 4*4 reversible gate is presented
and verified which is capable of producing the calculations necessary for two-bit comparisons.
The UPG and RC are implemented in the design of novel sequential and tree-based comparators.
Then, two novel 4*4 reversible logic gates (MRG and PAOG) are proposed with minimal delay,
and may be configured to produce a variety of logical calculations on fixed output lines based on
programmable select input lines. A 5*5 structure (MG) is proposed that extends the capabilities
of both the MRG and PAOG. The comparator designs are verified and its advantages to previous
designs are discussed. Then, reversible implementations of ripple-carry, carry-select and Kogge-
Stone carry look-ahead adders vii are analyzed and compared. Next, implementations of the
6
Kogge-Stone adder with sparsity-4, 8 and 16 were designed, verified and compared. The
enhanced sparsity-4 Kogge-Stone adder with ripple-carry adders was selected as the best design,
and its implemented in the design of a 32-bit arithmetic logic unit is demonstrated. The proposed
ALU design is verified and its advantages over the only existing ALU design are quantitatively
analyzed.

2.5 Design of a reversible single precision floating point multiplier based on

operand decomposition:

Reversible logic is a promising field of research that finds applications in low power
computing, quantum computing, optical computing, and other emerging computing technologies.
Further, floating point multiplication is one of the major operations in image and digital signal
processing applications. The single precision floating-point multiplier requires the design of
efficient 24x24 bit integer multiplier. In this work, we propose a new reversible design of single
precision floating point multiplier based on operand decomposition approach. To design the
reversible 24x24 (AxB) bit multiplier (assume A and B are of 24 bits each), the operands are
decomposed into three partitions of 8 bits each. Thus, the 24x24 bit reversible multiplication is
performed through nine reversible 8x8 bit Wallace tree multipliers, whose outputs are then
summed. We propose a new reversible design of the 8x8 bit Wallace tree multiplier that has been
optimized in terms of quantum cost, delay, and number of garbage outputs. Wallace tree
multiplication consists of three conceptual stages: Partial product generation, partial product
compression using 4:2 compressors, full adders, and half adders, and then the final addition stage
to generate the product. In this work we perform optimization at each of these three stages. For
the first stage, we have proposed a new generalized reversible partial product generation
circuitry. For the second stage we have proposed a new reversible 4:2 compressor design for use
in the compression tree. Finally, for the summation stage we have carefully chosen and arranged
the reversible half adders and full adders in such a way to yield an efficient multiplier optimized
in terms of quantum cost, delay, and garbage output.

7
 CHAPTER 3: EXISTING SYSTEM
INTRODUCTION

The structure of 32-piece Single Precision Floating Point Multiplier and Adder is reproduced
and introduced in this paper. The gliding point number can bolster wide scope of qualities. It is
spoken to utilizing three fields: sign, example and mantissa. In this paper gliding point expansion,
and increase calculations for IEEE-754 (single exactness) is displayed. The IEEE-754 converter is
utilized to change over decimal gliding point number into Binary drifting point organization and it
is additionally used to check the outcomes. A square graph of the primary information way bit of
the DSP square, two littler 18x18 multipliers, went before by discretionary info pre-adders, can be
utilized to execute free multipliers, totals of multipliers, or bigger 27x27 multipliers, utilizing the
multiplexers and blowers. The last CPA in the DSP square can be part in two on account of
individual multipliers. To help the entirety of the fixed-point modes and furthermore FP
augmentation, the last CPA was decayed into a lot of prefix structures lined up with both the fixed
and FP limits. The three FP multiplier steps post pressure: last sub-item decrease, standardization
and adjusting were consolidated into a solitary level CPA utilizing a hailed prefix approach. Our
hailed prefix approach, so as to help both fixed and FP estimations, utilizes a hailed prefix
structure, overlaid on the convey select structure, overlaid on a prefix snake structure.

3.1 Logic Computation

In computing, logic operations are used to model the information flow through digital
circuits. A logic operation connects and verifies two or more units of information. Logic that
implements a Boolean function is also known as digital or traditional logic. Mod- ern digital
devices follow the principle of Boolean logic and define a problem in terms of Boolean
functions. A circuit element that performs a logic operation is called a logic gate. Due to the
limitations of existing physical components in traditional logic (e.g. heat dis- sipation)
researchers are showing more interest in reversible logic computation [5]. The following
subsections explain the concepts of traditional and reversible logic computation.
3.1.1 Traditional Logic Computation
In traditional logic, a function maps one or more inputs to one or more outputs in a
Boolean domain B, where B = {0, 1}.

8
 In most cases, the number of outputs is less than the number of inputs (i.e. n < k). The input-
output relation of a traditional logic gate can be described by the associated truth table. A truth
table shows the mapping from the k input columns to the n output columns over 2k rows of any
Boolean logic function.
Table 3.1 Truth tables of traditional logic functions.

(a) NOT Operation (b)OR Operation (c)Full Adder Operation

Carryi A B Carryo S
A NOT (A) P Q P+
n ut u
0 1 Q
m
1 0 0 0 0 0 0 0 0 0
0 0 1 0 1 0 1 1
0 1 0 0 1 1 0 1
0 1 1 1 0 1 1 1
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
The truth table describes all possible logic values of the inputs along with the result-ing
outputs. Table 3.1a shows a NOT gate operation in traditional logic. The input-output relationship
of a traditional NOT gate operation is one-to-one and this is a reversible oper-ation. A reversible
operation is invertible and the input-output relationship of a reversible operation is one-to-one and
onto. However, Table 3.1b and Table 3.1c show functions for which the relationship between
inputs and outputs is not one to one. For example, a con-ventional OR gate has two inputs and
yields a single output. Thus, the OR gate is logically irreversible, meaning it is not possible to
determine unique inputs for all the outputs.

9
 Table 3.2 Truth tables of reversible logic
functions.

(a) NOT Operation. (b) Controlled NOT Operation.

A NOT (A) P Q X Y
0 1 0 0 0 0
1 0 0 1 0 1
1 0 1 1
1 1 1 0

(c) Full Adder Operation.

Constantin1 Carryin1 A B Carryout Sum Garbageout1 Garbageout2

0 0 0 0 0 0 0 0
0 0 0 1 0 1 1 1
0 0 1 0 0 1 1 0
0 0 1 1 1 0 0 1
0 1 0 0 0 1 0 0
0 1 0 1 1 0 1 1
0 1 1 0 1 0 1 0
0 1 1 1 1 1 0 1
1 0 0 0 1 0 0 0
1 0 0 1 1 1 1 1
1 0 1 0 1 1 1 0
1 0 1 1 0 0 0 1
1 1 0 0 1 1 0 0
1 1 0 1 0 0 1 1
1 1 1 0 0 0 1 0
1 1 1 1 0 1 0 1

1
0
 3.1.2 Reversible Logic Computation

In reversible logic a one to one mapping exists between the input and output assign- ment.
Therefore, reversible logic gates are bijective requiring an equal number of inputs and outputs.
Thus, reversible gates do not erase any information during computation and the computation can
be undone to recover the input information . In the scope of this thesis, our research addresses
only Boolean reversible logic functions. The truth table for a reversible function of k variables
requires 2k rows and 2k columns. The bijective rela-tionship between the inputs and outputs of a
NOT, Controlled NOT, and full adder logic . An irreversible logic circuit can be transformed into
a reversible circuit by adding inputs and/or outputs. These additional inputs are called constant
inputs and the unused outputs are called garbage outputs. For example, the truth table of a
reversible full adder presented in Table 3.2c shows additional constant input and garbage outputs
as compared to the truth table of the irreversible full adder presented in Table 3.1c. In a full adder,
Carry and Sum are the two output bits of interest. In Table 3.2c, two outputs, Carryout and Sum,
represent the carry and sum bits of a full adder. The garbage outputs do not contribute to the
property of the sum or carry output bits. The additional input Constantin1 and the two outputs,
Garbageout1 and Garbageout2 are used to maintain the bijective relation between the inputs and the
outputs of this reversible full adder operation. Constant inputs and garbage outputs are often used
as cost metrics of reversible circuits. The cost metrics in reversible logic are discussed further in
section 3.3.
3.2 Logic Gates

Logic gates are used to perform logic operations. Gates are combined (cascaded) to implement
the desired logic functions. Therefore, logic gates are the key components of a circuit. This
section introduces the reversible logic gates that are used to design the fault tolerant reversible
circuits of this thesis.
3.2.1 Reversible Gates

All reversible gates are bijective and maintain one-to-one and onto relationships be- tween the
inputs and outputs. The two most popular families of gates are the NCT (NOT- CNOT-Toffoli)
gate family and the SF (SWAP-Fredkin) gate family . This thesis uses Controlled NOT (CNOT)
and Toffoli gates from the NCT family and Fredkin gates which belong to the SF gate family.
These

1
gates are introduced in the following subsections. In the following figures the • symbol represents

1
the control points and the ⊕ symbol indicates. the targets of the reversible gates. The targets (⊕) of

the reversible gates perform the EXOR operation. The first n − 1 bits are known as control the
control bits, and the last nth bit is the target bit. The reversible gate passes the input values at controls
directly
to the correspond- ing outputs without any change and inverts the target bit if and only if all input
values at controls are 1. The NOT gate is a special case of a Toffoli gate with no controls. Negative

control points are shown as ◦ and inverts the target bit if and only if all input values at controls are
0.

(a) A reversible NOT gate . (b) A CNOT gate.

Figure 3.1 Reversible logic gates.

3.2.2 NOT Gates

One of the simplest reversible logic gates is a NOT gate. A reversible NOT gate oper-ation
shown in Table 3.2a is identical to the traditional NOT gate operation in Table 3.1a. A NOT
gate in traditional logic is the only logic gate that provides a one-to-one and onto relationship
between the inputs and outputs. Thus, the logical NOT operation is reversible. The truth table
for a logical NOT operation is presented in Table 3.2a.

3.2.3 CNOT Gates

The controlled-NOT (CNOT) gate belongs to the NCT gate family. A CNOT gate con-
sists of a control input and a target input. A specified value at the control input inverts the
target input value. If the control input value of 1 inverts the target input, the gate is referred to
as a positive-controlled gate. Figure 3.1b shows a positive controlled CNOT gate along with the
logic
1
function. The as- sociated truth table. A CNOT gate is also known as the Feynman gate .
3.2.4 Toffoli Gates

A Toffoli gate is a form of CNOT gate with multiple control points . The reversible NOT gate is a
special case of a Toffoli gate with n = 1 and no control values. When n = 2, the Toffoli gate is
also known as the CNOT or Feynman gate. It is possible to implement the three basic logic
operations (i.e. the NOT, AND and OR operations) using only Toffoli gates . Thus, a Toffoli gate
is considered to be a universal gate.

A 3 × 3 positive-controlled Toffoli gate.

A n × n MCT gate with positive and negative control points.

Figure 3.2 Toffoli gates.

The two input lines a1 and a2 are connected to the two control points and the input line a3 is
connected to the target. If the values of the two control points are 1 then the target input is
inverted. Otherwise, the target input remains unchanged.

1
 Table 3.3 Truth table of a 3 × 3 positive-controlled Toffoli gate.

input output
a1 a2 a3 x1 x2 x3
0 0 0 0 0 0
0 0 1 0 0 1
0 1 0 0 1 0
0 1 1 0 1 1
1 0 0 1 0 0
1 0 1 1 0 1
1 1 0 1 1 1
1 1 1 1 1 0

For example in Figure 2.2a, for the inputs (a1, a2, a3) ≡ (1, 1, 1), the output of the Toffoli

gate is (x1, x2, x3) ≡ (1, 1, 0). The truth table of a 3 × 3 positive-control Toffoli gate is shown

in Table 3.3.

Based on the value of the control points, a Toffoli gate can also be positive or negative
controlled (shown in Figure 3.2a and Figure 3.2b). The difference between a positive- controlled
and a negative-controlled Toffoli gate lies in the gate operation. A positive- controlled Toffoli
gate inverts the target when the control value is 1 while the negative- controlled Toffoli gate
inverts the target when the control value is 0. A negative-controlled Toffoli gate may have one or
more negative controls. In that case, this gate inverts the target when all the negative control
values are 0. A Toffoli gate can also have multiple control points in which case it is referred to
as an n-bit Toffoli gate

(where n − 1 is the number of controls and the nth bit is the target) or a multiple-controlled Toffoli
(MCT) gate. A MCT gate with different control points inverts the value of the target point when
all
of the positive controls are at 1 and the negative controls are at 0. An example of this is shown in
Figure 3.2c.

3.2.5 Fredkin Gates

1
A Fredkin gate is also a universal reversible gate that performs a logic operation con- trolled

1
by one or more control points . Unlike the gates in the NCT family, the target lines of a Fredkin
gate interchange their values depending on the value at the control points. A positive-controlled
Fredkin gate interchanges the target lines if the control point value is 1, otherwise the target lines
remain unchanged. Similarly, a negative-controlled Fredkin gate performs the logic operation
when

the control value is 0. Figure 3.3 shows different Fredkin gates. The truth table for a 3 × 3

positive- controlled Fredkin gate is presented in Table 3.4.

A SWAP gate.

A 3 × 3 positive-controlled Fredkin gate. A 3 × 3 negative-controlled Fredkin gate.

Figure 3.3 Reversible Fredkin gates.

Table 3.4 Behavior of a 3 × 3 positive-controlled Fredkin gate.

input output
a b c x y z
0 0 0 0 0 0
0 0 1 0 0 1
0 1 0 0 1 0
0 1 1 0 1 1
1 0 0 1 0 0
1 0 1 1 1 0
1 1 0 1 0 1
1 1 1 1 1 1
A 2-bit Fredkin gate is known as a SWAP gate and is shown in Figure 3.3(a). A SWAP gate
always interchanges the values of a positive and a negative control Fredkin gate. If a Fredkin gate

1
has multiple control points then the gate is called an n-bit Fredkin gate or Multiple Control
Fredkin (MCF) gate. In a MCF, the gate passes the control bits to the outputs unchanged and
interchanges the target bit values if all the positive control point values are 1 and all the negative
control points are 0.

3.3 Cost Metrics in Reversible Logic

A number of metrics are used to evaluate the efficiency of reversible circuits. Some of the
commonly used cost metrics of reversible circuits include gate count, garbage output, constant
input and quantum cost which are described below:

3.3.1 Gate Count (GC)

Gate count is one of the measures used to compare and evaluate different logic circuits. Gate count
refers to the number of logic gates used to implement a traditional or reversible circuit. However,
gate count does not evaluate the complexity of logic circuits. For example, let us consider two
reversible circuits where the first circuit consists of three 3-bit Toffoli gates and the second circuit
consists of two 6-bit Toffoli gates. In this case, the gate count measurement will indicate that the
second circuit uses fewer gates and therefore, is preferable compared to the first circuit. However,
as discussed in Section 2.3.4 a 6-bit Toffoli gate is more complex than a 2-bit Toffoli gate. Since
the gates have a different number of input bits, a simple gate count measure fails to fully evaluate
the complexity of the circuits. Gate count can be useful to compare different circuits consisting of
similar types of gates.

3.3.2 Garbage Output (GO)

Garbage output is another measure for comparing and evaluating reversible circuits. As
demonstrated in Section 2.1, it is sometimes necessary to add extra outputs in order to main- tain

reversibility.. For example, in Table 3.1c Garbageout1 and Garbageout2 are the garbage outputs.

However, adding garbage outputs adds extra lines and, therefore increases the circuit width.
According to Maslov , reducing the garbage outputs is more important than reducing the gate
count.

1
3.3.3 Constant Input (CI)

The number of constant inputs is another metric used to evaluate and compare imple- mentations.
Constant inputs are also known as ancilla inputs . Constant inputs are the input lines that are
added to a function to make it reversible. The relationship between garbage outputs and constant
inputs is given by the following equation:

inputs + ancilla inputs = outputs + garbage

3.3.4 Quantum Cost (QC)

Quantum cost is an important measure to evaluate and compare the cost of reversible circuits.

Quantum cost refers to the number of 1 × 1 or 2 × 2 (1 input−1 output, 2 input−2 output)

quantum

gates required to design a circuit. It is assumed that all reversible gates will be implemented at the

quantum level by basic 1 × 1 or 2 × 2 quantum gates . The quantum costs of the reversible gates
used for the examples and in designing the fault tolerant reversible circuits in this thesis are
shown
in Table 3.5.

Table 3.5 Quantum cost of some reversible gates.

Size Garb Name Quantum

(n) age Cost
1 0 NOT 1
2 0 positive-controlled 1
CNOT
2 0 negative-controlled 3
CNOT
3 0 Toffoli, 5
C2NOT
4 0 Toffoli, 13
C3NOT
5 0 Toffoli, 29
C4NOT
5 2 Toffoli, 26
C4NOT
6 0 Toffoli, 61
C5NOT
3 0 positive-controlled 5
Fredkin
1
3 0 negative-controlled 5
Fredkin

1
and t = xn is the target line. For n = 1, n = 2, and n = 3 the gates are called NOT , CNOT , and
C2NOT or Toffoli, respectively. A Cn−1NOT gate has an exponential cost of 2n − 3 only if the gate
has zero garbage lines with all positive controls.

• The quantum cost of an n − 1 negative-control Toffoli gate with at least one positive-
control is the same as the cost of an n − 1 positive-control Toffoli gate.

• The quantum cost of an n − 1 negative-control Toffoli gate with at least one

positive- control is the same as the cost of an n − 1 positive-control Toffoli gate.

• If all the controls of a Toffoli gate are negative an extra cost of 2 is added if zero or
(n − 3) garbage lines are used.

According to , a size n Fredkin gate can be simulated efficiently by a size n Toffoli gate and 2
CNOT gates. Thus, the cost of a size n Fredkin gate is calculated by the QC of a size n Toffoli
gate + 2. The quantum cost for different sizes of Toffoli and Fredkin gates is determined from the
gate implementation technique. In our calculations, the quantum cost of the generalized Toffoli
and Fredkin gates is taken from . However, the quantum cost for any of the gates, as given in ,
may change in the future as new technologies are developed.

3.4 Fault, Failures and Errors

Every system or module is designed for a specific output behaviour. When the system is in
service its behaviour can be observed and compared with a reference system. A system failure
denotes that the system is unable to perform its intended function because of an er-ror. According
to Laprie , “a system failure occurs when the delivered service no longer complies with the
specifications”. A fault can be defined as a physical or functional flaw that occurs within some
hardware or software components. A fault may occur due to the design errors, mistakes in system
specification or implementation, manufacturing problems or other external disturbances. In
general, faults can be classified as a) hard (permanent) or b) soft (transient). Hard faults result
from the physical changes of components. A determi-nate fault (‘stuck at zero’or ‘stuck at one’)
within a

1
digital logic circuit can be considered to be a hard fault. Soft faults can occur due to temporary
changes in the properties of logic cir-cuits. External influences such as electromagnetic
interference, noise in the power supply, or improper functioning of a circuit may result in soft
faults within a system.

An error is a manifestation of a fault. In a digital system, if the logical state of an element differs
from the intended value this indicates an error. It can be stated that a failure is the result of an
error, caused by a fault. This could be illustrated as:

Fault → Error → Failure

3.5 Fault Tolerance in Reversible Logic

In traditional logic, fault tolerance has become increasingly important due to the wide- spread
use of computers. Fault tolerance is a design attribute that enables a system to per- form the
intended operation even in the presence of a fault. The incorporation of fault tol- erance into a
design is an important approach to achieve reliable performance. Approaches to fault tolerance
techniques in traditional logic are described in. This thesis focuses on fault tolerance in reversible
logic.
One approach for achieving fault tolerance both in traditional and reversible logic is to introduce
redundancy. For designing fault tolerant reversible circuits this thesis work uses the concept of
redundancy. Readers are referred to section 3.6 for details on redundancy and the basic concept of
our approach. The concepts of fault detection, fault location, fault recovery, and fault masking are
important in the design of a fault tolerant system. These concepts are described in the following
subsections.

3.5.1 Fault Detection

A fault detection process identifies the occurrences of faults within a circuit. To ensure proper
functioning of the circuit, faults must be detected as early as possible .

3.5.2 Fault Location

1
 The process of fault location or fault diagnosis occurs after fault detection. Fault loca- tion is
the process of determining where a fault has occured (i.e. the physical location of the fault within
the circuit) .

3.5.3 Fault Recovery

Fault recovery is the process of keeping the circuit operational or restoring circuit oper- ation
after a fault has occured. A fault recovery process may require some reconfiguration of the circuit
.

3.5.4 Fault Masking

Fault masking is the process of preventing faults from introducing errors into the system.
Common approaches to fault masking include majority voting techniques for structural
redundancy or error correcting memories for correcting memory before a circuit uses the data .

3.6 BASIC ADDERS:

The gate used in implementing a reversible ripple-carry full adder is the TSG gate . The
TSG gate functions like a full adder. A reversible ripple-carry adder is faster than the non-
reversible adder, since the computation of carry in a reversible adder does not require the
computation of previous stage carry (as indicated in the critical paths). When previous stage carry
is being forwarded in the reversible adder, the computation of previous stage carry and
computation regarding sum is done simultaneously whereas in an irreversible adder the next stage
carry cannot start any computation till previous stage carry is fully generated. The critical paths of
4bit reversible and irreversible ripple- carry adders are as shown in fig.6 and fig.7.

1
 Fig 3.4 Critical path of 4-bit reversible adder and irreversible adder.

Furthermore, various parameters of reversible and non reversible adders were observed and
compared and are tabulated in Table 3.6.
Table 3.6 Comparsion of reversible and irreversible RCA.

2
 CHAPTER 4: PROPOSED SYSTEM
Here, we center around HUB groups. Center Fixed-point organizations were utilized to
improve DSP usage, since they permit better word-length advancement. The ASIC execution of
HUB-FP units has been read for binary16 (half), binary32 (single), and binary64 (twofold), and
significant enhancements have been accomplished. In this short correspondence, we stretch out
this examination to FPGAs over a wide scope of sizes. Contrasted with past articles, we give: An
exploratory blunder examination of the execution of FIR channels, which shows that the HUB
approach gives comparable measurable parameters to those of standard FP usage, including the
SNR. The consequences of FPGA usage of an essential FP snake and multiplier for a wide scope
of example and mantissa bit-widths under HUB and ordinary methodologies and their
examination. In the majority of the cases examined, the HUB arrangement lessens asset use and
expands the speed of these FP units. Besides, because of its effortlessness, any current delicate or
hard Core could be effectively upgraded by utilizing the proposed methodology. Subsequently, in
light of essential designs, our point is to urge scientists to improve their upgraded FP centers or
DSP
As the number of control inputs increases the quantum cost for the reversible gates also increases.
For example, a 3-bit positive control Toffoli gate has a quantum cost of 5, whereas a 6-bit Toffoli
gate has a cost of 61 . The quantum cost calculation of an n-bit Toffoli gate is presented in.
According to Arabzadeh et al. :

• A multiple control Toffoli gate with n − 1 controls and the nth bit as the target can be
written as Cn−1NOT (c;t), where c = {x1 ,...,xn−1} ⊂ X is the set of control lines.

A fundamental general engineering to work HUB-FP numbers is appeared in Fig. 1, where a

traditional FP math unit has been helpfully altered. Right off the bat, the ILSBs are attached to the
mantissas of the information operands before utilizing them. As result they are changed over to
regular configuration. Next, an ordinary information way is utilized, however from the outset the
mantissa information way must be onepiece more extensive. Since the conclusive outcome is in
HUB design, a straightforward truncation is performed for adjusting. Along these lines, after the
math activity itself, customary standardization rationale is used, yet no watchman bit is given at
the yield. The adjusting rationale of the regular engineering is just dispensed with (crossed out in
Fig. 1). Considering that the ILSB is a consistent, this general design could be additionally
streamlined relying upon the particular engineering.
21
 Fig 4.1 HUB Floating-point adder
Elliptic curve cryptography (ECC) is an asymmetric cryptographic system that provides an
equivalent security to the well-known Rivest, Shamir and Adleman system with much smaller key
sizes. The basic operation in ECC is scalar point multiplication, where a point on the curve is
multiplied by a scalar. A scalar point multiplication is performed by calculating series of point
additions and point doublings. Using their geometrical properties, points are added or doubled
through series of additions, subtractions, multiplications, and divisions of their respective
coordinates. Point coordinates are the elements of finite fields closed under a prime or an
irreducible polynomial. Various ECC processors have been proposed in the literature that either
target binary fields, prime fields, or dual field operations. In prime field ECC processors, carry
free arithmetic is necessary to avoid lengthy data paths caused by carry propagation. Redundant
schemes, such as carry save arithmetic (CSA), redundant signed digits (RSDs), or residue number
systems (RNSs), have been utilized in various designs. Carry logic or embedded digital signal
processing (DSP) blocks within field programmable gate arrays (FPGAs) are also utilized in some
designs to address the carry propagation problem. It is necessary to build an efficient addition data
path since it is a fundamental operation employed in other modular arithmetic operations. Modular
multiplication is

22
an essential operation in ECC. Two main approaches may be employed. The first is known as
interleaved modular multiplication using Montgomery’s method. Montgomery multiplication is
widely used in implementations where arbitrary curves are desired. Another approach is known as
multiply-then-reduce and is used in elliptic curves built over finite fields of Messene primes.
Messene primes are the special type of primes which allow for efficient modular reduction
through series of additions and subtractions. In order to optimize the multiplication process, some
ECC processors use the divide and conquer approach of Karatsuba–Of man multiplications, where
others use embedded multipliers and DSP blocks within FPGA fabrics.

Fig 4.2 Overall processor architecture

External data enter the processor through the external bus to the 256 RSD digits input bus. Data
are sent in binary format and a binary to RSD converter stuffs zeros in between the binary bits in
order to create the RSD representation. Hence, 256-bits binary represented integers are converted
to 512- bits RSD represented integers. To convert RSD digits to binary format, one needs to
subtract the negative component from the positive component of the RSD digit.

23
 Fig 4.3 Modular addition subtraction block diagram

In order to overcome the problem of overflow introduced in the adder proposed in, a new
adder is proposed based on the work proposed in. The proposed adder consists of two layers,
where layer 1 generates the carry and the interim sum, and layer 2 generates the sum, as shown in
Fig. 3. Table I shows the addition rules that are performed by layer 1 of the RSD adder, where
RSD digits 0, +1, and −1 are represented by Z, P, and N, respectively. It works by assuring that
layer 2 does not generate overflow through the use of previous digits in layer 1. The proposed
adder is used as the main block in the modular addition component to take advantage of the
reduced overflow feature. However, overflow is not an issue in both the multiplier and the divider
when an RSD adder is used as an internal block. Hence, the reduced area is taken as an advantage
in instantiating adders within the multiplier and the divider. The n-digits modular addition is
performed by three levels of RSD addition. Level 1 performs the basic addition of the operands
which produces n+1 digits as a result. If the most significant digit (MSD) of level 1 output has a
value of 1/−1, then level 2 adds/subtracts the modulo P256 from the level 1 output
correspondingly. The result of level 2 RSD addition has n+2 digits; however, only the n+1th digit
may have a value of 1/−1. This assertion is backed up by the fact that the operation of level 2 is
a reversed operation with the modulo P256, and most

24
importantly, the proposed adder assures that no unnecessary overflow is produced. If the n+1th
digit of level 2 result has a value 1 or −1, then level 3 is used to reduce the output to the n-digit
range. Algorithm 3 shows the sequence of operations performed by the modular addition block.
Notice that one modular addition is performed within one, two, or three clock cycles.

The proposed processor was implemented in Xilinx Virtex 5-XC5VLX110T FPGA and a
single point multiplication for P256 is achieved within 2.26 ms. Detailed implementation results
of individual blocks are listed in Table V. Such detailed results are useful in understanding the
main block contributors to the overall hardware resources. It can be noted that the modular
multiplier is the largest block within the design due to the three recursively built Karatsuba blocks,
which operate in parallel. With the extensive pipelining techniques that are applied to the
Karatsuba blocks, the CPD is shortened down to 6.24 ns. Such CPD figure allows the processor to
operate at 160 MHz, which is the fastest achieved in the literature in FPGA devices without
embedded blocks. Detailed timing performance of operations performed by the processor that is
operating at 160 MHz on Virtex 5 device are listed in Table VI. Table VII lists a comparison of
our modular divider implementation results against other FPGA-based designs. Our modular
divider performs the fastest timing of prime field dividers and competitive to binary field GF2233
modular divider. The performance enhancement is due to the usage of RSD, which leads to short
data path and high operating frequency. Efficient architecture that is based on implementing
complex operations through simple shifting single bit checking is another factor that gives our
divider such enhancement. Finally, the modular divider operates on higher radix which results in
improved throughput. The exportability feature of the processor comes from the fact that none of
the macros or embedded blocks within the FPGA fabric is utilized in the proposed processor.
Such feature gives our processor the freedom to be implemented in different FPGA devices from
different vendors and, eventually, as an application-specified integrated circuit (ASIC).

25
 CHAPTER 5:REVERSIBLE MAJORITY VOTER CIRCUITS
This chapter proposes a passive hardware fault tolerance technique and two new designs for a
majority voter circuit (MVC). A comparison of the proposed and existing designs is presented. In
addition, the performance of the proposed designs is presented as well as the overall costs in
terms of the cost metrics used in reversible logic.

5.1 Fault Tolerant Reversible Circuits

Most of the literature that propose fault tolerant reversible circuits provide only
fault detection mechanisms [19, 23, 45, 52]. However, for a circuit to be fault tolerant the
de- tected faults must also be corrected or masked. In this thesis we use a passive
hardware redundancy technique to achieve fault tolerance in reversible circuits. Passive
hardware redundancy techniques tolerate faults without the need of fault detection or
system recon- figuration. Unlike active hardware redundancy, passive hardware
redundancy techniques do not need to locate and correct a fault. Passive hardware
redundancy techniques generally use the concept of fault masking. Fault masking in a
passive hardware fault tolerant system saves the additional cost of fault location and
correction, while still resulting in an online fault tolerant approach. Details on passive
hardware redundancy techniques are provided in Chapter 2 of this thesis. All of the
passive fault masking techniques proposed for reversible logic [7, 43, 61] require
replication of modules. The most commonly used form of passive hardware redundancy
is a triple modular redundancy (TMR) technique . Readers are referred to Chapter 2 for
details on TMR. The basic concept of TMR is to use three identical hardware modules
and a voter circuit. The voter circuit provides an output with the value of the majority of
the input bits. Therefore, in the case of a fault resulting in an error in the value of one of
the inputs to the voter, the majority voter masks the fault and produces an output based
on the remaining fault free modules. Since fault masking is done by voting rather than
comparison or fault correction the entire functionality of a TMR-based design depends
on the majority voter circuit (MVC) .

26
5.1.1 Reversible Majority Voter Circuits in the Literature

There are only three works in the literature that propose reversible majority voter cir-cuits.
Boykin and Roychowdhury describe a reversible fault tolerant design using the concept of a
traditional 3-bit repetition code. Their technique introduces a multiplexing scheme and a voting
mechanism. A reversible MVC is used to generate the majority value of the input bits. The
proposed voter consists of two CNOT gates and one Toffoli gate as shown in Figure 5.1. This
voter provides the majority bit at the output line x. For example, if the input bits abc have the
values 100 then the value at line x is 0, which is the value of the majority of the input bits.

Figure 5.1: Reversible majority voter circuit .

The reversible multiplexing scheme proposed in introduces an error recovery circuit as shown
in Figure 5.2. The error recovery circuit uses six blocks of the majority voter circuit of Figure 5.1
for a total of eight operations. Functionality of the error recovery circuit is described using two
phases: encoding and decoding.

If an input bit has a logical value of 0 or 1, the encoding blocks map the bit to an expanded value

of 000 or 111. In other words, the MVC−1 blocks triplicate each input bit. The MVC blocks in
Figure
5.2 perform decoding and generate the majority value at each of the three designated output lines.
If there are no errors, the outputs of Figure 5.2 should match the inputs. In case of a fault, at most
one bit in each of the MVC outputs is altered and indicates an error. Since the MVCs in Figure 5.2
return the majority bit values of the encoded bits, a single error will not affect the majority bit
values at the outputs. In practical use, this error recovery cycle would be placed strategically
throughout the circuit interspersed with computations.

27
 Figure 5.2 Reversible fault tolerant multiplexing scheme .

The MVC in Figure 5.1 uses three reversible gates and therefore, the gate count for this circuit
is 3. Since the design does not require any additional inputs the number of constant inputs for this
voter is zero. The design of this MVC produces 2 garbage outputs. The MVC consists of two
positive-controlled CNOT gates and one positive-controlled 3-bit Toffoli gate. Thus, the total QC
of

this design is (1 + 1 + 5) = 7.
A 3-bit reversible majority voter circuit is proposed in [43]. Researchers in this study designate
a specific output line to carry the majority value. The proposed design is shown in Figure 5.3.

Figure 5.3 Reversible majority voter circuit.

For example, let us consider an input bit combination abc = 011. For this combination the control

28
bit value of the first gate is 0. This passes the bits to the second gate without any changes. The
second gate has its control bit at 1 and swaps the first and second input bits. This provides the
majority value of 1 at the output (on line p). The MVC presented in Figure 5.3 consists of a 2-
CNOT and a 3- bit Fredkin gate and does not require any constant input. The gate count of this

MVC is 2 with a QC of (1 + 5) = 6.

Figure 5.4 Majority voter with triplicated voter outputs proposed .

Another MVC proposed in [61] takes three input bits from three identical modules and provides
the majority line on all three outputs. In other words, the majority value is replicated on three
output

lines. In order to maintain reversibility, two control lines (C1 = 1, C2 = 0) are added at the voter

input and two garbage lines (G1, G2) are added with the voter outputs. Voting is done on the data
inputs

(a, b and c), and the goal is to produce all 0s or 101 and the control lines are set to C1 = 1, C2 =

0, this generates the value 111 at the data outputs xyz as shown in Figure 5.5. The number of
constant input and garbage output for the voter presented in Figure 5.4 is 2 and 2, respectively. The
circuit in Figure 5.4 uses 4 reversible gates which results in a gate count of 4. The QC of the
circuit

in Figure 5.4 is (5 + 5 + 5 + 1) = 16.

29
 Figure 5.5 Example of input assignments

5.2 Proposed Reversible Majority Voter Circuits

In this section we propose two designs for a 3-bit reversible majority voter. For a n × n
reversible circuit we can designate any of the output lines as an output line of interest [43, 7] and
consider
the rest of the outputs to be garbage. The voter circuit behaviour is characterized by the truth table
shown in Table 5.1.

Figure 5.6 MVC with two reversible gates.

30
 Table 5.1 Truth table of the majority voter with two reversible
gates.

after 1st gate after 2nd gate

abc a1b1c1 a2b2c2
000 010 010
001 001 001
010 000 000
011 011 110
100 110 011
101 101 101
110 101 101
111 111 111

The reversible MVC shown in Figure 5.6 consists of a negative control CNOT and a positive

control Fredkin gate. The output of interest is a2 which gives the majority of input bits (shown in

Table 5.1). The other two output lines are not used and are considered to be garbage lines. To

demonstrate the behaviour of this circuit, let us consider an input combination of abc = 100. As we
can see from Figure 5.6, the control of the Fredkin gate is (c ⊕ b). When c = b, (c ⊕ b) = 0 and the
Fredkin gate does not swap the values of a and c at the output. However, when c /= b then (c ⊕ b)
= 1, and the Fredkin gate operates and swaps the values of a and c at the output. Thus, the gate
count for this circuit is 2 and the design does not require any constant input. The QC of a negative-
controlled CNOT gate and a positive-controlled Fredkin gate is 3 and 5 respectively . Thus, the

QC of the circuit in Figure 5.6 is (3 + 5) = 8.

The second MVC we propose consists of three reversible gates: a positive control Tof- foli, a
negative control CNOT and a positive control Fredkin gate. For this circuit the output of interest is a3

and the rest are garbage outputs. The truth table shown in Table 5.2 demon- strates the bit

combinations at each gate output. This 3×3 reversible majority voter circuit provides the same
output as our design proposed in Figure 5.6. However, the MVCs pre- sented in Figure 5.6 and
Figure 5.7 differ in their fault tolerance mechanism. The functional difference of the proposed
voters is described in Section 3.5.

31
 The gate count for this circuit is 3 and the design does not require any constant in- put. The
QC of a positive-controlled Toffoli gate, a negative-controlled CNOT gate and a positive-
controlled

Fredkin gate is 3, 5, and 5 respectively . Thus, the QC of the circuit in Figure 3.7 is (5 + 3 + 5) =

13. 13.

5.2.1 Fault Tolerant Reversible Circuit Design

Our proposed voter circuits can be used with TMR to achieve fault tolerance for any

reversible circuit. For example, let us consider a 3×3 reversible logic circuit consisting of a 2-bit

Toffoli and

a CNOT gate. This circuit is shown in Figure 3.8a where x is the output of interest and y and z are
garbage outputs. In accordance with the basic principles of TMR we need three versions of the
circuit in Figure 3.8a for designing a fault tolerant reversible circuit.

(a) A reversible circuit. (b) Fault tolerant design of the circuit using TMR.

Figure 5.8 Fault tolerant reversible circuit design.

In this case, let us consider the two-gate voter circuit shown in Figure 5.6. If any one of the
modules is faulty, the majority voter masks the fault and sends the corrected output on line u. A
fault tolerant design of the circuit in Figure 5.8a is shown in Figure 5.8b. A full adder circuit is
considered to be a fundamental building block of many computational logic units. Figure 5.9
shows a fault tolerant full adder design using two majority voter circuits. For a full adder circuit
32
we have two functional outputs: Sum and Carry.

33
 Output lines carrying the Sum from the triplicated modules are connected to the majority
voter 1 and the Carry output lines are connected to the majority voter 2. To assure fault tolerance,
the circuit needs to mask the fault at both of these two output lines. Corrected Sum and Carry bits
are generated at Corrected Sum and Corrected Carry output lines as shown in Figure 5.9. Figure
5.9 also demonstrates the use of both of our proposed voter circuits in this example, although we
note that any voter circuit could be used in either place.

Figure 5.7 Reversible fault tolerant full adder circuit design.

34
 CHAPTER 6: SOFTWARE REQURIMENT

6.1 Migrating Projects from Previous ISE Software Releases:

When you open a project file from a previous release, the ISE® software prompts you to
migrate your project. If you click Backup and Migrate or Migrate Only, the software automatically
converts your project file to the current release. If you click Cancel, the software does not convert
your project and, instead, opens Project Navigator with no project loaded.
Note: After you convert your project, you cannot open it in previous versions of the ISE software,
such as the ISE 11 software. However, you can optionally create a backup of the original project as
part of project migration, as described below.

To Migrate a Project

1. In the ISE 12 Project Navigator, select File > Open Project.

2. In the Open Project dialog box, select the .xise file to migrate.
Note You may need to change the extension in the Files of type field to display .npl (ISE 5 and ISE
6 software) or .ise (ISE 7 through ISE 10 software) project files.
3. In the dialog box that appears, select Backup and Migrate or Migrate Only.
4. The ISE software automatically converts your project to an ISE 12 project.
Note If you chose to Backup and Migrate, a backup of the original project is created at
project_name_ise12migration.zip.
5. Implement the design using the new version of the software.

Note Implementation status is not maintained after migration.

6.2 Properties:

For information on properties that have changed in the ISE 12 software, see ISE 11 to ISE 12
Properties Conversion.

6.3 IP Modules:

35
 If your design includes IP modules that were created using CORE Generator™ software or
Xilinx® Platform Studio (XPS) and you need to modify these modules, you may be required to
update the core. However, if the core netlist is present and you do not need to modify the core,
updates are not required and the existing netlist is used during implementation.

6.4 Obsolute Source File Types:

The ISE 12 software supports all of the source types that were supported in the ISE 11
software.
If you are working with projects from previous releases, state diagram source files (.dia),
ABEL source files (.abl), and test bench waveform source files (.tbw) are no longer supported.
For state diagram and ABEL source files, the software finds an associated HDL file and adds it to
the project, if possible. For test bench waveform files, the software automatically converts the
TBW file to an HDL test bench and adds it to the project. To convert a TBW file after project
migration, see Converting a TBW File to an HDL Test Bench.

6.5 Using ISE Example Projects:

To help familiarize you with the ISE® software and with FPGA and CPLD designs, a set
of example designs is provided with Project Navigator. The examples show different design
techniques and source types, such as VHDL, Verilog, schematic, or EDIF, and include different
constraints and IP.

To Open an Example

1. Select File > Open Example.

2. In the Open Example dialog box, select the Sample Project Name.
Note To help you choose an example project, the Project Description field describes each
project. In addition, you can scroll to the right to see additional fields, which provide
details about the project.
3. In the Destination Directory field, enter a directory name or browse to the directory.
4. Click OK.

36
 The example project is extracted to the directory you specified in the Destination Directory
field and is automatically opened in Project Navigator. You can then run processes on the
example project and save any changes.
Note If you modified an example project and want to overwrite it with the original
example project, select File > Open Example, select the Sample Project Name, and specify the
same Destination Directory you originally used. In the dialog box that appears, select Overwrite
the existing project and click OK.

6.6 Creating a Project:

Project Navigator allows you to manage your FPGA and CPLD designs using an ISE®
project, which contains all the source files and settings specific to your design. First, you must
create a project and then, add source files, and set process properties. After you create a project,
you can run processes to implement, constrain, and analyze your design. Project Navigator
provides a wizard to help you create a project as follows.
Note If you prefer, you can create a project using the New Project dialog box instead of
the New Project Wizard. To use the New Project dialog box, deselect the Use New Project
wizard option in the ISE General page of the Preferences dialog box.

To Create a Project

1. Select File > New Project to launch the New Project Wizard.
2. In the Create New Project page, set the name, location, and project type, and click Next.
3. For EDIF or NGC/NGO projects only: In the Import EDIF/NGC Project page, select the
input and constraint file for the project, and click Next.
4. In the Project Settings page, set the device and project properties, and click Next.
5. In the Project Summary page, review the information, and click Finish to create the project

Project Navigator creates the project file (project_name.xise) in the directory you specified.
After you add source files to the project, the files appear in the Hierarchy pane.

6.7 Design panel:

Project Navigator manages your project based on the design properties (top-level
module type, device type, synthesis tool, and language) you selected when you created the project.

37
It organizes all the parts of your design and keeps track of the processes necessary to move the
design from design entry through implementation to programming the targeted Xilinx® device.
Note For information on changing design properties, see Changing Design Properties.
You can now perform any of the following:

 Create new source files for your project.

 Add existing source files to your project.

 Run processes on your source

files. Modify process properties.

VERILOG

Hardware description languages such as Verilog differ from software programming

languages because they include ways of describing the propagation of time and signal
dependencies (sensitivity). There are two assignment operators, a blocking assignment (=), and a
non-blocking (<=) assignment. The non-blocking assignment allows designers to describe a
state- machine update without needing to declare and use temporary storage variables (in any
general programming language we need to define some temporary storage spaces for the
operands to be operated on subsequently; those are temporary storage variables). Since these
concepts are part of Verilog's language semantics, designers could quickly write descriptions of
large circuits in a relatively compact and concise form. At the time of Verilog's introduction
(1984), Verilog represented a tremendous productivity improvement for circuit designers who
were already using graphical schematic capture software and specially-written software
programs to document and simulate electronic circuits.

The designers of Verilog wanted a language with syntax similar to the C programming
language, which was already widely used in engineering software development. Verilog is case-
sensitive, has a basic preprocessor (though less sophisticated than that of ANSI C/C++), and
equivalent control flow keywords (if/else, for, while, case, etc.), and compatible operator
precedence. Syntactic differences include variable declaration (Verilog requires bit-widths on

38
net/regtypes), demarcation of procedural blocks (begin/end instead of curly braces {}), and many
other minor differences.

A Verilog design consists of a hierarchy of modules. Modules encapsulate design hierarchy, and
communicate with other modules through a set of declared input, output, and bidirectional ports.
Internally, a module can contain any combination of the following: net/variable declarations
(wire, reg, integer, etc.), concurrent and sequential statement blocks, and instances of other
modules (sub- hierarchies). Sequential statements are placed inside a begin/end block and
executed in sequential order within the block. But the blocks themselves are executed
concurrently, qualifying Verilog.

39
 CHAPTER 7 :RESULT

40
41
42
 CHAPTER 8: CONCLUSION & FUTURE SCOPE
CONCLUSION
In conclusion, unbiased rounding for hub floating point addition offers numerous advantages,
such as fairness, accuracy, and consistency in calculations. It helps minimize bias and rounding
errors, ensuring more precise and reliable results. However, it's important to consider potential
disadvantages, such as increased computational complexity and resource requirements. The
decision to implement unbiased rounding should be based on the specific needs and trade-offs of
each application. By carefully evaluating these factors, we can determine whether the benefits of
unbiased rounding outweigh the potential drawbacks.
FUTURE SCOPE
Future scope of unbiased rounding for hub floating point addition, there are a few potential
areas of development. One area is the exploration of more advanced algorithms and techniques
that can further minimize bias and rounding errors. Researchers and developers can continue to
refine and optimize existing methods, as well as propose new approaches to enhance the
accuracy and precision of floating point addition. Additionally, there is room for improvement in
terms of performance and efficiency. As technology advances, hardware and software
optimizations can be implemented to reduce the computational overhead associated with
unbiased rounding. This can lead to faster and more efficient calculations without compromising
on accuracy. Overall, the future looks promising for unbiased rounding in hub floating point
addition, with ongoing research and advancements aimed at improving its effectiveness and
practicality.

43
 CHAPTER 9: APPENDIX

SOURCE CODE

module d3_8bit_top;

// Inputs

reg [7:0] a;

reg [7:0] b;

reg ci;

reg ctrl;

// Outputs

wire [8:0] s_d;

// Instantiate the Unit Under Test (UUT)

revesable_rca_8bit_d3 uut (

.a(a),

.b(b),

.ci(ci),

.ctrl(ctrl),

.s_d(s_d)

);

initial begin

// Initialize Inputs

a = 10;

b = 10;

44
 ci = 1;

ctrl = 0;

// Wait 100 ns for global reset to finish

#100;

a = 10;

b = 5;

ci = 1;

ctrl = 1;

#100;

a = 13;

b = 6;

ci = 0;

ctrl = 1;

#100;

a = 15;

b = 7;

ci = 1;

ctrl = 0;

#100 $finish;

// Add stimulus here

end

endmodule

45
 CHAPTER 10: BIBLIOGRAPHY

[1] E. Alpaydin, Machine learning: the new AI, 2016

[2] M. Kubat, An Introduction to Machine Learning, 2015, no. August.
[3] J. A. Stankovic, “Research directions for the internet of things,” IEEE Internet of
Things Journal, vol. 1, no. 1, pp. 3–9, feb 2014.
[4] F. K. Shaikh, S. Zeadally, and E. Exposito, “Enabling technologies for green Internet
of Things,” IEEE Systems Journal, vol. PP, no. 99, pp. 983–994, jun 2015.
[5] R. Murphy, T. Sterling, and C. Dekate, “Advanced architectures and execution models to
support green computing,” Computing in Science and Engineering, vol. 12, no. 6, pp. 38–47, nov
2010.
[6] P. P. Pande, A. Ganguly, and K. Chakrabarty, Design technologies for green and sustainable
computing systems, P. P. Pande, A. Ganguly, and K. Chakrabarty, Eds. New York, NY:
Springer New York, 2013.
[7] Synopsys, “DWFC Flexible Floating-Point Overview,” no. August, pp. 1–6, 2016.
[8] “IEEE standard for floating-point arithmetic,” IEEE Std 754-2008, pp. 1 –58, 29 2008.
[9] J. Hormigo and J. Villalba, “New formats for computing with real numbers under round-to-
nearest, “IEEE Transactions on Computers, vol. 65, no. 7, pp. 2158–2168, 2016.
[10] D. R. Lutz and N. Burgess, “Overcoming doublerounding errors under IEEE 754-2008
using software,” in 2010 Conference Record of the Forty Fourth Asilomar Conference on
Signals, Systems and Computers. IEEE, nov 2010, pp. 1399–1401.
[11] J. Hormigo and J. Villalba, “Measuring Improvement When Using HUB Formats to
Implement Floating-Point Systems under Round-to-Nearest,” IEEE Transactions on Very Large-
Scale Integration (VLSI) Systems, vol. 24, no. 6, pp. 2369–2377, 2016.
[12] H. L. Garner, “A survey of some recent contributions to computer arithmetic,”
IEEE Transactions on Computers, vol. C-25, no. 12, pp. 1277–1282, Dec 1976.
[13] W. J. Cody, “Static and dynamic numerical characteristics of floating-point
arithmetic,” IEEE Transactions on Computers, vol. C-22, no. 6, pp. 598– 601, June 1973.
[14] J. F. Reiser and D. E. Knuth, “Evading the drift in floating-point addition,” Information
Processing Letters, vol. 3, no. 3, pp. 84–87, jan 1975.
[15] H. Hilton, “Bias-free rounding in digital signal processing,” Apr. 22 2004, US Patent App.

46
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48
49
50
51
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53
54
55
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 CHAPTER 10 BIBLIOGRAPHY

[1] E. Alpaydin, Machine learning: the new AI, 2016

[2] M. Kubat, An Introduction to Machine Learning, 2015, no. August.
[3] J. A. Stankovic, “Research directions for the internet of things,” IEEE Internet of
Things Journal, vol. 1, no. 1, pp. 3–9, feb 2014.
[4] F. K. Shaikh, S. Zeadally, and E. Exposito, “Enabling technologies for green Internet
of Things,” IEEE Systems Journal, vol. PP, no. 99, pp. 983–994, jun 2015.
[5] R. Murphy, T. Sterling, and C. Dekate, “Advanced architectures and execution models to
support green computing,” Computing in Science and Engineering, vol. 12, no. 6, pp. 38–47, nov
2010.
[6] P. P. Pande, A. Ganguly, and K. Chakrabarty, Design technologies for green and sustainable
computing systems, P. P. Pande, A. Ganguly, and K. Chakrabarty, Eds. New York, NY:
Springer New York, 2013.
[7] Synopsys, “DWFC Flexible Floating-Point Overview,” no. August, pp. 1–6, 2016.
[8] “IEEE standard for floating-point arithmetic,” IEEE Std 754-2008, pp. 1 –58, 29 2008.
[9] J. Hormigo and J. Villalba, “New formats for computing with real numbers under round-to-
nearest, “IEEE Transactions on Computers, vol. 65, no. 7, pp. 2158–2168, 2016.
[10] D. R. Lutz and N. Burgess, “Overcoming doublerounding errors under IEEE 754-2008
using software,” in 2010 Conference Record of the Forty Fourth Asilomar Conference on
Signals, Systems and Computers. IEEE, nov 2010, pp. 1399–1401.
[11] J. Hormigo and J. Villalba, “Measuring Improvement When Using HUB Formats to
Implement Floating-Point Systems under Round-to-Nearest,” IEEE Transactions on Very Large-
Scale Integration (VLSI) Systems, vol. 24, no. 6, pp. 2369–2377, 2016.
[12] H. L. Garner, “A survey of some recent contributions to computer arithmetic,”
IEEE Transactions on Computers, vol. C-25, no. 12, pp. 1277–1282, Dec 1976.
[13] W. J. Cody, “Static and dynamic numerical characteristics of floating-point
arithmetic,” IEEE Transactions on Computers, vol. C-22, no. 6, pp. 598– 601, June 1973.
[14] J. F. Reiser and D. E. Knuth, “Evading the drift in floating-point addition,” Information
Processing Letters, vol. 3, no. 3, pp. 84–87, jan 1975.

61
[15] H. Hilton, “Bias-free rounding in digital signal processing,” Apr. 22 2004, US Patent
App. 10/277,419.
[16] J. Villalba-Moreno, “Digit recurrence floatingpoint division under HUB format,” 23rd
IEEE Symposium on Computer Arithmetic, Silicom Valley (California, USA), July 2016.
[17] M. D. Ercegovac and T. Lang, Digital Arithmetic. Morgan Kaufmann, San Francisco, 2004.

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