UNIT 5: Memory
Management
Operating System Concepts – 9th Edition Silberschatz, Galvin and Gagne ©2013
Memory
2 Important module of computer system
•CPU
•Memory
Memory
•Size (More)
•Access Time(Less)
•Per unit cost(Less)
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Memory
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Memory Management Strategies
● Strategies divided into several categories
1. Fetch Strategies
● Decide which piece of data to be loaded next
2. Placement Strategies
● Where in MM to Place incoming data
3. Replacement Strategies
● Decide which data to remove from MM
Operating System Concepts – 9th Edition 8.4 Silberschatz, Galvin and Gagne ©2013
Logical vs. Physical Address Space
● The concept of a logical address space that is bound to a
separate physical address space is central to proper memory
management
● Logical address – generated by the CPU; also referred to as
virtual address
● Physical address – address seen by the memory unit
● Logical address space is the set of all logical addresses
generated by a program
● Physical address space is the set of all physical addresses
generated by a program
Operating System Concepts – 9th Edition 8.5 Silberschatz, Galvin and Gagne ©2013
Memory-Management Unit (MMU)
● Hardware device that at run time maps virtual to physical address
Is called memory management unit(MMU)
● Base register now called relocation register
● The value in relocation register is added to every address
generated by the user process(ie CPU)
● The user program deals with logical addresses; it never sees the
real physical addresses
● Execution-time
binding occurs
when reference is made
to location in memory
● Logical address bound
to physical addresses Silberschatz, Galvin and Gagne ©2013
Operating System Concepts – 9th Edition 8.6
Background
● Program must be brought (from disk) into memory and placed within a
Main Memory for it to be run
● Main memory and registers are only storage CPU can access directly
● Protection of memory required to ensure correct operation
● A pair of base and limit registers define the logical address space
● CPU must check every memory access generated in user mode to be
sure it is between base and limit for that user
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Hardware Address Protection
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Hardware Support for Relocation and Limit Registers
Because every address generated by a CPU is checked against these
registers, we can protect both the operating system and the other
users programs and data from being modified by this running process.
Operating System Concepts – 9th Edition 8.9 Silberschatz, Galvin and Gagne ©2013
Swapping
● A process can be swapped temporarily out of memory to a
backing store(secondary memory), and then brought back into
memory(MM) for continued execution
● Roll out, roll in – swapping variant used for priority-based
scheduling algorithms; lower-priority process is swapped out so
higher-priority process can be loaded and executed
● Major part of swap time is transfer time; total transfer time is
directly proportional to the amount of memory swapped
● If next processes to be put on CPU is not in memory, need to
swap out a process and swap in target process
● Context switch time can then be very high
Operating System Concepts – 9th Edition 8.10 Silberschatz, Galvin and Gagne ©2013
Schematic View of Swapping
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Non-Contiguous
Static
Dynamic
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Contiguous Allocation
● The main memory must accommodate both the operating system
and the various user processes. Limited resource, must allocate
efficiently
● In contiguous memory allocation, each process is contained in a
single contiguous section of memory.
● Contiguous allocation is one early method
● Main memory usually into two partitions:
● Resident operating system, usually held in low memory
● User processes then held in high memory
● Each process contained in single contiguous section of
memory
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Continues Memory Allocation
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Advantage and Disadvantage of Fixed
Memory partition
● Advantage
This scheme is simple and is easy to implement
It supports multiprogramming as multiple processes can be
stored inside the main memory.
Management is easy using this scheme
● Disadvantage
Internal Fragmentation
Limitation on the size of the process
External Fragmentation
Degree of multiprogramming is less
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Variable Partitioning
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Advantage and Disadvantage of Variable
size Memory partition
● Advantage
No Internal Fragmentation
Degree of Multiprogramming is Dynamic
No Limitation on the Size of Process
● Disadvantage
External Fragmentation
Difficult Implementation
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Contigues Allocation Algorithm
● First fit-
• Allocate the first hole that is big enough.
• Searching can start either at the beginning of the set of holes
or at the location where the previous first-fit search ended.
• We can stop searching as soon as we find a free hole that is
large enough.
● Best fit.-
• Allocate the smallest hole that is big enough.
• We must search the entire list, unless the list is ordered by
size.
• This strategy produces the smallest leftover hole.
Operating System Concepts – 9th Edition 8.19 Silberschatz, Galvin and Gagne ©2013
● Worst fit.-
• Allocate the largest hole. Again, we must search the entire
list, unless it is sorted by size.
• This strategy produces the largest leftover hole, which may be
more useful than the smaller leftover hole from a best-fit
approach.
Operating System Concepts – 9th Edition 8.20 Silberschatz, Galvin and Gagne ©2013
Dynamic Storage-Allocation Problem
How to satisfy a request of size n from a list of free holes?
● First-fit: Allocate the first hole that is big enough
● Best-fit: Allocate the smallest hole that is big enough; must search
entire list, unless ordered by size
● Produces the smallest leftover hole
● Worst-fit: Allocate the largest hole; must also search entire list
● Produces the largest leftover hole
First-fit and best-fit better than worst-fit in terms of speed and storage utilization
Operating System Concepts – 9th Edition 8.21 Silberschatz, Galvin and Gagne ©2013
Fragmentation
● External Fragmentation – total memory space exists to satisfy a
request, but it is not contiguous
● Internal Fragmentation – allocated memory may be slightly larger
than requested memory; this size difference is memory internal to
a partition, but not being used
● Reduce external fragmentation by compaction
● Shuffle memory contents to place all free memory together in
one large block
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Paging
● Paging is a memory-management scheme that permits Physical
address space of a process can be noncontiguous;
● process is allocated physical memory whenever the space is available
● Avoids external fragmentation
● Avoids problem of varying sized memory chunks
● Divide physical memory into fixed-sized blocks called frames
● Size is power of 2, between 512 bytes and 16 Mbytes
● Divide logical memory(Process) into blocks of same size called pages
● Keep track of all free frames
● To run a program of size N pages, need to find N free frames and load
program
● Set up a page table to translate logical to physical addresses
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Address Translation Scheme
● Address generated by CPU is divided into:
● Page number (p) – used as an index into a page table
which contains base address of each page in physical
memory
● Page offset (d) – combined with base address to define
the physical memory address that is sent to the
memory unit
● For given logical address space 2m and page size 2n
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Paging Hardware
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Paging Model of Logical and Physical Memory
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Paging Example
n=2 and m=4 32-byte memory and 4-byte pages
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Paging (Cont.)
● Calculating internal fragmentation
● Page size = 2,048 bytes
● Process size = 72,766 bytes
● 35 pages + 1,086 bytes
● Internal fragmentation of 2,048 - 1,086 = 962 bytes
Operating System Concepts – 9th Edition 8.30 Silberschatz, Galvin and Gagne ©2013
Free Frames
Before allocation After allocation
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Operating System Concepts – 9th Edition 8.32 Silberschatz, Galvin and Gagne ©2013
Implementation of Page Table
● Page table is kept in main memory
● Page-table base register (PTBR) points to the page table
● Page-table length register (PTLR) indicates size of the page
table
● In this scheme every data/instruction access requires two
memory accesses
● One for the page table and one for the data / instruction
● The two memory access problem can be solved by the use of
a special fast-lookup hardware cache called associative
memory or translation look-aside buffers (TLBs)
Operating System Concepts – 9th Edition 8.33 Silberschatz, Galvin and Gagne ©2013
Associative Memory
● Associative memory – parallel search
● Address translation (p, d)
● If p is in associative register, get frame out
● Otherwise get frame from page table in memory
Operating System Concepts – 9th Edition 8.34 Silberschatz, Galvin and Gagne ©2013
Paging Hardware With TLB
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Effective Access Time
● Paging scheme using TLB. TLB access time 10 ns and
memory access time takes 50ns . What is effective
memory access time (in ns) if TLB hit ratio is 90% and
there is no page fault
EMAT=hit(TLB access time +Main Memory access)+miss( TLB
access time +Page Table access time+ Main Memory
access)
=90%(10+50) + 10%(10+50+50)
=
Operating System Concepts – 9th Edition 8.36 Silberschatz, Galvin and Gagne ©2013
Memory Protection
● Memory protection implemented by associating protection bit
with each frame to indicate if read-only or read-write access is
allowed
● Can also add more bits to indicate page execute-only, and
so on
● Valid-invalid bit attached to each entry in the page table:
● “valid” indicates that the associated page is in the process’
logical address space, and is thus a legal page
● “invalid” indicates that the page is not in the process’
logical address space
● Or use page-table length register (PTLR)
● Any violations result in a trap to the kernel
Operating System Concepts – 9th Edition 8.37 Silberschatz, Galvin and Gagne ©2013
Valid (v) or Invalid (i) Bit In A Page Table
Operating System Concepts – 9th Edition 8.38 Silberschatz, Galvin and Gagne ©2013
Segmentation
● Memory-management scheme that supports user view of
memory
● A program is a collection of segments
● A segment is a logical unit such as:
main program
procedure
function
method
object
local variables, global variables
common block
stack
symbol table
arrays
Operating System Concepts – 9th Edition 8.39 Silberschatz, Galvin and Gagne ©2013
User’s View of a Program
Operating System Concepts – 9th Edition 8.40 Silberschatz, Galvin and Gagne ©2013
Segmentation Architecture
● Logical address consists of a two tuple:
<segment-number, offset>,
● Segment table – maps two-dimensional physical addresses; each
table entry has:
● base – contains the starting physical address where the
segments reside in memory
● limit – specifies the length of the segment
● Segment-table base register (STBR) points to the segment
table’s location in memory
● Segment-table length register (STLR) indicates number of
segments used by a program;
Operating System Concepts – 9th Edition 8.41 Silberschatz, Galvin and Gagne ©2013
Logical View of Segmentation
4
1
3 2
4
user space physical memory space
Operating System Concepts – 9th Edition 8.42 Silberschatz, Galvin and Gagne ©2013
Segmentation Hardware
Operating System Concepts – 9th Edition 8.43 Silberschatz, Galvin and Gagne ©2013
End of Chapter 8
Operating System Concepts – 9th Edition Silberschatz, Galvin and Gagne ©2013