High-Performance Monolayer WSe2 p/n FETs via Antimony-Platinum

Modulated Contact Technology towards 2D CMOS Electronics

Ang-Sheng Chou1+*, Yu-Tung Lin1,3+, Yuxuan Cosmi Lin2, Ching-Hao Hsu1,3, Ming-Yang Li1, San-Lin Liew4, Sui-An Chou1,
Hung-Yu Chen2, Hsin-Yuan Chiu1,5, Po-Hsun Ho1, Ming-Chun Hsu3, Yu-Wei Hsu3, Ning Yang2, Wei-Yen Woon6, Szuya
Liao6, Duen-Huei Hou4, Chao-Hsin Chien5, Wen-Hao Chang7, Iuliana Radu1, Chih-I Wu3, H.-S. Philip Wong1 and Han Wang2*
1
Corporate Research, TSMC, Hsinchu, Taiwan; 2Corporate Research, TSMC, San Jose, CA, USA; 3Graduate Institute of Photonics and Optoelectronics, NTU,
Taipei, Taiwan; 4Quality & Reliability, TSMC, Hsinchu, Taiwan; 5Institute of Electronics, NYCU, Hsinchu, Taiwan; 6Pathfinding, TSMC, Hsinchu, Taiwan;
2022 IEEE International Electron Devices Meeting (IEDM) | 978-1-6654-8959-1/22/$31.00 ©2022 IEEE | DOI: 10.1109/IEDM45625.2022.10019491

7
Department of Electrophysics, NYCU, Hsinchu, Taiwan +Both authors contributed equally; *Email: [email protected], [email protected]

Abstract – Low resistance contact technology for 2D channel capping/doping technologies are developed for 1L WSe2
semiconductors is a key bottleneck for the practical application of pFET and nFET, respectively, to further boost the device
2D channel materials at advanced logic nodes. This work presents performance. (iv) The proposed device technologies have led to
a novel Sb-Pt modulated contact technology which can alleviate the hysteresis-free I-V characteristics, low SB heights close to thermal
Fermi-level pinning effect and mediate the band alignment at the voltage at room temperature, record low RC value down to 0.75
metal-2D semiconductor interface, leading to exceptional ohmic kΩ∙μm and 1.8 kΩ∙μm and high on-state current of 151 μA/μm and
contacts for both p-type and n-type WSe2 FETs (p/n FET). WSe2 147 μA/μm, for 1L WSe2 pFETs and nFETs, respectively.
FETs with different Sb/Pt contact compositions, in combination II. APPROACH
with new oxide-based encapsulation/doping technologies, exhibits
record low pFET contact resistance of 0.75 kΩ∙μm among all A. Bi-Assisted Dry Transfer of Wafer-Scale WSe2
reported monolayer (1L) 2D pFETs. The nFET contact resistance Throughout this study, 1L WSe2 was used as the channel material,
of 1.8 kΩ∙μm is also the lowest among 1L WSe2 nFETs. Both 1L grown by CVD. CVD-1L-WSe2 was transferred onto 100 nm SiNx/Si
WSe2 pFET and nFET demonstrated remarkable on-state p/n substrates by a new version of the bismuth (Bi)-assisted dry transfer
current ~150 μA/μm at |VD|=1 V, indicating the potential of WSe2 technology that we previously developed in-house [5], with novel
for CMOS applications. A new version of the semi-automated dry modifications using a new Bi/PMMA/TRT interfacial stack
transfer process for chemical vapor deposition (CVD) WSe2 was (schematic shown in Fig. 1). This semi-automated transfer process
also developed utilizing a novel Bi/PMMA/TRT support stack, utilizes the weakly coupled interface between semimetal Bi and
offering low defect wrinkle-free WSe2 transfer at wafer-scale. WSe2 to minimize the introduction of additional defects during the
transfer process, while the new PMMA/TRT support stack offers
I. INTRODUCTION
balanced adhesion property and mechanical flexibility to achieve
2D semiconducting transition metal dichalcogenides (TMD) are wrinkle-free transfer at large wafer-scale. Atomic force microscopy
promising as atomically thin channel materials for future post-silicon (AFM, Fig. 2b), and Raman spectrum/photoluminescence (PL) (Fig.
CMOS transistor technology at the ultimate scale [1]. However, 3) were conducted to characterize the surface cleanliness, roughness,
achieving low resistance contact for 2D semiconductor p/n FETs and uniformity of the material before and after the transfer process.
remains a crucial challenge towards such technology insertion at
advanced technology nodes. Recent development of semimetallic B. Devices Fabrication and Charecterization
contacts (e.g. Bi [2] and Sb [3]) as well as low-melting-point metal As described in Fig. 4, after dry-transfer, Helium-ion-beam
contacts (e.g. Sn and In) [4] have demonstrated reduction in contact lithography was used to pattern the S/D contact electrodes. Sb with
resistance (RC) and good performance for nFETs. However, the different thicknesses and Pt capping layers were deposited by e-
performances of pFETs made with TMDs are still one to two orders beam evaporation and followed by lift-off to form the contact
of magnitude lower, because these proposed contact metals for TMD electrodes. Then MoOx and SiONx were deposited on top as the
nFETs have improper band alignments for hole conductions, leading encapsulating layers, to achieve almost hysteresis-free pFET and
to high Schottky barrier (SB), high RC and poor current-delivery nFET, respectively. The I-V characteristics were measured in
capability. WSe2 has been proposed as a promising TMD with vacuum system with Keysight B1500A parameter analyzer. Raman
ambipolar conduction characteristics, and the recent development of spectra was utilized to examine the interface coupling between the
reliable and scalable synthesize and transfer technologies for TMDs, contact metal and WSe2, and energy-dispersive X-ray spectroscopy
including monolayer WSe2, have paved the way towards practical (EDS) in a scanning transmission electron microscope (STEM) was
applications. In this work, we develop a contact modulation used to reveal chemical compositions at the contact interfaces.
technology based on Sb-Pt stacked deposition, which can relieve the III. RESULTS
Fermi-level pinning effect and offers work function tuning with
different chemical compositions. This technology, in combination
A. Sb-Pt Contact Engineering for WSe2 p/n FETs
with proper channel capping layers, gives rise to low RC for both WSe2 with semimetal contact such as Bi has shown promising
electron and hole conductions towards enabling high performance nFET device characteristics. To reduce the contact resistance and
CMOS technologies based on monolayer CVD WSe2. The key achieve better WSe2 pFET performance, it is critical to identify
contributions of this work are four-folds: (i) a new version of semi- contact metals with appropriate work functions and weaker Fermi-
automated wafer-scale low defect transfer process based on Bi level pinning effect because of metal-induced gap sates (MIGS).
interfacial layers and PMMA/TRT support layer is demonstrated; (ii) We discover that by mixing thin layer semimetal Sb with the high-
Sb semimetal is mixed with high work function metal Pt as a work-function metal Pt, both issues can be effectively addressed,
modulated contact technology for monolayer WSe2, which enables which offers improved contact and better on-state performance for
low RC for both pFETs and nFETs; (iii) new MoOx and SiONx both nFETs and pFETs made with monolayer WSe2.

Authorized licensed use limited to: Universitaetsbibliothek der RWTH Aachen. Downloaded on November 29,2023 at 13:05:56 UTC from IEEE Xplore. Restrictions apply.
978-1-6654-8959-1/22/$31.00 ©2022 IEEE 7.2.1
146
 Fig. 5 summarizes typical transfer (ID-VG) characteristics of interface trap states passivation, and (ii) modulation doping. First,
pristine short-channel (LCH = 100 nm) WSe2 FETs with different Sb the capping layers are able to neutralize the trap states, making the
and Pt compositions and with Pd contact as the baseline device. Pd device characteristics almost hysteresis-free (Fig. 11). Second,
is selected as the control material throughout this study because modulation doping as well as an enhancement of on-state currents
direct deposition of pure Pt on WSe2 is known to suffer from can be induced by the MoOx and SiONx capping layer for pFET and
adhesion issue, and Pd has similar work function as Pt and can serve nFET, respectively.
as good reference. Depending on the Sb-to-Pt ratio, either p-branch After Sb-Pt contact engineering and capping layer engineering,
current or n-branch current is improved by one and two orders of we report high-performance I-V characteristics for both nFET and
magnitude, respectively, as compared to the Pd-contact device. It is pFET with monolayer WSe2. The output characteristics for the 1L
observed that device with thinner Sb on WSe2 shows stronger pFET WSe2 pFET and nFET are shown in Fig. 12 and Fig. 15, respectively.
behavior, whereas device with thicker Sb exhibits nFET behavior. The on-state current for pFET (contact metal: 10 nm Sb/12nm Pt;
We believe that the Sb-Pt contact plays two vital roles in capping: 10 nm MoOx ) is 151 μA/μm (VD = -1 V) and the on-state
achieving such improved pFET and nFET performance. First, the current for nFET (contact metal: 30 nm Sb/12nm Pt; capping: 30 nm
insertion of Sb provides a buffer layer in between WSe2 and the SiONx) is 147 μA/μm (VD = 1 V).
high-work-function Pt metal, which minimizes lattice damage to C. Contact Resistance and Schottky Barrier Height
WSe2 during Pt metal deposition, and alleviates the metal-WSe2
Both Y-function method (YFM) and transfer-length method
interactions. To confirm this effect, Sb/WSe2 and Pd/WSe2
(TLM) are used to estimate the contact resistances of the optimized
reference heterostructure samples are prepared for Raman
1L WSe2 pFET and nFET (Fig. 13, 14, and 16). According to YFM,
spectroscopy measurements [6], and the results are presented in Fig.
the contact resistances RC are extracted to be 0.9 kΩ·μm for the pFET
6. The Raman characteristic peak of WSe2 becomes wider and much
with MoOx capping, and 1.8 kΩ·μm for the nFET with SiONx
weaker after 1.5 nm Pd is deposited on top. The Pd/PMMA/WSe2
capping. In addition, we also employ the TLM method for the pFET
sample displays a similar Raman intensity to the pristine WSe2
to give a more accurate RC extraction since YFM method typically
sample, ruling out the possibility that 1.5 nm Pd may block the
tends to overestimate the contact resistance. Using TLM, the contact
incident light and attenuate the local light field on WSe2 during the
resistance is extracted to be 0.75 kΩ·μm for the 1L WSe2 pFET.
Raman spectroscopy measurement. Hence, some level of disruption
To extract the Schottky barrier heights ФSB at the p-type and n-
of the WSe2 lattice is induced after the deposition of conventional
type contacts of the p/n FETs, transfer characteristics are measured
high work-function metals such as Pd, possibly through defect
at different temperatures (from 100 K to 300 K), as plotted in Fig.
introduction or interfacial chemical bonding. Both effects can lead
17. It is observed that the drain currents for both the pFET and the
to severe Fermi-level pinning effects, including defect induced gap
nFET decrease at lower temperature, which suggest that the transport
states (DIGS) and MIGS. By contrast, the Raman peak of Sb/WSe2
characteristics for both devices are dominated by the ФSB at the metal
sample do not exhibit any intensity or width change, indicating less
contacts. ФSB can be extracted by finding the slopes of the Arrhenius
disruption caused to the WSe2 lattice by semimetal Sb than Pd.
plots (ln(ID/T1.5) versus 1/T) as shown in Fig. 18 (a). The ФSB as
Second, the interfacial properties, especially the effective work
functions of the gate voltage for the pFET and the nFET are
functions at the Sb-Pt/WSe2 interfaces can be modulated by the Sb-
summarized in Fig. 18 (b), which is the comprehensive result after
to-Pt ratio, which contributes to the nFET-to-pFET conversion.
considering the barrier width change caused by doping effect. Using
Cross-sectional STEM images and the corresponding EDS
this novel Sb-Pt modulated contact technology, the contact barriers
mappings on the Sb/Pt contact regions of WSe2 FETs are shown in
are small for both pFET and nFET at room temperature.
Fig. 7. It is worth noting that partial re-sublimation of Sb may take
place during the Pt evaporation because of heating, resulting in D. Benchmark
slightly smaller thickness of the actual Sb layers than the target Fig. 19 and 20 benchmark the ION as a function of channel length
deposition thickness. Another interesting observation is that mixing among our work and previous studies of monolayer CVD and
between Sb and Pt may occur at the metal/WSe2 interface especially exfoliated WSe2 FETs [7-17]. The on-state current for both our pFET
when thinner Sb (10 nm) is deposited (Fig. 7 b and c). The Sb-Pt and nFET are among the highest reported in the literature with the
mixing can modulate its effective work function, and thus the nFET current being record value among CVD 1L WSe2 nFET. Our
contact barrier at the metal/WSe2 interface. Note that the work reported pFET RC is the lowest among all monolayer 2D pFETs
function of pristine Sb and Pt are 4.4 eV and 5.6 eV, respectively, while the nFET RC is also the lowest among 1L CVD WSe2 nFETs,
and the Sb-Pt mixed layer could have an effective work function in as shown in Fig. 21. These devices exhibit high performance and low
between, which can result in the polarity modulation of the WSe2 contact resistance with minimal hysteresis for both pFETs and
FETs when the deposition thickness of Sb changes. nFETs, and are hence a promising technology for developing WSe2
Fig. 8 and 9 show the output (ID-VD) characteristics of the best FETs toward 2D CMOS electronics for advanced logic.
nFET and pFET for pristine WSe2 with Sb 10 nm/Pt 12 nm and Sb ACKNOWLEDGMENT: AFM was supported by Taiwan Instrument Research Institute.
30 nm/Pt 12 nm as the contact electrodes, respectively. The Helium-ion beam lithography was supported by TSMC-NTU Joint Research Center
relationship between the p-branch and n-branch on-currents and the and Ministry of Science and Technology (Grant No. MOST 110-2622-8-002-014).
different Sb/Pt compositions are summarized in Fig. 10. REFERENCES: [1] Q. Cheng, et al., InfoMat., 2, 4, 656 (2020). [2] P.-C. Shen, et al.,
Nature, 593, 211 (2021). [3] A.-S. Chou, et al., IEDM, 7.2.1 (2021). [4] A. Kumar, et
B. p/n FET Performance Boosting with Channel Modulation al., IEDM, pp. 7.3.1 (2021). [5] M.-Y. Li, et al., VLSI, T1-5 (2022). [6] W. Yalon, et
al., Nano Lett., 17, 6, 3429 (2017). [7] C.-C. Chiang, et al., IEEE EDL, 43, 2, 319
To further boost the on-state current for both the pFETs and the
(2022). [8] M. Yamamoto, et al., Nano Lett., 16, 4, 2720 (2016). [9] P. Zhao, et al.,
nFETs, we capped the WSe2 channels with different dielectric layers: ACS Nano, 8, 10, 10808 (2014). [10] K. Maxey, et al., VLSI, (2022). [11] Y. Jung, et
10 nm MoOx deposited by e-beam evaporation for pFETs, and 30 al., Nature Elec., 2, 187 (2019). [12] Y. Wang, et al., Nature, 568, 70 (2019). [13] B.
nm SiONx deposited by atomic layer deposition (ALD) for nFETs. Liu, et al., ACS Nano, 10, 5, 5153 (2016). [14] S. Rai, et al., JAP, 131, 094301 (2022).
[15] C.-S. Pang, et al., Small, 15, 41, 1902770 (2019). [16] W. Liu, et al., Nano Lett.,
The presence of capping layers leads to two beneficial impacts: (i) 13, 5, 1983 (2013). [17] L. Kong, et al., Nat. Comm., 11, 1866 (2020).

Authorized licensed use limited to: Universitaetsbibliothek der RWTH Aachen. Downloaded on November 29,2023 at 13:05:56 UTC from IEEE Xplore. Restrictions apply.
7.2.2
147
 Fig. 1. Schematic of the Bi-assisted semi-auto transfer Fig. 2. (a) Photograph of 2” CVD-1L-WSe2 Fig. 3. (a) Raman and (b) PL spectra of the
facility capable of handling up to 200 mm wafers. The transferred on 4” SiNx (100 nm)/p++-Si wafer. (b) transferred WSe2 on SiNx/Si substrate, showing
technology is further improved in this work by using AFM images of the SiNx/Si substrate alone and after uniform Raman and PL peak positions at all nine
thermal release tape (TRT) and PMMA to enhance WSe2 film is transferred, showing comparable locations of the 2” region in Fig. 2(a), demonstrating
transfer quality. surface roughness. the uniform quality of the transferred WSe2 material.

Fig. 4. Key process steps and schematic diagram of Fig. 5. Transfer characteristics (ID-VG) of the Pd- Fig. 6. Raman spectra of pristine 1L-WSe2, and those
the back-gated CVD 1L-WSe2 device fabrication with contacted and different compositions of Sb/Pt- capped with 1.5 nm Sb, Pd, and Pd/PMMA. WSe2 Raman
contact metal and encapsulation splits. Photo of the contacted 1L-WSe2 FETs at |VD| = 1V. The device peak becomes distorted in the sample directly capped
wafer after device fabrication is also shown. characteristics without encapsulation are ambipolar. with Pd, but remains intact in the Sb capped sample.

Fig. 7. High resolution cross-sectional STEM images and EDS mapping of (a) Pd. Pd is selected as the control p-type contact material because direct deposition of
pure Pt on WSe2 is known to suffer from adhesion issue, and Pd has similar work function as Pt and can serve as good reference, and (b-e) different compositions of
Sb/Pt contacted on 1L CVD WSe2. Note: (b) 10 nm Sb with 25 nm Pt, (c) 10 nm Sb with 12 nm Pt, (d) 20 nm Sb with 12 nm Pt, (e) 30 nm Sb with 12 nm Pt. Thinner
Sb intermixes more vigorously with Pt, resulting in more complete alloying of Sb and Pt.

Fig. 8. Output characteristics (ID-VD) of 1L- Fig. 9. Output characteristics (ID-VD) of 1L- Fig. 10. Changes in the p/n FETs performance with
WSe2 pFET (LCH = 100 nm) with 10 nm Sb + 12 WSe2 nFET (LCH = 100 nm) with 30 nm Sb + different contact compositions. 10 nm Sb + 12 nm
nm Pt of S/D contacts. 12 nm Pt of S/D contacts. Pt contact gives the best pFET performance.

Authorized licensed use limited to: Universitaetsbibliothek der RWTH Aachen. Downloaded on November 29,2023 at 13:05:56 UTC from IEEE Xplore. Restrictions apply.
7.2.3
148
 Fig. 11. Transfer characteristics (ID-VG) of the Fig. 12. Output characteristics (ID-VD) Fig. 13. Extraction of contact resistance by Y-
Sb/Pt-1L-WSe2 FET (LCH = 100 nm) at |VD| = 1 V, corresponding to bright-green-line in Fig. 11, i.e. function method for the Sb10Pt12-WSe2-pFET
before and after MoOx (Green) and SiONx (Pink) Sb/Pt:10/12 nm after MoOx capping. after MoOx capping.
encapsulation.

Fig. 14. Extraction of RC by TLM analysis for the Fig. 15. Output characteristics (ID-VD) Fig. 16. Extraction of contact resistance by Y-
MoOx capped 1L WSe2 pFET with carrier density corresponding to the pink-line in Fig. 11, i.e. function method for the Sb30Pt12-WSe2-nFET
modulated by the gate. RC = 0.75 kΩ∙µm is extracted Sb/Pt:30/12 nm after SiONx capping. after SiONx capping.
at carrier density p2D ~ 8.7x1012 cm-2.

Fig. 17. Temperature-dependent measurement of pFET Fig. 18. (a) Arrhenius plots of MoOx-capped-pFET (green) and SiONx-capped-nFET (red) at different gate
(Green) and nFET (red). The current levels in both overdrive (|VG| from 6 to 30 V, in step of 1 V). (b) The energy barrier of pFET (green) and nFET (red) are
devices decrease at lower temperature. close to be negligible at room temperature. kB is Boltzmann constant.

Fig. 19. Benchmark of ION at VD = -1 V for 1L WSe2 Fig. 20. Benchmark of ION at VD = 1 V for 1L WSe2 Fig. 21. Comparison of contact resistance for 1L WSe2
pFETs. The open and filled symbols are pristine and nFETs. The open and filled symbols are pristine p/n-FETs with respect to different contact approaches
doped samples, respectively. and doped samples, respectively. reported in the literature.

Authorized licensed use limited to: Universitaetsbibliothek der RWTH Aachen. Downloaded on November 29,2023 at 13:05:56 UTC from IEEE Xplore. Restrictions apply.
7.2.4
149