Application Note: SY8113B

High Efficiency, 500kHz, 3A, 18V Input

Synchronous Step Down Regulator

General Description Features

The SY8113B is a high efficiency 500 kHz • low RDS(ON) for internal switches (top/bottom):
synchronous step-down DC-DC converter capable of 80mΩ/40mΩ
delivering 3A current. The SY8113B operates over a • 4.5-18V input voltage range
wide input voltage range from 4.5V to 18V and • 3A output current capability
integrates main switch and synchronous switch with • 500 kHz switching frequency
very low RDS(ON) to minimize the conduction loss. • Instant PWM architecture to achieve fast transient
responses.
Low output voltage ripple and small external inductor • Cycle-by-cycle peak current limitation
and capacitor sizes are achieved with 500 kHz
• Internal softstart limits the inrush current
switching frequency. It adopts the instant PWM
• ±1.5% 0.6V reference
architecture to achieve fast transient responses for high
step down applications • TSOT23-6 package

Ordering Information Applications

SY8113 □(□□)□
Temperature Code • Set Top Box
Package Code • Portable TV
Optional Spec Code • Access Point Router
Temperature Range: -40°C to 85°C • DSL Modem
Ordering Number Package type Note • LCD TV
SY8113BADC TSOT23-6 --

Typical Applications

Figure 1. Schematic Diagram Figure 2. Efficiency Figure

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Pinout (top view)

BS LX

GND IN

FB EN

TSOT23-6(FC)
Top Mark: WCxyz, (Device code: WC, x=year code, y=week code, z= lot number code)

Pin Name Pin Number Pin Description

BS 1 Boot-Strap Pin. Supply high side gate driver. Decouple this pin to LX pin with
0.1uF ceramic cap.
GND 2 Ground pin
FB 3 Output Feedback Pin. Connect this pin to the center point of the output resistor
divider (as shown in Figure 1) to program the output voltage:
Vout=0.6*(1+R1/R2)
EN 4 Enable control. Pull high to turn on. Do not float.
IN 5 Input pin. Decouple this pin to GND pin with at least 1uF ceramic cap
LX 6 Inductor pin. Connect this pin to the switching node of inductor

Absolute Maximum Ratings (Note 1)

Supply Input Voltage ------------------------------------------------------------------------------------------------ 19V
Enable Voltage---------------------------------------------------------------------------------------------- VIN + 0.3V
FB Voltage ----------------------------------------------------------------------------------------------------------- 4V
Power Dissipation, PD @ TA = 25°C, TSOT23-6（FC）----------------------------------------------------- 1W
Package Thermal Resistance (Note 2)
θ JA ------------------------------------------------------------------------------------------------------ 100°C /W
θ JC ----------------------------------------------------------------------------------------------------- 11.2°C /W
Junction Temperature Range ----------------------------------------------------------------------------------- 150°C
Lead Temperature (Soldering, 10 sec.) ----------------------------------------------------------------------- 260°C
Storage Temperature Range ------------------------------------------------------------------------- -65°C to 150°C

Recommended Operating Conditions (Note 3)

Supply Input Voltage ---------------------------------------------------------------------------------------------- 4.5V to 18V
Junction Temperature Range ----------------------------------------------------------------------------------- -40°C to 125°C
Ambient Temperature Range ----------------------------------------------------------------------------------- -40°C to 85°C

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Electrical Characteristics
(VIN = 12V, VOUT = 1.2V, L = 2.2uH, COUT = 47uF, TA = 25°C, IOUT = 1A unless otherwise specified)

Parameter Symbol Test Conditions Min Typ Max Unit

Input Voltage Range VIN 4.5 18 V
Quiescent Current IQ IOUT=0, VFB=VREF*105% 100 µA
Shutdown Current ISHDN EN=0 5 10 µA
Feedback Reference VREF 0.591 0.6 0.609 V
Voltage
FB Input Current IFB VFB=3.3V -50 50 nA
Top FET RON RDS(ON)1 80 90 mΩ
Bottom FET RON RDS(ON)2 40 50 mΩ
Top FET PeakCurrent ILIM,TOP 6 A
Limit
Bottom FET Valley ILIM 3 4.25 A
Current Limit
EN Rising Threshold VENH 1.5 V
EN Falling Threshold VENL 0.4 V
Input UVLO Threshold VUVLO 4.5 V
UVLO Hysteresis VHYS 0.3 V
Min ON Time 50 80 120 ns
Min OFF Time 140 170 220 ns
Switching Frequency 500 kHz
Soft-start Time tSS 800 uS
Thermal Shutdown TSD 150 °C
Temperature
Thermal Shutdown THYS 15 °C
Hysteresis

Note 1: Stresses beyond the “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

Note 2: θ JA is measured in the natural convection at TA = 25°C on a low effective 4-layer thermal conductivity test
board of JEDEC 51-3 thermal measurement standard. Pin2 of TSOT23-6 packages is the case position for θ JC
measurement.

Note 3: The device is not guaranteed to function outside its operating conditions

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Block Diagram

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Typical Performance Characteristics
Efficiency vs. Load Current
100

95

90

85

80
VIN=6V,VOUT=5V
VIN=12V,VOUT=5V
75 VIN=16V,VOUT=5V

70
0.01 0.10 1.00 10.00

Load Current (A)

Efficiency vs. Load Current

95

90

85

80

75

70 VIN=5V,VOUT=1.2V
VIN=12V,VOUT=1.2V
65 VIN=16V,VOUT=1.2V

60
0.01 0.10 1.00 10.00

Load Current (A)

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Short Circuit Protection Short Circuit Protection

(VIN=12V, VOUT=3.3V, Open to Short) (VIN=12V, VOUT=3.3V, 3A to Short)

VOUT 2V/div VOUT 2V/div

IL 1A/div

IL 1A/div

Time (2ms/div) Time (2ms/div)

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To minimize the potential noise problem, place a

Operation typical X5R or better grade ceramic capacitor really
close to the IN and GND pins. Care should be taken to
SY8113B is a synchronous buck regulator IC that
minimize the loop area formed by CIN, and IN/GND
integrates the PWM control, top and bottom switches
pins. In this case, a 10uF low ESR ceramic capacitor is
on the same die to minimize the switching transition
recommended.
loss and conduction loss. With ultra low Rds(on) power
switches and proprietary PWM control, this regulator
Output capacitor COUT:
IC can achieve the highest efficiency and the highest
The output capacitor is selected to handle the output
switch frequency simultaneously to minimize the
ripple noise requirements. Both steady state ripple and
external inductor and capacitor size, and thus achieving
transient requirements must be taken into consideration
the minimum solution footprint.
when selecting this capacitor. For the best performance,
it is recommended to use X5R or better grade ceramic
SY8113B provides protection functions such as cycle
capacitor greater than 22uF capacitance.
by cycle current limiting and thermal shutdown
protection. SY8113B will sense the output voltage
Output inductor L:
conditions for the fault protection.
There are several considerations in choosing this
inductor.
Applications Information 1) Choose the inductance to provide the desired
ripple current. It is suggested to choose the ripple
Because of the high integration in the SY8113B IC, the current to be about 40% of the maximum output
application circuit based on this regulator IC is rather current. The inductance is calculated as:
simple. Only input capacitor CIN, output capacitor COUT,
output inductor L and feedback resistors (R1 and R2) VOUT (1 − VOUT /VIN, MAX )
L=
need to be selected for the targeted applications FSW × IOUT, MAX × 40%
specifications.
where Fsw is the switching frequency and IOUT,MAX is
Feedback resistor dividers R1 and R2: the maximum load current.
The SY8113B regulator IC is quite tolerant of different
Choose R1 and R2 to program the proper output voltage. ripple current amplitude. Consequently, the final choice
To minimize the power consumption under light loads, of inductance can be slightly off the calculation value
it is desirable to choose large resistance values for both without significantly impacting the performance.
R1 and R2. A value of between 10kΩ and 1MΩ is 2) The saturation current rating of the inductor must
highly recommended for both resistors. If Vout is 3.3V, be selected to be greater than the peak inductor
R1=100k is chosen, then using following equation, R2 current under full load conditions.
can be calculated to be 22.1k:
VOUT
VOUT(1-VOUT/VIN,MAX)
0.6V ISAT, MIN > IOUT, MAX +
R2 = R1 . 0.6VFB
R1 2 ⋅ FSW ⋅ L
VOUT − 0.6V
3) The DCR of the inductor and the core loss at the
GND R2
switching frequency must be low enough to
achieve the desired efficiency requirement. It is
desirable to choose an inductor with DCR<50mΩ
Input capacitor CIN:
to achieve a good overall efficiency.
The ripple current through input capacitor is calculated
External Boostrap Cap
as： This capacitor provides the gate driver voltage for
internal high side MOSEFET. A 100nF low ESR
I CIN _ RMS = I OUT ⋅ D(1 − D) . ceramic capacitor connected between BS pin and LX
pin is recommended.
BS
CB
100nF

LX
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Load Transient Considerations: 1) It is desirable to maximize the PCB copper area
The SY8113B regulator IC integrates the compensation connecting to GND pin to achieve the best thermal and
components to achieve good stability and fast transient noise performance. If the board space allowed, a
responses. In some applications, adding a 22pF ceramic ground plane is highly desirable.
cap in parallel with R1 may further speed up the load
transient responses and is thus recommended for 2) CIN must be close to Pins IN and GND. The loop
applications with large load transient step requirements. area formed by CIN and GND must be minimized.

3) The PCB copper area associated with LX pin must

be minimized to avoid the potential noise problem.

4) The components R1 and R2, and the trace connecting

to the FB pin must NOT be adjacent to the LX net on
the PCB layout to avoid the noise problem.

5) If the system chip interfacing with the EN pin has a

Layout Design: high impedance state at shutdown mode and the IN pin
is connected directly to a power source such as a Li-Ion
The layout design of SY8113B regulator is relatively battery, it is desirable to add a pull down 1Mohm
simple. For the best efficiency and minimum noise resistor between the EN and GND pins to prevent the
promblem, we should place the following components noise from falsely turning on the regulator at shutdown
close to the IC: CIN, L, R1 and R2. mode.

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TSOT23-6L (FC)Package outline & PCB layout
1.90
2.80 - 3.10
2.40

1.50 - 1.70
2.70 - 3.00
1.00

0.95 0.60 0.30 - 0.50

Recommended Pad Layout

0.01 - 0.1
0.1 - 0.20

1.00 (max)
0.25 REF

0.95 TYP
0.3 - 0.6 1.90 TYP

Notes: All dimension in MM

All dimension don’t not include mold flash & metal burr

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Taping & Reel Specification
1. Taping orientation
TSOT23-6
3.9/4.1 1.45/1.55
7.7/8.3

Feeding direction
2. Carrier Tape & Reel specification for packages
Reel
Width

Reel
Size

Tape
Package Pocket Reel size Reel Trailer Leader length Qty per
width
types pitch(mm) (Inch) width(mm) length(mm) (mm) reel
(mm)
SOT23-6 8 4 7" 8.4 280 160 3000

3. Others: NA

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