RV1126 Datasheet Rev 1.

Rockchip
RV1126
Datasheet

Revision 1.2
May. 2020

Copyright 2020 ©Fuzhou Rockchip Electronics Co., Ltd. 1

RV1126 Datasheet Rev 1.2

Revision History
Date Revision Description
2020-5-22 1.2 Update pin information
2020-04-03 1.1 Update
2020-03-19 1.0 Initial released

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RV1126 Datasheet Rev 1.2

Table of Content
Table of Content ...................................................................................................... 3
Figure Index ........................................................................................................... 4
Table Index............................................................................................................. 5
Warranty Disclaimer ................................................................................................. 6
Chapter 1 Introduction ..................................................................................... 7
1.1 Overview ............................................................................................... 7
1.2 Features ................................................................................................ 7
1.3 Block Diagram ...................................................................................... 15
Chapter 2 Package Information.........................................................................17
2.1 Order Information ................................................................................. 17
2.2 Top Marking ......................................................................................... 17
2.3 FCCSP 09L Dimension ............................................................................ 17
2.4 Pin Number List .................................................................................... 19
2.5 Power/Ground IO Description .................................................................. 26
2.6 Function IO Description .......................................................................... 28
2.7 IO Pin Name Description ........................................................................ 45
Chapter 3 Electrical Specification ......................................................................51
3.1 Absolute Ratings ................................................................................... 51
3.2 Recommended Operating Condition ......................................................... 51
3.3 DC Characteristics ................................................................................. 52
3.4 Electrical Characteristics for General IO .................................................... 52
3.5 Electrical Characteristics for PLL .............................................................. 52
3.6 Electrical Characteristics for USB 2.0 Interface .......................................... 53
3.7 Electrical Characteristics for DDR IO......................................................... 54
3.8 Electrical Characteristics for TSADC.......................................................... 54
3.9 Electrical Characteristics for SARADC ....................................................... 54
3.10 Electrical Characteristics for MIPI DPHY TX .............................................. 55
3.11 Electrical Characteristics for MIPI DPHY RX .............................................. 55
Chapter 4 Thermal Management .......................................................................57
4.1 Overview ............................................................................................. 57
4.2 Package Thermal Characteristics ............................................................. 57

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RV1126 Datasheet Rev 1.2

Figure Index
Fig.1-1 Block Diagram ....................................................................................... 16
Fig.2-1 Package definition .................................................................................. 17
Fig.2-2 Package Top and Side View ..................................................................... 17
Fig.2-3 Package Bottom View ............................................................................. 18

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RV1126 Datasheet Rev 1.2

Table Index
Table 2-1 Pin Number Order Information ................................................................ 19
Table 2-2 Power/Ground IO information ................................................................. 26
Table 2-3 Function IO description .......................................................................... 28
Table 2-4 IO function description list ..................................................................... 45
Table 3-1 Absolute ratings.................................................................................... 51
Table 3-2 Recommended operating condition .......................................................... 51
Table 3-3 DC Characteristics................................................................................. 52
Table 3-4 Electrical Characteristics for Digital General IO .......................................... 52
Table 3-5 Electrical Characteristics for PLL .............................................................. 52
Table 3-6 Electrical Characteristics for USB 2.0 Interface .......................................... 53
Table 3-7 Electrical Characteristics for DDR IO ........................................................ 54
Table 3-8 Electrical Characteristics for TSADC ......................................................... 54
Table 3-9 Electrical Characteristics for SARADC ....................................................... 54
Table 3-10 Electrical Characteristics for MIPI DPHY TX.............................................. 55
Table 3-11 Electrical Characteristics for MIPI DPHY RX(for MIPI mode) ....................... 55
Table 3-12 Electrical Characteristics for MIPI DPHY RX(for LVDS mode) ...................... 56
Table 4-1 Thermal Resistance Characteristics .......................................................... 57

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RV1126 Datasheet Rev 1.2

Warranty Disclaimer
Rockchip Electronics Co., Ltd makes no warranty, representation or guarantee (expressed, implied, statutory, or otherwise)
by or with respect to anything in this document, and shall not be liable for any implied warranties of non-infringement,
merchantability or fitness for a particular purpose or for any indirect, special or consequential damages.

Information furnished is believed to be accurate and reliable. However, Rockchip Electronics Co., Ltd assumes no
responsibility for the consequences of use of such information or for any infringement of patents or other rights of third
parties that may result from its use.

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Information in this document is provided solely to enable system and software implementers to use Rockchip Electronics Co.,
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Rockchip Electronics Co., Ltd does not convey any license under its patent rights nor the
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Reverse engineering or disassembly is prohibited.

ROCKCHIP ELECTRONICS CO., LTD. RESERVES THE RIGHT TO MAKE CHANGES IN ITS PRODUCTS OR PRODUCT
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RV1126 Datasheet Rev 1.2

Chapter 1 Introduction
1.1 Overview
RV1126 is a high-performance vision processor SoC for IPC/CVR, especially for AI related
application.
It is based on quad-core ARM Cortex-A7 32-bit core which integrates NEON and FPU. There
is a 32KB I-cache and 32KB D-cache for each core and 512KB unified L2 cache.
The build-in NPU supports INT8/INT16 hybrid operation and computing power is up to
2.0TOPs. In addition, with its strong compatibility, network models based on a series of
frameworks such as TensorFlow/MXNet/PyTorch/Caffe can be easily converted.
RV1126 also introduces a new generation totally hardware-based 14-megapixel ISP (image
signal processor) and post processor. It implements a lot of algorithm accelerators usually
used in IPC and CVR, such as HDR, 3A functions (AE, AF, AWB), LSC, 3DNR, 2DNR,
sharpening, dehaze, fisheye correction, gamma correction, feature points detection and so
on. All of them are real-time processing. Cooperating with two MIPI CSI (or
LVDS/SubLVDS) and one DVP (BT.601/BT.656/BT.1120) interface, users can build a system
that receives video data from 3 camera sensors simultaneous.
The video encoder embedded in RV1126 supports UHD H.265/H.264 encoding. It also
supports multi-stream encoding, up to one 4Kp30 and one 1080p30 simultaneous. With the
help of this feature, the video from camera can be encoded with higher resolution and
stored in local memory and transferred another lower resolution video to cloud storage at
the same time.
The H.264/H.265 video decoder in RV1126 supports 4Kp30 for H.264 and H.265.
In addition to the previous high-performance multimedia block, RV1126 also contains rich
audio, memory and other peripheral interfaces such as I2C, SPI, PWM and so on. These can
help users add more sensors or other peripherals into whole system to improve flexibility
and expansibility.
RV1126 has high-performance external DRAM (DDR3/DDR3L/DDR4/LPDDR3/LPDDR4)
capable of sustaining demanding memory bandwidths.

1.2 Features
The features listed below which may or may not be present in actual product, may be
subject to the third-party licensing requirements. Please contact Rockchip for actual
product feature configurations and licensing requirements.
1.2.1 Application Processor
 Quad-Core Cortex-A7
 Full implementation of the ARM architecture v7-A instruction set, ARM Neon Advanced
SIMD
 Separately Integrated Neon and FPU
 32KB L1 I-Cache and 32KB L1 D-Cache per Cortex-A7 CPU
 Unified 512KB L2 Cache for Quad-Core Cortex-A7
 TrustZone technology supported
 Separate power domains for CPU core system to support internal power switch and
externally turn on/off based on different application scenario
 PD_CPU0: 1st Cortex-A7 + Neon + FPU + L1 I/D Cache
 PD_CPU1: 2nd Cortex-A7 + Neon + FPU + L1 I/D Cache
 PD_CPU2: 3rd Cortex-A7 + Neon + FPU + L1 I/D Cache
 PD_CPU3: 4th Cortex-A7 + Neon + FPU + L1 I/D Cache
 One isolated voltage domain to support DVFS

1.2.2 Video Input Interface

 Interface and video input processor
 Two MIPI CSI/ LVDS/SubLVDS interfaces, 4 lanes each, 2.5Gbps per lane
 One 8/10/12/16-bit standard DVP interface, up to 150MHz input data
 Support BT.601/BT.656 and BT.1120 VI interfaces
 Support the polarity of pixel_clk、hsync、vsync configurable

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RV1126 Datasheet Rev 1.2
 ISP
 Maximum resolution is 14Mpixel(4416x3312)
 DVP input: ITU-R BT.601/656/1120 with raw8/raw10/raw12/raw16, YUV422
 MIPI input: RX data lane x1/x2/x4, raw8/raw10/raw12, YUV422
 3A: include AE/Histogram, AF, AWB statistics output
 FPN: Fixed Pattern Noise removal
 BLC: Black Level Correction
 DPCC: Static/Dynamic defect pixel cluster correction
 LSC: Lens shading correction
 Bayer-NR: Bayer-raw De-noising, 2DNR
 HDR: 3-/2-Frame Merge into High-Dynamic Range
 TMO: 3-/2-Frame Merge Video Tone mapping
 WDR: One Frame Wide-Dynamic Range Tone mapping
 Debayer: Advanced Adaptive Demosaic with Chromatic Aberration Correction
 CCM/CSM: Color correction matrix; RGB2YUV etc.
 Gamma: Gamma out correction
 Dehaze/Enhance: Automatic Dehaze and edge enhancement
 3DLUT: 3D-Lut Color Palette for Customer
 LDCH: Lens-distortion in the horizontal direction
 Output Scale*3: support scale down level*3(W0<3264; W1<1280; W2<1280)
 Output Scale*2: support scale down level*2(W0<1920; W1<1920)
 Output (FBC): support YUV422/420 with Frame Buffer Compression
 3DNR: Advanced Temporal Noise reduce in YUV
 2DNR: Advanced Spatial Noise reduce in YUV
 Sharp: Picture Sharpening & Edge Enhance in YUV
 ORB: Oriented Fast and Rotated BRIEF, a method of feature points detection
 FEC: the bigger Lens-distortion and Fish Eye Correction
 CGC: Color Gamut Compression, YUV full range/limit range convert

1.2.3 Video CODEC

 Video Decoder
 Real-time decoding of H.264 and H.265
 Main and Main10 profile for H.265, up to level 5.0 and 4096x2304@30fps
 Baseline, main, high, high10 and high 4:2:2(without MBAFF), up to level 5.1 and
4096x2304@30fps
 Video Encoder
 Real-time UHD H.265/H.264 video encoding
 I-/P-frames and SmartP reference.
 Five bit rate control modes (CBR, VBR, FixQp, AVBR, and QpMap)
 Up to 100 Mbit/s output bit rate
 Support ROI(no limit) encoding;
 High profile for H.264, up to level 5.1 and 4096x2304@30fps
 High profile for H.265, up to level 5.0 and 4096x2304@30fps
 Support multi-stream encoding
 3840 x 2160@30 fps + 1080p@30 fps encoding
 3840 x 2160@30 encoding + 3840 x 2160@30 fps decoding
 Input data format:
 YCbCr 4:2:0 planar
 YCbCr 4:2:0 semi-planar
 YCbYCr 4:2:2
 CbYCrY 4:2:2 interleaved
 RGB444 and BGR444
 RGB555 and BGR555
 RGB565 and BGR565
 RGB888 and BRG888
 RGB101010 and BRG101010
 One isolated voltage domain to support DVFS

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RV1126 Datasheet Rev 1.2

1.2.4 JPEG CODEC

 JPEG Encoder
 Baseline (DCT sequential)
 Encoder size is from 96x96 to 8192x8192(67Mpixels)
 Up to 90 million pixels per second
 JPEG Decoder
 Decoder size is from 48x48 to 8176x8176(66.8Mpixels)
 Up to 76 million pixels per second

1.2.5 Neural Process Unit

 Neural network acceleration engine with processing performance up to 2.0 TOPS
 Support integer 8, integer 16 convolution operation
 Support deeplearning frameworks: TensorFlow, TF-lite, Pytorch, Caffe, ONNX, MXNet,
Keras, Darknet
 Support OpenVX API
 One isolated voltage domain to support DVFS

1.2.6 Memory Organization

 Internal on-chip memory
 BootRom
 SYSTEM_SRAM in the voltage domain of VD_LOGIC
 PMU_SRAM in the voltage domain of VD_PMU for low power application
 External off-chip memory
 DDR3/DDR3L/DDR4/LPDDR3/LPDDR4
①

 SPI Flash
 eMMC
 SD Card
 Async Nand Flash

1.2.7 Internal Memory

 Internal BootRom
 Support system boot from the following device:
 FSPI Flash interface
 eMMC interface
 SDMMC interface
 Async Nand interface
 Support system code download by the following interface:
 USB OTG interface (Device mode)
 SYSTEM_SRAM
 Size: 64KB
 PMU_SRAM
 Size: 8KB

1.2.8 External Memory or Storage device

 Dynamic Memory Interface (DDR3/DDR3L/DDR4/LPDDR3/LPDDR4)
 Compatible with JEDEC standards
 Compatible with DDR3/DDR3L/ DDR4 /LPDDR3/LPDDR4
 Support 32-bit data width, 2 ranks (chip selects), max 4GB addressing space per
rank, total addressing space is 4GB (max)
 Low power modes, such as power-down and self-refresh for SDRAM
 eMMC Interface
 Compatible with standard iNAND interface
 Compatible with eMMC specification 4.51
 Support three data bus width: 1-bit, 4-bit or 8-bit
 Support up to HS200; but not support CMD Queue
 SD/MMC Interface

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RV1126 Datasheet Rev 1.2
 Compatible with SD3.0, MMC ver4.51
 Data bus width is 4bits
 Flexible Serial Flash Interface(FSPI)
 Support transfer data from/to serial flash device
 Support x1, x2, x4 data bits mode
 Support 2 chips select
 Nand Flash Interface
 Support async nand flash
 Data bus width is 8bits
 Support 1 chip select
 Support LBA nand flash
 Up to 16bits/1KB hardware ECC
 Support configurable interface timing

1.2.9 System Component

 RISC-V MCU
 32bit microcontroller core with RISC -V ISA
 Harvard architecture, separate Instruction and Data memories
 Instruction set is RV32I with M and C extensions
 Integrated Programmable Interrupt Controller (IPIC), all 123 IRQ lines
connected to GIC for Cortex-A7 also connect to RISC –V MCU
 Integrated Debug Controller with JTAG interface
 CRU (clock & reset unit)
 Support clock gating control for individual components
 One oscillator with 24MHz clock input
 Support global soft-reset control for whole chip, also individual soft-reset for each
component
 PMU (power management unit)
 Support 5 separate voltage domains
VD_CORE/VD_LOGIC/VD_PMU/VD_NPU/VD_VEPU
 Support 14 separate power domains, which can be power up/down by software
based on different application scenes
 Multiple configurable work modes to save power by different frequency or
automatic clock gating control or power domain on/off control
 Timer
 Support 6 64bit-timers with interrupt-based operation for non-secure application
 Support 2 64bit-timers with interrupt-based operation for secure application
 Support two operation modes: free-running and user-defined count
 Support timer work state checkable
 PWM
 Support 12 on-chip PWMs (PWM0~PWM11) with interrupt-based operation
 Programmable pre-scaled operation to bus clock and then further scaled
 Embedded 32-bit timer/counter facility
 Support capture mode
 Support continuous mode or one-shot mode
 Provides reference mode and output various duty-cycle waveform
 Optimized for IR application for PWM3, PWM7 and PWM11
 Watchdog
 32-bit watchdog counter
 Counter counts down from a preset value to 0 to indicate the occurrence of a
timeout
 WDT can perform two types of operations when timeout occurs:
 Generate a system reset
 First generate an interrupt and if this is not cleared by the service routine by
the time a second timeout occurs then generate a system reset
 Programmable reset pulse length
 Totally 16 defined-ranges of main timeout period

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RV1126 Datasheet Rev 1.2
 One Watchdog for non-secure application
 One Watchdog for secure application
 Interrupt Controller
 Support 128 SPI interrupt sources input from different components
 Support 16 software-triggered interrupts
 Two interrupt outputs (nFIQ and nIRQ) separately for each Cortex-A7, both are
low-level sensitive
 Support different interrupt priority for each interrupt source, and they are always
software-programmable
 DMAC
 Micro-code programming-based DMA
 Linked list DMA function is supported to complete scatter-gather transfer
 Support data transfer types with memory-to-memory, memory-to-peripheral,
peripheral-to-memory
 Signals the occurrence of various DMA events using the interrupt output signals
 One embedded DMA controller for system
 DMAC features:
 Support 8 channels
 27 hardware requests from peripherals
 2 interrupts output
 Support TrustZone technology and programmable secure state for each DMA
channel
 Secure System
 Cipher engine
 Support SM2/SM3/SM4 cipher
 Support SHA-1, SHA-256/224, SHA-512/384, MD5 with hardware padding
 Support Link List Item (LLI) DMA transfer
 Support AES-128 AES-256 encrypt & decrypt cipher
 Support AES ECB/CBC/OFB/CFB/CTR/CTS/XTS mode
 Support DES & TDES encrypt & decrypt cipher
 Support DES/TDES ECB/CBC/OFB/CFB mode
 Support up to 4096 bits PKA mathematical operations for RSA/ECC
 Support up to 8-channels configuration
 Support Up to 256 bits TRNG output
 Support data scrambling for all DDR types
 Support secure OTP
 Support secure debug
 Support secure OS
 Mailbox
 One Mailbox in SoC to service A7 and RISC-V MCU communication
 Support four mailbox elements per mailbox, each element includes one data word,
one command word register and one flag bit that can represent one interrupt
 Provide 32 lock registers for software to use to indicate whether mailbox is
occupied
 DECOM
 Support for decompressing GZIP files
 Support for decompressing LZ4 files, including the General Structure of LZ4 Frame
format and the Legacy Frame format.
 Support for decompressing data in Deflate format
 Support for decompressing data in ZLIB format
 Support complete interrupt and error interrupt output
 Support Hash32 check in LZ4 decompression process
 Support the limit size function of the decompressed data to prevent the memory
from being maliciously destroyed during the decompression process
 Support software to stop the decompression process

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RV1126 Datasheet Rev 1.2

1.2.10 Graphic Engine

 2D Graphics Engine (RGA):
 Source formats:
 ABGR8888, XBGR888, ARGB8888, XRGB888
 RGB888, RGB565
 RGBA5551, RGBA4444
 YUV420 planar, YUV420 semi-planar
 YUV422 planar, YUV422 semi-planar
 YUV 10-bit for YUV420/422 semi-planar
 BPP8, BPP4, BPP2, BPP1
 Destination formats:
 ABGR8888, XBGR888, ARGB8888, XRGB888
 RGB888, RGB565
 RGBA5551, RGBA4444
 YUV420 planar, YUV420 semi-planar
 YUV422 planar, YUV422 semi-planar
 Pixel Format conversion, BT.601/BT.709
 Max resolution: 8192x8192 source, 4096x4096 destination
 BitBLT
 Two source BitBLT:
 A+B=B only BitBLT, A support rotate and scale when B fixed
 A+B=C second source (B) has same attribute with (C) plus rotation function
 Color fill with gradient fill, and pattern fill
 High-performance stretch and shrink
 Monochrome expansion for text rendering
 New comprehensive per-pixel alpha (color/alpha channel separately)
 Alpha blending modes including Java 2 Porter-Duff compositing blending rules,
chroma key, pattern mask, fading
 Dither operation
 0, 90, 180, 270-degree rotation
 x-mirror, y-mirror and rotation operation
 Image Enhancement Processor (IEP):
 Image format
 Input data: YUV420/YUV422, semi-planar/planar, UV swap
 Output data: YUV420/YUV422, semi-planar, UV swap, Tile mode
 YUV down sampling conversion from 422 to 420
 Max resolution for dynamic image up to 1920x1080
 De-interlace

1.2.11 Display Interface

 One up to 24 bits RGB parallel video output interface
 One BT.1120 video output interface
 One 4 lane MIPI DSI interface, up to 1Gbps per lane
 Up to 1080p@60fps

1.2.12 Video Output Processor (VOP)

 Up to 1920x1080 @60fps
 Multiple layer
 Background layer
 Win0 layer
 Win2 layer
 Input format: RGB888, ARGB888, RGB565, YCbCr422, YCbCr420, YCbCr444
 1/8 to 8 scaling-down and scaling-up engine
 Support virtual display
 256 level alpha blending (pre-multiplied alpha support)
 Transparency color key
 YCbCr2RGB (rec601-mpeg/ rec601-jpeg/rec709)

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RV1126 Datasheet Rev 1.2
 RGB2YCbCr (BT.601/BT.709)
 Support multi-region
 Win0 layer and Win2 layer overlay exchangeable
 Support RGB or YUV domain overlay
 BCSH (Brightness, Contrast, Saturation, Hue adjustment)
 BCSH: YCbCr2RGB (rec601-mpeg/ rec601-jpeg/rec709)
 BCSH: RGB2YCbCr (BT.601/BT.709)
 Support Gamma adjust
 Support dither down allegro RGB888to666 RGB888to565 & dither down FRC
(configurable) RGB888to666
 Blank and black display

1.2.13 Audio Interface

 I2S0 with 8 channels
 Up to 8 channels TX and 8 channels RX path
 Audio resolution from 16bits to 32bits
 Sample rate up to 192KHz
 Provides master and slave work mode, software configurable
 Support 3 I2S formats (normal, left-justified, right-justified)
 Support 4 PCM formats (early, late1, late2, late3)
 I2S and PCM mode cannot be used at the same time

 I2S1/I2S2 with 2 channels

 Up to 2 channels for TX and 2 channels RX path
 Audio resolution from 16bits to 32bits
 Sample rate up to 192KHz
 Provides master and slave work mode, software configurable
 Support 3 I2S formats (normal, left-justified, right-justified)
 Support 4 PCM formats (early, late1, late2, late3)
 I2S and PCM cannot be used at the same time
 PDM
 Up to 8 channels
 Audio resolution from 16bits to 24bits
 Sample rate up to 192KHz
 Support PDM master receive mode
 TDM
 Support up to 8 channels for TX and 8 channels RX path
 Audio resolution from 16bits to 32bits
 Sample rate up to 192KHz
 Provides master and slave work mode, software configurable
 Support 3 I2S formats (normal, left-justified, right-justified)
 Support 4 PCM formats (early, late1, late2, late3)
 Audio PWM
 Support convert PCM to PWM format
 Sample rate up to 16x
 Support linear interpolation for 2x/4x/8x/16 oversampling
 Support 8/9/10/11 bits maskable L/R channel PWM output
 Digital Audio Codec
 Support 3-channel digital ADC
 Support 2-channel digital DAC
 Support I2S/PCM interface
 Support I2S/PCM master and slave mode
 Support 4-channel audio transmitting in I2S mode
 Support 2-channel audio receiving in I2S mode
 Support 2-channel audio transmitting or receiving in PCM mode
 Support 16~24 bit sample resolution for both digital ADC and digital DAC
 Both digital ADC and digital DAC support three groups of sample rates. Group 0 are

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RV1126 Datasheet Rev 1.2
8khz/16khz/32kHz/64kHz/128khz, group 1 are
11.025khz/22.05khz/44.1khz/88.2khz/176.4khz and group 2 are
12khz/24khz/48khz/96khz/192khz
 The passband of digital ADC filters is 0.45625*fs
 Support digital ADC pass-band ripple within +/-0.1dB
 The stop-band of digital ADC filters is 0.5*fs
 Support digital ADC stop-band attenuation at least 60dB
 Support volume control for both digital ADC and digital DAC
 Support Automatic Level Control (ALC)and noise gate for digital ADC
 Support communication with Analog Codec through I2C bus

1.2.14 Connectivity
 SDIO Interface
 Compatible with SDIO3.0 protocol
 4bits data bus widths
 GMAC 10/100/1000M ethernet controller
 Support 10/100/1000-Mbps data transfer rates with the RGMII interfaces
 Support 10/100-Mbps data transfer rates with the RMII interfaces
 Support both full-duplex and half-duplex operation
 Support for TCP Segmentation Offload (TSO) and UDP Segmentation Offload (USO)
network acceleration
 USB 2.0 Host
 Compatible with USB 2.0 specification
 Supports high-speed(480Mbps), full-speed(12Mbps) and low-speed(1.5Mbps) mode
 Support Enhanced Host Controller Interface Specification (EHCI), Revision 1.0
 Support Open Host Controller Interface Specification (OHCI), Revision 1.0a
 USB 2.0 OTG
 Compatible Specification
 Universal Serial Bus Specification, Revision 2.0
 Extensible Host Controller Interface for Universal Serial Bus (xHCI), Revision
1.1
 Support Control/Bulk/Interrupt/Isochronous Transfer
 SPI Interface
 Support 2 SPI Controllers, support two chip-select output
 Support serial-master and serial-slave mode, software-configurable
 I2C Interface
 Support 6 I2C interfaces(I2C0-I2C5)
 Support 7bits and 10bits address mode
 Software programmable clock frequency
 Data on the I2C-bus can be transferred at rates of up to 100k bits/s in the
Standard-mode, up to 400k bits/s in the Fast-mode or up to 1m bits/s in Fast-mode
Plus
 UART Interface
 Support 6 UART interfaces (UART0-UART5)
 Support 5bit, 6bit, 7bit, 8bit serial data transmit or receive
 Standard asynchronous communication bits such as start, stop and parity
 Support different input clock for UART operation to get up to 4Mbps baud rate
 Support auto flow control mode(except UART2)

1.2.15 Others
 Multiple Groups of GPIO
 All of GPIOs can be used to generate interrupt
 Support level trigger and edge trigger interrupt
 Support configurable polarity of level trigger interrupt
 Support configurable rising edge, falling edge and both edge trigger interrupt
 Support configurable pull direction (a weak pull-up and a weak pull-down)
 Support configurable drive strength

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RV1126 Datasheet Rev 1.2
 Temperature Sensor (TS-ADC)
 Support User-Defined Mode and Automatic Mode
 In User-Defined Mode, start_of_conversion can be controlled completely by
software, and also can be generated by hardware.
 In Automatic Mode, the temperature of alarm(high/low temperature) interrupt can
be configurable
 In Automatic Mode, the temperature of system reset can be configurable
 Support to 2 channel TS-ADC (used for CPU and NPU respectively), the
temperature criteria of each channel can be configurable
 -40~125°C temperature range and 5°C temperature resolution
 12-bit SARADC up to 732 S/s sampling rate
 Successive approximation ADC (SARADC)
 10-bit resolution
 Up to 1MS/s sampling rate
 6 single-ended input channels
 OTP
 Support 32Kbit space and higher 4k address space is non-secure part.
 Support read and program word mask in secure model
 Support program length from 1 to 32 bit
 Read operation support 8bit only
 Program and Read state can be read
 Program fail address record
 Package type
 FCCSP 409-pin (body: 14mm x 14mm; ball size: 0.3mm; ball pitch: 0.65mm)
Notes:
① : DDR3/DDR3L/DDR4/LPDDR3/LPDDR4 are not used simultaneously

1.3 Block Diagram

The following diagram shows the basic block diagram.

Copyright 2020 ©Fuzhou Rockchip Electronics Co., Ltd. 15

RV1126 Datasheet Rev 1.2

System Peripheral
Clock & Reset
RV1126 Connectivity
USB OTG 2.0
PMU Cortex-A7 Quad-Core USB HOST 2.0
(32K/32K L1 I/D Cache)
PLL x 5 RISC-V
MCU PDM
DECOM 512KB L2 Cache
audPWM
Timer x 8ch
I2S/PCM(2ch) x2
PWM(12ch)

Watchdog x 2 Multi-Media Processor I2S_TDM(8ch)

Crypto UART x 6
14M ISP NPU
SAR-ADC(6ch)
SPI x 2
TS-ADC(2ch) VDPU52X(H.264/H.265) VEPU34X(H.264/H.265) I2C x 6
Interrupt Controller
JPEG Encoder Giga-Ethernet
DMAC JPEG Decoder

PVTM x 3 SDIO 3.0 x2

RGA IEP
Mailbox GPIO

Video Input Interface CAN

MIPI-CSI/LVDS/SubLVDS X2

16-bit DVP External Memory Interface Embedded Memory

eMMC4.51 SD3.0/MMC4.5 System SRAM (64KB)

Video Output Interface
SPI NOR/NAND Flash, SLC NAND Flash PMU SRAM (8KB)
MIPI-DSI

DDR3/DDR3L/DDR4/LPDDR3/LPDDR4 ROM (20KB)

BT.1120

OTP
RGB 24-bit LCD Controller (32Kbits )

Fig.1-1 Block Diagram

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RV1126 Datasheet Rev 1.2

Chapter 2 Package Information

2.1 Order Information
Orderable RoHS Package
Package Device Feature
Device status Qty
1190pcs
RV1126 RoHS FCCSP409LD Quad core application processor
by tray

2.2 Top Marking

Rockchip : Brand Name

RVXXXX : Part Number

ABC : Internal Control Code

1234567 : Die Lot NO # maybe
letter
YYWW : Date Code

NXXXXXX FXX: Sub-lot info in

OSAT
The first pin
Fig.2-1 Package definition
2.3 FCCSP 09L Dimension

Fig.2-2 Package Top and Side View

Copyright 2020 ©Fuzhou Rockchip Electronics Co., Ltd. 17

RV1126 Datasheet Rev 1.2

Fig.2-3 Package Bottom View

Copyright 2020 ©Fuzhou Rockchip Electronics Co., Ltd. 18

 RV1126 Datasheet Rev 1.2

2.4 Pin Number List

Table 2-1 Pin Number Order Information
Pin name Pin# Pin name Pin#

VSS A1 VSS L6

DDR_DQ24 A2 DDR_VDD L7

DDR_DQ25 A3 VEPU_VDD L9

DDR_ACTN A4 LOGIC_VDD L10

DDR_ODT0 A5 VSS L11

DDR_BA1 A6 VSS L12

DDR_A5 A7 VSS L13

DDR_A8 A8 VSS L14

DDR_A4 A9 VSS L16

LCDC_D1/RGMII_CRS_M1/CIF_D1_M1/UART4_C
DDR_A10 A10 L17
TSN_M1/I2C5_SCL_M0/GPIO2_A5_d
LCDC_D4/I2S2_SDI_M1/UART5_TX_M1/PWM3_I
DDR_A14 A11 L19
R_M1/SPI0_MOSI_M2/GPIO2_B0_d
LCDC_D5/I2S2_SCLK_M1/UART5_RX_M1/PWM2
DDR_A13 A12 L20
_M1/SPI0_MISO_M2/GPIO2_B1_d
SDIO_PWR/
A13 DDR_DQ22 M1
I2C5_SDA_M2/UART1_RX_M1/GPIO1_D1_d

UART0_CTSn/GPIO1_C1_u A15 DDR_DM2 M2

SDIO_CMD/GPIO1_B3_u A16 VSS M3

ADCIN3 A18 DDR_DQ6 M4

MIPI_DSI_TX0_D0P A19 VSS M5

MIPI_DSI_TX0_D1P A20 DDR_VREF M6

AVSS A21 VSS M7

DDR_DQ30 B1 VSS M8

DDR_DQ31 B2 VEPU_VDD M9

DDR_DM3 B3 VSS M10

DDR_CS0N B4 LOGIC_VDD M11

DDR_A15 B5 VSS M12

DDR_A3 B6 VSS M13

DDR_A1 B7 VSS M14

DDR_A7 B8 VCCIO6_VDD M15

DDR_A9 B9 VSS M16

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 RV1126 Datasheet Rev 1.2

Pin name Pin# Pin name Pin#

CIF_D13_M0/RGMII_RXDV_M0/PDM_SDI0_M1/G
DDR_A16 B10 M17
PIO3_C1_d
CIF_D14_M0/RGMII_RXER_M0/PDM_SDI1_M1/G
DDR_A2 B11 M18
PIO3_C2_d
CIF_CLKIN_M0/CLK_OUT_ETHERNET_M0/UART3
VSS B12 M19
_CTSN_M0/GPIO3_C5_d
I2S2_MCLK_M0/SDIO_DET/SPI1_CS1n_M1/I2C5_SC LCDC_D3/I2S2_SDO_M1/UART4_RX_M1/PWM4_
B13 M20
L_M2/UART1_TX_M1/GPIO1_D0_d M1/SPI0_CS0n_M2/GPIO2_A7_d
I2S2_SDO_M0/SPI1_MOSI_M1/FLASH_TRIG_OUT/G LCDC_D2/RGMII_COL_M1/CIF_D2_M1/PWM5_M
B14 M21
PIO1_C4_d 1/ UART4_TX_M1/GPIO2_A6_d

UART0_RTSn/GPIO1_C0_u B15 DDR_DQS2N N1

SDIO_D0/GPIO1_B4_u B16 DDR_DQS2P N2

ADCIN5 B17 DDR_DM0 N3

ADCIN2 B18 DDR_DQ3 N4

MIPI_DSI_TX0_D0N B19 VSS N5

MIPI_DSI_TX0_D1N B20 VSS N6

MIPI_DSI_TX0_D2P B21 VSS N7

DDR_DQ14 C1 VEPU_VDD N8

DDR_DQ15 C2 VEPU_VDD N9

VSS C3 VSS N10

DDR_RESETn C4 VSS N11

VSS C5 ARM_VDD N12

DDR_CKE C6 VSS N13

VSS C7 VSS N14

DDR_A6 C8 VSS N16

CIF_D6_M0/RGMII_TXD3_M0/I2S0_LRCK_RX_M
DDR_A0 C9 N17
1/UART4_RTSN_M0/GPIO3_B2_d
CIF_D9_M0/RGMII_TXEN_M0/I2S0_SDO3_SDI1
VSS C10 N18
_M1/SPI1_CS0n_M0/GPIO3_B5_d
CIF_D12_M0/RGMII_CLK_M0/PDM_CLk0_M1/SPI
DDR_A11 C11 N19
1_CLK_M0/GPIO3_C0_d
CIF_D15_M0/RGMII_MDIO_M0/PDM_CLk1_M1/G
VSS C12 N20
PIO3_C3_d
I2S2_LRCK_M0/SPI1_CS0n_M1/UART1_CTSn_M1/GP CIF_VSYNC_M0/RGMII_MDC_M0/UART3_RTSN_
C13 N21
IO1_C7_d M0/GPIO3_C4_d

UART0_TX/GPIO1_C3_u C14 DDR_DQ23 P1

SDIO_D3/GPIO1_B7_u C15 DDR_DQ20 P2

SDIO_D1/GPIO1_B5_u C16 DDR_DQ7 P3

ADCIN4 C17 DDR_DQ2 P4

MIPI_DSI_TX0_CLKN C18 VSS P5

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 RV1126 Datasheet Rev 1.2

Pin name Pin# Pin name Pin#

MIPI_DSI_TX0_CLKP C19 VCCIO1_VDD P6

MIPI_DSI_TX0_D2N C20 VSS P7

LCDC_VSYNC/UART3_RTSN_M2/PWM9_M1/SPI1_MO
C21 VSS P8
SI_M2/GPIO2_D6_d

DDR_DQ9 D1 VSS P9

DDR_DQ8 D2 PMUIO_VDD_0V8 P10

DDR_DQS3P D3 PLL_AVDD_0V8 P11

DDR_CLKP D4 ARM_VDD P12

DDR_CLKN D5 ARM_VDD P13

DDR_BG0 D6 VSS P14

DDR_A12 D7 VCCIO4_VDD P15

DDR_CS1N D8 VSS P16

CIF_D2_M0/RGMII_COL_M0/I2S0_SDO0_M1/UA
VSS D9 RT5_TX_M0/CAN_RXD_M1/PWM10_M0/GPIO3_A P17
6_d
CIF_CLKOUT_M0/RGMII_TXCLK_M0/UART3_TX_
DDR_ODT1 D10 P19
M0/GPIO3_C6_d
CIF_HSYNC_M0/RGMII_RXCLK_M0/UART3_RX_M
DDR_BG1 D11 P20
0/GPIO3_C7_d

VSS D12 VSS R1

I2S2_SCLK_M0/SPI1_CLK_M1/PRELIGHT_TRIG_OUT FLASH_RDYn/FSPI_D1/I2S1_SCLK_M0/GPIO1_A
D13 R2
/UART1_RTSn_M1/ GPIO1_C6_d 1_u
FLASH_WPn/EMMC_RSTn/FSPI_CLK/GPIO1_A3_
UART0_RX/GPIO1_C2_u D14 R3
d
FLASH_RDn/FSPI_D3/I2S1_SDI_M0/GPIO1_A2_
SDIO_D2/GPIO1_B6_u D15 R4
u

SDIO_CLK/GPIO1_B2_d D16 VSS R5

ADCIN1 D17 USB_AVDD_0V8 R6

AVSS D18 USB_AVDD_1V8 R7

MIPI_DSI_TX0_D3N D19 PMUIO1_VDD R8

MIPI_DSI_TX0_D3P D20 PMUIO0_VDD R9

LCDC_CLK/UART3_CTSN_M2/PWM8_M1/SPI1_MISO_
D21 PMUIO_VDD_1V8 R10
M2/GPIO2_D7_d

DDR_DQ13 E1 PLL_AVDD_1V8 R11

DDR_DM1 E2 VSS R12

DDR_DQS3N E3 VSS R13

VSS E4 VSS R14

DDR_RZQ E5 MIPI_CSI_RX1_AVDD_0V8 R15

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 RV1126 Datasheet Rev 1.2

Pin name Pin# Pin name Pin#

VSS E6 MIPI_CSI_RX1_AVDD_1V8 R16

CIF_D0_M0/I2S0_SCLK_TX_M1/UART4_TX_M0/I
DDR_BA0 E7 R17
2C3_SCL_M0/PWM8_M0/GPIO3_A4_d
CIF_D3_M0/RGMII_RXD2_M0/I2S0_SDI0_M1/UA
VSS E8 RT5_RX_M0/CAN_TXD_M1/PWM11_IR_M0/GPIO R18
3_A7_d
CIF_D7_M0/RGMII_TXD0_M0/I2S0_SDO1_SDI3
VSS E9 R19
_M1/UART4_CTSN_M0/GPIO3_B3_d
CIF_D10_M0/RGMII_RXD0_M0/PDM_SDI2_M1/S
VSS E10 R20
PI1_MOSI_M0/GPIO3_B6_d
CIF_D11_M0/RGMII_RXD1_M0/PDM_SDI3_M1/S
VSS E11 R21
PI1_MISO_M0/GPIO3_B7_d

VSS E12 FLASH_CLE/EMMC_CLKO/GPIO0_D7_d T1

I2S2_SDI_M0/SPI1_MISO_M1/FLASH_TRIG_IN/GPIO FLASH_ALE/FSPI_D0/I2S1_LRCK_M0/GPIO1_A0
E13 T2
1_C5_d _d

VCCIO3_VDD E14 FSPI_D2/I2S1_SDO_M0/GPIO0_D6_d T3

ADC_AVDD_1V8 E16 FLASH_WRn/EMMC_CMD/GPIO0_D5_u T4

ADCIN0 E17 VSS T6

MIPI_DSI_TX0_AVDD_0V8 E18 USB_AVDD_3V3 T7

CAN_TXD_M0/UART3_RX_M2/PWM11_IR_M1/I2C4_
E19 TVSS T8
SDA_M0/GPIO3_A1_u
CAN_RXD_M0/UART3_TX_M2/PWM7_IR_M1/SPI1_C
E20 VSS T9
S1n_M2/I2C4_SCL_M0/GPIO3_A0_u

DDR_DQS1N F1 VSS T10

I2S0_SDO1_SDI3_M0/PDM_SDI3_M0/ACODEC_
DDR_DQS1P F2 T11
ADC_DATA/GPIO3_D7_d

VSS F3 VCCIO7_VDD T12

DDR_DQ27 F4 VCCIO2_VDD T13

VSS F5 VSS T14

DDR_AVSS F6 MIPI_CSI_RX0_AVDD_0V8 T15

VSS F7 MIPI_CSI_RX0_AVDD_1V8 T16

VSS F8 VSS T17

CIF_D1_M0/RGMII_CRS_M0/I2S0_LRCK_TX_M1/
VSS F9 UART4_RX_M0/I2C3_SDA_M0/PWM9_M0/GPIO3 T18
_A5_d
CIF_D4_M0/RGMII_RXD3_M0/I2S0_MCLK_M1/U
VSS F10 T19
ART5_RTSN_M0/I2C5_SCL_M1/GPIO3_B0_d
CIF_D5_M0/RGMII_TXD2_M0/I2S0_SCLK_RX_M
VSS F11 T20
1/UART5_CTSN_M0/I2C5_SDA_M1/GPIO3_B1_d
CIF_D8_M0/RGMII_TXD1_M0/I2S0_SDO2_SDI2
VSS F12 T21
_M1/SPI1_CS1n_M0/GPIO3_B4_d
FLASH_CS0n/FSPI_CS0n
VSS F13 U2
/I2S1_MCLK_M0/GPIO0_D4_u

AVSS F14 FLASH_D7/EMMC_D7/GPIO0_D3_u U3

AVSS F15 FLASH_D6/EMMC_D6/GPIO0_D2_u U4

Copyright 2020 ©Fuzhou Rockchip Electronics Co., Ltd. 22

 RV1126 Datasheet Rev 1.2

Pin name Pin# Pin name Pin#

LCDC_D23/RGMII_RXCLK_M1/CIF_HSYNC_M1/I2S1_
F19 HOST_EXTR U5
SDI_M2/GPIO2_D3_d
LCDC_D22/RGMII_TXCLK_M1/CIF_CLKIN_M1/I2S1_L
F20 OTG_EXTR U6
RCK_M2/GPIO2_D2_d
LCDC_D21/RGMII_TXD2_M1/CIF_CLKOUT_M1/I2S1_
F21 SDMMC0_DET/GPIO0_A3_u U7
SCLK_M2/GPIO2_D1_d
SDMMC0_PWR /UART1_RTSN_M0/
DDR_DQ12 G1 U9
PWM2_M0/GPIO0_C0_d
I2S0_SDO2_SDI2_M0/PDM_SDI2_M0/AUDPWM_
VSS G2 U11
L_M0/I2C4_SCL_M1/AUDDSM_RN/GPIO4_A0_d

DDR_DQ29 G3 I2S0_MCLK_M0/GPIO3_D2_d U12

SDMMC0_D3/UART3_TX_M1/A7_JTAG_TMS_M0/
DDR_DQ26 G4 U13
RISC-V_JTAG_TMS/GPIO1_A7_u

VSS G5 MIPI_CSI_RX0_CLKP/LVDS0_CLKP U15

VSS G6 MIPI_CSI_RX0_D0N/LVDS0_RX0N U16

SPI0_MISO_M1/I2S1_LRCK_M1/I2C3_SDA_M2/
DDR_VDD G7 U18
GPIO1_D7_d
SPI0_CS0n_M1/I2S1_SDI_M1/UART5_TX_M2/GP
DDR_VDD G8 U19
IO2_A0_d
SPI0_CLK_M1/I2S1_SDO_M1/UART5_RX_M2/GP
DDR_VDD G9 U20
IO2_A1_d

VSS G10 FLASH_D5/EMMC_D5/FSPI_CS1n/GPIO0_D1_u V1

VSS G11 FLASH_D4/EMMC_D4/GPIO0_D0_u V2

VSS G12 FLASH_D3/EMMC_D3/GPIO0_C7_u V3

VSS G13 FLASH_D2/EMMC_D2/GPIO0_C6_u V4

MIPI_DSI_TX0_AVDD_1V8 G15 OTG_VBUS1V8 V5

AVSS G16 SPI0_MOSI_M0/GPIO0_A6_d V6

AVSS G17 SPI0_CS1n_M0/GPIO0_A4_u V7

UART2_TX_M1/A7_JTAG_TCK_M1/GPIO3_A2_u G18 UART1_RX_M0/PWM1_M0/GPIO0_B7_d V9

LCDC_D19/RGMII_RXD2_M1/CIF_D15_M1/I2S1_MCL I2S0_SDO3_SDI1_M0/PDM_SDI1_M0/AUDPWM_
G19 V11
K_M2/GPIO2_C7_d R_M0/I2C4_SDA_M1/AUDDSM_RP/GPIO4_A1_d
LCDC_D18/RGMII_TXEN_M1/CIF_D14_M1/GPIO2_C6 I2S0_SCLK_RX_M0/PDM_CLk1_M0/ACODEC_AD
G20 V12
_d C_CLK/GPIO3_D1_d
LCDC_D17/CLK_OUT_ETHERNET_M1/CIF_D13_M1/G SDMMC0_D2/UART3_RX_M1/A7_JTAG_TCK_M0/
G21 V13
PIO2_C5_d RISC-V_JTAG_TCK/GPIO1_A6_u

DDR_DQ11 H1 MIPI_CSI_RX0_CLKN/LVDS0_CLKN V15

DDR_DQ10 H2 MIPI_CSI_RX0_D0P/LVDS0_RX0P V16

DDR_DQ28 H3 VSS V17

VSS H4 MIPI_CSI_RX1_CLKP/LVDS1_CLKP V18

SPI0_MOSI_M1/I2S1_SCLK_M1/I2C3_SCL_M2/G
VSS H5 V19
PIO1_D6_d
SPI0_CS1n_M1/I2S1_MCLK_M1/UART4_TX_M2/
VSS H6 V20
GPIO1_D5_d

VSS H7 MIPI_CSI_CLK0/UART5_CTSN_M2/GPIO2_A3_d V21

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 RV1126 Datasheet Rev 1.2

Pin name Pin# Pin name Pin#

DDR_VDD H8 FLASH_D1/EMMC_D1/GPIO0_C5_u W1

LOGIC_VDD H9 FLASH_D0/EMMC_D0/GPIO0_C4_u W2

VSS H10 OTG_DP W3

NPU_VDD H11 OTG_DM W4

NPU_VDD H12 SPI0_MISO_M0/GPIO0_A7_d W5

LOGIC_VDD H13 CLK_REF/GPIO0_A0_d W6

VCCIO_VDD_1V8 H14 NPOR_u W7

VSS H15 UART1_TX_M0/PWM0_M0/GPIO0_B6_d W8

UART2_RX_M1/A7_JTAG_TMS_M1/GPIO3_A3_u H16 VSS W9

LCDC_HSYNC/PWM10_M1/ SPI1_CLK_M2
H17 PMIC_IN/PWM7_IR_M0/GPIO0_B1_d W10
/I2C3_SDA_M1/GPIO2_D5_d
LCDC_D20/RGMII_RXD3_M1/CIF_VSYNC_M1/I2S1_S I2S0_LRCK_TX_M0/ACODEC_DAC_SYNC/AUDPW
H18 W11
DO_M2/GPIO2_D0_d M_L_M1/AUDDSM_LN/GPIO3_D3_d
LCDC_D16/RGMII_TXD1_M1/CIF_D12_M1/GPIO2_C4 I2S0_SCLK_TX_M0/ACODEC_DAC_CLK/GPIO3_D
H19 W12
_d 0_d
LCDC_D15/RGMII_TXD0_M1/CIF_D11_M1/GPIO2_C3 SDMMC0_D1/TEST_CLK0_OUT/UART2_TX_M0/RI
H20 W13
_d SC-V_JTAG_TRSTn/GPIO1_A5_u

DDR_DQ18 J1 VSS W14

DDR_DQ19 J2 MIPI_CSI_RX0_D2P/LVDS0_RX2P W15

DDR_DQ4 J3 MIPI_CSI_RX0_D1N/LVDS0_RX1N W16

DDR_DQ1 J4 MIPI_CSI_RX1_D3N/LVDS1_RX3N W17

VSS J5 MIPI_CSI_RX1_CLKN/LVDS1_CLKN W18

VSS J6 I2C1_SDA/UART4_RTSN_M2/GPIO1_D2_u W19

DDR_VDD J7 UART4_RX_M2/GPIO1_D4_d W20

LOGIC_VDD J9 MIPI_CSI_CLK1/UART5_RTSN_M2/GPIO2_A2_d W21

NPU_VDD J10 HOST_DP Y1

NPU_VDD J11 HOST_DM Y2

VSS J12 OTG_ID Y3

LOGIC_VDD J13 SPI0_CLK_M0/GPIO0_B0_d Y4

TSADC_SHUT_M0/TSADC_SHUTORG/GPIO0_A1_
VSS J14 Y5
z

VCCIO5_VDD J15 I2C2_SDA/PWM5_M0/GPIO0_C3_d Y6

VSS J16 I2C0_SDA/GPIO0_B5_u Y7

LCDC_DEN/PWM6_M1/SPI1_CS0n_M2/I2C3_SCL_M1
J17 FLASH_VOL_SEL/GPIO0_B3_d Y8
/GPIO2_D4_d
LCDC_D0/RGMII_TXD3_M1/CIF_D0_M1/UART4_RTS
J18 XOUT24M Y9
N_M1/GPIO2_A4_d

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 RV1126 Datasheet Rev 1.2

Pin name Pin# Pin name Pin#

LCDC_D12/RGMII_RXER_M1/CIF_D8_M1/GPIO2_C0_ PMIC_SLEEP/TSADC_SHUT_M1/PWM6_M0/GPIO
J19 Y10
d 0_B2_d
LCDC_D14/RGMII_MDC_M1/CIF_D10_M1/GPIO2_C2 I2S0_SDO0_M0/ACODEC_DAC_DATAR/AUDPWM
J20 Y11
_d _R_M1/AUDDSM_LP/GPIO3_D5_d
LCDC_D13/RGMII_MDIO_M1/CIF_D9_M1/GPIO2_C1 I2S0_LRCK_RX_M0/PDM_CLk0_M0/ACODEC_AD
J21 Y12
_d C_SYNC/GPIO3_D4_d
SDMMC0_CMD/UART3_CTSN_M1/RISC-
DDR_DQ16 K1 Y13
V_JTAG_TDI/GPIO1_B1_u
SDMMC0_D0/TEST_CLK1_OUT/UART2_RX_M0/G
DDR_DQ17 K2 Y14
PIO1_A4_u

DDR_DQ5 K3 MIPI_CSI_RX0_D2N/LVDS0_RX2N Y15

DDR_DQ0 K4 MIPI_CSI_RX0_D1P/LVDS0_RX1P Y16

VSS K5 MIPI_CSI_RX1_D3P/LVDS1_RX3P Y17

VSS K6 MIPI_CSI_RX1_D2N/LVDS1_RX2N Y18

DDR_VDD K7 MIPI_CSI_RX1_D1N/LVDS1_RX1N Y19

VSS K8 MIPI_CSI_RX1_D0N/LVDS1_RX0N Y20

VSS K9 I2C1_SCL/UART4_CTSN_M2/GPIO1_D3_u Y21

NPU_VDD K10 VSS AA1

NPU_VDD K11 SPI0_CS0n_M0/GPIO0_A5_u AA2

VSS K12 CLKI_CLKO_32K/GPIO0_A2_z AA3

PMU_DEBUG/UART1_CTSN_M0/PWM3_IR_M0/GP
VSS K13 AA4
IO0_C1_d

VSS K14 I2C2_SCL/PWM4_M0/GPIO0_C2_d AA6

VCCIO5_VDD K15 I2C0_SCL/GPIO0_B4_u AA7

LCDC_D6/I2S2_LRCK_M1/UART5_RTSN_M1/PWM1_
K16 XIN24M AA9
M1/SPI0_CLK_M2/GPIO2_B2_d
LCDC_D7/I2S2_MCLK_M1/CIF_D3_M1/UART5_CTSN
_M1/SPI0_CS1n_M2/PWM0_M1/I2C5_SDA_M0/ K17 VSS AA10
GPIO2_B3_d
LCDC_D8/RGMII_RXDV_M1/CIF_D4_M1/GPIO2_B4_ I2S0_SDI0_M0/PDM_SDI0_M0/ACODEC_DAC_D
K18 AA12
d ATAL/GPIO3_D6_d
LCDC_D9/RGMII_RXD0_M1/CIF_D5_M1/GPIO2_B5_ SDMMC0_CLK/UART3_RTSN_M1/RISC-
K19 AA13
d V_JTAG_TDO/GPIO1_B0_u
LCDC_D10/RGMII_RXD1_M1/CIF_D6_M1/GPIO2_B6
K20 MIPI_CSI_RX0_D3P/LVDS0_RX3P AA15
_d

LCDC_D11/RGMII_CLK_M1/CIF_D7_M1/GPIO2_B7_d K21 MIPI_CSI_RX0_D3N/LVDS0_RX3N AA16

DDR_DQ21 L1 MIPI_CSI_RX1_D2P/LVDS1_RX2P AA18

VSS L2 MIPI_CSI_RX1_D1P/LVDS1_RX1P AA19

DDR_DQS0N L3 MIPI_CSI_RX1_D0P/LVDS1_RX0P AA20

DDR_DQS0P L4 VSS AA21

VSS L5

Copyright 2020 ©Fuzhou Rockchip Electronics Co., Ltd. 25

RV1126 Datasheet Rev 1.2

2.5 Power/Ground IO Description

Table 2-2 Power/Ground IO information
Group Ball# Descriptions

A1 B12 C3 C5 C7 C10 C12 D9 D12 E4

E6 E8 E9 E10 E11 E12 F3 F5 F7 F8 F9
F10 F11 F12 F13 G2 G5 G6 G10 G11
G12 G13 H4 H5 H6 H7 H10 H15 J5 J6
J12 J14 J16 K5 K6 K8 K9 K12 K13 K14 Ground
VSS
L2 L5 L6 L11 L12 L13 L14 L16 M3 M5
M7 M8 M10 M12 M13 M14 M16 N5 N6
N7 N10 N11 N13 N14 N16 P5 P7 P8 P9
P14 P16 R1 R5 R12 R13 R14 T6 T9 T10
T14 T17 V17 W9 W14 AA1 AA10 AA21

AVSS A21 D18 F14 F15 G16 G17 Ground

ADC_AVDD_1V8 E16 SARADC 1.8V analog power

ARM_VDD N12 P12 P13 CORE power domain logic power

DDR_AVSS F6 DDR analog ground

DDR_VDD G7 G8 G9 H8 J7 K7 L7 DDR digital 0.8V power

LOGIC_VDD H9 H13 J9 J13 L10 M11 LOGIC 0.8V power

MIPI_CSI_RX0_AVDD_0V8 T15 MIPI CSI0 0.8V analog power

MIPI_CSI_RX0_AVDD_1V8 T16 MIPI CSI0 1.8V analog power

MIPI_CSI_RX1_AVDD_0V8 R15 MIPI CSI1 0.8V analog power

MIPI_CSI_RX1_AVDD_1V8 R16 MIPI CSI1 1.8V analog power

MIPI_DSI_TX0_AVDD_0V8 E18 MIPI DSI 0.8V analog power

MIPI_DSI_TX0_AVDD_1V8 G15 MIPI DSI 1.8V analog power

NPU_VDD H11 H12 J10 J11 K10 K11 NPU power domain logic power

PLL_AVDD_0V8 P11 PLL 0.8V analog power

PLL_AVDD_1V8 R11 PLL 1.8V analog power

PMUIO_VDD_0V8 P10 PMU IO 0.8V digital power

PMUIO_VDD_1V8 R10 PMU IO 1.8V digital power

PMUIO0_VDD R9 PMU IO0 0.8V digital power

PMUIO1_VDD R8 PMU IO1 0.8V digital power

USB_AVDD_0V8 R6 USB HOST/OTG 0.8V analog power

USB_AVDD_1V8 R7 USB HOST/OTG 1.8V analog power

USB_AVDD_3V3 T7 USB HOST/OTG 3.3V analog power

VCCIO1_VDD P6 VCCIO1 0.8V digital power

VCCIO2_VDD T13 VCCIO2 0.8V digital power

VCCIO3_VDD E14 VCCIO3 0.8V digital power

VCCIO4_VDD P15 VCCIO4 0.8V digital power

VCCIO5_VDD J15 VCCIO5 0.8V digital power

VCCIO5_VDD K15 VCCIO6 0.8V digital power

Copyright 2020 ©Fuzhou Rockchip Electronics Co., Ltd. 26

RV1126 Datasheet Rev 1.2

Group Ball# Descriptions

VCCIO6_VDD M15 VCCIO7 0.8V digital power

VEPU VDD L9 M9 N8 N9 VEPU power domain logic power

Copyright 2020 ©Fuzhou Rockchip Electronics Co., Ltd. 27

RV1126 Datasheet Rev 1.2

2.6 Function IO Description

Table 2-3 Function IO description
PAD Driver Pull up /
Pin# Pin Name Func0 Func1 Func2 Func3 Func4 Func5 Func6 Func7 IO domain
Type Def Strength Pull down

FLASH_ALE/FSPI_D0/I2S1_LRCK_M0/GPIO1_A0 FLASH_ FSPI_D I2S1_LR

T2 GPIO1_A0 I/O I 1 down
_d ALE 0 CK_M0

I/O
FLASH_ EMMC_
T1 FLASH_CLE/EMMC_CLKO/GPIO0_D7_d GPIO0_D7 I 2 down
CLE CLKO

I/O 1
FLASH_CS0n/FSPI_CS0n FLASH_ FSPI_C I2S1_M
U2 GPIO0_D4 I up
/I2S1_MCLK_M0/GPIO0_D4_u CS0n S0n CLK_M0

I/O 1 up
FLASH_ EMMC_
W2 FLASH_D0/EMMC_D0/GPIO0_C4_u GPIO0_C4 I
D0 D0

I/O 1 up
FLASH_ EMMC_
W1 FLASH_D1/EMMC_D1/GPIO0_C5_u GPIO0_C5 I
D1 D1

I/O 1 up
FLASH_ EMMC_
V4 FLASH_D2/EMMC_D2/GPIO0_C6_u GPIO0_C6 I
D2 D2

I/O 1 up
FLASH_ EMMC_
V3 FLASH_D3/EMMC_D3/GPIO0_C7_u GPIO0_C7 I
D3 D3

I/O 1 up
FLASH_ EMMC_
V2 FLASH_D4/EMMC_D4/GPIO0_D0_u GPIO0_D0 I
D4 D4
VCCIO1
I/O 1 up
FLASH_ EMMC_ FSPI_C
V1 FLASH_D5/EMMC_D5/FSPI_CS1n/GPIO0_D1_u GPIO0_D1 I
D5 D5 S1n

I/O 1 up
FLASH_ EMMC_
U4 FLASH_D6/EMMC_D6/GPIO0_D2_u GPIO0_D2 I
D6 D6

I/O 1 up
FLASH_ EMMC_
U3 FLASH_D7/EMMC_D7/GPIO0_D3_u GPIO0_D3 I
D7 D7

I/O 1 up
FLASH_RDn/FSPI_D3/I2S1_SDI_M0/GPIO1_A2_ FLASH_ FSPI_D I2S1_S
R4 GPIO1_A2 I
u RDn 3 DI_M0

I/O 1 up
FLASH_RDYn/FSPI_D1/I2S1_SCLK_M0/GPIO1_A FLASH_ FSPI_D I2S1_S
R2 GPIO1_A1 I
1_u RDYn 1 CLK_M0

I/O
FLASH_WPn/EMMC_RSTn/FSPI_CLK/GPIO1_A3_ FLASH_ EMMC_ FSPI_CL
R3 GPIO1_A3 I 2 down
d WPn RSTn K

I/O 1
FLASH_ EMMC_
T4 FLASH_WRn/EMMC_CMD/GPIO0_D5_u GPIO0_D5 I up
WRn CMD

I/O 1
FSPI_D I2S1_S
T3 FSPI_D2/I2S1_SDO_M0/GPIO0_D6_d GPIO0_D6 I down
2 DO_M0

Copyright 2020 ©Fuzhou Rockchip Electronics Co., Ltd. 28

RV1126 Datasheet Rev 1.2

PAD Driver Pull up /

Pin# Pin Name Func0 Func1 Func2 Func3 Func4 Func5 Func6 Func7 IO domain
Type Def Strength Pull down

UART3_ RISC- I/O up

SDMMC0_CLK/UART3_RTSN_M1/RISC- SDMMC
AA13 GPIO1_B0 RTSN_M V_JTAG I 2
V_JTAG_TDO/GPIO1_B0_u 0_CLK
1 _TDO
UART3_ RISC- I/O 1 up
SDMMC0_CMD/UART3_CTSN_M1/RISC- SDMMC
Y13 GPIO1_B1 CTSN_M V_JTAG I
V_JTAG_TDI/GPIO1_B1_u 0_CMD
1 _TDI
TEST_C I/O 1 up
SDMMC0_D0/TEST_CLK1_OUT/UART2_RX_M0/G SDMMC UART2_
Y14 GPIO1_A4 LK1_OU I
PIO1_A4_u 0_D0 RX_M0
T
VCCIO2
TEST_C RISC- I/O 1 up
SDMMC0_D1/TEST_CLK0_OUT/UART2_TX_M0/R SDMMC UART2_
W13 GPIO1_A5 LK0_OU V_JTAG I
ISC-V_JTAG_TRSTn/GPIO1_A5_u 0_D1 TX_M0
T _TRSTn
A7_JTA RISC- I/O 1 up
SDMMC0_D2/UART3_RX_M1/A7_JTAG_TCK_M0/ SDMMC UART3_
V13 GPIO1_A6 G_TCK_ V_JTAG I
RISC-V_JTAG_TCK/GPIO1_A6_u 0_D2 RX_M1
M0 _TCK
A7_JTA RISC- I/O 1 up
SDMMC0_D3/UART3_TX_M1/A7_JTAG_TMS_M0/ SDMMC UART3_
U13 GPIO1_A7 G_TMS_ V_JTAG I
RISC-V_JTAG_TMS/GPIO1_A7_u 0_D3 TX_M1
M0 _TMS
UART1_ I/O 1
I2S2_LRCK_M0/SPI1_CS0n_M1/UART1_CTSn_M I2S2_LR SPI1_C
C13 GPIO1_C7 CTSN_M I down
1/GPIO1_C7_d CK_M0 S0n_M1
1
I/O 1 down
I2S2_MCLK_M0/SDIO_DET/SPI1_CS1n_M1/I2C5 I2S2_M SDIO_D SPI1_C I2C5_S UART1_
B13 GPIO1_D0 I
_SCL_M2/UART1_TX_M1/GPIO1_D0_d CLK_M0 ET S1n_M1 CL_M2 TX_M1

I/O 1 down
I2S2_SCLK_M0/SPI1_CLK_M1/PRELIGHT_TRIG_ SDIO_P I2C5_S UART1_
D13 GPIO1_D1 I
OUT/UART1_RTSn_M1/ GPIO1_C6_d WR DA_M2 RX_M1

FLASH_ I/O 1 down

I2S2_SDI_M0/SPI1_MISO_M1/FLASH_TRIG_IN/ I2S2_S SPI1_MI
E13 GPIO1_C5 TRIG_I I
GPIO1_C5_d DI_M0 SO_M1
N
FLASH_ I/O 1 down
I2S2_SDO_M0/SPI1_MOSI_M1/FLASH_TRIG_OU I2S2_S SPI1_M
B14 GPIO1_C4 TRIG_O I
T/GPIO1_C4_d DO_M0 OSI_M1
UT
I/O down
SDIO_C
D16 SDIO_CLK/GPIO1_B2_d GPIO1_B2 I 2 VCCIO3
LK

I/O 1 up
SDIO_C
A16 SDIO_CMD/GPIO1_B3_u GPIO1_B3 I
MD

I/O 1 up
SDIO_D
B16 SDIO_D0/GPIO1_B4_u GPIO1_B4 I
0

I/O 1 up
SDIO_D
C16 SDIO_D1/GPIO1_B5_u GPIO1_B5 I
1

I/O 1 up
SDIO_D
D15 SDIO_D2/GPIO1_B6_u GPIO1_B6 I
2

I/O 1 up
SDIO_D
C15 SDIO_D3/GPIO1_B7_u GPIO1_B7 I
3

Copyright 2020 ©Fuzhou Rockchip Electronics Co., Ltd. 29

RV1126 Datasheet Rev 1.2

PAD Driver Pull up /

Pin# Pin Name Func0 Func1 Func2 Func3 Func4 Func5 Func6 Func7 IO domain
Type Def Strength Pull down

I/O 1 down
SDIO_PWR/ SDIO_P I2C5_S UART1_
A13 GPIO1_D1 I
I2C5_SDA_M2/UART1_RX_M1/GPIO1_D1_d WR DA_M2 RX_M1

I/O 1 down
UART0_
A15 UART0_CTSn/GPIO1_C1_u GPIO1_C1 I
CTSN

I/O 1 up
UART0_
B15 UART0_RTSn/GPIO1_C0_u GPIO1_C0 I
RTSN

I/O 1 up
UART0_
D14 UART0_RX/GPIO1_C2_u GPIO1_C2 I
RX

I/O 1 up
UART0_
C14 UART0_TX/GPIO1_C3_u GPIO1_C3 I
TX

UART4_ I/O 1 up
I2C1_S
Y21 I2C1_SCL/UART4_CTSN_M2/GPIO1_D3_u GPIO1_D3 CTSN_M I
CL
2
UART4_ I/O 1
I2C1_S
W19 I2C1_SDA/UART4_RTSN_M2/GPIO1_D2_u GPIO1_D2 RTSN_M I up
DA
2
MIPI_C UART5_ I/O down
V21 MIPI_CSI_CLK0/UART5_CTSN_M2/GPIO2_A3_d GPIO2_A3 SI_CLK CTSN_M I 2
0 2
MIPI_C UART5_ I/O down
W21 MIPI_CSI_CLK1/UART5_RTSN_M2/GPIO2_A2_d GPIO2_A2 SI_CLK RTSN_M I 2
1 2
I/O 1 down
SPI0_CLK_M1/I2S1_SDO_M1/UART5_RX_M2/GP SPI0_CL I2S1_S UART5_
U20 GPIO2_A1 I
IO2_A1_d K_M1 DO_M1 RX_M2
VCCIO4
I/O 1 down
SPI0_CS0n_M1/I2S1_SDI_M1/UART5_TX_M2/G SPI0_C I2S1_S UART5_
U19 GPIO2_A0 I
PIO2_A0_d S0n_M1 DI_M1 TX_M2

I/O 1 down
SPI0_CS1n_M1/I2S1_MCLK_M1/UART4_TX_M2/ SPI0_C I2S1_M UART4_
V20 GPIO1_D5 I
GPIO1_D5_d S1n_M1 CLK_M1 TX_M2

I/O 1 down
SPI0_MISO_M1/I2S1_LRCK_M1/I2C3_SDA_M2/ SPI0_MI I2S1_LR I2C3_S
U18 GPIO1_D7 I
GPIO1_D7_d SO_M1 CK_M1 DA_M2

I/O 1 down
SPI0_MOSI_M1/I2S1_SCLK_M1/I2C3_SCL_M2/G SPI0_M I2S1_S I2C3_S
V19 GPIO1_D6 I
PIO1_D6_d OSI_M1 CLK_M1 CL_M2

I/O 1 down
UART4_
W20 UART4_RX_M2/GPIO1_D4_d GPIO1_D4 I
RX_M2

I/O 1 down
CAN_RXD_M0/UART3_TX_M2/PWM7_IR_M1/SPI CAN_RX UART3_ PWM7_I SPI1_C I2C4_S
E20 GPIO3_A0 I
1_CS1n_M2/I2C4_SCL_M0/GPIO3_A0_u D_M0 TX_M2 R_M1 S1n_M2 CL_M0
VCCIO5
I/O 1 down
CAN_TXD_M0/UART3_RX_M2/PWM11_IR_M1/I2 CAN_TX UART3_ PWM11 I2C4_S
E19 GPIO3_A1 I
C4_SDA_M0/GPIO3_A1_u D_M0 RX_M2 _IR_M1 DA_M0

Copyright 2020 ©Fuzhou Rockchip Electronics Co., Ltd. 30

RV1126 Datasheet Rev 1.2

PAD Driver Pull up /

Pin# Pin Name Func0 Func1 Func2 Func3 Func4 Func5 Func6 Func7 IO domain
Type Def Strength Pull down

UART3_ I/O down

LCDC_CLK/UART3_CTSN_M2/PWM8_M1/SPI1_M LCDC_C PWM8_ SPI1_M
D21 GPIO2_D7 CTSN_M I 2
ISO_M2/GPIO2_D7_d LK M1 ISO_M2
2
RGMII_ UART4_ I/O 1 down
LCDC_D0/RGMII_TXD3_M1/CIF_D0_M1/UART4_ LCDC_D CIF_D0
J18 GPIO2_A4 TXD3_M RTSN_M I
RTSN_M1/GPIO2_A4_d 0 _M1
1 1
UART4_ I/O 1 down
LCDC_D1/RGMII_CRS_M1/CIF_D1_M1/UART4_C LCDC_D RGMII_ CIF_D1 I2C5_S
L17 GPIO2_A5 CTSN_M I
TSN_M1/I2C5_SCL_M0/GPIO2_A5_d 1 CRS_M1 _M1 CL_M0
1
RGMII_ I/O 1 down
LCDC_D10/RGMII_RXD1_M1/CIF_D6_M1/GPIO2 LCDC_D CIF_D6
K20 GPIO2_B6 RXD1_M I
_B6_d 10 _M1
1
I/O 1 down
LCDC_D11/RGMII_CLK_M1/CIF_D7_M1/GPIO2_ LCDC_D RGMII_ CIF_D7
K21 GPIO2_B7 I
B7_d 11 CLK_M1 _M1

RGMII_ I/O 1 down

LCDC_D12/RGMII_RXER_M1/CIF_D8_M1/GPIO2 GPIO2_C7_ LCDC_D CIF_D8
J19 RXER_M I
_C0_d d 12 _M1
1
RGMII_ I/O 1 down
LCDC_D13/RGMII_MDIO_M1/CIF_D9_M1/GPIO2 GPIO2_C1_ LCDC_D CIF_D9
J21 MDIO_ I
_C1_d d 13 _M1
M1
RGMII_ I/O 1 down
LCDC_D14/RGMII_MDC_M1/CIF_D10_M1/GPIO2 GPIO2_C2_ LCDC_D CIF_D1
J20 MDC_M I
_C2_d d 14 0_M1
1
RGMII_ I/O 1 down
LCDC_D15/RGMII_TXD0_M1/CIF_D11_M1/GPIO GPIO2_C3_ LCDC_D CIF_D1
H20 TXD0_M I
2_C3_d d 15 1_M1
1
RGMII_ I/O 1 down
LCDC_D16/RGMII_TXD1_M1/CIF_D12_M1/GPIO GPIO2_C4_ LCDC_D CIF_D1
H19 TXD1_M I
2_C4_d d 16 2_M1
1
CLK_OU I/O 1 down
LCDC_D17/CLK_OUT_ETHERNET_M1/CIF_D13_ GPIO2_C5_ LCDC_D T_ETHE CIF_D1
G21 I
M1/GPIO2_C5_d d 17 RNET_M 3_M1
1
RGMII_ I/O 1 down
LCDC_D18/RGMII_TXEN_M1/CIF_D14_M1/GPIO GPIO2_C6_ LCDC_D CIF_D1
G20 TXEN_M I
2_C6_d d 18 4_M1
1
RGMII_ I/O 1 down
LCDC_D19/RGMII_RXD2_M1/CIF_D15_M1/I2S1 GPIO2_C7_ LCDC_D CIF_D1
G19 RXD2_M I
_MCLK_M2/GPIO2_C7_d d 19 5_M1
1
I/O 1 down
LCDC_D2/RGMII_COL_M1/CIF_D2_M1/PWM5_M LCDC_D RGMII_ CIF_D2 UART4_ PWM5_
M21 GPIO2_A6 I
1/ UART4_TX_M1/GPIO2_A6_d 2 COL_M1 _M1 TX_M1 M1

RGMII_ I/O 1 down

LCDC_D20/RGMII_RXD3_M1/CIF_VSYNC_M1/I2 LCDC_D CIF_VS I2S1_S
H18 GPIO2_D0 RXD3_M I
S1_SDO_M2/GPIO2_D0_d 20 YNC_M1 DO_M2
1
RGMII_ CIF_CL I/O 1 down
LCDC_D21/RGMII_TXD2_M1/CIF_CLKOUT_M1/I LCDC_D I2S1_S
F21 GPIO2_D1 TXD2_M KOUT_ I
2S1_SCLK_M2/GPIO2_D1_d 21 CLK_M2
1 M1
RGMII_ I/O 1 down
LCDC_D22/RGMII_TXCLK_M1/CIF_CLKIN_M1/I2 LCDC_D CIF_CL I2S1_L
F20 GPIO2_D2 TXCLK_ I
S1_LRCK_M2/GPIO2_D2_d 22 KIN_M1 RCK_M2
M1

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RV1126 Datasheet Rev 1.2

PAD Driver Pull up /

Pin# Pin Name Func0 Func1 Func2 Func3 Func4 Func5 Func6 Func7 IO domain
Type Def Strength Pull down

RGMII_ I/O 1 down

LCDC_D23/RGMII_RXCLK_M1/CIF_HSYNC_M1/I LCDC_D CIF_HS I2S1_S
F19 GPIO2_D3 RXCLK_ I
2S1_SDI_M2/GPIO2_D3_d 23 YNC_M1 DI_M2
M1
I/O 1 down
LCDC_D3/I2S2_SDO_M1/UART4_RX_M1/PWM4_ LCDC_D I2S2_S UART4_ PWM4_ SPI0_C
M20 GPIO2_A7 I
M1/SPI0_CS0n_M2/GPIO2_A7_d 3 DO_M1 RX_M1 M1 S0n_M2

I/O 1 down
LCDC_D4/I2S2_SDI_M1/UART5_TX_M1/PWM3_I LCDC_D I2S2_S UART5_ PWM3_I SPI0_M
L19 GPIO2_B0 I
R_M1/SPI0_MOSI_M2/GPIO2_B0_d 4 DI_M1 TX_M1 R_M1 OSI_M2

I/O 1 down
LCDC_D5/I2S2_SCLK_M1/UART5_RX_M1/PWM2 LCDC_D I2S2_S UART5_ PWM2_ SPI0_M
L20 GPIO2_B1 I
_M1/SPI0_MISO_M2/GPIO2_B1_d 5 CLK_M1 RX_M1 M1 ISO_M2

UART5_ I/O 1 down

LCDC_D6/I2S2_LRCK_M1/UART5_RTSN_M1/PW LCDC_D I2S2_LR PWM1_ SPI0_CL
K16 GPIO2_B2 RTSN_M I
M1_M1/SPI0_CLK_M2/GPIO2_B2_d 6 CK_M1 M1 K_M2
1
LCDC_D7/I2S2_MCLK_M1/CIF_D3_M1/UART5_C UART5_ I/O 1 down
LCDC_D I2S2_M CIF_D3 PWM0_ SPI0_C I2C5_S
K17 TSN_M1/SPI0_CS1n_M2/PWM0_M1/I2C5_SDA_ GPIO2_B3 CTSN_M I
7 CLK_M1 _M1 M1 S1n_M2 DA_M0
M0/ GPIO2_B3_d 1
RGMII_ I/O 1 down
LCDC_D8/RGMII_RXDV_M1/CIF_D4_M1/GPIO2_ LCDC_D CIF_D4
K18 GPIO2_B4 RXDV_ I
B4_d 8 _M1
M1
RGMII_ I/O 1 down
LCDC_D9/RGMII_RXD0_M1/CIF_D5_M1/GPIO2_ LCDC_D CIF_D5
K19 GPIO2_B5 RXD0_M I
B5_d 9 _M1
1
I/O 1 down
LCDC_DEN/PWM6_M1/SPI1_CS0n_M2/I2C3_SCL LCDC_D PWM6_ SPI1_C I2C3_S
J17 GPIO2_D4 I
_M1/GPIO2_D4_d EN M1 S0n_M2 CL_M1

I/O 1 down
LCDC_HSYNC/PWM10_M1/ SPI1_CLK_M2 LCDC_H PWM10 SPI1_CL I2C3_S
H17 GPIO2_D5 I
/I2C3_SDA_M1/GPIO2_D5_d SYNC _M1 K_M2 DA_M1

UART3_ I/O 1 down

LCDC_VSYNC/UART3_RTSN_M2/PWM9_M1/SPI1 LCDC_V PWM9_ SPI1_M
C21 GPIO2_D6 RTSN_M I
_MOSI_M2/GPIO2_D6_d SYNC M1 OSI_M2
2
A7_JTA I/O 1 up
UART2_
H16 UART2_RX_M1/A7_JTAG_TMS_M1/GPIO3_A3_u GPIO3_A3 G_TMS_ I
RX_M1
M1
A7_JTA I/O 1 up
UART2_
G18 UART2_TX_M1/A7_JTAG_TCK_M1/GPIO3_A2_u GPIO3_A2 G_TCK_ I
TX_M1
M1
CLK_OU I/O 1 down
UART3_
CIF_CLKIN_M0/CLK_OUT_ETHERNET_M0/UART3 CIF_CLK T_ETHE
M19 GPIO3_C5 CTSN_M I
_CTSN_M0/GPIO3_C5_d IN_M0 RNET_M
0
0
RGMII_ I/O 1 down
CIF_CLKOUT_M0/RGMII_TXCLK_M0/UART3_TX_ CIF_CLK UART3_
P19 GPIO3_C6 TXCLK_ I
M0/GPIO3_C6_d OUT_M0 TX_M0
M0
VCCIO6
I2S0_S I/O 1 down
CIF_D0_M0/I2S0_SCLK_TX_M1/UART4_TX_M0/I CIF_D0 UART4_ I2C3_S PWM8_
R17 GPIO3_A4 CLK_TX I
2C3_SCL_M0/PWM8_M0/GPIO3_A4_d _M0 TX_M0 CL_M0 M0
_M1
RGMII_ I/O 1 down
CIF_D10_M0/RGMII_RXD0_M0/PDM_SDI2_M1/S CIF_D1 PDM_S SPI1_M
R20 GPIO3_B6 RXD0_M I
PI1_MOSI_M0/GPIO3_B6_d 0_M0 DI2_M1 OSI_M0
0

Copyright 2020 ©Fuzhou Rockchip Electronics Co., Ltd. 32

RV1126 Datasheet Rev 1.2

PAD Driver Pull up /

Pin# Pin Name Func0 Func1 Func2 Func3 Func4 Func5 Func6 Func7 IO domain
Type Def Strength Pull down

RGMII_ I/O 1 down

CIF_D11_M0/RGMII_RXD1_M0/PDM_SDI3_M1/S CIF_D1 PDM_S SPI1_MI
R21 GPIO3_B7 RXD1_M I
PI1_MISO_M0/GPIO3_B7_d 1_M0 DI3_M1 SO_M0
0
I/O 1 down
CIF_D12_M0/RGMII_CLK_M0/PDM_CLk0_M1/SP CIF_D1 RGMII_ PDM_CL
N19 GPIO3_C0 I
I1_CLK_M0/GPIO3_C0_d 2_M0 CLK_M0 k0_M1

RGMII_ I/O 1 down

CIF_D13_M0/RGMII_RXDV_M0/PDM_SDI0_M1/ CIF_D1 PDM_S
M17 GPIO3_C1 RXDV_ I
GPIO3_C1_d 3_M0 DI0_M1
M0
RGMII_ I/O 1 down
CIF_D14_M0/RGMII_RXER_M0/PDM_SDI1_M1/G CIF_D1 PDM_S
M18 GPIO3_C2 RXER_M I
PIO3_C2_d 4_M0 DI1_M1
0
RGMII_ I/O 1 down
CIF_D15_M0/RGMII_MDIO_M0/PDM_CLk1_M1/G CIF_D1 PDM_CL
N20 GPIO3_C3 MDIO_ I
PIO3_C3_d 5_M0 k1_M1
M0
CIF_D1_M0/RGMII_CRS_M0/I2S0_LRCK_TX_M1 I2S0_LR I/O 1 down
CIF_D1 RGMII_ UART4_ I2C3_S PWM9_
T18 /UART4_RX_M0/I2C3_SDA_M0/PWM9_M0/GPIO GPIO3_A5 CK_TX_ I
_M0 CRS_M0 RX_M0 DA_M0 M0
3_A5_d M1
CIF_D2_M0/RGMII_COL_M0/I2S0_SDO0_M1/UA I2S0_S I/O 1 down
CIF_D2 RGMII_ UART5_ CAN_RX PWM10
P17 RT5_TX_M0/CAN_RXD_M1/PWM10_M0/GPIO3_A GPIO3_A6 DO0_M I
_M0 COL_M0 TX_M0 D_M1 _M0
6_d 1
CIF_D3_M0/RGMII_RXD2_M0/I2S0_SDI0_M1/U RGMII_ I/O 1 down
CIF_D3 I2S0_S UART5_ CAN_TX PWM11
R18 ART5_RX_M0/CAN_TXD_M1/PWM11_IR_M0/GPI GPIO3_A7 RXD2_M I
_M0 DI0_M1 RX_M0 D_M1 _IR_M0
O3_A7_d 0
RGMII_ UART5_ I/O 1 down
CIF_D4_M0/RGMII_RXD3_M0/I2S0_MCLK_M1/U CIF_D4 I2S0_M I2C5_S
T19 GPIO3_B0 RXD3_M RTSN_M I
ART5_RTSN_M0/I2C5_SCL_M1/GPIO3_B0_d _M0 CLK_M1 CL_M1
0 0
RGMII_ I2S0_S UART5_ I/O 1 down
CIF_D5_M0/RGMII_TXD2_M0/I2S0_SCLK_RX_M CIF_D5 I2C5_S
T20 GPIO3_B1 TXD2_M CLK_RX CTSN_M I
1/UART5_CTSN_M0/I2C5_SDA_M1/GPIO3_B1_d _M0 DA_M1
0 _M1 0
RGMII_ I2S0_LR UART4_ I/O 1 down
CIF_D6_M0/RGMII_TXD3_M0/I2S0_LRCK_RX_M CIF_D6
N17 GPIO3_B2 TXD3_M CK_RX_ RTSN_M I
1/UART4_RTSN_M0/GPIO3_B2_d _M0
0 M1 0
RGMII_ I2S0_S UART4_ I/O 1 down
CIF_D7_M0/RGMII_TXD0_M0/I2S0_SDO1_SDI3 CIF_D7
R19 GPIO3_B3 TXD0_M DO1_S CTSN_M I
_M1/UART4_CTSN_M0/GPIO3_B3_d _M0
0 DI3_M1 0
RGMII_ I2S0_S I/O 1 down
CIF_D8_M0/RGMII_TXD1_M0/I2S0_SDO2_SDI2 CIF_D8 SPI1_C
T21 GPIO3_B4 TXD1_M DO2_S I
_M1/SPI1_CS1n_M0/GPIO3_B4_d _M0 S1n_M0
0 DI2_M1
RGMII_ I2S0_S I/O 1 down
CIF_D9_M0/RGMII_TXEN_M0/I2S0_SDO3_SDI1 CIF_D9 SPI1_C
N18 GPIO3_B5 TXEN_M DO3_S I
_M1/SPI1_CS0n_M0/GPIO3_B5_d _M0 S0n_M0
0 DI1_M1
RGMII_ I/O 1 down
CIF_HSYNC_M0/RGMII_RXCLK_M0/UART3_RX_ CIF_HS UART3_
P20 GPIO3_C7 RXCLK_ I
M0/GPIO3_C7_d YNC_M0 RX_M0
M0
RGMII_ UART3_ I/O 1 down
CIF_VSYNC_M0/RGMII_MDC_M0/UART3_RTSN_ CIF_VS
N21 GPIO3_C4 MDC_M RTSN_M I
M0/GPIO3_C4_d YNC_M0
0 0
I2S0_LR ACODE I/O 1 down
I2S0_LRCK_RX_M0/PDM_CLk0_M0/ACODEC_AD PDM_CL
Y12 GPIO3_D4 CK_RX_ C_ADC_ I VCCIO7
C_SYNC/GPIO3_D4_d k0_M0
M0 SYNC

Copyright 2020 ©Fuzhou Rockchip Electronics Co., Ltd. 33

RV1126 Datasheet Rev 1.2

PAD Driver Pull up /

Pin# Pin Name Func0 Func1 Func2 Func3 Func4 Func5 Func6 Func7 IO domain
Type Def Strength Pull down

I2S0_LR ACODE I/O 1 down

I2S0_LRCK_TX_M0/ACODEC_DAC_SYNC/AUDPW AUDPW AUDDS
W11 GPIO3_D3 CK_TX_ C_DAC_ I
M_L_M1/AUDDSM_LN/GPIO3_D3_d M_L_M1 M_LN
M0 SYNC
I/O 1 down
I2S0_M
U12 I2S0_MCLK_M0/GPIO3_D2_d GPIO3_D2 I
CLK_M0

I2S0_S ACODE I/O 1 down

I2S0_SCLK_RX_M0/PDM_CLk1_M0/ACODEC_AD PDM_CL
V12 GPIO3_D1 CLK_RX C_ADC_ I
C_CLK/GPIO3_D1_d k1_M0
_M0 CLK
I2S0_S ACODE I/O 1 down
I2S0_SCLK_TX_M0/ACODEC_DAC_CLK/GPIO3_
W12 GPIO3_D0 CLK_TX C_DAC_ I
D0_d
_M0 CLK
ACODE I/O 1 down
I2S0_SDI0_M0/PDM_SDI0_M0/ACODEC_DAC_D I2S0_S PDM_S
AA12 GPIO3_D6 C_DAC_ I
ATAL/GPIO3_D6_d DI0_M0 DI0_M0
DATAL
I2S0_S ACODE AUDPW I/O 1 down
I2S0_SDO0_M0/ACODEC_DAC_DATAR/AUDPWM AUDDS
Y11 GPIO3_D5 DO0_M C_DAC_ M_R_M I
_R_M1/AUDDSM_LP/GPIO3_D5_d M_LP
0 DATAR 1
I2S0_S ACODE I/O 1 down
I2S0_SDO1_SDI3_M0/PDM_SDI3_M0/ACODEC_ PDM_S
T11 GPIO3_D7 DO1_SD C_ADC_ I
ADC_DATA/GPIO3_D7_d DI3_M0
I3_M0 DATA
I2S0_S I/O 1 down
I2S0_SDO2_SDI2_M0/PDM_SDI2_M0/AUDPWM_ PDM_S AUDPW I2C4_S AUDDS
U11 GPIO4_A0 DO2_SD I
L_M0/I2C4_SCL_M1/AUDDSM_RN/GPIO4_A0_d DI2_M0 M_L_M0 CL_M1 M_RN
I2_M0
I2S0_S AUDPW I/O 1 down
I2S0_SDO3_SDI1_M0/PDM_SDI1_M0/AUDPWM_ PDM_S I2C4_S AUDDS
V11 GPIO4_A1 DO3_SD M_R_M I
R_M0/I2C4_SDA_M1/AUDDSM_RP/GPIO4_A1_d DI1_M0 DA_M1 M_RP
I1_M0 0
I/O 1 z
CLKI_CL
AA3 CLKI_CLKO_32K/GPIO0_A2_z GPIO0_A2 I
KO_32K

I/O 1 down
CLK_RE
W6 CLK_REF/GPIO0_A0_d GPIO0_A0 I
F

I/O 1
SDMMC
U7 SDMMC0_DET/GPIO0_A3_u GPIO0_A3 I up
0_DET

I/O 1 down
SPI0_CL
Y4 SPI0_CLK_M0/GPIO0_B0_d GPIO0_B0 I
K_M0
PMUIO0
I/O 1 down
SPI0_C
AA2 SPI0_CS0n_M0/GPIO0_A5_u GPIO0_A5 I
S0n_M0

I/O 1 up
SPI0_C
V7 SPI0_CS1n_M0/GPIO0_A4_u GPIO0_A4 I
S1n_M0

I/O 1 up
SPI0_MI
W5 SPI0_MISO_M0/GPIO0_A7_d GPIO0_A7 I
SO_M0

I/O 1 down
SPI0_M
V6 SPI0_MOSI_M0/GPIO0_A6_d GPIO0_A6 I
OSI_M0

Copyright 2020 ©Fuzhou Rockchip Electronics Co., Ltd. 34

RV1126 Datasheet Rev 1.2

PAD Driver Pull up /

Pin# Pin Name Func0 Func1 Func2 Func3 Func4 Func5 Func6 Func7 IO domain
Type Def Strength Pull down

TSADC_ TSADC_ I/O 1 z

TSADC_SHUT_M0/TSADC_SHUTORG/GPIO0_A1_
Y5 GPIO0_A1 SHUT_M SHUTOR I
z
0 G
FLASH_ I/O 1 down
Y8 FLASH_VOL_SEL/GPIO0_B3_d GPIO0_B3 VOL_SE I
L
I/O 1 down
I2C0_S
AA7 I2C0_SCL/GPIO0_B4_u GPIO0_B4 I
CL

I/O 1 up
I2C0_S
Y7 I2C0_SDA/GPIO0_B5_u GPIO0_B5 I
DA

I/O 1 up
I2C2_S PWM4_
AA6 I2C2_SCL/PWM4_M0/GPIO0_C2_d GPIO0_C2 I
CL M0

I/O 1 down
I2C2_S PWM5_
Y6 I2C2_SDA/PWM5_M0/GPIO0_C3_d GPIO0_C3 I
DA M0

I/O 1 down
PMIC_I PWM7_I
W10 PMIC_IN/PWM7_IR_M0/GPIO0_B1_d GPIO0_B1 I PMUIO1
NT R_M0

TSADC_ I/O 1 down

PMIC_SLEEP/TSADC_SHUT_M1/PWM6_M0/GPIO PMIC_S PWM6_
Y10 GPIO0_B2 SHUT_M I
0_B2_d LEEP M0
1
UART1_ I/O 1 down
PMU_DEBUG/UART1_CTSN_M0/PWM3_IR_M0/G PMU_DE PWM3_I
AA4 GPIO0_C1 CTSN_M I
PIO0_C1_d BUG R_M0
0
UART1_ I/O 1 down
SDMMC0_PWR /UART1_RTSN_M0/ SDMMC PWM2_
U9 GPIO0_C0 RTSN_M I
PWM2_M0/GPIO0_C0_d 0_PWR M0
0
I/O 1 down
UART1_ PWM1_
V9 UART1_RX_M0/PWM1_M0/GPIO0_B7_d GPIO0_B7 I
RX_M0 M0

I/O 1 down
UART1_ PWM0_
W8 UART1_TX_M0/PWM0_M0/GPIO0_B6_d GPIO0_B6 I
TX_M0 M0

W7 NPOR_u NPOR A

A
T8 TVSS_d TVSS

A
AA9 XIN24M XIN24M

A
Y9 XOUT24M XOUT24M

A
E17 ADCIN0 ADCIN0

Copyright 2020 ©Fuzhou Rockchip Electronics Co., Ltd. 35

RV1126 Datasheet Rev 1.2

PAD Driver Pull up /

Pin# Pin Name Func0 Func1 Func2 Func3 Func4 Func5 Func6 Func7 IO domain
Type Def Strength Pull down

A
D17 ADCIN1 ADCIN1

A
B18 ADCIN2 ADCIN2

A
A18 ADCIN3 ADCIN3

A
C17 ADCIN4 ADCIN4

A
B17 ADCIN5 ADCIN5

A
N3 DDR_DM0 DDR_DM0

A
E2 DDR_DM1 DDR_DM1

A
K4 DDR_DQ0 DDR_DQ0

A
J4 DDR_DQ1 DDR_DQ1

A
H2 DDR_DQ10 DDR_DQ10

A
H1 DDR_DQ11 DDR_DQ11

A
G1 DDR_DQ12 DDR_DQ12

A
E1 DDR_DQ13 DDR_DQ13

A
C1 DDR_DQ14 DDR_DQ14

A
C2 DDR_DQ15 DDR_DQ15

A
P4 DDR_DQ2 DDR_DQ2

A
N4 DDR_DQ3 DDR_DQ3

Copyright 2020 ©Fuzhou Rockchip Electronics Co., Ltd. 36

RV1126 Datasheet Rev 1.2

PAD Driver Pull up /

Pin# Pin Name Func0 Func1 Func2 Func3 Func4 Func5 Func6 Func7 IO domain
Type Def Strength Pull down

A
J3 DDR_DQ4 DDR_DQ4

A
K3 DDR_DQ5 DDR_DQ5

A
M4 DDR_DQ6 DDR_DQ6

A
P3 DDR_DQ7 DDR_DQ7

A
D2 DDR_DQ8 DDR_DQ8

A
D1 DDR_DQ9 DDR_DQ9

A
DDR_DQS0
L4 DDR_DQS0P
P

A
DDR_DQS1
F2 DDR_DQS1P
P

A
DDR_DQS0
L3 DDR_DQS0N
N

A
DDR_DQS1
F1 DDR_DQS1N
N

A
C9 DDR_A0 DDR_A0

A
B7 DDR_A1 DDR_A1

A
A10 DDR_A10 DDR_A10

A
C11 DDR_A11 DDR_A11

A
D7 DDR_A12 DDR_A12

A
A12 DDR_A13 DDR_A13

A
A11 DDR_A14 DDR_A14

Copyright 2020 ©Fuzhou Rockchip Electronics Co., Ltd. 37

RV1126 Datasheet Rev 1.2

PAD Driver Pull up /

Pin# Pin Name Func0 Func1 Func2 Func3 Func4 Func5 Func6 Func7 IO domain
Type Def Strength Pull down

A
B5 DDR_A15 DDR_A15

A
B10 DDR_A16 DDR_A16

A
B11 DDR_A2 DDR_A2

A
B6 DDR_A3 DDR_A3

A
A9 DDR_A4 DDR_A4

A
A7 DDR_A5 DDR_A5

A
C8 DDR_A6 DDR_A6

A
B8 DDR_A7 DDR_A7

A
A8 DDR_A8 DDR_A8

A
B9 DDR_A9 DDR_A9

A
A4 DDR_ACTN DDR_ACTN

A
M2 DDR_DM2 DDR_DM2

A
B3 DDR_DM3 DDR_DM3

A
K1 DDR_DQ16 DDR_DQ16

A
K2 DDR_DQ17 DDR_DQ17

A
G4 DDR_DQ26 DDR_DQ26

A
F4 DDR_DQ27 DDR_DQ27

Copyright 2020 ©Fuzhou Rockchip Electronics Co., Ltd. 38

RV1126 Datasheet Rev 1.2

PAD Driver Pull up /

Pin# Pin Name Func0 Func1 Func2 Func3 Func4 Func5 Func6 Func7 IO domain
Type Def Strength Pull down

A
H3 DDR_DQ28 DDR_DQ28

A
G3 DDR_DQ29 DDR_DQ29

A
B1 DDR_DQ30 DDR_DQ30

A
B2 DDR_DQ31 DDR_DQ31

A
J1 DDR_DQ18 DDR_DQ18

A
J2 DDR_DQ19 DDR_DQ19

A
P2 DDR_DQ20 DDR_DQ20

A
L1 DDR_DQ21 DDR_DQ21

A
M1 DDR_DQ22 DDR_DQ22

A
P1 DDR_DQ23 DDR_DQ23

A
A2 DDR_DQ24 DDR_DQ24

A
A3 DDR_DQ25 DDR_DQ25

A
DDR_DQS2
N2 DDR_DQS2P
P

A
DDR_DQS3
D3 DDR_DQS3P
P

A
DDR_DQS2
N1 DDR_DQS2N
N

A
DDR_DQS3
E3 DDR_DQS3N
N

A
E7 DDR_BA0 DDR_BA0

Copyright 2020 ©Fuzhou Rockchip Electronics Co., Ltd. 39

RV1126 Datasheet Rev 1.2

PAD Driver Pull up /

Pin# Pin Name Func0 Func1 Func2 Func3 Func4 Func5 Func6 Func7 IO domain
Type Def Strength Pull down

A
A6 DDR_BA1 DDR_BA1

A
D6 DDR_BG0 DDR_BG0

A
D11 DDR_BG1 DDR_BG1

A
D4 DDR_CLKP DDR_CLKP

A
D5 DDR_CLKN DDR_CLKN

A
C6 DDR_CKE DDR_CKE

A
B4 DDR_CS0N DDR_CS0N

A
D8 DDR_CS1N DDR_CS1N

A
A5 DDR_ODT0 DDR_ODT0

A
D10 DDR_ODT1 DDR_ODT1

A
M6 DDR_VREF DDR_VREF

A
DDR_RESE
C4 DDR_RESETn
Tn

A
E5 DDR_RZQ DDR_RZQ

MIPI_CSI_ A
RX0_CLKP/
U15 MIPI_CSI_RX0_CLKP/LVDS0_CLKP
LVDS0_CLK
P
MIPI_CSI_ A
RX0_CLKN/
V15 MIPI_CSI_RX0_CLKN/LVDS0_CLKN
LVDS0_CLK
N
MIPI_CSI_ A
RX0_D0N/L
U16 MIPI_CSI_RX0_D0N/LVDS0_RX0N
VDS0_RX0
N
MIPI_CSI_ A
RX0_D1N/L
W16 MIPI_CSI_RX0_D1N/LVDS0_RX1N
VDS0_RX1
N

Copyright 2020 ©Fuzhou Rockchip Electronics Co., Ltd. 40

RV1126 Datasheet Rev 1.2

PAD Driver Pull up /

Pin# Pin Name Func0 Func1 Func2 Func3 Func4 Func5 Func6 Func7 IO domain
Type Def Strength Pull down

MIPI_CSI_ A
RX0_D2N/L
Y15 MIPI_CSI_RX0_D2N/LVDS0_RX2N
VDS0_RX2
N
MIPI_CSI_ A
RX0_D3N/L
AA16 MIPI_CSI_RX0_D3N/LVDS0_RX3N
VDS0_RX3
N
MIPI_CSI_ A
RX0_D0P/L
V16 MIPI_CSI_RX0_D0P/LVDS0_RX0P
VDS0_RX0
P
MIPI_CSI_ A
RX0_D1P/L
Y16 MIPI_CSI_RX0_D1P/LVDS0_RX1P
VDS0_RX1
P
MIPI_CSI_ A
RX0_D2P/L
W15 MIPI_CSI_RX0_D2P/LVDS0_RX2P
VDS0_RX2
P
MIPI_CSI_ A
RX0_D3P/L
AA15 MIPI_CSI_RX0_D3P/LVDS0_RX3P
VDS0_RX3
P
MIPI_CSI_ A
T15 MIPI_CSI_RX0_AVDD_0V8 RX0_AVDD
_0V8
MIPI_CSI_ A
T16 MIPI_CSI_RX0_AVDD_1V8 RX0_AVDD
_1V8
MIPI_CSI_ A
RX1_CLKP/
V18 MIPI_CSI_RX1_CLKP/LVDS1_CLKP
LVDS1_CLK
P
MIPI_CSI_ A
RX1_CLKN/
W18 MIPI_CSI_RX1_CLKN/LVDS1_CLKN
LVDS1_CLK
N
MIPI_CSI_ A
RX1_D0N/L
Y20 MIPI_CSI_RX1_D0N/LVDS1_RX0N
VDS1_RX0
N
MIPI_CSI_ A
RX1_D1N/L
Y19 MIPI_CSI_RX1_D1N/LVDS1_RX1N
VDS1_RX1
N
MIPI_CSI_ A
RX1_D2N/L
Y18 MIPI_CSI_RX1_D2N/LVDS1_RX2N
VDS1_RX2
N
MIPI_CSI_ A
RX1_D3N/L
W17 MIPI_CSI_RX1_D3N/LVDS1_RX3N
VDS1_RX3
N
MIPI_CSI_ A
RX1_D0P/L
AA20 MIPI_CSI_RX1_D0P/LVDS1_RX0P
VDS1_RX0
P

Copyright 2020 ©Fuzhou Rockchip Electronics Co., Ltd. 41

RV1126 Datasheet Rev 1.2

PAD Driver Pull up /

Pin# Pin Name Func0 Func1 Func2 Func3 Func4 Func5 Func6 Func7 IO domain
Type Def Strength Pull down

MIPI_CSI_ A
RX1_D1P/L
AA19 MIPI_CSI_RX1_D1P/LVDS1_RX1P
VDS1_RX1
P
MIPI_CSI_ A
RX1_D2P/L
AA18 MIPI_CSI_RX1_D2P/LVDS1_RX2P
VDS1_RX2
P
MIPI_CSI_ A
RX1_D3P/L
Y17 MIPI_CSI_RX1_D3P/LVDS1_RX3P
VDS1_RX3
P
MIPI_CSI_ A
R15 MIPI_CSI_RX1_AVDD_0V8 RX1_AVDD
_0V8
MIPI_CSI_ A
R16 MIPI_CSI_RX1_AVDD_1V8 RX1_AVDD
_1V8
A
MIPI_DSI_
A19 MIPI_DSI_TX0_D0P
TX0_D0P

A
MIPI_DSI_
C18 MIPI_DSI_TX0_CLKN
TX0_CLKN

A
MIPI_DSI_
C19 MIPI_DSI_TX0_CLKP
TX0_CLKP

A
MIPI_DSI_
B19 MIPI_DSI_TX0_D0N
TX0_D0N

A
MIPI_DSI_
B20 MIPI_DSI_TX0_D1N
TX0_D1N

A
MIPI_DSI_
C20 MIPI_DSI_TX0_D2N
TX0_D2N

A
MIPI_DSI_
D19 MIPI_DSI_TX0_D3N
TX0_D3N

A
MIPI_DSI_
A20 MIPI_DSI_TX0_D1P
TX0_D1P

A
MIPI_DSI_
B21 MIPI_DSI_TX0_D2P
TX0_D2P

A
MIPI_DSI_
D20 MIPI_DSI_TX0_D3P
TX0_D3P

MIPI_DSI_ A
E18 MIPI_DSI_TX0_AVDD_0V8 TX0_AVDD
_0V8
MIPI_DSI_ A
E18 MIPI_DSI_TX0_AVDD_0V8 TX0_AVDD
_0V8

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RV1126 Datasheet Rev 1.2

PAD Driver Pull up /

Pin# Pin Name Func0 Func1 Func2 Func3 Func4 Func5 Func6 Func7 IO domain
Type Def Strength Pull down

MIPI_DSI_ A
E18 MIPI_DSI_TX0_AVDD_0V8 TX0_AVDD
_0V8
MIPI_DSI_ A
G15 MIPI_DSI_TX0_AVDD_1V8 TX0_AVDD
_1V8
MIPI_DSI_ A
G15 MIPI_DSI_TX0_AVDD_1V8 TX0_AVDD
_1V8
MIPI_DSI_ A
G15 MIPI_DSI_TX0_AVDD_1V8 TX0_AVDD
_1V8
MIPI_DSI_ A
G15 MIPI_DSI_TX0_AVDD_1V8 TX0_AVDD
_1V8
A
Y3 OTG_ID OTG_ID

A
OTG_VBUS
V5 OTG_VBUS1V8
1V8

A
USB_AVDD
R7 USB_AVDD_1V8
_1V8

A
W3 OTG_DP OTG_DP

A
W4 OTG_DM OTG_DM

A
U6 OTG_EXTR OTG_EXTR

A
USB_AVDD
T7 USB_AVDD_3V3
_3V3

A
USB_AVDD
R6 USB_AVDD_0V8
_0V8

A
USB_AVDD
R7 USB_AVDD_1V8
_1V8

A
Y1 HOST_DP HOST_DP

A
Y2 HOST_DM HOST_DM

A
HOST_EXT
U5 HOST_EXTR
R

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RV1126 Datasheet Rev 1.2
Notes:
①:Type: I = input, O = output, I/O = input/output (bidirectional), A = Analog
②:Output Drive Unit is mA, only Digital IO has driver strength value;
③:Def: I = input without any pull resistor, O = output without any pull resistor;
④:INT: interrupt
⑤:Driver Strength: 1 means Level1, 2 means Level2

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RV1126 Datasheet Rev 1.2

2.7 IO Pin Name Description

This sub-chapter will focus on the detailed function description of every pins based on
different interface.
Table 2-4 IO function description list
Interface Pin Name Direction Description

XIN24M I Clock input of 24MHz crystal

XOUT24M O Clock output of 24MHz crystal

Misc
NPOR_u I Chip hardware reset

TVSS I Test mode

Interface Pin Name Direction Description

Cortex-A7 JTAG interface clock input/SWD
A7_JTAG_TCK I
interface clock input
A7 SWJ-DP
Cortex-A7 JTAG interface TMS input/SWD
A7_JTAG_TMS I/O
interface data out

Interface Pin Name Direction Description

RISC-V_JTAG_TRSTn I RISC-V JTAG reset signal
RISC-V_JTAG_TCK I RISC-V JTAG interface TCK input
RISC-V
RISC-V_JTAG_TMS I RISC-V JTAG mode selection input signal
JTAG
RISC-V_JTAG_TDO O RISC-V JTAG interface TDO output
RISC-V_JTAG_TDI I RISC-V JTAG interface TDI input

Interface Pin Name Direction Description

SDMMC0_CLK O sdmmc card clock
sdmmc card command output and response
SDMMC0_CMD I/O
SDMMC input
Host
Controller SDMMC0_Di (i=0~3) I/O sdmmc card data input and output

sdmmc card detect signal, 0 represents

SDMMC0_DETN I
presence of card

Interface Pin Name Direction Description

SDIO_CLK O sdio card clock
SDIO Host
SDIO_CMD I/O sdio card command output and response input
Controller
SDIO_Di (i=0~3) I/O sdio card data input and output

Interface Pin Name Direction Description

EMMC_CLKO O emmc card clock
eMMC emmc card command output and response
EMMC_CMD I/O
Interface input
EMMC_Di (i=0~7) I/O emmc card data input and output

Interface Pin Name Direction Description

FSPI_CLK O FSPI serial clock

FSPI
FSPI_CSin(i=0,1) O FSPI chip select signal,low active
Controller

FSPI_Di(i=0~3) I/O FSPI serial data output

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RV1126 Datasheet Rev 1.2
Interface Pin Name Direction Description
FLASH_ALE O Flash address latch enable signal
FLASH_CLE O Flash command latch enable signal
FLASH_WRn O Flash write enable and clock signal
FLASH_RDn O Flash read enable and write/read signal
NAND
FLASH_RDYn I Flash ready/busy signal
FLASH_CS0n O Flash chip enable signal for chip
FLASH_WPn O Flash write-protected signal
FLASH_DATAi(i=0~7) I/O Flash data inputs/outputs signal

Interface Pin Name Direction Description

LCDC_CLK O LCDC RGB interface display clock out, MCU i80

interface RS signal

LCDC_VSYNC O LCDC RGB interface vertical sync pulse, MCU

LCDC i80 interface CSN signal
interface LDCD_HSYNC O LCDC RGB interface horizontal sync pulse, MCU
&BT.1120 i80 interface WEN signal

LCDC_DEN O LCDC RGB interface data enable, MCU i80

interface REN signal
LCDC_Di (i=0~23) O LCDC data output/input or BT.1120(i=0~15)

Interface Pin Name Direction Description

DDR_CLKP O Active-high clock signal
DDR_CLKN O Active-low clock signal

DDR_CKE O Active-high clock enable signal

Active-low chip select signal .There are two chip

DDR_CSin (i=0,1) O
select

DDR_RASn O Active-low row address strobe

DDR_CASn O Active-low column address strobe

DDR_WEn O Active-low write enable strobe

DDR
Interface DDR_BAi(i=0,1,2) O Bank address signal
DDR_Ai(i=0~16) O Address signal
DDR_DQi(i=0~31) I/O Bidirectional data line
DDR_DQSi_P
I/O Active-high bidirectional data strobes
(i=0~3)
DDR_DQSi_N
I/O Active-low bidirectional data strobes
(i=0~3)

DDR_DMi (i=0~3) O Active-low data mask signal

On-Die Termination output signal for two chip

DDR_ODTi (i=0,1) O
select.
DDR_RESETn O DDR3/DDR4 reset signal

Interface Pin Name Direction Description

I2S0_MCLK O I2S/PCM clock to external device
I2S0_SCLK_TX I/O I2S/PCM serial clock
I2S0_SCLK_RX I/O I2S/PCM serial clock
I2S/PCM left & right channel signal for receiving
I2S0_8CH serial data, synchronous left & right channel in
Controller I2S0_LRCK_RX I/O
I2S mode and the beginning of a group of left &
right channels in PCM mode
I2S/PCM left & right channel signal for
transmitting serial data, synchronous left &
I2S0_LRCK_TX I/O
right channel in I2S mode and the beginning of
a group of left & right channels in PCM mode

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RV1126 Datasheet Rev 1.2
Interface Pin Name Direction Description
I2S0_SDI0 I I2S/PCM serial data input
I2S0_SDO0 O I2S/PCM serial data output
I2S0_SDO1_SDI3 I/O
I2S0_SDO2_SDI2 I/O I2S/PCM serial data input/output
I2S0_SDO3_SDI1 I/O

Interface Pin Name Direction Description

I2Si_MCLK O I2S/PCM clock source
I2Si_SCLK I/O I2S/PCM serial clock
I2S/PCM left & right channel signal for receiving
I2Si_2CH serial data, synchronous left & right channel in
Controller I2Si_LRCK I/O
I2S mode and the beginning of a group of left &
(i=1,2) right channels in PCM mode
I2Si_SDI I I2S/PCM serial data input

I2Si_SDO O I2S/PCM serial data output

Interface Pin Name Direction Description

PDM_CLK i (i=0~1) O PDM clock signal

PDM
PDM_SDIi (i=0~3) I PDM input data

Interface Pin Name Direction Description

SPIi_CLK I/O SPI serial clock

SPIi_CSin (i=0,1) I/O SPI chip select signal, low active

SPIi (i=0,1

SPIi_TXD O SPI serial data output

SPIi_RXD I SPI serial data input

Interface Pin Name Direction Description

PWM0 I/O Pulse Width Modulation input or output
PWM1 I/O Pulse Width Modulation input or output
PWM2 I/O Pulse Width Modulation input or output
I/O Pulse Width Modulation input or output, used
PWM3
for IR application recommended
PWM5 I/O Pulse Width Modulation input and output
PWM6 I/O Pulse Width Modulation input or output
PWM
I/O Pulse Width Modulation input or output, used
PWM7
for IR application recommended
PWM8 I/O Pulse Width Modulation input or output
PWM9 I/O Pulse Width Modulation input or output
PWM10 I/O Pulse Width Modulation input or output
I/O Pulse Width Modulation input or output, used
PWM11
for IR application recommended

Interface Pin Name Direction Description

I2Ci_SDA
I/O Data/Address of I2C
(i=0,1,2,3,4,5)
I2C
I2Ci_SCL
I/O Clock of I2C
(i=0,1,2,3,4,5)

Interface Pin Name Direction Description

UARTi_RX
UART I UART serial data input
(i=0,1,2,3,4,5)

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RV1126 Datasheet Rev 1.2
Interface Pin Name Direction Description
UARTi_TX
O UART serial data output
(i=0,1,2,3,4,5)
UARTi_CTS
I UART clear-to-send signal
(i=0,1,3,4,5)
UARTi_RTS
O UART request-to-send signal
(i=0,1,3,4,5)

Interface Pin Name Direction Description

CLK_OUT_ETHERNET O output reference clock to PHY
RGMII_CLK I/O MAC REC_CLK output or external clock input
RGMII_TXCLK O MAC TX clock
RGMII_RXCLK I MAC RX clock
RX data validity and carrier sense signal of the
RGMII_RXDV I
RMII
RGMII_MDC O MAC management interface clock
RGMII_MDIO I/O MAC management interface data
GMAC
RGMII_TXDi(i=0~3) O MAC TX data
RGMII_RXDi(i=0~3) I MAC RX data
RGMII_TXEN O MAC TX data validity signal
RGMII_RXER I MAC RX error signal
RGMII_RXDV O MAC RX enable
RGMII_CRS I PHY CRS signal
RGMII_COL I PHY collision detected

Interface Pin Name Direction Description

HOST_DP I/O USB 2.0 Data signal DP

USB 2.0 HOST_DM I/O USB 2.0 Data signal DM

HOST
Connect 200 ohm resistor to ground to
HOST_RREF I/O
generate reference current

Interface Pin Name Direction Description

OTG_DP I/O USB 2.0 Data signal DP

OTG_DM I/O USB 2.0 Data signal DM

USB 2.0 Connect 200 ohm resistor to ground to

OTG_RREF I/O
OTG generate reference current

OTG_VBUS I Insert detect when act as USB device

OTG_ID I USB Mini-Receptacle Identifier

Interface Pin Name Direction Description

MIPI_CSI_CLKi(i=0,1) O clock output for sensor
CIF_Di(i=0~15) I Camera interface input pixel data
VICAP
(Camera CIF_VSYNC I Camera interface vertical sync signal
IF)
CIF_CLKIN I Camera interface input pixel clock
CIF_HSYNC I Camera interface horizontal sync signal

Interface Pin Name Direction Description

MIPI DSI negative differential data line
MIPI_DSI_TX0_DiN(i=0~3) O
transceiver output
MIPI DSI positive differential data line
MIPI_DSI MIPI_DSI_TX0_DiP(i=0~3) O
transceiver output
MIPI DSI positive differential clock line
MIPI_DSI_TX0_CLKP O
transceiver output

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RV1126 Datasheet Rev 1.2
Interface Pin Name Direction Description
MIPI DSI negative differential clock line
MIPI_DSI_TX0_CLKN O
transceiver output

Interface Pin Name Direction Description

MIPI_CSI_RX0_DiN MIPI CSI negative differential data line
I
(i=0~3) transceiver output
MIPI CSI positive differential data line
MIPI_CSI_RX0_DiP (i=0~3) I
transceiver output
MIPI_CSI0
MIPI CSI positive differential clock line
MIPI_CSI_RX0_CLKP I
transceiver output
MIPI CSI negative differential clock line
MIPI_CSI_RX0_CLKN I
transceiver output

Interface Pin Name Direction Description

MIPI_CSI_RX1_DiN MIPI CSI negative differential data line
I
(i=0~3) transceiver output
MIPI CSI positive differential data line
MIPI_CSI_RX1_DiP (i=0~3) I
transceiver output
MIPI_CSI1
MIPI CSI positive differential clock line
MIPI_CSI_RX1_CLKP I
transceiver output
MIPI CSI negative differential clock line
MIPI_CSI_RX1_CLKN I
transceiver output

Interface Pin Name Direction Description

LVDS negative differential data line
LVDS0_RXiN (i=0~3) I
transceiver output
LVDS positive differential data line
LVDS0_RXiP(i=0~3) I
transceiver output
LVDS0
LVDS positive differential clock line
LVDS0_RXCLKP I
transceiver output
LVDS negative differential clock line
LVDS0_RXCLKN I
transceiver output

Interface Pin Name Direction Description

LVDS negative differential data line
LVDS1_RXiN (i=0~3) I
transceiver output
LVDS positive differential data line
LVDS1_RXiP(i=0~3) I
transceiver output
LVDS1
LVDS positive differential clock line
LVDS1_RXCLKP I
transceiver output
LVDS negative differential clock line
LVDS1_RXCLKN I
transceiver output

Interface Pin Name Direction Description

CAN_RXD I CAN receive data
CAN
CAN_TXD O CAN transmit data

Interface Pin Name Direction Description

AUDPWM_L O Audio PWM left channel data
Audio PWM
AUDPWM_R O Audio PWM right channel data

Interface Pin Name Direction Description

ACODEC_DAC_CLK O CODEC DAC clock output signal
ACODEC_ADC_CLK O CODEC ADC clock output signal
ACODEC_DAC_SYNC O CODEC DAC synchronous signal
Digital
Audio ACODEC_ADC_SYNC O CODEC ADC synchronous signal
CODEC
ACODEC_DAC_DATAR O CODEC DAC right channel data
ACODEC_DAC_DATAL O CODEC DAC left channel data
ACODEC_ADC_DATA I CODEC ADC data

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RV1126 Datasheet Rev 1.2
Interface Pin Name Direction Description
Audio DSM negative differential left channel
O
AUDDSM_LN data
Audio DSM positive differential left channel
O
AUDDSM_LP data
Audio DSM
Audio DSM negative differential right
O
AUDDSM_RN channel data
Audio DSM positive differential right
O
AUDDSM_RP channel data

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RV1126 Datasheet Rev 1.2

Chapter 3 Electrical Specification

3.1 Absolute Ratings
The below table provides the absolute ratings.
Absolute maximum ratings specify the values beyond which the device may be damaged
permanently. Long-term exposure to absolute maximum ratings conditions may affect
device reliability.
Table 3-1 Absolute ratings
Parameters Related Power Group Min Max Unit
Supply voltage for CPU ARM_VDD 0 1.045 V
Supply voltage for NPU NPU_VDD 0 1.045 V
Supply voltage for VEPU VEPU_VDD 0 1.045 V
Supply voltage for Logic LOGIC_VDD 0 0.98 V
Supply voltage for PMU PMUIO_VDD_0V8 0 0.98 V
PLL_AVDD_0V8
MIPI_CSI_RX0_AVDD_0V8
0.8V supply voltage MIPI_CSI_RX1_AVDD_0V8 0 0.98 V
MIPI_DSI_TX0_AVDD_0V8
USB_AVDD_0V8
PMUIO_VDD_1V8
VCCIO_VDD_1V8
PLL_AVDD_1V8
MIPI_CSI_RX0_AVDD_1V8
1.8V supply voltage MIPI_CSI_RX1_AVDD_1V8 0 1.98 V
MIPI_DSI_TX0_AVDD_1V8
USB_AVDD_1V8
VCCIOi_VDD(i=1~7, 1.8V mode)
PMUIOi_VDD(i=1~7, 1.8V mode)
USB_AVDD_3V3
3.3V supply voltage VCCIOi_VDD(i=1~7, 3.3V mode) 0 3.63 V
PMUIOi_VDD(i=1~7, 3.3V mode)
Supply voltage for DDR IO DDR_VDD 0 TBD V
Storage Temperature Tstg -40 125 ℃
Max Conjunction Temperature Tj NA 125 ℃

3.2 Recommended Operating Condition

Following table describes the recommended operating condition.
Table 3-2 Recommended operating condition
Parameters Symbol Min Typ Max Unit
Voltage for CPU ARM_VDD 0.72 0.80 0.945 V
Voltage for NPU NPU_VDD 0.72 0.80 0.945 V
Voltage for VEPU VEPU_VDD 0.72 0.80 0.945 V
Voltage for Logic LOGIC_VDD 0.72 0.80 0.88 V
Voltage for PMU PMUIO_VDD_0V8 0.72 0.80 0.88 V
PMUIO_VDD_1V8
Digital GPIO Power (1.8V) 1.62 1.80 1.98 V
VCCIO_VDD_1V8
PMUIO0_VDD, PMUIO1_VDD,
VCCIO1, VCCIO2, 3.135 3.30 3.465
Digital GPIO Power (3.3V/1.8V) V
VCCIO3, VCCIO4, VCCIO5, 1.62 1.80 1.98
VCCIO6, VCCIO7, PMUIO2
PLL Analog Power (0.8V) PLL_AVDD_0V8 0.72 0.80 0.88 V

PLL Analog Power (1.8V) PLL_AVDD_1V8 1.62 1.80 1.98 V

SARADC/OTG Analog Power ADC_AVDD_1V8 1.62 1.80 1.98 V

USB 2.0 OTG/Host Analog
USB_AVDD_0V8 0.72 0.80 0.88 V
Power (0.8V)
USB 2.0 OTG/Host Analog
USB_AVDD_1V8 1.62 1.80 1.98 V
Power (1.8V)
USB 2.0 OTG/Host Analog
USB_AVDD_3V3 2.97 3.30 3.63 V
Power (3.3V)

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RV1126 Datasheet Rev 1.2
Parameters Symbol Min Typ Max Unit

MIPI_CSI_RX0_AVDD_0V8
DPHY Power (0.8V) MIPI_CSI_RX1_AVDD_0V8 0.72 0.80 0.88 V
MIPI_DSI_TX0_AVDD_0V8

MIPI_CSI_RX0_AVDD_1V8
DPHY Analog Power (1.8V) MIPI_CSI_RX1_AVDD_1V8 1.62 1.80 1.98 V
MIPI_DSI_TX0_AVDD_1V8
OSC input clock frequency NA 24 NA MHz
Max CPU frequency of A7 NA NA TBD GHz
Ambient Operating Temperature TA TBD 25 TBD ℃
Notes:① Symbol name is same as the pin name in the io descriptions

3.3 DC Characteristics
Table 3-3 DC Characteristics
Parameters Symbol Min Typ Max Unit
Input Low Voltage Vil -0.3 NA 0.8 V
Input High Voltage Vih 2 NA VDD33+0.3 V
Digital GPIO Output Low Voltage Vol NA NA 0.2*VDD33 V
@3.3V Output High Voltage Voh 0.8*VDDD33 NA NA V
Pullup Resistor Rpu 23 31 40 Kohm
Pulldown Resistor Rpd 22 29 36 Kohm
Input Low Voltage Vil -0.3 NA VDD33*0.35 V
Input High Voltage Vih 0.65*VDD33 NA VDD33 + 0.3 V
Digital GPIO Output Low Voltage Vol NA NA VDD33*0.2 V
@1.8V Output High Voltage Voh VDD33*0.8 NA NA V
Pull-up Resistor Rpu 21 28 35 Kohm
Pull-down Resistor Rpd 22 29 36 Kohm

3.4 Electrical Characteristics for General IO

Table 3-4 Electrical Characteristics for Digital General IO
Parameters Symbol Test condition Min Typ Max Unit
+/-
Input leakage current Ii Vin = 3.3V or 0V NA NA uA
10
Tri-state output leakage +/-
Ioz Vout = 3.3V or 0V NA NA uA
current 10
Vin = 3.3V, pull down
Digital GPIO NA NA TBD uA
disabled
@3.3V High level input current Iih
Vin = 3.3V, pull down
NA NA TBD uA
enabled
Vin = 0V, pull up disabled NA NA TBD uA
Low level input current Iil
Vin = 0V, pull up enabled NA NA TBD uA
+/-
Input leakage current Ii Vin = 1.8V or 0V NA NA uA
10
Tri-state output leakage +/-
Ioz Vout = 1.8V or 0V NA NA uA
current 10
Vin = 1.8V, pull down
Digital GPIO NA NA TBD uA
disabled
@1.8V High level input current Iih
Vin = 1.8V, pull down
NA NA TBD uA
enabled
Vin = 0V, pull up disabled NA NA TBD uA
Low level input current Iil
Vin = 0V, pull up enabled NA NA TBD uA

3.5 Electrical Characteristics for PLL

Table 3-5 Electrical Characteristics for PLL

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RV1126 Datasheet Rev 1.2
Parameters Symbol Test condition Min Typ Max Unit
Input clock
Fin Fin = FREF @1.8V/0.8V 5 NA 1200 MHz
frequency(Int)
Input clock
Fin Fin = FREF @1.8V/0.8V 10 NA 1200 MHz
frequency(Frac)
VCO operating Fvco = Fref * FBDIV
Fvco 1600 NA 6400 MHz
range @1.8V/0.8V
Output clock Fout = Fvco/POSTDIV
Fout 8 NA 3200 MHz
frequency @1.8V/0.8V
Input
Lock FREF=24M,REFDIV=1
Tlt NA 125 250 clock
time(frequency) @1.8V/0.8V
cycles
Fvco = 3.2GHz,
VDDHV current FBDIV<256
NA 2.0 2.4 mA
consumption Current scale as
(Fvco/3.2GHz)1.5
Fvco = 3.2GHz,
VDDHV current FBDIV>255
NA 2.5 3 mA
PLL consumption Current scale as
(Fvco/3.2GHz)1.5
VDDREF Current
VDD =0.8V NA 0.14 0.50 uA/MHz
consumption
VDDPOST Current
VDD =0.8V NA 0.38 0.70 uA/MHz
consumption
VDDHV Power TYP=TT/25C/0.80V/1.80
consumption V
NA 0.03 1 uA
(power-down MAX=FFG/85C/0.80V/1.
mode) 80V
VDDREF Power TYP=TT/25C/0.80V/1.80
consumption V
NA 10 100 uA
(power-down MAX=FFG/85C/0.80V/1.
mode) 80V
VDDPOST Power TYP=TT/25C/0.80V/1.80
consumption V
NA 4 160 uA
(power-down MAX=FFG/85C/0.80V/1.
mode) 80V
Notes:
① REFDIV is the input divider value;
② FBDIV is the feedback divider value;
③ POSTDIV is the output divider value.

3.6 Electrical Characteristics for USB 2.0 Interface

Table 3-6 Electrical Characteristics for USB 2.0 Interface
Parameters Symbol Test condition Min Typ Max Unit
Transmitter
Classic mode (Vout = 0 or
40 45 50 ohms
Output resistance ROUT 3.3V)
HS mode (Vout = 0 to 800mV) 40 45 50 ohms
Output Capacitance COUT seen from D+ or D- NA 2.0 NA pF
Classic (LS/FS) mode 1.3 1.65 2.0 V
Output Common Mode Voltage VM
HS mode 0.1 0.2 0.3 V
Classic (LS/FS); Io=0mA 2.97 3.3 3.63 V
Differential output signal high VOH Classic (LS/FS); Io=6mA 2.67 3.0 3.40 V
HS mode; Io=0mA 360 400 440 mV
Classic (LS/FS); Io=0mA NA NA 0.1 V
Differential output signal low VOL Classic (LS/FS); Io=6mA 0.24 0.27 0.30 V
HS mode; Io=0mA NA NA 10 mV
Receiver
High input level VIH 2.90 NA 3.63 V
Low input level VIL NA NA 0.1 V
Classic mode 200 NA NA mV
Receiver sensitivity RSENS
HS mode 50 NA NA mV

Receiver common mode RCM Classic mode 0.8 1.65 2.5 V

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RV1126 Datasheet Rev 1.2
Parameters Symbol Test condition Min Typ Max Unit
HS mode (differential and
0 NA 0.3 V
squelch comparator)
HS mode (disconnect
0 NA 0.5 V
comparator)
Input capacitance (seen at D+ or D-) NA 2.0 NA pF
Squelch threshold 100 NA 150 mV
Disconnect threshold 525 NA 625 mV
High output level VOH V
Low output level VOL V

3.7 Electrical Characteristics for DDR IO

Table 3-7 Electrical Characteristics for DDR IO
Parameters Symbol Test condition Min Typ Max Unit
DDR IO Input leakage current,
@ 1.5V , 125℃ uA
@DDR3 mode SSTL mode, unterminated
DDR IO
Input leakage current @ 1.35V , 125℃ nA
@DDR3L mode
DDR IO
Input leakage current @ 1.2V , 125℃ nA
@LPDDR3 mode
DDR IO
Input leakage current @ 1.2V , 125℃ uA
@DDR4 mode
DDR IO
Input leakage current @ 1.1V , 125℃ uA
@LPDDR4 mode

3.8 Electrical Characteristics for TSADC

Table 3-8 Electrical Characteristics for TSADC
Parameters Symbol Test condition Min Typ Max Unit

Temperature Resolution NA +/-5 NA ℃

Temperature Range -40 125 ℃

Analog power ICCA AVDD18 NA 180 NA uA

Digital power ICCD DVDD@VTDC mode NA 3 NA uA

Clock Frequency Fclk Fclk 2 4 6 MHz

Power Down Current from Analog IOFFA AVDD18 Power down NA 3 NA uA

Power Down Current from Digital IOFFD DVDD power down NA 5 NA uA

3.9 Electrical Characteristics for SARADC

Table 3-9 Electrical Characteristics for SARADC
Parameters Symbol Test condition Min Typ Max Units

Resolution NA 10 NA bits

Effective Number of Bit ENOB NA TBD NA bits

Differential Nonlinearity DNL NA +/-1 NA LSB

Integral Nonlinearity INL -2 NA +2 LSB

Input Voltage Range VIN 0 NA 1.8 AVDD

Input Capacitance CIN NA 6 NA pF

Sampling Rate fs NA NA 1 Msps

Analog power IAVDD Fs= 1Msps NA TBD NA uA

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RV1126 Datasheet Rev 1.2
Parameters Symbol Test condition Min Typ Max Units

Digital power IVDD Fs= 1Msps NA TBD NA uA

Power Down Current from Analog IAVDD Power down NA TBD NA uA

Power Down Current from Digital IVDD Power down NA TBD NA uA

3.10 Electrical Characteristics for MIPI DPHY TX

Table 3-10 Electrical Characteristics for MIPI DPHY TX
Parameters Symbol Test condition Min Typ Max Units

HS TX static common-mode Vcmtx 150 200 250 mV

Vcmtx mismatch when output is

ΔVcmtx(1,0) NA NA 5 mV
Differential-1 or Differential-0

HS Transmit differential voltage Vod 140 200 270 mV

Vod mismatch when output is

ΔVod NA NA 14 mV
Differential-1 or Differential-0

HS output high voltage Vohhs NA NA 360 mV

Single ended output impedance Zos 40 50 62.5 Ohm

Single ended output impedance

ΔZos NA NA 10 %
mismacth

The venin output high level Voh 1.08 1.2 1.32 V

The venin output low level Vol -50 NA 50 mV

Output impedance of LP Zolp 110 NA NA Ω

3.11 Electrical Characteristics for MIPI DPHY RX

Table 3-11 Electrical Characteristics for MIPI DPHY RX(for MIPI mode)
Parameters Symbol Test condition Min Typ Max Units
Common-mode voltage HS receive
Vcmrx(dc) 70 300 mV
mode

<=1.5Gbps 70 mV
Differential input high threshold Vidth
>1.5Gbps 40 mV

<=1.5Gbps -70 NA NA mV
Differential input low threshold Vidtl
>1.5Gbps -40

Single-ended input high voltage Vihhs NA NA 460 mV

Single-ended input low voltage Vilhs -40 NA NA mV

Single-ended threshold for HS

Vterm-en NA NA 450 mV
termination enable

Differential input impedance Zid 80 100 125 Ω

Thevenin output high level Voh 1.08 1.2 1.32 V

Thevenin output low level Vol -50 50 mV

Though no maximum
value for Zolp is
Output impedance of LP transmitter Zolp 110 Ω
specified, the LP
transmitter output

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RV1126 Datasheet Rev 1.2
Parameters Symbol Test condition Min Typ Max Units
impedance shall ensure
that the TRLP/TFLP
specification is met

<=1.5Gbps 880 NA NA mV
Logic 1 input voltage Vih
>1.5Gbps 740 NA NA mV

Logic 0 input voltage, not in ULP

Vil NA NA 550 mV
state

Logic 0 input voltage, ULP state Vil-ulps NA NA 300 mV

Input hysteresis Vhyst 25 NA NA mV

Table 3-12 Electrical Characteristics for MIPI DPHY RX(for LVDS mode)
Parameters Symbol Test condition Min Typ Max Units
Common-mode voltage HS receive
Vcmrx(dc) 0.9 NA 1.32 V
mode

Differential input high threshold Vidth <=1.5Gbps NA NA 70 mV

Differential input low threshold Vidtl <=1.5Gbps -70 NA NA mV

Single-ended input high voltage Vihhs NA NA 1.5 V

Single-ended input low voltage Vilhs -40 NA NA mV

Differential input impedance Zid 80 100 125 Ω

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RV1126 Datasheet Rev 1.2

Chapter 4 Thermal Management

4.1 Overview
For reliability and operability concerns, the absolute maximum junction temperature has to
be below 125℃.
4.2 Package Thermal Characteristics
Table 4-1 provides the thermal resistance characteristics for the package used on the SoC.
The resulting simulation data for reference only, please prevail in kind test.
Table 4-1 Thermal Resistance Characteristics
Parameter Symbol Typical Unit
Junction-to-ambient thermal resistance 𝜽𝑱𝑨 33.3 (℃/𝑾)
Junction-to-board thermal resistance 𝜽𝑱𝑩 7.3 (℃/𝑾)
Junction-to-case thermal resistance 𝜽𝑱𝑪 3.7 (℃/𝑾)

Note: The testing PCB is 4 layers, 45mmx45mm, 1mm thickness, Ambient temperature is 25℃.

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