** Information Specification ** INF-8438i Rev 1.

SFF Committee documentation may be purchased in hard copy or electronic form

SFF specifications are available at ftp://ftp.seagate.com/sff

_________________________________________________________________

SFF-8436 QSFP+ was developed to update this specification

_________________________________________________________________

SFF Committee

INF-8438i Specification for

QSFP (Quad Small Formfactor Pluggable) Transceiver

Rev 1.0 November 2006

Secretariat: SFF Committee

Abstract: This specification describes the QSFP (Quad Small Formfactor Pluggable)
Transceivers developed by the MSA (Multiple Source Agreement) group. The following
companies participated in the MSA:
Avago Technologies Molex
Beam Express Opnext
Emcore Fiber Optics Optical Communication Products
Emulex Picolight
Fiberxon QLogic
Finisar Reflex Photonics
Force10 Networks The Siemon Company
Helix AG Tyco Electronics
JDS Uniphase Xloom Communications
McDATA Zarlink Semiconductor
Merge Optics
This Information Specification was not developed or endorsed by the SFF Committee
but was submitted for distribution on the basis that it is of interest to the
storage industry.
The copyright on the contents remains with the contributor.
Contributors are not required to abide by the SFF patent policy. Readers are
advised of the possibility that there may be patent issues associated with an
implementation which relies upon the contents of an 'i' specification.
SFF accepts no responsibility for the validity of the contents.
POINTS OF CONTACT:

Scott Kipp I. Dal Allan

Technical Editor Chairman SFF Committee
McDATA 14426 Black Walnut Court
4 McDATA Parkway Saratoga
Broomfield CO 80021 CA 95070
720-558-3452 408-867-6630
[email protected] [email protected]

QSFP (Quad Small Formfactor Pluggable) Transceiver

** Information Specification ** INF-8438i Rev 1.0

EXPRESSION OF SUPPORT BY MANUFACTURERS

The following member companies of the SFF Committee voted in favor of this
industry specification.

AMCC
Amphenol
Avago
Emulex
FCI
Fujitsu CPA
Hewlett Packard
Hitachi GST
JDS Uniphase
Molex
Picolight
Samsung
Sun Microsystems
Tyco
Vitesse Semiconductor

The following member companies of the SFF Committee voted to abstain on this
industry specification.

Clariphy
Comax
Cortina Systems
Foxconn
Seagate

QSFP (Quad Small Formfactor Pluggable) Transceiver

** Information Specification ** INF-8438i Rev 1.0

SFF COMMITTEE

The SFF Committee is an industry group. The membership of the committee since its
formation in August 1990 has included a mix of companies which are leaders across
the industry.

When 2 1/2" diameter disk drives were introduced, there was no commonality on
external dimensions e.g. physical size, mounting locations, connector type,
connector location, between vendors.

The first use of these disk drives was in specific applications such as laptop
portable computers and system integrators worked individually with vendors to
develop the packaging. The result was wide diversity, and incompatibility.

The problems faced by integrators, device suppliers, and component suppliers led
to the formation of the SFF Committee as an industry ad hoc group to address the
marketing and engineering considerations of the emerging new technology.

During the development of the form factor definitions, other activities were
suggested because participants in the SFF Committee faced more problems than the
physical form factors of disk drives. In November 1992, the charter was expanded
to address any issues of general interest and concern to the storage industry.
The SFF Committee became a forum for resolving industry issues that are either
not addressed by the standards process or need an immediate solution.

Those companies which have agreed to support a specification are identified in

the first pages of each SFF Specification. Industry consensus is not an essential
requirement to publish an SFF Specification because it is recognized that in an
emerging product area, there is room for more than one approach. By making the
documentation on competing proposals available, an integrator can examine the
alternatives available and select the product that is felt to be most suitable.

SFF Committee meetings are held during T10 weeks (see www.t10.org), and Specific
Subject Working Groups are held at the convenience of the participants. Material
presented at SFF Committee meetings becomes public domain, and there are no
restrictions on the open mailing of material presented at committee meetings.

Most of the specifications developed by the SFF Committee have either been
incorporated into standards or adopted as standards by EIA (Electronic Industries
Association), ANSI (American National Standards Institute) and IEC (International
Electrotechnical Commission).

Suggestions for improvement of this specification will be welcome. They should be

sent to the SFF Committee, 14426 Black Walnut Ct, Saratoga, CA 95070.

QSFP (Quad Small Formfactor Pluggable) Transceiver

** Information Specification ** INF-8438i Rev 1.0

The complete list of SFF Specifications which have been completed or are
currently being worked on by the SFF Committee can be found at:

ftp://ftp.seagate.com/sff/SFF-8000.TXT

If you wish to know more about the SFF Committee, the principles which guide the
activities can be found at:

ftp://ftp.seagate.com/sff/SFF-8032.TXT

If you are interested in participating or wish to follow the activities of the

SFF Committee, the signup for membership and/or documentation can be found at:

www.sffcommittee.com/ie/join.html

or, the following application can be submitted.

Name: ____________________________ Title: __________________________

Company: ______________________________________________________________

Address: ______________________________________________________________

______________________________________________________________

Phone: ____________________________ Fax: ____________________________

Email: ______________________________________________________________

Please register me with the SFF Committee for one year.

___ Voting Membership w/Electronic documentation $ 2,160

___ Voting Membership w/Meeting documentation $ 1,800

___ Non-voting Observer w/Electronic documentation $ 660 U.S.

$ 760 Overseas

___ Non-voting Observer w/Meeting documentation $ 300 U.S.

$ 400 Overseas

Check Payable to SFF Committee for $_________ is Enclosed

Please invoice me for $_________ on PO #: ___________________

MC/Visa/AmX______________________________________ Expires_________

SFF Committee 408-867-6630

14426 Black Walnut Ct
Saratoga CA 95070 [email protected]

QSFP (Quad Small Formfactor Pluggable) Transceiver

Quad Small Form-factor Pluggable (QSFP)
Transceiver Specification
Revision 1.0

QSFP Chair and Editor QSFP Secretary

Scott Kipp Alex Ngi
McDATA Corporation Helix AG
4 McDATA Parkway Seefeldstrasse 45
Broomfield, CO 80021 CH-8008 Zurich
Voice: 720-558-3452 Switzerland
Fax: 720-558-8999 Voice: (41) 44-260-2434
[email protected] Fax: (41) 44-260-2433
[email protected]

This is the final released draft of this specification.

QSFP Public Specification 1

 Legal Disclaimer

The promoters of the QSFP specification revision 0.96 (“QSFP MSA GROUP”), and
many contributors, collaborated to develop a specification for a Multi-channel small foot
print pluggable module. The promoters stated a wish to encourage broad and rapid
industry adoption of the specification.
This version is the result of such collaboration. In the future the QSFP specification may
be offered to more formal standards bodies to further support the adoption of the
specification.
THIS SPECIFICATION IS PROVIDED “AS IS” WITH NO WARRANTIES
WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY,
NONINFRINGEMENT, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY
WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION OR
SAMPLE. THE QSFP PROMOTERS DISCLAIM ALL LIABILITY, INCLUDING LIABILITY
FOR INFRINGEMENT OF ANY PROPRIETARY RIGHTS, RELATING TO USE OF
INFORMATION IN THIS SPECIFICATION. IN NO EVENT SHALL THE QSFP
PROMOTERS, CONTRIBUTORS OR ADOPTERS BE LIABLE FOR ANY DIRECT,
INDIRECT, SPECIAL, EXEMPLARY, PUNITIVE, OR CONSEQUENTIAL DAMAGES,
INCLUDING, WITHOUT LIMITATION, LOST PROFITS, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGES.
This specification may contain, and sometimes even require the use of intellectual
property owned by others. No license, express or implied, by estoppel or otherwise, to
any intellectual property rights is granted herein, except that a license is hereby granted
to copy and reproduce this specification for internal use only.

QSFP Public Specification 2

Revision History

REVISION RELEASE DATE CHANGE

0.1 October 25, 2004 First Draft
0.2 November 25, 2004 Second Draft
0.3 December 9, 2004 Third Draft
0.4 February 24, 2005 Fourth Draft
0.5 March 5, 2005 fifth Draft
0.6 June 20, 2005 Mechanical Clause
0.61 June 27, 2005 Electrical and Mechanical Clauses
0.62 August 4, 2005 Electrical, mechanical Clauses, Layout
0.63 September 27, 2005 Electrical specification improvements
Electrical specification improvements, changed
0.64 February 2, 2006
cage specification, finished memory map
Reorganization of mechanical clauses to specify
0.70 March 1, 2006
module only. Completed Memory Map.
Changes made due to letter ballot review. All
changes are documented in the comment data-
base and major changes were regarding
0.75 May 17, 2006
LPMode_Reset pin, Packet Error Checking,
removed Appendix A and filled in missing
details.
Mechanical changes made due to letter ballot
0.80 June 28, 2006
review. Changes due to review of Draft 0.75.
Mechanical changes made due to letter ballot
review of Revision 0.8. Management Section
0.85 July 18, 2006
reorganized in page, byte order and Rate Select
explanation improved.
Minor changes made due to letter ballot review
of Revision 0.85. Rate Select explanation
0.90 July 25, 2006
improved and length of module outside of cage
extended by 5 mm.
0.95 August 1, 2006 Editorial changes to make this a public draft.
Changes due to public review. LPMode_Reset
pin was converted to ResetL and LPMode pins.
0.96 November 15, 2006
Mechanical clarifications to connector, module
and cage.
Minor editorial changes due to review of Draft
1.0 December 1, 2006
0.96.

QSFP Public Specification 3

Table of Contents Page

1 Contact Information for Member Companies..............................................................................................................9

1.1 Acknowledgement of Contributors..................................................................................................................10

2 Scope..........................................................................................................................................................................11

3 Electrical Specification........... ...................................................................................................................................14

3.1 Electrical Connector......... ...............................................................................................................................14
3.1.1 Low Speed Electrical Hardware Pins.......... ..........................................................................................17
3.1.2 Low Speed Electrical Specification.......................................................................................................18
3.1.3 High Speed Electrical Specification.......... ............................................................................................19
3.2 Power Requirements......... ...............................................................................................................................19
3.2.1 Host Board Power Supply Filtering.......... ............................................................................................20
3.3 ESD..................................................................................................................................................................21

4 Mechanical and Board Definition..............................................................................................................................22

4.1 Introduction......................................................................................................................................................22
4.2 QSFP Datums and Component Alignment......................................................................................................23
4.3 QSFP Transceiver Mechanical Package Dimensions......................................................................................24
4.3.1 Mating of QSFP Transceiver PCB to QSFP Electrical Connector........................................................27
4.4 Host PCB Layout.............................................................................................................................................28
4.4.1 Insertion, Extraction and Retention Forces for QSFP Transceivers......................................................29
4.5 Color Coding and Labeling of QSFP Transceivers......... ................................................................................30
4.6 Bezel for Systems Using QSFP Transceivers..................................................................................................31
4.7 QSFP Electrical Connector Mechanical......... .................................................................................................32
4.8 Individual QSFP Cage Assembly......... ...........................................................................................................33
4.8.1 QSFP Heat Sink Clip Dimensions.........................................................................................................35
4.8.2 QSFP Heat Sink Dimensions.................................................................................................................36
4.8.3 Light Pipes.............................................................................................................................................37
4.9 Dust / EMI Cover............................................................................................................................................37
4.10 Optical Interface......... ...................................................................................................................................37

5 Environmental and Thermal........... ...........................................................................................................................39

5.1 Thermal Requirements.....................................................................................................................................39

6 Management Interface........... ....................................................................................................................................40

6.1 Introduction......................................................................................................................................................40
6.2 Timing Specification......... ..............................................................................................................................40
6.2.1 Introduction.......... .................................................................................................................................40
6.2.2 Management Interface Timing Specification.......... ..............................................................................40
6.2.3 Serial Interface Protocol.......... ..............................................................................................................40
6.3 Memory Interaction Specifications..................................................................................................................42
6.3.1 Timing for Soft Control and Status Functions.......... ............................................................................43
6.4 Device Addressing and Operation......... ..........................................................................................................44
6.5 Read/Write Functionality.................................................................................................................................45
6.5.1 QSFP Memory Address Counter (Read AND Write Operations).........................................................45
6.5.2 Read Operations (Current Address Read).......... ...................................................................................46
6.5.3 Read Operations (Random Read).......... ................................................................................................46
6.5.4 Write Operations (BYTE Write).......... .................................................................................................47

QSFP Public Specification 4

 6.5.5 Write Operations (Sequential Write).....................................................................................................48
6.5.6 Write Operations (Acknowledge Polling).......... ...................................................................................48
6.6 QSFP Memory Map.........................................................................................................................................48
6.6.1 Lower Memory Map..............................................................................................................................50
6.6.2 Upper Memory Map Page 00h.......... ....................................................................................................59
6.6.3 Upper Memory Map Page 01h.......... ....................................................................................................68
6.6.4 User Writable and Vendor Specific Memory.......... ..............................................................................68
6.6.5 Upper Memory Page 03h.......................................................................................................................69

QSFP Public Specification 5

List of Figures Page

1. Application Reference Model ..................................................................................................................................13

2. QSFP Transceiver Pad Layout .................................................................................................................................14
3. Example QSFP Host Board Schematic ....................................................................................................................16
4. Recommended Host Board Power Supply Filtering ................................................................................................20
5. QSFP Module Rendering .........................................................................................................................................22
6. QSFP Datum Alignment, Depth ..............................................................................................................................24
7. Drawing of QSFP Transceiver (Part 1 of 2) ............................................................................................................25
8. Drawing of QSFP Transceiver (Part 2 of 2) ............................................................................................................26
9. Pattern Layout for QSFP Printed Circuit Board ......................................................................................................27
10. QSFP Host PCB Mechanical Layout .....................................................................................................................28
11.QSFP Host PCB Mechanical Layout, Detail Z .......................................................................................................29
12. Recommended Bezel Design .................................................................................................................................31
13. QSFP Transceiver Electrical Connector Illustration ..............................................................................................32
14. QSFP Electrical Connector Specification ..............................................................................................................32
15. Cage and Optional Heat Sink Design (exploded view) .........................................................................................33
16. 1-by-1 cage .............................................................................................................................................................34
17. QSFP Heat Sink Clip .............................................................................................................................................35
18. QSFP Heat Sink ....................................................................................................................................................36
19. Dust / EMI Cover ...................................................................................................................................................37
20. QSFP Optical Receptacle and Channel Orientation ..............................................................................................38
21. QSFP Timing Diagram ..........................................................................................................................................40
22. QSFP Device Address ............................................................................................................................................45
23. QSFP Current Address Read Operation ................................................................................................................46
24. QSFP Random Read ..............................................................................................................................................46
25. Sequential Address Read Starting at QSFP Current Address ................................................................................47
26. Sequential Address Read Starting with Random QSFP Read ...............................................................................47
27. QSFP Write Byte Operation ..................................................................................................................................47
28. QSFP Sequential Write Operation .........................................................................................................................48
29. QSFP Memory Map ...............................................................................................................................................49

QSFP Public Specification 6

List of Tables Page

1. Multimode Fiber Applications............................................................................................................................12

2. Singlemode Fiber Applications ..........................................................................................................................12
3. Pin Function Definition ......................................................................................................................................15
4. Power Mode Truth Table ....................................................................................................................................19
5. Low Speed Control and Sense Signals ...............................................................................................................19
6. Power Supply Specification................................................................................................................................21
7. Power Budget Classification...............................................................................................................................22
8. Definition of Datums ..........................................................................................................................................24
9. Insertion, Extraction and Retention Forces.........................................................................................................30
10. Temperature Classification of Module Case ......................................................................................................39
11. QSFP 2-Wire Timing Specifications ..................................................................................................................41
12. QSFP Memory Specification ..............................................................................................................................42
13. Single Byte Writable Memory Block .................................................................................................................42
14. Multiple Byte Writable Memory Block..............................................................................................................42
15. I/O Timing for Soft Control and Status Functions .............................................................................................43
16. I/O Timing for Squelch and Disable...................................................................................................................44
17. Lower Memory Map Page A0h ..........................................................................................................................50
18. Status Indicators..................................................................................................................................................50
19. Channel Status Interrupt Flags............................................................................................................................51
20. Module Monitor Interrupt Flags .........................................................................................................................51
21. Channel Monitor Interrupt Flags ........................................................................................................................52
22. Module Monitoring Values.................................................................................................................................53
23. Channel Monitoring Values................................................................................................................................54
24. Control Bytes ......................................................................................................................................................55
25. IntL Masking Bits for Module and Channel Status Interrupts............................................................................56
26. Functionality of RxN_Rate_Select with Extended Rate Selection.....................................................................57
27. Definition of Application Select (Bytes 89 to 92) ..............................................................................................57
28. Detailed Description of Control Mode (Bytes 89 to 92, bit 7 and 6)) ................................................................58
29. Serial ID: Data Fields .........................................................................................................................................59
30. Identifier Values .................................................................................................................................................60
31. Extended Identifier Values .................................................................................................................................60
32. Connector Values................................................................................................................................................61
33. Transceiver Values .............................................................................................................................................62
34. Encoding Values .................................................................................................................................................63
35. Extended RateSelect Compliance Tag Assignment............................................................................................63
36. Description of Device Technology .....................................................................................................................64
37. Transmitter Technology......................................................................................................................................64
38. Extended Transceiver Code Values ....................................................................................................................65
39. Option Values .....................................................................................................................................................66
40. Date Codes ..........................................................................................................................................................67
41. Diagnostic Monitoring Type...............................................................................................................................67

QSFP Public Specification 7

42. Enhanced Options (byte 221)) ............................................................................................................................67
43. Application Select Table (Page 01) ....................................................................................................................68
44. Application Code Structure ................................................................................................................................68
45. Upper Memory Map Page 03h............................................................................................................................69
46. Module and Channel Thresholds ........................................................................................................................69
47. Optional Channel Controls .................................................................................................................................70
48. Channel Monitor Masks......................................................................................................................................71

QSFP Public Specification 8

1 Contact Information for Member Companies

Company Representative Contact Information

Avago Technologies Jugnu Ojha [email protected]
350 West Trimble Road MS Tel: 408-435-4270
90TH
San Jose, CA 95131
Beam Express
910 E California Street
Sunnyvale, CA 94085
Emcore Fiber Optics Kenneth P. [email protected]
5314 Connemara Drive NE Jackson Tel: 505-349-0922
Rochester, MN 55906
Emulex Corp. Hossein [email protected]
Hashemi
Fiberxon Helena Feng [email protected]
Finisar Stephen Nelson [email protected]
Force10 Networks, Inc. Michael Laudon [email protected]
1440 McCarthy Blvd
San Jose, CA 95035
Helix AG Alex Ngi [email protected]
Seefeldstrasse 45 Tel: 41-44-260-24-34
Zurich, Switzerland CH-8008 Fax: 41-44-260-24-33
JDS Uniphase Corp David Lewis [email protected]
Tel: 408-546-5448
McDATA Corporation Scott Kipp [email protected]
4 McDATA Parkway Tel: 720-558-3452
Broomfield, CO 80021 Fax 720-558-8999
Merge Optics Jens Fiedler [email protected]

Molex Incorporated Jay Neer [email protected]

2222 Wellington Court Tel: 561-447-2907x3889
Lisle, IL 60532 Fax 561-447-2908
Opnext Inc. Josef C. Berger [email protected]
940 Auburn Ct. Tel: 310-301-6710
Fremont, CA 94538 Fax 310-305-1609
Optical Communication Kirk Bovill [email protected]
Products, Inc. Tel: 818 251-7183
Picolight Inc. Mike Dudek [email protected]
1480 Arthur Avenue Tel: 303-530-3189 x7533
Louisville, CO 80027
Qlogic Inc. Mark Owen [email protected]
6321 Bury Drive Tel: 952-908-2326
Eden Prairie, MN 55346
Reflex Photonics Tomas Maj [email protected]
550 Sherbrooke West Tel: 514-842-5179
Suite 680, West Tower Fax: 514-842-8142
Montreal, Quebec
Canada H3A 1B9

QSFP Public Specification 9

 Company Representative Contact Information
The Siemon Company Olindo Savi [email protected]
101 Siemon Co. Drive Tel: 860-945-4246
Watertown, CT 06795 Fax: 860-945-5871
Tyco Electronics Ed Bright [email protected]
3101 Fulling Mill Road M/S: Tel: 717-592-6041
128-083 Fax: 717-986-3410
Middletown, PA 17057
Xloom Communications Inc. Dubravko [email protected]
11 Derech Hashalom Babic
Tel Aviv, Israel 67892
Zarlink Semiconductor AB Marco Ghisoni [email protected]
Bruttovägen 1, Box 520SE- Tel : 46 (0)8 580 24 500
175 26, Järfälla, Sweden Fax: 46 (0)8 580 20 110

1.1 Acknowledgement of Contributors

The MSA would like to acknowledge the hard work of the major contributors to this standard. The cage and
transceiver design was spearheaded by Ed Bright who has contributed successfully to many transceiver
designs. Jay Neer and KC Simonson contributed the connector design and confirmed many of the cage and
transceiver designs. Phil McClay designed the Memory Map and Kannan Raj proposed the Serial ID clauses
of the draft. Mike Dudek was very active in reviewing all aspects of the design and John Petrilla contributed to
many areas as well - particularly doing thorough reviews of the later drafts. Jerry Malagrino oversaw the
thermal simulations of the modules and cages. Many others contributed to the specification as well.
Jens Fiedler edited and chaired the QSFP for the first seven drafts of the MSA and has been the webmaster
for www.qsfpmsa.org. Alex Ngi contributed as the secretary and wrote the Rate Select sections and
contributed regularly to the memory map.

QSFP Public Specification 10

2 Scope
The scope of this Specification covers the following items:
a) electrical interfaces (including pinout for data, control, status, configuration and test signals) and the
electrical connector and recommended host PCB layout requirements
b) management interfaces encompassing features from the current SFP MSA and includes specific
multi-data rate and multi-protocol implementations
c) optical interfaces (including the optical connector receptacle and mating fiber optic connector plug
and recommended breakout cable assembly.) The optical specifications are left to the applicable
standards for each protocol.
d) mechanical including package outline with latching detail and optical connector receptacle detail,
electrical connector mechanical details for both the transceiver and host PCB halves, front panel
cut-out recommended dimensions and a mis-plugging solution to prevent damage from related XFP
modules and cages
e) thermal requirements (case temperatures)
f) electromagnetic interference (EMI) requirements (including necessary shielding features to seal the
OEM chassis front panel cutout with and without the QSFP module installed in the cage.)
g) electrostatic discharge (ESD) requirements solely to the extent disclosed with particularity in the
Specifications where the sole purpose of such disclosure is to enable products to operate, connect or
communicate as defined within the Specifications.
The overall package dimensions shall conform to the indicated dimensions and tolerances, and the mounting
features shall be located such that the products are mechanically interchangeable with the rail and connector
system. In addition, the overall dimensions and mounting requirements for the rail and connector system on a
circuit board shall be configured such that the products are mechanically and electrically interchangeable, and
the overall dimensions and insertion requirements for the optical connector and corresponding fiber optic
cable plug shall be such that the products are mechanically and optically interchangeable.
The electrical and optical specifications shall be compatible with those enumerated in the ITU-T
Recommendation G.957 (STM-1, STM-4 and STM-16), Telcordia Technologies GR-253-CORE (OC-3, OC-12
and OC-48), Ethernet- IEEE 802.3-2005 (Fast Ethernet and Gigabit Ethernet), InfiniBand Architecture
Specifications (SDR and DDR) or Fibre Channel-PI-2 (1GFC, 2GFC and 4GFC). Electrical and optical
specifications may be compatible with standards under development such as Fibre Channel-PI-3 and Fibre
Channel-PI-4.
The specific implementation and internal design of the module is entirely at the discretion of each Participant
and is not covered by the Specifications. The Participants recognize that their products may not be identical,
but need only meet the criteria shown in the Specifications to assure interoperation and interchangeability.
Each Participant acknowledges the Specifications will provide a common solution for combined four-channel
fiber optic ports that support SONET/SDH and/or Ethernet and/or Fibre Channel specifications. This MSA
encompasses transceiver design(s) capable of supporting multimode and single mode applications for
operation covering the transmission rates and distances noted below. Other standards covering higher data
rates and/or longer distance options are not part of this agreement but may be supported. A QSFP module
may support applications in Table 1 and Table 2 that are supplied for reference only.

QSFP Public Specification 11

 Table 1 — Multimode Fiber Applications

Fiber Type IEEE 802.3 Fibre Channel-FC-PI-2 InfiniBand

Core Diameter/ Fast Gigabit
Distance MHZ*km Ethernet Ethernet 1GFC 2GFC 4GFC SDR DDR
2km MM 62.5/200 x
300m MM 62.5/200 x
275m MM 62.5/200 x
220m MM 62.5/160 x
150m MM 62.5/200 x
75m MM 62.5/200 x
70m MM 62.5/200 x
50m MM 62.5/200 x
550m MM 50/500 x
500m MM 50/400 x
500m MM 50/500 x
300m MM 50/500 x
150m MM 50/500 x
125m MM 50/500 x
75m MM 50/500 x
860m MM 50/2000 x
500m MM 50/2000 x
270m MM 50/2000 x
200m MM 50/2000 x
150m MM 50/2000 x

Table 2 — Singlemode Fiber Applications

Fibre Channel -
IEEE 802.3 FC-PI-2 ITU-T G.957 InfiniBand
Fiber Fast Gigabit
Distance Type Ethernet Ethernet 1GFC 2GFC 4GFC STM1 STM4 STM16 SDR 4x-LX DDR
2km SM x x x
10km SM x x x x x x x x
15km SM x x
40km SM x x

QSFP Public Specification 12

An Application Reference Model, see Figure 1, shows the high-speed data interface between an ASIC
(SerDes) and the QSFP module. Only one data channel of the interface is shown for simplicity.
Figure 1 — Application Reference Model

Host Board
(Only one channel shown for simplicity)

C Rx 1
Rx 2

Host Edge Card Connector

D C'

Module Card Edge (Host

Optical Connector/Port
Rx Out p Rx 3

(Optical Interface)
Rx Rx 4
Rx Out n

Interface)
ASIC (SerDes) QSFP Module
Tx In p
Tx Tx 4
Tx In n
Tx 3
A B' Tx 2
Tx 1
B

QSFP compliance and reference points are as follows:

A: Host ASIC transmitter output at ASIC package pin on a DUT board – Reference point
B: Host ASIC transmitter output across the Host Board and Host Edge Card connector at the Module
Card Edge interface - Reference point
B’: Host ASIC transmitter output across the Host Board at Host Edge Card Connector - Compliance
point
C: QSFP receiver output at the Module Card Edge Interface - Reference point
C’: QSFP receiver output at Host Edge Card Connector - Compliance point
D: QSFP receiver output at Host ASIC package receiver input pin on a DUT board– Reference point

QSFP Public Specification 13

1 3 Electrical Specification
2 This clause contains pin definition data for the QSFP transceiver. The pin definition data is generic for gigabit
3 -per-second datacom applications such as Fibre Channel and Gigabit Ethernet and SONET/ATM applications.
4 Compliance Points for high-speed signal electrical measurements are defined in Figure 1. Compliance Points
5 for all other electrical signals are at comparable points at the host edge card connector.
6
7 3.1 Electrical Connector
8 Figure 2 shows the signal symbols and contact numbering for the QSFP module edge connector. The diagram
9 shows the module PCB edge as a top and bottom view. There are 38 pins intended for high speed, low speed
10 signals, power and ground connections. Table 3 provides more information about each of the 38 pins.
11 For EMI protection the signals to the connector should be shut off when the QSFP transceiver is removed.
12 Standard board layout practices such as connections to Vcc and GND with Vias, use of short and equal-length
13 differential signal lines, use of microstrip-lines and 50 Ohm terminations are recommended. The chassis
ground (case common) of the QSFP module is isolated from the module’s circuit ground, GND, to provide the
14
equipment designer flexibility regarding connections between external electromagnetic interference shields
15 and circuit ground, GND, of the module.
16
Figure 2 — QSFP Transceiver Pad Layout
17
18
19 38 GND
GND 1
37 TX1n
20 36 TX1p
TX2n 2
21 TX2p 3
35 GND
GND 4
22 34 TX3n
TX4n 5
33 TX3p
23 32 GND
TX4p 6
GND 7
Card Edge

24 31 LPMode
ModSelL 8
25 30 Vcc1
ResetL 9
29 VccTx
26 VccRx 10
28 IntL
SCL 11
27 27 ModPrsL
SDA 12
28 26 GND
GND 13
25 RX4p
29 RX3p 14
24 RX4n
RX3n 15
30 23 GND
GND 16
22 RX2p
31 21 RX2n
RX1p 17
32 RX1n 18
20 GND
GND 19
33
34
35 Top Side Bottom Side
36 Viewed from Top Viewed from Bottom
37
38
39
40
41
42
43
44
45
46
47
48
49

QSFP Public Specification 14

1 Table 3 — Pin Function Definition
2 Pin Logic Symbol Description Plug Notes
3 Sequence
4 1 GND Ground 1 1
5 2 CML-I Tx2n Transmitter Inverted Data Input 3
6 3 CML-I Tx2p Transmitter Non-Inverted Data Input 3
7 4 GND Ground 1 1
8 5 CML-I Tx4n Transmitter Inverted Data Input 3
9 6 CML-I Tx4p Transmitter Non-Inverted Data Input 3
10 7 GND Ground 1 1
11 8 LVTTL-I ModSelL Module Select 3
12 9 LVTTL-I ResetL Module Reset 3
13 10 Vcc Rx +3.3 V Power supply receiver 2 2
14 11 LVCMOS-I/O SCL 2-wire serial interface clock 3
15 12 LVCMOS-I/O SDA 2-wire serial interface data 3
16 13 GND Ground 1 1
17 14 CML-O Rx3p Receiver Non-Inverted Data Output 3
18 15 CML-O Rx3n Receiver Inverted Data Output 3
19 16 GND Ground 1 1
20 17 CML-O Rx1p Receiver Non-Inverted Data Output 3
21 18 CML-O Rx1n Receiver Inverted Data Output 3
22 19 GND Ground 1 1
23 20 GND Ground 1 1
24 21 CML-O Rx2n Receiver Inverted Data Output 3
25 22 CML-O Rx2p Receiver Non-Inverted Data Output 3
26 23 GND Ground 1 1
27 24 CML-O Rx4n Receiver Inverted Data Output 3
28 25 CML-O Rx4p Receiver Non-Inverted Data Output 3
29 26 GND Ground 1 1
30 27 LVTTL-O ModPrsL Module Present 3
31 28 LVTTL-O IntL Interrupt 3
32 29 Vcc Tx +3.3 V Power supply transmitter 2 2
33 30 Vcc1 +3.3 V Power Supply 2 2
34 31 LVTTL-I LPMode Low Power Mode 3
35 32 GND Ground 1 1
36 33 CML-I Tx3p Transmitter Non-Inverted Data Input 3
37 34 CML-I Tx3n Transmitter Inverted Data Input 3
38 35 GND Ground 1 1
39 36 CML-I Tx1p Transmitter Non-Inverted Data Input 3
40 37 CML-I Tx1n Transmitter Inverted Data Input 3
41 38 GND Ground 1 1
42 Note 1: GND is the symbol for signal and supply (power) common for the QSFP module. All are
43 common within the QSFP module and all module voltages are referenced to this potential unless
44 otherwise noted. Connect these directly to the host board signal-common ground plane.
45 Note 2: Vcc Rx, Vcc1 and Vcc Tx are the receiver and transmitter power supplies and shall be
46 applied concurrently. Requirements, defined for the host side of the Host Edge Card Connector,
47 are listed in Table 6. Recommended host board power supply filtering is shown in Figure 4. Vcc Rx,
48 Vcc1and Vcc Tx may be internally connected within the QSFP transceiver module in any
combination. The connector pins are each rated for a maximum current of 500 mA.
49

QSFP Public Specification 15

1 Figure 3 shows an example of a complete QSFP host PCB schematic with connections to SerDes and control
2 ICs.
3 Figure 3 — Example QSFP Host Board Schematic
4 Vcc_host
To other QSFP modules

5 =3.3 V

6 4.7k to 10k ohm

7 4.7k to 10k ohm

4.7k to 10k ohm

8
9 ModPrsL Micro
10 SCL Controller
11 4.7k to 10k ohm
SDA

12 PLD/PAL
13 ModSelL

14 ResetL
IntL
15 LPMode
16
Vcc Rx
17
Tx Disable <1:4>

22 uF 0.1 uF
Tx Fault <1:4>

Rx Rate <1:4>
Rx Los <1:4>

18
19
GND
20
21 Quad
22 Tx Data Bus
.01uF TIA
100 ohm Rx1p .01uF &
23 Protocol Rx1n .01uF Limiting
24 IC 100 ohm Rx2p .01uF Amplifier
25 Rx Data Bus Rx2n .01uF

26 100 ohm Rx3p .01uF

Rx3n
27 .01uF

Vcc_host
100 ohm Rx4p .01uF
28 =3.3 V 1uH Rx4n
29 Quad
SERDES
30 1uH IC
0.1 uF 22 uF
31 .01uF

32 Tx4p .01uF 100 ohm

1uH Tx4n
33 Tx3p
.01uF

.01uF 100 ohm

34 Tx3n .01uF

35 Tx2p .01uF 100 ohm

36 Tx2n .01uF

37 Tx1p .01uF 100 ohm

Tx1n
38 Quad
Vcc Tx
39 Note: Decoupling capacitor 22 uF 0.1 uF Laser
40 values are informative and
vary depending on applications Driver
41 GND

42
43
44
45 Note: VCC1 connection may Vcc1
be connected to VccTx or
46 VccRx provided the applicable
22 uF 0.1 uF

47 derating of the maximum

current limit is used. GND
48
49 QSFP Module

QSFP Public Specification 16

1 3.1.1 Low Speed Electrical Hardware Pins
2 In addition to the 2-wire serial interface the module has the following low speed pins for control and status:
3
a) ModSelL
4 b) LPMode
5 c) ResetL
6 d) ModPrsL
7 e) IntL
8
3.1.1.1 ModSelL
9
10 The ModSelL is an input pin. When held low by the host, the module responds to 2-wire serial communication
11 commands. The ModSelL allows the use of multiple QSFP modules on a single 2-wire interface bus. When
the ModSelL is “High”, the module shall not respond to or acknowledge any 2-wire interface communication
12
from the host. ModSelL signal input node must be biased to the “High” state in the module.
13
14 In order to avoid conflicts, the host system shall not attempt 2-wire interface communications within the
ModSelL de-assert time after any QSFP modules are deselected. Similarly, the host must wait at least for the
15
period of the ModSelL assert time before communicating with the newly selected module. The assertion and
16 de-asserting periods of different modules may overlap as long as the above timing requirements are met.
17
18 3.1.1.2 ResetL
19 The ResetL pin must be pulled to Vcc in the QSFP module. A low level on the ResetL pin for longer than the
20 minimum pulse length (t_Reset_init) initiates a complete module reset, returning all user module settings to
21 their default state. Module Reset Assert Time (t_init) starts on the rising edge after the low level on the ResetL
22 pin is released. During the execution of a reset (t_init) the host shall disregard all status bits until the module
23 inidicates a completion of the reset interrupt. The module indicates this by posting an IntL signal with the
Data_Not_Ready bit negated. Note that on power up (including hot insertion) the module should post this
24
completion of reset interrupt without requiring a reset.
25
26 3.1.1.3 LPMode
27
The LPMode pin shall be pulled up to Vcc in the QSFP module. This function is affected by the LPMode pin
28 and the combination of the Power_over-ride and Power_set software control bits (Address A0h, byte 93 bits
29 0,1).
30
The module has two modes a low power mode and a high power mode. The high power mode operates in one
31 of the four power classes.
32
When the module is in a low power mode it has a maximum power consumption of 1.5W. This protects hosts
33
that are not capable of cooling higher power modules, should such modules be accidentally inserted.
34
35 The modules 2-wire serial interface and all laser safety functions must be fully operational in this low power
mode. The module shall still support the completion of reset interrupt in this low power mode.
36
37 If the Extended Identifier bits (Page 00h, byte 129 bits 6-7) indicate a power consumption greater than 1.5W
38 and the module is in low power mode it must reduce its power consumption to less than 1.5W while still
maintaining the functionality above. The exact method of accomplishing low power is not specified, however it
39
is likely that either the Tx or Rx or both will not be operational in this state.
40
41 If the Extended Identifier bits (Page 00h, byte 129 bits 6-7) indicate that its power consumption is less than
1.5W then the module shall be fully functional independent of whether it is in low power or high power mode.
42
43 The Module should be in low power mode if the LPMode pin is in the high state, or if the Power_ over-ride bit
44 is in the high state and the Power_set bit is also high. The module should be in high power mode if the
LPMode pin is in the low state, or the Power_over-ride bit is high and the Power_set bit is low. Note that the
45
default state for the Power_over-ride bit is low.
46
47
48
49

QSFP Public Specification 17

1 A truth table for the relevant configurations of the LPMode and the Power_over-ride and Power_set are shown
2 in Table 4.
3
Table 4 — Power Mode Truth Table
4
5 LPMode Power_Over-ride Bit Power_set Bit Module Power Allowed
6 1 0 X Low Power
7 0 0 X High Power
X 1 1 Low Power
8
X 1 0 High Power
9
10 At Power up, the Power_over-ride and Power_set bits shall be set to 0.
11
12 3.1.1.4 ModPrsL
13 ModPrsL is pulled up to Vcc_Host on the host board and grounded in the module. The ModPrsL is asserted
14 “Low” when inserted and deasserted “High” when the module is physically absent from the host connector.
15
3.1.1.5 IntL
16
17 IntL is an output pin. When “Low”, it indicates a possible module operational fault or a status critical to the host
18 system. The host identifies the source of the interrupt using the 2-wire serial interface.The IntL pin is an open
collector output and must be pulled to host supply voltage on the host board.
19
20 3.1.2 Low Speed Electrical Specification
21
Low speed signaling other than SCL and SDA is based on Low Voltage TTL (LVTTL) operating at Vcc. Vcc
22
refers to the generic supply voltages of VccTx, VccRx, Vcc_host or Vcc1. Hosts shall use a pull-up resistor
23 connected to Vcc_host on each of the 2-wire interface SCL (clock), SDA (data), and all low speed status
24 outputs.The SCL and SDA is a hot plug interface that may support a bus topology. During module insertion or
25 removal, the module may implement a pre-charge circuit which prevents corrupting data transfers from other
26 modules that are already using the bus.
27
NOTE 1 - Timing diagrams for SCL and SDA are included in Clause 6.2.2.
28
29 The QSFP low speed electrical specifications are given in Table 5. This specification ensures compatibility
30 between host bus masters and the 2-wire interface.
31
32 Table 5 — Low Speed Control and Sense Signals
33 Parameter Symbol Min Max Unit Condition
34 VOL 0 0.4 V IOL(max) = 3.0 mA
35 SCL and SDA VOH Vcc - 0.5 Vcc + 0.3 V
36 VIL -0.3 Vcc*0.3 V
SCL and SDA VIH Vcc*0.7 Vcc + 0.5 V
37
Capacitance for SCL
38 and SDA I/O pin Ci 14 pF
39 3.0 k Ohms Pullup
40 Cb 100 pF resistor, max
41 Total bus capacitive 1.6 k Ohms Pullup
42 load for SCL and SDA 200 pF resistor, max
43 | Iin | </= 125 uA for
44 LPMode, Reset and VIL -0.3 0.8 V 0V < Vin < Vcc
45 ModeSelL VIH 2 VCC + 0.3 V
46 VOL 0 0.4 V Iol = 2.0 mA
47 ModPrsL and IntL VOH VCC - 0.5 VCC + 0.3 V
48
49

QSFP Public Specification 18

1 3.1.3 High Speed Electrical Specification
2
3.1.3.1 Rx(n)(p/n)
3
4 Rx(n)(p/n) are QSFP module receiver data outputs. Rx(n)(p/n) are AC-coupled 100 Ohm differential lines that
5 should be terminated with 100 Ohm differentially at the Host ASIC(SerDes). The AC coupling is inside the
QSFP module and not required on the Host board. When properly terminated, the single-ended voltage swing
6
will be between 170 mV to 800 mV and the differential voltage swing (absolute value) will be between 340
7 mVpp to 1600 mVpp.
8
Output squelch for loss of optical input signal, hereafter Rx Squelch, is required and shall function as follows.
9
In the event of the optical signal on any channel becoming equal to or less than the level required to assert
10 LOS, then the receiver data output for that channel shall be squelched or disabled. In the squelched or
11 disabled state output impedance levels are maintained while the differential voltage swing shall be less than
12 50 mVpp.
13 In normal operation the default case has Rx Squelch active. Rx Squelch can be deactivated using Rx
14 Squelch Disable through the 2-wire serial interface. Rx Squelch Disable is an optional function. For specific
15 details refer to Clause 6.6.5.2.
16
17 3.1.3.2 Tx(n)(p/n)
18 Tx(n)(p/n) are QSFP module transmitter data inputs. They are AC-coupled 100 Ohm differential lines with 100
19 Ohm differential terminations inside the QSFP module. The AC coupling is inside the QSFP module and not
20 required on the Host board. The inputs will accept single-ended voltage swings between 250 mV to 800 mV
and differential voltage swings between 500 mVpp to 1600 mVpp (absolute value). For best EMI results,
21
single-ended swings between 250 mV and 600 mV and differential voltage swings between 500 mVpp to 1200
22 mVpp (absolute value) are recommended.
23
Output squelch, hereafter Tx Squelch, for loss of input signal, hereafter Tx LOS, is an optional function.
24
Where implemented it shall function as follows. In the event of the differential, peak-to-peak electrical signal
25 on any channel becomes equal to or less than 50 mVpp, then the transmitter optical output for that channel
26 shall be squelched or disabled and the associated TxLOS flag set.
27
28 Where squelched, the transmitter OMA shall be less than or equal to -26 dBm and when disabled the
29 transmitter power shall be less than or equal to -30 dBm. For applications, e.g. Ethernet, where the transmitter
30 off condition is defined in terms of average power, disabling the transmitter is recommended and for
applications, e.g. InfiniBand, where the transmitter off condition is defined in terms of OMA, squelching the
31
transmitter is recommended.
32
33 In module operation, where Tx Squelch is implemented, the default case has Tx Squelch active. Tx Squelch
can be deactivated using Tx Squelch Disable through the 2-wire serial interface. Tx Squelch Disable is an
34
optional function. For specific details refer to Clause 6.6.5.2.
35
36 3.2 Power Requirements
37
The power supply has three designated pins, Vcc Tx, Vcc1, and Vcc Rx, in the connector. Vcc1 is used to
38
supplement Vcc Tx or Vcc Rx at the discretion of the module vendor. Power is applied concurrently to these
39 pins.
40
Since different classes of modules exist with pre-defined maximum power consumption limits, it is necessary
41
to avoid exceeding the system power supply limits and cooling capacity when a module is inserted into a
42 system designed to only accommodate lower power modules. It is recommended that the host, through the
43 management interface, identify the power consumption class of the module before allowing the module to go
44 into high power mode.
45 A host board together with the QSFP module(s) forms an integrated power system. The host supplies stable
46 power to the module. The module limits electrical noise coupled back into the host system and limits inrush
47 charge/current during hot plug insertion.
48
49

QSFP Public Specification 19

1 All specifications shall be met at the maximum power supply current. No power sequencing of the power
2 supply is required of the host system since the module sequences the contacts in the order of ground, supply
and signals during insertion.
3
4 3.2.1 Host Board Power Supply Filtering
5
The host board should use the power supply filtering shown in Figure 4.
6
7 Figure 4 — Recommended Host Board Power Supply Filtering
8
1uH
9
10 Vcc Tx
11 0.1 uF 22 uF
Vcc_host =
12 GND 3.3 Volt
13
14 1uH
15 Vcc Rx
16 0.1 uF 22 uF 0.1 uF 22 uF
17 GND
18
19
20 1uH
21 Vcc1
22 0.1 uF 22 uF
23 GND
24
25
26
QSFP Module
27
28
29 Any voltage drop across a filter network on the host is counted against the host DC set point accuracy
30 specification. Inductors with DC Resistance of less than 0.1 Ohm should be used in order to maintain the
31 required voltage at the Host Edge Card Connector.
32 The specification for the power supply is shown in Table 6.
33
34 Table 6 — Power Supply Specification
35 Parameter Min Nominal Max Unit Condition
36 Measured at Vcc Tx, Vcc Rx and
37 Vcc 3.3 V Vcc1.
Measured at Vcc Tx, Vcc Rx and
38
Vcc set point accuracy -5 5 % Vcc1.
39
Power Supply Noise 1 kHz to frequency of operation
40 including ripple 50 mV measured at Vcc_host.
41 Module Maximum Current
42 Inrush with LPMode Pin
43 asserted 0.55 A
44 Module Maximum Current
45 Inrush with LPMode Pin
deasserted 1.3 A
46
47
Module Current Ramp Rate 100 mA/uS
48
49

QSFP Public Specification 20

1 Power levels associated with classifications of modules is shown in Table 7.
2
Table 7 — Power Budget Classification
3
4 Power Level Max Power (W)
5 1 1.5
2 2
6
3 2.5
7 4 3.5
8
9 In general, the higher power classification level is associated with higher data rates and longer reach. The
10 system designer is responsible for ensuring that the maximum temperature does not exceed the case
temperature requirements.
11
12 3.3 ESD
13
14 The module and all pins shall withstand 500V electrostatic discharge based on Human Body Model per
JEDEC JESD22-A114-B.
15
16 The module shall meet ESD requirements given in EN61000-4-2, criterion B test specification such that when
17 installed in a properly grounded cage and chassis the units are subjected to 15KV air discharges during
operation and 8KV direct contact discharges to the case.
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49

QSFP Public Specification 21

1 4 Mechanical and Board Definition
2
3 4.1 Introduction
4 The overall transceiver module defined in this clause is illustrated in Figure 5. The module and connector
5 dimensions described in this clause are constant for all applications. The bezel, cage assembly, heat sink, and
6 clip can be designed and/or adjusted for the individual application.
7 Figure 5 — QSFP Module Rendering
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49

QSFP Public Specification 22

1 4.2 QSFP Datums and Component Alignment
2 A listing of the datums for the various components is contained in Table 8. The alignments of some of the
3 datums are noted. The relationship of the Transceiver, Cage, and Connector relative to the Host Board and
4 Bezel is illustrated in Figure 6 by the location of the key datums of each of the components. In order to reduce
5 the complexity of the drawings, all dimensions are considered centered unless otherwise specified.
6
Table 8 — Definition of Datums
7
8 Datum Description
9 A Host Board top surface
10 B Centerline of bezel
C **Distance between Connector terminal thru holes on host board
11
D *Hard stop on transceiver
12 E **Width of transceiver
13 F Height of transceiver housing
14 G **Width of transceiver pc board
15 H Leading edge of signal contact pads on transceiver pc board
16 J Top surface of transceiver pc board
17 K *Host Board thru hole #1 to accept connector guide post
18 L *Host Board thru hole #2 to accept connector guide post
M **Width of bezel cut out
19
N Connector alignment pin
20 P **Width of inside of cage at EMI gasket (when fully compressed)
21 R Height of inside of cage at EMI Gasket (when fully compressed)
22 S Seating Plane of cage on host board
23 T *Hard stop on cage
24 V Length of heat sink clip
25 W Seating Surface of the heat sink on the cage
X&Y Host board horizontal and depth datums established by customers’
26
fiducials
27 Z **Width of heat sink surface that fits into clip
28 AA **Connector slot width
29 BB Seating plane of cage on host board
30 CC Length of boss on heat sink that fits inside of the cage
31 *Datums D, K, L, N, and T are aligned when assembled (see Figure 6)
**Centerlines of datums AA C, E, G, M, P and Z are aligned on the same vertical axis
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49

QSFP Public Specification 23

1 Figure 6 — QSFP Datum Alignment, Depth
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
4.3 QSFP Transceiver Mechanical Package Dimensions
30
31 A common mechanical outline is used for all QSFP transceivers. The preferred method of removing the
transceiver from the cage assembly is by a bail type actuation method. The module shall provide a means to
32
self-lock with the cage upon insertion. The package dimensions for the QSFP transceiver are defined in
33 Figure 7 and Figure 8. The dimensions that control the size of the transceiver that extends outside of the cage
34 are listed as maximum dimensions per Note 1 and Note 6 in Figure 7.
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49

QSFP Public Specification 24

1 Figure 7 — Drawing of QSFP Transceiver (Part 1 of 2)
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49

QSFP Public Specification 25

1 Figure 8 — Drawing of QSFP Transceiver (Part 2 of 2)
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49

QSFP Public Specification 26

1 4.3.1 Mating of QSFP Transceiver PCB to QSFP Electrical Connector
2 The QSFP transceiver contains a printed circuit board that mates with the QSFP electrical connector. The
3 pads are designed for a sequenced mating:
4 First mate – ground contacts
5 Second mate – power contacts
6 Third mate – signal contacts
7 The pattern layout for the QSFP Printed Circuit Board is shown in Figure 9.
8
Figure 9 — Pattern Layout for QSFP Printed Circuit Board
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49

QSFP Public Specification 27

1 4.4 Host PCB Layout
2 A typical host board mechanical layout for attaching the QSFP Connector and Cage System is shown in
3 Figure 10 and Figure 11. Location of the pattern on the host board is application specific. See Clause 4.6 for
4 details on the location of the pattern relative to the bezel.
5 Figure 10 — QSFP Host PCB Mechanical Layout
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49

QSFP Public Specification 28

1 Figure 11 — QSFP Host PCB Mechanical Layout, Detail Z
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30 4.4.1 Insertion, Extraction and Retention Forces for QSFP Transceivers
31 The requirement for insertion forces, extraction forces and retention forces are specified in Table 9. The QSFP
32 cage and module design combinations must ensure excessive force applied to a cable does not damage the
33 QSFP cage or host connector. If any part is damaged by excessive force, it should be the cable or media
34 module and not the cage or host connector which is part of the host system.
35
Table 9 — Insertion, Extraction and Retention Forces
36
37 Measurement Min Max Units Comments
38 QSFP transceiver insertion 0 40 N
QSFP transceiver extraction 0 30 N
39
QSFP transceiver retention 90 N/A N No damage to transceiver below 90N
40 Cage retention (Latch strength) 180 N/A N No damage to latch below 180N
41 Cage retention in Host Board 114 N/A N Force to be applied in a vertical direction,
42 no damage to cage
43 Insertion / removal cycles, 100 N/A Cyc. Number of cycles for the connector and
44 connector/cage cage with multiple transceivers.
45 Insertion / removal cycles, QSFP 50 N/A Cyc. Number of cycles for an individual
46 Transceiver transceiver.
47
48
49

QSFP Public Specification 29

1 4.5 Color Coding and Labeling of QSFP Transceivers
2 An exposed feature of the QSFP transceiver (a feature or surface extending outside of the bezel) shall be
3 color coded as follows:
4
Beige for 850nm
5 Blue for 1310nm
6 White for 1550nm
7
Each QSFP transceiver shall be clearly labeled. The complete labeling need not be visible when the QSFP
8 transceiver is installed and the bottom of the device is the recommended location for the label. Labeling shall
9 include:
10
Appropriate manufacturing and part number identification
11 Appropriate regulatory compliance labeling
12 A manufacturing trace ability code
13
Also the label should include clear specification of the external port characteristics such as:
14
15 Optical wavelength
Required fiber characteristics
16
Operating data rate
17 Interface standards supported
18 Link length supported
19
The labeling shall not interfere with the mechanical, thermal or EMI features.
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49

QSFP Public Specification 30

1 4.6 Bezel for Systems Using QSFP Transceivers
2 Host enclosures that use QSFP devices should provide appropriate clearances between the QSFP
3 transceivers to allow insertion and extraction without the use of special tools and a bezel enclosure with
4 sufficient mechanical strength. See Figure 12 for the recommended bezel designs. The minimum
5 recommended host board thickness for belly-to-belly mounting of the assemblies is 2.2mm minimum.
6 Applications with host boards less than 2.2 mm minumum will require module dimensions of less than 1.6 mm
shown with Note 1 of Figure 7.
7
8 The front surface of the cage assembly passes through the bezel. If EMI spring fingers are used, they make
9 contact to the inside of the bezel cutouts. If an EMI gasket is used, it makes contact to the inside surface of the
bezel. To accept all cage designs, both bezel surfaces must be conductive and connected to chassis ground.
10
11 The recommended basic dimension from the bezel centerline to Datum K and Datum L (See Figure 6 and
12 Figure 12) on the Host board is 43.8mm nominal. The total tolerance can be calculated as follows:
13 +/- tolerance = 1/2 (bezel thickness) + 0.3mm
14 For example, a bezel thickness of 1.6mm will have a bezel centerline tolerance of +/- 1.1mm.
15 The dimension of 43.8 +/- 1.1mm would apply from the Centerline of the bezel to Datums K and L.
16
The QSFP transceiver insertion slot should be clear of nearby moldings and covers that might block
17 convenient access to the latching mechanisms, the QSFP transceiver, or the cables connected to the
18 QSFP transceiver.
19 Figure 12 — Recommended Bezel Design
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49

QSFP Public Specification 31

1 4.7 QSFP Electrical Connector Mechanical
2 The QSFP Connector is a 38-contact, right angle surface mount connector and is shown in Figure 13. The
3 mechanical specification for the connector is shown in Figure 14.
4
Figure 13 — QSFP Transceiver Electrical Connector Illustration
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Figure 14 — QSFP Electrical Connector Specification
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49

QSFP Public Specification 32

1 4.8 Individual QSFP Cage Assembly
2 An exploded view of a complete 1-by-1 assembly is shown schematically in Figure 15.
3
Figure 15 — Cage and Optional Heat Sink Design (exploded view)
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49

QSFP Public Specification 33

1 The detailed drawing for the cage assembly is shown in Figure 16.
2 Figure 16 — 1-by-1 cage
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49

QSFP Public Specification 34

1 4.8.1 QSFP Heat Sink Clip Dimensions
2 The heat sink clip defined in Figure 17 is for reference only. The design of the heat sink clip, heat sink and
3 features on the cage assembly are vendor specific and not defined in this document. When fastened to the
4 cage, the clip will provide a minimum force of 5 Newtons at the interface of the heat sink and QSFP
5 transceiver. The clip is designed to permit a heat sink to be fastened into the clip then assembled to the cage
and to expand slightly during transceiver insertion in order to maintain a contact force between the transceiver
6
and heat sink.
7
8 Figure 17 — QSFP Heat Sink Clip
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49

QSFP Public Specification 35

1 4.8.2 QSFP Heat Sink Dimensions
2 The heat sink illustrated in Figure 18 is for reference only. Critical dimensions to ensure that the heat sink will
3 be compatible with the Heat Sink Clip are defined. The configuration of the fins or posts is application specific
4 along with the outside envelope. The heat sink includes a beveled edge which “rides up” the leading edge of
5 the transceiver as the transceiver is inserted into the cage assembly. The recommended material for the heat
sink is aluminum and the surface treatment for the transceiver contacting surface can be anodizing or nickel
6
plating.
7
8 Figure 18 — QSFP Heat Sink
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49

QSFP Public Specification 36

1 4.8.3 Light Pipes
2 The use of light pipes to indicate status of the transceiver is application specific.
3
4 4.9 Dust / EMI Cover
5 In order to prevent contamination of the internal components and to optimize EMI performance, it is
6 recommended that a Dust/EMI Cover be inserted into the cage assembly when no transceiver is present. See
7 Figure 19 for the recommended design. During installation, the front flange on the cover shall be seated
8 against the front surface of the bezel to prevent dust from entering the equipment. The conductivity of the
9 materials should be chosen for the Dust/EMI Cover to block EMI emissions.
10 Figure 19 — Dust / EMI Cover
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32 4.10 Optical Interface
33 The QSFP optical interface port shall receive a female MPO receptacle as specified in IEC 61754-7. Aligned
34 key (Type B) MPO patchcords should be used to ensure alignment of the signals between the modules.
35 TIA-568 has standardized an aligned key patchcord. The transmit / receive convention is detailed in Figure 20.
36 If the optical connector is orientated such that the keying feature of the MPO receptacle is on the top, then
fibers are numbered left to right as 12 through 1 looking into the receptacle.
37
38 The four fiber positions on the left (fibers 12, 11, 10, 9) are used for the optical transmit signals (Channel 1
39 through 4). The fiber positions on the right (fibers 4, 3, 2, 1) are used for the optical receive signals (Channel 4
through 1).
40
41 The central four fibers (5, 6, 7, 8) may be physically present.
42
43
44
45
46
47
48
49

QSFP Public Specification 37

1
2 Figure 20 — QSFP Optical Receptacle and Channel Orientation
3
4
5
6
7
8
9
10 Fiber Number: 12 11 10 9 ...... 4 3 2 1
11 Transmit Channels: 1 2 3 4
12
Receive Channels: 4321
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49

QSFP Public Specification 38

5 Environmental and Thermal

5.1 Thermal Requirements

The QSFP module shall operate within one or more of the case temperatures ranges defined in Table 10. The
temperature ranges are applicable between 60m below sea level and 1800m above sea level, (Ref. NEBS
GR-63) utilizing the host systems designed airflow.

Table 10 — Temperature Classification of Module Case

Class Case Temperature Range

Standard 0 through 70C
Extended -5 through 85C
Industrial -40 through 85C

QSFP is designed to allow for up to 16 adjacent transceivers, ganged and/or belly-to-belly, with the
appropriate thermal design for cooling / airflow. (Ref. NEBS GR-63)

QSFP Public Specification 39

1 6 Management Interface
2
3 6.1 Introduction
4 A management interface, as already commonly used in other form factors like GBIC, SFP, and XFP, is
5 specified in order to enable flexible use of the transceiver by the user. The specification has been changed in
6 order to adopt the use of a multi-channel transceiver. Some timing requirements are critical especially for a
7 multi-channel device, so the interface speed has been increased.
8
6.2 Timing Specification
9
10 6.2.1 Introduction
11
Low speed signaling is based on Low Voltage CMOS (LVCMOS) operating at Vcc. Hosts shall use a pull-up
12 resistor connected to a Vcc_host on the 2-wire interface SCL (clock) and SDA (Data) signals. Detailed
13 electrical specification is given in Clause 3.1.2. Nomenclature for all registers more than 1 bit long is
14 MSB-LSB.
15
16 6.2.2 Management Interface Timing Specification
17 In order to support a multi-channel device a higher clock rate for the serial interface is considered. The timing
18 requirements are shown in Figure 21 and specified in Table 11.
19 QSFP is positioned to leverage 2-wire timing (Fast Mode devices) to align the use of related cores on host
20 ASICs. This clause closely follows the XFP MSA specification.
21 Figure 21 — QSFP Timing Diagram
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
Before initiating a 2-wire serial bus communication, the host shall provide setup time (Host_select_setup -
40 Table 11) on the ModSelL line of all modules on the 2-wire bus. The host shall not change the ModSelL line of
41 any module until the 2-wire serial bus communication is complete and the hold time requirement
42 (Host_select_hold - Table 11) is satisfied. The 2-wire serial interface address of the QSFP module is
43 1010000X (A0h). In order to allow access to multiple QSFP modules on the same 2-wire serial bus, the QSFP
44 pinout includes a ModSelL or module select pin. This pin (which is pulled high or deselected in the module)
45 must be held low by the host to select the module of interest and allow communication over the 2-wire serial
interface. The module must not respond to or accept 2-wire serial bus instructions unless it is selected.
46
47 6.2.3 Serial Interface Protocol
48
The module asserts LOW for clock stretch on SCL.
49

QSFP Public Specification 40

1 6.2.3.1 Management Timing Parameters
2 The timing parameters for the 2-Wire interface to the QSFP module are shown in Table 11.
3
4 Table 11 — QSFP 2-Wire Timing Specifications
5 Parameter Symbol Min Max Unit Conditions
6 Clock Frequency fSCL 0 400 kHz
7
Clock Pulse Width Low tLOW 1.3 us
8
9 Clock Pulse Width High tHIGH 0.6 us
10
11 Time bus free before tBUF 20 us Between STOP and START
new transmission can
12
start
13
START Hold Time tHD,STA 0.6 us
14
15 START Set-up Time tSU,STA 0.6 us
16 Data In Hold Time tHD,DAT 0 us
17 Data In Set-up Time tSU,DAT 0.1 us
18
Input Rise Time tR,400 300 ns From (VIL,MAX - 0.15) to
19
(400kHz) (VIH,MIN + 0.15)
20
Input Fall Time (400kHz) tF,400 300 ns From (VIH,MIN + 0.15) to
21 (VIL,MAX - 0.15)
22
STOP Set-up Time tSU,STO 0.6 us
23
24 ModSelL Setup Time Host_sele 2 ms Setup time on the select lines
ct_setup before start of a host initiated
25
serial bus sequence
26 ModSelL Hold Time Host_sele 10 us Delay from completion of a
27 ct_hold serial bus sequence to changes
28 of transceiver select status
29
30 Aborted sequence - bus Deselect_ 2 ms Delay from a host de-asserting
31 release Abort ModSelL (at any point in a bus
32 sequence),to the QSFP module
releasing SCL and SDA
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49

QSFP Public Specification 41

1 6.3 Memory Interaction Specifications
2 QSFP memory transaction timings are given in Table 12. Single byte writable memory blocks are given in
3 Table 13. Multiple byte writable memory blocks are defined in Table 14.
4
5 Table 12 — QSFP Memory Specification
6 Parameter Symbol Min Max Unit Conditions
7 Serial Interface Clock T_clock_hold 500 us Maximum time the QSFP
8 Holdoff "Clock Stretching" module may hold the SCL line
9 low before continuing with a
10 read or write operation
11 Complete Single or tWR 40 ms Complete (up to) 4 Byte Write
Sequential Write
12 o
Endurance (Write Cycles) 50 k cycles 70 C
13
14
15 Table 13 — Single Byte Writable Memory Block
16 Page Address Volatile or NonVolatile Description
17 A0h 86 Volatile Control Register
18 A0h 87 Volatile Rx Rate select register
19 A0h 88 Volatile Tx Rate select register
A0h 127 Volatile Page Select Byte
20
21
22 Table 14 — Multiple Byte Writable Memory Block
23 Volatile /
24 Address # Bytes NonVolatile Description
25 89-92 4 Volatile Application select per channel
26 100-106 7 Volatile Module Mask
119-122 4 Volatile Password Change Entry Area (Optional)
27 Password Entry Area (Optional)
123-126 4 Volatile
28 128-255 128 Non-Volatile User Writable memory - Page 02h
29 225-241 16 Volatile Vendor Specific Channel Controls - Page 03h
30 242-253 12 Volatile Channel Monitor Masks - Page 03h
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49

QSFP Public Specification 42

1 6.3.1 Timing for Soft Control and Status Functions
2 Timing for QSFP soft control and status functions are described in Table 15.
3
4 Table 15 — I/O Timing for Soft Control and Status Functions
5 Parameter Symbol Max Unit Conditions
Initialization Time t_init 2000 ms 2
6 Time from power on , hot plug or rising edge of
3
7 Reset until the module is fully functional This
8 time does not apply to non-Power Level 0
modules in the Low Power State.
9 Reset Init Assert Time t_reset_init 2 us A Reset is generated by a low level longer than
10 the minimum reset pulse time present on the
11 ResetL pin.
12 Serial Bus Hardware t_serial 2000 ms 2
Time from power on until module responds to
13 Ready Time data transmission over the 2-wire serial bus
14 Monitor Data Ready t_data 2000 ms 2
Time from power on to data not ready, bit 0 of
15 Time Byte 2, deasserted and IntL asserted
16 Reset Assert Time t_reset 2000 ms Time from rising edge on the ResetL pin until
3
17 the module is fully functional
LPMode Assert Time ton_LPMode 100 us Time from assertion of LPMode (Vin:LPMode =
18 Vih) until module power consumption enters
19 Power Level 1
20 IntL Assert Time ton_IntL 200 ms Time from occurrence of condition triggering
21 IntL until Vout:IntL = Vol
IntL Deassert Time toff_IntL 500 us 4
22 Time from clear on read operation of
23 associated flag until Vout:IntL = Voh. This
includes deassert times for Rx LOS, Tx Fault
24
and other flag bits.
25 Rx LOS Assert Time ton_los 100 ms Time from Rx LOS state to Rx LOS bit set
26 (value = 1b) and IntL asserted
27 Tx Fault Assert Time ton_Txfault 200 ms Time from Tx Fault state to Tx Fault bit set
28 (value = 1b) and IntL asserted
29 Flag Assert Time ton_flag 200 ms Time from occurrence of condition triggering flag
to associated flag bit set (value = 1b) and IntL
30 asserted
31 Mask Assert Time ton_mask 100 ms 1
Time from mask bit set (value = 1b) until
32 associated IntL assertion is inhibited
33 Mask Deassert Time toff_mask 100 ms Time from mask bit cleared (value = 0b) until
1

34 associated IntlL operation resumes

35 Application or Rate t_ratesel 100 ms Time from change of state of Application or Rate
36 Select Change Time 1
Select bit until transmitter or receiver bandwidth
37 is in conformance with appropriate specification
38 1
Power_over-ride or ton_Pdown 100 ms Time from P_Down bit set (value = 1b) until
39 Power-set Assert Time module power consumption enters Power Level
40 1
41 Power_over-ride or toff_Pdown 300 ms 1
Time from P_Down bit cleared (value = 0b) until
42 Power-set Deassert 3
the module is fully functional
43 Time
44 Note 1. Measured from falling clock edge after stop bit of write transaction.
45 Note 2. Power on is defined as the instant when supply voltages reach and remain at or above the
46 minimum level specified in Table 6.
47 Note 3. Fully functional is defined as IntL asserted due to data not ready bit, bit 0 byte 2 deasserted. The
module should also meet optical and electrical specifications.
48
49 Note 4. Measured from falling clock edge after stop bit of read transaction.

QSFP Public Specification 43

1 Squelch and disable timings are defined in Table 16.
2
Table 16 — I/O Timing for Squelch and Disable
3
4 Parameter Symbol Max Unit Conditions
5 Rx Squelch Assert Time ton_Rxsq 80 us Time from loss of Rx input signal until the
6 squelched output condition is reached. See
clause 3.1.3.1.
7
Rx Squelch Deassert toff_Rxsq 80 us Time from resumption of Rx input signals until
8 Time normal Rx output condition is reached. See
9 clause 3.1.3.1.
10
Tx Squelch Assert Time ton_Txsq 400 ms Time from loss of Tx input signal until the
11 squelched output condition is reached. See
12 clause 3.1.3.2.
13 Tx Squelch Deassert toff_Txsq 400 ms Time from resumption of Tx input signals until
14 Time normal Tx output condition is reached. See
15 clause 3.1.3.2.
16 Tx Disable Assert Time ton_txdis 100 ms 1
Time from Tx Disable bit set (value = 1b) until
17 optical output falls below 10% of nominal
18
Tx Disable Deassert toff_txdis 400 ms 1
19 Time from Tx Disable bit cleared (value = 0b)
20 Time until optical output rises above 90% of nominal
21
Rx Output Disable ton_rxdis 100 ms Time from Rx Output Disable bit set (value =
22 1
Assert Time 1b) until Rx output falls below 10% of nominal
23
24 Rx Output Disable toff_rxdis 100 ms Time from Rx Output Disable bit cleared (value
25 Deassert Time 1
= 0b) until Rx output rises above 90% of
26 nominal
27 Squelch Disable Assert ton_sqdis 100 ms This applies to Rx and Tx Squelch and is the
28 Time 1
time from bit set (value = 1b) until squelch
29 functionality is disabled.
30 Squelch Disable toff_sqdis 100 ms This applies to Rx and Tx Squelch and is the
Deassert Time 1
31 time from bit cleared (value = 0b) until squelch
32 functionality is enabled.
33 Note 1. Measured from falling clock edge after stop bit of write transaction.
34
35 6.4 Device Addressing and Operation
36 Serial Clock (SCL): The host supplied SCL input to QSFP transceivers is used to positive-edge clock data into
37 each QSFP device and negative-edge clock data out of each device. The SCL line may be pulled low by an
38 QSFP module during clock stretching.
39 Serial Data (SDA): The SDA pin is bi-directional for serial data transfer. This pin is open-drain or
40 open-collector driven and may be wire-ORed with any number of open-drain or open collector devices.
41
Master/Slave: QSFP transceivers operate only as slave devices. The host must provide a bus master for SCL
42 and initiate all read/write communication.
43
44 Device Address: Each QSFP is hard wired at the device address A0h. See Clause 6.6 for memory structure
within each transceiver.
45
46 Multiple Devices per SCL/SDA: While QSFP transceivers are compatible with point-to-point SCL/SDA, they
47 can share a single SCL/SDA bus by using the QSFP ModSelL line. See Clause 3.1.1.1,Clause 3.1.2 and
Table 3 for more information.
48
49

QSFP Public Specification 44

1 Clock and Data Transitions: The SDA pin is normally pulled high with an external device. Data on the SDA pin
may change only during SCL low time periods. Data changes during SCL high periods indicate a START or
2
STOP condition. All addresses and data words are serially transmitted to and from the QSFP in 8-bit words.
3 Every byte on the SDA line must be 8-bits long. Data is transferred with the most significant bit (MSB) first.
4
START Condition: A high-to-low transition of SDA with SCL high is a START condition, which must precede
5
any other command.
6
7 STOP Condition: A low-to-high transition of SDA with SCL high is a STOP condition.
8 Acknowledge: After sending each 8-bit word, the transmitter releases the SDA line for one bit time, during
9 which the receiver is allowed to pull SDA low (zero) to acknowledge (ACK) that it has received each word.
10 Device address bytes and write data bytes initiated by the host shall be acknowledged by QSFP transceivers.
Read data bytes transmitted by QSFP transceivers shall be acknowledged by the host for all but the final byte
11
read, for which the host shall respond with a STOP instead of an ACK.
12
13 Memory (Management Interface) Reset: After an interruption in protocol, power loss or system reset the
QSFP management interface can be reset. Memory reset is intended only to reset the QSFP transceiver
14
management interface (to correct a hung bus). No other transceiver functionality is implied.
15
16 1) Clock up to 9 cycles.
2) Look for SDA high in each cycle while SCL is high.
17
3) Create a START condition as SDA is high
18
19 Device Addressing: QSFP devices require an 8-bit device address word following a start condition to enable a
read or write operation. The device address word consists of a mandatory sequence for the first seven most
20
significant bits in Figure 22. This is common to all QSFP devices.
21
22 Figure 22 — QSFP Device Address
23 1 0 1 0 0 0 0 R/W
24 MSB LSB
25
The eighth bit of the device address is the read/write operating select bit. A read operation is initiated if this bit
26 is set high and a write operation is initiated if this bit is set low. Upon compare of the device address (with
27 ModSelL in the low state) the QSFP transceiver shall output a zero (ACK) on the SDA line to acknowledge the
28 address.
29
30 6.5 Read/Write Functionality
31
32 6.5.1 QSFP Memory Address Counter (Read AND Write Operations)
33 QSFP devices maintain an internal data word address counter containing the last address accessed during
34 the latest read or write operation, incremented by one. The address counter is incremented whenever a data
35 word is received or sent by the transceiver. This address stays valid between operations as long as QSFP
power is maintained. The address “roll over” during read and writes operations is from the last byte of the
36 128-byte memory page to the first byte of the same page.
37
38
39
40
41
42
43
44
45
46
47
48
49

QSFP Public Specification 45

1 6.5.2 Read Operations (Current Address Read)
2 A current address read operation requires only the device address read word (10100001) be sent, see Figure
3 23. Once acknowledged by the QSFP, the current address data word is serially clocked out. The host does not
4 respond with an acknowledge, but does generate a STOP condition once the data word is read.
5 Figure 23 — QSFP Current Address Read Operation
6 <-- QSFP ADDR -->
7 H S M L R N S
8 O T S S E A T
S A B B A C O
9 T R D K P
10 T
1 0 1 0 0 0 0 1 0 x x x x x x x x 1
11 Q A M L
12 S C S S
13 F K B B
P
14 <---DATA WORD--->
15
16
6.5.3 Read Operations (Random Read)
17
18 A random read operation requires a “dummy” write operation to load in the target byte address as shown in
19 Figure 24. This is accomplished by the following sequence: The target 8-bit data word address is sent
following the device address write word (10100000) and acknowledged by the QSFP. The host then generates
20 another START condition (aborting the dummy write without incrementing the counter) and a current address
21 read by sending a device read address (10100001). The QSFP acknowledges the device address and serially
22 clocks out the requested data word. The host does not respond with an acknowledge, but does generate a
23 STOP condition once the data word is read.
24 Figure 24 — QSFP Random Read
25
26 <-- QSFP ADDR --> <--MEMORY ADDR-> <QSFP ADDR->
27 S W
S
28 H T R T R N S
29 O A M L I M L AM L E A T
S R S S T S S RS S A C O
30 T T B B E B B T B B D K P
31 1 0 1 0 0 0 0 0 0 x x x x x x x x 0 1 0 1 0 0 0 0 1 0x x x x x x x x 1
32 Q
33 S A A A M L
34 F C C C S S
P K K K B B
35
<DATA WORD n-->
36
37
38 6.5.3.1 Read Operations (Sequential Read)
39 Sequential reads are initiated by either a current address read Figure 25 or a random address read Figure 26.
40 To specify a sequential read, the host responds with an acknowledge (instead of a STOP) after each data
41
42
43
44
45
46
47
48
49

QSFP Public Specification 46

1 word. As long as the QSFP receives an acknowledge, it shall serially clock out sequential data words. The
sequence is terminated when the host responds with a NACK and a STOP instead of an acknowledge.
2
3 Figure 25 — Sequential Address Read Starting at QSFP Current Address
4 <QSFP ADDR>
5 S
6 H T R N S
O A M L E A A A T
7 S RS S A C C C O
8 T T B B D K K K P
9 1 0 1 0 0 0 0 1 0 x x x x x x x x 0 x x x x x x x x 0 x x x x x x x x 1

10 Q
S A M L M L M L
11 F CS S S S S S
12 P K B B B B B B
13 <DATA W ORD n> <DATA W ORD n+1> <DATA W ORD n+x>

14
15 Figure 26 — Sequential Address Read Starting with Random QSFP Read
16 <-- QSFP ADDR --> <-MEMORY ADDR> <-- QSFP ADDR -->
17
S W S
18 H T R T R N S
19 O A M L I M L A M L E A A A T
S R S S T S S R S S A C C C O
20 T T B B E B B T B B D K K K P
21 1 0 1 0 0 0 0 0 0x x x x x x x x 0 1 0 1 0 0 0 0 1 0x x x x x x x x 0x x x x x x x x 0x x x x x x x x 1
22 Q
S A A A M L M L M L
23 F C C C S S S S S S
24 P K K K B B B B B B

25 <DATA WORD n> <DATA WORD n+1> <DATA WORD n+x>

26
27 6.5.4 Write Operations (BYTE Write)
28 A write operation requires an 8-bit data word address following the device address write word (10100000) and
29 acknowledgement, see Figure 27. Upon receipt of this address, the QSFP shall again respond with a zero
30 (ACK) to acknowledge and then clock in the first 8-bit data word. Following the receipt of the 8-bit data word,
31 the QSFP shall output a zero (ACK) and the host master must terminate the write sequence with a STOP
32 condition for the write cycle to begin. If a START condition is sent in place of a STOP condition (i.e. a repeated
START per the 2-wire interface specification) the write is aborted and the data received during that operation
33 is discarded. Upon receipt of the proper STOP condition, the QSFP enters an internally timed write cycle, tWR,
34 to internal memory. The QSFP disables it’s management interface input during this write cycle and shall not
35 respond or acknowledge subsequent commands until the write is complete. Note that 2-wire interface
36 “Combined Format” using repeated START conditions is not supported on QSFP write commands.
37 Figure 27 — QSFP Write Byte Operation
38 <-- QSFP ADDR --> <-MEMORY ADDR-> <-- DATA W ORD -->
39 S W
40 H T R S
O A M L I M L M L T
41 S R S S T S S S S O
42 T T B B E B B B B P
43 1 0 1 0 0 0 0 0 0x x x x x x x x 0 x x x x x x x x 0
44 Q
S A A A
45 F C C C
46 P K K K
47
48
49

QSFP Public Specification 47

1 6.5.5 Write Operations (Sequential Write)
2 QSFP’s shall support up to a 4 sequential byte write without repeatedly sending QSFP address and memory
3 address information as shown in Figure 28. A “sequential” write is initiated the same way as a single byte
4 write, but the host master does not send a stop condition after the first word is clocked in. Instead, after the
QSFP acknowledges receipt of the first data word, the host can transmit up to three more data words. The
5
QSFP shall send an acknowledge after each data word received. The host must terminate the sequential write
6 sequence with a STOP condition or the write operation shall be aborted and data discarded. Note that 2-wire
7 interface “combined format” using repeated START conditions is not supported on QSFP write commands.
8
Figure 28 — QSFP Sequential Write Operation
9
10 <- QSFP ADDR -> <MEMORY ADDR> <--DATA WORD 1-> <--DATA WORD 2-> <--DATA WORD 3-> <-DATA WORD 4-->

11 S W
H T R S
12 O A M L I M L M L M L M L M L T
S R S S T S S S S S S S S S S O
13 T T B B E B B B B B B B B B B P
14 1 0 1 0 0 0 0 0 0x x x x x x x x 0x x x x x x x x 0x x x x x x x x 0x x x x x x x x 0x x x x x x x x 0
15 Q
16 S A A A A A A
F C C C C C C
17 P K K K K K K
18
19
20 6.5.6 Write Operations (Acknowledge Polling)
21
22 Once the QSFP internally timed write cycle has begun (and inputs are being ignored on the bus) acknowledge
polling can be used to determine when the write operation is complete. This involves sending a START
23 condition followed by the device address word. Only if the internal write cycle is complete shall the QSFP
24 respond with an acknowledge to subsequent commands, indicating read or write operations can continue.
25
26 6.6 QSFP Memory Map
27 This subclause defines the Memory Map for QSFP transceiver used for serial ID, digital monitoring and
28 certain control functions. The interface is mandatory for all QSFP devices. The interface has been designed
29 largely after the XFP MSA as defined in INF-8077i Rev.4.0. The memory map has been changed in order to
30 accommodate 4 optical channels and limit the required memory space. The single address approach as used
31 in XFP using paging for provision of more less time critical memory content is used in order to enable time
32 critical interactions between host and transceiver.
33 The structure of the memory is shown in Figure 29. The memory space is arranged into a lower, single page,
34 address space of 128 bytes and multiple upper address space pages. This structure permits timely access to
35 addresses in the lower page, e.g. Interrupt Flags and Monitors. Less time critical entries, e.g. serial ID
information and threshold settings, are available with the Page Select function. The structure also provides
36 address expansion by adding additional upper pages as needed. For example, in Figure 29 upper pages 01
37 and 02 are optional. Upper page 01 allows implementation of Application Select Table, and upper page 02
38 provides user read/write space. The lower page and upper pages 00 and 03 are always implemented. See
39 Table 39 for details regarding declaration of optional upper pages 01 and 02.
40
41
42
43
44
45
46
47
48
49

QSFP Public Specification 48

1 The interface address used is A0xh and is mainly used for time critical data like interrupt handling in order to
enable a “one-time-read” for all data related to an interrupt situation. After an Interrupt, IntL, has been
2
asserted, the host can read out the flag field to determine the effected channel and type of flag.
3
4 Figure 29 — QSFP Memory Map
2-wire serial address, 1010000x (A0h)"
5
0 (3 Bytes)
6 2
ID and status

7 3
21
Interrupt Flags
(19 Bytes)

8 22
33
Module Monitors
(12 Bytes)

9 34
81
Channel Monitors
(48 Bytes)

10 82
85
Reserved
(4 Bytes)

11 86
Control
(12 Bytes)
97
12 98
Reserved
(2 Bytes)
99
13 100
Module and Channel Mask
(7 Bytes)
106
14 107
Reserved
(12 Bytes)

15 118
119 Password Change Entry (4 Bytes)
Area (Optional)
16 122
123 Password Entry Area (4 Bytes)

17 126
127
(Optional)
(1 Bytes)
Page Select Byte
18 127

19
20
21
22 Page 00 Page 01 (Optional) Page 02 (Optional) Page 03

23 128
Base ID Fields
(64 Bytes) 128
CC_APPS
(1 Bytes) 128
User EEPROM Data
(128 Bytes) 128
Module Threshold
(48 Bytes)

24 191
192 (32 Bytes)
128
129 (1 Bytes)
255 175
176 (48 Bytes)
Extended ID AST Table Length (TL) Channel Threshold
25 223
224 (32 Bytes)
129
130 (2 Bytes)
223
224 (2 Bytes)
Vendor Specific ID Application Code Entry 0 Reserved
26 255 131
132 (2 Bytes)
225
226 Vendor Specific Channel (16 Bytes)
Application Code Entry 1
27 133 241
242
Controls
(12 Bytes)
other entries Channel Monitor Masks
28 253
254 (2 Bytes) 254 (2 Bytes)
29 255
Application Code Entry TL
255
Reserved

30
31
In order to allow access to multiple QSFP transceivers on the same 2-wire serial interface, the QSFP pinout
32 includes a ModSelL pin which allows the host to select the respective transceiver for interaction. See Clause
33 3.1.1.1 for details on ModSelL and Clause 3.1.2 for details of the 2-Wire serial interface.
34
Note: Unless specifically noted, all informative ID fields must be filled out. Using a value of 0 to indicate a field
35 is unspecified (as is common in the SFP definition) is not permitted. Reserved memory locations are to be
36 filled with logic zeros in all bit locations for reserved bytes, and in reserved bit locations for partially specified
37 byte locations as described in this clause.
38 APPLICABLE DOCUMENTS
39
Digital Diagnostic Monitoring Interface for Optical Transceivers SFF document number: SFF-8472, rev. 9.5
40
June 1, 2004.
41
42
43
44
45
46
47
48
49

QSFP Public Specification 49

1 6.6.1 Lower Memory Map
2 The lower 128 bytes of the 2-wire serial bus address space, see Table 17, is used to access a variety of
3 measurements and diagnostic functions, a set of control functions, and a means to select which of the various
4 upper memory map pages are accessed on subsequent reads. This portion of the address space is always
directly addressable and thus is chosen for monitoring and control functions that may need to be repeatedly
5
accessed. The definition of Identifier field is the same as page 00h Byte 128.
6
7 Table 17 — Lower Memory Map
8 Byte Address Description Type
9 0 Identifier (1 Byte) Read-Only
10 1-2 Status (2 Bytes) Read-Only
11 3-21 Interrupt Flags (19 Bytes) Read-Only
12 22-33 Module Monitors (12 Bytes) Read-Only
13 34-81 Channel Monitors (48 Bytes) Read-Only
14 82-85 Reserved (4 Bytes) Read-Only
86-97 Control (12 Bytes) Read/Write
15 98-99 Reserved (2 Bytes) Read/Write
16 100-106 Module and Channel Masks (7 Bytes) Read/Write
17 107-118 Reserved (12 Bytes) Read/Write
18 119-122 Password Change Entry Area (optional) (4 Bytes) Read/Write
19 123-126 Password Entry Area (optional) (4 Bytes) Read/Write
20 127 Page Select Byte Read/Write
21
22 6.6.1.1 Status Indicator Bits
23 The Status Indicators are defined in Table 18.
24
25 Table 18 — Status Indicators
26 Byte Bit Name Description
27 1 All Reserved
28 2 7 Reserved
29 6 Reserved
30 5 Reserved
4 Reserved
31 3 Reserved
32 2 Reserved
33 1 IntL Digital state of the IntL interrupt output pin.
34 0 Data_Not_ Indicates transceiver has not yet achieved power up and monitor data is
35 Ready not ready. Bit remains high until data is ready to be read at which time
36 the device sets the bit low.
37
38 The Data_Not_Ready bit is high during module power up and prior to a valid suite of monitor readings. Once
all monitor readings are valid, the bit is set low until the device is powered down.
39
40
41
42
43
44
45
46
47
48
49

QSFP Public Specification 50

1 6.6.1.2 Interrupt Flags
2 A portion of the memory map (Bytes 3 through 21), form a flag field. Within this field, the status of LOS and Tx
3 Fault as well as alarms and warnings for the various monitored items is reported. For normal operation and
4 default state, the bits in this field have the value of 0b. For the defined conditions of LOS, Tx Fault, module
and channel alarms and warnings, the appropriate bit or bits are set, value = 1b. Once asserted, the bits
5
remained set (latched) until cleared by a read operation that includes the affected bit or reset by the ResetL
6 pin.
7
The Channel Status Interrupt Flags are defined in Table 19.
8
9 Table 19 — Channel Status Interrupt Flags
10
11 Byte Bit Name Description
12 3 7 L-Tx4 LOS Latched TX LOS indicator, channel 4 (Optional)
13 6 L-Tx3 LOS Latched TX LOS indicator, channel 3 (Optional)
14 5 L-Tx2 LOS Latched TX LOS indicator, channel 2 (Optional)
15 4 L-Tx1 LOS Latched TX LOS indicator, channel 1 (Optional)
16 3 L-Rx4 LOS Latched RX LOS indicator, channel 4
17 2 L-Rx3 LOS Latched RX LOS indicator, channel 3
1 L-Rx2 LOS Latched RX LOS indicator, channel 2
18
0 L-Rx1 LOS Latched RX LOS indicator, channel 1
19
4 7-4 Reserved
20
3 L-Tx4 Fault Latched TX fault indicator, channel 4
21
2 L-Tx3 Fault Latched TX fault indicator, channel 3
22
1 L-Tx2 Fault Latched TX fault indicator, channel 2
23
0 L-Tx1 Fault Latched TX fault indicator, channel 1
24
5 All Reserved
25
26 The Module Monitor Interrupt Flags are defined in Table 20.
27
28 Table 20 — Module Monitor Interrupt Flags
29 Byte Bit Name Description
30 6 7 L-Temp High Alarm Latched high temperature alarm
31 6 L-Temp Low Alarm Latched low temperature alarm
32 5 L-Temp High Warning Latched high temperature warning
33 4 L-Temp Low Warning Latched low temperature warning
34 3-0 Reserved
35 7 7 L-Vcc High Alarm Latched high supply voltage alarm
36 6 L-Vcc Low Alarm Latched low supply voltage alarm
37 5 L-Vcc High Warning Latched high supply voltage warning
38 4 L-Vcc Low Warning Latched low supply voltage warning
39
3-0 Reserved
40
41 8 All Reserved
42
43
44
45
46
47
48
49

QSFP Public Specification 51

1 The Channel Monitor Interrupt Flags are defined in Table 21.
2
Table 21 — Channel Monitor Interrupt Flags
3
4 Byte Bit Name Description
5 9 7 L-Rx1 Power High Alarm Latched high RX power alarm, channel 1
6 6 L-Rx1 Power Low Alarm Latched low RX power alarm, channel 1
5 L-Rx1 Power High Warning Latched high RX power warning, channel 1
7 4 L-Rx1 Power Low Warning Latched low RX power warning, channel 1
8 3 L-Rx2 Power High Alarm Latched high RX power alarm, channel 2
9 2 L-Rx2 Power Low Alarm Latched low RX power alarm, channel 2
10 1 L-Rx2 Power High Warning Latched high RX power warning, channel 2
11 0 L-Rx2 Power Low Warning Latched low RX power warning, channel 2
12 10 7 L-Rx3 Power High Alarm Latched high RX power alarm, channel 3
13 6 L-Rx3 Power Low Alarm Latched low RX power alarm, channel 3
5 L-Rx3 Power High Warning Latched high RX power warning, channel 3
14
4 L-Rx3 Power Low Warning Latched low RX power warning, channel 3
15 3 L-Rx4 Power High Alarm Latched high RX power alarm, channel 4
16 2 L-Rx4 Power Low Alarm Latched low RX power alarm, channel 4
17 1 L-Rx4 Power High Warning Latched high RX power warning, channel 4
18 0 L-Rx4 Power Low Warning Latched low RX power warning, channel 4
19 11 7 L-Tx1 Bias High Alarm Latched high TX bias alarm, channel 1
20 6 L-Tx1 Bias Low Alarm Latched low TX bias alarm, channel 1
21 5 L-Tx1 Bias High Warning Latched high TX bias warning, channel 1
4 L-Tx1 Bias Low Warning Latched low TX bias warning, channel 1
22 3 L-Tx2 Bias High Alarm Latched high TX bias alarm, channel 2
23 2 L-Tx2 Bias Low Alarm Latched low TX bias alarm, channel 2
24 1 L-Tx2 Bias High Warning Latched high TX bias warning, channel 2
25 0 L-Tx2 Bias Low Warning Latched low TX bias warning, channel 2
26 12 7 L-Tx3 Bias High Alarm Latched high TX bias alarm, channel 3
27 6 L-Tx3 Bias Low Alarm Latched low TX bias alarm, channel 3
28 5 L-Tx3 Bias High Warning Latched high TX bias warning, channel 3
4 L-Tx3 Bias Low Warning Latched low TX bias warning, channel 3
29
3 L-Tx4 Bias High Alarm Latched high TX bias alarm, channel 4
30 2 L-Tx4 Bias Low Alarm Latched low TX bias alarm, channel 4
31 1 L-Tx4 Bias High Warning Latched high TX bias warning, channel 4
32 0 L-Tx4 Bias Low Warning Latched low TX bias warning, channel 4
33 13-14 All Reserved Reserved channel monitor flags, set 3
34 15-16 All Reserved Reserved channel monitor flags, set 4
35 17-18 All Reserved Reserved channel monitor flags, set 5
36 19-20 All Reserved Reserved channel monitor flags, set 6
21 All Reserved
37
38
39 6.6.1.3 Module Monitors
40 Real time monitoring for the QSFP module include transceiver temperature, transceiver supply voltage, and
41 monitoring for each transmit and receive channel. Channel monitoring functions are described in Clause
42 6.6.1.4.
43 Measured parameters are reported in 16-bit data fields, i.e., two concatenated bytes. These are shown in
44 Table 22. The 16 bit-data fields allow for wide dynamic range. This is not intended to imply that a 16-bit A/D
45 system is recommended or required in order to achieve the accuracy goals stated below. The width of the
data field should not be taken to imply a given level of precision. It is conceivable that the accuracy goals
46 herein can be achieved by a system having less than 16 bits of resolution. It is recommended that any
47 low-order data bits beyond the system’s specified accuracy be fixed at zero. Overall system accuracy and
48 precision will be vendor dependent.
49

QSFP Public Specification 52

1 To guarantee coherency of the diagnostic monitoring data, the host is required to retrieve any multi-byte fields
from the diagnostic monitoring data structure by the use of a single two-byte read sequence across the 2-wire
2
serial interface. The transceiver is required to insure that any multi-byte fields that are updated with
3 diagnostic monitoring data must have this update done in a fashion that guarantees coherency and
4 consistency of the data. In other words, the update of a multi-byte field by the transceiver must not occur such
5 that a partially updated multi-byte field can be transferred to the host. Also, the transceiver shall not update a
6 multi-byte field within the structure during the transfer of that multi-byte field to the host, such that partially
7 updated data would be transferred to the host.
8 Accuracy requirements specified below shall apply to the operating signal range specified in the relevant
9 standard. The manufacturer’s specification should be consulted for more detail on the conditions under which
10 the accuracy requirements are met.
11 Measurements are calibrated over vendor specified operating temperature and voltage and should be
12 interpreted as defined below. Alarm and warning threshold values should be interpreted in the same manner
13 as real time 16-bit data.
14 Internally measured transceiver temperature are represented as a 16-bit signed twos complement value in
15 increments of 1/256 degrees Celsius, yielding a total range of –128C to +128C that is considered valid
16 between –40 and +125C. Temperature accuracy is vendor specific but must be better than ±3 degrees
Celsius over specified operating temperature and voltage. Please see vendor specification for details on
17
location of temperature sensor.
18
19 Internally measured transceiver supply voltage are represented as a 16-bit unsigned integer with the voltage
defined as the full 16 bit value (0 – 65535) with LSB equal to 100 uVolt, yielding a total measurement range of
20
0 to +6.55 Volts. Practical considerations to be defined by transceiver manufacturer will tend to limit the actual
21 bounds of the supply voltage measurement. Accuracy is vendor specific but must be better than ±3% of the
22 manufacturer’s nominal value over specified operating temperature and voltage.
23
24 Table 22 — Module Monitoring Values
25 Byte Bit Name Description
26 22 All Temperature MSB Internally measured module temperature
27 23 All Temperature LSB
28 24-25 All Reserved
29 26 All Supply Voltage MSB Internally measured module supply voltage
30 27 All Supply Voltage LSB
28 - 33 All Reserved
31
32
33 6.6.1.4 Channel Monitoring
34 Real time channel monitoring is for each transmit and receive channel and includes optical input power and
35 Tx bias current. Module monitoring functions are described in Clause 6.6.1.3.
36 Measurements are calibrated over vendor specified operating temperature and voltage and should be
37 interpreted as defined below. Alarm and warning threshold values should be interpreted in the same manner
38 as real time 16-bit data. Table 23 defines the Channel Monitoring.
39 Measured TX bias current is in mA and are represented as a 16-bit unsigned integer with the current defined
40 as the full 16 bit value (0 – 65535) with LSB equal to 2 uA, yielding a total measurement range of 0 to 131 mA.
41 Accuracy is vendor specific but must be better than ±10% of the manufacturer’s nominal value over specified
42 operating temperature and voltage.
43 Measured RX received optical power is in mW and can represent either average received power or OMA
44 depending upon how bit 3 of byte 220 (upper memory page 00h) is set. Represented as a 16 bit unsigned
45 integer with the power defined as the full 16 bit value (0 – 65535) with LSB equal to 0.1 uW, yielding a total
measurement range of 0 to 6.5535 mW (~-40 to +8.2 dBm). Absolute accuracy is dependent upon the exact
46 optical wavelength. For the vendor specified wavelength, accuracy shall be better than ±3 dB over specified
47 temperature and voltage. This accuracy shall be maintained for input power levels up to the lesser of
48 maximum transmitted or maximum received optical power per the appropriate standard. It shall be
49

QSFP Public Specification 53

1 maintained down to the minimum transmitted power minus cable plant loss (insertion loss or passive loss) per
the appropriate standard. Absolute accuracy beyond this minimum required received input optical power
2
range is vendor specific.
3
4 Table 23 — Channel Monitoring Values
5
Byte Bit Name Description
6 34 All Rx1 Power MSB Internally measured RX input power, channel 1
7 35 All Rx1 Power LSB
8 36 All Rx2 Power MSB Internally measured RX input power, channel 2
9 37 All Rx2 Power LSB
10 38 All Rx3 Power MSB Internally measured RX input power, channel 3
11 39 All Rx3 Power LSB
12 40 All Rx4 Power MSB Internally measured RX input power, channel 4
41 All Rx4 Power LSB
13
42 All Tx1 Bias MSB Internally measured TX bias, channel 1
14 43 All Tx1 Bias LSB
15 44 All Tx2 Bias MSB Internally measured TX bias, channel 2
16 45 All Tx2 Bias LSB
17 46 All Tx3 Bias MSB Internally measured TX bias, channel 3
18 47 All Tx3 Bias LSB
19 48 All Tx4 Bias MSB Internally measured TX bias, channel 4
49 All Tx4 Bias LSB
20
50-57 Reserved channel monitor set 3
21 58-65 Reserved channel monitor set 4
22 66-73 Reserved channel monitor set 5
23 74-81 Reserved channel monitor set 6
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49

QSFP Public Specification 54

1 6.6.1.5 Control Bytes
2 Control Bytes are defined in Table 24.
3
4 Table 24 — Control Bytes
5 Byte Bit Name Description
6 86 7-4 Reserved
3 Tx4_Disable 1
7 Read/write bit that allows software disable of transmitters.
2 Tx3_Disable 1
8 Read/write bit that allows software disable of transmitters.
1 Tx2_Disable 1
9 Read/write bit that allows software disable of transmitters.
0 Tx1_Disable 1
10 Read/write bit that allows software disable of transmitters.
87 7 Rx4_Rate_Select Software Rate Select, Rx channel 4 msb (Optional)
11
6 Rx4_Rate_Select Software Rate Select, Rx channel 4 lsb (Optional)
12
5 Rx3_Rate_Select Software Rate Select, Rx channel 3 msb (Optional)
13
4 Rx3_Rate_Select Software Rate Select, Rx channel 3 lsb (Optional)
14 3 Rx2_Rate_Select Software Rate Select, Rx channel 2 msb (Optional)
15 2 Rx2_Rate_Select Software Rate Select, Rx channel 2 lsb (Optional)
16 1 Rx1_Rate_Select Software Rate Select, Rx channel 1 msb (Optional)
17 0 Rx1_Rate_Select Software Rate Select, Rx channel 1 lsb (Optional)
18 88 7 Tx4_Rate_Select Software Rate Select, Tx channel 4 msb (Optional)
19 6 Tx4_Rate_Select Software Rate Select, Tx channel 4 lsb (Optional)
20 5 Tx3_Rate_Select Software Rate Select, Tx channel 3 msb (Optional)
21 4 Tx3_Rate_Select Software Rate Select, Tx channel 3 lsb (Optional)
22 3 Tx2_Rate_Select Software Rate Select, Tx channel 2 msb (Optional)
23 2 Tx2_Rate_Select Software Rate Select, Tx channel 2 lsb (Optional)
24 1 Tx1_Rate_Select Software Rate Select, Tx channel 1 msb (Optional)
25 0 Tx1_Rate_Select Software Rate Select, Tx channel 1 lsb (Optional)
26 89 All Rx4_Application_Select Software Application Select per SFF-8079, Rx Channel 4 (Optional)
27 90 All Rx3_Application_Select Software Application Select per SFF-8079, Rx Channel 3 (Optional)
28 91 All Rx2_Application_Select Software Application Select per SFF-8079, Rx Channel 2 (Optional)
29 92 All Rx1_Application_Select Software Application Select per SFF-8079, Rx Channel 1 (Optional)
30 93 2-7 Reserved
93 1 Power_set Power set to low power mode. Default 0.
31
93 0 Power_over-ride Override of LPMode signal setting the power mode with software.
32 94 All Tx4_Application_Select Software Application Select per SFF-8079, Tx Channel 4 (Optional)
33 95 All Tx3_Application_Select Software Application Select per SFF-8079, Tx Channel 3 (Optional)
34 96 All Tx2_Application_Select Software Application Select per SFF-8079, Tx Channel 2 (Optional)
35 97 All Tx1_Application_Select Software Application Select per SFF-8079, Tx Channel 1 (Optional)
36 98-99 All Reserved
37 1. Writing “1” disables the laser of the channel.
38
39 If software Rate Select is not implemented, the transceiver ignores the value of Rate Select bits. The registers
40 read all “0”s upon power-up.
41
6.6.1.6 Module and Channel Masks
42
43 The host system may control which flags result in an interrupt (IntL) by setting high individual bits from a set of
44 masking bits in bytes 100-104 for module flags, and bytes 242-253 of page 03h for channel flags. These are
described in Table 25 and Table 48. A 1 value in a masking bit prevents the assertion of the hardware IntL pin
45
by the corresponding latched flag bit. Masking bits are volatile and startup with all unmasked (masking bits 0).
46
47 The mask bits may be used to prevent continued interruption from on-going conditions, which would otherwise
continually reassert the hardware IntL pin.
48
49

QSFP Public Specification 55

1 Table 25 — IntL Masking Bits for Module and Channel Status Interrupts
2 Byte Bit Name Description
3 100 7 M-Tx4 LOS Masking bit for TX LOS indicator, channel 4 (Optional)
6 M-Tx3 LOS Masking bit for TX LOS indicator, channel 3 (Optional)
4
5 M-Tx2 LOS Masking bit for TX LOS indicator, channel 2 (Optional)
5
4 M-Tx1 LOS Masking bit for TX LOS indicator, channel 1 (Optional)
6 3 M-Rx4 LOS Masking bit for RX LOS indicator, channel 4
7 2 M-Rx3 LOS Masking bit for RX LOS indicator, channel 3
8 1 M-Rx2 LOS Masking bit for RX LOS indicator, channel 2
9 0 M-Rx1 LOS Masking bit for RX LOS indicator, channel 1
10 101 7-4 Reserved
11 3 M-Tx4 Fault Masking bit for TX fault indicator, channel 4
12 2 M-Tx3 Fault Masking bit for TX fault indicator, channel 3
13 1 M-Tx2 Fault Masking bit for TX fault indicator, channel 2
14 0 M-Tx1 Fault Masking bit for TX fault indicator, channel 1
15 102 All Reserved
16 103 7 M-Temp High Alarm Masking bit for high Temperature alarm
17 6 M-Temp Low Alarm Masking bit for low Temperature alarm
18 5 M-Temp High Warning Masking bit for high Temperature warning
19 4 M-Temp Low Warning Masking bit for low Temperature warning
3-0 Reserved
20 104 7 M-Vcc High Alarm Masking bit for high Vcc alarm
21 6 M-Vcc Low Alarm Masking bit for low Vcc alarm
22 5 M-Vcc High Warning Masking bit for high Vcc warning
23 4 M-Vcc Low Warning Masking bit for low Vcc warning
24 3-0 Reserved
25 105-106 All Reserved
26
27 6.6.1.7 Rate Select
28 Rate Select is an optional control used to limit the receiver bandwidth for compatibility with multiple data rates
29 (most likely Fibre Channel). In addition, rate selection allows the transmitter to be fine tuned for specific data
30 rate transmissions.
31 The transceiver may:
32
a) Provide no support for rate selection
33
b) Rate selection using extended rate select
34 c) Rate selection with application select tables
35
36 6.6.1.7.1 No Rate Selection Support
37 When no rate selection is supported, (page 00h, byte 221, bits 2 and 3) have a value of 0 and Options (page
38 00h, byte 195, bit 5) have a value of 0. Lack of implementation does not indicate lack of simultaneous
39 compliance with multiple standard rates. Compliance with particular standards should be determined from
40 Transceiver Values (See Table 33).
41
6.6.1.7.2 Extended Rate Selection
42
43 When (page 00h, byte 221, bits 2 and 3) have the values of 0 and 1 respectively and at least one of the bits in
44 the Extended Rate Compliance byte (page 00h, byte 141) have a value of one, the module supports extended
rate select. Extended rate selection has reserved two bits per channel in the Rxn_Rate_Select and two bits
45
per channel in the Txn_Rate_Select to denote up to four rates. Table 26 defines the functionality when bit 0 of
46 byte 141 is 1. All other values of Extended Rate Compliance byte are reserved.
47
48
49

QSFP Public Specification 56

1 Table 26 — Functionality of xN_Rate_Select with Extended Rate Selection
2 xN_Rate_Select xN_Rate_Select Description
3 msb Value lsb Value
4 0 0 Optimized for data rates less than
5 2.2Gb/s
6 0 1 Optimized for data rates from 2.2 up
7 to 6.6Gb/s
8 1 0 Optimized for 6.6 Gb/s data rates and
9 above
10 1 1 Reserved
11
12 6.6.1.7.3 Rate Selection Using Application Select Tables
13 Application Select maximizes compatibility with SFF-8079 Part 2 for transceivers that are SFF-8472
14 compliant.
15 When the Rate Select declaration bits (page 00h, byte 221, bits 2 and 3) have the values of 1 and 0
16 respectively, the Application Select method defined in Page 01h is used (see Clause 6.6.3).
17
The host reads the entire application select table on page 01h to determine the capabilities of the transceiver.
18 The host controls each channel separately by writing a Control Mode and Table Select (TS) byte to bytes
19 89-92 and bytes 94-97. The bits of the Rx_Application Select and the Tx_Application Select registers are
20 defined in Table 27.
21
22 Table 27 — Definition of Application Select (Bytes 89 to 92 and Bytes 94 to 97))
23 7 6 5 4 3 2 1 0
24 Control Mode Table Select, TS
25
Control Mode defines the application control mode. Table Select selects module behavior from the AST
26
among 63 possibilities (000000 to 111110). Note that (111111) is invalid.
27
28 Table 28 — Detailed Description of Control Mode
29
30 Bit 7 Bit 6 Function Address 87, 88 Control Table Select Control
31 lsb and msb are used according to
32 0 0 Extended rate selection declaration bits. Ignored
33 Don't Field points to
34 1 care Application Select Ignored application
35 Default values for control mode is 0,0 and is volatile memory.
36
37 6.6.1.8 Password Entry and change
38 Bytes 119-126 are reserved for an optional password entry function. The Password entry bytes are write only
39 and will be retained until power down, reset, or rewritten by host. This function may be used to control read/
40 write access to vendor specific page 02h. Additionally, module vendors may use this function to implement
41 write protection of Serial ID and other QSFP read only information. Passwords may be supplied to and used
42 by Host manufacturers to limit write access in the User EEPROM Page 02h.
43 Password access shall not be required to access QSFP defined data in the lower memory page 00h or in
44 upper pages 00h, 02h and 03h. Note that multiple module manufacturer passwords may be defined to allow
45 selective access to read or write to various sections of memory as allowed above.
46 Host manufacturer and module manufacturer passwords shall be distinguished by the high order bit (bit 7,
47 byte 123). All host manufacturer passwords shall fall in the range of 00000000h to 7FFFFFFFh, and all
48 module manufacturer passwords in the range of 80000000h to FFFFFFFFh. Host manufacturer passwords
49 shall be initially set to 00001011h in new modules.

QSFP Public Specification 57

1 Host manufacturer passwords may be changed by writing a new password in bytes 119-122 when the correct
current Host manufacture password has been entered in 123-126, with the high order bit being ignored and
2
forced to a value of 0 in the new password.
3
4 The password entry field shall be set to 00000000h on power up and reset.
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49

QSFP Public Specification 58

1 6.6.2 Upper Memory Map Page 00h
2 Page 00h consists of the Serial ID and is used for read only identification information. The Serial ID is divided
3 into the Base_ID Fields, Extended ID Fields and Vendor Specific ID Fields. The format of the Serial ID
4 Memory Map is shown in Table 29.
5
Table 29 — Serial ID: Data Fields
6
7 Address Size (Bytes) Name Description of Base ID Field
8 Base_ID Fields
128 1 Identifier Identifier Type of serial transceiver
9
129 1 Ext. Identifier Extended identifier of serial transceiver
10 130 1 Connector Code for connector type
11 131-138 8 Transceiver Code for electronic compatibility or optical compatibility
12 139 1 Encoding Code for serial encoding algorithm
13 140 1 BR, nominal Nominal bit rate, units of 100 MBits/s.
14 Extended RateSelect
141 1 Compliance Tags for Extended RateSelect compliance
15
142 1 Length(SMF) Link length supported for SMF fiber in km
16
17 143 1 Length (E-50µm) Link length supported for EBW 50/125 µm fiber, units of 2 m
18 144 1 Length (50 µm) Link length supported for 50/125 µm fiber, units of 1 m
19 145 1 Length (62.5 µm) Link length supported for 62.5/125 µm fiber, units of 1 m
20 146 1 Length (Copper) Link length supported for copper, units of 1m
21 147 1 Device Tech Device technology
22 148-163 16 Vendor name QSFP vendor name (ASCII)
23 164 1 Extended Transceiver Extended Transceiver Codes for InfiniBand
165-167 3 Vendor OUI QSFP vendor IEEE company ID
24
168-183 16 Vendor PN Part number provided by QSFP vendor (ASCII)
25
184-185 2 Vendor rev Revision level for part number provided by vendor (ASCII)
26 186-187 2 Wavelength Nominal laser wavelength (Wavelength = value / 20 in nm)
27 Guaranteed range of laser wavelength (+/- value) from Nominal
28 188-189 2 Wavelength Tolerance wavelength.(Wavelength Tol. = value/200 in nm)
29 190 1 Max Case Temp Maximum Case Temperature in Degrees C.
30 191 1 CC_BASE Check code for Base ID Fields (addresses 128-190)
31 Extended ID Fields
32 192-195 4 Options Rate Select, TX Disable, TX Fault, LOS
33 196-211 16 Vendor SN Serial number provided by vendor (ASCII)
34 212-219 8 Date code Vendor's manufacturing date code
35 Diagnostic Monitoring Indicates which type of diagnostic monitoring is implemented (if
36 220 1 Type any) in the transceiver. Bit 1, 0 Reserved
37 Indicates which optional enhanced features are implemented in
221 1 Enhanced Options the transceiver.
38 1 Reserved Reserved
222
39 223 1 CC_EXT Check code for the Extended ID Fields (addresses 192-222)
40 Vendor Specific ID Fields
41 224-255 32 Vendor Specific Vendor Specific EEPROM
42
43
44
45
46
47
48
49

QSFP Public Specification 59

1 6.6.2.1 Identifier (Address 128)
2 The identifier value specifies the physical device described by the serial information. This value shall be
3 included in the serial data. The defined identifier values are shown in Table 30. The QSFP transceiver shall
4 use the identifier 0Ch.
5
Table 30 — Identifier Values
6
7 Value Description of Physical Device
00h Unknown or unspecified
8
01h GBIC
9 02h Module/connector soldered to motherboard
10 03h SFP transceiver
11 04h 300 pin XBI
12 05h XENPAK
13 06h XFP
14 07h XFF
15 08h XFP-E
09h XPAK
16
0Ah X2
17 0Bh DWDM-SFP
18 0Ch QSFP
19 0Dh-7Fh Reserved
20 80-FFh Vendor specific
21
22 6.6.2.2 Extended Identifier (Address 129)
23 The extended identifier provides additional information about the basic transceiver types such as whether the
24 transceiver contains a CDR function and identifies the power consumption class it belongs to.
25
26 Table 31 — Extended Identifier Values
27 Bit Description of device type
28 7-6 00: Power Class 1 Module (1.5 W max. power consumption)
01: Power Class 2 Module (2.0 W max. power consumption)
29
10: Power Class 3 Module (2.5 W max. power consumption)
30 11: Power Class 4 Module (3.5 W max. power consumption)
31 5 Reserved
32 4 0: No CLEI code present in Page 02h
33 1: CLEI code present in Page 02h
34 3-0 Reserved
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49

QSFP Public Specification 60

1 6.6.2.3 Connector (Address 130)
2 The Connector value indicates the external connector provided on the interface. This value shall be included
3 in the serial data. The defined connector values are shown in Table 32. Note that 01h – 0Bh are not QSFP
4 compatible, and are included for compatibility with other standards.
5
Table 32 — Connector Values
6
Value Description of Connector
7
00h Unknown or unspecified
8 01h SC
9 02h Fibre Channel Style 1 copper connector
10 03h Fibre Channel Style 2 copper connector
11 04h BNC/TNC
12 05h Fibre Channel coaxial headers
13 06h FiberJack
07h LC
14
08h MT-RJ
15 09h MU
16 0Ah SG
17 0Bh Optical pigtail
18 0Ch MPO
19 OD-1Fh Reserved
20 20h HSSDC II
21 21h Copper Pigtail
22h RJ45
22
23h-7Fh Reserved
23 80-FFh Vendor specific
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49

QSFP Public Specification 61

1 6.6.2.4 Transceiver (Address 131-138)
2 The following bit significant indicators define the electronic or optical interfaces that are supported by the
3 QSFP transceiver. At least one bit shall be set in this field. For Fibre Channel QSFPs, the Fibre Channel
4 speed, transmission media, transmitter technology, and distance capability shall all be indicated.
5
Table 33 — Transceiver Values
6
Address Bit Description of Transceiver Data
7 10 Gigabit Ethernet Compliance Codes
8 131 7 Reserved
131 6 10GBase-LRM
9 131 5 10GBase-LR
10 131 4 10GBASE-SR
131 3-0 Reserved
11 SONET Compliance Codes
12 132 7-4 Reserved
13 132 3 Reserved
132 2 OC 48, long reach
14 132 1 OC 48, intermediate reach
15 132 0 OC 48, short reach
133 7 Reserved
16 133 6 OC 12, single mode long reach
17 133 5 OC 12, single mode inter. reach
18 133 4 OC 12, single mode short reach
133 3 Reserved
19 133 2 OC 3, single mode long reach
20 133 1 OC 3, single mode inter. Reach
133 0 OC3, single mode short reach
21 Gigabit Ethernet Compliance Codes
22 134 7-4 Reserved
23 134 3 1000BASE-T
134 2 1000BASE-CX
24 134 1 1000BASE-LX
25 134 0 1000BASE-SX
Fibre Channel link length
26 135 7 very long distance (V)
27 135 6 short distance (S)
28 135 5 Intermediate distance (I)
135 4 Long distance (L)
29 135 3 Medium (M)
30 Fibre Channel transmitter technology
135 2 Reserved
31 135 1 Longwave laser (LC)
32 135 0 Electrical inter-enclosure (EL)
33 136 7 Electrical intra-enclosure
136 6 Shortwave laser w/o OFC (SN)
34 136 5 Shortwave laser w/ OFC (SL)
35 136 4 Longwave laser (LL)
136 0-3 Reserved
36 Fiber Channel transmission media
37 137 7 Twin Axial Pair (TW)
38 137 6 Shielded Twisted Pair (TP)
137 5 Miniature Coax (MI)
39 137 4 Video Coax (TV)
40 137 3 Multi-mode, 62.5m (M6)
137 2 Multi-mode, 50m (M5)
41 137 1 Multi-mode, 50um (OM3)
42 137 0 Single Mode (SM)
43 Fibre Channel Speed
138 7 1200 MBytes/Sec
44 138 6 800 MBytes/Sec
45 138 5 Reserved
138 4 400 MBytes/Sec
46 138 3 Reserved
47 138 2 200 MBytes/Sec
138 1 Reserved
48
138 0 100 MBytes/Sec
49

QSFP Public Specification 62

1 6.6.2.5 Encoding (Address 139)
2 The encoding value indicates the serial encoding mechanism that is the nominal design target of the particular
3 QSFP transceiver. The value shall be contained in the serial data. The defined encoding values are shown in
4 Table 34.
5
Table 34 — Encoding Values
6
7 Code Description of encoding mechanism
00h Unspecified
8 01h 8B10B
9 02h 4B5B
10 03h NRZ
11 04h SONET Scrambled
12 05h 64B66B
13 06h Manchester
14 07h - FFh Reserved
15
16 6.6.2.6 BR, nominal (Address 140)
17 The nominal bit rate (BR, nominal) is specified in units of 100 Megabits per second, rounded off to the nearest
18 100 Megabits per second. The bit rate includes those bits necessary to encode and delimit the signal as well
19 as those bits carrying data information. A value of 0 indicates that the bit rate is not specified and must be
20 determined from the transceiver technology. The actual information transfer rate will depend on the encoding
21 of the data, as defined by the encoding value.
22 6.6.2.7 Extended RateSelect Compliance (Address 141)
23
24 The Extended RateSelect Compliance field is used to allow a single QSFP transceiver the flexibility to comply
with single or multiple Extended RateSelect definitions. A definition is indicated by presence of a “1” in the
25 specified bit tag position. If exclusive, non-overlapping bit tag definitions are used, Page 00h, byte 141 will
26 allow compliance to 8 (1-8) distinct multi-rate definitions.
27
28 Table 35 — Extended RateSelect Compliance Tag Assignment
29 Address Bits Description
30 141 7-1 Reserved
31
32 QSFP Rate Select Version 1. This functionality
33 141 0 is different from SFF-8472 and SFF-8431.
34
Further details of the use of this field can be found in Clause 6.6.1.7.
35
36 6.6.2.8 Length (Standard SM Fiber)-km (Address 142)
37
Addition to EEPROM data from original GBIC definition. This value specifies the link length that is supported
38 by the QSFP transceiver while operating in compliance with the applicable standards using single mode fiber.
39 Supported link length is as specified in the SFF 8074i standard. The value is in units of kilometers. A value of
40 zero means that the transceiver does not support single mode fiber or that the length information must be
41 determined from the transceiver technology.
42
6.6.2.9 Length (OM3) (Address 143)
43
44 This value specifies the link length that is supported by the QSFP transceiver while operating in compliance
45 with the applicable standards using 2000 MHZ*km (850 nm) extended bandwidth 50 micron core multimode
fiber. The value is in units of 2 meters. A value of zero means that the transceiver does not support OM3 fiber
46
or that the length information must be determined from the transceiver technology.
47
48
49

QSFP Public Specification 63

1 6.6.2.10 Length (OM2) (Address 144)
2 This value specifies the link length that is supported by the QSFP transceiver while operating in compliance
3 with the applicable standards using 500 MHz*Km (850 nm and 1310 nm) 50 micron multi-mode fiber. The
4 value is in units of 1 meter. A value of zero means that the transceiver does not support OM2 fiber or that the
length information must be determined from the transceiver technology.
5
6 6.6.2.11 Length (OM1) (Address 145)
7
This value specifies the link length that is supported by the QSFP transceiver while operating in compliance
8
with the applicable standards using 200 MHz*Km (850 nm) and 500 MHz*Km (1310 nm) 62.5 micron
9 multi-mode fiber. The value is in units of 1 meter. A value of zero means that the transceiver does not support
10 OM1 fiber or that the length information must be determined from the transceiver technology.
11
12 6.6.2.12 Length (Copper) (Address 146)
13 This value specifies the minimum link length that is supported by the QSFP transceiver while operating in
14 compliance with the applicable standards using copper cable. The value is in units of 1 meter. Supported link
15 length is as specified in the SFF 8074i standard. A value of zero means that the transceiver does not support
16 Copper or that the length information must be determined from the transceiver technology. Further information
about the cable design, equalization, and connectors is usually required to guarantee meeting a particular
17
length requirement.
18
19 6.6.2.13 Device Tech (Address 147)
20
The technology used in the device is described in Table 36 and Table 37. The top 4 bits of the Device Tech
21 byte describe the device technology used. The lower four bits (bits 7-4) of the Device Tech byte are used to
22 describe the transmitter technology.
23
24 Table 36 — Description of Device Technology
25 Bits Description of physical device
26 7-4 Transmitter technology
27 3 0: No wavelength control
28 1: Active wavelength control
29 2 0: Uncooled transmitter device
1: Cooled transmitter
30
1 0: PIN detector
31 1: APD detector
32 0 0: Transmitter not tuneable
33 1: Transmitter tuneable
34
35 Table 37 — Transmitter Technology
36 Value Description of physical device
37 0000b 850 nm VCSEL
38 0001b 1310 nm VCSEL
39 0010b 1550 nm VCSEL
40 0011b 1310 nm FP
41 0100b 1310 nm DFB
0101b 1550 nm DFB
42 0110b 1310 nm EML
43 0111b 1550 nm EML
44 1000b Copper or others
45 1111b-1001b Reserved
46
47
48
49

QSFP Public Specification 64

1 6.6.2.14 Vendor Name (Address 148-163)
2 The vendor name is a 16 character field that contains ASCII characters, left-aligned and padded on the right
3 with ASCII spaces (20h). The vendor name shall be the full name of the corporation, a commonly accepted
4 abbreviation of the name of the corporation, the SCSI company code for the corporation, or the stock
exchange code for the corporation. At least one of the vendor name or the vendor OUI fields shall contain
5
valid serial data.
6
7 6.6.2.15 Extended Transceiver Codes (Address 164)
8
The Extended Transceiver Codes define the electronic or optical interfaces for InfiniBand that are supported
9 by the QSFP transceiver as shown in Table 38.
10
11 Table 38 — Extended Transceiver Code Values
12 Address Bit Description of Transceiver Data
13 InfiniBand Compliance Codes
14 164 7-6 Reserved
15 164 5 IB 4X 850 nm
16 164 4 IB 4X Copper Active
17 164 3 IB 4X Copper Passive
164 2 QDR Speed (10 Gb/s)
18
164 1 DDR Speed (5.0 Gb/s)
19 164 0 SDR Speed (2.5 Gbps)
20
21
22 6.6.2.16 Vendor OUI (Address 165-167)
23 The vendor organizationally unique identifier field (vendor OUI) is a 3-byte field that contains the IEEE
24 Company Identifier for the vendor. A value of all zero in the 3-byte field indicates that the Vendor OUI is
25 unspecified.
26 6.6.2.17 Vendor PN (Address 168-183)
27
28 The vendor part number (vendor PN) is a 16-byte field that contains ASCII characters, left aligned and padded
on the right with ASCII spaces (20h), defining the vendor part number or product name. A value of all zero in
29 the 16-byte field indicates that the vendor PN is unspecified.
30
31 6.6.2.18 Vendor Rev (Address 184-185)
32 The vendor revision number (vendor rev) is a 2-byte field that contains ASCII characters, left aligned and
33 padded on the right with ASCII spaces (20h), defining the vendor’s product revision number. A value of all
34 zero in the field indicates that the vendor Rev is unspecified.
35
36 6.6.2.19 Wavelength (Address 186-187)
37 Nominal transmitter output wavelength at room temperature. 16 bit value with byte 186 as high order byte and
38 byte 187 as low order byte. The laser wavelength is equal to the 16 bit integer value divided by 20 in nm (units
39 of 0.05nm). This resolution should be adequate to cover all relevant wavelengths yet provide enough
40 resolution for all expected DWDM applications. For accurate representation of controlled wavelength
applications, this value should represent the center of the guaranteed wavelength range.
41
42 6.6.2.20 Wavelength Tolerance (Address 188-189)
43
The guaranteed +/- range of transmitter output wavelength under all normal operating conditions. 16 bit value
44 with byte 188 as high order byte and byte 189 as low order byte. The laser wavelength is equal to the 16 bit
45 integer value divided by 200 in nm (units of 0.005nm). Thus, the following two examples:
46
Example 1:
47
48 10GBASE-LR Wavelength Range = 1260 to 1355 nm
49 Nominal Wavelength in bytes 186 - 187 = 1307.5 nm.

QSFP Public Specification 65

1 Represented as INT(1307.5 nm * 20) = 26150 = 6626h
Wavelength Tolerance in bytes 188 - 189 = 47.5nm.
2
Represented as INT(47.5 nm * 200) = 9500 = 251Ch
3
4 Example 2:
5 ITU-T Grid Wavelength = 1534.25 nm (195.4 THz) with 0.236 nm ( 30 GHz) Tolerance
6 Nominal Wavelength in bytes 186 - 187 = 1534.25 nm.
7 Represented as INT(1534.25nm * 20) = 30685 = 77DDh
Wavelength Tolerance in bytes 188 - 189 = 0.236 nm.
8
Represented as INT(0.236 nm * 200) = 47 = 002Fh
9
10 6.6.2.21 Max Case Temp (Address 190)
11
Allows specification of a maximum case temperature other than the QSFP standard of 70C. Maximum case
12 temperature is an 8-bit value in Degrees C.
13
14 6.6.2.22 CC_BASE (Address 191)
15 The check code is a one byte code that can be used to verify that the first 64 bytes of serial information in the
16 QSFP transceiver is valid. The check code shall be the low order 8 bits of the sum of the contents of all the
17 bytes from byte 128 to byte 190, inclusive.
18
19 6.6.2.23 Options (Address 192-195)
20 The bits in the option field shall specify the options implemented in the QSFP transceiver as described in
21 Table 39.
22
Table 39 — Option Values
23
24 Address bit Description of option
192-193 7-0 Reserved
25 194 7-4 Reserved
26 194 3 Rx_Squelch Disable implemented, coded 1 if implemented, else 0
27 194 2 Rx_Output Disable capable: coded 1 if implemented, else 0.
28 194 1 Tx Squelch Disable implemented: coded 1 if implemented, else 0
194 0 Tx Squelch implemented: coded 1 if implemented, else 0
29 195 7 Memory page 02 provided: coded 1 if implemented, else 0.
30 195 6 Memory page 01 provided: coded 1 if implemented, else 0.
31 RATE_SELECT is implemented. If the bit is set to 1 then active control of the rate select bits
32 in the upper memory table is required to change rates. If the bit is set to 0, no control of the
33 rate select bits in the upper memory table is required. In all cases, compliance with multiple
rate standards should be determined by Transceiver Codes in Bytes 132, 133, 134 and 135
34 195 5 of Page 00h.
35 195 4 TX_DISABLE is implemented and disables the serial output.
36 195 3 TX_FAULT signal implemented, coded 1 if implemented, else 0
37 195 2 Tx Squelch implemented to reduce OMA coded 0,implemented to reduce Pave coded 1.
38 195 1 Loss of Signal implemented, coded 1 if implemented, else 0
195 0 Reserved
39
40
41 6.6.2.24 Vendor SN (Address 196-211)
42 The vendor serial number (vendor SN) is a 16-character field that contains ASCII characters, left aligned and
43 padded on the right with ASCII spaces (20h), defining the vendor’s serial number for the QSFP transceiver. A
44 value of all zero in the 16-byte field indicates that the vendor SN is unspecified.
45
46 6.6.2.25 Date Code (Address 212-219)
47 The date code is an 8-byte field that contains the vendor’s date code in ASCII characters. The date code is
48 mandatory. The date code shall be in the format specified by Table 40.
49

QSFP Public Specification 66

1 Table 40 — Date Codes
2 Address Description of field
3 212-213 ASCII code, two low order digits of year. (00 = 2000).
4 214-215 ASCII code, digits of month (01 = Jan through 12 = Dec)
5 216-217 ASCII code, day of month (01 - 31)
218-219 ASCII code, vendor specific lot code, may be blank
6
7
8 6.6.2.26 Diagnostic Monitoring Type (Address 220)
9 “Diagnostic Monitoring Type” is a 1-byte field with 8 single bit indicators describing how diagnostic monitoring
10 is implemented in the particular QSFP transceiver. Bit indicators are shown in Table 41.
11 Digital Diagnostic Monitors monitor received power, bias current, supply voltage and temperature.
12 Additionally, alarm and warning thresholds must be written as specified in this document. Auxiliary monitoring
13 fields are optional extensions to Digital Diagnostics.
14 All digital monitoring values must be internally calibrated and reported in the units defined in this document.
15 Bit 3 indicates whether the received power measurement represents average input optical power or OMA. If
16 the bit is set, average power is monitored. If not, OMA is monitored.
17
18 Table 41 — Diagnostic Monitoring Type
19 Address Bits Description
20 220 7-5 Reserved
21 220 4 Module Respond to FEC BER, 0 = No BER Support, 1=BER Support
22 220 3 Received power measurement type, 0 = OMA, 1 = Average Power
23 220 2 Reserved
24 220 1-0 Reserved
25
26 6.6.2.27 Enhanced Options (Address 221)
27 The format of the Enhanced Options byte are shown in Table 42. The use of the Enhanced Options field is
28 defined in Clause 6.6.1.7. The state where the Rate Select declaration bits both have a value of 1 is reserved
29 and should not be used.
30
31 Table 42 — Enhanced Options (byte 221))
32 Address Bit Description
33 221 7-4 Reserved
221 3 Rate Selection Declaration: When this declaration bit is 0, the module does not support rate
34 selection. When this declaration bit is 1, rate selection is implemented using Extended Rate
35 Selection. See 6.6.1.7.2.
36 221 2 Application Select Table Declaration. When this declaration bit is 1, the module supports rate
37 selection using application select table mechanism. When this declaration bit is 0, the module
does not support application select and page 01 does not exist.
38
39 221 1-0 reserved
40
41 6.6.2.28 CC_EXT (Address 223)
42 The check code is a one-byte code that can be used to verify that the first 32 bytes of extended serial
43 information in the QSFP transceiver is valid. The check code shall be the low order 8 bits of the sum of the
44 contents of all the bytes from byte 192 to byte 222, inclusive.
45
46 6.6.2.29 Vendor Specific (Address 224-255)
47 This area may contain vendor specific information, which can be read from the QSFP Transceiver. The data is
48 read only. Bytes 224-255 of Page 00h may be used for Vendor Specific ID functions.
49

QSFP Public Specification 67

1 6.6.3 Upper Memory Map Page 01h
2 The format of Page 01h is defined in Table 43.
3
4 Table 43 — Application Select Table (Page 01)
5 Byte Bit range Name of Field Description
6 128 7-0 CC_APPS Check code for the AST; the check code shall be the
7 low order 8 bits of the sum of the contents of all the
8 bytes from byte 129 to byte 255, inclusive.
9 129 7,6 Reserved
10 129 5-0 AST Table Length, TL A 6-bit binary number, TL, specifies how many
application table entries are defined in bytes 130-255
11
addresses. TL is valid between 0 (1 entry) and 62 (for
12 a total of 63 entries).
13
130, 131 7-0, 7-0 Application code 0 Definition of first application supported
14
15 … Other table entries
16 130+2*TL, 7-0, 7-0 Application code TL Definition of last application supported
17 131+2*TL
18
19 Table 44 — Application Code Structure
20 Low order Byte High order Byte
21 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
22 reserved category variant
23
24
6.6.4 User Writable and Vendor Specific Memory
25
26 Page 02 is optionally provided as user writable EEPROM. The host system may read or write this memory for
27 any purpose. If bit 4 of Page 00 byte 129 is set, however, the first 10 bytes of Table 02h, bytes128-137 will be
used to store the CLEI code for the module.
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49

QSFP Public Specification 68

1 6.6.5 Upper Memory Page 03h
2 The upper memory map page 03h contains module thresholds, channel thresholds and masks, and optional
3 channel controls. These are shown in Table 45 and described in detail in Clause 6.6.1, Clause 6.6.1.6 and
4 Clause 6.6.1.4.
5
Table 45 — Upper Memory Map Page 03h
6
7 Byte Address Description Type
128-175 Module Thresholds (48 Bytes) Read-Only
8
176-223 Channel Thresholds (48 Bytes) Read-Only
9 224-225 Reserved (2 Bytes) Read-Only
10 226-239 Vendor Specific Channel Controls (14 Bytes) Read/Write
11 240-241 Optional Channel Controls (2 Bytes) Read/Write
12 242-253 Channel Monitor Masks (12 Bytes) Read/Write
13 254-255 Reserved (2 Bytes) Read/Write
14
15 6.6.5.1 Module and Channel Thresholds
16 Each monitor value has a corresponding high alarm, low alarm, high warning and low warning threshold.
17 These factory-preset values allow the user to determine when a particular value is outside of “normal” limits as
18 determined by the transceiver manufacturer. It is assumed that these values will vary with different
19 technologies and different implementations. These values are stored in read-only memory in bytes 128-223
20 of the upper memory page 03h as shown in Table 46.
21 The values reported in the Alarm and Warning Thresholds area may be typical values at some chosen
22 nominal operating conditions and may be temperature compensated or otherwise adjusted when setting
23 warning and/or alarm flags. Any threshold compensation or adjustment is vendor specific and optional. Refer
to the vendor’s data sheet for use of alarm and warning thresholds.
24
25 Table 46 — Module and Channel Thresholds
26
Address # Bytes Name Description
27
128-129 2 Temp High Alarm MSB at low address
28
130-131 2 Temp Low Alarm MSB at low address
29 132-133 2 Temp High Warning MSB at low address
30 134-135 2 Temp Low Warning MSB at low address
31 136-143 8 Reserved
32 144-145 2 Vcc High Alarm MSB at low address
33 146-147 2 Vcc Low Alarm MSB at low address
34 148-149 2 Vcc High Warning MSB at low address
35 150-151 2 Vcc Low Warning MSB at low address
152-175 14 Reserved
36
176-177 2 RX Power High Alarm MSB at low address
37 178-179 2 RX Power Low Alarm MSB at low address
38 180-181 2 RX Power High Warning MSB at low address
39 182-183 2 RX Power Low Warning MSB at low address
40 184-185 2 TX Bias High Alarm MSB at low address
41 186-187 2 TX Bias Low Alarm MSB at low address
42 188-189 2 TX Bias High Warning MSB at low address
43 190-191 2 TX Bias Low Warning MSB at low address
192-199 8 Reserved Reserved thresholds for channel parameter set 3
44 200-207 8 Reserved Reserved thresholds for channel parameter set 4
45 208-215 8 Reserved Reserved thresholds for channel parameter set 5
46 216-223 8 Reserved Reserved thresholds for channel parameter set 6
47
48
49

QSFP Public Specification 69

1 6.6.5.2 Optional Channel Controls
2 Upper Memory Page Control Bits are defined in Table 47.
3
4 Table 47 — Optional Channel Controls
5 Byte Bit Name Description
6 240 7 Rx4_SQ_Disable Rx Squelch Disable, channel 4 (optional)
7 6 Rx3_SQ_Disable Rx Squelch Disable, channel 3 (optional)
8 5 Rx2_SQ_Disable Rx Squelch Disable, channel 2 (optional)
9 4 Rx1_SQ_Disable Rx Squelch Disable, channel 1 (optional)
10 3 Tx4_SQ_Disable Tx Squelch Disable, channel 4 (optional)
2 Tx3_SQ_Disable Tx Squelch Disable, channel 3 (optional)
11
1 Tx2_SQ_Disable Tx Squelch Disable, channel 2 (optional)
12 0 Tx1_SQ_Disable Tx Squelch Disable, channel 1 (optional)
13 241 7 Rx4_Output_Disable Rx Output Disable, channel 4 (optional)
14 6 Rx3_Output_Disable Rx Output Disable, channel 3 (optional)
15 5 Rx2_Output_Disable Rx Output Disable, channel 2 (optional)
16 4 Rx1_Output_Disable Rx Output Disable, channel 1 (optional)
17 3 Reserved
18 2 Reserved
1 Reserved
19
0 Reserved
20
21 Squelch and output control functionality is optional; if implemented, squelch and output disable is controlled
22 for each channel using bytes 240 and 241 of page 03h. Squelch is normally operational as described in
23 Clause 3.1.3, High Speed Electrical Specification. Writing a “1” in the Squelch Disable register (byte 240,
24 page 03h) disables the squelch for the associated channel. Writing a “1” in the Output Disable register (byte
25 241, page 03h) squelches the output of the associated channel. When a “1” is written in both registers for a
channel, the associated output is disabled. The registers read all “0”s upon power-up.
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49

QSFP Public Specification 70

1 6.6.5.3 Channel Monitor Masks
2 The Masking Bits for the Channel Monitor Functions are defined in Table 48.
3
4 Table 48 — Channel Monitor Masks
5 Byte Bit Name Description
6 242 7 M-Rx1 Power High Alarm Masking bit for high RX Power alarm, channel 1
7 6 M-Rx1 Power Low Alarm Masking bit for low RX Power alarm, channel 1
8 5 M-Rx1 Power High Warning Masking bit for high RX Power warning, channel 1
9 4 M-Rx1 Power Low Warning Masking bit for low RX Power warning, channel 1
3 M-Rx2 Power High Alarm Masking bit for high RX Power alarm, channel 2
10
2 M-Rx2 Power Low Alarm Masking bit for low RX Power alarm, channel 2
11 1 M-Rx2 Power High Warning Masking bit for high RX Power warning, channel 2
12 0 M-Rx2 Power Low Warning Masking bit for low RX Power warning, channel 2
13 243 7 M-Rx3 Power High Alarm Masking bit for high RX Power alarm, channel 3
14 6 M-Rx3 Power Low Alarm Masking bit for low RX Power alarm, channel 3
15 5 M-Rx3 Power High Warning Masking bit for high RX Power warning, channel 3
16 4 M-Rx3 Power Low Warning Masking bit for low RX Power warning, channel 3
17 3 M-Rx4 Power High Alarm Masking bit for high RX Power alarm, channel 4
2 M-Rx4 Power Low Alarm Masking bit for low RX Power alarm, channel 4
18
1 M-Rx4 Power High Warning Masking bit for high RX Power warning, channel 4
19 0 M-Rx4 Power Low Warning Masking bit for low RX Power warning, channel 4
20 244 7 M-Tx1 Bias High Alarm Masking bit for high TX Bias alarm, channel 1
21 6 M-Tx1 Bias Low Alarm Masking bit for low TX Bias alarm, channel 1
22 5 M-Tx1 Bias High Warning Masking bit for high TX Bias warning, channel 1
23 4 M-Tx1 Bias Low Warning Masking bit for low TX Bias warning, channel 1
24 3 M-Tx2 Bias High Alarm Masking bit for high TX Bias alarm, channel 2
2 M-Tx2 Bias Low Alarm Masking bit for low TX Bias alarm, channel 2
25
1 M-Tx2 Bias High Warning Masking bit for high TX Bias warning, channel 2
26 0 M-Tx2 Bias Low Warning Masking bit for low TX Bias warning, channel 2
27 245 7 M-Tx3 Bias High Alarm Masking bit for high TX Bias alarm, channel 3
28 6 M-Tx3 Bias Low Alarm Masking bit for low TX Bias alarm, channel 3
29 5 M-Tx3 Bias High Warning Masking bit for high TX Bias warning, channel 3
30 4 M-Tx3 Bias Low Warning Masking bit for low TX Bias warning, channel 3
31 3 M-Tx4 Bias High Alarm Masking bit for high TX Bias alarm, channel 4
32 2 M-Tx4 Bias Low Alarm Masking bit for low TX Bias alarm, channel 4
1 M-Tx4 Bias High Warning Masking bit for high TX Bias warning, channel 4
33
0 M-Tx4 Bias Low Warning Masking bit for low TX Bias warning, channel 4
34 246-247 All Reserved Reserved channel monitor masks, set 3
35 248-249 All Reserved Reserved channel monitor masks, set 4
36 250-251 All Reserved Reserved channel monitor masks, set 5
37 252-253 All Reserved Reserved channel monitor masks, set 6
38
39
40
41
42
43
44
45
46
47
48
49

QSFP Public Specification 71