An Update on IEEE 1149.

6 – Successes and Issues

Bill Eklow

Cisco Systems, Inc., San Jose CA

The IEEE 1149.6 standard is able to overcome these

Abstract effects by placing analog, edge detectors (test receivers)
This paper will look at IEEE 1149.6, two years after on each of the two differential inputs. The test receivers
being approved as an IEEE standard. The paper was can reliably capture boundary scan signals which are
written based on: interviews with companies that have driven through the capacitor (and subsequently decay
implemented IEEE 1149.6 (either in hardware or over time). By placing test receivers on each of the input
software tools), emails from the 1149.6 distribution list, pins of the differential receiver, coverage and fault
working group meetings and previous papers. The paper isolation are improved over the “analog” approach of
will begin with a review of the 1149.6 standard, including placing boundary scan cells “behind” the functional driver
objectives of the standard and what the standard was not and receiver. Note: The standard also works with
meant to do. It will then present some initial findings and transformer coupled nets, such as found in Token Ring
concerns, prior to release of the standard. The paper will applications, and other connection schemes where the
also discuss the adoption of the standard and issues that connection appears to be a passive, high-pass filter.
have been discovered by companies trying to implement Examples of an 1149.6 driver and receiver are shown in
the standard. Figure 1 [3] and Figure 2 [3] respectively.

1. Introduction
Mission
The IEEE 1149.6 standard [1] was approved and released 0 Data
Shift out
in March of 2003. The standard was written to address 0
0 1

test issues with respect to high speed serial data links. 1

1
C U Mode
These high speed, serial data links are characterized by: AC Mode AC Test Signal
Shift in Insertion, per driver
AC-coupling (adding a series capacitor in the data path ShiftDR
UpdateDR Mode AC Mode Train/Pulse
between the driver and the receiver), and differential ClockDR
1149.1 Bypass 0 X X
signaling. Nets which are “AC-coupled” render “static” Train/Pulse 1149.1 Extest 1 0 X

(IEEE 1149.1[2]) boundary-scan techniques ineffective, Extest_Pulse 1 1 0

Extest_Train 1 1 1
because the capacitor that is introduced into the signaling RTI State
AC Test Signal
(distributed to all AC
path causes the driven boundary-scan signal to decay over TCK drivers) AC Test Signal
Generator (near TAP)
time. This creates time constraints on the boundary-scan
network that violate the IEEE 1149.1 boundary-scan
Figure 1: 1149.6 Driver
standard. Differential signaling associated with high
speed nets also creates coverage and diagnosis issues for
boundary-scan testing. Users of IEEE 1149.1 generally
address the issue of differential signaling in “DC” The objectives of the working group were: to provide an
environments by placing the boundary-scan cell on the equal or better level of fault coverage and fault isolation
output of the functional, differential receiver. This is as an IEEE 1149.1 device in a “DC-coupled”
referred to as the “analog” model in the 1149.1 standard. environment; to be compatible with IEEE 1149.1
This approach compromises both test coverage and (including minimal impact to 1149.1 tools); to provide
diagnostic capabilities. Opens on either of the inputs may minimal performance and overhead impact. The standard
not be detected due to the fault tolerant nature of the did not try to address “parametric” or speed related issues
differential network. In addition, several types of faults (i.e. wrong value resistors or capacitors, bit errors caused
on either of the two input signals could create the same by defects in functional logic). The working group
failure signature (i.e. a stuck high on the positive input limited the scope of the standard to detecting and
and a stuck low on the negative input will both generate a diagnosing “structural” faults (shorts, opens and stuck-
stuck high value in the boundary-scan input cell. These at’s) which occur in a typical 1149.1 environment.
issues are documented in more detail in [3] and While separate tests receivers provide better coverage and
subsequently in [4] and [8]. fault isolation for differential signaling, noise immunity is
compromised by treating each of the differential inputs as

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 a single-ended signal. Noise was a significant concern of verify the logic in the standard. Fourth, test equipment
the working group. Several steps were taken by the supports the standard.
working group to minimize the effect of noise on the
single-ended test receiver, including: using hysteresis to There were several papers that have been presented with
filter some of the effects of the noise and decreasing the regards to 1149.6. Notably [3], [4], [5], [6], [7], [8], [9]
time between when the boundary-scan signal is driven have been presented at ITC, DATE, ITSW. These papers
and when it is loaded from the test receiver to the concentrated on technical details of 1149.6 and
boundary register. implementation experiences. The papers confirmed the
feasibility of 1149.6, especially in the areas of test
coverage, performance and real estate impact. Both
Duzivek and Vandivier confirmed that the real estate and
performance penalties were not unreasonable. Both
papers were also significant in that they specifically
documented test coverage and fault isolation capabilities
of 1149.6 (results in both papers, and working group
simulation results were all consistent with each other).
One noteworthy item was the effect of shorts (Transmitter
to Transmitter and Receiver to Receiver) on fault
diagnosis. In this case, unlike 1149.1, fault diagnosis was
not intuitive. The captured value of both sets of test
receivers must be examined for both low to high and high
to low transitions. In some cases, the effect of the short
was evident; however, in other cases the nets did not
appear to react as would be expected [5]. This is an issue
that may challenge ATPG pattern generation for 1149.6
boundary scan testing.
In addition to the papers described above, at least 2
tutorials have been presented in the last year (at ITC and
ATS) which focus specifically and solely on 1149.6.
Several other tutorials cover 1149.6 as part of the tutorial,
Figure 2: 1149.6 Receiver although 1149.6 is not the main focus of these tutorials.
There has been one article published in IEEE Design &
Test and at least one boundary-scan book now has a
Performance and real estate were also concerns of the section dedicated to 1149.6 [12]. This significant amount
working group (in addition to noise immunity). While of socialization should ensure enough dissemination of
Vandivier [5] and Duzivek [6] seemed to show that these information and should generate enough interest to drive
were not an issue, there was still some concern amongst the continued advancement of the standard over the next
the working group. This paper will discuss how these several years.
concerns have played out in “real life” so far and will
address other issues that were not foreseen by the working 2.2 Hardware Deployment and Issues
group. The paper will not focus on the details of the Several IEEE 1149.6 compliant devices are already
1149.6 standard but will rather focus on the available and several more are in development. This is
implementation of the standard thus far. significant given the additional complexity of 1149.6.
The analog test receiver, which is critical to the operation
2. Initial Adoption of the Standard of the standard, is significantly different and much more
complex than the logic described in the 1149.1 standard.
2.1 Socialization In addition, given the performance requirements of the
As with most standards, adoption of the 1149.6 standard high speed I/O’s that the 1149.6 logic will service,
did not come immediately following its release. Adoption integration of the 1149.6 test logic can potentially have a
usually proceeds in four phases. First the working group much more significant impact on device performance than
continues to socialize the standard. Papers are submitted, 1149.1.
tutorials are given, articles are written in technical
publications and companies are solicited on an individual The timing of the standard was optimal/lucky in that the
basis. Second, chips are developed based on the standard industry was in the process of making a change to 90nm
document. Third, tools are developed to help insert and technology and therefore needed to re-characterize the I/O
logic. Characterization of I/O’s is a significant process

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 and could have potentially become a bottleneck to (still mandatory on 1149.6). However, in the case of an
releasing components on time. Component suppliers 1149.1 driver and an 1149.6 receiver, the variability in the
were more willing to integrate 1149.6 into their I/O’s common mode voltage and the variability of the
since they were going to have to incur the cost of re- termination voltage may be greater than the hysteresis of
characterization anyway. Had the standard been released the test receiver (this is especially true of LVDS logic).
a year later, it would have been much more difficult to get In this case the test receiver cannot be guaranteed to
the 1149.6 logic integrated into the ASIC’s as quickly as capture the correct value in response to the EXTEST
it was. Most ASIC suppliers have now integrated 1149.6 instruction. Even if the variability doesn’t exceed the
on 90nm technology parts. In addition to ASIC’s, several calculated hysteresis value, it may reduce the noise
off-the-shelf SERDES parts have been released with margin to the point that operation in a noisy board test
1149.6 support. Also, at least one FPGA supplier is also environment is unreliable. One attempt to try to get
working on adding 1149.6 compliant I/O’s to its next around this problem has been to try to recover the
generation FPGA’s. common mode value from the inputs at the receiver. On
one device where this “dynamic threshold detection” was
Feedback from the component vendors confirmed that implemented most defects could be reliably detected.
real estate and performance were not severely impacted However, in this case, it was not possible to detect a
by the additional of the 1149.6 test logic. Real estate, shorted capacitor when the device was AC-coupled.
however, is still a potential issue for devices which are Simulation results also indicate that some defect
I/O dominant (Note that 1149.6 does consume a conditions may cause erroneous recovery that may, in
significant amount of area with respect to the SERDES fact, prevent detection of those defects (in a DC-coupled
logic, however, this usually does not represent a mode as well). At this point, adding a third boundary
significant percentage of the overall real estate in most scan cell to the output of the functional receiver is the best
devices). solution that the working group can suggest.
Understanding what was required by the standard was the 2.2.2 Documentation Issues with the Standard
most significant issue for vendors working on their first
1149.6 design. Most said that the standard was difficult The second significant issue that was discovered came
about as part of a thorough review of the standard
to understand. However, after implementing the test logic
document. Bill Bruce identified issues with Figure 48
on one or two designs, the implementation became much
(page 58) and Figure 49 (page 59) in the standard
more intuitive. Note that in most cases, the test logic
document. The figures were included to help clarify Rule
needed to be “hand inserted and verified” since there were 6.2.3.1d and Recommendation 6.2.3.2b. Rule 6.2.3.1d
no insertion and verification tools initially. Verification states: Whenever a test receiver is operating in the edge-
for the analog part of 1149.6 is still not available. detection mode on an AC input signal, the test receiver
Three significant issues were discovered as component output shall be cleared of prior history at the time
suppliers began implementing the test logic and more between exiting the Shift-DR TAP Controller state and
scrutiny was given to the standard. The first issue occurs before entering the Update-DR TAP Controller state.
when an 1149.1 EXTEST instruction is used to test a Recommendation 6.2.3.2b states: In order to minimize
network with an 1149.1 driver and an 1149.6 receiver. the time during which noise on an input pin might be
The second issue involves a documentation mistake in the falsely detected as a valid input, the prior history should
standard. The third issue involves a general be cleared at the rising edge of TCK in both Exit1-DR
misconception on the part of the industry and a mis- and Exit2-DR TAP controller states. Very briefly, the
communication (not enough emphasis) concerning the intent of the rule and recommendation is that the
requirement for 1149.6 on differential networks which hysteretic memory be preloaded as close to when data is
may not be AC-coupled. driven on the net, in order to minimize the effect of noise
on the “captured data”.
2.2.1 Voltage Margin vs. Hysteresis The two figures (Figure 48 and 49) are similar, except
During the early stages of adoption it was expected that Figure 49 uses a latch-based initialization for the
there would initially be several instances where 1149.1 hysteretic memory (shown in the center right of the
and 1149.6 compliant components would be figure) whereas Figure 48 uses a flip-flop based
interconnected. The working group addressed the issue of initialization. Figure 48 is included as Figure 2 in this
interconnecting 1149.1 and 1149.6 parts on AC-coupled paper. Figure 49 is shown as Figure 3 (shown below).
networks (see A.3.4.3 in the 1149.6 standard). The Three potential problems were discovered through a
working group did not initially believe that there would careful examination of these figures. First, a race
be any issues with 1149.1 and 1149.6 components condition occurs during the transition from the Capture-
interconnected in a DC-coupled environment. In this DR state to the Exit1-DR state. Looking at Figure 2, a
case, the 1149.6 component could be put in an 1149.1 rising TCK in the Capture-DR state will cause a rising
compliant mode by executing the EXTEST instruction

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 edge on the ClockDR signal going to the Capture FF. In
addition, with TMS=1, the rising edge of TCK will also
cause a transition from the Capture-DR state to the Exit1-
DR state. This will cause the OR-AND-OR circuit to
drive a rising edge and clock the Hyst Mem. The result is
the Capture FF, which provides data for the Hyst. Mem. is
being clocked at the same time as the Hyst. Mem., which
is providing data for the Capture FF. Data which is
driven on to the net during the Update-DR state is used to
set or clear the Hyst. Mem. Given the scenario described
above, if the ClockDR signal arrives before the Hyst.
Mem. clock, the state of the net that was loaded into the
Hyst. Mem. is captured into the Capture FF. This is the
expected behavior. However, if the Hyst. Mem. clock
arrives before ClockDR, the data from the Capture FF is
loaded into the Hyst. Mem. and the state of the net is lost.
One other side effect of the OR-AND-OR gating scheme
occurs during the transition from Exit2-DR to Update-DR
(the second problem). Assuming that the rising TCK
edge will arrive before the Exit2-DR has been deasserted,
the circuit will generate a glitch. The effect of the glitch
should be inconsequential, but nevertheless, is poor
design practice. The resulting glitch was confirmed by Figure 3: 1149.6 Receiver (Latch-based)
National Semiconductor as part of the verification and
implementation of their first 1149.6 compliant device. 2.2.3 Differential vs. AC-coupled
To address these two issues, a transparent latch was added While there has been strong adoption of 1149.6 for
to allow the gated signals ((EXTEST_TRAIN OR SERDES logic, which is typically AC-coupled, many
EXTEST_PULSE) AND (EXIT1-DR OR EXIT2-DR)) to suppliers have not embedded the 1149.6 test logic on
change only when TCK is low. The transparent latch I/O’s which are differential, but are not normally AC-
fixes both the potential glitch that occurs when TCK rises coupled. Discussions with several ASIC suppliers
before EXIT-DR goes away, and also fixes the race revealed that the “differential” part of the standard was
condition (the Hyst. Mem. clock occurs one TCK later – not sufficiently communicated and understood. Most
transitioning out of the Exit1-DR state instead of into the suppliers focused on the AC-coupled part of the standard
Exit1-DR state). The new version of Figures 48 and 49 and hence spent most of their effort incorporating 1149.6
along with resulting timing diagram are shown as Figures into high speed SERDES at the expense of logic such as
4 and 5 below. In addition to the latch (shown after the DDR, QDR, SPI-4 and Hypertransport which are
AND gate in the lower part of the figure), TMS was also primarily DC-coupled. As is pointed out in the standard,
gated with the EXTEST_TRAIN, EXTEST_PULSE and and earlier in this paper, there are significant coverage
EXIT-DR signals to insure that the Initialization signal and diagnostic issues for differential nets which do not
was generated only on a transition to the UPDATE-DR incorporate 1149.6. Unfortunately, most suppliers clearly
state. understood the issue with AC-coupling (AC-coupling
breaks 1149.1), but did not understand the issues with
differential signaling on DC-coupled nets since there is
nothing “broken” with 1149.1. In addition, now that
90nm technology has moved to the deployment phase, it
will be much more difficult to get the 1149.6 logic

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 Figure 4: 1149.6 Improved Figure 48
Figure 5: 1149.6 Improved Figure 49
integrated into these differential I/O’s which are not AC-
coupled. This will probably be one of the greatest
challenges of the working group going forward. Capture logic associated with the boundary cells, and
their connection to the 1149.6 driver and test receiver.
2.3 CAE Software Adoption and Issues Digital verification is relatively straightforward. Much of
CAE tools perform test logic insertion, verification, the verification is very similar to verification that is
BSDL generation and compliance checking. As is typical currently done for 1149.1. Additional verification
with most standards, software adoption lagged behind involves verifying correct behavior of the TAP, and
hardware by several months. Most tools developers tend proper behavior of the input and output boundary-scan
to wait until there is some level of hardware adoption cells (minus the test receiver) while executing the 1149.6
before beginning to develop tools to help support this specific EXTEST_PULSE and EXTEST_TRAIN
hardware development. As was mentioned, designers of instructions.
“early” devices had to manually insert, verify and test the
There are currently no tools available which verify the
1149.6 logic.
analog characteristics of the test receiver and its
Currently, however, there are 1149.6 insertion and surrounding logic. One analog verification tool is
verification tools available and in development. One tool currently in development and should be completed by the
has already been documented [11]. Most, if not all tools time this paper is presented. Insertion and verification
focus on the “digital” part of 1149.6. The test receiver is tool developers face the same problem as hardware
generally treated as a “black box”. This makes sense designers, difficulty in understanding the standard
since the test receiver is highly integrated into the device (especially the analog portion of the standard).
I/O and is technology dependent. This would make Developers are also challenged by the lack of a standard,
insertion via CAE software very difficult. Current supporting, analog simulation environment. The result is
insertion tools address the TAP and the Update and that most analog verification must be done manually by
the chip developer. In some cases, analog verification

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 consists solely of manually checking the parameters external environment on the operation of the test receiver.
discussed in Section 6 of the standard (Hysteresis values Obviously, the external resistor and capacitor can affect
and correct calculation of high pass vs. low pass filter the operation/performance of the test receiver. The driver
values). technology (LVDS, CML, LVPECL) can also have an
impact on the operation/performance of the test receiver.
There were two BSDL related issues that were identified
Currently, the 1149.6 standard does not allow for the
after the standard was released. This first issue came
description of the board level resistor and capacitor or the
about as insertion and verification tools were being
device technology and characteristics of the driver. This
developed. Rule 7.2.1d specifies documentation of the
precludes any type of verification of the analog
differential I/O that is slightly different from 1149.1. The
parameters at the board level (driver, coupling capacitor,
rule states: “When the output of a mission receiver
termination and receiver). A related issue brought up by
connected to a differential pair is monitored with a
component vendors was that there is a relationship
Boundary-Scan Register cell, then that differential input
between device and board characteristics that can
pin pair shall be documented within a Port Grouping
potentially affect the operation of the 1149.6 circuit. The
attribute of the BSDL description.” In the 1149.1
effect of on board resistors and capacitors has already
standard, differential pins are “grouped” when they are
been seen by at least one component supplier. The
connected to a differential mission receiver which is
working group has not addressed this issue at this time.
operating in the “analog” test mode (that is, a boundary-
This will be a very challenging issue, since the
scan cell is connected to the output of the mission
interdependence of board and chip parameters seems to
receiver). In the 1149.6 standard, the boundary cell
have become much more critical.
connection to the mission receiver is optional but is not
used in most cases since it is redundant with the test
2.4 Board Level Test Tools
receivers. This caused a lengthy discussion amongst the
working group about the semantics of describing the nets 1149.6 board test tools have lagged both hardware and
as single-ended or differential in the boundary-scan CAE development. This tends to be the case with most
context. The 1149.1 standard states that “The optional standards. In essence, the development of test tools is
<grouped port identification> shall be used to identify gated by having working hardware available. Currently,
system I/O signals that have the special characteristic of several standalone, boundary-scan test platforms support
using more than one pin to carry a bit of data…” When test generation for 1149.6 to 1149.6 interconnections.
the boundary-scan cell is removed from the output of the There are much fewer, if any, applications which are
mission receiver (as usually occurs in 1149.6), the rule capable of testing a board with both 1149.1 and 1149.6
above seems to be invalidated. That is, given that a test components. It was noted in [8] that there were several
receiver is already monitoring each pin of the differential issues that needed to be addressed when testing boards
net, and there is no boundary-scan cell on the output of with both 1149.1 and 1149.6. Among some of these
the mission receiver (the single data bit which is using issues were: ATPG for boards with both 1149.6 and
more than one pin to carry its data), the rule would imply 1149.1 logic, timing of driving data from 1149.6 drivers
that the differential pins should not be grouped. This vs. 1149.1 drivers, and diagnosis shorts between 1149.6
semantic discrepancy is traded off by the requirement of and 1149.1 components. At this point in time, there are
verification tools to know that the negative pin of the not enough “real” test cases to determine if there are any
differential pair must share the same “behavior” (as issues with test pattern generation for boards with both
defined by 1149.6) as the positive pin. There would be no 1149.6 and 1149.6 logic. It also remains to be seen how
where else in the BSDL where this would be documented. well the boundary-scan ATPG tools have addressed the
There was also some argument that the two pins could other issues identified in [8] (parameter calculation,
possibly influence each other and, as such, should not be hysteresis loading, driver/driver and receiver/receiver
treated as single ended. This is consistent with results shorts as described above).
from Vandivier. Finally, there was some concern about One significant issue for In-Circuit test comes about when
ATPG tools damaging the receiver and/or driver by an 1149.6 driver is driving a differential signal off-board
attempting to drive both pins to the same state. This (through a connector) with on board coupling. While this
would probably be most likely in an In-Circuit test situation is not likely (in most cases the coupling
environment. This item is still open and will be re- capacitor is place close to the receiver), it represents a
addressed by the working group when it begins work on significant challenge to the capabilities of the tester. In
the next revision of the standard. this case, the tester would have to emulate an 1149.6
The second issue is not a BSDL issue, but more of a receiver. A much more common case, initially, would be
board level documentation issue. The issue came about an 1149.6 driver which is AC-coupled to an 1149.1
during functional device verification (on board). One receiver, where test points were placed on the receiver
difference between 1149.1 and 1149.6 is the impact of side of the capacitor. Placing test points on only one side

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 of the capacitor would represent a significant real estate Thanks to the following people, whose participation in
savings, if the In-Circuit tester were able to support email and personal conversations contributed significantly
1149.6 receiver emulation. In either case, it would be to the content of this paper: Carl Barnhart, Ken Parker,
very difficult for an In-Circuit tester to capture edges as Jeff Rearick, Steve Sunter, Ted Eaton, Ken Filliter, Bill
specified by the 1149.6 standard (including appropriate Aronson, Ivan Duzivek, James Brandt, Bill Bruce, Vivek
use of hysteresis). It remains to be seen, whether this Chickermane, Harry Linzer and Brian Foutz.
capability will be required of In-Circuit testers in the
future. 5. References
[1] IEEE Std 1149.6-2003, IEEE Standard for
3. Conclusions Boundary-Scan Testing of Advanced Digital
The 1149.6 standard progressed from concept to release Networks.
in less than two years. Adoption of 1149.6 has [2] IEEE Std 1149.1-2001, IEEE Standard Test Access
progressed very quickly as well. The standard has been Port and Boundary-Scan Architecture.
well documented in papers, tutorials, articles and even [3] Eklow, Barnhart, Parker, “IEEE 1149.6: A
books. The standard has been used to address high speed, Boundary-Scan Standard for Advanced Digital
serial communication links. Adoption from component Networks”, Proceedings of International Test
vendors in this market sector has been very quick and Conference, 2002, pp. 1056 - 1065.
very high. The timing of the standard release had a lot to [4] Eklow, Barnhart, Parker, “IEEE 1149.6: A
do with the early adoption by component vendors Boundary-Scan Standard for Advanced Digital
(component vendors were moving to 90nm technology Networks”, IEEE Design&Test of Computers,
and the impact on device characterization was not September, 2003, pp. 76 - 82.
significant). Software and tools vendors have lagged but [5] Vandivier, Wahl, Rearick, “First IC Validation of
are now putting several tools in place. Unfortunately, IEEE Std. 1149.6”, Proceedings Of International
adoption of the 1149.6 standard for DC-coupled, Test Conference, 2003.
differential nets has been slow. In fact, at this point the [6] Duzivek, “Design and Implementation of IEEE
standard may have missed the 90nm technology window. 1149.6”, Proceedings Of International Test
It is hoped that the working group will be able to Conference, 2003.
convince component suppliers to implement the standard [7] Eklow, Barnhart, Parker, Rearick, “Testing of AC-
for existing technology, but at a worst case, guarantee that Coupled Board Nets with IEEE 1149.6: Theory and
it is implemented in 65nm technology. Application”, International Test Synthesis
Workshop, 2003.
As adoption grows with a new standard, so too will the [8] Eklow, Barnhart, Ricchetti, Borroz, “IEEE 1149.6 –
number of issues. There have been several issues (which A Practical Perspective”, Proceedings of
have been presented in this paper) that have been or will International Test Conference, 2003, pp. 494 - 502.
need to be addressed by the working group. Thus far, [9] Shaikh, “IEEE Std 1149.6 Implementation for a
there have been no issues that “break” the standard; most XAUI-to-Serial 10-Gbps Transceiver, Proceedings
issues have been related to the 1149.6 standard document of International Test Conference, 2004, pp. 543-550.
itself. The issues of interdependence between component [10] Eklow, “IEEE 1149.6-2003 AC-EXTEST
and board level parameters, voltage tolerances vs. Standard”, Design, Automation and Test in Europe,
hysteresis settings, as well as the documentation issues 2004.
related to hysteretic memory initialization, port grouping [11] Foutz, Chickermane, Linzer, Li, Brown, A System
and requirements for 1149.6 on differential, DC-coupled for Automatic Insertion of 1149.6 Compliant
networks will need to be addressed in the next revision of Boundary Scan, International Test Synthesis
the standard. Workshop, 2005.
[12] K. Parker, The Boundary-Scan Handbook, Third
4. Acknowledgements Edition, Kulwer Academic Publishers, June, 2004.

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