SLAS060F − JANUARY 1995 − REVISED APRIL 2009

features
DW OR N PACKAGE
D Four 8-Bit D/A Converters (TOP VIEW)
D Microprocessor Compatible
D TTL/CMOS Compatible OUTB 1 20 OUTC
OUTA 2 19 OUTD
D Single Supply Operation Possible
VSS VDD
3 18
D CMOS Technology REF 4 17 A0
AGND 5 16 A1
applications DGND 6 15 WR
D Process Control DB7 7 14 DB0
DB6 DB1
D Automatic Test Equipment 8 13
DB5 9 12 DB2
D Automatic Calibration of Large System DB4 10 11 DB3
Parameters, e.g. Gain/Offset

description FK PACKAGE
(TOP VIEW)
The TLC7226C, TLC7226I, and TLC7226M

OUTC
OUTD
OUTB
OUTA
consist of four 8-bit voltage-output digital-to-

V SS
analog converters (DACs) with output buffer
amplifiers and interface logic on a single
3 2 1 20 19
monolithic chip.
REF 4 18 VDD
Separate on-chip latches are provided for each of AGND 5 17 A0
the four DACs. Data is transferred into one of
these data latches through a common 8-bit DGND 6 16 A1
TTL /CMOS-compatible 5-V input port. Control DB7 7 15 WR
inputs A0 and A1 determine which DAC is loaded DB6 8 14 DB0
when WR goes low. The control logic is speed 9 10 11 12 13
compatible with most 8-bit microprocessors.
DB5
DB4
DB3
DB2
DB1
Each DAC includes an output buffer amplifier
capable of sourcing up to 5 mA of output current.
The TLC7226 performance is specified for input reference voltages from 2 V to VDD − 4 V with dual supplies.
The voltage mode configuration of the DACs allows the TLC7226 to be operated from a single power supply
rail at a reference of 10 V.
The TLC7226 is fabricated in a LinBiCMOS process that has been specifically developed to allow high-speed
digital logic circuits and precision analog circuits to be integrated on the same chip. The TLC7226 has a common
8-bit data bus with individual DAC latches. This provides a versatile control architecture for simple interface to
microprocessors. All latch-enable signals are level triggered.
Combining four DACs, four operational amplifiers, and interface logic into either a 0.3-inch wide, 20-terminal
dual-in-line IC (DIP) or a small 20-terminal small-outline IC (SOIC) allows a dramatic reduction in board space
requirements and offers increased reliability in systems using multiple converters. The Leadless Ceramic Chip
Carrier (LCCC) package provides for operation at military temperature range. The pinout is aimed at optimizing
board layout with all of the analog inputs and outputs at one end of the package and all of the digital inputs at
the other.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

LinBiCMOS is a trademark of Texas Instruments.

 

!" # $%&" !#  '%()$!" *!"&+ Copyright  2009, Texas Instruments Incorporated
*%$"# $ " #'&$$!"# '& ",& "&# 
&-!# #"%&"#
#"!*!* .!!"/+ *%$" '$&##0 *&# " &$&##!)/ $)%*&
"&#"0  !)) '!!&"&#+

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SLAS060F − JANUARY 1995 − REVISED APRIL 2009

description (continued)
The TLC7226C is characterized for operation from 0°C to 70°C. The TLC7226I is characterized for operation
from −30°C to 85°C. The TLC7226M is characterized for operation from − 55°C to 125°C.
AVAILABLE OPTIONS
PACKAGE
TA SMALL OUTLINE PLASTIC DIP LCCC
(DW) (N) (FK)
0°C to 70°C TLC7226CDW TLC7226CN —
−30°C to 85°C TLC7226IDW TLC7226IN —
−55°C to 125°C — — TLC7226MFKB

functional block diagram

4
REF
_
2
8 Latch 8 OUTA
DAC A +
A

_
1
8 Latch 8 OUTB
DAC B +
7 −14 8 B
DB0 −DB7

_
20
8 Latch 8 OUTC
DAC C +
C

_
19
8 Latch 8 OUTD
DAC D +
D

15
WR
17 Control
A0 Logic
16
A1

schematic of outputs

EQUIVALENT ANALOG OUTPUT

VDD

Output

450 µA

VSS

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SLAS060F − JANUARY 1995 − REVISED APRIL 2009

Terminal Functions
TERMINAL
I/O DESCRIPTION
NAME NO.†
AGND 5 Analog ground. AGND is the reference and return terminal for the analog signals and supply.
A0, A1 17, 16 I DAC select inputs. The combination of high or low levels select either DACA, DACB, DACC, or DACD.
DGND 6 Digital ground. DGND is the reference and return terminal for the digital signals and supply.
DB0 −DB7 14−7 I Digital DAC data inputs. DB0 −DB7 are the input digital data used for conversion.
OUTA 2 O DACA output. OUTA is the analog output of DACA.
OUTB 1 O DACB output. OUTB is the analog output of DACB.
OUTC 20 O DACC output. OUTC is the analog output of DACC.
OUTD 19 O DACD output. OUTD is the analog output of DACD.
REF 4 I Voltage reference input. The voltage level on REF determines the full scale analog output.
VDD 18 Positive supply voltage input terminal
VSS 3 Negative supply voltage input terminal
WR 15 I Write input. WR selects DAC transparency or latch mode. The selected input latch is transparent when WR
is low.
† Terminal numbers shown are for the DW, N, and FK packages.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VDD: AGND or DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 17 V
VSS‡ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 24 V
Supply voltage range, VSS: AGND or DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −7 V to 0.3 V
Voltage range between AGND and DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −17 V to 17 V
Input voltage range, VI (to DGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VDD + 0.3 V
Reference voltage range: Vref (to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VDD
Vref (to VSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 20 V
Output voltage range, VO (to AGND) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS to VDD
Continuous total power dissipation at (or below) TA = 25°C (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . 500 mW
Operating free-air temperature range, TA: C suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
E suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −30°C to 85°C
M suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Case temperature for 10 seconds: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
‡ The VSS terminal is connected to the substrate and must be tied to the most negative supply voltage applied to the device.
NOTES: 1. Output voltages may be shorted to AGND provided that the power dissipation of the package is not exceeded. Typically short circuit
current to AGND is 60 mA.
2. For operation above TA = 75°C, derate linearly at the rate of 2 mW/°C.

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SLAS060F − JANUARY 1995 − REVISED APRIL 2009

recommended operating conditions

MIN MAX UNIT
Supply voltage, VDD 11.4 16.5 V
Supply voltage, VSS −5.5 0 V
High-level input voltage, VIH 2 V
Low-level input voltage, VIL 0.8 V
Reference voltage, Vref 0 VDD −4 V
Load resistance, RL 2 kΩ
Setup time, address valid before WR↓, tsu(AW) (see Figure 1) VDD = 11.4 V to 16.5 V *0 ns
Setup time, data valid before WR↑, tsu(DW) (see Figure 1) VDD = 11.4 V to 16.5 V *45 ns
Hold time, address valid after WR↑, th(AW) (see Figure 1) VDD = 11.4 V to 16.5 V *0 ns
Hold time, data valid after WR↑, th(DW) (see Figure 1) VDD = 11.4 V to 16.5 V *10 ns
Pulse duration, WR low, tw (see Figure 1) VDD = 11.4 V to 16.5 V *50 ns
C suffix 0 70
Operating free-air temperature, TA I suffix −25 85 °C
C
M suffix −55 125
* This parameter is not tested for M suffix devices.

electrical characteristics over recommended operating free-air temperature range

dual power supply over recommended power supply and reference voltage ranges, AGND = DGND = 0 V
(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
II Input current, digital VI = 0 V or VDD ±1 µA
VI = 0.8 V or 2.4 V, VDD = 16.5 V,
I(DD) Supply current 6 16 mA
VSS = − 5 V, No load
I(SS) Supply current VI = 0.8 V or 2.4 V, No load 4 10 mA
ri(ref) Reference input resistance 2 4 kΩ
Power supply sensitivity ∆VDD = ± 5% 0.01 %/%
C and I suffix 65
All 0s loaded
REF input M suffix *30
Ci Input capacitance All 1s loaded *300 pF
C and I suffix 8
Digital inputs
M suffix *12
* This parameter is not tested for M suffix devices.

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SLAS060F − JANUARY 1995 − REVISED APRIL 2009

operating characteristics over recommended operating free-air temperature range

dual power supply over recommended power supply and reference voltage ranges, AGND = DGND = 0 V
(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Slew rate *2.5 V•µs
Positive full scale *5
Settling time to 1/2 LSB Vref = 10 V µss
Negative full scale *7
Resolution 8 bits
Total unadjusted error ±2 LSB
Linearity error Differential/integral ±1 LSB
VDD = 15 V ± 5%, Vref = 10 V
Full-scale error ±2 LSB
Gain error ± 0.25 LSB
Full scale VDD = 14 V to 16.5 V, Vref = 10 V ± 20 ppm/°C
Temperature coefficient of gain
Zero-code error ± 50 µV/°C
Zero-code error ± 20 ± 80 mV
Digital crosstalk glitch impulse area Vref = 0 50 nV•s
* This parameter is not tested for M suffix devices.

single power supply, VDD = 14.25 V to 15.75 V, VSS = AGND = DGND = 0 V, Vref = 10 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Supply current, IDD VI = 0.8 V or 2.4 V, No load 5 13 mA
Slew rate *2 V•µs
Positive full scale *5
Settling time to 1/2 LSB µss
Negative full scale *20
Resolution 8 bits
Total unadjusted error ±2 LSB
Full-scale error ±2 LSB
Full scale VDD = 14 V to 16.5 V, Vref = 10 V ± 20 ppm/°C
Temperature coefficient of gain
Zero-code error ± 50 µV/°C
Linearity error Differential ±1 LSB
Digital crosstalk-glitch impulse area 50 nV•s
* This parameter is not tested for M suffix devices.

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SLAS060F − JANUARY 1995 − REVISED APRIL 2009

PARAMETER MEASUREMENT INFORMATION

tsu(DW)
VDD
Data
0V
th(DW)

VDD
Address
0V
th(AW)
tsu(AW)
tw
VDD

WR 0V
NOTES: A. tr = tf = 20 ns over VDD range.
B. The timing measurement reference level is equal to VIH + VIL
divided by 2.
C. The selected input latch is transparent while WR is low. Invalid
data during this time can cause erroneous outputs.

Figure 1. Write-Cycle Voltage Waveforms

TYPICAL CHARACTERISTICS

OUTPUT CURRENT OUTPUT CURRENT (SINK)

vs vs
OUTPUT VOLTAGE OUTPUT VOLTAGE
200 700
TA = 25°C
VDD = 15 V VDD = 15 V
150 600
Source Current
I O − Output Current (Sink) − µ A

Short-Circuit
100
I O − Output Current − mA

Limiting 500
VSS = − 5 V
50
400
VSS = 0
0
300
−0.1

TA = 25°C 200
−0.2 VSS = − 5 V
Digital In = 0 V
100
−0.3
Sinking
Current Source
−0.4 0
−2 −1 0 1 2 0 1 2 3 4 5 6 7 8 9 10
VO − Output Voltage − V VO − Output Voltage − V

Figure 2 Figure 3

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SLAS060F − JANUARY 1995 − REVISED APRIL 2009

PRINCIPLES OF OPERATION

AGND bias for direct bipolar output operation

The TLC7226 can be used in bipolar operation without adding more external operational amplifiers as shown
in Figure 4 by biasing AGND to VSS. This configuration provides an excellent method for providing a direct
bipolar output with no additional components. The transfer values are shown in Table 1.
REF (Vref = 5 V) VDD
4 18
TLC7226‡

_ OUT
2 Output range
AGND DAC A +
(5 V to − 5 V)
5

3 6
VSS DGND

−5 V
‡ Digital inputs omitted for clarity.

Figure 4. AGND Bias for Direct Bipolar Operation

Table 1. Bipolar (Offset Binary) Code

DAC LATCH CONTENTS
ANALOG OUTPUT
MSB LSB

1111 1111 )V ǒ Ǔ
127
ref 128

1000 0001 )V ǒ Ǔ
1
ref 128
1000 0000 0V

0111 1111 *V ǒ Ǔ
1
ref 128

0000 0001 * V ǒ127Ǔ

ref 128

0000 0000 –V ǒ128Ǔ + * V

ref 128 ref

AGND bias for positive output offset

The TLC7226 AGND terminal can be biased above or below the system ground terminal, DGND, to provide an
offset analog output voltage level. Figure 5 shows a circuit configuration to achieve this for channel A of the
TLC7226. The output voltage, VO, at OUTA can be expressed as:

V
O
+V
BIAS
)D
A
ǒVIǓ (1)

where DA is a fractional representation of the digital input word (0 ≤ D ≤ 255/256).

Increasing AGND above system GND reduces the output range. VDD − Vref must be at least 4 V to ensure
specified operation. Since the AGND terminal is common to all four DACs, this method biases up the output
voltages of all the DACs in the TLC7226. Supply voltages VDD and VSS for the TLC7226 should be referenced
to DGND.

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SLAS060F − JANUARY 1995 − REVISED APRIL 2009

PRINCIPLES OF OPERATION

AGND bias for positive output offset (continued)

Vref VDD
4 18
TLC7226†
VI
_
2 OUTA
AGND DAC A +
5

Vbias 3 6
VSS DGND

† Digital inputs omitted for clarity.

Figure 5. AGND Bias Circuit

interface logic information

Address lines A0 and A1 select which DAC accepts data from the input port. Table 2 shows the operations of
the four DACs. Figure 6 shows the input control logic. When the WR signal is low, the input latches of the
selected DAC are transparent and the output responds to activity on the data bus. The data is latched into the
addressed DAC latch on the rising edge of WR. While WR is high, the analog outputs remain at the value
corresponding to the data held in their respective latches.

Table 2. Function Table

CONTROL INPUTS
OPERATION
WR A1 A0
H X X No operation
Device not selected
L L L DAC A transparent
↑ L L DAC A latched
L L H DAC B transparent
↑ L H DAC B latched
L H L DAC C transparent
↑ H L DAC C latched
L H H DAC D transparent
↑ H H DAC D latched
L = low, H = high, X = irrelevant

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SLAS060F − JANUARY 1995 − REVISED APRIL 2009

PRINCIPLES OF OPERATION

interface logic information (continued)

17
A0
To Latch A

16
A1 To Latch B

To Latch C

15 To Latch D
WR

Figure 6. Input Control Logic

unipolar output operation

The unipolar output operation is the basic mode of operation for each channel of the TLC7226, with the output
voltages having the same positive polarity as Vref. The TLC7226 can be operated with a single power supply
(VSS = AGND) or with positive/negative power supplies. The voltage at Vref must never be negative with respect
to AGND to prevent parasitic transistor turnon. Connections for the unipolar output operation are shown in
Figure 7. Transfer values are shown in Table 3.

Table 3. Unipolar Code

_
2
4 OUTA DAC LATCH CONTENTS
REF DAC A + ANALOG OUTPUT
MSB LSB

_
1111 1111 )V ǒ Ǔ
255
ref 256
1
DAC B +
OUTB
1000 0001 )V ǒ Ǔ129
ref 256

) V ǒ128Ǔ + ) ref
V
1000 0000 ref 256 2
_
20
DAC C +
OUTC
0111 1111 )V ǒ Ǔ 127
ref 256

_ 0000 0001 )V ǒ 1 Ǔ
ref 256
19
OUTD 0000 0000 0V
DAC D +
NOTE A. 1 LSB + V ǒ ref
Ǔ
2– 8 + V ǒ Ǔ
1
ref 256
Figure 7. Unipolar Output Circuit

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SLAS060F − JANUARY 1995 − REVISED APRIL 2009

PRINCIPLES OF OPERATION

linearity, offset, and gain error using single-ended power supplies

When an amplifier is operated from a single power supply, the voltage offset can still be either positive or
negative. With a positive offset, the output voltage changes on the first code change. With a negative offset the
output voltage may not change with the first code depending on the magnitude of the offset voltage.
The output amplifier, with a negative voltage offset, attempts to drive the output to a negative voltage. However,
because the most negative supply rail is ground, the output cannot be driven to a negative voltage.
So when the output offset voltage is negative, the output voltage remains at zero volts until the input code value
produces a sufficient output voltage to overcome the inherent negative offset voltage, resulting in a transfer
function shown in Figure 8.

Output
Voltage

0V
DAC Code
Negative
Offset

Figure 8. Effect of Negative Offset (Single Power Supply)

This negative offset error, not the linearity error, produces the breakpoint. The transfer function would have
followed the dotted line if the output buffer could be driven to a negative voltage.
For a DAC, linearity is measured between zero input code (all inputs 0) and full scale code (all inputs 1) after
offset and full scale are adjusted out or accounted for in some way. However, single power supply operation does
not allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity
in the unipolar mode is measured between full scale code and the lowest code which produces a positive output
voltage.
The code is calculated from the maximum specification for the negative offset.

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SLAS060F − JANUARY 1995 − REVISED APRIL 2009

APPLICATION INFORMATION

bipolar output operation using external amplifier

Each of the DACs of the TLC7226 can also be individually configured to provide bipolar output operation, using
an external amplifier and two resistors per channel. Figure 9 shows a circuit used to implement offset binary
coding (bipolar operation) with DAC A of the TLC7226. In this case:

V
O
+ 1 ) R2
R1
ǒDA V Ǔ * R2
ref R1
ǒVrefǓ (2)

with R1 + R2
V
O
ǒ
+ 2D * 1
A
Ǔ V
ref
where D is a fractional representation of the digital word in latch A.
A
Mismatch between R1 and R2 causes gain and offset errors. Therefore, these resistors must match and track
over temperature. The TLC7226 can be operated with a single power supply or from positive and negative
power supplies.
REF
R1†
R2†
4
TLC7226 15 V
_
_ VO
2
+
DAC A +
−15 V
† R1 = R2 = 10 kΩ ±0.1%

Figure 9. Bipolar Output Circuit

staircase window comparator

In many test systems, it is important to be able to determine whether some parameter lies within defined limits.
The staircase window comparator shown in Figure 10 is a circuit that can be used to measure the VOH and VOL
thresholds of a TTL device under test. Upper and lower limits on both VOH and VOL can be programmed using
the TLC7226. Each adjacent pair of comparators forms a window of programmable size (see Figure 11). When
the test voltage (Vtest) is within a window, then the output for that window is higher. With a reference of 2.56 V
applied to the REF input, the minimum window size is 10 mV.

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SLAS060F − JANUARY 1995 − REVISED APRIL 2009

APPLICATION INFORMATION

staircase window comparator (continued)

Reference Voltage 5V
Vtest 10 kΩ
From DUT +
_
4 Window 1
REF +
_
5V

VOH 10 kΩ
2
OUTA +
_
Window 2
+
_
TLC7226 5V

VOH 10 kΩ
1 +
OUTB
_
Window 3
+
_
5V

10 kΩ
20 VOL
OUTC +
_
Window 4
+
_
5V

10 kΩ
19 VOL
OUTD +
_
AGND Window 5
5 +
_

Figure 10. Logic Level Measurement

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SLAS060F − JANUARY 1995 − REVISED APRIL 2009

APPLICATION INFORMATION

staircase window comparator (continued)

REF
Window 1
OUTA
Window 2
OUTB

Window 3

OUTC
Window 4
OUTD
Window 5
AGND

Figure 11. Adjacent Window Structure

The circuit can easily be adapted as shown in Figure 12 to allow for overlapping of windows. When the three
outputs from this circuit are decoded, five different nonoverlapping programmable window possibilities can
again be defined (see Figure 13).

Reference Voltage 5V
Vtest 10 kΩ
From DUT +
_
4 Window 1
REF +
2 _
OUTA 5V

10 kΩ
1 +
OUTB
_
Window 2
TLC7226 +
20 _
OUTC 5V

10 kΩ
19
OUTD +
_
Window 3
AGND +
5 _

Figure 12. Overlapping Window Circuit

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SLAS060F − JANUARY 1995 − REVISED APRIL 2009

APPLICATION INFORMATION

staircase window comparator (continued)

REF

Window 1
OUTB
Windows 1 and 2
OUTA
Window 2
OUTD
Windows 2 and 3
OUTC Window 3

AGND

Figure 13. Overlapping Window Structure

output buffer amplifier

The unity-gain output amplifier is capable of sourcing 5 mA into a 2-kΩ load and can drive a 3300-pF capacitor.
The output can be shorted to AGND indefinitely or it can be shorted to any voltage between VSS and VDD
consistent with the maximum device power dissipation.

multiplying DAC
The TLC7226 can be used as a multiplying DAC when the reference signal is maintained between 2 V and
VDD − 4 V. When this configuration is used, VDD should be 14.25 V to 15.75 V. A low output-impedance buffer
should be used so that the input signal is not loaded by the resistor ladder. Figure 14 shows the general
schematic.
15 V

R1 1/4 TLC7226

15 V Vref _
_
4 VO
DAC +
+
AC Reference OP07
Input Signal AGND DGND
5 6
R2

Figure 14. AC Signal Input Scheme

14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 PACKAGE OPTION ADDENDUM

www.ti.com 18-Nov-2023

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

5962-87802012A ACTIVE LCCC FK 20 55 RoHS-Exempt SNPB N / A for Pkg Type -55 to 125 5962- Samples
& Green 87802012A
TLC7226
MFKB
5962-87802012C ACTIVE LCCC FK 20 55 RoHS-Exempt Call TI N / A for Pkg Type -55 to 125 5962- Samples
& Green 87802012C
TLC7226CDW ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TLC7226C Samples

TLC7226CDWG4 ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TLC7226C Samples

TLC7226CDWR ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TLC7226C Samples

TLC7226CN ACTIVE PDIP N 20 20 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TLC7226CN Samples

TLC7226IDW ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TLC7226I Samples

TLC7226IDWR ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TLC7226I Samples

TLC7226IN ACTIVE PDIP N 20 20 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 TLC7226IN Samples

TLC7226MFKB ACTIVE LCCC FK 20 55 RoHS-Exempt SNPB N / A for Pkg Type -55 to 125 5962- Samples
& Green 87802012A
TLC7226
MFKB

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 18-Nov-2023

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TLC7226, TLC7226M :

• Catalog : TLC7226
• Military : TLC7226M

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

• Military - QML certified for Military and Defense Applications

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Dec-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLC7226CDWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1
TLC7226IDWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Dec-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLC7226CDWR SOIC DW 20 2000 350.0 350.0 43.0
TLC7226IDWR SOIC DW 20 2000 350.0 350.0 43.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Dec-2023

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
5962-87802012A FK LCCC 20 55 506.98 12.06 2030 NA
5962-87802012C FK LCCC 20 55 506.98 12.06 2030 NA
TLC7226CDW DW SOIC 20 25 506.98 12.7 4826 6.6
TLC7226CDWG4 DW SOIC 20 25 506.98 12.7 4826 6.6
TLC7226CN N PDIP 20 20 506 13.97 11230 4.32
TLC7226IDW DW SOIC 20 25 506.98 12.7 4826 6.6
TLC7226IN N PDIP 20 20 506 13.97 11230 4.32
TLC7226MFKB FK LCCC 20 55 506.98 12.06 2030 NA

Pack Materials-Page 3
 GENERIC PACKAGE VIEW
FK 20 LCCC - 2.03 mm max height
8.89 x 8.89, 1.27 mm pitch LEADLESS CERAMIC CHIP CARRIER

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4229370\/A\

www.ti.com
 PACKAGE OUTLINE
DW0020A SCALE 1.200
SOIC - 2.65 mm max height
SOIC

10.63 SEATING PLANE

TYP
9.97
PIN 1 ID 0.1 C
A
AREA
18X 1.27
20
1

13.0 2X
12.6 11.43
NOTE 3

10
11
0.51
20X
7.6 0.31 2.65 MAX
B 0.25 C A B
7.4
NOTE 4

0.33
TYP
0.10

0.25
SEE DETAIL A GAGE PLANE

1.27 0.3
0 -8 0.40 0.1

DETAIL A
TYPICAL

4220724/A 05/2016

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.

www.ti.com
 EXAMPLE BOARD LAYOUT
DW0020A SOIC - 2.65 mm max height
SOIC

20X (2) SYMM

1
20

20X (0.6)

18X (1.27)

SYMM

(R0.05)
TYP

10 11

(9.3)

LAND PATTERN EXAMPLE

SCALE:6X

SOLDER MASK METAL UNDER SOLDER MASK

METAL OPENING
OPENING SOLDER MASK

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4220724/A 05/2016
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DW0020A SOIC - 2.65 mm max height
SOIC

20X (2)
SYMM
1
20

20X (0.6)

18X (1.27)

SYMM

10 11

(9.3)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:6X

4220724/A 05/2016
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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