Scribd
Upload
65 views7 pages

Program Praktikum 6

The document describes 4 modifications to a counter circuit. The first modification adds a reset to 0 condition when the counter reaches 5. The second modification allows the counter to count down as well as up. The third modification implements an asynchronous counter using JK flip flops with each output connected to the clock of the next stage.

Uploaded by

MUHAMMAD SYAIFULLAH MAIBARA -
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
65 views7 pages

Program Praktikum 6

The document describes 4 modifications to a counter circuit. The first modification adds a reset to 0 condition when the counter reaches 5. The second modification allows the counter to count down as well as up. The third modification implements an asynchronous counter using JK flip flops with each output connected to the clock of the next stage.

Uploaded by

MUHAMMAD SYAIFULLAH MAIBARA -
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 7

Program UNIT 6

1. COUNT

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity count is
port(
clk, rst, up : in std_logic;
Q : out std_logic_vector(3 downto 0)
);
end count;

architecture archi of count is


signal tmp: std_logic_vector(3 downto 0);
begin

process (clk, rst)


begin
if(rst = '1') then
tmp <= "0000";
elsif (clk'event and clk = '1') then
if(up = '1') then
tmp <= tmp + 1;
else
tmp <= tmp;
end if;
end if;
end process;

Q <= tmp;

end archi;
TESTBENCH

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity count_tb is
end count_tb;

architecture TB of count_tb is
component count
port(
clk, rst, up : in std_logic;
Q : out std_logic_vector(3 downto
0)
);
end component;

signal T_clk : std_logic;


signal T_rst : std_logic;
signal T_up : std_logic;
signal T_Q : std_logic_vector(3 downto 0);

begin
U_count: count port map(
clk => T_clk,
rst => T_rst,
up => T_up,
Q => T_Q
);

rst_process: process
begin
T_rst <= '0';
wait for 10 ns;
T_rst <= '1';
wait for 17 ns;
T_rst <= '0';
wait for 333 ns;
end process rst_process;

clk_process: process
begin
T_clk <= '1';
wait for 10 ns;
T_clk <= '0';
wait for 10 ns;
end process clk_process;

up_process: process
begin
T_up <= '0';
wait for 30 ns;
T_up <= '1';
wait for 20 ns;
T_up <= '0';
wait for 30 ns;
T_up <= '1';
wait for 40 ns;
T_up <= '0';
wait for 20 ns;
T_up <= '1';
wait for 20 ns;
T_up <= '0';
wait for 35 ns;
T_up <= '1';
wait for 55 ns;
T_up <= '0';
wait for 10 ns;
T_up <= '1';
wait for 40 ns;
T_up <= '0';
wait for 20 ns;
T_up <= '1';
wait for 40 ns;
end process up_process;
end;
2. MODIFIKASI COUNT

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity count_2 is
port(
clk, rst, up : in std_logic;
Q : out std_logic_vector(3 downto 0)
);
end count_2;

architecture archi of count_2 is


signal tmp: std_logic_vector(3 downto 0);
begin

process (clk,rst)
begin
if (rst='1') then
tmp <= "0000";
elsif (clk'event and clk='1')then
if(tmp="0101")then
tmp <= "0000";
elsif (up = '1')then
tmp <= tmp + 1;
else
tmp <= tmp;
end if;
end if;
end process;

Q <= tmp;

end archi;
3. MODIFIKASI COUNT 2

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity count_3 is
port(
clk, rst, up : in std_logic;
Q : out std_logic_vector(3 downto 0)
);
end count_3;

architecture archi of count_3 is


signal tmp: std_logic_vector(3 downto 0);
begin

process (clk,rst)
begin
if (rst='1') then
tmp <= "0000";
elsif (clk'event and clk='1')then
if(tmp="0101")then
tmp <= "0000";
elsif (up = '1')then
tmp <= tmp + 1;
else
tmp <= tmp - 1;
end if;
end if;
end process;

Q <= tmp;

end archi;
4. Percobaan Asynchronous
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity async is
port( reset : in std_logic;
clock : in std_logic;
count : out std_logic_vector(3 downto 0)
);
end async;
architecture rtl of async is
component jk_ff
port(
reset : in std_logic;
clock : in std_logic;
j : in std_logic;
k : in std_logic;
q : out std_logic
);
end component;

signal temp : std_logic_vector(3 downto 0);


begin
d0 : jk_ff
port map (
reset => reset,
clock => clock,
j => '1',
k => '1',
q => temp(3)
);

d1 : jk_ff
port map (
reset => reset,
clock => temp(3),
j => '1',
k => '1',
q => temp(2)
);

d2 : jk_ff
port map (
reset => reset,
clock => temp(2),
j => '1',
k => '1',
q => temp(1)
);

d3 : jk_ff
port map (
reset => reset,
clock => temp(1),
j => '1',
k => '1',
q => temp(0)
);

count(3) <= temp(0);


count(2) <= temp(1);
count(1) <= temp(2);
count(0) <= temp(3);
end rtl;

You might also like